ADATA 2GB DDR3 PC3-12800 DC Kit
Contents
1. 133 35 52 50 00 128 95 076 77 gt al c 2 CO 12 00 472 44 lE ol sar 140 eL Hole C NES 22 489 98 00X2X von ji 4 00 1850 39 71 00 9 795 28 2 1 9C203 4x2 X 47 0061850 39 R1 00 39 3 75x28 X l 5 2 lt CU gt lt IAE 2 10682 68 4X 5498 S H M 6 NAS NM P Note 1 Tolerance 0 15mm 5 91 mils ix FH sr ei t9 00 X dp 2 50 98 43 S e gt DATA vosuu 0 50019 69D min 1 27 0 10 50 00 3 94 0 20 5 0 800105 m 5 00 196 85 0 05MMCMin 3T5011 97 u J 1 50 0 10 a 59 063 94 VIS en z VIEW C C Detail A Detail OPTIONAL AD64H1A08 DDR3 1600 CL 8 IGB 128Mx8 Pb free Rev 1 2008 10 20 Page 6 of 62. DATA Memory Module Data Sheet A Wonderful Memory AD64H1A08 DDR3 1600 CL8 240 Pin U DIMM 1GB 128M x 64 bits General Description The ADATA s AD64H1A08 is a 128Mx64 bits 1GB 1024MB DDR3 1600 CL8 SDRAM over clocking memory module The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9 9 9 24 at 1 5V The module is composed of eight 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass epoxy printed circuit board The AD64H1A08 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply Normal VDD amp VDDQ 1 5V x 0 075V e 1 5V SSTL 15 compatible I O Timing Reference DDR3 1333 CL9 9 9 24 at 1 5V DDR3 1600 CL8 8 8 24 at 1 75V Burst Length 4 8 Programmable Additive Latency 0 CL 2 or CL 1 clock Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition Average Refresh Period 7 8us at lower then TCASE 85 3 9us at 85 TCASE s 95 8 bit pre f
3. a unique ZQ resistor is connected to A0 1 A2 SAO SA1 SA2 AD64H1A08 DDR3 1600 CL 8 1GB 128Mx8 Pb free Rev 2008 10 20 ground The ZQ resistor is 240 Ohm 1 Page 4 of 6 Kon Absolute Maximum Ratings Voltage on VDD supply relative to Vss 0 4 1 975 Voltage on VDDQ pin relative to Vss VDDQ 0 4 1 975 Voltage on any pin relative to Vss VIN Vout 0 4 1 975 Storage temperature TStg 55 100 Note DDR3 SDRAM component specification Operation Temperature Condition amm we ew e Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 5V 0 075V Tc 0 to 85 C omes veac exem v _ eee vw wem v _ Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 The AC peak noise on VREF may not allow VREF to deviate from VREF DC by more than 1 VDD for reference approx 15 4 For reference approx VDD 2 15 AD64H1A08 DDR3 1600 CL 8 IGB 128Mx8 Pb free Rev 2008 10 20 Page 5 of 6 Package Dimensions i UO U1 U2 U3 U4 05 US U7 C o El o G 1 48 f 49 120 J B L 240 169 f 168 121
4. No Connection on the device AD64H1A08 DDR3 1600 CL 8 IGB 128Mx8 Pb free Rev 2008 10 20 Page 3 of 6 Block Diagram SO DOQSO DQSO DMO DQS1 DOSI DM1 DQS2 DQS 2 DM2 0053 DQS3 DM3 2 A13 RAS CAS WE 054 DQS4 DM4 DQO 001 02 DO4 DQ5 DQ6 DQ7 Vss DOS5 DQS5 DM5 DQS DQ9 DQ10 0011 0012 0013 0014 0015 Vs DOS6 DQS6 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 Vss DQS7 DQS7 DM7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Vss BAO BA2 SDRAMs UO U7 A0 A13 SDRAMs UO U7 Vpp Vppq RAS SDRAMs UO U7 CAS SDRAMs UO U7 SDRAMs UO U7 WE SDRAMs UO U7 Vss DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 Vss 0040 DO41 DQ42 DQ43 0044 0045 0046 0047 Vss 0048 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 DQ60 0061 0062 DQ63 Vss 5938858888 g 5 2 c rw e e FA 5 LA DQ DQ DQ DQ DQ DQ DQ DQ ZQ 938588888 9838588888 C eo e z e de ce 2 Je SPD UO U7 UO U7 UO U7 VRERCA U0 U7 e DATA CKO ODT SDRAMs U0 U7 2 SDRAM 8 CKO CK SDRAMs UO U7 CK1 j CK L3 Serial PD SCL Note WP SDA 1 For each DRAM
5. etch On Die Termination using ODT pin Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm 1 EEPROM VDDSPD 3 3V Typical e PCB Height 30 00mm 1 181 Single sided component Clock Cycle Time tCK DDR3 1333 tCK 1 5ns DDR3 1600 tCK 1 25ns Refresh to Active Refresh Command Time tRFC 110ns Lead free products are ROHS compliant Pin Assignment nf Erom pem romi Pin mont fpr Baek Pin Baek Pin Baek VREFDQ pos 121 461 NC DM8 DM8 201 pox 4 wo js vss 103 pos 103 vss 28 _ a oar a vss mos ta vss 162 NocBe 204 nc 5 vss noose pasa 125 165 205 vss 6 maso 46 se vss 126 vss 2 Dos 7 poo ar vss j 107 vss wo 207 po 8 vss 458 No pos 128 pas 168 meser 208 ves 9 no s wo a vss 19 par 169 ckernc 20 pas so ceo s 130 vss 10 210 Do vss s vo je 181 im ms an vss s sa o f vss pam 172 a oms Dos se No mass 193 vss 173 zo wo m vss 9 vo pos 134 ow a A2 aa ves _ mos ss an 9 vss 15 wc 5 ao 215 _ Das se a Do 136 vss 16 voo 216 po
6. g 7 vs s vo o oos 187 far as am vss 8s ss as vss 138 178 as ze poo 19 so A poe 19 vss 19 29 boo vss 6 10 Dom 10 220 vss z poe ot a m vss vay pon er zat om 2 bou c 102 mase 2 vss 182 voo 22 wo 25 vss cnc 5 pase 143 183 voo 23 vss 2 masz amp ikinc 14 vss M4 1 24 Dow 25 65 vno pos vss 185 225 Dos vss 66 vob 106 bos 146 pom 186 voo 226 vss _ 67 vrerca 107 vss 147 ser wc EvENT 227 Doo 25 e 108 pos 148 vss 188 ao 228 Do vss e 109 pasz 49 pos 189 voo ze vss 30 Dam atop wo vss 150 190 BA 29 DW 5 pos fpr bw m masr 151 vss 11 21 wo s vss 72 pos ts om 192 mas 232 vss 33 moss 7s vss 153 No 193 so 233 oo s Dass za icas 14 Dos 54 vss 194 voo 234 Dae s vss 75 15 pos 155 pos 195 235 vss 36 ze sinc we vss 156 pas 196 236 voDSPD 5r omnc nz sw 157 vss 197 voo 2v SM _ _ vs
7. s 78 sco 158 198 No 238 soa 39 r9 mo sw 159 Noces 199 vss 239 vss 4 woos vss 12 vss 20 poe zo vr AD64H1A08 DDR3 1600 CL 8 IGB 128Mx8 Pb free Rev 2008 10 20 Page 2 of 6 Kon Pin Description NAME FUNCTION System Clock CKO Active on the positive and negative edge to sample all inputs CKO Masks system clock to freeze operation from the next clock cycle CKE should be enabled at CKEO Clock Enable least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and S0 Chip Select L U DOM Row Column address are multiplexed on the same pins A0 A13 Address Row Address A0 A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time BAO BA2 Banks Select Selects bank for read write during column address latch time Data Data and check bit inputs outputs are multiplexed on the same pins Data Strobe When high termination resistance is enabled for all DQ DQ and DM pins assuming the DQ0 DQ63 DQSO DQS7 Bi directional Data Strobe DQS0 DQS7 DMO DM7 RAS ICAS VDD VSS VREFDQ VREFCA V ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left
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