ADATA 3GB DDR3 PC3-10666 TC Kit
Contents
1. so vss 120 vr io vss 20 poe 240 vr SC63G1A08 DDR3 1333 CL 7 1GB 128Mx8 Pb free Rev 1 2008 10 15 Page 2 of 6 Kon Pin Description NAME FUNCTION System Clock CKO Active on the positive and negative edge to sample all inputs CKO Masks system clock to freeze operation from the next clock cycle CKE should be enabled at CKEO Clock Enable least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and S0 Chip Select L U DOM Row Column address are multiplexed on the same pins A0 A13 Address Row Address A0 A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time BAO BA2 Banks Select Selects bank for read write during column address latch time Data Data and check bit inputs outputs are multiplexed on the same pins Data Strobe When high termination resistance is enabled for all DQ DQ and DM pins assuming the DQ0 DQ63 DQSO DQS7 Bi directional Data Strobe DQS0 DQS7 DMO DM7 RAS ICAS VDD VSS VREFDQ VREFCA V ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device SC63G1A08 DDR3 1333 CL 7 1GB 128Mx8 Pb free Rev 1 2008 10 15 Page 3 of 6 Block Diagram SO BAO BA2. 1 Rev 1 2008 10 15 Page 4 of 6 RATA Absolute Maximum Ratings Voltage on VDD supply relative to Vss 0 4 1 975 Voltage on VDDQ pin relative to Vss VDDQ 0 4 1 975 Voltage on any pin relative to Vss VIN Vout 0 4 1 975 Storage temperature TStg 55 100 Note DDR3 SDRAM component specification Operation Temperature Condition amm we ont e Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 5V 0 075V Tc 0 to 85 C omes OO exem v oa eee 7 7 vw wem owwme v Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 The AC peak noise on VREF may not allow VREF to deviate from VREF DC by more than 1 VDD for reference approx 15mV 4 For reference approx VDD 2 15mV SC63G1A08 DDR3 1333 CL 7 1GB 128Mx8 Pb free Rev 1 2008 10 15 Page 5 of 6 Package Dimensions UO U1 U2 U3 U4 U5 US U7 C O O O ol El O O O o 1 48 f 49 120 J la B L 240 169 f 168 121 133 35 52 50 00 128 95 5076 77 M Z 2 o 00 l 12 00 472 44 lE r Pt N k 0 Z L Hole C 4 o 2 489 98 00X2 0 E E AN E AE ENUIAE e n u oun
3. On Die Termination using ODT pin Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm x 1 EEPROM VDDSPD 3 3V Typical PCB Height 30 00mm 1 181 Single sided component Clock Cycle Time tCK DDR3 1333 tCK 1 5ns Refresh to Active Refresh Command Time tRFC 110ns Lead free products are RoHS compliant Pin Assignment nf Erom pem romi Pin mont fpr Baek Pin Baek Pin Baek VREFDQ pos 121 461 NC DM8 DM8 201 pox el me tate ee tee tet MCI N 8 cao 4 wo as vss v3 pos 18 vss 203 om 4 oar a vss ee mos ta vss 14 NocBe 204 nc 5 vss 4 noose a5 pasa 125 pmo 165 noosr 205 vss 6 maso 4 Noces se vss 126 No 166 vss 206 Dos 7 poo ar vss j bow vr vss 17 wo 207 pas 8 vss as No a pos 128 pas meser 208 ves 9 no s wo a vss 19 par 169 ckernc 20 pas to Das so ceo s Dow 130 vss 10 voo 20 Do vss s vo je van poe im ms am vss bos s sa e vss pam 12 maa a oms 1 Dos se No o mass 13 vss a voo zo wo a vss 9 vo pos 1s om a A2 aa ves 15 mos ss an 9 vss fis wc 5 ao 215 poe s Das se a 9 Do vss 176 voo 2t6 pog 7 vs s vo o oos sr bo far as am vss 8s c
4. P8 4 1 HH E wa 120 47 00 1850 39 71 0062795 28 2 1 9C203 4x2 X 4 7 00 1850 39 R1 00 39 3 75x28 X l x gt lt CU gt lt S xo SS SS 2 1082 684X mE bh S H M 6 OIM Min P Note Y da 1 Tolerance 0 15mm 5 91mils E TA FH ME eres o Od i V v e 50 98 43 D y e 100000 gt DATA vosuu 0 50019 69D min 1 27 0 10 350 00 3 94 0 COMMCMa x 0 80 0 05 m 5 00 196 85 0 05MM lt Min gt 3T50 1 97 u T 1 500 10 i A 59 06 3 94 05MM n Z VIEW C C Detail A ze Detail B OPTIONAL SC63G1A08_DDR3 1333 CL 7 1GB 128Mx8 Pb free Rev 1 2008 10 15 Page 6 of 6
5. 2 AO A13 RAS CAS CKEO WE ODTO CKO SCL DQSO DQSO DMO DM CS DOS DOS DQO DQ DQ1 DQ2 DQ3 DO4 DQ5 DQ6 DQ7 DQS1 Vss DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 Vss DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS34 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Vss BAO BA2 SDRAMs UO U7 e A0 A13 SDRAMs U0 U7 RAS SDRAMs U0 U7 CAS SDRAMs U0 U7 CKE SDRAMs U0 U7 gt WE SDRAMsUO U7 ODT SDRAMs U0 U7 CK SDRAMs U0 U7 Serial PD WP SDA AO A1 A2 SAO SA1 SA2 SC63G1A08 DDR3 1333 CL 7 1GB 128Mx8 Pb free DOS4 DQS4 DM4 CS DOS DOS DQ32 DQ DQ33 DQ DQ34 DQ DQ35 DQ DQ36 DQ U4 DQ37 DQ DQ38 DQ DQ39 DQ ZQ DQS5 Vss DQS5 DM5 DM CSF DOS DOS DO40 DO ues DO41 DQ DO42 DQ DO43 DQ DO44 pq Us DO45 DQ DO46 DQ DO47 DQ V ZQ DQS6 E DQS6 DM6 DM CS DOS DOS DO48 DQ DO49 DQ DQ50 DQ DQ51 DQ DQ52 DQ U6 DQ53 DQ DQ54 DQ DQ55 DQ v ZQ DQS7 a DQS7 DM7 a poi M CSF Das DOS DQ57 DQ DQ58 DQ DQ59 DQ DQ60 DQ U7 DQ61 DQ DQ62 DQ DQ63 DQ ZQ Vss VDDSPD SPD Vpp Vppa UO U7 VREFDQ UO U7 Vee UO U7 VRERCA M 0 U7 CKO cko DDR3 SDRAM x8 Ki d CK1 Note e DATA 1 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 240 Ohm
6. DAT Memory Module Data Sheet A Wonderful Memory SC63G1A08 DDR3 1333 CL7 240 Pin O C U DIMM 1GB 128M x 64 bits General Description The ADATA s SC63G1A08 is a 128Mx64 bits 1GB 1024MB DDR3 1333 CL7 SDRAM over clocking memory module The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9 9 9 24 at 1 5V The module is composed of eight 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass epoxy printed circuit board The SC63G1A08 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply Normal VDD amp VDDQ 1 5V 0 075V e 1 5V SSTL_15 compatible I O Timing Reference DDR3 1333 CL9 9 9 24 at 1 5V DDR3 1333 CL7 7 7 20 at 1 75V Burst Length 4 8 Programmable Additive Latency 0 CL 2 or CL 1 clock Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition Average Refresh Period 7 8us at lower then TCASE 85 C 3 9us at 85 C TCASE s 95 C 8 bit pre fetch
7. a ss as es vss 138 pas ve as ze poo 19 Dom so A poe 19 vss 1 voo 29 boo vss 6 vwm 10 po 10 1 Dom 10 as 220 vss z poe ot a m vss vay pon ter ar zat om 2 bou c vom 12 mase 2 vss 182 voo 22 wo 25 vss e cnc 5 pase 143 pm tes voo 23 vss 2 masz amp ikinc 14 vss M4 nc 1 cko 24 Dow 25 Dos 65 vno 105 pos 145 vss 185 cko 225 Dos vss 66 vob 106 bos 146 pom 186 voo 226 vss 27 pos e vrerca tor vss wr Dazs ser Novevent 227 Doo 25 cars e noo 108 pos 148 vss__ 198 ao 228 Do vss e vom 109 pasz 149 pos 189 voo ze vss 30 Dam 70 atop io vss 150 paz 190 BA 29 DW 5 pos fpr bw m masr isi vss ter voo 21 wo s vss 72 vw n pos ts om 192 mas 232 vss 33 moss 7s me me vss 153 No 193 so 233 oo s Dass za icas 4 Dos 54 vss 194 voo 9 Dae s vss 75 v 15 pos 155 pos 195 opo 23 vss 36 Baz ze sinc we vss 156 pas tee A 236 voDSPD 5r pox 77 omnc nz sw 57 vss 197 voo 2v sa ss vss 78 vw nsf sco 158 neces 198 No 295 soa 39 Noceo0 r9 No mo sw 159 Nocss 199 vss 239 vss 4 woos
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