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Intel Pentium III

1. esses 60 5 1 1 FC PGA2 Mechanical Specifications 63 5 2 Processor Markings tone eR el IER E 65 5 2 1 Processor Markings for 65 5 3 Recommended Mechanical Keep Out Zones 66 5 4 Processor Signal neue 67 Boxed Processor Specifications 80 6 1 Mechanical Specifications for the Boxed Intel Pentium III Processor 80 6 1 1 Boxed Processor Thermal Cooling Solution Dimensions 80 6 1 2 Boxed Processor Heatsink 82 6 1 3 Boxed Processor Thermal Cooling Solution Clip 82 6 2 Thermal 82 6 2 1 Boxed Processor Cooling Requirements 82 6 3 Electrical Requirements for the Boxed Intel Pentium Processor 83 6 3 1 Fan Heatsink Power 8 83 Processor Signal Description 2 2 2 2 85 7 1 Alphabetical Signals Reference 85 7 2 Signal Summaries o rete o 92 Datasheet intel Figures Datasheet Q R GOM Pentium Ill Processor for the PGA
2. sette 84 5 Pentium Ill Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel Tables 22 23 24 25 26 27 28 29 30 Processor vasa ue o chen brun pen 10 Voltage Identification 21 System Bus Signal Groups 1 23 System Bus Signal Groups 23 Frequency Select Truth Table for BSEL 1 01 26 Absolute Maximum 26 Voltage and Current Specifications 28 PL Slew Rate Data 2 33 AGTL AGTL Signal Groups DC Specifications 34 Non AGTL Signal Group DC Specifications 34 Non AGTL Signal Group DC Specifications 35 Processor AGTL Bus Specifications sse 36 Processor AGTL Bus Specifications 36 System Bus AC Specifications SET Clock 37 System Bus Timing Specifications Differential Clock 38 System Bus AC Specifications AGTL or Signal Group 39 System Bus AC Specifications CMOS Signal Group 40 System Bus AC
3. Power Other U35 T Vm Power Other 7 GND Power Other U37 vit 4 Power Other 22 GND Power Other V2 GND Power Other Z4 A29 AGTL I O V4 BERR AGTL I O Z6 A18 AGTL I O V6 Power Other 232 Power Other V32 Power Other Z34 GND Power Other V34 GND Power Other 736 5 Power Other NOTES See next page for notes Datasheet 78 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz NOTES 1 These pins are required for backwards compatibility with other Intel processors They are not used by the Pentium processor Refer to the appropriate platform design guide and Section 7 1 for implementation details RESET signal must be connected to pins and for backwards compatibility Refer to the appropriate platform design guide and Section 7 1 for implementation details If backwards compatibility is not required then RESET2 X4 should be connected to GND must be supplied by the same voltage source supplying the VTT pins These VTT pins must be left unconnected N C for backwards compatibility with Celeron processors CPUID 066xh For designs which do not support the Celeron processors CPUID 066xh and for compatibility with future processors these VTT pins should be connected to the VTT plane Refer to the appropriate platform design guide and Section 7 1 for implementation details For du
4. Datasheet Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 7 Voltage and Current Specifications Sheet 4 of 5 Processor Symbol Parameter Min Typ Max Unit Notes Core cpuip Freq 500E MHz 0x683 10 0 3 8 9 soog 0x686 12 0 3 8 9 MHz 68 12 6 3 8 9 600EB 0x686 12 0 3 8 9 650 Mhz 0x686 13 0 3 8 9 6678 0x686 13 3 3 8 9 700 0x686 14 0 3 8 9 MHz 68 14 8 3 8 9 733B 0x686 14 6 3 8 9 MHz 0 68 15 4 3 8 9 750 0 686 15 0 3 8 9 MHz 68 15 7 3 8 9 800 MHz 0x686 16 0 3 8 9 for processor core A 0x686 16 0 3 8 9 MHz 68 16 6 3 8 9 850 0x686 16 2 3 8 9 MHz 68 17 3 3 8 9 866 0x686 16 3 3 8 9 MHz 68 17 6 3 8 9 0 686 17 0 3 8 9 MHz 68 18 4 3 8 9 933 0 686 17 7 3 8 9 MHz 0 68 18 8 3 8 9 20 1B 0x686 19 4 3 8 9 GHz 68 20 2 3 8 9 20 1GHz 0 68 20 2 3 8 9 1 10 GHz 0 68 22 6 3 8 9 1 13 22 6 3 8 9 20 Datasheet 31 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 32 Table 7 Voltage and Current Specifications Sheet 5 of 5 Proce
5. Power Other D28 Power Other B24 GND Power Other D30 GND Power Other B26 Power Other D32 Power Other B28 GND Power Other D34 GND Power Other B30 Power Other D36 Power Other B32 GND Power Other E1 AGTL I O B34 Power Other D25 AGTL I O B36 BINIT AGTL I O E5 Power Other C1 D33 AGTL I O E7 GND Power Other C3 Power Other E9 Power Other C5 D31 AGTL I O E11 GND Power Other C7 D34 AGTL I O E13 VCCcoRE Power Other C9 0364 AGTL I O E15 GND Power Other C11 D45 AGTL I O E17 Power Other C13 D49it AGTL E19 GND Power Other C15 D40 AGTL E21 Reserved Reserved for future use C17 D59 AGTL E23 vrr 4 Power Other C19 D55 AGTL I O E25 D62 AGTL I O C21 D54 AGTL I O E27 SLEWCTRL Power Other C23 D58 AGTL I O E29 DEP6 AGTL I O 76 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 40 Signal Listing in Order by Pin Table 40 Signal Listing in Order by Pin Number Continued Number Continued Pin Name Signal Group Signal Group E31 DEP4 AGTL I O K2 VCCconE Power Other E33 VngrO Power Other K4 Vngr2 Power Other E35 BPM1 AGTL I O K6 D24 AGTL I O E37 BP3
6. The ADS Address Strobe signal is asserted to indicate the validity of the transaction address on the A 35 3 pins All bus agents observe the ADS ADS VO activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all processor system bus agents The AERR Address Parity Error signal is observed and driven by all processor system bus agents and if used must connect the appropriate pins on all processor system bus agents AERR observation is optionally enabled during power on AERR VO configuration if enabled a valid assertion of AERR aborts the current transaction If AERR observation is disabled during power on configuration a central agent may handle an assertion of AERR as appropriate to the error handling architecture of the system The AP 1 0 Address Parity signals are driven by the request initiator along with ADS A 35 3 REQ 4 0 Z and RP covers A 35 24 and covers 23 3 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all processor system bus agents 1 0 VO The BCLK Bus Clock signal determines the bus frequency All proces
7. On motherboards that support operation at either 100 MHz or 133 MHz the BSEL1 signal must be pulled up to a logic high by a resistor located on the motherboard and provided as a frequency selection signal to the clock driver synthesizer This signal can also be incorporated into RESET logic on the motherboard if only 133 MHz operation is supported thus forcing the RESET signal to remain active as long as the BSEL1 signal is low The BSELO signal will float from the processor and should be pulled up to a logic high by a resistor located on the motherboard The BSELO signal can be incorporated into RESET logic on the motherboard if 66 MHz operation is unsupported as demonstrated in Figure 7 Refer to the appropriate clock synthesizer design guidelines and platform design guide for more details on the bus frequency select signals In a 2 way MP system design these BSEL 1 0 signals must connect the pins of both processors BSEL 1 0 Example for a 100 133 MHz or 100 MHz Only System Design 3 3V 3 3V Processor BSELO BSEL1 10 KQ 1 Clock Driver 10 10 Note 2 Note 2 Chipset NOTES 1 Some clock drivers may require a series resistor on their BSEL1 input 2 Some chipsets may connect to the BSEL 1 0 signals and require a series resistor See the appropriate platform design guide for implementation details 25 Pentium Processor fo
8. 0 686 1 70 V 3 4 0x68A 1 75 3 4 900 0x686 1 70 3 4 MHz 0 68 1 75 34 0x683 1 65 3 4 933 MHz 0x686 1 70 3 4 0x68A 1 75 3 4 20 1GHz 0x68A 1 75 3 4 0x686 1 70 3 4 1B GHz 0x686 1 76 3 4 18 19 0x68A 1 75 3 4 20 1 10 GHz 0x68A 1 75 3 4 1 13 GHz 0x68A 1 75 3 4 Datasheet 29 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 7 Voltage and Current Specifications Sheet 3 of 5 30 Processor Symbol Parameter Min Typ Max Unit Notes Core cpuip Freq Static AGTL bus 1455 150 1545 V 1 533955 6 Vit termination voltage Static AGTL bus 5 16 17 termination voltage 1 213 1 25 1 288 V 1 25 396 579 Transient AGTL bus 1 365 1 50 1 635 V 1 5 9 5 termination voltage Transient AGTL bus 547 termination voltage 1 138 1 25 1 363 V 1 25 9 gt Static AGTL bus A 5 termination voltage 1 455 1 50 1 545 V 1 5 3 AGTL input reference 8 2 3 VREF voltage 2 VTT 2 V 2 Jo 7 CLKREF input VCLKREF reference voltage 1 169 1 25 1 331 V 26 59 15 Baseboard Processor core voltage static tolerance level at 0 080 0 040 6 Tolerance the PGAS370 socket 0 001 0 100 18 19 Static pins Baseboard Processor core voltage 0 130 0 080 6 transient tolerance level zi Tolerance at the PGA370 socket 9 110 9 099 V n Transient pins 0 025 0 130 18 19
9. 1 25 V used to provide AGTL AGTL termination voltage to the processor and the Vgpgpinputs are used as AGTL AGTL reference voltage for the processor Note that not all VTT inputs must be connected to the VTT supply Refer to Section 5 4 for more details On the motherboard all VCCcogg pins must be connected to a voltage island an island is a portion of a power plane that has been divided or an entire plane In addition the motherboard must implement the VTT pins as a voltage island or large trace Similarly all GND pins must be connected to a system ground plane Three additional power related pins exist on a processors utilizing the PGA370 socket They are 5 VCC55 and VCCemos The VCCcyos pin provides the CMOS voltage for the pull up resistors required on the system platform A 2 5 V source must be provided to the and 1 5 V source must be provided to the VCC 5 pin The source for VCC 5 must be the same as the one supplying VTT The processor routes the compatible CMOS voltage source 1 5 V or 2 5 V through the package and out to the output pin Processors based 0 25 micron technology e g the Celeron processor utilize 2 5 V CMOS buffers Processors based on 0 18 micron technology e g the Pentium Ill processor for the PGA370 socket utilize 1 5 V CMOS buffers The signal can be used by hardware on the motherboard to detect which CMOS voltage the processor
10. 6 2 1 82 1 6 gt 1 13 18 1 0 12 24 88 Boxed Processor Thermal Cooling Solution Clip The boxed processor thermal solution requires installation by a system integrator to secure the thermal cooling solution to the processor after it is installed in the 370 pin socket ZIF socket Motherboards designed for use by system integrators should take care to consider the implications of clip installation and potential scraping of the motherboard PCB underneath the 370 pin socket attach tabs Motherboard components should not be placed too close to the 370 pin socket attach tabs in a way that interferes with the installation of the boxed processor thermal cooling solution see Section 5 3 for specification Thermal Specifications This section describes the cooling requirements of the thermal cooling solution utilized by the boxed processor Boxed Processor Cooling Requirements The boxed processor is directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Section 4 0 of this document The boxed processor fan heatsink is able to keep the processor core within the specifications see Table 33 and Table 34 in chassis that provide good thermal management Datasheet intel Pentium Proces
11. Table 39 Signal Listing in Order by Signal Name Continued Datasheet E Pin Name Signal Group Pin Name Signal Group AKSO Reserved Reserved for future use F22 VCCcoRE Power Other AM2 Reserved Reserved for future use F26 Power Other F10 Reserved Reserved for future use F30 Power Other X34 Reserved Reserved for future use F34 VCCcoRE Power Other E21 Reserved Reserved for future use F4 VCCcORE Power Other 2 BR1 AGTL Input H32 Power Other 4 RESET 2 AGTL Input 36 Power Other X4 2 2 AGTL I O J5 Power Other AN23 AGTL I O K2 Power Other AH26 RSO Input K32 VCCconE Power Other AH22 RS1 AGTL Input K34 Power Other AK28 RS2 AGTL Input M32 VcCcoRE Power Other AC37 RSP AGTL Input N5 VCCconE Power Other S35 RTTCTRL Power Other P2 VCCcoRE Power Other E27 SLEWCTRL Power Other P34 Power Other AH30 SLP CMOS Input R32 VCCconE Power Other AJ35 CMOS Input R36 Power Other AG35 STPCLK CMOS Input S5 Power Other AL33 TCK TAP Input T2 VCCcoRE Power Other 35 TDI TAP Input T34 VCCcoRE Power Other AN37 TDO TAP Output V32 Power Other AL29 THERMDN Power Other V36 VCCconE Power Other AL31
12. INTel Processor Symbol Parameter m Min Typ Max Unit Notes Freq CPUID 0x681 1 60 3 4 500 0x683 1 60 34 0x686 n a 34 0x681 1 65 34 ES 1 65 34 0x686 n a 34 0x681 1 60 3 4 0x683 1 65 3 4 0x686 1 70 3 4 0x681 1 65 3 4 600 0x683 1 65 3 4 MHz 0x686 1 70 3 4 0x68A 1 75 3 4 0x681 1 65 3 4 600 Ox683 1 65 34 0x686 1 70 3 4 VCCconE Vcc for Processor Core 650 V zi 0x683 1 65 3 4 0x686 1 70 3 4 0x681 1 65 34 667 Ox683 1 65 34 0x686 1 70 3 4 0x681 1 65 3 4 700 0x683 1 65 3 4 MHz 0x686 1 70 3 4 0x68A 1 75 3 4 0x681 1 65 3 4 733 0x683 1 65 3 4 MHz 0 686 1 70 3 4 0x68A 1 75 3 4 0x681 1 65 3 4 750 0x683 1 65 3 4 MHz 0x686 1 70 3 4 0x68A 1 75 3 4 Datasheet Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 7 Voltage and Current Specifications Sheet 2 of 5 Processor Symbol Parameter Min Typ Max Unit Notes Core cpuip Freq 0x681 1 65 3 4 800 0x683 1 65 3 4 0x686 1 70 3 4 0x681 1 65 3 4 MHz 0 686 1 70 34 0x68A 1 75 3 4 0x681 1 65 3 4 MHz 0 686 1 70 34 0x68A 1 75 3 4 0x681 1 65 3 4 Vcc for Processor Core
13. Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 5 3 66 Figure 28 Top Side Processor Markings for FC PGA2 In GRPILNI GRPILN2 GRP2LN1 GRP2LN2 GRP1LN1 INTEL m c 01 Country of Origin GRP1LN2 Core freq Cache Bus Freq Voltage GRP2LN1 FPO S N GRP2LN2 PENTIUM III S Spec Figure 29 Volumetric Keep Out for FC PGA and FC PGA2 T 2 Recommended Mechanical Keep Out Zones i 55 Pa 2 1 350 4 72 1 350 1 494 a SECTION 2 140 i 1 570 a 0 2 160 1 993 NE i j THERMAL AIR SPACE REG D FOR ACTIVE SOLUTION NON OBSTRUCT IVE INTRUSIONS ARE PERMISSIBLE 3 504 r 1 679 X SECTION A ALL DIMENSIONS ARE MINIMUM UNLESS OTHERWISE SPECIFIED A 2 5284 DESIG 005 REFERENCE SPECIFICATION NOTES 1 This drawing applies to FC PGA2 package The only differences from the FC PGA package Keep Out drawing are as follows height 2 160 was changed from 2 100 and height 1 118 was changed from 1 058 2 Refer to the Pentium Thermal Mechanical Solution Functional Guidelines see section 1 2 for reference order number for
14. High Time T4 T24 T33 Low Time T1 T22 T81 BCLK TCK PICCLK Period BCLK is referenced to 0 30V Differential Mode 0 50V Single Ended Mode TCK is referenced to Vref 200 mV PICCLK is referenced to 0 4V V2 BCLKis refernced to 0 9V Differental Mode 2 0V Single Ended Mode TCK is referenced to Vref 200 mV PICCLK is refernced to 1 6V V3 BCLK and BLCK crossing point of the rising edge and the falling edge of BCLK Differential Mode BCLK i refereced to 1 25V Single Ended Mode PICCLK is reference to 1 0V TCK is referenced to Vcmosref lt cc Figure 11 System Bus Valid Delay Timings Signal Tx T7 T11 T29a T29b Valid Delay NOTE Single Ended clock uses BCLK only Tpw 714 T15 Pulse Width Differential clock uses BCLK and BCLK V Vref for AGTL signal group Vcmosref for CMOS APIC and TAP signal groups 42 Datasheet intel Figure 12 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz System Bus Setup and Hold Timings Voross Crossing point BCLK Ts T8 12 T27 Setup Time NOTE Single Ended clock uses BCLK only Th T9 T13 T28 Hold Time Differential clock uses BCLK and BCLK Vref for signal group 0 75V for APIC and TAP signal groups Figure 13 System Bus Reset and Configuration Timings BCLK BCLK RESET Configuration 14 5 B
15. Low BCLK AGTL Input Always RS 2 0 Low BCLK AGTL Input Always RSP Low BCLK AGTL Input Always RTTCTRL N A Asynch Power Other SLEWCTRL N A Asynch Power Other SLP Low Asynch CMOS Input During Stop Grant state SMI Low Asynch CMOS Input STPCLK Low Asynch CMOS Input TRDY Low BCLK AGTL Input NOTE 1 Synchronous assertion with active TDRY ensures synchronization Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 94 Table 45 Input Output Signals Single Driver Active Level Clock Signal Group Qualified 35 3 Low BCLK AGTL I O ADS ADS 1 ADS Low BCLK AGTL I O Always 1 0 Low BCLK AGTL I O ADS ADS 1 BP 3 2 Low BCLK AGTL I O Always BPM 1 0 Low BCLK AGTL I O Always BRO Low BCLK AGTL I O Always BSEL 1 0 High Asynch Power Other Always D 63 0 Low BCLK AGTL I O DRDY DBSY Low BCLK AGTL I O Always DEP 7 0 Low BCLK AGTL I O DRDY DRDY Low BCLK AGTL I O Always LOCK Low BCLK AGTL I O Always REQ 4 0 Low BCLK AGTL I O ADS ADS 1 RP Low BCLK AGTL I O ADS ADS 1 Table 46 Input Output Signals Multiple Driver Name Active Level Clock Signal Group Qualified AERR Low BCLK AGTL I O ADS 3 BERR Low BCLK AGTL I O Always BINIT Low BCLK AGTL I O Always BNR Low BCLK AGTL I O Always HIT Low BCLK AGTL I O Always HITM Low BCLK AGTL I O Always PICD 1 0 Hig
16. The processor s execution engine S E C C The processor package technology called Single Edge Contact Cartridge Used with Intel Pentium II processors S E C C 2 The follow on to S E C C processor package technology This differs from its predecessor in that it has no extended thermal plate thus reducing thermal resistance Used with Pentium III processors and latest versions of the Pentium II processor Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 1 1 2 10 Table 1 intel e SC242 The 242 contact slot connector previously referred to as slot 1 connector that the S E C C and S E C C 2 plug into just as the Intel The cache and L2 cache are an industry designated names Processor Naming Convention Pentium Pro processor uses socket 8 A letter s is added to certain processors e g 600EB MHz when the core frequency alone may not uniquely identify the processor Below is a summary of what each letter means as well as a table listing all the available Pentium lll processors for the PGA370 socket 133 MHZ System Bus Frequency Processor with Advanced Transfer Cache CPUID 068xh and greater Processor Identification Processor Gore Frequency ux R CPUID 500E 500 100 256 ATC 068xh 533EB 533 133 256 ATC 068xh 550E 550 100 256 ATC 068xh 600E 600 100
17. Thermal Design Additional Processor Br Frequency Power 23 case Nokes NHertey MHz CPUID 068Ah MHz W C 866 866 133 29 5 70 5 933 933 133 31 5 72 5 1B GHz 1000 133 33 9 69 5 1 13 GHz 1133 133 37 5 72 NOTES 1 These values are specified at nominal for the processor pins 2 Thermal Design Power TDP represents the maximum amount of power the thermal solution is required to dissipate The thermal solution should be designed to dissipate the TDP power without exceeding the maximum Tcase specification 3 TDP does not represent the power delivery and voltage regulation requirements for the processor Refer to Table 7 for voltage regulation and electrical specifications 4 Tcaseottset I5 the worst case difference between the maximum case temperature and the thermal diode temperature on the processor s core For more information please refer to the document Inte Pentium Processor in the FC PGA2 Package Thermal Design Guide 5 This processor exists in both FC PGA and FC PGA2 packages Processor Die Area Figure 21 is a block diagram of the Pentium III processor die layout and Table 32 contains Pentium processor die layout measurements The layout differentiates the processor core from the cache die area In effect the thermal design power identified in Table 30 is dissipated entirely from the processor core area Thermal solution designs should compensate for this smaller heat flux area and not assu
18. pins can be used to support automatic selection of power supply voltages These pins are not signals but are either an open circuit or a short circuit to 55 on the processor The combination of opens and shorts defines the VID 3 0 voltage required by the processor The VID pins are needed to cleanly support voltage specification variations on processors See Table 2 for definitions of these pins The power supply must supply the voltage that is requested by these pins or disable itself The pin indicate the type of processor core present This pin will float for 2 0 based processor will be shorted to Vss for the Pentium III processor The VCC 5 V input pin provides the termination voltage for CMOS signals interfacing to the processor The Pentium processor reroutes the 1 5 V input to 1 5 the output via the package The supply for Vcc 5 V must be the same used to supply VTT The 5 V input pin provides the termination voltage for CMOS signals 25 interfacing to processors which require 2 5 V termination on the CMOS signals This signal is not used by the Pentium processor Vcc The VccCMOS pin provides the CMOS voltage for use by the platform and is used CMOS for terminating CMOS signals that interface to the processor The Vggr input pins supply the AGTL reference voltage which is typically 2 3 of VREF VTT Vper is used by the AGTL
19. the AGTL AGTL system bus Termination usually a resistor at each end of the signal trace is used to pull the bus up to the high voltage level and to control reflections on the transmission line The processor contains on die termination resistors that provide termination for one end of the bus except for RESET These specifications assume another resistor at the end of each signal trace to ensure adequate signal quality for the AGTL AGTL signals and provide backwards compatibility for the Celeron processor see Table 12 for the bus termination voltage specifications for AGTL Refer to the Intel Pentium II Processor Developer 5 Manual for the AGTL bus specification Solutions exist for single ended termination as well though this implementation changes system design and eliminate backwards compatibility for Celeron processors in the PPGA package Single ended termination designs must still provide an AGTL termination resistor on the motherboard for the RESET signal Figure 2 is a schematic representation of the AGTL AGTL bus topology for the Pentium III processors in PGA370 socket Figure 3 is a schematic representation of the AGTL AGTL bus topology in a dual processor configuration with Pentium processors in the PGA370 socket Both AGTL and AGTL bus depend on incident wave switching Therefore timing calculations for or AGIL signals are based flight time as opposed to capacitive deratings Analog
20. 11 For the Coppermine T differential clock this signal has been redefined to 2 0 V tolerant 12 1 25 V signal for Differential clock application and 2 5 V for Single ended clock application 13 This signal is 3 3 V Asynchronous vs Synchronous for System Bus Signals AGTL signals are synchronous to BCLK All of the CMOS Clock APIC and TAP signals can be applied asynchronously to BCLK All APIC signals are synchronous to PICCLK Datasheet intel 2 8 2 Figure 7 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz System Bus Frequency Select Signals BSEL 1 0 These signals are used to select the system bus frequency for the processor The BSEL signals are also used by the chipset and system bus clock generator Table 5 defines the possible combinations of the signals and the frequency associated with each combination The frequency selection is determined by the processor s and driven out to the chipset and clock generator All system bus agents must operate at the same frequency determined by the processor The Pentium lll processor for the PGA370 socket operates at 100 MHz or 133 MHz system bus frequency 66 MHz system bus operation is not supported Individual processors will only operate at their specified front side bus FSB frequency either 100 MHz or 133 MHZ not both Over or under clocking the system bus frequency outside the specified rating marked on the package is not recommended
21. 2 18 V 2 Input voltage can never go below VTT 2 18 V 3 Parameter applies to CMOS except BCLK PICCLK PWRGOOD and APIC bus signal groups only 4 Parameter applies to CMOS signals BCLK PICCLK and PWRGOOD only Datasheet intel 2 10 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Processor DC Specifications The processor DC specifications in this section are defined at the PGA370 socket pins bottom side of the motherboard See Section 7 0 for the processor signal descriptions and Section 5 4 for the signal listings Most of the signals the processor system bus are in the AGTL AGTL signal group These signals are specified to be terminated to 1 5 V for AGTL or 1 25 V for AGIL The DC specifications for these signals are listed in Table 9 on page 34 To allow connection with other devices the clock CMOS and APIC signals are designed to interface at non AGTL levels The DC specifications for these pins are listed in Table 11 on page 35 Table 7 through Table 12 list the DC specifications for the Pentium lll processor for the PGA370 socket Specifications are valid only while meeting specifications for junction temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter 27 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 28 Table 7 Voltage and Current Specifications 12 Sheet 1 of 5
22. 250 6 7 11 2 5 9 10 T3 BCLK High Time ns 9 1 4 9 11 2 4 9 10 T4 BCLK Low Time ns 9 1 4 9 11 T5 BCLK Rise Time 0 4 1 6 ns 9 3 8 T6 BCLK Fall Time 0 4 1 6 ns 9 3 8 NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium III processors at all frequencies 2 All AC timings for the AGTL signals are referenced to the BCLK rising edge at 1 25 V at the processor pin All AGTL signal timings address bus data bus etc are referenced at 1 00 V at the processor pins 37 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 3 Not 10095 tested Specified by design characterization as a clock driver requirement 4 The internal core clock frequency is derived from the processor system bus clock The system bus clock to core clock ratio is determined during initialization Individual processors will only operate at their specified System bus frequency either 100 MHz or 133 MHz not both 5 The BCLK period allows a 0 5 ns tolerance for clock driver variation See the appropriate clock synthesizer driver specification for details 6 Due to the difficulty of accurately measuring clock jitter in a system it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pF This should be measured on the rising edges of adjacent BCLKs crossing 1 25 V at the processor pin The jitter present m
23. 256 ATC 068xh 600EB 600 133 256 ATC 068xh 650 650 100 256 ATC 068xh 667 667 133 256 ATC 068xh 700 700 100 256 ATC 068xh 733 733 133 256 ATC 068xh 750 750 100 256 ATC 068xh 800 800 100 256 ATC 068xh 800EB 800 133 256 ATC 068xh 850 850 100 256 ATC 068xh 866 866 133 256 ATC 068xh 900 900 100 256 ATC 068xh 933 933 133 256 ATC 068xh 1 GHz 1000 100 256 ATC 068xh 1B GHz 1000 133 256 ATC 068xh 1 10 GHz 1100 100 256 ATC 068xh 1 13 GHz 1133 133 256 ATC 068xh NOTES 1 Refer to the Pentium IIl Processor Specification Update for the exact CPUID for each processor 2 ATC Advanced Transfer Cache ATC is an L2 Cache integrated on the same die as the processor core With ATC the interface between the processor core and L2 Cache is 256 bits wide runs at the same frequency as the processor core and has enhanced buffering Datasheet 1 2 Datasheet Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Related Documents The reader of this specification should also be familiar with material and concepts presented in the following documents 12 Document Intel Document Number AP 485 Inte Processor Identification and CPUID Instruction 241618 AP 585 Pentium Processor GTL Guidelines 243330 AP 589 Design for EMI 243334 AP 905 Pentium IIl Processor Thermal Design Guidelines 245087 AP 907 Pentium IIl Proces
24. 3 650 650 100 17 0 N A N A 82 2 7 667 667 133 17 5 N A N A 82 2 8 700 700 100 18 3 21 9 34 1 80 2 9 733 733 133 19 1 22 8 35 5 80 3 0 750 750 100 19 5 23 2 36 1 80 3 0 800 800 100 20 8 24 5 38 2 80 3 2 800EB 800 133 20 8 24 5 38 2 80 3 2 850 850 100 22 5 25 7 40 0 80 3 4 866 866 133 22 9 26 1 40 7 80 3 4 900 900 100 23 2 26 7 41 6 77 3 5 933 933 133 24 5 27 5 42 8 77 3 6 1 GHz 1000 100 N A 29 0 45 2 758 3 8 1B GHz 1000 133 26 1 29 0 45 2 70 758 3 8 1B GHz 1000 133 29 6 N A N A 70 3 9 1 10 GHz 1100 100 N A 33 0 51 4 77 4 4 NOTES 1 These values are specified at nominal VcCcore for the processor pins 56 Datasheet Table 31 4 2 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 10 GHz 2 Thermal Design Power TDP represents the maximum amount of power the thermal solution is required to dissipate The thermal solution should be designed to dissipate the TDP power without exceeding the maximum Tjunction specification 3 TDP does not represent the power delivery and voltage regulation requirements for the processor Refer to Table 6 for voltage regulation and electrical specifications 4 Tiunctionottset 5 the worst case difference between the thermal reading from the on die thermal diode and the hottest location on the processor s core 5 Power density is the maximum power the processor die can dissipate i e processor power divided by the die area over which the power is generated Power for the
25. 46 3 2 AGTL AGTL Signal Quality Specifications and Measurement Guidelines 47 3 3 AGTL Signal Quality Specifications and Measurement Guidelines 48 3 3 1 X Overshoot Undershoot Guidelines 48 3 3 2 Overshoot Undershoot Magnitude 49 3 3 3 Overshoot Undershoot Pulse 49 3 9 4 AGllVIty Facto ect teri 49 3 3 5 Reading Overshoot Undershoot Specification Tables 50 3 3 6 Determining if a System Meets the Overshoot Undershoot E 51 3 4 Non AGTL Non AGTL Signal Quality Specifications and Measurement Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel m 4 0 5 0 6 0 7 0 Guidelines p t ere e RE P ta die Mg 54 3 4 4 Overshoot Undershoot Guidelines 54 3 4 2 Ringback 55 3 4 3 Settling Limit Guideline 55 Thermal Specifications and Design 56 4 1 Thermal Specifications 22 deii rene cer ect De ee o Ce ce redet 56 4 2 Processor Die Area e REEL 57 4 3 Thermal Ree eer eid 58 Mechanical Specifications 2 2 2 2 00404 60 5 1 FC PGA Mechanical Specifications
26. 88 V 20 20 10 20 20 20 NOTES 1 BCLK period is 10 ns 2 Measurements taken at the processor socket pins on the solder side of the motherboard 51 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 52 INTel Table 26 133 MHz AGTL AGTL Signal Group Overshoot Undershoot Tolerance 1 2 Maximum Pulse Duration at Tj 80 Maximum Pulse Duration at Tj 85 C Overshoot Undershoot C ns ns Magnitude AF z 0 01 AF 0 1 AF 1 0 01 0 1 1 2 18 V 15 1 9 0 19 14 1 4 0 14 2 13 V 15 3 7 0 37 15 2 4 0 24 2 08 V 15 6 8 0 68 15 4 6 0 46 2 03 V 15 12 5 1 25 15 8 6 0 84 1 98 V 15 15 2 28 15 15 1 5 1 93 V 15 15 4 1 15 15 5 1 88 V 15 15 7 5 15 15 15 NOTES 1 BCLK period is 7 5 ns 2 Measurements taken at the processor socket pins on the solder side of the motherboard Table 27 33 MHz CMOS Signal Group Overshoot Undershoot Tolerance at Processor 2 Overshoot Maximum Pulse rang at Tj 80 C Maximum Pulse at Tj 85 C Undershoot Mediums AF 0 01 AF 01 AF 1 AF 0 01 AF 0 1 AF 1 2 18 V 60 7 6 0 76 56 5 6 0 56 2 13 V 60 14 8 1 48 60 9 6 0 96 2 08 V 60 27 2 2 7 60 18 4 1 8 2 03 V 60 50 5 60 33 3 3 1 98 V 60 60 9 1 60 60 6 1 93 V 60 60 16 4 60 60 20 1 88 V 60 60 30 60 60 60 NOTES 1 PICCLK period is 30 ns 2 Measurements taken at the processor socket pins on the
27. 9 1 7V 0 7V T27 PICD 1 0 Setup Time 5 0 ns 12 4 T28 PICD 1 0 Hold Time 2 5 ns 12 4 T29a PICD 1 0 Valid Delay Rising Edge 1 5 8 7 ns 10 11 4 5 6 T29b PICD 1 0 Valid Delay Falling Edge 1 5 12 0 ns 10 11 4 5 6 NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium processors at all frequencies 2 These specifications are tested during manufacturing 3 All AC timings for the APIC I O signals are referenced to the PICCLK rising edge at 1 25 V at the processor pins All APIC I O signal timings are referenced at 0 75 V at the processor pins 4 Referenced to PICCLK rising edge 5 For open drain signals valid delay is synonymous with float delay 6 Valid delay timings for these signals are specified into 150 load pulled up to 1 5 V Table 20 Platform Power On Timings Parameter Min Max Unit Figure Notes T45 Valid Time Before PWRGD 1 0 14 1 T46 Valid Time Before PWRGOOD 2 0 14 1 147 RESET Inactive to Valid Outputs 1 BCLK 14 1 148 RESET Inactive to Drive Signals 4 BCLK 14 1 NOTES Datasheet ntel B Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 1 All signals during their invalid states must be guarded against spurious levels from effecting the platform during processor power up sequence 2 Configuration Input signals include A 14 5 BR1 INIT For timing of these
28. DBSY is deasserted This signal must connect the appropriate pins on all processor system bus agents DEFER The DEFER signal is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory agent This signal must connect the appropriate pins of all processor system bus agents DEP 7 0 y o The DEP 7 0 Data Bus ECC Protection signals provide optional ECC protection for the data bus They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor system bus agents which use them The DEP 7 0 signals are enabled or disabled for ECC protection during power on configuration DRDY y o The DRDY Data Ready signal is asserted by the data driver on each data transfer indicating valid data on the data bus In multi cycle data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor system bus agents EDGCTRL The EDGCTRL input adjusts the edge rate of AGTL output buffers for previous processors and should be pulled up to with 51 2595 resistor See the platform design guide for implementation details This signal is not used by the Pentium processor FERR The FERR Floating point Error signal is asserted when the processor detects an unma
29. Datasheet 45 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 3 0 Signal Quality Specifications Signals driven on the processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component Specifications are provided for simulation at the processor pins Meeting the specifications at the processor pins in Table 21 Table Table 23 Table and Table ensures that signal quality effects will not adversely affect processor operation 3 1 BCLK BCLK and PICCLK Signal Quality Specifications and Measurement Guidelines Table 21 describes the signal quality specifications at the processor pins for the processor system bus clock BCLK and APIC clock PICCLK signals Figure 16 describes the signal quality waveform for the system bus clock at the processor pins Table 21 BCLK PICCLK Signal Quality Specifications for Simulation at the Processor Pins Parameter Min Nom Max Unit Figure Notes V1 BCLK ViL 0 500 V 16 V1 PICCLK ViL 0 700 V 16 V2 BCLK ViH 2 000 V 16 V2 PICCLK ViH 2 000 V 16 V3 VIN Absolute Voltage Range 0 58 3 18 V 16 V4 BCLK Rising Edge Ringback 2 000 V 16 2 V4 PICCLK Rising Edge Ringback 2 000 V 16 2 V5 BCLK Falling Edge Ringback 0 500 V 16 2 V5 PICCLK Falling Edge Ringback 0 700 V 16 2 NOTES 1 U
30. Group 1 2 3 4 Parameter Min Max Unit Figure Notes T14 CMOS Input Pulse Width except Active and PWRGOOD Inactive states T15 PWRGOOD Inactive Pulse Width 10 BCLKs 11 14 5 NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium processors at all frequencies 2 These specifications are tested during manufacturing 3 These signals may be driven asynchronously 4 All CMOS outputs shall be asserted for at least 2 BCLKs 5 When driven inactive or after VTT and BCLK become stable System Bus AC Specifications Reset Conditions Parameter Min Max Unit Figure Notes T16 Reset Configuration Signals 4 BCLKs 13 Before deassertion A 14 5 BRO INIT Setup Time of RESET T17 Reset Configuration Signals 2 20 BCLKs 13 After clock that A 14 5 BRO INIT Hold Time deasserts RESET NOTE 1 Unless otherwise noted all specifications in this table apply to all Pentium processor frequencies System Bus AC Specifications APIC Clock and APIC I O 2 3 T Parameter Min Max Unit Figure Notes T21 PICCLK Frequency 2 0 33 3 MHz T22 PICCLK Period 30 0 500 0 ns 9 T23 PICCLK High Time 10 5 ns 9 gt 1 7V T24 PICCLK Low Time 10 5 ns 9 lt 0 7V T25 PICCLK Rise Time 0 25 3 0 ns 9 0 7V 1 7V T26 PICCLK Fall Time 0 25 3 0 ns
31. Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertions of the SLP STPCLK and RESET signals while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and APIC processor core units The System Management Interrupt signal is asserted asynchronously by System logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler STPCLK The STPCLK Stop Clock signal when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the bus and APIC units The processor continues to snoop bus transactions and latch interrupts while Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units services pending interrupts while in the Stop Grant state and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input THERMDN Thermal Diode Cathode Used to calculate core junction temperature See Section 4 3 THERMDP Thermal Diode Anod
32. Order by Pin Number Number Continued Pin n No Pin Name Signal Group No Pin Name Signal Group A3 D29it AGTL I O AD34 GND Power Other A5 028 AGTL AD36 Vcc 5 Power Other A7 AGTL I O AE1 17 AGTL I O AQ D37 AGTL I O AE3 A22 AGTL I O A11 D44 AGTL I O AE5 Power Other A13 D51 AGTL AE33 20 CMOS Input A15 D47 AGTL AE35 IERR CMOS Output A17 D48 AGTL AE37 FLUSH CMOS Input A19 D57 AGTL I O AF2 Power Other A21 D46 AGTL AF4 5 AGTL I O A23 D53 AGTL AF6 A25it AGTL I O A25 D60 AGTL AF32 GND Power Other A27 061 AGTL I O AF34 Power Other A29 DEP7 AGTL I O AF36 GND Power Other A31 DEP3 AGTL AG1 EDGCTRL 5 Power Other A33 DEP2 AGTL AG3 A19 AGTL I O A35 PRDY AGTL Output AG5 GND Power Other A37 GND Power Other AGS3S3 INIT CMOS Input 1 A27 AGTL AG35 STPCLK CMOS Input AA3 A30 AGTL AG37 IGNNE CMOS Input AAS Power Other AH2 GND Power Other Power Other 2 AGTL Input 5 Power Other AH6 A10 AGTL I O AA37 Power Other 8 5 AGTL I O AB2 Power Other AH10 AGTL I O AB4 A24 AGTL AH12 A4 AGTL I O AB6 A23
33. Other 24 Power Other AJ37 VID3 Power Other AM28 Power Other E33 VngrO Power Other AM32 Power Other F18 Vnerl Power Other AM4 VCCCORE Power Other K4 VREF2 Power Other AM8 VCCCORE Power Other R6 VREF3 Power Other B10 Power Other V6 Vngr4 Power Other B14 VcCconE Power Other AD6 Vngr5 Power Other B18 VcCconE Power Other AK12 Vngr6 Power Other B22 Power Other AK22 Power Other B26 Power Other AH20 VTT Power Other B30 Power Other AK16 Power Other B34 VCCconE Power Other ALi3 Power Other B6 Power Other AL21 VTT Power Other Power Other 11 VTT Power Other D20 VCCconE Power Other AN15 VTT Power Other D24 Power Other G35 VTT Power Other D28 VcCcoRE Power Other Power Other D32 Power Other 5 Power Other D36 Power Other AN21 4 Power Other D6 VcCcoRE Power Other E23 vrr 4 Power Other E13 Power Other 833 Power Other E17 Power Other 837 Power Other AJ9 Power Other 35 4 Power Other AL35 VIDO Power Other 037 vrr Power Other AM36 VID1 Power Other Datasheet 73 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 40 Signal Listing in Order by Pin Table 40 Signal Listing in
34. P N 22 23 2031 AMP P N 640456 3 lt or equivalent Fan Heatsink Power and Signal Specifications Description Min Typ Max 12 V 12 volt fan power supply 10 8 V 12V 13 2 V IC Fan current draw 100 mA SENSE SENSE frequency motherboard should pull this 2 pulses per pin up to appropriate Vcc with resistor fan revolution Figure 37 Motherboard Power Header Placement Relative to the Boxed Intel Pentium 84 Processor 0000000000000000 132 922929592259225509502 000000000000 D O e Oo PGA370 exon o 5020 500 0505 0 0 9 00000 O O O O O O O O O O 96 ceo oS O5 O exe 55525 25322592252 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 7 0 Processor Signal Description This section provides an alphabetical listing of all the Pentium III processor signals The
35. RRINQD ACK E 54 Processor Functional Die Layout for 58 FC PGA FC PGA2 Package Types 60 Package Dimensions sornas ER RR 61 Package Dimensions for 2 63 FC PGA2 Flatness 64 Top Side Processor Markings for FC PGA up to CPUID 0x686H 65 Top Side Processor Markings for FC PGA for CPUID 0x68AH 65 Top Side Processor Markings for 2 66 Volumetric Keep Out for FC PGA and 2 66 Component 67 Intel Pentium III Processor Pinout ettet 68 Conceptual Boxed Intel Pentium Processor for the PGA370 Socket 80 Dimensions of Mechanical Step Feature in Heatsink 81 Dimensions of Notches in Heatsink Base 82 Thermal Airspace Requirement for all Boxed Intel Pentium IIl Processor Fan Heatsinks in the 70 Socket eee 83 Boxed Processor Fan Heatsink Power Cable Connector Description 84 Motherboard Power Header Placement Relative to the Boxed Intel Pentium III Processor
36. THERMDP Power Other w5 VCCCORE Power Other AH28 THERMTRIP CMOS Output Y35 Power Other AK32 TMS TAP Input 732 Power Other AN25 TRDY AGTL Input AF2 VCCcoRE Power Other AN33 TRST TAP Input AF34 Power Other AD36 VCC 5 Power Other AH24 VCCconE Power Other Z36 VCCo5 Power Other AH32 Power Other AB36 Power Other AH36 Power Other 7 Power Other AJ13 Power Other 5 Power Other AJ17 VCCconE Power Other AB2 Power Other AJ21 Power Other AB34 Power Other AJ25 VCCcoRE Power Other AD32 Power Other AJ29 VCCconE Power Other AE5 VcCconE Power Other AJ5 Power Other E5 Power Other AK2 Power Other E9 VCCconE Power Other AK34 Power Other F14 Power Other 12 Power Other F2 VcCconE Power Other 16 VCCconE Power Other 72 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 39 Signal Listing in Order by Table 39 Signal Listing in Order by Signal Name Continued Signal Name Continued Pin No Pin Name Signal Group No Pin Name Signal Group 20 Power Other AL37 VID2 Power
37. a reference voltage called Refer to the appropriate platform design guide for more information Table 12 below lists the nominal specification for the AGTL termination voltage VTT The AGTL reference voltage is generated on the system motherboard and should be set to 2 3 for the processor and other logic It is important that the baseboard impedance be specified and held to a 15 tolerance and that the intrinsic trace capacitance for the AGTL signal group traces is known and well controlled For more details on the AGTL buffer specification see the Intel Pentium II Processor Developer s Manual and AP 585 Intel Pentium II Processor AGTL Guidelines Processor AGTL Bus Specifications 2 Symbol Parameter Min Typ Max Units Notes VTT Bus Termination Voltage 1 50 V 3 On die Termination Resistor 40 130 4 VREF Bus Reference Voltage 0 950 2 3 VIT 1 05 V 5 NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium processors at all frequencies 2 Pentium processors for the PGA370 socket contain AGTL termination resistors on the processor die except for the RESET input 3 VTT and Vcc 5 must be held to 1 5 V 9 It is required that VTT and Vcc 5 be held to 1 5 V 3 while the processor system bus is idle static condition This is measured at the PGA370 socket pins on the bottom side of the baseboard 4 The
38. as shown below BR 1 0 Signal Agent IDs Pin Sampled Active in RESET Agent ID BRO 0 BR1 3 BSEL 1 0 Vo These signals are used to select the system bus frequency A BSEL 1 0 01 selects a 100 MHz system bus frequency and a BSEL 1 0 11 selects 133 MHz System bus frequency The frequency is determined by the processors chipset and frequency synthesizer capabilities All system bus agents must operate at the same frequency The Pentium processor for the PGA370 socket operates at 100 MHz and 133 MHz system bus frequencies Individual processors will only operate at their specified front side bus FSB frequency Either 100 MHz or 133 MHz not both On motherboards which support operation at either 66 MHz or 100 MHz a BSEL 1 0 0 will select 66 Mhz system bus frequency 66 MHz operation is not support by the Pentium III processor for the PGA370 socket therefore BSELO is ignored These signals must be pulled up to 2 5 V 3 3V with 1 resistors and provided as a frequency selection signal to the clock driver synthesizer If the system motherboard is not capable of operating at 133 MHz it should ground the BSEL1 signal and generate a 100 MHz system bus frequency See Section 2 8 2 for implementation examples CLKREF The CLKREF input is a filtered 1 25 V supply voltage for the processor PLL A voltage divider and decoupling solution is provided by the
39. can be to either Normal Mode or the AutoHALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information FLUSH is serviced during the AutoHALT state and the processor will return to the AutoHALT state 15 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 2 2 3 2 2 4 2 2 5 The system generate a STPCLK while the processor is in the AutoHALT Power Down state When the system deasserts the STPCLK interrupt the processor returns execution to the HALT state Stop Grant State State The Stop Grant state on the processor is entered when the STPCLK signal is asserted Since the AGTL signal pins receive power from the system bus these pins should not be driven allowing the level to return to VTT for minimum power drawn by the termination resistors in this state In addition all other input pins on the system bus should be driven to the inactive state BINIT and FLUSH are not serviced during the Stop Grant state causes the processor to immediately initialize itself but the processor stays in Stop Grant state A transition back to the Normal state occurs with the deassertion of the STPCLK signal A transition to the HALT Grant Snoop state occurs when the processor detects a snoop on the system bus see Section 2 2 4 A transition to the Sleep state see Section 2 2 5 occurs with the assertion
40. design guideline Actual slew rate values and wave shapes may vary slightly depending on the type and size of decoupling capacitors used in a particular implementation Figure 8 Slew Rate 23A Load Step Icc A Socket IP 23A CPUID 068xh Table 8 PL Slew Rate Data 23A Sheet 1 of 2 Datasheet Time us 0 1 9 55 0 15 14 4 0 5 20 85 1 23 04 1 5 23 44 2 23 28 2 5 22 32 3 21 63 3 5 21 45 4 21 63 33 Time us Icc 4 5 21 88 5 22 01 Table 8 PL Slew Rate Data 23A Sheet 2 of 2 Table 9 AGTL AGTL Signal Groups DC Specifications Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz INTel Symbol Parameter Min Max Unit Notes Input Low Voltage 0 150 0 200 V 6 VIH Input High Voltage 0 200 VTT V 2 3 6 Buffer Resistance 16 67 5 Leakage Current for inputs IL outputs and I O alii NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium III processors at all frequencies 2 All inputs outputs and I O pins must comply with the signal quality specifications in Section 3 0 3 Minimum and maximum are given in Table 12 on page 36 4 0 lt VIN lt 1 5 V 395 and 0 lt 0 lt 1 5 V 3 5 Refer to the processor I O Buffer Models for I V characteristics 6 St
41. detailed information The processor utilizes multiple low power states such as AutoHALT Stop Grant Sleep and Deep Sleep to conserve power during idle times The processor includes an integrated on die 256 KB 8 way set associative level two L2 cache The L2 cache implements the new Advanced Transfer Cache Architecture with a 256 bit wide bus The processor also includes 16 KB level 1 1 instruction cache and 16 L1 data cache These cache arrays run at the full speed of the processor core As with the Pentium III processor for the SC242 connector the Pentium lll processor for the PGA370 socket has a dedicated L2 cache bus thus maintaining the dual independent bus architecture to deliver high bus bandwidth and performance see Figure 1 Memory is cacheable for 64 GB of addressable memory space allowing significant headroom for desktop systems Refer to the Specification Update document for this processor to determine the cacheability and cache configuration options for a specific processor The Specification Update document can be requested at your nearest Intel sales office The processor utilizes the same multiprocessing system bus technology as the Pentium ll processor This allows for a higher level of performance for both uni processor and two way multiprocessor systems The system bus uses a variant signaling technology called Assisted Gunning Transceiver Logic AGTL AGTL signaling technology Figure 1 Seco
42. millimeters Datasheet intel 5 2 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Processor Markings The following figure exemplifies the processor top side markings and it is provided to aid in the identification of an Pentium III processor for the PGA370 socket Table 35 and Table 37 list the measurements for the package dimensions Figure 26 Top Side Processor Markings for FC PGA up to CPUID 0x686H Figure 27 Top Side Processor Markings for FC PGA for CPUID 0x68AH 5 2 1 Datasheet Static Mark ink printed at substrate supplier pentium logo Country of Origin Y intel amp pentiumelll nae 1 m 99 RB80526PY550266 FFFFFFFF 0001 SSSSS S N S specit Product Code Dynamic Laser Mark Swatch GRPILINE4 GRP1LN1 INTEL m c 01 COO GRP1LN2 Speed Cache Bus Voltage GRP2LN1 FPO S N GRPILINE1 RP2LN2 PENTIUM III S B Processor Markings for FC PGA2 The following figure exemplifies the processor top side markings and it is provided to aid in the identification of an Pentium III processor for the FC PGA2 socket Table 37 lists the measurements for the package dimensions Note this package label will also have a 2D matrix mark 65 Pentium
43. of the SLP signal While in Stop Grant State SMI INIT and LINT 1 0 are latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event is recognized and serviced upon return to the Normal state HALT Grant Snoop State State 4 The processor responds to snoop transactions on the system bus while in Stop Grant state or in AutoHALT Power Down state During a snoop transaction the processor enters the HALT Grant Snoop state The processor stays in this state until the snoop on the system bus has been serviced whether by the processor or another agent on the system bus After the snoop is serviced the processor returns to the Stop Grant state or AutoHALT Power Down state as appropriate Sleep State State 5 The Sleep state is a very low power state in which the processor maintains its context maintains the phase locked loop PLL and has stopped all internal clocks The Sleep state can only be entered from the Stop Grant state Once in the Stop Grant state the 51 pin can be asserted causing the processor to enter the Sleep state The SLP pin is not recognized in the Normal AutoHALT states Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions
44. receivers to determine if a signal is a logical 0 or a logical 1 7 2 Signal Summaries Table 43 through Table 46 list attributes of the processor output input and I O signals Table 43 Output Signals Name Active Level Clock Signal Group CPUPRES Low Asynch Power Other EDGCTRL N A Asynch Power Other FERR Low Asynch CMOS Output IERR Low Asynch CMOS Output PRDY Low BCLK AGTL Output THERMTRIP Low Asynch CMOS Output VCOREpET N A Asynch Power Other VID 3 0 N A Asynch Power Other Table 44 Input Signals Sheet 1 of 2 Name Active Level Clock Signal Group Qualified A20M Low Asynch CMOS Input Always BCLK High System Bus Clock Always Low BCLK AGTL Input Always BR1 Low BCLK AGTL Input Always 92 Datasheet Table 44 Input Signals Sheet 2 of 2 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Name Active Level Clock Signal Group Qualified DEFER Low BCLK AGTL Input Always FLUSH Low Asynch CMOS Input Always IGNNE Low Asynch CMOS Input Always INIT Low Asynch CMOS Input Always INTR High Asynch CMOS Input APIC disabled mode LINT 1 0 High Asynch CMOS Input APIC enabled mode NMI High Asynch CMOS Input APIC disabled mode PICCLK High APIC Clock Always PREQ Low Asynch CMOS Input Always PWRGOOD High Asynch CMOS Input Always RESET
45. requires VCOREpg7 connected to Vss within the processor indicates 1 5 V requirement on VCCcyos Refer to Figure 5 Each power signal must meet the specifications stated in Table 7 on page 28 Processor Package Routing 2 5 2 5 Supply VCCoyos Intel Pentium III Processor CMOS Pullups 1 5V Supply CMOS Signa ICH or Other Logic Note Ensure this logic is compatible with 1 5V signal levels of the Inte Pentium IIl processor for the PGA370 socket Phase Lock Loop PLL Power It is highly critical that phase lock loop power delivery to the processor meets Intel s requirements A low pass filter is required for power delivery to pins PLL1 and PLL2 This serves as an isolated decoupled power source for the internal PLL Please refer to the Phase Lock Loop Power section in the appropriate platform design guide for the recommended filter specifications Datasheet intel 2 4 2 4 1 2 5 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Decoupling Guidelines Due to the large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states The fluctuations can cause voltages on power planes to sag below their nominal values if bulk decoupling is not adequate Care must be taken in the board design to ensure that th
46. signal simulation of the system bus including trace lengths is highly recommended when designing a 13 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel system with a heavily loaded AGTL bus especially for systems using a single set of termination resistors 1 those on the processor die Such designs will not match the solution space allowed for by installation of termination resistors on the baseboard Figure 2 AGTL AGTL Bus Topology in a Uniprocessor Configuration Processor Chipset Figure 3 AGTL AGTL Bus Topology in a Dual Processor Configuration LA Processor Chipset Processor 2 2 Clock Control and Low Power States Processors allow the use of AutoHALT Stop Grant Sleep and Deep Sleep states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 4 for a visual representation of the processor low power states 14 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Figure 4 Stop Clock State Machine 2 2 1 2 2 2 Datasheet HALT Instruction and HALT Bus Cycle Generated 1 Normal State Normal execution 2 Auto HALT Power Down State BCLK running Snoops and interrupts allowed BINIT INTR RESET NMI gt STPCLK Asserted Snoop Snoop STPCLK De asserted
47. the latest information Datasheet intel Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Figure 30 Component Keep Out 5 4 Datasheet Si a 1 57 290 T X 1 YA 1 49 43 ZZ NO COMPONENTS 2 5284 005 A i HEIGHT REF LT PGA310 1 022 MAX HEIGHT DESIG OFF M B SPEC 1 43 N 0 127 MAX HEIGHT OFF M B Y o oy 1 49 Y 210 672 99 ALL DIMENSIONS ARE MINIMUM UNLHSS OTHERWISE SPECIFIED Processor Signal Listing Table 39 and Table 40 provide the processor pin definitions The signal locations on the PGA370 socket are to be used for signal routing simulation and component placement on the baseboard Figure 31 provides a pin side view of the Pentium processor pinout 67 Figure 31 Intel Pentium IIl Processor Pinout Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz AN AN vss A12 A16 A6 VIT AP1 VIT BPRI DEFER NTT RP TRDY DRDY BRO ADS TRST TDI TDO AM AM RSV voc vss _ VSS _ vss vss vec vss _ VSS _ _ vss vec _ VSS VIDI AL AL vss VSS A15 A13 A9 APO VTT A7 REQ4 REQ3 VTT HITM HIT DBSY THRMDN THRMDP TCK
48. to the Pentium III Processor Specification Update for a complete listing of processors that support this pin 8 This signal is used to control the value of the processor on die termination resistance Refer to the platform design guide for the recommended pull down resistor value Table 4 System Bus Signal Groups AGTL Sheet 1 of 2 Datasheet Group Name Signals AGTL Input BPRI BR147 DEFER RSP TRDY RS 2 0 AGTL Output PRDY AGTL 1 0 A 35 3 ADS AERR AP 1 0 BERR BINIT BNR BP 3 2 BPM 1 0 BRO D 63 0 DBSY DEP 7 0 DRDY HIT HITM LOCK REQ 4 0 CMOS Inout A20M FLUSH IGNNE INIT LINTO INTR LINT1 NMI PREQ SLP SMI pu STPCLK EG Input PWRGOOD CMOS Output 10 3 0 3 BSEL 1 0 1 23 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 4 System Bus Signal Groups AGTL Sheet 2 of 2 2 8 1 24 Group Name Signals System Bus Clock 12 BCLK BCLKO 1 25 V 2 5 V APIC Clock 2 0 V PICCLK APIC PICD 1 0 Power Other THERMDP RTTCTRL VcoREpes VID 3 0 VCC4 5 5 BSEL 1 0 CLKREF CPUPRES EDGCTRL PLL 2 1 RESET2 SLEWCTRL VSS VTT Reserved NOTES 1 2 8 9 See Section 7 0 for informati
49. 1 Falling Edge Ring Back 0 35 0 35 V 1 Cross Point at 1V 0 51 0 76 0 51 0 76 V Input High Voltage 0 92 1 45 0 92 1 45 V 8 Input Low Voltage 0 2 0 35 0 2 0 35 V 8 NOTES 1 Measurement taken from differential waveform defined as BCLK BCLK 2 Period is defined from one rising 0 V crossing to the next 3 Measurement taken from differential waveform voltage range from 0 35 V to 0 35 V 4 Measurement taken from common mode waveform measure rise fall time from 0 41 V to 0 86 V Rise fall time matching is defined as the instantaneous difference between maximum BCLK rise fall and minimum BCLK fall rise time or minimum BCLK rise fall and maximum fall rise time This parameter is designed to guard waveform symmetry Period difference measured around 0 V crossings measurement taken from differential waveform The rising and falling edge ringback voltage specified is the minimum rising or them maximum falling voltage the differential waveform can go after passing Vih diff rising or Vil diff falling 7 Measured in absolute voltage i e single ended measurement Includes every cross point for both rise and fall of BCLK 8 Input high or input low voltage range measured in absolute voltage i e single ended measurement 9 The internal Core clock frequency is derived from the processor system bus clock The system bus clock to core clock ratio is determined
50. 370 Socket at 500 MHz to 1 13 GHz Second Level L2 Cache Implementation 8 AGTL AGTL Bus Topology in Uniprocessor Configuration 14 AGTL AGTL Bus Topology in a Dual Processor Configuration 14 Stop Clock State 15 Processor Package Routing 18 Differential Clocking Example ee eee ee 20 BSEL 1 0 Example for a 100 133 MHz or 100 MHz Only System Design 25 Slew Rate 23A Load 581 33 Generic Clock Waveform 41 BCLK PICCLK Generic Clock 42 System Bus Valid Delay 5 42 System Bus Setup Hold 5 43 System Bus Reset and Configuration 43 Platform Power On Sequence 44 Power On Reset and Configuration Timings sse 45 BCLK PICCLK Generic Clock Waveform at the Processor Pins 47 Low to High AGTL Receiver Ringback 48 Maximum Acceptable AGTL Overshoot Undershoot Waveform 53 Maximum Acceptable AGTL Overshoot Undershoot Waveform 53 Non AGTL Non AGTL Overshoot Undershoot Settling Limit and
51. 49660 11 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz m NOTES 1 Unless otherwise noted this reference material can be found on the Intel Developer s Website located at http developer intel com 2 For a complete listing of Pentium processor reference material please refer to the Intel Developer s Website at http developer intel com design Pentiumlll 3 This material is available through an Intel field sales representative 12 Datasheet intel 2 0 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Electrical Specifications 2 1 Datasheet Processor System Bus and The Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic GIL signaling technology The Pentium Pro processor system bus specification is similar to the GTL specification but was enhanced to provide larger noise margins and reduced ringing The improvements are accomplished by increasing the termination voltage level and controlling the edge rates This specification is different from the specification and is referred to as GIL For more information specifications see the buffer specification in the Intel Pentium II Processor Developer s Manual Current P6 family processors vary from the Pentium Pro processor in their output buffer implementation The buffers that drive the system bus signals on the Celeron
52. 7 224 Glock Controls 17 2 3 Power andi Ground Ping cien er eerte t need 17 2 8 1 Phase Lock Loop PLL 18 2 4 Decoupling Guidelines 19 2 4 1 Processor and AGTL AGTL Decoupling 19 2 5 Processor System Bus Clock and Processor Clocking 19 2 5 1 Mixing Processors of Different 20 2 6 Voltage Te 1 e e eter ere tree estt be eor 20 2 7 Processor System Bus Unused 22 2 8 Processor System Bus Signal Groups 22 2 8 1 Asynchronous vs Synchronous for System Bus Signals 24 2 8 2 System Bus Frequency Select Signals BSEL 1 0 25 2 9 MmU RANG Seine MID Roin EU ERR DEP I EE 26 2 10 Processor DC 5 27 2 10 1 ICC Slew Rate 33 2 11 AGTL AGTL System Bus Specifications 36 2 12 System Bus AC Specifications 37 2 121 Buffer Model cit ei cet e etre eeu e 37 Signal Quality 46 3 1 BCLK BCLK and PICCLK Signal Quality Specifications and Measurement ET
53. 9 D55 AGTL I O D26 GND Power Other C27 D56 AGTL I O D30 GND Power Other A19 0574 AGTL I O D34 GND Power Other C23 D58 AGTL I O D4 GND Power Other C17 D59 AGTL I O E11 GND Power Other A25 060 AGTL I O 15 GND Power Other A27 061 AGTL I O E19 GND Power Other E25 062 AGTL I O 7 GND Power Other F16 AGTL I O F20 GND Power Other AL27 DBSY AGTL I O F24 GND Power Other 19 DEFER AGTL Input F28 GND Power Other C33 DEPO AGTL I O F32 GND Power Other Datasheet 70 Datasheet Table 39 Signal Listing in Order by Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Signal Name Continued Table 39 Signal Listing in Order by Signal Name Continued a Pin Name Signal Group Pin Name Signal Group F36 GND Power Other V2 GND Power Other G5 GND Power Other V34 GND Power Other H2 GND Power Other X32 GND Power Other H34 GND Power Other X36 GND Power Other K36 GND Power Other Y37 GND Power Other L5 GND Power Other Y5 GND Power Other M2 GND Power Other 22 GND Power Other M34 GND Power Other 234 GND Power Other P32 GND Power Other AL25 HIT AGTL I O P36 GND Power Other AL23 HITM AGTL I O A37 GND Power Other AE35 IERR CMOS Output AB32 GND Power Other AG37 IGNNE CMOS Input AC33 GND Power Other AG33 INIT CMOS Input AC5 GN
54. A7 AGTL I O C35 AGTL I O AH10 A8 AGTL I O E35 BPM1 AGTL I O ALY AQ AGTL I O AN17 BPRI AGTL Input AH6 A10 AGTL I O AN29 BRO AGTL I O AK10 11 AGTL I O X2 BR14 AGTL Input 5 A123 AGTL I O AJ33 BSELO Power Other AL7 A13 AGTL I O AJ31 BSEL1 Power Other AK14 A144 AGTL I O CLKREF 7 Power Other AL5 15 AGTL I O C37 CPUPRES Power Other AN7 A16 AGTL I O W1 00 AGTL I O AE1 A17 AGTL I O T4 AGTL I O Z6 A18 AGTL I O N1 D2 AGTL I O AG3 A19 AGTL I O M6 D3 AGTL I O AC3 A20 AGTL I O U1 D4 AGTL I O 20 CMOS Input S3 D5 AGTL I O AJ1 A21 AGTL I O T6 064 AGTL I O AES A22 AGTL I O J1 D7 AGTL I O AB6 A23 AGTL I O S1 D8 AGTL I O AB4 A24 AGTL I O P6 9 AGTL I O AF6 A25 AGTL I O Q3 D10 AGTL I O 26 AGTL I O M4 011 AGTL I O AA1 A27 AGTL I O Q1 D12 AGTL I O AK6 A28 AGTL I O L1 AGTL I O Z4 A29 AGTL I O N3 D14 AGTL I O AA3 A30 AGTL I O U3 D15 AGTL I O AD4 A31 AGTL I O H4 D16 AGTL I O X6 2 AGTL I O R4 D17 AGTL I O AC1 A33 AGTL I O P4 D18 AGTL I O W3 A34 AGTL I O H6 D19 AGTL I O AF4 A35 AGTL I O L3 D20 AGTL I O AN31 ADS AGTL I O G1 AGTL I O AK24 AERR AGTL I O F8 D22 AGTL I O AL11 AGTL I O G3 D23 AGTL I O AN13 AP1 AGTL I O K6 D24 AGTL I O W37 BCLK System Bus Clock E3 D25 AGTL I O V4 BERR AGTL I O E1 D26 AGTL I O 69 Pentium III Processo
55. AGTL AH14 BNR AGTL I O AB32 GND Power Other 16 AGTL I O AB34 Power Other AH18 REQ2 AGTL I O 6 Power Other AH20 Power Other AC1 A33 AGTL AH22 RS1 AGTL Input A20 AGTL I O AH24 Power Other AC5 GND Power Other AH26 0 AGTL Input AC33 GND Power Other 28 THERMTRIP CMOS Output 5 FERR CMOS Output AH30 SLP CMOS Input AC37 RSP AGTL Input AH32 VCCconE Power Other AD2 GND Power Other AH34 GND Power Other AD4 A31 AGTL I O AH36 Power Other AD6 Vngr5 Power Other AJ1 21 AGTL I O AD32 Power Other GND Power Other Datasheet 74 Datasheet Table 40 Signal Listing in Order by Pin Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Number Continued Table 40 Signal Listing in Order by Pin Number Continued E Pin Name Signal Group Pin Name Signal Group AJ5 VCCconRE Power Other AL11 APO AGTL I O AJ7 GND Power Other AL13 VIT Power Other AJ9 Power Other AL15 ATH AGTL I O AJ11 GND Power Other AL17 REQ4 AGTL I O AJ13 Power Other AL19 REQ3 AGTL I O AJ15 GND Power Other AL21 VIT Power Other AJ17 Power Other AL23 HITM AGTL I O AJ19 GND P
56. AGTL I O K32 VCCconE Power Other F2 Power Other K34 Power Other F4 VcCconE Power Other K36 GND Power Other F6 D32 AGTL I O L1 AGTL I O F8 D22 AGTL I O L3 D20 AGTL I O F10 Reserved Reserved for future use L5 GND Power Other F12 D27 AGTL I O L33 Reserved Reserved for future use F14 VcCconE Power Other L35 PICD1 APIC F16 D63 AGTL I O L37 LINT1 NMI CMOS Input F18 Power Other M2 GND Power Other F20 GND Power Other M4 011 AGTL F22 Power Other M6 D3 AGTL I O F24 GND Power Other M32 Power Other F26 VcCconE Power Other M34 GND Power Other F28 GND Power Other M36 LINTO INTR CMOS Input F30 VCCconE Power Other 1 AGTL I O F32 GND Power Other N3 D14 AGTL I O F34 VcCconE Power Other N5 Power Other F36 GND Power Other N33 Reserved Reserved for future use G1 D21 AGTL I O N35 Reserved Reserved for future use G3 D23 AGTL I O N37 Reserved Reserved for future use G5 GND Power Other P2 Power Other G33 BP2 AGTL I O P4 D18 AGTL I O G35 VIT Power Other P6 D9 AGTL I O G37 Reserved Reserved for future use P32 GND Power Other H2 GND Power Other P34 VCCcoRE Power Other H4 D16 AGTL I O P36 GND Power Other H6 D19 AGTL I O Q1 D12 AGTL I O H32 VCCconE Power Other Q3 D10 AGTL I O H34 GND Power Other Q5 GND Power Other H36 Power Other Q33 Reserved Reserved for future use J1 D7 AGTL I O Q35 Reserved
57. AN11 VIT Power Other AL5 15 AGTL I O AN13 AP1 AGTL I O AL7 A13 AGTL I O AN15 Power Other AL9 9 AGTL I O AN17 BPRI AGTL Input 75 Datasheet Table 40 Signal Listing in Order by Pin Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Number Continued Table 40 Signal Listing in Order by Pin Number Continued E Pin Name Signal Group ey Pin Name Signal Group AN19 DEFER AGTL Input C25 D50 AGTL I O AN21 Vr Power Other C27 056 AGTL AN23 AGTL I O C29 DEP5 AGTL I O AN25 TRDY AGTL Input C31 DEP1 AGTL I O AN27 DRDY AGTL I O C33 DEPO AGTL I O AN29 BRO AGTL I O C35 BPMO AGTL I O 1 ADS AGTL I O C37 CPUPRES Power Other AN33 TRST TAP Input D2 GND Power Other 5 TDI TAP Input D4 GND Power Other AN37 TDO TAP Output D6 Power Other B2 D35it AGTL D8 D38 AGTL I O B4 GND Power Other D10 D39 AGTL I O B6 VCCconE Power Other D12 D42 AGTL I O B8 GND Power Other D14 D41 AGTL I O B10 Power Other D16 D52 AGTL I O B12 GND Power Other D18 GND Power Other B14 VcCconE Power Other D20 Power Other B16 GND Power Other D22 GND Power Other B18 Power Other D24 VCCconE Power Other B20 GND Power Other D26 GND Power Other B22
58. CLK signal quality is detailed in Section 3 1 Overshoot Undershoot Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above the nominal high voltage or below Vss The overshoot guideline limits transitions beyond VCC or VSs due to the fast signal edge rates see Figure 20 for non AGTL signals The processor can be damaged by repeated overshoot events 1 5 V or 2 5 V tolerant buffers if the charge is large enough 1 if the overshoot is great enough Permanent damage to the processor is the likely result of excessive overshoot undershoot Violating the overshoot undershoot guideline will also make satisfying the ringback specification difficult The overshoot undershoot guideline is 0 3 V and assumes the absence of diodes on the input These guidelines should be verified in simulations without the on chip ESD protection diodes present because the diodes will begin clamping the 1 5 V and 2 5 V tolerant signals beginning at approximately 0 7 V above the appropriate supply and 0 7 V below Vss If signals are not reaching the clamping voltage this will not be an issue A system should not rely on the diodes for overshoot undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult The undershoot guideline limits transitions exactly as described for the ATGL AGTL signals See Figure 18 Datasheet intel 3 4 2 Table 28 Tab
59. D Power Other M36 LINTO INTR CMOS Input AD2 GND Power Other L37 LINT1 NMI CMOS Input AD34 GND Power Other AK20 LOCK AGTL I O AF32 GND Power Other J33 PICCLK APIC Clock Input AF36 GND Power Other J35 PICDO APIC I O AG5 GND Power Other L35 PICD1 APIC AH2 GND Power Other W33 PLL1 Power Other AH34 GND Power Other U33 PLL2 Power Other AJ11 GND Power Other A35 PRDY AGTL Output AJ15 GND Power Other J37 PREQ CMOS Input AJ19 GND Power Other AK26 PWRGOOD CMOS Input AJ23 GND Power Other AK18 REQO AGTL I O AJ27 GND Power Other AH16 1 AGTL I O AJ3 GND Power Other AH18 REQ2 AGTL I O AJ7 GND Power Other AL19 REQ3 AGTL I O AK36 GND Power Other AL17 REQ4 AGTL I O AK4 GND Power Other G37 Reserved Reserved for future use AL1 GND Power Other L33 Reserved Reserved for future use AL3 GND Power Other N33 Reserved Reserved for future use 10 GND Power Other N35 Reserved Reserved for future use 14 GND Power Other N37 Reserved Reserved for future use AM18 GND Power Other Q33 Reserved Reserved for future use Q5 GND Power Other Q35 Reserved Reserved for future use R34 GND Power Other Q37 Reserved Reserved for future use T32 GND Power Other R2 Reserved Reserved for future use T36 GND Power Other W35 Reserved Reserved for future use U5 GND Power Other Y1 Reserved Reserved for future use 71 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 39 Signal Listing in Order by Signal Name Continued
60. GTL platforms do not support the Celeron processor in the PPGA package Both and AGTL input signals have differential input buffers which use Vggp as a reference signal AGTL output signals require termination to 1 5 V while AGTL output signals require termination to 1 25 V In this document the term AGTL Input refers to the AGTL input group as well as the I O group when receiving Similarly AGTL Output refers to AGTL output group as well as the I O group when driving The PWRGOOD BCLK and PICCLK inputs can each be driven from ground to 2 5 V Other CMOS inputs A20M IGNNE INIT LINTO INTR LINTI NMI PREQ SMI SLP and STPCLK23 are only 1 5 V tolerant and must be pulled up to The CMOS APIC and TAP outputs are open drain and must be pulled high to This ensures correct operation for current Pentium lll and Celeron processors Datasheet In Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz The groups and the signals contained within each group are shown in Table 3 and Table 4 Refer to Section 7 0 for a description of these signals Table 3 System Bus Signal Groups Group Name Signals AGTL Input BPRI BR147 DEFER RESET 5 RESET2 RS 2 0 RSP TRDY AGTL Output PRDY AGTL VO 35 3 ADS AERR AP 1 0 BERR BINIT BNR BP 3 2 BPM 1 0 BROZ 0 63 0 DBS
61. Hz intel 4 0 Thermal Specifications and Design Considerations This chapter provides needed data for designing a thermal solution However for the correct thermal measuring processes refer to AP 905 Intel Pentium IIl Processor Thermal Design Guidelines Document Number 245087 The Pentium processor uses flip chip pin grid array packaging technology and has a junction Tjunction or case temperature Tease specified 4 1 Thermal Specifications Table 30 provides the thermal design power dissipation and maximum temperatures for the Pentium lll processor for the PGA370 socket Systems should design for the highest possible processor power even if a processor with a lower thermal dissipation is planned A thermal solution should be designed to ensure the junction temperature never exceeds these specifications Table 30 Intel Pentium III Processor Thermal Design Power for the FC PGA Package Processor Thermal Processor Power Tena Processor System Design erma eee Offset for Processor cure Bus Power baan CPUID Tyunction Latest Frequency Frequency up to Stepping CPUID 068Ah 2 MHz CPUID 2 C 4 6 068Ah W cm 0686h W W 500E 500 100 13 2 N A N A 85 1 9 533EB 533 133 14 0 N A N A 85 2 0 550E 550 100 14 5 N A N A 85 2 1 600E 600 100 15 8 19 6 30 5 82 2 6 600EB 600 133 15 8 N A N A 82 2
62. It is recommended that the BCLK input be held low during the Deep Sleep State Stopping of the BCLK input lowers the overall current consumption to leakage levels To re enter the Sleep state the BCLK input must be restarted A period of 1 ms to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin can be deasserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals are allowed on the system bus while the processor is in Deep Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior Clock Control BCLK provides the clock signal for the processor and on die L2 cache During AutoHALT Power Down and Stop Grant states the processor will process a system bus snoop The processor does not stop the clock to the L2 cache during AutoHALT Power Down or Stop Grant states Entrance into the Halt Grant Snoop state allows the L2 cache to be snooped similar to the Normal state When the processor is in Sleep and Deep Sleep states it does not respond to interrupts or snoop transactions During the Sleep state the internal clock to the L2 cache is not stopped During the Deep Sleep state the internal clock to the L2 cache is stopped The internal clo
63. LK at the processor pins All AGTL signal timings compatibility signals etc are referenced at 1 00 V 2 3 VTT for AGTL at the processor pins Valid delay timings for these signals are specified into 50 Q to 1 5 V at 1 0 V 2 and with 56 on die For AGTL platforms the valid delay timings are specified into 50 to 1 25 V at 2 3 VTT 2 and with 56 on die A minimum of 3 clocks must be guaranteed between two active to inactive transitions of TRDY RESET can be asserted active asynchronously but must be deasserted synchronously For 2 way MP systems RESET should be synchronous Specification is for a minimum 0 40 V swing from 200 mV to 200 mV This assumes an edge rate of 0 3V ns Specification is for a maximum 1 0 V 2 3 VTT for AGTL swing from VTT 1V to VTT This assumes an edge rate of 3V ns This should be measured after VTT and BCLK become stable 10 This specification applies to the Pentium III processor running at 100 MHz system bus frequency 11 This specification applies to the Pentium III processor running at 133 MHz system bus frequency 12 BREQ signals at 133 MHz system bus observe a 1 2 ns minimum setup time 13 For AGTL VREF is 2 3 3 39 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 40 Table 17 Table 18 Table 19 System Bus AC Specifications CMOS Signal
64. Pentium II and Pentium III processors are actively driven to for one clock cycle after the low to high transition to improve rise times These signals should still be considered open drain and require termination to a supply that provides the high signal level Because this specification is different from the standard specification it is referred to as AGTL or Assisted in this and other documentation AGTL logic logic are compatible with each other and may both be used on the same system bus For more information on AGTL routing see the appropriate platform design guide Note that some Pentium lll processors with CPUID 068xh support the AGTL specification in addition to the AGTL specification AGTL logic and logic are not compatible with each other due to differences with the signal switching levels Processors that do not support the AGTL specification cannot be installed into platforms where the chipset only supports the AGTL signal levels For more information on AGTL AGIL routing please refer to the appropriate platform design guide Both AGTL and AGTL inputs use differential receivers which require a reference signal Vggr 15 used by the receivers to determine if a signal is a logical 0 or a logical 1 and is supplied by the motherboard to the PGA370 socket for the processor core Local copies should also be generated on the motherboard for all other devices
65. RESET must always be terminated on the motherboard as the Pentium III processor for the PGA370 socket does not provide on die termination of this input For unused CMOS inputs active low signals should be connected through a pull up resistor to and meet Vy requirements Unused active high CMOS inputs should be connected through a pull down resistor to ground Vss and meet requirements Unused CMOS outputs can be left unconnected A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Processor System Bus Signal Groups To simplify the following discussion the processor system bus signals have been combined into groups by buffer type P6 family processor system bus outputs are open drain and require high level source provided termination resistors However the Pentium lll processor for the PGA370 socket includes on die termination Motherboard designs that also support Celeron processors in the PPGA package will need to provide AGTL termination on the system motherboard as well Platform designs that support dual processor configurations will need to provide AGTL termination via a termination package in any socket not populated with a processor Please refer to the Pentium Processor Specification Update for a complete listing of the processors that support the AGTL and AGTL specifications Note that A
66. RO BR1 FLUSH INT T9 AGTL Input Hold Time NOTE Single Ended clock uses BCLK only T8 AGTL Input Setup Time Differential clock uses BCLK and BCLK 10 RESET Pulse Width T16 Reset Configuration Signals A 14 5 BHOR BR1 FLUSH INIT Setup Time T17 Reset Configuration Signals A 14 5 BRO BR1 FLUSH INIT Hold Time Datasheet 43 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 44 Figure 14 Platform Power On Sequence Timings Vtt Vref Vcmosref VID b Valid BSEL 1 0 45 Valid 145 VTT PWRGD VCC Core SSS SSS SS 47S BCLK NI N x PICCLK VCC PWRGD Configuration Inputs Inactive Valid Config x Active RESET THERMTRIP PICD 1 0 AGTL Outputs All other CMOS Outputs All other Inputs Inactive Datasheet ntel B Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Figure 15 Power On Reset and Configuration Timings BCLK Vtr REF PWRGOOD RESET Tc Configuration A20M IGNNE Valid Ratio INTR NMI T 2 715 PWRGOOD Inactive Pulse T10 RESET Pulse Width T T20 Reset Configuration Signals 20 IGNNE LINT 1 0 Hold Time m o 765a
67. Reserved for future use J3 D30 AGTL I O Q37 Reserved Reserved for future use J5 Power Other R2 Reserved Reserved for future use J33 PICCLK APIC Clock Input R4 D17 AGTL I O J35 PICDO APIC I O R6 VREFS Power Other J37 PREQ CMOS Input R32 VCCcoRE Power Other Datasheet 77 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 40 Signal Listing in Order by Pin Table 40 Signal Listing in Order by Pin Number Continued Number Continued Pin z 5 No Pin Name Signal Group No Pin Name Signal Group R34 GND Power Other V36 Power Other R36 Power Other WT DO AGTL I O 51 D8 AGTL I O A34 AGTL I O S3 05 AGTL I O w5 VCCconE Power Other S5 Power Other W33 PLL1 Power Other S33 VTT Power Other W35 Reserved Reserved for future use S35 RTTCTRL Power Other W37 BCLK System Bus Clock S37 vit 4 Power Other X2 BR148 AGTL input T2 Power Other X4 RESET2 2 AGTL I O T4 01 AGTL I O X6 A32 AGTL I O T6 D6 AGTL I O X32 GND Power Other T32 GND Power Other X34 Reserved Reserved for future use T34 VCCconE Power Other X36 GND Power Other T36 GND Power Other Y1 Reserved Reserved for future use U1 D4 AGTL I O Y3 A26 AGTL I O U3 D15 AGTL I O Y5 GND Power Other 05 GND Power Other Power Other U33 PLL2 Power Other Y35
68. STPCLK STPCLK Event Event and Stop Grant State Asserted De asserted Occurs Serviced entered from AutoHALT 4 HALT Grant Snoop State Snoop Event Occurs 3 Stop Grant State BCLK running BCLK running Service snoops to caches Snoop Event Serviced Snoops and interrupts allowed SLP SLP Asserted De asserted 5 Sleep State BCLK running No snoops or interrupts allowed BCLK BCLK Input Input Stopped Restarted 6 Deep Sleep State BCLK stopped No snoops or interrupts allowed PCB757a For the processor to fully realize the low current consumption of the Stop Grant Sleep and Deep Sleep states a Model Specific Register MSR bit must be set For the MSR at 02AH Hex bit 26 must be set to a 1 this is the power on default setting for the processor to stop all internal clocks during these modes For more information see the Intel Architecture Software Developer s Manual Volume 3 System Programming Guide located on the developer intel com website Normal State State 1 This is the normal operating state for the processor AutoHALT Powerdown State State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction The processor transitions to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET causes the processor to immediately initialize itself The return from a System Management Interrupt SMI handler
69. Specifications Reset Conditions 40 System Bus AC Specifications APIC Clock and APIC 40 Platform Power On 5 40 BCLK PICCLK Signal Quality Specifications for Simulation at the Processor lat 46 BCLK PICCLK Signal Quality Specifications for Simulation at the Processor Pins in a Differential Clock Platform for 46 AGTL Signal Groups Ringback Tolerance Specifications at the Processor de 47 Example Platform Information eese 50 100 MHz AGTL AGTL Signal Group Overshoot Undershoot Tolerance at Processor PINS RERO 51 133 MHz AGTL AGTL Signal Group Overshoot Undershoot Tolerance 52 33 MHz CMOS Signal Group Overshoot Undershoot Tolerance at dla 52 Signal Ringback Specifications for Non AGTL Signal Simulations at the Processor Em 55 Signal Ringback Specifications for Non AGTL Signal Simulations at the PrOCESSOM PINS si 55 Intel Pentium Processor Thermal Design Power for the FC PGA Package 56 Intel Pentium Processor for the FC PGA2 Package Thermal Dosign me 57 Processor Functional Die Layout for FC PGA 58 Thermal Diode Parameters 59 Thermal Diode
70. T and HITM together IERR The IERR Internal Error signal is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor system bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT IGNNE The IGNNE Ignore Numeric Error signal is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding Write bus transaction INIT The INIT Initialization signal when asserted resets integer registers inside all processors without affecting their internal L1 or L2 caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appr
71. Table 25 100MHz signal group If the signal is an signal operating with 133MHz system bus use Table 26 133 MHz AGTL signal group If the signal is CMOS signal use Table 27 33 MHz CMOS signal group 2 Determine the maximum junction temperature Tj for the range of processors that the system will support 80 C or 85 C 3 Determine the Magnitude of the overshoot relative to VSS Determine the Activity Factor how often does this overshoot occur 5 From the appropriate Specification table read off the Maximum Pulse Duration in ns allowed 6 Compare the specified Maximum Pulse Duration to the signal being measured If the Pulse Duration measured is less than the Pulse Duration shown in the table then the signal meets the specifications The above procedure is similar for undershoots after the undershoot waveform has been converted to look like an overshoot Undershoot events must be analyzed separately from Overshoot events as they are mutually exclusive Below is an example showing how the maximum pulse duration is determined for a given waveform Example Platform Information Required Information Maximum Platform Support Notes FSB Signal Group 133 MHz AGTL Max Tj 85 C Overshoot Magnitude 2 13V Measured Value Activity Factor AF 0 1 Measured overshoot occurs on average every 20 clocks NOTES 1 Corresponding Maximum Pulse Duration Specific
72. VIDO VID2 AK vcc vss A28 A3 A11 VREF6 A14 VIT REQO LOCK VREF7 AERR PWRGD RS2 RSV TMS VCC VSS AJ AJ A21 vss vec _ VSS _ vss vec _ 55 _ vss vec vss _ VSS _BSEL1 BSELO AH vss RESET A10 AS A8 A4 BNR 2 VTT RS1 voc RSO THERM SLP voc VSS VCC AG EIE AG EDGCTRL A19 vss INIT IGNNE AF voc A35 A25 vss voc _ VSS AE AE A17 A22 VCC A20M IERR FLUSH AD AD VSS A31 VREF5 vss 15 A33 A20 vss vss FERR RSP AB _ 24 A23 vss vec V CMOS AA AA A27 A30 vec VIT VIT 2 2 VSS A29 A18 vcc vss V 2 5 Y Y RSV A26 vss CLKREF _ VSS x O x BR1 RESET2 A32 vss RSV vss W W A34 VOC RSV BCLK Rm m vss BERR VREF4 x L S Vi Vi o Q Pin Side View Q u D4 D15 VSS PLL2 VIT VIT T vec Dt 56 vss _ vss 5 5 08 05 VIT RIT VIT R R RSV 017 VREF3 vec _ VSS _ Q 012 010 VSS RSV RSV RSV P o voc 018 D9 vss vec _ VSS N N D2 014 VCC RSV RSV RSV M vss Di 03 5 LNTO L 020 VSS RSV PICD1 LINTI K K _ VREF2 024 vec vec _ vss J J D7 D30 voc PICCLK PICDO PREQ H o H vss 016 019
73. Y DEP 7 0 DRDY HIT HITM LOCK 4 0 CMOS Inout A20M FLUSH IGNNE INIT LINTO INTR LINT1 NMI PREQ SLP SMI P STPCLK CMOS Input PWRGOOD CMOS Output FERR IERR THERMTRIP System Bus Clock Berk APIC Clock PICCLK APIC PICD 1 0 BSEL 1 0 CLKREF CPUPRES EDGCTRL PLL 2 1 RESET2 SLEWCTRL Power Other THERMDN THERMDP RTTCTRL8 VcoREper VID 3 0 VCC 5 5 VCComos VSS VTT Reserved 5 1 See Section 7 0 for information on the these signals 2 The BRO pin is the only BREQ signal that is bidirectional See Section 7 0 for more information The internal BREQ signals are mapped onto the BR 1 0 pins after the agent ID is determined 3 These signals are specified for 1 5 V for the Pentium processor operation 4 These signals are 2 5 V tolerant 5 is the power supply for the processor core is described in Section 2 6 VID 3 0 is described in Section 2 6 VTT is used to terminate the system bus and generate on the motherboard Vss is system ground VCOC1 5 VCC2 5 are described in Section 2 3 BSEL 1 0 is described in Section 2 8 2 and Section 7 0 All other signals are described in Section 7 0 6 RESET must always be terminated to VTT on the motherboard on die termination is not provided for this signal 7 This signal is not supported by all processors Refer
74. a package technology called flip chip pin grid array or FC PGA This package utilizes the same 370 pin zero insertion force socket PGA370 used by the Intel Celeron processor Thermal solutions are attached directly to the back of the processor core package without the use of a thermal plate or heat spreader As core frequencies increase the need for better power dissipation arises so an Integrated Heat Spreader IHS has been introduced at the higher frequencies near 1B GHz The package with an IHS is called FC PGA2 The Pentium lll processor like its predecessors in the P6 family of processors implements a Dynamic Execution microarchitecture a unique combination of multiple branch prediction data flow analysis and speculative execution This enables these processors to deliver higher performance than the Pentium processor while maintaining binary compatibility with all previous Intel Architecture processors The processor also executes Intel MMX technology instructions for enhanced media and communication performance just as it s predecessor the Pentium III processor Additionally Pentium lll processor executes Streaming SIMD single instruction multiple data Extensions for enhanced floating point and 3 D application performance The concept of processor identification via CPUID is extended in the processor family with the addition of a processor serial number Refer to the Intel Processor Serial Number application note for more
75. ack Specifications for Non AGTL Signal Simulations at the Processor Pins iss Maximum Ringback Input Signal Group Transition with Input Diodes Present Unit Figure Non AGTL Signals 2 0 1 ner 0 200 V 20 Non AGTL Signals 2 120 Vcwos 0 300 V 20 PWRGOOD 0 1 2 003 20 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium processor frequencies 2 Non AGTL signals except PWRGOOD 3 For Coppermine T with differential clocking this signal is 1 8 V tolerant Settling Limit Guideline Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition The amount allowed is 10 of the total signal swing above and below its final value A signal should be within the settling limits of its final value when either in its high state or low state before it transitions again Signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity Simulations to verify settling limit may be done either with or without the input protection diodes present Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions 55 Pentium Processor for the PGA370 Socket at 500 MHz to 1 10 G
76. al processor designs these pins must be connected to VTT This pin is required for backwards compatibility If backwards compatibility is not required this pin may be left connected to Refer to the appropriate platform design guide for implementation details Previously PGA370 designs defined this pin as a GND It is now reserved and must be left unconnected N C Previously PGA370 socket designs defined this pin as GND It is now CLKREF For Uniprocessor designs this pin is not used and it is defined as RESERVED Refer to the Pentium Ill processor Specification Update for a complete listing of processors that support DP operation Future low voltage AGTL PGA370 designs will redefine this pin as VTT Refer to the appropriate platform design guide for connectivity and to the Pentium IIl processor Specification Update for a complete listing of processors that support the new pinout definition 10 Future low voltage AGTL PGA370 designs define these pins as GND Refer to the appropriate platform design guide for connectivity and to the Pentium Ill processor Specification Update for a complete listing of processors that support the new pinout definition 11 Future low voltage AGTL PGA370 designs define this pin as RESERVED and must be left unconnected Refer to the appropriate platform design guide for connectivity 12 Future low voltage AGTL PGA370 designs will redefine these pins Refer to the appr
77. ansition of RESET for power on configuration These configuration options are described in the P6 Family of Processors Hardware Developer s Manual for details The processor may have its outputs tristated via power on configuration Otherwise if INIT is sampled active during the active to inactive transition of RESET the processor will execute its Built in Self Test BIST Whether or not BIST is executed the processor will begin program execution at the power on Reset vector default 0 FFFF FFFOh RESET must connect the appropriate pins of all processor System bus agents RESET2 The RESET2 pin is provided for compatibility with other Intel Architecture processors The Pentium processor does not use the RESET2 pin Refer to the platform design guide for the proper connections of this signal RP yo The Request Parity signal is driven by the request initiator and provides parity protection on ADS and REQ 4 0 It must connect the appropriate pins of all processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high RS 2 0 The RS 2 0 Response Status signals are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor syste
78. ation 2 4 ns 2 Pulse Duration measured 2 0 ns Given the above parameters and using Table 26 85 C AF 0 1 column the maximum allowed pulse duration is 2 4 ns Since the measure pulse duration is 2 0 ns this particular overshoot event passes the overshoot specifications although this doesn t guarantee that the combined overshoot undershoot events meet the specifications Datasheet intel 3 3 6 Table 25 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Determining if a System Meets the Overshoot Undershoot Specifications The overshoot undershoot specifications listed in the following tables specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that each have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when you add the total impact of all overshoot events the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below It is important to meet these guidelines otherwise contact your Intel field representative 1 Insure no signal CMOS or AGTL AGTL ever exceed the 1 635 V OR 2 If only one overshoot undershoot event magnitude occurs ensure it meets the over undershoot specifications in the following tables OR 3 If multiple overshoots an
79. by design characterization 4 Please see Table 25 for maximum allowable overshoot 5 Ringback between 100 mV and 200 mV or 200 mV 100 mVs requires the flight time measurements to be adjusted as described in the Intel AGTL Specifications ntef amp PentiumIl Developers Manual Ringback below 100 mV or above 100 mV is not supported 47 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 6 Intel recommends simulations not exceed a ringback value of 200 mV to allow margin for other Sources of system noise 7 negative value for p indicates that the amplitude of ringback is above Vpe_r i e 100 mV specifies the signal cannot ringback below 100 mV 8 and p are measured relative to is measured relative to 200 mV Figure 17 Low to High AGTL Receiver Ringback Tolerance 3 3 3 3 1 48 Vaer 0 2 REF Vae 0 2 1 Time Note High to low case is analogous AGTL Signal Quality Specifications and Measurement Guidelines Overshoot Undershoot Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above the nominal high voltage or below Vss The overshoot guideline limits transitions beyond VCC or Vss due to the fast signal edge rates The processor can be damaged by repeated overshoot events on 1 5 V or 2 5 V tolerant buff
80. ck to the L2 cache is restarted only after the internal clocking mechanism for the processor is stable i e the processor has re entered Sleep state PICCLK should not be removed during the AutoHALT Power Down or Stop Grant states PICCLK can be removed during the Sleep or Deep Sleep states When transitioning from the Deep Sleep state to the Sleep state PICCLK must be restarted with BCLK Power and Ground Pins The operating voltage of the Pentium III processor for the PGA370 socket is the same for the core and the L2 cache There are four pins defined on the package for voltage identification VID These pins specify the voltage required by the processor core These have been added to cleanly support voltage specification variations on current and future processors For clean on chip power and voltage reference distribution the Pentium processors in the PGA370 socket have 75 VCCcorg 8 7 for AGTL platforms 15 VTT and 77 Vss ground inputs VCCcorg inputs supply the processor core including the on die L2 cache VTT inputs 1 For processors using AGTL level bus with differential clocking the deep sleep state is entered by stopping BCLK and BCLK input 2 For processors using AGTL level bus with differential clocking this would also include the BCLK signal as well Datasheet 17 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 5 2 3 1 1 5
81. d operation and ensure the atomicity of lock Datasheet 89 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 90 Table 42 Signal Description Sheet 6 of 8 Name Type Description PICCLK The PICCLK APIC Clock signal is an input clock to the processor and core logic or APIC which is required for operation of all processors core logic and I O APIC components on the APIC bus PICD 1 0 yo The PICD 1 0 APIC Data signals are used for bidirectional serial message passing on the APIC bus and must connect the appropriate pins of all processors and core logic or APIC components on the APIC bus PLL1 PLL2 All Pentium processors have an internal analog PLL clock generator that requires a quiet power supply PLL1 and PLL2 are inputs to this PLL and must be connected to through a low pass filter that minimizes jitter See the platform design guide for implementation details PRDY The PRDY Probe Ready signal is a processor output used by debug tools to determine processor debug readiness PREQ The PREQ Probe Request signal is used by debug tools to request debug operation of the processors PWRGOOD The PWRGOOD Power Good signal is processor input The processor requires this signal to be a clean indication that the clocks and power supplies etc are stable and within their specifications Clean implies that t
82. d VTT undershoot While overshoot can be measured relative to VSS using one probe probe to signal and GND lead to VSS undershoot must be measured relative to VTT This could be accomplished by simultaneously measuring the VTT plane while measuring the signal undershoot Today s oscilloscopes can easily calculate the true undershoot waveform The true undershoot waveform can also be obtained with the following oscilloscope data file analysis Converted Undershoot Waveform VTT Signal measured The converted undershoot waveform appears as a positive overshoot signal Overshoot rising edge and undershoot falling edge conditions are separate and their impact must be determined independently After the true waveform conversion the undershoot overshoot specifications shown in Table 25 through Table 27 can be applied to the converted undershoot waveform using the same magnitude and pulse duration specifications used with an overshoot waveform Overshoot undershoot magnitude levels must observe the Absolute Maximum Specifications listed in Table 25 through Table 27 These specifications must not be violated at any time regardless of bus activity or system state Within these specifications are threshold levels that define different allowed pulse durations Provided that the magnitude of the overshoot undershoot is within the Absolute Maximum Specifications 2 18V the pulse magnitude duration and activity factor must all be used to determine
83. d or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 1 specifications If all of these worst case overshoot or undershoot events meet the specifications measured time specifications in the table where AF 1 then the system passes The following notes apply to Table 25 through Table 27 NOTES Overshoot Undershoot Magnitude 2 18 V is an Absolute value and should never be exceeded Overshoot is measured relative to Vss Undershoot is measured relative to VTT Overshoot Undershoot Pulse Duration is measured relative to 1 635 V Ringbacks below VTT can not be subtracted from Overshoots Undershoots Leser Undershoot does not allocate longer or larger Overshoot OEM s are encouraged to follow Intel provided layout guidelines Consult the layout guidelines provided in the specific platform design guide All values specified by design characterization Oo On E GMM 100 MHz AGTL AGTL Signal Group Overshoot Undershoot Tolerance at Processor Pins OverahaoU Maximum Pulse P at Tj 80 C Maximum Pulse r a at Tj 85 C Undershoot 0 01 AF 0 1 1 0 01 0 1 1 2 18 V 20 2 53 0 25 18 6 1 86 0 18 2 13 V 20 4 93 0 49 20 3 2 0 32 2 08 V 20 9 1 0 91 20 6 1 0 6 2 03 V 20 16 6 1 67 20 11 4 1 1 1 98 V 20 20 3 0 20 20 2 1 93 V 20 20 5 5 20 20 6 6 1
84. details on the RTTCTRL signal Refer to the recommendation guidelines for the specific chipset processor combination 5 Vngr is generated on the motherboard and should be 2 3 VTT 2 nominally Insure that there is adequate decoupling on the motherboard 6 For the Coppermine T differential clock platform the on die RTT min should be 50 Q 7 Coppermine T UP platforms require 560 resistor and Coppermine T DP platforms require a 680 resistor Tolerance for the on die is 10 for 560 and 680 resistors and 15 for 100 resistors Datasheet intel 2 12 2 12 1 Table 14 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz System Bus AC Specifications The processor system bus timings specified in this section are defined at the socket pins on the bottom of the motherboard Unless otherwise specified timings are tested at the processor pins during manufacturing Timings at the processor pins are specified by design characterization See Section 7 0 for the processor signal definitions Table 14 through Table 20 list the AC specifications associated with the processor system bus These specifications are placed into the following categories Table 14 and Table 15 contain the system bus clock specifications Table 16 contains the AGTL AGTL specifications Table 17 contains the CMOS signal group specifications Table 18 contains timings for the reset conditions Table 19 and covers APIC bu
85. ductance tolerable and reaction time of the voltage regulator This parameter is not tested 14 dlcc dt specifications are measured and specified at the PGA370 socket pins 15 CLKREF must be held to 1 25 V 6 5 This tolerance accounts for 5 power supply and 1 resistor divider tolerance It is recommended that the motherboard generate the CLKREF reference from either the 2 5 V or 3 3 V supply should not be used due to risk of AGTL switching noise coupling to this analog reference 16 Static voltage regulation includes DC output initial voltage set point adjust Output ripple and noise Output load ranges specified in the tables above 17 This specification applies to PGA370 processors operating at frequencies of 933 MHz or higher Datasheet 2 10 1 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 18 This specification only applies to 1B GHz S spec SLAWM This part has a VID request of 1 70 V however the processor should be supplied 1 76 V at the PGA Vcc pin by the Voltage Regulator Circuit or VRM 19 This specification applies only to 1B GHz S spec SLAWM This value is 60 mV offset from the standard specification and more at the Minimum specification These tolerances are measured from a 1 70 V base while Vcc supplied is 1 76 V 20 This processor exists in both FC PGA and FC PGA2 Icc Slew Rate Specifications This section contains typical current slew rate data for processors covered by this
86. during initialization Individual processors will only operate at their specified System bus frequency 133 MHz Table 16 shows supported ratios for each processor 10 Due to the difficulty of accurately measuring clock jitter in a system it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 pF to 20 pF The jitter must be accounted for as a component of BCLK timing skew between devices 11 AC parameters are measured at the processor pins 12 BCLK BCLK must rise fall monotonically between Vil and Vih 38 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 16 System Bus AC Specifications AGTL AGTL Signal Group 2 3 13 Datasheet Parameter Min Max Unit Figure Notes T7 AGTL Output Valid Delay 0 40 3 25 ns 11 4 10 11 1 20 ns 12 5 6 7 10 T8 AGTL Input Setup Time 0 95 ns 12 5 6 7 11 12 T9 AGTL Input Hold Time 1 00 ns 12 8 10 T10 RESET Pulse Width 1 00 ms 13 6 9 10 NOTES 1 2 3 8 9 Unless otherwise noted all specifications in this table apply to Pentium III processors at all frequencies These specifications are tested during manufacturing All timings for the AGTL signals are referenced to the BCLK rising edge at 1 25 V at the processor pins for the timings are referenced to the rising edge of BCLK and the falling edge of BC
87. e BPRI The BPRI Bus Priority Request signal is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of all processor system bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 42 Signal Description Sheet 3 of 8 Datasheet Name Type Description BRO BR1 Vo The BRO and BR1 Bus Request pins drive the BREQ 1 0 signals in the system The BREQ 1 0 signals are interconnected in a rotating manner to individual processor pins The table below gives the rotating interconnect between the processor and bus signals BRO I O and BR1 Signals Rotating Interconnect Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO 1 BR1 BRO During power up configuration the central agent must assert the BRO bus signal All symmetric agents sample their BR 1 0 pins on active to inactive transition of RESETH The pin on which the agent samples an active level determines its symmetric agent ID All agents then configure their pins to match the appropriate bus signal protocol
88. e Used to calculate core junction temperature See Section 4 3 THERMTRIP The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 135 C This is signaled to the system by the THERMTRIP Thermal Trip pin Once activated the signal remains latched and the processor stopped until RESET goes active There is no hysteresis built into the thermal sensor itself as long as the die temperature drops below the trip level a RESET pulse will reset the processor and execution will continue If the temperature has not dropped below the trip level the processor will continue to drive THERMTRIP and remain stopped The system designer should not act upon THERMTRIP until after RESET input is de asserted since until this time the THERMTRIP output is indeterminate TRDY The TRDY Target Ready signal is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all processor system bus agents 91 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 42 Signal Description Sheet 8 of 8 Name Type Description The VID 3 0 Voltage ID
89. e associativity provides improved m Internet Streaming SIMD Extensions for cache hit rate on reads store operations enhanced video sound and 3D performance m Error correcting code for System Bus data m Binary compatible with applications running m Enables systems which are scaleable for up to on previous members of the Intel two processors microprocessor line The Pentium III processor is designed for high performance desktops and for workstations and servers It is binary compatible with previous Intel Architecture processors The Pentium III processor provides great performance for applications running on advanced operating systems such as Windows 98 Windows NT and UNIX This is achieved by integrating the best attributes of Intel processors the dynamic execution Dual Independent Bus architecture plus Intel MMX technology and Internet Streaming SIMD Extentions bringing a new level of performance for systems buyers The Pentium III processor is scaleable to two processors in a multiprocessor system and extends the power of the Pentium II processor with performance headroom for business media communication and internet capabilities Systems based on Pentium III processors also include the latest features to simplify system management and lower the cost of ownership for large and small business environments The Pentium III processor offers great performance for today s and tomorrow s applications FC PGA370 Package J
90. e measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the Tjunction temperature can change Datasheet Pentium III Processor for the PGA370 Socket at 500 MHz to 1 10 GHz Table 33 Thermal Diode Parameters Symbol Parameter Min Typ Max Unit Notes lew Forward Bias Current 5 300 UA 1 n Diode Ideality Factor 1 0057 1 0080 1 0125 2 3 4 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized at 100 C with a forward bias current of 5 300 LA 3 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation Vd q nkT 1 where Is saturation current q electronic charge Vd voltage across the diode Boltzmann Constant and T absolute temperature Kelvin 4 Not 100 tested Specified by design characterization Table 34 Thermal Diode Interface Pin Name PGA370 Socket Pin Description THERMDP AL31 diode anode p_junction THERMDN AL29 diode cathode n_junction Datasheet 59 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 5 0 Mechanical Specifications The Pentium III processor uses a FC PGA and FC PGA2 package technology Mechanical specifications for the processor are given in this sectio
91. e technology used on Pentium III processors for the PGA370 socket FC PGA2 Flip Chip Pin Grid Array with an Integrated Heat Spreader IHS The package technology used on Pentium III processors for the PGA370 socket for increased power dissipation away from the die The IHS covers the die and has a very low thermal resistance Integrated Heat Spreader IHS The IHS is a metal cover on the die and is an integral part of the CPU The IHS promotes heat spreading away from the die backside to ease thermal constraints Advanced Transfer Cache ATC New L2 cache architecture unique to the 0 18 micron Pentium III processors ATC consists of microarchitectural improvements that provide a higher data bandwidth interface into the processor core that is completely scaleable with the processor core frequency Keep out zone The area on or near a FC PGA packaged processor that system designs can not utilize Keep in zone The area of a FC PGA packaged processor that thermal solutions may utilize OLGA Organic Land Grid Array The package technology for the core used in S E C C 2 processors that permits attachment of the heatsink directly to the die PPGA Plastic Pin Grid Array The package technology used for Celeron processors that utilize the PGA370 socket Processor this document the term processor is the generic form of the Pentium Ill processor for the PGA370 socket in the FC PGA package Processor core
92. e voltage provided to the processor remains within the specifications listed in Table 7 Failure to do so can result in timing violations in the event of a voltage sag or a reduced lifetime of the component in the event of a voltage overshoot Unlike SC242 based designs motherboards utilizing the PGA370 socket must provide high frequency decoupling capacitors on all power planes for the processor Processor and AGTL AGTL Decoupling The regulator for the input must be capable of delivering the dICCcopp dt defined in Table 7 while maintaining the required tolerances also defined in Table 7 Failure to meet these specifications can result in timing violations during sag or a reduced lifetime of the component during VCCcorg Overshoot The processor requires both high frequency and bulk decoupling on the system motherboard for proper AGTL AGTL bus operation See the AGTL buffer specification in the Intel Pentium II Processor Developer s Manual for more information Also refer to the appropriate platform design guide for recommended capacitor component placement The minimum recommendation for the processor decoupling is listed below capacitors should be placed within the PGA370 socket cavity and mounted on the primary side of the motherboard The capacitors are arranged to minimize the overall inductance between the VCCc ogg and Vss power pins VCCcorg decoupling 4 7 uF capac
93. eady state input voltage must not be above Vss 1 65 V or below VTT 1 65 Table 10 Non AGTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes REF VIL 5 Input Low Voltage 0 150 0 200 V 9 ViLo 5 Input Low Voltage 0 58 0 700 V 5 8 i REF 5 Input High Voltage 0 200 1 5 V 6 9 5 Input High Voltage 2 000 3 18 V 5 8 VoL Output Low Voltage 0 400 V 2 Ron 35 2 D 7 9 All outputs are Output High Voltage 1 5 V open drain loL Output Low Current 9 mA Input Leakage Current 2100 UA 3 6 Output Leakage Current 2100 UA 4 7 NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium processors at all frequencies 2 Parameter measured at 9 mA for use with TTL inputs 3 0 lt VIN 2 5 V 5 4 0 VOUT 2 5 V 5 5 For BCLK specifications refer to Table 24 on page 51 6 0 lt VIN 1 5 V 3 7 0 lt lt 1 5 V 4396 8 Applies to non AGTL signals except BCLK PICCLK and PWRGOOD 9 Applies to non AGTL signals except BCLK PICCLK and PWRGOOD 34 Datasheet Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 11 Non AGTL Signal Group DC Specifications Datasheet Symbol Parameter Min Max Unit Notes REF VIL 5 Input Low Voltage 0 150 0 300 V 7 8 5 Input Low V
94. ers if the charge is large enough i e if the overshoot is great enough Determining the impact of an overshoot undershoot condition requires knowledge of the magnitude the pulse direction and the activity factor AF Permanent damage to the processor is the likely result of excessive overshoot undershoot Violating the overshoot undershoot guideline will also make satisfying the ringback specification difficult When performing simulations to determine impact of overshoot and overshoot ESD diodes must be properly characterized ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection ESD diodes modeled within Intel I O Buffer models do not clamp undershoot or overshoot and will yield correct simulation results If other I O buffer models are being used to characterize the Pentium 111 processor performance care must be taken to ensure that ESD models do not clamp extreme voltage levels Intel I O Buffer models also contain I O capacitance characterization Therefore removing the ESD diodes from an I O Buffer model will impact results and may yield excessive overshoot undershoot Datasheet intel 3 3 2 Note Note 3 3 3 Note Note 3 3 4 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Overshoot Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level VSS overshoot an
95. form at the Processor Pins 3 2 Table 23 Datasheet v3 V4 v2 V1 V5 V3 AGTL AGTL Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate platform design guide Refer to the Intel Pentium II Processor Developer s Manual Order Number 243502 for the AGTL AGTL buffer specification Table 23 provides the AGTL signal quality specifications for the processor for use in simulating signal quality at the processor pins The Pentium III processor for the PGA370 socket maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 25 through Table 27 Figure 17 shows the AGTL AGTL ringback tolerance and Figure 18 shows the overshoot undershoot waveform AGTL Signal Groups Ringback Tolerance Specifications at the Processor Pins Parameter Min Unit Figure Notes a Overshoot 100 mV 17 4 8 Minimum Time at High 0 50 ns 17 p Amplitude of Ringback 200 mV 17 5 6 7 8 Final Settling Voltage 200 mV 17 8 5 Duration of Squarewave Ringback N A ns 17 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium processors frequencies 2 Specifications are for the edge rate of 0 3 0 8V ns See Figure 17 for the generic waveform 3 All values specified
96. h PICCLK APIC I O Always Datasheet
97. he signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state The figure below illustrates the relationship of PWRGOOD to other system signals PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 19 and be followed by a 1 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation 4 0 yo The REQ 4 0 Request Command signals must connect the appropriate pins of all processor system bus agents They are asserted by the current bus owner over two clock cycles to define the currently active transaction type RESET Asserting the RESET signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after and CLK have reached their proper specifications On observing active RESET all processor system bus agents will deassert their outputs within two clocks A number of bus signals are sampled at the active to inactive tr
98. hort circuit to VSS on the processor The combination of opens and shorts defines the voltage required by the processor core The VID pins are needed to cleanly support voltage specification variations on current and future processors VID 3 0 are defined in Table 2 A 1 in this table refers to an open pin a 0 refers to a short to ground The voltage regulator or must supply the voltage that is requested or disable itself To ensure a system is ready for current and future processors the range of values in bold in Table 2 should be supported A smaller range will risk the ability of the system to migrate to a higher performance processor and or maintain compatibility with current processors Datasheet intel Table 2 Note Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Voltage Identification Definition 2 VID3 VID2 VID1 VIDO 1 1 1 1 1 30 1 1 1 0 1 35 1 1 0 1 1 40 1 1 0 0 1 45 1 0 1 1 1 50 1 0 1 0 1 55 1 0 0 1 1 603 1 0 0 0 1 653 0 1 1 1 1 70 0 1 1 0 1 753 0 1 0 1 1 809 0 1 0 0 1 85 3 0 0 1 1 1 90 3 0 0 1 0 1 95 3 0 0 0 1 2 00 3 0 0 0 0 2 053 1 1 1 1 NOTES 1 0 Processor pin connected to Vss 2 1 Open on processor may be pulled up to TTL on baseboard 3 To ensure a system is ready for the Pentium IIl and Celeron processors the val
99. ic Activity Factor Each Table entry is independent of all others meaning that the Pulse Duration reflects the existence of overshoot undershoot events of that magnitude only A platform with an overshoot undershoot that 49 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Note Note 3 3 5 Table 24 50 intel just meets the pulse duration for a specific magnitude where the AF 1 means that there can be NO other overshoot undershoot events even of lesser magnitude note that if AF 1 then the event occurs at all times and no other events can occur Activity factor for signals is referenced to frequency Activity factor for CMOS signals is referenced to PICCLK frequency Reading Overshoot Undershoot Specification Tables The overshoot undershoot specification for the Pentium processor for the PGA370 socket is not a simple single value Instead many factors are needed to determine what the over undershoot specification is In addition to the magnitude of the overshoot the following parameters must also be known the junction temperature the processor will be operating at the width of the overshoot as measured above 1 635 V and the Activity Factor AF To determine the allowed overshoot for a particular overshoot event the following must be done 1 Determine the signal group that particular signal falls into If the signal is an AGTL signal operating with a 100 MHz system bus use
100. if the overshoot undershoot pulse is within specifications Overshoot Undershoot Pulse Duration Pulse duration describes the total time an overshoot undershoot event exceeds the overshoot undershoot reference voltage Vos ref 1 635 V The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration Multiple Overshoot Undershoot events occurring within the same clock cycle must be considered together as one event Using the worst case Overshoot Undershoot Magnitude sum together the individual Pulse Durations to determine the total Overshoot Undershoot Pulse Duration for that total event Activity Factor Activity Factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of an AGTL or a CMOS signal is every other clock an AF 1 indicates that the specific overshoot or undershoot waveform occurs EVERY OTHER clock cycle Thus an AF 0 01 indicates that the specific overshoot or undershoot waveform occurs one time in every 200 clock cycles The specifications provided in Table 25 through Table 27 show the Maximum Pulse Duration allowed for a given Overshoot Undershoot Magnitude at a specif
101. imensions is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin side capacitors will be located on the processor Table 35 includes the measurements for these dimensions in both inches and millimeters 60 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Figure 23 Package Dimensions BOTTOM VIEW TOP VIEW e D be j DI 9 9 8 6 8 8 9 0 6 9 6 8 9 9 6 O 0 0 oo x 45 5 9 0 0 9 92 09 CAPACITOR PLACEMENT a o o a o o e AREA D B2 C2 4 e 19 2000000 9 9 99 x N OOK o N VA 6 DE UNDERFILL AREA i SEATING PLANE 2 1 1 T PIE REFERT Wr G3 TP SIDE VIEW Table 35 Intel Pentium Processor Package Dimensions Millimeters Inches Symbol Minimum Maximum Notes Minimum Maximum Notes A1 0 787 0 889 0 031d 0 035 A2 1 000 1 200 0 039 0 047 B1 11 226 11 329 0 442 0 446 B2 9 296 9 398 0 366 0 370 C1 23 495 max 0 925 max C2 21 590 max 0 850 max D 49 428 49 632 1 946 1 954 D1 45 466 45 974 1 790 1 810 G1 0 000 17 780 0 0 700 G2 0 000 17 780 0 0 700 G3 0 000 0 889 0 0 035 H 2 540 Nominal 0 100 Nominal 3 048 3 302 0 120 0 130 0 431 0 483 Pin Diameter 0 017 0 019 Pin TP 0 508 Diametric True Position Pin to Pin 0 020 Diamet
102. in Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Datasheet Revision 8 Product Features m Available in 1 13 GHz 1B GHz 933 866 m Dynamic execution micro architecture 800EB 733 667 600EB and 533EB MHz Intel Processor Serial Number for 133 MHz system bus or m Power Management capabilities m Available in 1 10 GHz 1 GHz 900 850 800 750 700 650 600E 550E and 500 e a M MHZ for a 100 MHz system bus Multiple low power states m System bus frequency at 100 MHz and m Optimized for 32 bit applications running on 133 MHz E denotes support for advanced 32 bit operating systems 2 KG Flip Chip Pin Grid Array FC PGA FC PGA2 153 MHzs bus where a y processors deliver high performance with rm improved handling protection and socketability of 1 foreach ling item m Integrated high performance 16 KB instruction Available in versions that incorpore and 16 KB data nonblocking level one cache 256 KB Advanced Transfer Cache on die 256 KB Integrated Full Speed level two cache full speed Level 2 L2 cache with Error allows for low latency on read store operations Correcting Code ECC m Double Quad Word Wide 256 bit cache data m Dual Independent Bus DIB architecture bus provides extremely high throughput on Separate dedicated external System Bus and read store operations dedicated internal high speed cache bus m 8 way cach
103. ithin the static voltage specification within 100 us after a transient event see the VRM 8 4 DC DC Converter Design Guidelines for further details 7 should be generated from VTT by a voltage divider of 1 resistors 1 matched resistors Refer to the Intel Pentium II Processor Developer s Manual for more details on VREF 8 Maximum ICC is measured at VCC typical voltage and under a maximum signal loading conditions 9 Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage at maximum current output is no greater than the nominal i e typical voltage level of VccconE In this case the maximum current level for the regulator IcccgRE REG can be reduced from the specified maximum current max and is calculated by the equation Icccong X sTATIC TOLERANCE 10 The current specified is the current required for a single processor A similar amount of current is drawn through the termination resistors on the opposite end of the AGTL bus unless single ended termination is used see Section 2 1 11 The current specified is also for AutoHALT state 12 Maximum values are specified by design characterization at nominal 13 Based on simulation and averaged over the duration of any change in current Use to compute the maximum in
104. itors in a 1206 package 2 decoupling 0 1 uF capacitors in 0603 package 3 decoupling 0 1 uF and 0 001 uF capacitors in 0603 package placed near the Vpgp pins For additional decoupling requirements please refer to the appropriate platform design guide for recommended capacitor component value quantity and placement Processor System Bus Clock and Processor Clocking The BCLK input directly controls the operating speed of the system bus interface All AGTL AGTL system bus timing parameters are specified with respect to the rising edge of the BCLK input The Coppermine T processor will implement an auto detect mechanism that will let the processor use either single ended or differential signaling for the system bus and processor clocking The processor checks to see if the signal on pin Y33 is toggling If this signal is toggling then the processor operates in differential mode Refer to Figure 6 for a differential clocking example Resistor values and clock topology are listed in the appropriate platform design guide for a differential implementation 19 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel Figure 6 2 5 1 2 6 20 Note Note Note References to BCLK throughout this document will also imply to its complement signal BCLK in differential implementations and when noted otherwise For a differential clock input all AGTL system bus timing parameters are s
105. kage The FC PGA processor markings are visible after installation of the fan heatsink due to notched sides of the heatsink base see Figure 34 The boxed processor fan heatsink is also asymmetrical in that the mechanical step feature see Figure 33 must sit over the socket s cam The step allows the heatsink to securely interface with the processor in order to meet thermal requirements Note The heatsink airflow keepout zones found in Figure 35 refer specifically to the boxed processor s active fan heatsink This does not reflect the worst case dimensions that may exist with other third party passive or active fan heatsinks The Pentium III processor is manufactured in two different packages FC PGA and FC PGA2 For specifications on these two packages please see Section 5 0 of this document Not all frequencies of Pentium III processors are offered both packages The thermal solutions for these two packages are incompatible Therefore the thermal solution shipped with each boxed Pentium III processor should only be used with the accompanied processor Figure 33 Dimensions of Mechanical Step Feature in Heatsink Base Datasheet 0 043 E 0 472 81 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 6 1 2 Boxed Processor Heatsink Weight The boxed processor thermal cooling solution will not weigh more than 180 grams Figure 34 Dimensions of Notches in Heatsink Base 6 2
106. l Minimum Maximum Notes Minimum Maximum Notes Pin TP 0 508 Diametric True Position Pin to Pin 0 020 Diametric True Position Pin to Pin NOTE Capacitors will be placed on the pin side of the FC PGA package in the area defined by G1 G2 and G3 This area is a keepout zone for motherboard designers For Table 38 the following apply 1 Itis not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions 2 Parameters assume uniformly applied loads Table 38 Processor Case Loading Parameters for FC PGA2 Transient Dynamic Static Parameter max max max Unit IHS Surface 200 200 100 Ibf IHS Edge 125 N A N A Ibf IHS Corner 75 N A N A Ibf NOTES 1 Transient loading refers to a one time short duration loading such as during heatsink installation 2 Dynamic loading refers to a shock load 3 This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface Please see socket manufacturer s force loading specification also to ensure compliance Maximum static loading listed here does not account for the maximum reaction forces on the socket tabs or pins Designs must ensure that the socket can withstand this force 4 Figure 25 FC PGA2 Flatness Specification 0 05 0 203 A 2 0 52 Note Flatness specifications in
107. lIntertace err rn 59 Intel Pentium Processor Package 5 61 Processor Die Loading Parameters for FC PGA 62 Package Dimensions for Intel Pentium Processor FC PGA2 Package 63 Processor Case Loading Parameters for FC PGA2 64 Signal Listing in Order by Signal 69 Signal Listing in Order by Pin 74 Datasheet intel Datasheet Pentium Ill Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Fan Heatsink Power and Signal 84 Signal Descriptio Ni Feet eaa oto het end 85 Output Signals I eed ie dede pee oe 92 Iiei Es le Pm 92 Input Output Signals Single Driver essen 94 Input Output Signals Multiple Driver 94 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 1 0 Introduction The Intel Pentium III processor for the PGA370 socket is the next member of the P6 family in the Intel IA 32 processor line and hereafter will be referred to as the Pentium III processor or simply the processor The processor uses the same core and offers the same performance as the Pentium lll processor for the SC242 connector but utilizes
108. le 29 3 4 3 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Ringback Specification Ringback refers to the amount of reflection seen after a signal has switched The ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value See Figure 20 for an illustration of ringback Excessive ringback can cause false signal detection or extend the propagation delay The ringback specification applies to the input pin of each receiving agent Violations of the signal ringback specification are not allowed under any circumstances for non AGTL non AGTL signals Ringback can be simulated with or without the input protection diodes that can be added to the input buffer model However signals that reach the clamping voltage should be evaluated further See Table for the signal ringback specifications for signals for simulations at the processor pins Signal Ringback Specifications for Non AGTL Signal Simulations at the Processor Pins x Maximum Ringback s Input Signal Group Transition with Input Diodes Present Unit Figure Non AGTL Signals 2 0 1 ner 0 200 V 20 Non AGTL Signals 2 120 ner 0 200 V 20 PWRGOOD 0 1 2 00 V 20 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium processor frequencies 2 Non AGTL signals except PWRGOOD Signal Ringb
109. m bus agents Datasheet Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 42 Signal Description Sheet 7 of 8 Datasheet Name Type Description RSP The RSP Response Parity signal is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect the appropriate pins of all processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity RTTCTRL The RTTCTRL input signal provides AGTL termination control The Pentium III processor samples this input to sense the presence of motherboard AGTL termination See the platform design guide for implementation details SLEWCTRL The SLEWCTRL input signal provides AGTL slew rate control The Pentium processor samples this input to determine the slew rate for AGTL signals when it is the driving agent See the platform design guide for implementation details SLP The SLP Sleep signal when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked
110. me that the power is uniformly distributed across the entire die area 57 Pentium Processor for the PGA370 Socket at 500 MHz to 1 10 GHz Figure 21 Processor Functional Die Layout for FC PGA Table 32 C Cache Area Product Label A Die Area B Core Area 63 of die area Processor Functional Die Layout for FC PGA CPUID A Die Area cm B Core Area cm C Cache Area cm 0683H 1 046 0 726 0 320 0686H 0 900 0 642 0 258 068AH 0 947 0 642 0 305 4 3 Note 58 Thermal Diode The Pentium III processor for the PGA370 socket incorporates an on die diode that may be used to monitor the die temperature junction temperature A thermal sensor located on the motherboard or a stand alone measurement kit may monitor the die temperature of the processor for thermal management or instrumentation purposes Table 33 and Table 34 provide the diode parameter and interface specifications For more information please refer to the document Intel Pentium Processor in the FC PGA2 Package Thermal Design Guide The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the temperature of the hottest location on the die This is due to inaccuracies in the thermal sensor on die temperature gradients between the location of the thermal diode and the hottest location on the die at a given point in time and time based variations in the die temperatur
111. motherboard See the design guide for implementation details 87 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 42 Signal Description Sheet 4 of 8 Name Type Description CPUPRES The CPUPRES signal is defined to allow a system design to detect the presence of a terminator device or processor in a PGA370 socket Combined with the VID combination of VID 3 0 1111 see Section 2 6 a system can determine if a socket is occupied and whether a processor core is present See the table below for states and values for determining the presence of a device PGA370 Socket Occupation Truth Table Signal Value Status 0 Anything other than 1111 CPUPRES 0 Terminator device installed in the VID 3 0 1111 70 socket i e no core present CPUPRES 1 VID 3 0 Any value CPUPRES VID 3 0 Processor core installed in the PGA370 Socket PGA370 socket not occupied D 63 0 y o The D 63 0 Data signals are the data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer DBSY yo The DBSY Data Bus Busy signal is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use The data bus is released after
112. n FC PGA2 contains an Integrated Heat Spreader IHS to spread out the heat generated from the die See Section 1 1 1 for a complete terminology listing The processor utilizes a PGA370 socket for installation into the motherboard Details on the socket are available in the 370 Pin Socket PGA370 Design Guidelines Note Figure 23 and Figure 24 the following apply 1 Unless otherwise specified the following drawings are dimensioned in inches 2 All dimensions provided with tolerances are guaranteed to be met for all normal production product 3 Figures and drawings labeled as Reference Dimensions are provided for informational purposes only Reference dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied Reference dimensions are NOT checked as part of the processor manufacturing Unless noted as such dimensions in parentheses without tolerances are reference dimensions 4 Drawings are not to scale The following figure with package dimensions is provided to aid in the design of heatsink and clip solutions as well as demonstrate where pin side capacitors will be located on the processor Table 35 includes the measurements for these dimensions in both inches and millimeters Figure 22 FC PGA and FC PGA2 Package Types 2 5 1 FC PGA Mechanical Specifications The following figure with package d
113. nd Level L2 Cache Implementation Processor Processor Core Core Intel Pentium SECC2 Processor Intel Pentium 1 FC PGA Processor Datasheet intel 1 1 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Terminology In this document a symbol after a signal name refers to an active low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when FLUSH is low a flush has been requested When NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 refers to a hex A and D 3 0 also refers to a hex A H High logic level L Low logic level The term system bus refers to the interface between the processor system core logic a k a the chipset components and other bus agents Package and Processor Terminology The following terms are used often in this document and are explained here for clarification Pentium lll processor The entire product including all internal components PGA370 socket 370 pin Zero Insertion Force ZIF socket which a FC PGA or PPGA packaged processor plugs into FC PGA Flip Chip Pin Grid Array The packag
114. nless otherwise noted all specifications in this table apply to all Pentium III processors frequencies 2 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK PICCLK signal can dip back to after passing the rising or VIL falling voltage limits This specification is an absolute value Table 22 BCLK PICCLK Signal Quality Specifications for Simulation at the Processor Pins in a Differential Clock Platform for AGTL T Parameter Min Nom Max Unit Figure Notes V1 PICCLK ViL 0 40 V 16 V2 PICCLK ViH 1 60 V 16 V3 PICCLK Absolute Voltage 0 4 24 16 Range V4 PICCLK Rising Edge Ringback 1 60 V 16 2 V5 PICCLK Falling Edge Ringback 0 40 V 16 2 NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium processors that support the AGTL specification Refer to the Inte Pentium IIl Processor Specification Update for a complete listing on the processors that support the AGTL specification 46 Datasheet Intel Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 2 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK PICCLK signal can dip back to after passing the rising or VIL falling voltage limits This specification is an absolute value Figure 16 BCLK PICCLK Generic Clock Wave
115. o ensure compliance Datasheet intel 5 1 1 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz FC PGA2 Mechanical Specifications The following figure is provided to aid in the design of heatsink and clip solutions Also it is used to demonstrate where pin side capacitors will be located on the processor Table 31 includes the measurements for these dimensions in both inches and millimeters Figure 24 Package Dimensions for FC PGA2 Table 37 Datasheet BOTTOM VIEW CAPACI TOR PLACEMENT AREA GI HS LID SEALAN 1 SEATING P E 1 SIDE VIEW Package Dimensions for Intel Pentium Processor FC PGA2 Package Millimeters Inches Symbol Minimum Maximum Notes Minimum Maximum Notes A1 2 266 2 690 0 089 0 106 A2 0 980 1 180 0 038 0 047 B1 30 800 31 200 1 212 1 229 B2 30 800 31 200 1 212 1 229 C1 33 000 max 1 299 max C2 33 000 max 1 299 max D 49 428 49 632 1 946 1 954 D1 45 466 45 974 1 790 1 810 G1 0 000 17 780 0 000 0 700 G2 0 000 17 780 0 000 0 700 G3 0 000 0 889 0 000 0 035 H 2 540 Nominal 0 100 Nominal 3 048 3 302 0 120 0 130 0 431 0 483 0 017 0 019 63 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz In Table 37 Package Dimensions for Intel Pentium IIl Processor FC PGA2 Package Millimeters Inches Symbo
116. of signals with the exception of 51 or RESET are allowed on the system bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant State If RESET is driven active while the processor is in the Sleep State the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the reset sequence Datasheet intel 2 2 6 2 2 7 2 3 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz While in the Sleep state the processor is capable of entering its lowest power state the Deep Sleep state by stopping the BCLK input see Section 2 2 6 Once in the Sleep or Deep Sleep states the SLP pin can be deasserted if another asynchronous system bus event occurs The 51 pin has a minimum assertion of one BCLK period Deep Sleep State State 6 The Deep Sleep state is the lowest power state the processor can enter while maintaining context The Deep Sleep state is entered by stopping the BCLK input after the Sleep state was entered from the assertion of the SLP pin The processor is in Deep Sleep state immediately after BCLK is stopped
117. oltage 0 58 0 700 V 4 6 REF 5 Input High Voltage 0 200 1 5 V 5 7 5 Input High Voltage 2 000 3 18 V 4 6 VoL Output Low Voltage 0 300 V 2 Ron 35 2 5 7 All outputs are VOH Output High Voltage 1 5 V open drain loL Output Low Current 9 mA Input Leakage Current 100 3 5 Output Leakage Current 2100 UA 3 5 NOTES 1 Unless otherwise noted all specifications in this table apply to Pentium processors at all frequencies 2 Parameter measured at 9 mA for use with TTL inputs 3 0 lt VIN 2 5 V 5 0 x VOUT x 2 5 5 4 For BCLK specifications refer to Table 24 on page 51 5 0 VIN lt 1 5 V 4396 0 VOUT lt 1 5 V 4396 6 Applies to signals except BCLK PICCLK and PWRGOOD 7 Applies to non AGTL signals except BCLK PICCLK and PWRGOOD 8 For Coppermine T differential clocking the input low voltage is VCMOS REF 0 300 V 35 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 2 11 Table 12 Table 13 36 INTel AGTL AGTL System Bus Specifications It is recommended that the bus be routed in daisy chain fashion with termination resistors to VTT These termination resistors are placed electrically between the ends of the signal traces and the VTT voltage supply and generally are chosen to approximate the system platform impedance The valid high and low levels are determined by the input buffers using
118. on is enabled during power on configuration and BINIT is sampled asserted all bus state machines are reset and any data which was in transit is lost All agents reset their rotating ID for bus arbitration to the state after Reset and internal count information is lost The L1 and L2 caches are not affected If BINIT observation is disabled during power on configuration a central agent may handle an assertion BINIT as appropriate to the error handling architecture of the system BNR y o The BNR Block Next Request signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wire OR signal which must connect the appropriate pins of all processor system bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BP 3 2 yo The BP 3 2 Breakpoint signals are outputs from the processor that indicate the status of breakpoints 1 0 y o The BPM 1 0 Breakpoint Monitor signals are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performanc
119. on on the these signals The BRO pin is the only BREQ signal that is bidirectional See Section 7 0 for more information The internal BREQ signals are mapped onto the BR 1 0 pins after the agent ID is determined These signals are specified for 1 5 V for the Pentium processor operation These signals are 2 5 V tolerant 15 the power supply for the processor core and is described in Section 2 6 VID 3 0 is described in Section 2 6 VTT is used to terminate the system bus and generate on the motherboard Vss is system ground VCC4 5 VCC2 5 are described in Section 2 3 BSEL 1 0 is described in Section 2 8 2 and Section 7 0 All other signals are described in Section 7 0 RESET must always be terminated to on the motherboard on die termination is not provided for this signal This signal is not supported by all processors Refer to the Pentium IIl Processor Specification Update for a complete listing of processors that support this pin This signal is used to control the value of the processor on die termination resistance Refer to the platform design guide for the recommended pull down resistor value These signals are also classified as AGTL Refer to the Pentium IIl Processor Specification Update for a complete listing of processors that support the AGTL and AGTL specifications 10 For differential clock systems the CLKREF pin becomes BCLK
120. opriate pins of all processor system bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST LINT 1 0 The LINT 1 0 Local APIC Interrupt signals must connect the appropriate pins of all APIC Bus agents including all processors and the core logic or APIC component When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK Vo The LOCK signal indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor system bus it will wait until it observes deasserted This enables symmetric agents to retain ownership of the processor system bus throughout the bus locke
121. opriate platform design guide for connectivity and to the Pentium IIl processor Specification Update for a complete listing of processors that support the new pinout definition 13 and differential clock platforms this pin is defined as BCLK 79 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 6 0 Boxed Processor Specifications Note The Pentium III processor for the PGA370 socket is also offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from motherboards and standard components The boxed Pentium lll processor for the PGA370 socket will be supplied with an unattached fan heatsink This section documents motherboard and system requirements for the fan heatsink that will be supplied with the boxed Pentium III processor This section is particularly important for OEMs that manufacture motherboards for system integrators Unless otherwise noted all figures in this section are dimensioned in inches Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all heatsinks It is the system designer s responsibility to consider their proprietary solution when designing to the required keep out zone on their system platform and chassis Refer to the Intel Pentium IIl Processor Thermal Mechanical Functional Specifications fo
122. ors that support both VRM specifications 21 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 2 7 2 8 22 Processor System Bus Unused Pins RESERVED pins must remain unconnected unless specifically noted Connection of these pins to VSS VTT or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 5 4 for a pin listing of the processor and the location of each RESERVED pin PICCLK must be driven with a valid clock input and the PICD 1 0 signals must be pulled up to even when the APIC will not be used A separate pull up resistor must be provided for each PICD signal For reliable operation always connect unused inputs or bidirectional signals to their deasserted signal level The pull up or pull down resistor values are system dependent and should be chosen such that the logic high and logic low requirements met See Table 10 and Table 11 for DC specifications of non AGTL AGTL signals Unused AGTL AGTL inputs must be properly terminated to VTT on PGA370 socket motherboards which support the Celeron and the Pentium processors For designs that intend to only support the Pentium III processor unused AGTL inputs will be terminated by the processor s on die termination resistors and thus do not need to be terminated on the motherboard However
123. ower Other AL25 HIT AGTL I O AJ21 Power Other 127 DBSY AGTL I O AJ23 GND Power Other AL29 THERMDN Power Other AJ25 Power Other AL31 THERMDP Power Other AJ27 GND Power Other AL33 TCK TAP Input AJ29 Power Other AL35 VIDO Power Other AJ31 BSEL1 Power Other AL37 VID2 Power Other AJ33 BSELO Power Other 29 Reserved Reserved for future use AJ35 SMI CMOS Input AM4 VCCcoRE Power Other AJ37 VID3 Power Other AM6 GND Power Other AK2 VcCconE Power Other 8 Power Other AK4 GND Power Other AM10 GND Power Other AK6 A28 AGTL I O 12 VCCconE Power Other AK8 A3 AGTL I O 14 GND Power Other AK10 11 AGTL I O AM16 Power Other AK12 Power Other AM18 GND Power Other 14 AGTL AM20 Power Other AK16 VTT Power Other AM22 GND Power Other AK18 REQO AGTL I O 24 Power Other AK20 LOCK AGTL I O AM26 GND Power Other AK22 Vngr7 Power Other 28 Power Other 24 AERR AGTL I O 30 GND Power Other AK26 PWRGOOD CMOS Input 2 VCCconE Power Other AK28 RS2 AGTL Input 34 GND Power Other AK30 Reserved Reserved for future use AMS6 VID1 Power Other AK32 TMS TAP Input AN3 GND Power Other AK34 Power Other AN5 A12 AGTL I O AK36 GND Power Other AN7 16 AGTL I O AL1 GND Power Other AN9 AGTL I O AL3 GND Power Other
124. pecified with respect to the crossing point of the rising edge of the BCLK input and the falling edge of the BCLK input See the P6 Family of Processors Hardware Developer s Manual for further details For differential clocking the reference voltage of the BCLK in the P6 Family of Processors Hardware Developer s Manual is re defined as the crossing point of the BCLK and the BCLK inputs Differential Clocking Example BCLK Clock Processor or Driver Chipset BCLK Mixing Processors of Different Frequencies In two way MP multi processor systems mixing processors of different internal clock frequencies is not supported and has not been validated Pentium III processors do not support a variable multiplier ratio therefore adjusting the ratio setting to a common clock frequency is not valid However mixing processors of the same frequency but of different steppings is supported Details on support for mixed steppings is provided in the Pentium III Processor Specification Update Not all Pentium processors for the PGA370 socket are validated for use in dual processor DP systems Refer to the Pentium III Processor Specification Update to determine which processors are DP capable Voltage Identification There are four voltage identification pins on the PGA370 socket These pins can be used to support automatic selection of voltages These pins are not signals but are either an open circuit or a s
125. r for the PGA370 Socket at 500 MHz to 1 13 GHz Table 39 Signal Listing in Order by Table 39 Signal Listing in Order by Signal Name Continued Signal Name Continued E Pin Name Signal Group Signal Group F12 D27 AGTL I O C31 DEP1 AGTL UO A5 028 AGTL I O DEP2 AGTL UO A3 D29 AGTL I O A31 DEP3 AGTL UO J3 D30 AGTL I O E31 DEP4 AGTL UO C5 D31 AGTL I O C29 DEP5 AGTL UO F6 D32 AGTL I O E29 DEP6 AGTL UO C1 D33 AGTL I O A29 DEP7 AGTL UO C7 D34 AGTL I O AN27 DRDY AGTL I O B2 D35 AGTL I O AG1 EDGCTRL Power Other C9 036 AGTL I O AC35 FERR CMOS Output A9 D37 AGTL I O AE37 FLUSH CMOS Input D8 038 AGTL I O AM22 GND Power Other D10 039 AGTL I O 26 GND Power Other C15 D40 AGTL I O AM30 GND Power Other D14 D41 AGTL I O AM34 GND Power Other D12 D42 AGTL I O AM6 GND Power Other A7 AGTL I O AN3 GND Power Other A11 D44 AGTL I O B12 GND Power Other C11 D45 AGTL I O B16 GND Power Other A21 D46 AGTL I O B20 GND Power Other A15 D47 AGTL I O B24 GND Power Other A17 048 AGTL I O 28 GND Power Other C13 D49 AGTL I O B32 GND Power Other C25 D50 AGTL I O B4 GND Power Other A13 D51 AGTL I O B8 GND Power Other D16 D52 AGTL I O D18 GND Power Other A23 D53 AGTL I O D2 GND Power Other C21 D544t AGTL I O D22 GND Power Other C1
126. r further guidance Contact your local Intel Sales Representative for this document Figure 32 Conceptual Boxed Intel Pentium Processor for the PGA370 Socket 6 1 80 FAN CABLE FC PGA PACKAGE SOCKET Mechanical Specifications for the Boxed Intel Pentium 111 Processor Boxed Processor Thermal Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium III processor fan heatsink in the FC PGA package The boxed processor in the FC PGA package ships with an un attached fan heatsink Figure 32 shows a mechanical representation of the boxed Pentium III processor for the PGA370 socket in the Flip Chip Pin Grid Array FC PGA package Section 5 3 of this document also shows the recommended mechanical keepout zones for the boxed processor fan heatsink assembly Figure 30 and Figure 31 show the required keepout dimensions for the boxed processor thermal solution The cooling fin orientation on the heatsink relative to the PGA 370 socket is subject to change Contact your local Intel Sales Representative for documentation specific to the boxed fan heatsink orientation relative to the PGA 370 socket Also contact your Intel representative for specific fan heatsink dimensions Datasheet intel Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz The fan heatsink is designed to allow visibility of the FC PGA processor markings located on top of the pac
127. r the PGA370 Socket at 500 MHz to 1 13 GHz Table 5 Frequency Select Truth Table for BSEL 1 0 2 9 26 Table 6 BSEL1 BSELO Frequency 0 0 66 MHz unsupported 0 1 100 MHz 1 0 Reserved 1 1 133 MHz Maximum Ratings Table 6 contains processor stress ratings only Functional operation at the absolute maximum and minimum is not implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating conditions are given in the AC and DC tables in Section 2 10 through Section 2 12 Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes TSTORAGE Processor storage temperature 40 85 C Veccore and Processor core voltage and termination 0 5 24 VTT supply voltage with respect to Vss AGTL buffer input voltage VTT 2 18 2 18 V 1 2 1 5 CMOS buffer DC input voltage with respect 2 18 2 18 V 1 2 3 to Vss Vincmos2 5 CMOS buffer DC input voltage with respect 0 58 3 18 4 to Vss Max VID pin current 0 3 mA ICPUPRES Max CPUPRES pin current mA NOTES 1 Input voltage can never exceed Vss
128. ric True Position Pin to Pin NOTE Capacitors will be placed on the pin side of the FC PGA package in the area defined by G1 G2 and G3 This area is a keepout zone for motherboard designers Datasheet 61 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 62 Table 36 The bare processor die has mechanical load limits that should not be exceeded during heat sink assembly mechanical stress testing or standard drop and shipping conditions The heatsink attach solution must not induce permanent stress into the processor substrate with the exception of a uniform load to maintain the heatsink to the processor thermal interface The package dynamic and static loading parameters are listed in Table 36 For Table 36 the following apply 1 It is not recommended to use any portion of the processor substrate as a mechanical reference or load bearing surface for thermal solutions 2 Parameters assume uniformly applied loads Processor Die Loading Parameters for FC PGA 1 x 2 5 Added Parameter Dynamic max Static max Unit Notes Silicon Die Surface 200 50 Ibf 3 Silicon Die Edge 100 12 Ibf 3 NOTES 1 This specification applies to a uniform and a non uniform load 2 This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface 3 Please see socket manufacturer s force loading specification also t
129. s timing and Table 20 covers power on timing All processor system bus AC specifications for the AGTL AGTL signal group are relative to the rising edge of the BCLK input All AGTL AGTL timings are referenced to for both 0 and P logic levels unless otherwise specified The timings specified in this section should be used in conjunction with the I O buffer models provided by Intel These I O buffer models which include package information are available for the Pentium processor in the FC PGA package in Viewlogic XTK XNS model format formerly known as QUAD format and IBIS 3 1 format as the Pentium III Processor for the 70 Socket Buffer Models Electronic Format AGIL and AGTL layout guidelines are also available in the appropriate platform design guide Care should be taken to read all notes associated with a particular timing parameter Buffer Model An electronic copy of the Buffer Model for the and CMOS signals is available at Intel s Developer s Website http developer intel com The model is for use in single processor designs and assumes the presence of motherboard values as described in Table 12 on page 36 System Bus AC Specifications SET Clock 2 Parameter Min Nom Max Unit Figure Notes 100 00 System Bus Frequency MHz 4 133 33 10 4 1 T1 BCLK Period n ns 9 e TE 7 5 4 5 11 2250 6 7 10 T2 BCLK Period Stabilit S
130. se processors is generated from the core area shown in Figure 21 6 TJUNCTION offset values do not include any thermal diode kit measurement error Diode kit measurement error must be added to the TJUNCTION offset value from the table as outlined in the Inte Pentium III processor Thermal Metrology for CPUID 068h Family Processors Order Number 245301 Intel has characterized the use of the Analog Devices AD1021 diode measurement kit and found its measurement error to be 1 7 This specification only applies to 1B GHz S Spec SLAWM This part has a VID request of 1 70 V however the processor should be supplied 1 76 V at the PGA Vcc pins by the VRM Voltage Regulator Module or by the voltage regulator circuit 8 This specification applies to processors with CPUID 068AH 1B GHz exists in both FC PGA and FC PGA2 packages 9 This specification applies to processors with CPUID 0686H 10 Tjunction minimum specification is 0 C Table 31 provides the thermal design power dissipation and maximum temperatures for the Pentium lll processor for the FC PGA2 package Systems should design for the highest possible processor power even if a processor with a lower thermal dissipation is planned A thermal solution should be designed to ensure the case temperature never exceeds these specifications Intel Pentium Processor for the FC PGA2 Package Thermal Design Power 1 Processor Ur on System Bus
131. signals please refer to Table 17 and Figure 13 Note For Figure 9 through Figure 15 the following apply 1 Figure 9 through Figure 15 are to be used in conjunction with Table 14 through Table 20 2 All AC timings for the AGTL signals at the processor pins are referenced to the BCLK rising edge at 1 25 V AGTL signal timings address bus data bus etc are referenced at 1 00 V at the processor pins 3 AC timings for the APIC I O signals at the processor pins are referenced to the PICCLK rising edge at 1 25 V APIC UO signal timings are referenced at 0 75 V at the processor pins 4 AIL AC timings for the TAP signals at the processor pins are referenced to the TCK rising edge at 0 75 V TAP signal timings 5 TDI etc are referenced at 0 75 V at the processor pins Figure 9 Generic Clock Waveform 1 BCLK vL Vcross Tan 1 BCLK Period NOTE Single Ended clock uses BCLK only Differential clock uses and BCLK Datasheet 41 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Figure 10 BCLK PICCLK and TCK Generic Clock Waveform Vih diff Vringback rise 4Z1 v2 v3 V1 OV Vringback fall ee ee Vil diff T5 T25 T34 Rise Time T6 T26 135 Fall Time T T T T3 T23 T32
132. sked floating point error FERR is similar to the ERROR signal on the Intel387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting 88 Datasheet Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 42 Signal Description Sheet 5 of 8 Name Type Description FLUSH When the FLUSH input signal is asserted processors write back all data in the Modified state from their internal caches and invalidate all internal cache lines At the completion of this operation the processor issues a Flush Acknowledge transaction The processor does not cache any new data while the FLUSH signal remains asserted FLUSH is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding Write bus transaction On the active to inactive transition of RESET each processor samples FLUSH to determine its power on configuration See the P6 Family of Processors Hardware Developer s Manual for details HIT HITM Vo Vo The HIT Snoop Hit and HITM Hit Modified signals convey transaction snoop operation results and must connect the appropriate pins of all processor system bus agents Any such agent may assert both and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HI
133. solder side of the motherboard Datasheet intel Figure 18 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Maximum Acceptable AGTL Overshoot Undershoot Waveform Time Dependent Converted Undershoot Overshoot Waveform 2 18V 2 08V 1 98V 1 88V 1 635V Overshoot Magnitude Undershoot Magnitude Vss y Overshoot Magnitude Signal Vss Undershoot Magnitude Te Signal Time Dependent Undershoot Figure 19 Maximum Acceptable AGTL Overshoot Undershoot Waveform Time dependent Overshoot ins Iv ns v Time dependent Undershoot Datasheet 53 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz ntel 3 4 Non AGTL Non AGTL Signal Quality Specifications and Measurement Guidelines There are three signal quality parameters defined for non AGTL signals overshoot undershoot ringback and settling limit All three signal quality parameters are shown in Figure 20 for the non signal group Figure 20 Non AGTL Non AGTL Overshoot Undershoot Settling Limit and Ringback 1 3 4 1 54 Note Settling Limit Overshoot Vui Rising Edge Ringback 8 Falling Edge Ringback Settling Limit Mo Vss NOTES 1 Vy 1 5 V for all non AGTL signals except for BCLK PICCLK and PWRGOOD Vy 2 5 V for BCLK PICCLK PWRGOOD BCLK and PIC
134. sor Power Distribution Guidelines 245085 AP 909 inte Processor Serial Number 245125 Inte Architecture Software Developer s Manual 243193 Volume I Basic Architecture 243190 Volume Instruction Set Reference 243191 Volume System Programming Guide 243192 P6 Family of Processors Hardware Developer s Manual 244001 Pentium II Processor Developer s Manual 243502 Pentium III Processor Datasheet for SECC2 244452 Pentium Processor Datasheet for PGA370 245264 Pentium III Processor Specification Update 244453 Inte Celeron Processor Datasheet 243658 Inte Celeron Processor Specification Update 243748 370 Pin Socket PGA370 Design Guidelines 244410 PGA370 Heat Sink Cooling in MicroATX Chassis 245025 Inte 810E Chipset Platform Design Guide 290675 Inte 815 B step Chipset Platform Design Guide Inte 815E Chipset Platform Design Guide 298234 Inte 820 Chipset Platform Design Guide 290631 Inte 840 Chipset Platform Design Guide 298021 CK98 Clock Synthesizer Driver Design Guidelines 245338 Inte 810E Chipset Clock Synthesizer Driver Specification 3 VRM 8 4 DC DC Converter Design Guidelines 245335 Pentium III Processor for the PGA370 Socket Buffer Models XTK XNS Format Pentium Pro Processor BIOS Writer s Guide Extensions to the Pentium Pro Processor BIOS Writer s Guide rev 3 7 Pentium IIl Thermal Mechanical Solution Functional Guidelines 245241 Intef Pentium III Processor in the FC PGA2 Package Thermal Design Guide 2
135. sor for the PGA370 Socket at 500 MHz to 1 13 GHz For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 35 illustrates an acceptable airspace clearance for the fan heatsink It is also recommended that the air temperature entering the fan be kept below 45 C Meeting the processor s temperature specification is the responsibility of the system integrator The processor temperature specification is found in Section 4 0 of this document Figure 35 Thermal Airspace Requirement for all Boxed Intel Pentium Processor Fan 6 3 6 3 1 Datasheet Heatsinks in the PGA370 Socket Measure ambient temperature 0 3 above center of fan inlet 0 20 Min 0 20 Min Air Space Air Space Fan Heatsink Processor PGA 370 Socket Electrical Requirements for the Boxed Intel Pentium Processor Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable is attached to the fan and will draw power from a power header on the motherboard The power cable connector and pinout are shown in Figure 36 Mo
136. sor system bus agents must receive this signal to drive their outputs and latch their inputs on BCLK BCLK the BCLK rising edge All external timing parameters are specified with respect to the BCLK signal Datasheet 85 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz 86 Table 42 Signal Description Sheet 2 of 8 Name Type Description BERR yo The Bus Error signal is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor system bus agents and must connect the appropriate pins of all such agents if used However Pentium processors do not observe assertions of the BERR signal BERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted optionally for internal errors along with IERR Asserted optionally by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction BINIT y o The BINIT Bus Initialization signal may be observed and driven by all processor system bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT observati
137. ssor Symbol Parameter Min Typ Max Unit Notes Core Freq Icc for 250 mA CLKREF voltage supply current 60 HA Termination voltage 27 A 10 supply current Icc Stop Grant for 6 9 A 8 11 processor core Icc Sleep for processor 6 9 A 8 core Icc Deep Sleep for processor core 66 2 K Power supply current dleccone At Siew rate 240 A us 12 13 14 Termination current 12 13 See slew rate 8 Alus Table 12 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All specifications in this table apply only to the Pentium processor For motherboard compatibility with the Celeron processor see the Inte Celeron Processor Datasheet 3 VeCcore and Icccore supply the processor core and the on die L2 cache 4 Use the typical voltage specification with the tolerance specifications to provide correct voltage regulation to the processor 5 VTT and Vcc 5 must be held to 1 5 9 while the AGTL bus is active It is required that VTT and Vcc 5 be held to 1 5 3 while the processor system bus is static idle condition The 3 range is the required design target 9 will come from the transient noise added This is measured at the PGA370 socket pins on the bottom side of the baseboard 6 These are the tolerance requirements across a 20 MHz frequency bandwidth measured at the processor socket on the soldered side of the motherboard VcCcore must return to w
138. tables at the end of this section summarize the signals by direction output input and I O 7 1 Alphabetical Signals Reference Table 42 Signal Description Sheet 1 of 8 Name Type Description The A 35 3 Address signals define a 2 byte physical memory address space When ADS is active these pins transmit the address of a transaction when ADS is inactive these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the processor system bus The A 35 3 it yo A 35 24 signals are parity protected by the AP1 parity signal the A 23 3 signals are parity protected by the APO parity signal On the active to inactive transition of RESET the processors sample the A 35 3 pins to determine their power on configuration See the Inte Pentium II Processor Developer s Manual for details If the 20 Address 20 Mask input signal is asserted the processor masks physical address bit 20 A208 before looking up a line in any internal cache before driving a read write transaction on the bus Asserting 20 emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion 20 is only supported in real mode 20 is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding Write bus transaction A20M
139. therboards must provide a matched power header to support the boxed processor Table 41 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE open collector output signal that pulses at a rate of two pulses per fan revolution A motherboard pull up resistor provides VOH to match the motherboard mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the motherboard documentation or on the motherboard Figure 37 shows the recommended location of the fan power connector relative to the PGA370 socket The motherboard power header should be positioned within 4 00 inches lateral from the center of the PGA370 socket 83 Pentium Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Figure 36 Boxed Processor Fan Heatsink Power Cable Connector Description Table 41 Pin Signal 1 GND Straight square pin 3 pin terminal housing with polarizing ribs and friction locking ramp 2 12V 0 100 pin pitch 0 025 square pin width 3 SENSE Waldom Molex P N 22 01 3037 or equivalent Match with straight pin friction lock header on motherboard Waldom Molex
140. ues in BOLD in Table 2 should be supported Note that the 1111 all opens ID can be used to detect the absence of a processor core in a given socket as long as the power supply used does not affect these lines Detection logic and pull ups should not affect VID inputs at the power source see Section 7 0 The VID pins should be pulled up to a TTL compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the VID 3 0 signals The power source chosen must be guaranteed to be stable whenever the supply to the voltage regulator is stable This will prevent the possibility of the processor supply going above the specified in the event of a failure in the supply for the VID lines In the case of DC to DC converter this can be accomplished by using the input voltage to the converter for the VID line pull ups A resistor of greater than or equal to 10 may be used to connect the VID signals to the converter input Note that no changes have been made to the physical connector or pin definitions between the Intel enabled VRM 8 2 and VRM 8 4 specifications 8 5 specification uses five VID pin assignments VID 3 0 25mV and it is not compatible with VRM 8 4 Some Pentium lll processors with CPUID 068xh are capable of supporting both 8 4 and 8 5 specifications Please refer to the Pentium III Specification Update for a listing of process
141. une 2001 Document Number 245264 08 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Pentium IIl processor may contain design defects or errors known as errata which may cause the product to deviate from published specifcations Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which ha
142. ust be accounted for as a component of BCLK timing skew between devices 7 The clock driver s closed loop jitter bandwidth must be set low to allow any PLL based device to track the jitter created by the clock driver The 20 dB attenuation point as measured into a 10 to 20 pF load should be less than 500 kHz This specification may be ensured by design characterization and or measured with a spectrum analyzer See the appropriate clock synthesizer driver specification for details 8 BCLK Rise time is measure between 0 5 2 0 V BCLK fall time is measured between 2 0 0 5 V 9 BCLK high time is measured as the period of time above 2 0 V BCLK low time is measured as the period of time below 0 5 V 10 This specification applies to Pentium processors operating at a system bus frequency of 100 MHz 11 This specification applies to Pentium processors operating at a system bus frequency of 133 MHz Table 15 System Bus Timing Specifications Differential Clock 11 12 133 MHz 100 MHz Parameter Units Notes Min Max Min Max Clock Period Average 7 5 7 7 10 0 10 2 ns 2 9 10 Instantaneous Minimum Clock Period 7 30 9 8 ns 2 9 10 CLK Differential Rise Time 175 550 175 467 ps 1 3 CLK Differential Fall Time 175 550 175 467 ps 1 3 Waveform Symmetry 325 325 ps 4 Differential Cycle to Cycle Jitter 200 200 ps 1 5 Differential Duty Cycle 4596 55 45 55 1 Rising Edge Ring Back 0 35 0 35 V
143. value of the on die is determined by the resistor value measured by the RTTCTRL signal pin See Section 7 0 for more details on the RTTCTRL signal Refer to the recommendation guidelines for the specific chipset processor combination 5 Vngr is generated the motherboard and should be 2 3 VTT 2 nominally Insure that there is adequate decoupling on the motherboard Processor AGTL Bus Specifications 1 2 Symbol Parameter Min Typ Max Units Notes VTT Bus Termination Voltage 1 14 1 25 1 308 V 3 On die Termination Resistor 508 56 68 115 4 7 VREF Bus Reference Voltage 2 3 VIT 2 2 8 2 8 VIT 2 V 5 NOTES 1 Specifications in this table do not apply to Pentium processors at all frequencies Please refer to the Inte Pentium IIl Processor Specification Update for a complete listing on the processors that support the AGTL specification 2 Pentium processors for the PGA370 socket contain AGTL termination resistors on the processor die except for the RESET input 3 VTT must be held to 1 25 V 9 It is required that VTT be held to 1 25 V 3 while the processor system bus is idle static condition This is measured at the 70 socket pins on the bottom side of the baseboard 4 The value of the on die is determined by the resistor value measured by the RTTCTRL signal pin The on die has a resistance tolerance of 15 See Section 7 0 for more
144. ve an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Pentium Il Pentium Pentium Pro Celeron and Intel387 are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright O Intel Corporation 2001 Datasheet intel Pentium Ill Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Contents 1 0 2 0 3 0 Datasheet 8 1 1 Mna 9 1 1 1 Package and Processor Terminology 9 1 1 2 Processor Naming 10 1 2 Related Documents inedite pioneer esa Taar 11 Electrical 5 egets dines 13 2 1 Processor System Bus and Vggp esent 13 2 2 Clock Control and Low Power Sales 14 2 21 Normal State State 1 15 2 2 2 AutoHALT Powerdown State State 2 15 2 2 3 Stop Grant State State 3 16 2 2 4 HALT Grant Snoop State State 4 16 2 2 5 Sleep State State B 16 2 2 0 Deep Sleep State State D eee 1
145. voc vss vec G G D21 023 VSS BP2 VTT RSV F vec 032 022 _ RSV D27 _ VCC 063 _ VSS VSS vss vec VSS _ VSS E 026 025 voc vss vss voc vss voc vss RSV VIT 062 _ SLEW DEP6 DEP4 VREFO BPM1 BP3 D CTRL p vss vss _ D38 D39 042 052 _ VSS _ vss VCC _ VSS _ vss _ VSS voc D33 VCC D31 D34 D36 D45 D49 D40 D59 D55 D54 D58 D50 D56 DEP5 DEP1 DEPO BPMO CPUPRES B 035 vss _ vss VSS vec _ vss _ vss _ vss vec _ vss _ VSS _ VCC _ BINIT 029 028 043 037 044 051 047 048 057 046 053 060 061 DEP7 2 PRDY VSS Dep7 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 pinout Datasheet 68 Pentium III Processor for the PGA370 Socket at 500 MHz to 1 13 GHz Table 39 Signal Listing in Order by Table 39 Signal Listing in Order by Datasheet Signal Name Signal Name Continued ad Pin Name Signal Group Pin Name Signal Group AK8 A3 AGTL I O B36 BINIT AGTL I O AH12 A4 AGTL I O AH14 BNR AGTL I O AH8 Abit AGTL I O G33 BP2 AGTL I O AN9 A6 AGTL I O E37 BP3 AGTL I O AL15

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