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Intel Pentium 4

1. Table 30 Pin Listing by Pin Name Table 30 Pin Listing by Pin Name Pin Name Pin Number aU AN Direction Pin Name Pin Number dg Direction DSTBNO AG35 Source Synch Input Output SMI K38 Asynch GTL Input DSTBN1 AP32 Source Synch Input Output STPCLK C5 Asynch GTL Input DSTBN2 AP22 Source Synch Input Output TCK R37 TAP Input DSTBN3 AP18 Source Synch Input Output TDI J39 TAP Input DSTBPO AJ35 Source Synch Input Output TDO P36 TAP Output DSTBP1 AP30 Source Synch Input Output TESTHIO A7 Power Other Input DSTBP2 AP20 Source Synch Input Output TESTHI1 AT10 Power Other Input DSTBP3 AP16 Source Synch Input Output TESTHI2 AT6 Power Other Input FERR P38 Asynch GTL Output TESTHIS AT8 Power Other Input GTLREF AC35 Power Other Input TESTHI4 AU7 Power Other Input GTLREF AP10 Power Other Input TESTHI5 AU9 Power Other Input GTLREF F14 Power Other Input TESTHI6 AU11 Power Other Input GTLREF T36 Power Other Input TESTHI7 AW5 Power Other Input HIT K36 Common Clock Input Output TESTHI8 D16 Power Other Input HITM D36 Common Clock Input Output TESTHI9 D18 Power Other Input IERR C7 Common Clock Output TESTHI10 D20 Power Other Input IGNNE M38 Asynch GTL Input THERMDA H38 Power Other INIT D8 Asynch GTL Input THERMDC E39 Power Other ITP_CLKO AU1 TAP Input THERMTRIP U37 Asynch G
2. NU Pin Name ac ees Direction Al VID4 Power Other Output A3 VID3 Power Other Output A5 SKTOCC Power Other Output A7 TESTHIO Power Other Input AQ A32 Source Synch Input Output A11 A33 Source Synch Input Output A13 A27 Source Synch Input Output A15 A26 Source Synch Input Output A17 A20 Source Synch Input Output A19 A30 Source Synch Input Output A21 A22 Source Synch Input Output A23 A14 Source Synch Input Output A25 A13 Source Synch Input Output A27 A15 Source Synch Input Output A29 A17 Source Synch Input Output A31 A114 Source Synch Input Output A33 LOCK Common Clock Input Output A35 TRDY Common Clock Input A37 VCC Power Other A39 VCC Power Other B2 VID1 Power Other Output B4 VID2 Power Other Output B6 VCC Power Other B8 VSS Power Other B10 VCC Power Other B12 VSS Power Other B14 VCC Power Other B16 VSS Power Other B18 VCC Power Other B20 VSS Power Other B22 VCC Power Other Number Pin Name Type Direction B24 VSS Power Other B26 VCC Power Other B28 VSS Power Other B30 VCC Power Other B32 VSS Power Other B34 DBSY Common Clock Input Output B36 BRO Common Clock Input Output B38 VSS Power Other C1 VIDO Power Other Output C3 VCC Power Other C5 STPCLK Asynch GTL Input C7 IERR Common Clock Output C9 RSP Common Clock Input C11 A313 Source Synch Input Output C13 BPM4 Common Cl
3. 1 These speci fications are specified at the processor silicon Absolute Absol te Pul Pulse Pulse aan en a Duration ns Burton ns Duration 9 Notes 1 2 3 4 V V 2 30 0 65 0 26 2 60 20 0 2 25 0 60 0 49 4 88 20 0 2 20 0 55 0 90 9 00 20 0 2 15 0 50 1 66 16 60 20 0 2 10 0 45 2 96 20 0 20 0 2 05 0 40 5 52 20 0 20 0 2 00 0 35 10 0 20 0 20 0 1 95 0 30 18 0 20 0 20 0 1 90 0 25 20 0 20 0 20 0 1 85 0 20 20 0 20 0 20 0 1 80 0 15 20 0 20 0 20 0 1 75 0 10 20 0 20 0 20 0 NOTES 1 These specifications are specified at the processor silicon 2 BCLK period is 10 ns 3 AF is referenced to BCLK 1 0 4 These specifications apply to 1 7V processors i e those with a VID 00110 Table 21 Asynchronous GTL and TAP Signal Groups Overshoot Undershoot Tolerance 1 7V Processors Absolute Absolute Pul Pul bot kj i Duration ns Du ration ns Duration ns Notes 1 23 V V 2 30 0 65 0 78 7 80 60 0 2 25 0 60 1 46 14 64 60 0 2 20 0 55 2 70 27 0 60 0 2 15 0 50 4 98 49 8 60 0 2 10 0 45 8 88 60 0 60 0 2 05 0 40 16 56 60 0 60 0 2 00 0 35 30 0 60 0 60 0 1 95 0 30 54 0 60 0 60 0 1 90 0 25 60 0 60 0 60 0 1 85 0 20 60 0 60 0 60 0 1 80 0 15 60 0 60 0 60 0 1 75 0 10 60 0 60 0 60 0 NOTES In Table 22 Source Synchronous 400MHz AGTL Signal Group Overshoot Undershoot Table 23 Source Synchronous 200MHz AGTL Signal Group Overshoot
4. BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of all processor system bus agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BRO Input Output BRO drives the BREOO signal in the system and is used by the processor to reguest the bus During power on configuration this pin is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated COMP 1 0 Analog COMP 1 0 must be terminated on the system board using precision resistors Refer to Table 9 in Chapter 2 0 in Intel Pentium 4 Processor in the 423 pin Package Table 32 Signal Description Page 3 of 8 Name Type Description D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each gro
5. Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing Voltage is defined as absolute voltage where rising edge of BCLKO is equal to the falling edge of BCLK1 The V and Vy used to calculate Voross are the actual Vi and Vy seen by the processor Overshoot is defined as the absolute value of the maximum voltage allowed above the Vj level Undershoot is defined as the absolute value of the maximum voltage allowed below the Vgs level Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback Threshold Region is defined as a region centered about the crossing voltage in which the differential receiver Switches It includes input threshold hysteresis Table 7 AGTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 150 GTLREF 100mV V 2 6 VIH Input High Voltage GTLREF 100mV Voc V 3 4 6 VoH Output High Voltage GTLREF 100mV Voc V 4 6 Voc 0 5 Rtt min lot Output Low Current RON MIN mA 6 Iu Input Leakage Current 100 uA ILo Output Leakage Current 100 uA RON Buffer On Resistance 5 11 Q 5 NOTES ug 2 Unless otherwise noted all specifications in this table apply to all processor freguencies VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a lo
6. When the priority agent asserts BPRI to arbitrate for ownership of the processor system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock MCERR Input Output MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor system bus agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture please refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide PROCHOT Output PROCHOT will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum tested operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled See Section 7 3 for more details 67 Intel Pentium 4 Processor in the 423 pin Package In Table 32 Signal Description Page 6 of 8 Name Type De
7. The drawing below is not to scale and is for reference only The socket and system board are supplied as a reference only Figure 16 Exploded View of Processor Components on a System Board IHS g Die Thermal Interface OLGA I Y Capacitors System board 43 Package pin Intel Pentium 4 Processor in the 423 Figure 17 Processor Package ee Ree kd o o o o a o eee M NTERPOS Intel Pentium 4 Processor in the 423 pin Package Table 26 Description Table for Processor Dimensions Code Letter Min Typ Max Notes 2 094 2 100 2 106 B 1 217 1 220 1 224 C 1 059 1 063 1 067 2 D 0 054 0 079 0 104 E 0 509 0 515 0 521 F 0 459 0 465 0 471 G 0 167 0 192 0 217 H 0 941 0 950 0 959 J 0 941 0 950 0 959 K 0 100 L 0 727 0 737 0 747 M 0 571 0 576 0 581 N 0 677 0 687 0 697 P 0 055 0 067 0 079 3 T 0 891 0 900 0 909 U 0 100 V 0 891 0 900 0 909 NOTES 1 All dimensions in inches unless otherwise noted 2 Nickel plated copper 3 Diameter Figure 18 details the keep in specification for pin side components Pentium 4 processors may contain pin side capacitors mounted to the processor OLGA package The capacitors will be exposed within the opening of the interposer cavity Figure 20 detail
8. T13 RESETH Pulse Width Ty 145 Reset Configuration Signals Setup Time T T46 Reset Configuration Signals Hold Time Figure 8 Source Synchronous 2X Address Timings T1 T2 25ns 5 0ns 7 5ns BCLK1 BCLKO ADSTB driver A driver ADSTB receiver A receiver Ty T23 Source Sync Address Output Valid Before Address Strobe T T24 Source Sync Address Output Valid After Address Strobe T T27 Source Sync Input Setup to BCLK Ty T26 Source Sync Input Hold Time T T25 Source Sync Input Setup Time T20 Source Sync Output Valid Delay T31 Address Strobe Output Valid Delay N P S R 28 intel Figure 9 Intel Pentium 4 Processor in the 423 pin Package Source Synchronous 4X Timings TO Ti T2 25ns 5 0ns 7 5ns BCLK1 BCLKO DSTBp driver DSTBn driver DSTBp receiver DSTBn receiver D receiver gt o M MW wy on gon od T21 Source Sync Data Output Valid Delay Before Data Strobe T22 Source Sync Data Output Valid Delay After Data Strobe T27 Source Sync Setup Time to BCLK T30 Source Sync Data Strobe N DSTBN Output Valid Delay T25 Source Sync Input Setup Time T26 Source Sync Input Hold Time T29 First Data Strobe to Subsequent Strobes T20 Source Sync Data Output Valid Delay Ow om 44444444 c I Figure 10 Power On Reset and Co
9. lvip Max VID pin current 5 mA NOTE 1 This rating applies to any processor pin Processor DC Specifications The processor DC specifications in this section are defined at the processor core silicon and not the package pins unless noted otherwise See Chapter 5 0 for the pin signal definitions and signal pin assignments Most of the signals on the processor system bus are in the AGTL signal group The DC specifications for these signals are listed in Table 7 Previously legacy signals and Test Access Port TAP signals to the processor used low voltage CMOS buffer types However these interfaces now follow DC specifications similar to GTL The DC specifications for these signal groups are listed in Table 8 Table 5 through Table 8 list the DC specifications for the Pentium 4 processor and are valid only while meeting specifications for case temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter Intel Pentium 4 Processor in the 423 pin Package Table 5 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes Voc Vcc for processor at 1 30 GHz 1 565 1 70 V 2 3 4 9 VID 1 7V 1 40 GHz 1 560 1 70 V 2 3 4 9 1 50 GHz 1 555 1 70 V 2 3 4 9 Voc for processor at 1 30 GHz 1 605 1 75 V 2 3 4 10 1 40 GHz 1 600 1 75 V 2 3 4 10 Voc 1 50 GHz 1 595 1 75 V 2 3 4 10 VID 1 75V 1
10. Nickel over copper Interposer FR4 Interposer pins Gold over nickel Processor Markings The following section details the processor top side laser markings and is provided to aid in the identification of the Pentium 4 processor Specific details regarding individual fields in the product markings will be provided in a future release of the EMTS Figure 21 Processor Markings 4 6 48 S Spec Country of Assy FPO Serial Intel pentium 1 5GHz 256 400 1 7V SYYYY XXXXXX FFFFFFFF NNNN Frequency Cache Bus Voltage 2 D Matrix Mark NOTES 1 All characters will be in upper case Processor Pin Out Coordinates Figure 22 details the coordinates of the 423 processor pins as viewed from the bottom of the package Intel Pentium 4 Processor in the 423 pin Package Figure 22 Processor Pinout Diagram Bottom View E lt Ec cCAwmvz Fr Ke TH 7M Oo Dw gt 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lt lt cAaAwmv2z Fr Re TH 7M OU 49 Intel Pentium 4 Processor in the 423 pin Package 50 5 0 Pin Listing and Signal Definitions Intel Pentium 4 Processor in the 423 pin Package Section
11. Pin Listing by Pin Name Pin Name Pin Number err Direction A281 F20 Source Synch Input Output A291 C21 Source Synch Input Output A30 A19 Source Synch Input Output A31 C11 Source Synch Input Output A32 AQ Source Synch Input Output A33 A11 Source Synch Input Output A341 C15 Source Synch Input Output A35 D12 Source Synch Input Output A20M T38 Asynch GTL Input ADS F36 Common Clock Input Output ADSTBO G25 Source Synch Input Output ADSTB1 G21 Source Synch Input Output APO F16 Common Clock Input Output AP1 D14 Common Clock Input Output BCLKO AR7 Bus Clock Input BCLK1 AP8 Bus Clock Input BINIT F18 Common Clock Input Output BNR E35 Common Clock Input Output BPMO F8 Common Clock Input Output BPM1 F12 Common Clock Input Output BPM2 F10 Common Clock Input Output BPM3 E7 Common Clock Input Output BPM4 C13 Common Clock Input Output BPM5 D6 Common Clock Input Output BPRIH L37 Common Clock Input BROH B36 Common Clock Input Output 51 Intel Pentium 4 Processor in the 423 pin Package intel Table 30 Pin Listing by Pin Name Table 30 Pin Listing by Pin Name Pin Name Pin Number ae Direction Pin Name Pin Number Rc d Direction COMPO AU27 Power
12. T21 Tygp Source Synchronous Data Output Valid Before Strobe 0 09 nS a 28 T22 Tyap Source Synchronous Data Output Valid After Strobe mae is a 198 T23 Tyga Source Synchronous Address Output Valid Before Strobe s DR 8 98 T24 TyaA Source Synchronous Address Output Valid After Strobe 100 Re Gr mes T25 T3uss Source Synchronous Input Setup Time to Strobe ge ns ind 3 T26 Tugs Source Synchronous Input Hold Time to Strobe DET me am d T27 Tsucc Source Synchronous Input Setup Time to BCLK 1 0 06 ng Ba ie T28 Trass First Address Strobe to Second Address Strobe ME BOLK 3 10 T29 Trpss First Data Strobe to Subsequent Strobes we BOLK a Mete T30 Data Strobe n DSTBN Output 8 80 10 20 hs 9 13 Valid Delay T31 Address Strobe Output Valid 2 27 4 23 ns 8 Delay NOTE 1 2 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes Not 100 tested Specified by design characterization 23 Intel Pentium 4 Processor in the 423 pin Package In All source synchronous AC timings are referenced to their associated strobe at GTLREF Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at GTLREF at the processor core Unless otherwise noted these specifi
13. The LAI pins plug into the socket while the Pentium 4 processor pins plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the Pentium 4 processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may include space normally occupied by the Pentium 4 processor heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the system bus therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide 89 Intel Pentium 4 Processor in the 423 pin Package 90
14. 1 90 0 25 5 00 5 00 5 00 1 85 0 20 5 00 5 00 5 00 1 80 0 15 5 00 5 00 5 00 1 75 0 10 5 00 5 00 5 00 NOTES 1 These specifications are specified at the processor silicon 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes 4 These specifications apply to 1 7V processors i e those with a VID 00110 Table 19 Source Synchronous 200MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 7V Processors Absolute Absolute Maximum Maximum Pulse Pulse Pulse 1 2 3 4 Duration ns Duration ns Duration ns Notes gt gt Overshoot Undershoot AF 1 AF 0 1 AF 0 01 V V 2 30 0 65 0 13 1 30 10 0 2 25 0 60 0 24 2 44 10 0 2 20 0 55 0 45 4 50 10 0 2 15 0 50 0 83 8 30 10 0 2 10 0 45 1 48 10 0 10 0 2 05 0 40 2 76 10 0 10 0 2 00 0 35 5 00 10 0 10 0 1 95 0 30 5 00 10 0 10 0 1 90 0 25 10 0 10 0 10 0 1 85 0 20 10 0 10 0 10 0 1 80 0 15 10 0 10 0 10 0 1 75 0 10 10 0 10 0 10 0 NOTES 1 These specifications are specified at the processor silicon 2 Assumes a BCLK period of 10 ns 37 Intel Pentium 4 Processor in the 423 pin Package 38 3 AF is referenced to associated source synchronous strobes 4 These specifications apply to 1 7V processors i e those with a VID 00110 Table 20 Common Clock 100MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 7V Processors
15. 10 0 385 9 00 60 0 60 0 2 05 0 335 16 2 60 0 60 0 2 00 0 285 30 0 60 0 60 0 1 95 0 235 56 4 60 0 60 0 1 90 0 185 60 0 60 0 60 0 1 85 0 135 60 0 60 0 60 0 1 80 0 085 60 0 60 0 60 0 NOTES 1 These specifications are specified at the processor pad 2 This table assumes a 33MHz time domain a intel Intel Pentium 4 Processor in the 423 pin Package 3 These specifications apply to 1 75V processors i e those with a VID 00100 Figure 15 Maximum Acceptable Overshoot Undershoot Waveform Maximum Absolute Overshoot Time dependent Overshoot SS CAM rA A SE Time dependent Maximum Undershoot Absolute Undershoot nnaran 41 Intel Pentium 4 Processor in the 423 pin Package 42 Intel Pentium 4 Processor in the 423 pin Package Package Mechanical Specifications Note The Intel Pentium 4 Processor in the 423 pin Package uses Pin Grid Array PGA package technology Components of the package include an integrated heat spreader processor silicon silicon mounting substrate or Organic Land Grid Array OLGA and an interposer which is the pincarrier Mechanical specifications for the processor are given in this section See Section 1 1 for a terminology listing The processor socket which accepts the Pentium 4 processor in the 423 pin package is referred to as a 423 Pin Socket See the 423 Pin Socket PGA423 Design Guidelines for further details on the 423 Pin Socket
16. 48 DBIS DSTBN3 DSTBP 3 0 Input Output Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBIS DSTBP3 FERR Output FERR Floating point Error is asserted when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting GTLREF Input GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 Voc GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical 1 Refer to the Inte Pentium 4 Processor and Inte 850 Chipset Platform Design Guide for more information HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any system bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor system bus This transaction may optionally be converted to an external error signal e g
17. 5 1 contains the pinlist for the Intel Pentium 4 Processor in the 423 pin Package in Table 30 and Table 31 Table 30 is a listing of all processor pins ordered alphabetically by pin name Table 5 1 Processor Pin Assignments 31 is also a listing of all processor pins but ordered by pin number 5 1 1 Pin Listing by Pin Name Table 30 Pin Listing by Pin Name Pin Name Pin Number a Direction A3 F30 Source Synch Input Output A4 C29 Source Synch Input Output Abit D30 Source Synch Input Output A6 C31 Source Synch Input Output ATH F28 Source Synch Input Output A8 D28 Source Synch Input Output A9 F26 Source Synch Input Output A10 C23 Source Synch Input Output A11 A31 Source Synch Input Output A12 C25 Source Synch Input Output A13 A25 Source Synch Input Output A14 A23 Source Synch Input Output A15 A27 Source Synch Input Output A16 D24 Source Synch Input Output A17 A29 Source Synch Input Output A18 C27 Source Synch Input Output A19 D26 Source Synch Input Output A20 A17 Source Synch Input Output A21it C17 Source Synch Input Output A22 A21 Source Synch Input Output A23 C19 Source Synch Input Output A24 F22 Source Synch Input Output A25 D22 Source Synch Input Output A26 A15 Source Synch Input Output A27 A13 Source Synch Input Output Table 30
18. 60 GHz 1 590 1 75 V 2 3 4 10 1 70 GHz 1 580 1 75 V 2 3 4 10 1 80 GHz 1 575 1 75 V 2 3 4 10 1 90 GHz 1 570 1 75 2 3 4 10 2 GHz 1 560 1 75 2 3 4 10 in RU c TT lcc for processor loc 1 30 GHz 38 1 A 4 5 9 VID 1 70V 1 40 GHz 40 6 A 4 5 9 1 50 GHz 43 0 A 4 5 9 lcc for processor 1 30 GHz 39 8 A 4 5 10 1 40 GHz 42 2 A 4 5 10 1 50 GHz 45 0 A 4 5 10 lcc 1 60 GHz 477 4 5 10 VID 1 75V 1 70 GHz 50 2 A 4 5 10 1 80 GHz 50 6 A 4 5 10 1 90 GHz 52 7 A 4 5 10 2 GHz 55 0 A 4 5 10 leg Stop Grant Icc Sleep 6 8 1 30 GHz 9 7 A 1 40 GHz 9 8 A isa 1 50 GHz 9 9 A 1 60 GHz 10 7 A lsP 1 70 GHz 10 9 A 1 80 GHz 11 1 A 1 90 GHz 11 0 A 2 GHz 11 3 A Ipsi P lcc Deep Sleep 8 7 A 8 Irec leg TCC active loc A 7 Ioc_PLL lcc for PLL pins 30 mA NOTES 1 Unless otherwise noted all specifications in this table are based on estimates and simulations or early empirical data These specifications will be updated with characterized data from silicon measurements at a later date 19 Intel Pentium 4 Processor in the 423 pin Package 20 8 9 intel These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 4 and Table 2 for more information The voltage specification requirements are measured across Vcc sense and Vas sense pins at the socket with a 100MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum i
19. AF38 D7 Source Synch Input Output AA1 VCC Power Other AG1 VSS Power Other AA3 VSS Power Other AG3 VCC Power Other AAS VCC Power Other AG5 VSS Power Other AA7 VSS Power Other AG7 VCC Power Other AA35 D5 Source Synch Input Output AG35 DSTBNO Source Synch Input Output AA37 VSS Power Other AG37 VCC Power Other AA39 D15 Source Synch Input Output AG39 D4 Source Synch Input Output AB2 VSS Power Other AH2 VCC Power Other AB4 VCC Power Other AH4 VSS Power Other AB6 VSS Power Other AH6 VCC Power Other AB8 VCC Power Other AH8 VSS Power Other AB36 D10 Source Synch Input Output AH36 D12 Source Synch Input Output AB38 VCC Power Other AH38 VSS Power Other AC1 VSS Power Other AJ1 VCC Power Other AC3 VCC Power Other AJ3 VSS Power Other AC5 VSS Power Other AJ5 VCC Power Other AC7 VCC Power Other AJ7 VSS Power Other AC35 GTLREF Power Other Input AJ35 DSTBPO Source Synch Input Output AC37 D14 Source Synch Input Output AJ37 D13 Source Synch Input Output AC39 VSS Power Other AJ39 VCC Power Other AD2 VCC Power Other AK2 VSS Power Other AD4 VSS Power Other AK4 VCC Power Other AD6 VCC Power Other AK6 VSS Power Other AD8 VSS Power Other AK8 VCC Power Other AD36 D1 Source Synch Input Output AK36 D24 Source Synch Input Output AD38 D114 Source Synch Input Output AK38 D17 Source Synch Input Output AE1 VCC Power Other AL1 VSS Power Other AE3 VSS Power Other AL3 VCC Power Other AE5 VCC Power Other AL5 VSS Power Other AE7 VSS Power Other AL7 VCC Power Other AE35 V
20. Bus Common Clock AC Specifications T Parameter Min Max Unit Figure Notes T10 Common Clock Output Valid Delay 0 20 1 45 ns 6 4 T11 Common Clock Input Setup Time 0 65 ns 6 5 T12 Common Clock Input Hold Time 0 40 ns 6 5 T13 RESET Pulse Width 1 00 10 00 ms 7 6 7 8 NOTES 1 2 3 MND Unless otherwise noted all specifications in this table apply to all processor frequencies Not 100 tested Specified by design characterization All common clock AC timings for AGTL signals are referenced to the Crossing Voltage Vcnoss of the BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at GTLREF at the processor core Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF at 2 3 Voc 2 Specification is for a minimum swing defined between AGTL Vi__ max to Vi min This assumes an edge rate of 0 4 V ns to 4 0V ns RESET can be asserted asynchronously but must be deasserted synchronously This should be measured after Voc and BCLK 1 0 become stable Maximum specification applies only while PWRGOOD is asserted Table 12 System Bus Source Synch AC Specifications AGTL Signal Group T Parameter Min Typ Max Unit Figure Notesb234 T20 Source Synchronous Data Output Valid Delay first data address only mb 1 30 ne ae 3
21. L7 Power Other VCC AV6 Power Other VCC M2 Power Other VCC B10 Power Other VCC M6 Power Other VCC B14 Power Other VCC N1 Power Other VCC B18 Power Other VCC N5 Power Other 54 intel Intel Pentium 4 Processor in the 423 pin Package Table 30 Pin Listing by Pin Name Table 30 Pin Listing by Pin Name Pin Name Pin Number aU id Direction Pin Name Pin Number ironia Direction VCC P4 Power Other VSS AG1 Power Other VCC P8 Power Other VSS AG5 Power Other VCC R3 Power Other VSS AH38 Power Other VCC R7 Power Other VSS AH4 Power Other VCC T2 Power Other VSS AH8 Power Other VCC T6 Power Other VSS AJ3 Power Other VCC U1 Power Other VSS AJ7 Power Other VCC U39 Power Other VSS AK2 Power Other VCC US Power Other VSS AK6 Power Other VCC V4 Power Other VSS AL1 Power Other VCC V8 Power Other VSS AL35 Power Other VCC W3 Power Other VSS AL5 Power Other VCC W7 Power Other VSS AM4 Power Other VCC Y2 Power Other VSS AM8 Power Other VCC Y36 Power Other VSS AN3 Power Other VCC Y6 Power Other VSS AN37 Power Other VCC_SENSE N39 Power Other Output VSS AN7 Power Other VCCA AU5 Power Other VSS AP2 Power Other VCCIOPLL AW3 Power Other VSS AP6 Power Other VIDO C1 Power Other Output VSS A
22. Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in real mode A20Mi is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 AP 1 0 Input Output AP 1 0 t Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This
23. Name Pin Name Pin Number Se dd Direction Pin Name Pin Number dee Direction VCC AG37 Power Other VCC B22 Power Other VOC AG7 Power Other VCC B26 Power Other VCC AH2 Power Other VCC B30 Power Other VCC AH6 Power Other VCC B6 Power Other VCC AJ1 Power Other VCC C3 Power Other VCC AJ39 Power Other VCC C37 Power Other VOC AJ5 Power Other VCC D2 Power Other VOC AK4 Power Other VCC E1 Power Other VCC AK8 Power Other VCC E13 Power Other VCC AL3 Power Other VCC E17 Power Other VCC AL7 Power Other VCC E21 Power Other VCC AM2 Power Other VCC E25 Power Other VCC AM36 Power Other VCC E29 Power Other VCC AM6 Power Other VCC E33 Power Other VCC AN1 Power Other VCC E5 Power Other VCC AN5 Power Other VCC E9 Power Other VCC AP38 Power Other VCC F4 Power Other VCC AP4 Power Other VCC G13 Power Other VCC AR13 Power Other VCC G19 Power Other VCC AR17 Power Other VCC G29 Power Other VCC AR21 Power Other VCC G3 Power Other VCC AR25 Power Other VCC G33 Power Other VCC AR29 Power Other VCC G39 Power Other VCC AR3 Power Other VCC G7 Power Other VCC AR33 Power Other VCC G9 Power Other VCC AR9 Power Other VCC H2 Power Other VCC AT2 Power Other VCC H6 Power Other VCC AV10 Power Other VCC J1 Power Other VCC AV14 Power Other VCC J37 Power Other VCC AV18 Power Other VCC J5 Power Other VCC AV22 Power Other VCC K4 Power Other VCC AV26 Power Other VCC K8 Power Other VCC AV30 Power Other VCC L3 Power Other VCC AV34 Power Other VCC L35 Power Other VCC AV38 Power Other VCC
24. Other Input Output D37 AW29 Source Synch Input Output COMP1 F24 Power Other Input Output D38 AU31 Source Synch Input Output DO Y38 Source Synch Input Output D39 AT30 Source Synch Input Output Ditt AD36 Source Synch Input Output D40 AT28 Source Synch Input Output D2 W37 Source Synch Input Output D41 AP24 Source Synch Input Output D3 AE37 Source Synch Input Output D42 AU25 Source Synch Input Output D4 AG39 Source Synch Input Output D43 AP28 Source Synch Input Output D5 AA35 Source Synch Input Output D44 AW25 Source Synch Input Output D6 V36 Source Synch Input Output D45 AT24 Source Synch Input Output D7 AF38 Source Synch Input Output D46 AW23 Source Synch Input Output D8 W39 Source Synch Input Output D47 AU23 Source Synch Input Output Dot AE39 Source Synch Input Output D48 AU19 Source Synch Input Output D10 AB36 Source Synch Input Output D49 AT20 Source Synch Input Output D11 AD38 Source Synch Input Output D50 AU21 Source Synch Input Output D12 AH36 Source Synch Input Output D51 AW21 Source Synch Input Output D13 AJ37 Source Synch Input Output D52 AW19 Source Synch Input Output D14 AC37 Source Synch Input Output D53 AT18 Source Synch Input Output D15 AA39 Source Synch Input Output D54 AU17 Source Synch Input Output D16 AT36 Source Synch Input Output D55 AT16 Source Synch Input Output D17 AK38 Source Synch Input Output D56 AU15 Source Synch Input Output D18 AP34 Source Synch Input Output D57 AT14 Source Synch Input Outpu
25. STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the system bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TESTHI 10 0 Input TESTHI 10 0 must be connected to a Voc power source through 1 10 KQ resistors for proper processor operation See Section 2 5 for more details THERMDA Other Thermal Diode Anode See Section 7 3 1 THERMDC Other Thermal Diode Cathode See Section 7 3 1 THERMTRIP Output The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the norma
26. allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all Pentium 4 processor system bus agents The following table defines the coverage model of these signals Request Signals subphase 1 subphase 2 A 35 24 APO AP1 A 23 3 AP1 APO REG 4 0 if AP1 APO BCLK 1 0 Input The differential pair BCLK Bus Clock determines the system bus frequency All processor system bus agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss 63 Intel Pentium 4 Processor in the 423 pin Package In 64 Table 32 Signal Description Page 2 of 8 Name Type Description BINIT Input Output BINIT Bus Initialization may be observed and driven by all processor system bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their IOO and transaction tracking state machines upon observation of BINIT activation Once
27. be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process a system bus snoop HALT Grant Snoop State State 4 The processor will respond to snoop transactions on the system bus while in Stop Grant state or in AutoHALT Power Down state During a snoop transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the system bus has been serviced whether by the processor or another agent on the system bus After the snoop is serviced the processor will return to the Stop Grant state or AutoHALT Power Down state as appropriate Sleep State State 5 The Sleep state is a very low power state in which the processor maintains its context maintains the phase locked loop PLL and has stopped all internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state the processor will enter the Sleep state upon the assertion of the SLP signal The SLP pin should only be asserted when the processor is in the Stop Grant state SLP assertions while the processor is not in the Stop Grant state is out of specification and may result in illegal operation Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior
28. in the 423 pin Package 26 Figure 3 AC Test Circuit AC Timings test measurements made here Rload 50 ohms Figure 4 TCK Clock Waveform tr T56 T58 Rise Time tf T57 T59 Fall Time tp T55 TCK Period Figure 5 Figure 6 Intel Pentium 4 Processor in the 423 pin Package Differential Clock Waveform Tph e a Overshoot BCLK1 VH Rising Edge ce OE Ef s tee GN Nee EEEE Ringback Pe De a ON LESE Crossing Crossing Ringback Threshold Voltage Voltage Margin Region x TK HETE Te Falling Edge ctt Ha EE I AO VE NAG ME Ringback BCLKO e VL IAL ILL NL IL LLSG SS Yolo pee ds sell synn Sar Undershoot Tpl SS Tp Tp T1 BCLK 1 0 period T2 BCLK 1 0 Period stability not shown Tph T3 BCLK 1 0 pulse high time Tpl T4 BCLK 1 0 pulse low time T5 BCLK 1 0 rise time through the threshold region not shown T6 BCLK 1 0 fall time through the threshold region not shown System Bus Common Clock Valid Delay Timings TO T1 T2 BCLK1 BCLKO Common Clock 7 Signal driver Common Clock Signal receiver Tp T10 Too Data Valid Output Delay Tg T11 Tay Common Clock Setup TR T12 Ty Common Clock Hold Time 27 Intel Pentium 4 Processor in the 423 pin Package in Figure 7 System Bus Reset and Configuration Timings Tu T gt RESET iii TUI INIT SMI Ty
29. maintaining context Deep Sleep state is entered by stopping the BCLK 1 0 inputs after the Sleep state was entered from the assertion of the SLP pin The processor is in Deep Sleep state immediately after BLCK 1 0 is stopped To provide maximum power conservation hold the BLCKO input at Vor and the BCLK1 input at Voy during the Deep Sleep state Stopping the BCLK input lowers the overall current consumption to leakage levels To re enter the Sleep state the BLCK input must be restarted A period of 1 ms to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep State Once in the Sleep state the SLP pin can be deasserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals are allowed on the system bus while the processor is in Deep Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior The processor has to stay in Deep Sleep mode for a minimum of 25 ms When the processor is in Deep Sleep state it will not respond to interrupts or snoop transactions Thermal Monitor Thermal Monitor is a new feature found in the Pentium 4 processor which allows system designers to design lower cost thermal solutions without compromising system integrity or reliability By using a factory t
30. pin Package intel 36 these worst case overshoot or undershoot events meet the specifications measured time lt specifications in the table where AF 1 then the system passes The following notes apply to Table 18 through Table 21 NOTES 1 Absolute Maximum Overshoot magnitude of 2 3V must never be exceeded 2 Absolute Maximum Overshoot is measured relative to Vss Pulse Duration of overshoot is measured relative to Vcc 3 Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to Vss 4 Ringback below Vcc can not be subtracted from overshoots undershoots 5 Lesser undershoot does not allocate longer or larger overshoot 6 OEM s are strongly encouraged to follow Intel provided layout guidelines 7 All values specified by design characterization In Intel Pentium 4 Processor in the 423 pin Package Table 18 Source Synchronous 400MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 7V Processors Maximum Maximum Pulse Pulse Pulse pa Overshoot Undershoot Duration ns Duration ns Duration ns Notes AF 1 AF 0 1 AF 0 01 V V 2 30 0 65 0 07 0 65 5 00 2 25 0 60 0 12 1 22 5 00 2 20 0 55 0 23 2 25 5 00 2 15 0 50 0 42 4 15 5 00 2 10 0 45 0 74 5 00 5 00 2 05 0 40 1 38 5 00 5 00 2 00 0 35 2 50 5 00 5 00 1 95 0 30 4 50 5 00 5 00
31. rrrnnnnnnnnnnnnnnnrnnnnnnnnnrnnnnnnnnnnn 83 8 2 3 Boxed Processor Retention Mechanism and Fan Heatsink Supports 83 8 3 Boxed Processor Requirements sse nenne 84 8 3 1 Fan Heatsink Power Supply seen 84 8 4 Thermal Specifications esses 85 8 4 1 Boxed Processor Cooling Requirements ssssssss 85 8 4 2 Variable Speed Fan rrnnnnrnnnannvnnnnrrrnnnnvnnnenrenannrnnnenvensnnrnnsnnnennnnrnnennnnenen 87 Debug Tools Specifications sss 89 9 1 Logic Analyzer Interface LAI ssssseeeeenenn 89 9 1 1 Mechanical Considerations ssssssssseeeeeee enn 89 9 1 2 Electrical Considerations ssssssssseeeeeeenennn 89 intel Figures O c0o O O G gt o Mo Contents Typical VCCIOPLL VCCA and VSSA Power Distribution ssssse 14 Phase Lock Loop PLL Filter Requirements cccceeeeeeeeeeeeeecteceeeeeeteeees 15 AG Test Circuits iria retos dere te Pet eden a FT lara TT TAR 26 TEK Clock Wavelform iiid kate d teri entera dee audi Nas code deg dca 26 Differential Clock Waveform sse enne nennen nnns 27 System Bus Common Clock Valid Delay Timings ssssesesss 27 System Bus Reset and Configuration Timings sssssssess 28 Source Synchronous 2X Address Timings rorrrrnn
32. temperature is near the trip point Once the temperature has returned to a non critical level and the hysteresis timer has expired modulation ceases and TCC goes inactive Processor performance will be decreased by 50 when the TCC is active assuming a 50 duty cycle however with a properly designed and characterised thermal solution the TCC most likely will only be activated briefly when the system is near maximum temperature and during the most power intensive applications For automatic mode the 50 duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardware software drivers or interrupt handling routines 7 3 1 Table 35 Intel Pentium 4 Processor in the 423 pin Package The TCC may also be activated via On Demand mode If bit 4 of the ACPI Thermal Monitor Control Register is written to a 1 the TCC will be activated immediately independent of the processor temperature When using On Demand mode to activate the TCC the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Thermal Monitor Control Register In automatic mode the duty cycle is fixed at 50 on 50 off however in On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 590 on 12 5 off in 12 590 increments On Demand mode may be used at the same time Automatic mode is enabled however if the system tries to enable the TCC via On Demand mode at the sam
33. 0 8 0 9 0 5 2 Alphabetical Signals Reference sse 63 Thermal Specifications and Design Considerations 71 6 1 Thermal Specifications esses ener nnns 72 6 2 Thermal Analysis teeth t e te ete Pt rte end e p RE Ern ee Rn ete 72 6 2 1 Measurements For Thermal Specifications sss 72 6 2 1 1 Processor Case Temperature Measurement 72 Features c abeat in tes c cun en 75 7 1 Power On Configuration Options ssssssseeeeneeeeen nnns 75 7 2 Clock Control and Low Power States ssssssssssssseeeeeeen 75 7 2 4 Normal State State 1 sssssssssssssseeeeeeen tenens 75 7 2 2 AutoHALT Powerdown State State 2 sss 75 7 2 8 Stop Grant State State 3 sssssssssssssssseeeenn 76 7 2 4 HALT Grant Snoop State State 4 ssssssssssssseeee 77 7 2 5 Sleep State State 5 77 7 2 6 Deep Sleep State State 6 78 7 3 Thermal Monitor diu nee eu CA Ti te E Ete Dn TD CR ee it un 78 fid ThermalDiode erat et eben rc dd 79 Boxed Processor Specifications sss 81 8 1 Iritro QU ction te eed tee a e Hen addit eie 81 8 2 Mechanical Specifications essen 81 8 2 1 Boxed Processor Fan Heatsink Dimensions seeess 82 8 2 2 Boxed Processor Fan Heatsink Weight
34. 10 GTLREF Power Other Input AT10 TESTHI1 Power Other Input AP12 D63 Source Synch Input Output AT12 D60s Source Synch Input Output AP14 D61 Source Synch Input Output AT14 D57 Source Synch Input Output AP16 DSTBP3 Source Synch Input Output AT16 D55 Source Synch Input Output AP18 DSTBN3 Source Synch Input Output AT18 D53 Source Synch Input Output AP20 DSTBP2 Source Synch Input Output AT20 D49 Source Synch Input Output AP22 DSTBN2 Source Synch Input Output AT22 DBl2 Source Synch Input Output AP24 D41 Source Synch Input Output AT24 D45 Source Synch Input Output AP26 D35 Source Synch Input Output AT26 DP3 Common Clock Input Output AP28 D43 Source Synch Input Output AT28 D40 Source Synch Input Output AP30 DSTBP1 Source Synch Input Output AT30 D39 Source Synch Input Output AP32 DSTBN1 Source Synch Input Output AT32 D33 Source Synch Input Output AP34 D18 Source Synch Input Output AT34 D30 Source Synch Input Output AP36 D22 Source Synch Input Output AT36 D16 Source Synch Input Output AP38 VCC Power Other AT38 D26 Source Synch Input Output AR1 VSS Power Other AU1 ITP_CLKO TAP Input AR3 VCC Power Other AU3 VSS Power Other AR5 VSS Power Other AU5 VCCA Power Other AR7 BCLKO Bus Clk Input AU7 TESTHI4 Power Other Input ARQ VCC Power Other AU9 TESTHI5 Power Other Input AR11 VSS Power Other AU11 TESTHI5 Power Other Input AR13 VCC Power Other AU13 D59 Source Synch Input Output AR15 VSS Power Other AU15 D56 Source Synch Input Output AR1
35. 2 Phase Lock Loop PLL Filter Requirements 2 5 0 5 dB pa ee O O ER DC I Hz fpeak 1 MHz 66 MHz fcore lt M passband high frequency band NOTES 1 Diagram not to scale 2 No specification for frequencies beyond fcore core frequency 3 fpeak if existent should be less than 0 05 MHz Reserved Unused Pins and TESTHI 10 0 All RESERVED pins must remain unconnected Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future Pentium 4 processors See Chapter 5 0 for a pin listing of the processor and the location of all RESERVED pins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level In a system level design on die termination has been included on the Pentium 4 processor to allow signals to be terminated within the processor silicon Most unused AGTL inputs should be left as no connects as AGTL termination is provided on the processor silicon However see Table 3 for details on AGTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vs Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boudary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal
36. 25 0 1 0 0 0 1 650 0 0 1 1 1 1 675 0 0 1 1 0 1 700 0 0 1 0 1 1 725 0 0 1 0 0 1 750 0 0 0 1 1 1 775 0 0 0 1 0 1 800 0 0 0 0 1 1 825 0 0 0 0 0 1 850 Phase Lock Loop PLL Power and Filter Vcca and VccropLu are power sources required by the PLL clock generators on the Pentium 4 processor silicon Since these PLLs are analog in nature they require quiet power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings i e maximum frequency To prevent this degradation these supplies must be low pass filtered from Vcc A typical filter topology is shown in Figure 1 The AC low pass requirements with input at Vcc and output measured across the capacitor Ca or Cro in Figure 1 is as follows 13 a Intel Pentium 4 Processor in the 423 pin Package intel 14 e lt 0 2 dB gain in pass band e lt 0 5 dB attenuation in pass band lt 1 Hz see DC drop in next set of requirements e gt 34 dB attenuation from I MHz to 66 MHz e gt 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2 For recommendations on implementing the filter refer to the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide Figure 1 Typical VeciopLL VccA and Vssa Power Distribution VCC L Processor Core Intel Pentium 4 Processor in the 423 pin Package Figure
37. 2X address bus provide a data bus bandwidth of up to 3 2 Gbytes second 3200Mbytes sec Finally the system bus also introduces transactions that are used to deliver interrupts Signals on the system bus use Assisted GTL AGTL level voltages which are fully described in the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide Terminology A 4 symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHU refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level System bus refers to the interface between the processor and system core logic a k a the chipset components The system bus is a interface to the processor memory and I O For this document system bus is used as the generic term for the Pentium 4 processor bus Processor Packaging Terminology Commonly used terms are explained here for clarification Intel Pentium 4 Processor in the 423 pin Package The entire product including processor core integrated heat spreader and interp
38. 7 VCC Power Other AU17 D54 Source Synch Input Output AR19 VSS Power Other AU19 D48 Source Synch Input Output AR21 VCC Power Other AU21 D50 Source Synch Input Output 61 Intel Pentium 4 Processor in the 423 pin Package Table 31 Pin Listing by Pin Number intel Table 31 Pin Listing by Pin Number Tram Pin Name pet Direction aan Pin Name a e Direction AU23 D47 Source Synch Input Output AW23 D46 Source Synch Input Output AU25 D42 Source Synch Input Output AW25 D44 Source Synch Input Output AU27 COMPO Power Other Input Output AW27 DP2 Common Clock Input Output AU29 D34 Source Synch Input Output AW29 D37 Source Synch Input Output AU31 D38 Source Synch Input Output AW31 D32 Source Synch Input Output AU33 D36 Source Synch Input Output AW33 DPO Common Clock Input Output AU35 D28 Source Synch Input Output AW35 DP1 Common Clock Input Output AU37 DBI1 Source Synch Input Output AW37 D19 Source Synch Input Output AU39 D21 Source Synch Input Output AW39 D29 Source Synch Input Output AV2 DBR Asynch GTL Output AV4 VSSA Power Other AV6 VCC Power Other AV8 VSS Power Other AV10 VCC Power Other AV12 VSS Power Other AV14 VCC Power Other AV16 VSS Power Other AV18 VCC Power Other AV20 VSS Power Other AV22 VCC Power Other AV24 VSS Power Othe
39. CC Power Other AL35 VSS Power Other AE37 D3 Source Synch Input Output AL37 D31 Source Synch Input Output AE39 D9 Source Synch Input Output AL39 DBIO Source Synch Input Output AF2 VSS Power Other AM2 VCC Power Other AF4 VCC Power Other AM4 VSS Power Other AF6 VSS Power Other AM6 VCC Power Other AF8 VCC Power Other AM8 VSS Power Other 60 In Intel Pentium 4 Processor in the 423 pin Package Table 31 Pin Listing by Pin Number Table 31 Pin Listing by Pin Number Am Pin Name eT Direction um Pin Name d g Direction AM36 VCC Power Other AR23 VSS Power Other AM38 D20 Source Synch Input Output AR25 VCC Power Other AN1 VCC Power Other AR27 VSS Power Other AN3 VSS Power Other AR29 VCC Power Other AN5 VCC Power Other AR31 VSS Power Other AN7 VSS Power Other AR33 VCC Power Other AN35 D27 Source Synch Input Output AR35 VSS Power Other AN37 VSS Power Other AR37 D25 Source Synch Input Output AN39 D23 Source Synch Input Output AR39 VSS Power Other AP2 VSS Power Other AT2 VCC Power Other AP4 VCC Power Other AT4 RESERVED AP6 VSS Power Other AT6 TESTHI2 Power Other Input AP8 BCLK1 System Bus Clk Input AT8 TESTHI3 Power Other Input AP
40. If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST ITP_CLK 1 0 Input ITP_CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP_CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system ITP_CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt reguest signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction
41. In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the system bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behaviour If RESETH is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant State If RESET is driven active while the processor is in the Sleep State the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering its lowest power state the Deep Sleep state by stopping the BCLK 1 0 inputs See Section 7 2 6 Once in the Sleep or Deep Sleep states the SLP pin must be de asserted if another asynchronous system bus event needs to occur The SLP pin has a minimum assertion of one BCLK period When the processor is in Sleep state it will not respond to interrupts or snoop transactions 77 a Intel Pentium 4 Processor in the 423 pin Package intel amp 7 2 6 7 3 78 Deep Sleep State State 6 Deep Sleep state is the lowest power state the processor can enter while
42. Intel Pentium 4 Processor in the 423 pin Package at 1 30 1 40 1 50 1 60 1 70 1 80 1 90 and 2 GHz Product Features m Available at 1 30 1 40 1 50 1 60 1 70 1 80 1 90 and 2 GHz m Binary compatible with applications running on previous members of the Intel microprocessor line m Intel NetBurst micro architecture m System bus frequency at 400 MHz m Rapid Execution Engine Arithmetic Logic Units ALUs run at twice the processor core frequency m Hyper Pipelined Technology m Advance Dynamic Execution Very deep out of order execution Enhanced branch prediction m Level 1 Execution Trace Cache stores 12K micro ops and removes decoder latency from main execution loops Datasheet m8 KB Level 1 data cache m 256 KB Advanced Transfer Cache on die full speed Level 2 L2 cache with 8 way associativity and Error Correcting Code ECC m 144 new Streaming SIMD Extensions 2 SSE2 instructions m Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance m Power Management capabilities System Management mode Multiple low power states m Optimized for 32 bit applications running on advanced 32 bit operating systems m 8 way cache associativity provides improved cache hit rate on reads store operations The Intel Pentium 4 processor is designed for high performance desktops and entry level workstations It is binary compatible with previous Intel Arc
43. MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 75V Processors jae oaa AEEA ENA ARER NESA EA EAS aE 39 Common Clock 100MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 75V Processors areri a ra EE AEAN E ERAEN a 40 Asynchronous GTL and TAP Signal Groups Overshoot Undershoot Tolerance 1 75V Processors jrin a a a E AS aae 40 Description Table for Processor Dimensions ese 45 Package Dynamic and Static Load Specifications eesssssusse 47 Processor Mass eiii IR EE 47 Processor Material Properties sssssssseeee nn 48 Pin Listing by Pin Name rE anaE Era AE EATI nennt nennen 51 Pin Listing oy Pin Number dsi e ete ete ee te eere EA vd 57 Signal Description s oes eet estende to oH OR Rx Ene esso a tr usse meu S ME DES 63 Processor Thermal Design Power essem 72 Power On Configuration Option Pins sseseeeeneeeenennee 75 Thermal Diode Parameters sia enne enan eanan aaa a a a aaae aaan ainakaa 79 Thermal Diode Interface ccccccccceceseeeeeececeeeeeeeeeeeeeeseeeeceeaaeeeeeeeeeeeeeeeesenninaes 80 Fan Heatsink Power and Signal Specifications ssessssuss 84 Boxed Processor Fan Heatsink Set Points ssssssssssseee 87 Intel Pentium 4 Processor in the 423 pin Package Introduction The Intel Pentium 4 Processor in the 423 pin Package socket with I
44. NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT This signal does not have on die termination Refer to section 2 5 for termination requirements IGNNE Input IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction 66 Intel Pentium 4 Processor in the 423 pin Package Table 32 Signal Description Page 5 of 8 Name Type Description INIT Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor system bus agents
45. R1 Power Other VID1 B2 Power Other Output VSS AR11 Power Other VID2 B4 Power Other Output VSS AR15 Power Other VID3 A3 Power Other Output VSS AR19 Power Other VID4 A1 Power Other Output VSS AR23 Power Other VSS AA3 Power Other VSS AR27 Power Other VSS AA37 Power Other VSS AR31 Power Other VSS AA7 Power Other VSS AR35 Power Other VSS AB2 Power Other VSS AR39 Power Other VSS AB6 Power Other VSS AR5 Power Other VSS AC1 Power Other VSS AU3 Power Other VSS AC39 Power Other VSS AV12 Power Other VSS AC5 Power Other VSS AV16 Power Other VSS AD4 Power Other VSS AV20 Power Other VSS AD8 Power Other VSS AV24 Power Other VSS AE3 Power Other VSS AV28 Power Other VSS AE7 Power Other VSS AV32 Power Other VSS AF2 Power Other VSS AV36 Power Other VSS AF36 Power Other VSS AV8 Power Other VSS AF6 Power Other VSS B12 Power Other 55 Intel Pentium 4 Processor in the 423 pin Package intel Table 30 Pin Listing by Pin Name Table 30 Pin Listing by Pin Name Pin Name Pin Number vr Direction Pin Name Pin Number cred Direction VSS B16 Power Other VSS M8 Power Other VSS B20 Power Other VSS N3 Power Other VSS B24 Power Other VSS N37 Power Other VSS B28 Power Other VSS N7 Power Other VSS B32 Power Other VSS P2 Powe
46. TL Output ITP_CLK1 AW1 TAP Input TMS D38 TAP Input LINTO H36 Asynch GTL Input TRDY A35 Common Clock Input LINT1 W35 Asynch GTL Input TRST R35 TAP Input LOCK A33 Common Clock Input Output VCC A37 Power Other MCERR D10 Common Clock Input Output VCC A39 Power Other PROCHOT F38 Asynch GTL Output VCC AA1 Power Other PWRGOOD AW9 Asynch GTL Input VCC AAS Power Other REQO C33 Source Synch Input Output VCC AB38 Power Other REQ1 ft D32 Source Synch Input Output VCC AB4 Power Other REQ2 F34 Source Synch Input Output VCC AB8 Power Other REQ3 D34 Source Synch Input Output VCC AC3 Power Other REQ4 F32 Source Synch Input Output VCC AC7 Power Other RESERVED AT4 VCC AD2 Power Other RESET AW11 Common Clock Input VCC AD6 Power Other RSO M36 Common Clock Input VCC AE1 Power Other RS1 N35 Common Clock Input VCC AE35 Power Other RS2 U35 Common Clock Input VCC AE5 Power Other RSP C9 Common Clock Input VCC AF4 Power Other SKTOCC A5 Power Other Output VCC AF8 Power Other SLP AW7 Asynch GTL Input VCC AG3 Power Other 53 Intel Pentium 4 Processor in the 423 pin Package intel Table 30 Pin Listing by Pin Name Table 30 Pin Listing by Pin
47. TLREF ue pci bec cante t t RE E e e E edes 11 2 2 Power and Ground Pins rerannnvvnnnnrnnnrnnnnrnnanvvnrsrrsnnnrnsssnsnnnnrssssnnnnnrsssrnnnnnsssrsnnnnne 11 2 3 Decoupling Guidelines sessi tenente 11 2 94 MOGDeco plirgz etta hi t E eats 12 2 3 2 System Bus AGTL Decoupling sssseeen 12 2 3 3 System Bus Clock BCLK 1 0 and Processor Clocking 12 2 4 Voltage Identificatior ote hr eee een 12 2 4 1 Phase Lock Loop PLL Power and Filter sees 13 2 5 Reserved Unused Pins and TESTHI 10 0 rrnrnnrnnnnnnnnrnrrrnnnnrvnrrnnrrnnrnrrrrrnnnnnr 15 2 6 System Bus Signal Groups ssssssssseeeee nne 16 2 7 Asynchronous G TEF Signals aiae en i en aaan aeaaaee aeaa ahneita 17 2 8 Test Access Port TAP Connection esses 17 2 9 Maximum Ranga issa a a E O AEA EATR EAT pedet debes 18 2 10 Processor DC Specifications sssssssssssssses eene 18 2 11 AGTL System Bus Specifications ssssssssssseseeeenneee 21 2 12 System Bus AC Specifications 22 2 13 Processor AC Timing Waveforms sssssssssseseeeeeenneeee nennen 25 System Bus Signal Quality Specifications 0 000 000 0000 eee 31 3 1 BCLK Signal Quality Specifications and Measurement Guidelines 31 3 2 System Bus Signal Quality Specifications and Measurement Guidelines 32 3 3 Syste
48. The tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of Vcc 3 GTLREF should be generated from Vcc by a voltage divider of 1 resistors or 1 matched resistors Refer to the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide for implementation details 4 Rrr is the on die termination resistance measured at Vo of the AGTL output driver Refer to processor I O buffer models for I V characteristics 5 COMP resistance must be provided on the system board with 196 resistors See the Intef Pentium 4 Processor and Inte 850 Chipset Platform Design Guide for implementation details 6 The Voc referred to in these specifications is the instantaneous Voc 7 A COMP Resistance of 43 2 1 is the preferred value System Bus AC Specifications The processor System bus timings specified in this section are defined at the processor core silicon and are thus not measurable at the processor pins See Chapter 5 0 for the Pentium 4 processor pin signal definitions Table 10 through Table 15 list the AC specifications associated with the processor system bus All AGTL timings are referenced to GTLREF for both 0 and 1 logic levels unless otherwise specified The timings specified in this section should be used in conjunction with the I O buffer models provided by Intel These I O buffer models which include package
49. Undershoot Intel Pentium 4 Processor in the 423 pin Package 2 This table assumes a 33MHz time domain 3 These specifications apply to 1 7V processors i e those with a VID 00110 Tolerance 1 75V Processors Absolute Absolute San Kerr EN Duration ns Duration ns Duration ns Notes 1254 V V 2 30 0 585 0 06 0 63 5 00 2 25 0 535 0 11 1 10 5 00 2 20 0 485 0 22 2 20 5 00 2 15 0 435 0 41 4 10 5 00 2 10 0 385 0 75 5 00 5 00 2 05 0 335 1 35 5 00 5 00 2 00 0 285 2 50 5 00 5 00 1 95 0 235 4 70 5 00 5 00 1 90 0 185 5 00 5 00 5 00 1 85 0 135 5 00 5 00 5 00 1 80 0 085 5 00 5 00 5 00 NOTES 1 These specifications are specified at the processor pad 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes 4 These specifications apply to 1 75V processors i e those with a VID 00100 Tolerance 1 75V Processors Absolute Absolute Li MU Ud Duration ns Duration ns Duration ns Notes 1234 V V 2 30 0 585 0 12 1 20 10 0 2 25 0 535 0 22 2 20 10 0 2 20 0 485 0 44 4 40 10 0 2 15 0 435 0 82 8 20 10 0 2 10 0 385 1 50 10 0 10 0 2 05 0 335 2 70 10 0 10 0 2 00 0 285 5 00 10 0 10 0 1 95 0 235 9 40 10 0 10 0 1 90 0 185 10 0 10 0 10 0 1 85 0 135 10 0 10 0 10 0 1 80 0 085 10 0 10 0 10 0 NOTES 1 These specification
50. ack tolerance for low to high transitions and Figure 14 shows ringback tolerance for high to low transitions Ringback Specifications for AGTL Asynchronous GTL and TAP Signal Groups Maximum Ringback Notes Signal Group Transition with Input Diodes Present Unit Figure All Signals 01 GTLREF 0 100 V 13 1 2 3 4 5 6 7 All Signals 1 0 GTLREF 0 100 V 14 1 2 3 4 5 6 7 NOTES All signal integrity specifications are measured at the processor silicon Unless otherwise noted all specifications in this table apply to all Pentium 4 processor frequencies Specifications are for the edge rate of 0 3 4 0V ns All values specified by design characterization Please see Section 3 3 for maximum allowable overshoot Ringback between GTLREF 100 mV and GTLREF 100 mV is not supported Intel recommends simulations not exceed a ringback value of GTLREF 200 mV to allow margin for other sources of system noise NORWOOD Intel Pentium 4 Processor in the 423 pin Package Figure 13 Low to High System Bus Receiver Ringback Tolerance Vcc 100 mV GTLREF 100 mV Noise Margin Vss Figure 14 High to Low System Bus Receiver Ringback Tolerance 3 3 3 3 1 Voc 100 mV GTLREF 100 mV Vss System Bus Signal Guality Specifications and Measurement Guidelines Overshoot Undershoot Guidelines Overshoot or undershoot is th
51. als A 31 3 BRO INIT SMI amp Setup Time BLISS U T46 Reset Configuration Signals A 31 3 2 20 BCLKs 7 2 BRO INIT SMIf Hold Time NOTES 1 2 3 24 Before the deassertion of RESET After clock that deasserts RESET After the assertion of RESET Intel Pentium 4 Processor in the 423 pin Package Table 15 TAP Signals AC Specifications 2 13 Parameter Min Max Unit Figure Notes T55 TCK Period 60 0 1000 ns 4 T56 TCK Rise Time 9 5 ns 4 4 T57 TCK Fall Time 9 5 ns 4 4 T58 TMS Rise Time 8 5 ns 4 4 T59 TMS Fall Time 8 5 ns 4 4 T60 TMS Clock to Output Delay 5 2 ns 5 T61 TDI Setup Time 0 ns 5 8 T62 TDI Hold Time 3 ns 5 8 T63 TDO Clock to Output Delay 0 5 3 5 ns 6 T64 TRST Assert Time 2 TCK 11 7 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Not 100 tested Specified by design characterization 3 All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins All TAP signal timings TMS TDI etc are referenced at GTLREF at the processor pins Rise and fall times are measured from the 20 to 80 points of the signal swing Referenced to the falling edge of TCK Referenced to the rising edge of FBO TCK at the debug port connector TRST is synchronized to TCK and is asserted for 5 TCK pe
52. ation and location should be documented in the platform documentation or on the system board itself Figure 32 shows the location of the fan power connector relative to the processor socket The system board power header should be positioned within 4 33 inches from the center of the processor socket Figure 31 Boxed Processor Fan Heatsink Power Cable Connector Description MT Straight sguare pin 3 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pin pitch 0 025 square pin width Waldom Molex P N 22 01 3037 or equivalent Match with straight pin friction lock header on motherboard Waldom Molex P N 22 23 2031 AMP P N 640456 3 or equivalent Table 37 Fan Heatsink Power and Signal Specifications 84 Description Min Typ Max Unit Notes 12V 12 volt fan power supply 10 2 12 13 8 V IC Fan current draw 300 mA SENSE SENSE frequency 2 PRSE 1 NOTE 1 System board should pull this pin up to Vcc with a resistor Intel Pentium 4 Processor in the 423 pin Package Figure 32 Acceptable System Board Power Header Placement 8 4 8 4 1 Relative to Processor Socket RHO 4 351 B Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cool
53. be connected to a system ground plane The processor Vcc pins must be supplied the voltage determined by the VID Voltage ID pins Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5 Failure to do so can result in timing violations or reduced lifetime of the component For further information and design guidelines refer to the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide 11 a Intel Pentium 4 Processor in the 423 pin Package intel amp 2 3 1 2 3 2 2 3 3 2 4 12 Vcc Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and keep a low interconnect resistance from the regulator or VRM pins to the socket Bulk decoupling for the large current swings when the part is powering on or entering exiting low power states must be provided by the voltage regulator solution VRM For more details on this topic refer to the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide System Bus AGTL Decoupling Pentium 4 processors int
54. cations apply to both data and address timings Valid delay timings for these signals are specified into the test circuit described in Figure 3 and with GTLREF at 2 3 Voc 290 Specification is for a minimum swing defined between AGTL Vi max to Vi min This assumes an edge rate of 0 3 V ns to 4 0V ns All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe This specification represents the minimum time the data or address will be valid before its strobe Refer to the Intel Pentium 4 Processor and Inte 850 Chipset Platform Design Guide for more information on the definitions and use of these specifications This specification represents the minimum time the data or address will be valid after its strobe Refer to the Intel Pentium 4 Processor and Inte 850 Chipset Platform Design Guide for more information on the definitions and use of these specifications 10 The rising edge of ADSTB must come approximately 1 2 BCLK period 5 ns after the falling edge of 11 ADSTB For this timing parameter n 1 2 and 3 for the second third and last data strobes respectively 12 The second data strobe falling edge of DSTBn must come approximately 1 4 BCLK period 2 5 ns after the first falling edge of DSTBp The third data strobe falling edge of DSTBp must come approximately 2 4 BCLK period 5 ns after the first falling edge of DSTBp T
55. cessor fan will operate at different speeds over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal temperature until the upper set point is reached At that Intel Pentium 4 Processor in the 423 pin Package point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adeguate air around the boxed processor fan heatsink that remains below the lower set point These set points represented in Figure 35 and Table 38 can vary by a few degrees from fan heatsink to fan heatsink Figure 35 Boxed Processor Fan Heatsink Set Points Lowest Moise Level 30 Highest Moise Level Bisher Jes Ening lacreasing Moise aad 40 50 Internal Chassis Temperature Degrees C Table 38 Boxed Processor Fan Heatsink Set Points Boxed Processor Fan Heatsink Set Point Boxed Processor Fan Speed C When the internal chassis temperature is below this set 36 point the fan operates at its lowest speed Recommended maximum internal chassis temperature for nominal operating environment When the internal chassis temperature is at this point the 40 fan operates between its lowest and highest speeds Recommended maximum internal chassis te
56. e absolute value of the maximum voltage above or below Vss The overshoot undershoot specifications limit transitions beyond Vcc or Vss due to the fast signal edge rates The processor can be damaged by repeated overshoot or undershoot events on any input output or I O buffer if the charge is large enough i e if the over undershoot is great enough Determining the impact of an overshoot undershoot condition reguires knowledge of the magnitude the pulse direction and the activity factor AF of the incident waveform Permanent damage to the processor is the likely result of excessive overshoot undershoot 33 a Intel Pentium 4 Processor in the 423 pin Package intel amp 3 3 2 3 3 3 3 3 4 34 When performing simulations to determine impact of overshoot and undershoot ESD diodes must be properly modelled ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection ESD diodes modelled within Intel I O buffer models do not clamp undershoot or overshoot and will yield correct simulation results If other I O buffer models are being used to characterize the Pentium 4 processor system bus care must be taken to ensure that ESD models do not clamp extreme voltage levels Intel I O buffer models also contain I O capacitance characterization Therefore removing the ESD diodes from an I O buffer model will impact results and may yield excessive overshoot undershoot Overshoot Undershoot Ma
57. e changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Pentium 4 Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel Intel logo Pentium and Intel NetBurst are trademarks or registered trademarks of Intel Corporation or it subsidiaries in the United States and other countries Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Copyright Intel Corporation 2001 Other brands and names may be claimed as the property of others intel Contents 1 0 2 0 3 0 4 0 5 0 Contents Tuiigote U les 6 y Rm 7 1 1 Terminology Hl Das 8 1 1 1 Processor Packaging Terminology eee 8 1 2 References te PEINE 9 Electrical Specifications sss 11 2 1 System B s and G
58. e time automatic mode is enabled AND a high temperature condition exists the 5090 duty cycle of the automatic mode will override the duty cycle selected by the On Demand mode An external signal PROCHOT processor hot is asserted any time the TCC is active either in Automatic or On Demand mode Bus snooping and interrupt latching are also active while the TCC is active The temperature at which the thermal control circuit activates is not user configurable and is not software visible Besides the thermal sensor and thermal control circuit the Thermal Monitor feature also includes one ACPI register one performance counter register three model specific registers MSR and one I O pin PROCHOT All are available to monitor and control the state of the Thermal Monitor feature Thermal Monitor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT i e upon the activation deactivation of TCC If automatic mode is disabled the processor will be operating out of specification and cannot be guaranteed to provide reliable results Regardless of enabling of the automatic or On Demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 135 C At this point the system bus signal THERMTRIP will go active and stay active until the processor has cooled down and RESET has been initiated THERMTRIP activation is
59. ection documents signal quality metrics used to derive topology and routing guidelines through simulation and all specifications are at the processor silicon and cannot be measured at the processor pins The Intel Pentium 4 Processor Overshoot Checker Tool is to be utilized to determine pass fail signal quality conditions found through simulation analysis with the Intel Pentium 4 Processor I O Buffer Models IBIS format This tool takes into account the specifications contained in this section Specifications for signal quality are for measurements at the processor core only and are only observable through simulation The same is true for all system bus AC timing specifications in Section 2 12 Therefore proper simulation of the Pentium 4 processor system bus is the only means to verify proper timing and signal quality metrics and Intel highly recommends simulation during system design and measurement during system analysis BCLK Signal Quality Specifications and Measurement Guidelines Table 16 describes the signal quality specifications for the processor system bus clock BCLK signals Figure 12 describes the signal quality waveform for the system bus clock at the processor silicon Specifications are measured at the processor silicon not the 423 pin Socket pins Table 16 BCLK Signal Quality Specifications Parameter Min Max Unit Figure Notes BCLK 1 0 Overshoot N A 0 30 V 12 BCLK 1 0 Undersh
60. ed maximum pulse duration to the signal being measured If the pulse duration measured is less than the pulse duration shown in the table then the signal meets the specifications Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive Determining if a System Meets the Over Undershoot Specifications The overshoot undershoot specifications listed in the following tables specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that each have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when you add the total impact of all overshoot events the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below Results from simulation may also be evaluated by utilizing the Intel Pentium 4 Processor Overshoot Checker Tool through the use of time voltage data files 1 Ensure no signal ever exceeds Vcc or 0 25V OR 2 If only one overshoot undershoot event occurs ensure it meets the over undershoot specifications in the following tables OR 3 If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF specifications If all of 35 a Intel Pentium 4 Processor in the 423
61. ed with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Chapter 6 0 of this document The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 33 in chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 33 and Figure 34 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 40 C Again meeting the processor s temperature specification is the responsibility of the system integrator 85 nu Intel Pentium 4 Processor in the 423 pin Package intel 86 Figure 34 nm Er i Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view i Oe id Fa J AIRFLOW Intel 8 4 2 Variable Speed Fan The boxed pro
62. egrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package Decoupling must also be provided by the system motherboard for proper AGTL bus operation For more information refer to the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide System Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the system bus interface speed as well as the core frequency of the processor As in previous generation processors the Pentium 4 processor core freguency is a multiple of the BCLK 1 0 freguency The Pentium 4 processor bus ratio multiplier is set at its default ratio at manufacturing No jumpers or user intervention is necessary the processor will automatically run at the speed indicated on the package Unlike previous processors the Pentium 4 processor uses a differential clocking implementation For more information on Pentium 4 processor clocking refer to the CK00 Clock Synthesizer Driver Design Guidelines Voltage Identification The VID specification for Pentium 4 processors is different from that of previous generations and is supported by the VRM 9 0 DC DC Convertor Design Guidelines The voltage set by the VID pins is the maximum voltage allowed by the processor A minimum voltage is provided in Table 5 and changes with frequency This allows processors running at a higher frequency to have a relaxed minimum voltage specification The s
63. elines for Veca and refer to the Intel Pentium 4 Processor and Inte 850 Chipset Platform Design Guide for complete implementation details VocseNnse Output Vocsense IS an isolated low impedance connection to processor core power Vcc It can be used to sense or measure power near the silicon with little noise 69 Intel Pentium 4 Processor in the 423 pin Package In 70 Table 32 Signal Description Page 8 of 8 Name Type Description VID 4 0 Output VID 4 0 Voltage ID pins can be used to support automatic selection of power supply voltages These pins are not signals but are either an open circuit or a short circuit to VSS on the processor The combination of opens and shorts defines the voltage reguired by the processor The VID pins are needed to cleanly support processor voltage specification variations See Table 2 for definitions of these pins The power supply must supply the voltage that is reguested by these pins or disable itself Vssa Input Vssa IS the isolated ground for internal PLL s VsssENsE Output Vsssensg IS an isolated low impedance connection to processor core Vas It can be used to sense or measure ground near the silicon with little noise Intel Pentium 4 Processor in the 423 pin Package Thermal Specifications and Design Considerations Note Intel Pentium 4 Processor in the 423 pin Package use an integrated the
64. gical low value Table 8 2 11 Table 9 Intel Pentium 4 Processor in the 423 pin Package 3 VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 VoH may experience excursions above Vcc However input signal drivers must comply with the signal quality specifications in Chapter 3 0 5 Refer to processor I O Buffer Models for I V characteristics 6 The Vcc referred to in these specifications is the instantaneous Vcc Asynchronous GTL and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vit Input Low Voltage 0 150 GTLREF 100mV V 5 Vi Input Low Voltage 0 150 Voc 2 0 30 Vin Input High Voltage GTLREF 100mV Voc V 4 5 Vin Input High Voltage Voc 2 0 30 Voc Vou Output High Voltage Voc V 3 4 5 lo Output Low Current 56 mA 6 lui Input Leakage Current 100 uA lio Output Leakage Current 100 uA NOTES Unless otherwise noted all specifications in this table apply to all processor frequencies Parameter will be measured at 9mA for use with system inputs All outputs are open drain Vin and Voy may experience excursions above Voc However input signal drivers must comply with the signal quality specifications in Chapter 3 0 The Vcc referred to in these specifications is the instantaneous Voc These specifications apply to the asynchronous GTL signal group The
65. gnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level For the Pentium 4 processor both overshoot and undershoot are referenced to Vgs It is important to note that overshoot and undershoot conditions are separate and their impacts must be determined independently Overshoot undershoot magnitude levels must observe the absolute maximum specifications listed in Table 18 through Table 21 These specifications must not be violated at any time regardless of bus activity or system state Within these specifications are threshold levels that define different allowed pulse durations Provided that the magnitude of the overshoot undershoot is within the absolute maximum specifications 2 3V for overshoot and 0 65V for undershoot the pulse magnitude duration and activity factor must all be used to determine if the overshoot undershoot pulse is within specifications Overshoot Undershoot Pulse Duration Pulse duration describes the total time an overshoot undershoot event exceeds the overshoot undershoot reference voltage The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Note 1 Oscillations below the reference voltage cannot be subtracted from the total overshoot undershoot pulse duration Activity Factor Activity Facto
66. ground by the processor System board designers may use this pin to determine if the processor is present SLP Input SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If the BCLK input is stopped while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state 68 Table 32 Signal Description Intel Pentium 4 Processor in the 423 pin Package Page 7 of 8 Name Type Description SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tristate its outputs STPCLK Input
67. he last data strobe falling edge of DSTBn must come approximately 3 4 BCLK period 7 5 ns after the first falling edge of DSTBp 13 This specification applies only to DSTBN 3 0 and is measured to the second falling edge of the strobe Table 13 Asynchronous GTL Signals AC Specifications T Parameter Min Max Unit Figure Notes 2 3 6 T35 Asynch GTL Input Pulse Width except PWRGOOD 2 EUS T36 PWRGOOD to RESET de assertion 1 10 ms 10 time T37 PWRGOOD Inactive Pulse Width 10 BCLKs 10 4 T38 PROCHOT pulse width 500 us 11 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 6 All AC timings for the Asynch GTL signals are referenced to the BCLKO rising edge at Crossing Voltage All Asynch GTL signal timings are referenced at GTLREF 3 These signals may be driven asynchronously 4 5 Length of assertion for PROCHOT does not equal internal clock modulation time Time is allocated after the Refer to the PWRGOOD definition for more details regarding the behavior of this signal assertion and before the deassertion of PROCHOT for the processor to complete current instruction execution See section Section 7 2 for additional timing requirements for entering and leaving the low power states Table 14 System Bus AC Specifications Reset Conditions T Parameter Min Max Unit Figure Notes T45 Reset Configuration Sign
68. her U7 VSS Power Other L35 VCC Power Other U35 RS2 Common Clock Input L37 BPRI Common Clock Input U37 THERMTRIP Asynch GTL Output L39 VSS Power Other U39 VCC Power Other M2 VCC Power Other V2 VSS Power Other M4 VSS Power Other V4 VCC Power Other M6 VCC Power Other V6 VSS Power Other M8 VSS Power Other V8 VCC Power Other M36 RSO Common Clock Input V36 D6 Source Synch Input Output M38 IGNNE Asynch GTL Input V38 VSS Power Other N1 VCC Power Other W1 VSS Power Other N3 VSS Power Other W3 VCC Power Other N5 VCC Power Other W5 VSS Power Other N7 VSS Power Other W7 VCC Power Other N35 RS1 Common Clock Input W35 LINT1 Asynch GTL Input N37 VSS Power Other W37 D2 Source Synch Input Output N39 VCC_SENSE Power Other Output W39 D8 Source Synch Input Output P2 VSS Power Other Y2 VCC Power Other P4 VCC Power Other Y4 VSS Power Other P6 VSS Power Other Y6 VCC Power Other P8 VCC Power Other Y8 VSS Power Other 59 Intel Pentium 4 Processor in the 423 pin Package Table 31 Pin Listing by Pin Number intel Table 31 Pin Listing by Pin Number TL Pin Name er Direction NOn Pin Name ee Direction Y36 VCC Power Other AF36 VSS Power Other Y38 DO Source Synch Input Output
69. hitecture processors The Pentium 4 processor provides great performance for applications running on advanced operating systems such as Windows 98 Windows ME Windows 2000 and UNIX This is achieved by the Intel NetBurst micro architecture which brings a new level of performance for system buyers The Pentium 4 processor extends the power of the Pentium lll processor with performance headroom for advanced audio and video internet capabilities Systems based on Pentium 4 processors also include the latest features to simplify system management and lower the total cost of ownership for large and small business environments The Pentium 4 processor offers great performance for today s and tomorrow s applications Order Number 249198 005 August 2001 Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may mak
70. ignal integrity and platform design methods become more critical than with previous processor families Design guidelines for the Pentium 4 processor system bus are detailed in the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide The AGTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the system board See Table 13 for GTLREF specifications Termination resistors are provided on the processor silicon and are terminated to its core voltage Vcc Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the system board for most AGTL signals Some AGTL signals do not include on die termination and must be terminated on the system board See Table 4 for details regarding these signals The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the system bus including trace lengths is highly recommended when designing a system Contact your Intel Field Representative to obtain the buffer models Intel Pentium 4 Processor I O Buffer Models Power and Ground Pins For clean on chip power distribution Pentium 4 processors have 111 Vcc power and 112 Vss ground inputs All power pins must be connected to Vcc while all Vgs pins must
71. implify the following discussion the system bus signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals which are dependant upon the rising edge of BCLK0 ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 3 identifies which signals are common clock source synchronous and asynchronous System Bus Pin Groups Page 1 of 2 Signal Group Type Signals AGTL Common Clock Input Synchronous BPRI DEFER RESETH RS 2 0 RSP TRDY to BCLK 1 0 Synchronous APL 01 ADS BINIT BNR BPM 5 0 2 BRO 2 AGTL Common Clock I O y 15 DBSY DP 3 0 DRDY HIT HITM LOCK to BCLK 1 0 MCERR Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO Synchronous 5 AGTL Source Synchronous I O t
72. independent of processor activity and does not generate any bus cycles Thermal Diode The Pentium 4 processor incorporates an on die thermal diode A thermal sensor located on the system board may monitor the die temperature of the Pentium 4 processor for thermal management long term die temperature change purposes Table 35 and Table 36 provide the diode parameter and interface specifications This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor Thermal Diode Parameters Symbol Min Typ Max Unit Notes forward bias 5 450 uA 2 n_ideality 0 9933 1 0045 1 0368 3 4 NOTES 1 Not 100 tested Specified by design characterization 2 Intel does not support or recommend operation of the thermal diode under reverse bias 3 At room temperature with a forward bias of 630 mV 4 n_ideality is the diode ideality factor parameter as represented by the diode equation I lo e Vd g nKT 1 79 Intel Pentium 4 Processor in the 423 pin Package 80 Table 36 Thermal Diode Interface Pin Name Pin Number Pin Description THERMDA H38 diode anode THERMDC E39 diode cathode Intel Pentium 4 Processor in the 423 pin Package Boxed Processor Specifications 8 1 Introduction The Intel Pentium 4 Processor in the 423 pin Package is also offered as an Intel boxed processor Intel boxed pr
73. information are available for the Pentium 4 processor in IBIS format AGTL layout guidelines are also available in the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guidelines Care should be taken to read all notes associated with a particular timing parameter System Bus Differential Clock Specifications T Parameter Min Nom Max Unit Figure Notes System Bus Frequency 100 MHz T1 BCLK 1 0 Period 10 0 10 2 ns 5 2 T2 BCLK 1 0 Period Stability 200 ps 3 4 T3 BCLK 1 0 High Time 3 94 5 6 12 ns 5 T4 BCLK 1 0 Low Time 3 94 5 6 12 ns 5 T5 BCLK 1 0 Rise Time 175 700 ps 5 5 T6 BCLK 1 0 Fall Time 175 700 ps 5 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor core frequencies 2 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 3 For the clock jitter specification refer to the CK00 Clock Synthesizer Driver Design Guidelines 4 In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 5 Slew rate is measured between the 35 and 65 points of the clock swing V to Vp Intel Pentium 4 Processor in the 423 pin Package Table 11 System
74. ink retention mechanisms and sockets are reguired for the Pentium 4 processor in the 423 pin package The socket for the Pentium 4 processor in the 423 pin package is called the 423 Pin Socket in this and other documentation Through hole ZIF technology will be used for the 423 Pin Socket Reference heat sink and retention mechanism designs have been developed with manufacturability as a high priority Hence mechanical assembly can be completed from the top of the motherboard and should not reguire any special tooling The Pentium 4 processor in the 423 pin package uses a new scalable system bus protocol referred to as the system bus in this document The Pentium 4 processor system bus utilizes a split transaction deferred reply protocol similar to that of the P6 processor family system bus but is not compatible with the P6 processor family system bus The system bus uses Source Synchronous Transfer SST of address and data to improve performance Whereas the P6 processor family transfers data once per bus clock the Pentium 4 processor transfers data four times per bus clock a Intel Pentium 4 Processor in the 423 pin Package intel amp 1 1 1 1 1 AX data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and
75. l operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 135 C This is signalled to the system by the THERMTRIP Thermal Trip pin Once activated the signal remains latched and the processor stopped until RESET goes active There is no hysteresis built into the thermal sensor itself as long as the die temperature drops below the trip level a RESET pulse will reset the processor and execution will continue If the temperature has not dropped below the trip level the processor will continue to drive THERMTRIP and remain stopped TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all system bus agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset This can be done with a 680 Q pull down resistor Voca Input Voca provides isolated power for the internal processor core PLL s Refer to the Intel Pentium 4 Processor and Inte 850 Chipset Platform Design Guide for complete implementation details VoclopLt Input Vccioeu Provides isolated power for internal processor system bus PLL s Follow the guid
76. learance is reguired around the fan heatsink to ensure unimpeded airflow for proper cooling see Figure 33 and Figure 34 The physical space reguirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 29 Side Views and Figure 30 Top View The airspace reguirements for the boxed processor fan heatsink must also be incorporated into new platform and system designs Airspace reguirements are shown in Figure 33 and Figure 34 Note that some figures have datum shown marked with alphabetic designations to clarify relative dimensioning Figure 29 Side View Space Reguirements for the Boxed Processor 82 Intel Pentium 4 Processor in the 423 pin Package Figure 30 Top View Space Requirements for the Boxed Processor 8 2 2 8 2 3 m mrd8 04 3 230 99 29 3 909 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams See Chapter 4 0 and the Intel Pentium 4 Processor Thermal Design Guidelines for details on the processor weight and heatsink requirements The boxed Pentium 4 processor requires direct attach of the retention mechanism to the chassis wall as described in the Intel Pentium 9 4 Processor Thermal Mechanical Design Guide Boxed Processor Retention Mechanism and Fan Heatsink Supports The boxed processor require
77. ltage Definitions sssssessseeeeeneeennnns 21 System Bus Differential Clock Specifications sess 22 System Bus Common Clock AC Specifications sss 22 System Bus Source Synch AC Specifications AGTL Signal Group 23 Asynchronous GTL Signals AC Specifications sssssssss 24 System Bus AC Specifications Reset Conditions ssssssssss 24 TAP Signals AC Specifications sss eee 25 BCLK Signal Quality Specifications sse 31 Ringback Specifications for AGTL Asynchronous GTL and TAP Signal Groups 00 ccccecccesceeeseeeeesaeeeeeeceeeaaeesneaaaeenaeeeseaeeseeeaesesaeeeenaaees 32 Source Synchronous 400MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 7V Processors ssssssss 37 Source Synchronous 200MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 7V Processors ssssssssss 37 Common Clock 100MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 7V Processors ssssssss 38 Asynchronous GTL and TAP Signal Groups Overshoot Undershoot Tolerance 1 7V Processors sssssssssss 38 Source Synchronous 400MHz AGTL Signal Group Overshoot Undershoot Tolerance 1 75V Processors mernrnnvnnnonnnnnvnnonnnnnvnnnennnnnennennnnneneeennnnnnneennnnnnnee 39 Source Synchronous 200
78. ly initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the AutoHALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information 75 a Intel Pentium 4 Processor in the 423 pin Package intel e The system can generate a STPCLK while the processor is in the AutoH ALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in AutoHALT Power Down state the processor will process bus snoops Figure 27 Stop Clock State Machine 7 2 3 76 HALT Instruction and HALT Bus Cycle Generated 2 Auto HALT Power Down State 1 Normal State BCLK running SRE En INTR NMI Normal execution Snoops and interrupts allowed SMW RESET gt Snoop Snoop STPCLK STPCLK Event Event Asserted De asserted Occurs Serviced 4 HALT Grant Snoop State SNOOP Event Occurs Stop Grant State BCLK running Snoops and interrupts allowed BCLK running Service snoops to caches Snoop Event Serviced SLP SLP Asserted De asserted 5 Sleep State BCLK running No snoops or interrupts allowed BCLK BCLK Input Input Stopped Restarted 6 Deep Sleep State BCLK stopped No snoops or interrupts allowed Stop Grant State State 3 When the STPCLK pi
79. lysis Measurements For Thermal Specifications Processor Case Temperature Measurement The maximum and minimum case temperature Tcasg for the Pentium 4 processor is specified in Table 33 This temperature specification is meant to ensure correct and reliable operation of the processor Figure 24 illustrates where Intel recommends that Tcasg thermal measurements should be made Figures 25 and 26 illustrate two possible measuring techniques Refer to the Intel Pentium 4 Processor Thermal Design Guidelines for more information Figure 24 Guideline Locations for Case Temperature TcAsg Thermocouple Placement Figure 25 Technique for Measuring with 0 Degree Angle Attachment Measure from edge of processor 1 125 Measure TCASE at this point LJ Thermal grease should cover the entire surface of the Integrated Heat Spreader 000874b T nr 73 Intel Pentium 4 Processor in the 423 pin Package Figure 26 Technique for Measuring with 90 Degree Angle Attachment 74 Intel Pentium 4 Processor in the 423 pin Package Features 7 1 Table 34 7 2 7 2 1 7 2 2 Power On Configuration Options Several configuration options can be configured by hardware The Intel Pentium 4 Processor in the 423 pin Package sample its hardware configuration at reset on the active to inactive transition of RESET For specifications on these options please refer
80. m 4 Processor EMI Guidelines Voltage Regulator Module VRM 9 0 DC DC Converter Design Guidelines 423 Pin Socket PGA423 Design Guidelines Intel Architecture Software Developer s Manual 243193 Volume I Basic Architecture 243190 Volume ll Instruction Set Reference 243191 Volume Ill System Programming Guide 243192 Inte Pentium 4 Processor I O Buffer Models Inte Pentium 4 Processor Overshoot Checker Tool Note 1 Contact your Intel representative for the latest revision of the documents without order numbers 2 The I O Buffer Models are in IBIS format Intel Pentium 4 Processor in the 423 pin Package 10 intel 2 0 Intel Pentium 4 Processor in the 423 pin Package Electrical Specifications 2 1 2 2 2 3 System Bus and GTLREF Most system bus signals of the Intel Pentium 4 Processor in the 423 pin Package system bus signals use Assisted Gunning Transceiver Logic AGTL signalling technology As with the Intel P6 family of microprocessors this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Unlike the P6 processor family the termination voltage level for the Pentium 4 processor AGTL signals is Vcc the operating voltage of the processor core P6 family processors utilize a fixed 1 5V termination voltage known as Vr Because of the speed improvements to data and address busses s
81. m Bus Signal Quality Specifications and Measurement Guidelines 33 3 3 1 Overshooi Undershoot Guidelines sssssssees 33 3 3 2 Overshoot Undershoot Magnitude sssssssseee 34 3 3 8 Overshooi Undershoot Pulse Duration sssseeees 34 3 3 4 Activity FACTO Ns iuis iet eio rna Pax eie E fee Rura Dep 34 3 3 5 Reading Overshoot Undershoot Specification Tables 35 3 3 6 Determining if a System Meets the Over Undershoot Specifications 35 Package Mechanical Specifications sss 43 4 1 Package Load Specifications ssssssssssssseeeneenneee 46 4 2 Processor Insertion Specifications sssssssssseeeeenneee 47 4 3 Processor Mass Specifications esssssssssssseeneenenenn 47 4 4 Processor Material Sonni nirna Yd NO eed eee eee Fd satel 47 4 5 Processor Markings eer emiten Dee at hid Hee tp erri 48 4 6 Processor Pin Out Coordinates sssssssssesssee eene 48 Pin Listing and Signal Definitions sse 51 5 1 Processor Pin Assignments ssssssssseeee enne eee enn 51 5 1 1 Pin Listing by Pin Name rrennrnonnrrrnnnnnnnrrnnrnrnnrrnnnrenrnrenrrnnnrrenersnsrrrnerenennr 51 5 1 2 Pin Listing by Pin Number eerannrrrnnnnnnnvrnnnnrnnrrnnnrnnnnrrnnrrrnrrennrsnsrrrnerenennr 57 Contents 6 0 7
82. mpedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe The processor should not be subjected to any static Vc and lc combination wherein Vog exceeds Vec mip 0 055 1 lcc lcc max V Moreover Voc should never exceed Vec max VID Failure to adhere to this specification can shorten the processor lifetime i 5 Maximum current is defined at Vcc mip 6 7 The maximum instantaneous current the processor will draw while the thermal control circuit is active as The current specified is also for AutoHALT State indicated by the assertion of PROCHOT is the same as the maximum lcc for the processor Icc Stop Grant leg Sleep and lcc Deep Sleep are specified at Voc max These specifications apply to 1 7V processors i e those with a VID 00110 10 These specifications apply to 1 75V processors i e those with a VID 00100 Table 6 System Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 5 Vy Input High Voltage 0 660 0 710 0 850 V 5 Vcnoss Crossing Voltage 0 45 Vj Vj 0 5 Vy V_ 0 55 Vy V V 5 2 3 Vov Overshoot N A N A 0 3 V 5 4 Vus Undershoot N A N A 0 3 V 5 5 VnBM Ringback Margin 0 200 V 5 6 VTH Threshold Region Vcnoss 0 100 Veross 0 100 V 5 7 NOTES 1 o oi i co N
83. mperature for worst case operating environment 45 When the internal chassis temperature is above this set point the fan operates at its highest speed NOTES 1 Set points may vary 1 C The internal chassis temperature should be kept below 40 C When the internal chassis temperature increases above 45 C the Thermal Monitor may become active see Section 7 3 Meeting the processor s temperature specification see Chapter 6 0 is the responsibility of the system integrator 87 Intel Pentium 4 Processor in the 423 pin Package 88 Intel Pentium 4 Processor in the 423 pin Package Debug Tools Specifications 9 1 9 1 1 Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Pentium 4 processor systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Pentium 4 processor systems the LAI is critical in providing the ability to probe and capture system bus signals There are two sets of considerations to keep in mind when designing a Pentium 4 processor system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the Pentium 4 processor
84. n is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state Since the AGTL signal pins receive power from the system bus these pins should not be driven allowing the level to return to Vcc for minimum power drawn by the termination resistors in this state In addition all other input pins on the system bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state 7 2 4 7 2 5 Intel Pentium 4 Processor in the 423 pin Package RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal When re entering the Stop Grant state from the Sleep state STPCLK should only be de asserted one or more bus clocks after the de assertion of SLP A transition to the HALT Grant Snoop state will occur when the processor detects a snoop on the system bus see Section 7 2 4 A transition to the Sleep state see Section 7 2 5 will occur with the assertion of the SLP signal While in the Stop Grant State SMI INIT BINIT and LINT 1 0 will
85. nfiguration Timings cox DTI CO IK T Configuration aome GNNER MH ve LINT 1 0 Ta T37 PWRGOOD Inactive Pulse Width Tb T36 PWRGOOD to RESET de assertion time Tc T46 Reset Configuration Signals Hold Time 29 Intel Pentium 4 Processor in the 423 pin Package 30 Figure 11 Test Reset Timings tel TRST i Tq Tq T64 T38 TRST Pulse Width PROCHOT Pulse Width Intel Pentium 4 Processor in the 423 pin Package System Bus Signal Quality Specifications 3 1 Source synchronous data transfer requires the clean reception of data signals and their associated strobes Ringing below receiver thresholds non monotonic signal edges and excessive voltage swing will adversely affect system timings Ringback and signal non monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines or cause incorrect latching of data Excessive signal swings overshoot and undershoot are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded Additionally overshoot and undershoot can cause timing degradation due to the build up of inter symbol interference IST effects For these reasons it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing This s
86. nrrnnnnvvnrnnrrnnnnnnnnrrrrennnnnnnnennn 28 Source Synchronous 4X Timings sse 29 Power On Reset and Configuration Timings sseene 29 Test BReset Timings ime tec t Dee free ert E rep e teret uci 30 BCLK 1 0 Signal Integrity Waveform sse 32 Low to High System Bus Receiver Ringback Tolerance sssss 33 High to Low System Bus Receiver Ringback Tolerance ssses 33 Maximum Acceptable Overshoot Undershoot Waveform suuuss 41 Exploded View of Processor Components on a System Board 43 Processor Package i ccrte eed aset cpi accu AFON yi FO 44 Processor Cross Section and Keep in ssssssssssssseeene 45 Processor PiriD tail iti rete err er t cH ERE er en Ede aeg 46 IHS Flatness Specification srnrnnrrnnnnnvnnnvrrrnnnnrnnnnnrnnnnrnnnnnnrrnennrnenrnnressrrnnnnnnnnenn 46 Processor Markings 0 erit eine eene Huet ie teo Hip aridi 48 Processor Pinout Diagram Bottom View sese 49 Example Thermal Solution Not to scale 71 Guideline Locations for Case Temperature TCASE Thermocouple Placement73 Technique for Measuring with 0 Degree Angle Attachment 73 Technique for Measuring with 90 Degree Angle Attachment 73 Stop Clock State Machine rrrrnnnvvrrrrrnnrvvrrr
87. ntel NetBurst micro architechture is based on a new 32 bit micro architecture that operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA 32 processors While based on the Intel NetBurst micro architecture it still maintains the tradition of compatibility with IA 32 software The Intel NetBurst micro architecture features include hyper pipelined technology a rapid execution engine a 400 MHz system bus and an execution trace cache The hyper pipelined technology doubles the pipeline depth in the Pentium 4 processor allowing the processor to reach much higher core freguencies The rapid execution engine allows the two integer ALUs in the processor to run at twice the core freguency which allows many integer instructions to execute in 1 2 clock tick The 400 MHz system bus is a guad pumped bus running off a 100 MHz system clock making 3 2 GB sec data transfer rates possible The execution trace cache is a level 1 cache that stores approximately 12k decoded micro operations which removes the decoder from the main execution path thereby increasing performance Improved features within the Intel NetBurst micro architecture include advanced dynamic execution advanced transfer cache enhanced floating point and multi media unit and Streaming SIMD Extensions 2 SSE2 The advanced dynamic execution improves speculative execution and branch prediction internal
88. o assoc A 35 1 7 ADSTB1 strobe D 15 0 DBIO DSTBPO DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 Intel Pentium 4 Processor in the 423 pin Package Table 3 System Bus Pin Groups Page 2 of 2 2 7 2 8 Signal Group Type Signals AGTL Strobes see ADSTB 1 0 f DSTBP 3 0 DSTBN 3 0 7 A20M DBR IGNNE INIT LINTO INTR LINT1 NMI Asynchronous GTL Input PWRGOOD SMI SLP STPCLK Asynchronous GTL Output FERR IERR THERMTRIP PROCHOTH TAP Input Gyncyonous TOK TDI TMS TRST TAP Output lg DBR3 TDO System Bus Clock Clock BCLK 1 0 ITP_CLK 1 0 Veo Veca Vocioeu VID 4 0 Veg Vega GTLREF 3 0 Power Other COMP 1 0 RESERVED SKTOCG TESTHI 10 0 THERMDA THERMDC Veg sense Vss SENSE NOTE 1 Refer to Section 5 2 for signal descriptions 2 These AGTL signals do not have on die termination and must be terminated on the system board 3 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 4 These signal groups are not terminated by the processor Refer to section 2 5 and the ntel amp Pentium 4 Processor and Intel 850 Chipset Platform Design Guide and ITP700 Debug Port De
89. ocessors are intended for system integrators who build systems from system boards and components The boxed Pentium 4 processor will be supplied with a cooling solution This chapter documents platform and system requirements for the cooling solution that will be supplied with the boxed Pentium 4 processor This chapter is particularly important for OEMs that manufacture platforms for system integrators Unless otherwise noted all figures in this chapter are dimensioned in millimeters and in inches in brackets Figure 28 shows a mechanical representation of a boxed Pentium 4 processor NOTE Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designer s responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platform and chassis Figure 28 Mechanical Representation of the Boxed Pentium 4 Processor 8 2 Note The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Mechanical Specifications This section documents the mechanical specifications of the boxed Pentium 4 processor fan heatsink 81 a Intel Pentium 4 Processor in the 423 pin Package intel e 8 2 1 Boxed Processor Fan Heatsink Dimensions The boxed processor will be shipped with an unattached fan heatsink C
90. ock Input Output C15 A34 Source Synch Input Output C17 A21 Source Synch Input Output C19 A23 Source Synch Input Output C21 A29 Source Synch Input Output C23 A10 Source Synch Input Output C25 A123 Source Synch Input Output C27 A18 Source Synch Input Output C29 A4 Source Synch Input Output C31 A6 Source Synch Input Output C33 REQO Source Synch Input Output C35 VSS Power Other C37 VCC Power Other C39 VSS Power Other D2 VCC Power Other D4 VSS Power Other D6 BPM5 Common Clock Input Output D8 INIT Asynch GTL Input 57 Intel Pentium 4 Processor in the 423 pin Package Table 31 Pin Listing by Pin Number intel Table 31 Pin Listing by Pin Number PLN Pin Name oer Direction aus Pin Name A Direction D10 MCERR Common Clock Input Output F10 BPM2 Common Clock Input Output D12 A35 Source Synch Input Output F12 BPM1 Common Clock Input Output D14 AP1 Common Clock Input Output F14 GTLREF Power Other Input D16 TESTHI8 Power Other Input F16 APO Common Clock Input Output D18 TESTHI9 Power Other Input F18 BINIT Common Clock Input Output D20 TESTHI10 Power Other Input F20 A28 Source Synch Input Output D22 A25 Source Synch Input Output F22 A24 Source Synch In
91. oot N A 0 30 V 12 BCLK 1 0 Ringback Margin 0 20 N A V 12 BCLK 1 0 Threshold Region N A 0 10 V 12 2 NOTES 1 Unless otherwise noted all specifications in this table apply to all Pentium 4 processor frequencies 2 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal can dip back to after passing the Vj rising or Vi falling voltage limits This specification is an absolute value 31 Intel Pentium 4 Processor in the 423 pin Package in Figure 12 BCLK 1 0 Signal Integrity Waveform 3 2 32 Table 17 Overshoot BCLK1 VH Rising Edge Ringback Keen ty eee Crossing Crossing Ringback Threshold I Voltage Voltage Margin Region z TE Falling Edge Ringback BCLKO VL Undershoot System Bus Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL layout guidelines which are available in the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide Table 17 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor silicon Signal quality measurements cannot be made at the processor pins The Pentium 4 processor maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 18 through Table 21 Figure 13 shows the system bus ringb
92. oser Pentium 4 processor Throughout this document Pentium 4 processor refers to the Intel Pentium 4 Processor in the 423 pin Package Interposer The structure on which the processor core package and I O pins are mounted Processor core The processor s execution engine All AC timings and signal integrity specifications are to the silicon of the processor core Integrated heat spreader The surface used to make contact between a heatsink or other thermal solution and the processor Abbreviated as IHS 423 Pin Socket The connector which mates the Pentium 4 processor to the system board Retention mechanism The support structure that is mounted on the system board to provide added support and retention for heatsinks OLGA Organic Land Grid Array Package Microprocessor packaging using flip chip design where the processor is attached to the substrate face down for better signal integrity more efficient heat removal and lower inductance 1 2 Intel Pentium 4 Processor in the 423 pin Package References Material and concepts available in the following documents may be beneficial when reading this document Table 1 References Document Order Number Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide AP 485 Intel Processor Identification and the CPUID Instruction 241618 Intef Pentium 4 Processor Thermal Design Guidelines Intef Pentiu
93. pecifications have been set such that one voltage regulator can work with all supported frequencies Pentium 4 processors use five voltage identification pins VID 4 0 to support automatic selection of power supply voltages Table 2 specifies the voltage level corresponding to the state of VID 4 0 A 1 in this table refers to an open pin and a 0 refers to low voltage level The definition provided in Table 2 is not related in any way to previous processors or VRMs If the processor socket is empty VID 4 0 11111 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself See the VRM 9 0 DC DC Converter Design Guidelines for more details Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Intel Pentium 4 Processor in the 423 pin Package Table 2 Voltage Identification Definition 2 4 1 Processor Pins VID4 VID3 VID2 VID1 VIDO Vcc max 1 1 1 1 1 VRM output off 1 1 1 1 0 1 100 1 1 1 0 1 1125 1 1 1 0 0 1 150 1 1 0 1 1 1 175 1 1 0 1 0 1 200 1 1 0 0 1 1 225 1 1 0 0 0 1 250 1 0 1 1 1 1 275 1 0 1 1 0 1 300 1 0 1 0 1 1 325 1 0 1 0 0 1 350 1 0 0 1 1 1 375 1 0 0 1 0 1 400 1 0 0 0 1 1 425 1 0 0 0 0 1 450 0 1 1 1 1 1 475 0 1 1 1 0 1 500 0 1 1 0 1 1 525 0 1 1 0 0 1 550 0 1 0 1 1 1 575 0 1 0 1 0 1 600 0 1 0 0 1 1 6
94. put Output D24 A16 Source Synch Input Output F24 COMP1 Power Other Input Output D26 A19 Source Synch Input Output F26 AQ Source Synch Input Output D28 A8 Source Synch Input Output F28 ATH Source Synch Input Output D30 Abit Source Synch Input Output F30 A3 Source Synch Input Output D32 REO1F Source Synch Input Output F32 REQ4 Source Synch Input Output D34 REQ3 Source Synch Input Output F34 REQ2 Source Synch Input Output D36 HITM Common Clock Input Output F36 ADS Common Clock Input Output D38 TMS TAP Input F38 PROCHOT Asynch GTL Output E1 VCC Power Other G1 VSS Power Other E3 VSS Power Other G3 VCC Power Other E5 VCC Power Other G5 VSS Power Other E7 BPM3 Common Clock Input Output G7 VCC Power Other E9 VCC Power Other G9 VCC Power Other E11 VSS Power Other G11 VSS Power Other E13 VCC Power Other G13 VCC Power Other E15 VSS Power Other G15 VSS Power Other E17 VCC Power Other G17 VSS Power Other E19 VSS Power Other G19 VCC Power Other E21 VCC Power Other G21 ADSTB1 Source Synch Input Output E23 VSS Power Other G23 VSS Power Other E25 VCC Power Other G25 ADSTBO Source Synch Input Output E27 VSS Power Other G27 VSS Power Other E29 VCC Power Other G29 VCC Power Other E31 VSS Power Other G31 VSS Power Other E33 VCC Power Other G33 VCC Power Other E35 BNR Common Clock Input Output G35 VSS Power Other E37 VSS Power Other G37 DRDY Common Clock Input Output E39 THERMDC Power Other G39 VCC Power Other F2 VSS Power O
95. r AV26 VCC Power Other AV28 VSS Power Other AV30 VCC Power Other AV32 VSS Power Other AV34 VCC Power Other AV36 VSS Power Other AV38 VCC Power Other AW1 ITP_CLK1 TAP Input AW3 VCCIOPLL Power Other AW5 TESTHI7 Power Other Input AW7 SLP Asynch GTL Input AW9 PWRGOOD Asynch GTL Input AW11 RESET Common Clock Input AW13 D58 Source Synch Input Output AW15 DBI3 Source Synch Input Output AW17 D62 Source Synch Input Output AW19 D52 Source Synch Input Output AW21 D51 Source Synch Input Output 62 Intel Intel Pentium 4 Processor in the 423 pin Package 5 2 Alphabetical Signals Reference Table 32 Signal Description Page 1 of 8 Name Type Description A 35 3 Input Output A 35 3 Address define a 236 pyte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the Pentium 4 processor in the 423 pin package system bus A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 pins to determine power on configuration See Section 7 1 for more details A20M Input If A20Mz Address 20
96. r AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of any common clock signal is every other clock an AF 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle Thus an AF 0 01 indicates that the specific overshoot or undershoot waveform occurs one time in every 200 clock cycles For source synchronous signals address data and associated strobes the activity factor is in reference to the strobe edge since the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe An AF 1 indicates that the specific overshoot or undershoot waveform occurs every strobe cycle The specifications provided in Table 18 through Table 21 show the maximum pulse duration allowed for a given overshoot undershoot magnitude at a specific activity factor Each table entry is independent of all others meaning that the pulse duration reflects the existence of overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just 3 3 5 3 3 6 Intel Pentium 4 Processor in the 423 pin Package meets the pulse duration for a specific magnitude where the AF lt 1 means that there can be no other overshoot undershoot events even of lesser magnitude note that if AF 1 then the event occurs at all times and no other events can occur Note 1 Activit
97. r components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate 17 Intel Pentium 4 Processor in the 423 pin Package In 2 9 Table 4 2 10 18 voltage level Similar considerations must be made for TCK TMS and TRST Two copies of each signal may be required with each driving a different voltage level Refer to Chapter 9 0 for more detailed information Maximum Ratings Table 4 lists the processor s maximum environmental stress ratings Functional operation at the absolute maximum and minimum is neither implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating parameters are listed in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Processor DC Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Processor storage TSTORAGE temperature 40 85 C Any processor supply E Voc voltage with respect to Vsg 9 3 p y 1 AGTL buffer DC input VinaGTL voltage with respect to Vss 0 3 24 y Asynch GTL buffer DC Vinasynch GTL input voltage with respect 0 3 2 1 V to Vas
98. r Other VSS B38 Power Other VSS P6 Power Other VSS B8 Power Other VSS R1 Power Other VSS C35 Power Other VSS R5 Power Other VSS C39 Power Other VSS T4 Power Other VSS D4 Power Other VSS T8 Power Other VSS E11 Power Other VSS U3 Power Other VSS E15 Power Other VSS U7 Power Other VSS E19 Power Other VSS V2 Power Other VSS E23 Power Other VSS V38 Power Other VSS E27 Power Other VSS V6 Power Other VSS E3 Power Other VSS W1 Power Other VSS E31 Power Other VSS W5 Power Other VSS E37 Power Other VSS Y4 Power Other VSS F2 Power Other VSS Y8 Power Other VSS F6 Power Other VSS SENSE R39 Power Other Output VSS G1 Power Other VSSA AV4 Power Other VSS G11 Power Other VSS G15 Power Other VSS G17 Power Other VSS G23 Power Other VSS G27 Power Other VSS G31 Power Other VSS G35 Power Other VSS G5 Power Other VSS H4 Power Other VSS H8 Power Other VSS J3 Power Other VSS J7 Power Other VSS K2 Power Other VSS K6 Power Other VSS L1 Power Other VSS L39 Power Other VSS L5 Power Other VSS M4 Power Other 56 intel 5 1 2 Intel Pentium 4 Processor in the 423 pin Package Pin Listing by Pin Number Table 31 contains a listing of the Pentium 4 processor pins in order by pin number Table 31 Pin Listing by Pin Number Table 31 Pin Listing by Pin Number Pin Signal Buffer
99. riods while TMS is asserted Specification for a minimum swing defined between TAP Vi max to Vi min This assumes a minimum edge rate of 0 5V ns B H ONO Processor AC Timing Waveforms The following figures are used in conjunction with the AC timing tables Table 10 through Table 15 Note For Figure 4 through Figure 11 the following apply 1 All common clock AC timings for AGTL signals are referenced to the Crossing Voltage Vcnoss of the BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at GTLREF at the processor core 2 All source synchronous AC timings for AGTL signals are referenced to their associated strobe address or data at GTLREF Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at GTLREF at the processor silicon 3 All AC timings for AGTL strobe signals are referenced to BCLK 1 0 at Vcgoss All AGTL strobe signal timings are referenced at GTLREF at the processor silicon 4 All AC timings for the TAP signals are referenced to the TCK signal at GTLREF at the processor pins All TAP signal timings TMS TDI etc are referenced at the processor pins The circuit used to test the AC specifications is shown in Figure 3 25 Intel Pentium 4 Processor
100. rmal heat spreader for heatsink attachment which is intended to provide for multiple types of thermal solutions This section will provide data necessary for development of a thermal solution See Figure 23 for an exploded view of an example Pentium 4 processor thermal solution This is for illustration purposes only For further thermal solution design details please refer to the Intel Pentium 4 Processor Thermal Design Guidelines The processor is either shipped by itself or with a heatsink for boxed processors See Chapter 8 0 for details on boxed processors Figure 23 Example Thermal Solution Not to scale Heatsink Processor Retention Mechanism 423 pin Socket 71 Intel Pentium 4 Processor in the 423 pin Package In 6 1 Thermal Specifications Table 33 specifies the thermal design power dissipation envelope for Pentium 4 processors Analysis indicates that real applications are unlikely to cause the processor to consume its maximum possible power consumption Intel recommends that system thermal designs target the Thermal Design Power indicated in Table 33 The Thermal Monitor feature refer to Section 7 3 is intended to protect the processor from overheating when running high power code that exceeds the recommendations in this table For more details on the usage of this feature refer to Section 7 3 In all cases the Thermal Monitor feature must be enabled for the processor
101. rnnnvvenrrrnnrvererrnnnrnesrrrnnnvererrnnnnesrrennn 76 Mechanical Representation of the Boxed Pentium 4 Processor 81 Side View Space Requirements for the Boxed Processor ssuuuse 82 Top View Space Requirements for the Boxed Processor esssss 83 Boxed Processor Fan Heatsink Power Cable Connector Description 84 Acceptable System Board Power Header Placement Relative to Processor Socket sssssssssssssseseeeeeee eene 85 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view 86 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view 86 Boxed Processor Fan Heatsink Set Points ssssssssssssseeeee 87 Contents Tables OONDOOaABRWND 19 20 21 22 23 24 References cista de e ub s e Rte bet ederet ektet 9 Voltage Identification Definition eeeeeeeeeenn enn 13 System Bus Pin Groups sssssssssssseneeeeenen enne nennen nens 16 Processor DC Absolute Maximum Ratings ssseseeeeeene 18 Voltage and Current Specifications sess 19 System Bus Differential BCLK Specifications sss 20 AGTL Signal Group DC Specifications srrnonrrnnnnvrnnnnvvnnrrrrnnnnrnnnrnrennnnrnnnrnnennn 20 Asynchronous GTL and TAP Signal Group DC Specifications 21 AGTL Bus Vo
102. s are specified at the processor pad 2 Assumes a BCLK period of 10 ns 39 Intel Pentium 4 Processor in the 423 pin Package 40 3 AF is referenced to associated source synchronous strobes 4 These specifications apply to 1 75V processors i e those with a VID 00100 Tolerance 1 75V Processors Table 24 Common Clock 100MHz AGTL Signal Group Overshoot Undershoot Absolute Absolute ke U a Duration ns Duration ns Duration ns Notes 1 234 V V 2 30 0 585 0 24 2 40 20 0 2 25 0 535 0 44 4 40 20 0 2 20 0 485 0 88 8 80 20 0 2 15 0 435 1 64 16 4 20 0 2 10 0 385 3 00 20 0 20 0 2 05 0 335 5 40 20 0 20 0 2 00 0 285 10 0 20 0 20 0 1 95 0 235 18 8 20 0 20 0 1 90 0 185 20 0 20 0 20 0 1 85 0 135 20 0 20 0 20 0 1 80 0 085 20 0 20 0 20 0 NOTES 1 These specifications are specified at the processor pad 2 BCLK period is 10 ns 3 AF is referenced to associated source synchronous strobes 4 These specifications apply to 1 75V processors i e those with a VID 00100 Tolerance 1 75V Processors Table 25 Asynchronous GTL and TAP Signal Groups Overshoot Undershoot Absolute Absolute E Un a Duration ns Duration ns Duration ns Notes 123 V V 2 30 0 585 0 72 7 20 60 0 2 25 0 535 1 32 13 2 60 0 2 20 0 485 2 64 26 4 60 0 2 15 0 435 4 92 49 2 60 0 2
103. s processor retention mechanisms to secure the processor in the baseboard socket The boxed processor will not ship with retention mechanisms or cooling solution retention clips Platforms designed for use by system integrators should include retention mechanisms and clips that support the boxed Pentium 4 processor System board documentation should include appropriate retention mechanism installation instructions 83 Intel Pentium 4 Processor in the 423 pin Package In 8 3 8 3 1 Boxed Processor Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the system board The power cable connector and pinout are shown in Figure 31 Platforms must provide a matched power header to support the boxed processor Table 37 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of two pulses per fan revolution A system board pull up resistor provides VOH to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identific
104. s the flatness and tilt specifications for the IHS Tilt is measured with the reference datum set to the bottom of the processor interposer Figure 18 Processor Cross Section and Keep in IHS Interposer 0 050 528 Component Keepin Socket must allow clearance for pin shoulders and mate flush with this surface 45 a Intel Pentium 4 Processor in the 423 pin Package intel amp 4 1 46 Figure 19 Figure 20 Processor Pin Detail 125 5 005 501g 0025 5 018 p gt SN Las 1 All dimensions in inches 2 8 microinches Au over 80 microinches Ni min 3 010 Diametric true position pin to pin IHS Flatness Specification 271004 IHS 008 Y 4 LTT META eil z J 4 A INTERPOSER J Package Load Specifications Table 27 provides dynamic and static load specifications for the Pentium 4 processor in the 423 pin package IHS These mechanical load limits should not be exceeded during heatsink assembly mechanical stress testing or standard drop and shipping conditions The heatsink attach solutions 4 2 4 3 4 4 Table 27 Note Table 28 Intel Pentium 4 Processor in the 423 pin Package must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heat sink to processor thermal interface It is no
105. scription PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Figure 10 illustrates the relationship of PWRGOOD to the RESET signal PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 13 and be followed by a 1 to 10 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REG 4 0 if Input Output REQ 4 0 Request Command must connect the appropriate pins of all processor system bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO Refer to the AP 1 0 signal description for a details on parity checking of these signals RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches wi
106. se specifications apply to the TAP signal group RON NOW AGTL System Bus Specifications Routing topology recommendations may be found in the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide Termination resistors are not required for most AGTL signals as these are integrated into the processor silicon Valid high and low levels are determined by the input buffers which compare a signal s voltage with a reference voltage called GTLREF known as Vngr in previous documentation Table 9 lists the GTLREF specifications The AGTL reference voltage GTLREF should be generated on the system board using high precision voltage divider circuits It is important that the system board impedance is held to the specified tolerance and that the intrinsic trace capacitance for the AGTL signal group traces is known and well controlled For more details on platform design see the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide AGTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF Bus Reference Voltage 2 2 3 Voc 2 V 2 3 6 Fr Termination Resistance 36 41 46 Q 4 COMP 1 0 COMP Resistance 42 77 43 2 45 45 O 5 7 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 21 a Intel Pentium 4 Processor in the 423 pin Package intel 2 12 22 Table 10 2
107. sign Guide for termination requirements and further details 5 The value of these pins during the active to inactive edge of RESET determine processor configuration options See Section 7 1 for details Asynchronous GTL Signals Pentium 4 processors do not utilize CMOS voltage levels on any signals that connect to the processor As a result legacy input signals such as A2ZOM IGNNE INIT LINTO INTR LINTI NMI PWRGOOD SMI SLP and STPCLK utilize GTL input buffers Legacy output FERR and other non AGTL signals THERMTRIP and PROCHOT utilize GTL output buffers All of these signals follow the same DC requirements as AGTL signals however the outputs are not actively driven high during a logical O to 1 transition by the processor the major difference between GTL and AGTL These signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the Asynchronous GTL signals are required to be asserted for at least two BCLKs in order for the processor to recognize them See Section 2 10 and Section 2 12 for the DC and AC specifications for the Asynchronous GTL signal groups See section Section 7 2 for additional timing requirements for entering and leaving the low power states Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the Pentium 4 processor be first in the TAP chain and followed by any othe
108. sserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor system bus agents DEFER Input DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of all processor system bus agents DP 3 0 Input Output DP 3 0 Data parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all Pentium 4 processor system bus agents 65 Intel Pentium 4 Processor in the 423 pin Package In Table 32 Signal Description Page 4 of 8 Name Type Description DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor system bus agents DSTBN 3 0 Input Output Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 D 63
109. t D19 AW37 Source Synch Input Output D58 AW13 Source Synch Input Output D20 AM38 Source Synch Input Output D59 AU13 Source Synch Input Output D21 AU39 Source Synch Input Output D60 AT12 Source Synch Input Output D22 AP36 Source Synch Input Output D61 AP14 Source Synch Input Output D23 AN39 Source Synch Input Output D62 AW17 Source Synch Input Output D24 AK36 Source Synch Input Output D63 AP12 Source Synch Input Output D25 AR37 Source Synch Input Output DBIO AL39 Source Synch Input Output D26 AT38 Source Synch Input Output DBI1 AU37 Source Synch Input Output D27 AN35 Source Synch Input Output DBI2 AT22 Source Synch Input Output D28 AU35 Source Synch Input Output DBI3 AW15 Source Synch Input Output D29 AW39 Source Synch Input Output DBR AV2 Asynch GTL Output D30 AT34 Source Synch Input Output DBSY B34 Common Clock Input Output D31 AL37 Source Synch Input Output DEFER J35 Common Clock Input D32 AW31 Source Synch Input Output DPO AW33 Common Clock Input Output D33 AT32 Source Synch Input Output DP1 AW35 Common Clock Input Output D34 AU29 Source Synch Input Output DP2 AW27 Common Clock Input Output D35 AP26 Source Synch Input Output DP3 AT26 Common Clock Input Output D36 AU33 Source Synch Input Output DRDY G37 Common Clock Input Output 52 intel Intel Pentium 4 Processor in the 423 pin Package
110. t recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions Package Dynamic and Static Load Specifications Parameter Max Unit Notes Static 25 Ibf 1 2 3 Dynamic 100 Ibf 1 3 4 NOTES This specification applies to a uniform load 4 This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface 5 These parameters are based on design characterization and not tested 6 Dynamic load specifications are defined assuming a maximum duration of 11ms Processor Insertion Specifications The Pentium 4 processor in the 423 pin package can be inserted and removed 30 times from a 423 pin socket meeting the 423 Pin Socket Design Guidelines document Note that this specification is based on design characterization and is not tested Processor Mass Specifications Table 28 specifies the processor s mass This includes all components which make up the entire processor product Processor Mass Processor Mass grams Pentium 4 processor 31mm OLGA 23 Processor Materials The Pentium 4 processor is assembled from several components The basic material properties are described in Table 29 47 Intel Pentium 4 Processor in the 423 pin Package Table 29 Processor Material Properties 4 5 Component Material Notes Integrated Heat Spreader
111. the BINIT assertion has been observed the bus agents will re arbitrate for the system bus and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BPM 5 0 Input Output BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all Pentium 4 processor system bus agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor Please refer to the Inte Pentium 4 Processor and Intel 850 Chipset Platform Design Guide for more detailed information These signals do not have on die termination Refer to section 2 5 and the product TP700 Debug Port Design Guide for termination requirements
112. ther H2 VCC Power Other F4 VCC Power Other H4 VSS Power Other F6 VSS Power Other H6 VCC Power Other F8 BPMO Common Clock Input Output H8 VSS Power Other 58 In Intel Pentium 4 Processor in the 423 pin Package Table 31 Pin Listing by Pin Number Table 31 Pin Listing by Pin Number Tem Pin Name Y Direction RA Pin Name e Direction H36 LINTO Asynch GTL Input P36 TDO TAP Output H38 THERMDA Power Other P38 FERR Asynch GTL Output J1 VCC Power Other R1 VSS Power Other J3 VSS Power Other R3 VCC Power Other J5 VCC Power Other R5 VSS Power Other J7 VSS Power Other R7 VCC Power Other J35 DEFER Common Clock Input R35 TRST TAP Input J37 VCC Power Other R37 TCK TAP Input J39 TDI TAP Input R39 VSS_SENSE Power Other Output K2 VSS Power Other T2 VCC Power Other K4 VCC Power Other T4 VSS Power Other K6 VSS Power Other T6 VCC Power Other K8 VCC Power Other T8 VSS Power Other K36 HIT Common Clock Input Output T36 GTLREF Power Other Input K38 SMI Asynch GTL Input T38 A20M Asynch GTL Input L1 VSS Power Other U1 VCC Power Other L3 VCC Power Other U3 VSS Power Other L5 VSS Power Other U5 VCC Power Other L7 VCC Power Ot
113. thout writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all system bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 4 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor system bus agents RSP Input RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor system bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC Output SKTOCC Socket Occupied will be pulled to
114. to Table 34 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except during another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Pins Configuration Option Pin Output tristate SMI Execute BIST INIT In Order Queue pipelining set IOQ depth to 1 A7 Disable MCERR observation AQ Disable BINIT observation A10 APIC Cluster ID 0 3 A 12 11 4 Disable bus parking A154 Symmetric agent arbitration ID BRO NOTE 1 Asserting this signal during RESET will select the corresponding option Clock Control and Low Power States The use of AutoHALT Stop Grant Sleep and Deep Sleep states is allowed in Pentium 4 processor based systems to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 27 for a visual representation of the processor low power states Normal State State 1 This is the normal operating state for the processor AutoHALT Powerdown State State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediate
115. to be in specification Table 33 also lists the maximum and minimum processor temperature specifications for TcAsg A thermal solution should be designed to ensure the temperature of the processor never exceeds these specifications Table 33 Processor Thermal Design Power Processor and Core Frequency Thermal Design Me er spelet Notes GHz Power W C C 1 7V processors 1 30 GHz 48 9 5 69 1 3 1 40 GHz 51 8 5 70 1 3 1 50 GHz 54 7 5 72 1 3 1 75V processors 1 30 GHz 51 6 5 70 1 4 1 40 GHz 54 7 5 72 1 4 1 50 GHz 57 8 5 73 1 4 1 60 GHz 61 0 5 75 1 4 1 70 GHz 64 0 5 76 1 4 1 80 GHz 66 7 5 78 1 4 1 90 GHz 69 2 5 73 1 4 2 GHz 71 8 5 74 1 4 NOTES 1 These values are specified at Voc mo for the processor Systems must be designed to ensure that the processor not be subjected to any static Voc and lc combination wherein Vcc exceeds Voc mip 0 055 1 loc lee max V 2 The numbers in this column reflect Intel s recommended design point and are not indicative of the maximum power the processor can dissipate under worst case conditions For more details refer to the Inte Pentium 4 Processor Thermal Design Guidelines 3 These specifications apply to 1 7V processors i e those with a VID 00110 4 These specifications apply to 1 75V processors i e those with a VID 00100 72 6 2 6 2 1 6 2 1 1 Intel Pentium 4 Processor in the 423 pin Package Thermal Ana
116. to power or ground a resistor will also allow for system testability For unused AGTL input or I O signals use pull up resistors of the same value for the on die termination resistors Rrr See Table 9 15 a Intel Pentium 4 Processor in the 423 pin Package intel amp 2 6 16 Table 3 TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and used outputs must be terminated on the system board Unused outputs may be terminated on the system board or left unconnected Note that leaving unused output not terminated may interfere with some TAP functions complicate debug probing and prevent boudary scan testing Signal termination for these signal types is discussed in the Intel Pentium 4 Processor and Intel 850 Chipset Platform Design Guide and ITP700 Debug Port Design Guide The TESTHI 10 0 pins must be connected to Vcc via a pull up resistor TESTHI 10 0 may be connected individually to Vcc via pull up resistors between I kQ and 10 KQ value Alternately TESTHI 1 0 may be tied together and pulled up to Vcc with a single 1 KQ 4 7 KQ resistor TESTHI 7 2 may be tied together and pulled up to Vcc with a single 1 KQ 4 7 KQ resistor and TESTHI 10 8 may be tied together and pulled up to Vcc with a single I KQ 4 7 KQ resistor However tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing System Bus Signal Groups In order to s
117. to the processor The advanced transfer cache is a 256kB on die level 2 cache with increased bandwidth over previous micro architectures The floating point and multi media units have been improved by making the registers 128 bits wide and adding a separate register for data movement Finally SSE2 adds 144 new instructions for double precision floating point SIMD integer and memory management The Streaming SIMD Extensions 2 enable break through levels of performance in multimedia applications including 3 D graphics video decoding encoding and speech recognition The new packed double precision floating point instructions enhance performance for applications that require greater range and precision including scientific and engineering applications and advanced 3 D geometry techniques such as ray tracing The Pentium 4 processor supports uni processor configurations only As a result of this integration the return to Pin Grid Array PGA style processor packaging is possible The same manageability features which are included in Intel Pentium III processors are included on Pentium 4 processors with the addition of Thermal Monitor The Thermal Monitor allows systems to be designed for anticipated processor thermals as opposed to worst case with no performance degradation expected Power management capabilities such as AutoHALT Stop Grant Sleep and Deep Sleep have also been retained for power management capabilities New heat sinks heat s
118. uned precision on die thermal sensor and a fast acting thermal control circuit TCC the processor without the aid of any additional software or hardware can keep the processors die temperature within factory specifications under typical real world operating conditions Thermal Monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications instead of being designed to the much higher maximum theoretical processor power envelopes Thermal Monitor controls the processor temperature by modulating the internal processor core clocks The processor clocks are modulated when the TCC is activated Thermal Monitor uses two modes to activate the TCC Automatic mode and On Demand mode Automatic mode is required for the processor to operate within specifications and must first be enabled via BIOS Once automatic mode is enabled the TCC will activate only when the internal die temperature is very near the temperature limits of the processor When TCC is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a a 50 duty cycle Clocks will not be off more than 3 us when TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor
119. up of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups Input DSTBN D 63 0 amp Output Data Group DSTBP DBl D 15 0 0 D 31 16 1 D 47 32 2 D 63 48 3 Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 Input Output DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DBI 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DBI3 D 63 48 DBI2 D 47 32 DBIt D 31 16 f DBIO D 15 0 DBR Output DBRi is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is a
120. y factor for common clock AGTL signals is referenced to BCLK 1 0 frequency Note 2 Activity factor for source synchronous 2x signals is referenced to ADSTB 1 0 Note 3 Activity factor for source synchronous 4x signals is referenced to DSTBP 3 0 and DSTBN 3 0 Reading Overshoot Undershoot Specification Tables The overshoot undershoot specification for the Pentium 4 processor is not a simple single value Instead many factors are needed to determine the over undershoot specification In addition to the magnitude of the overshoot the following parameters must also be known the width of the overshoot and the activity factor AF To determine the allowed overshoot for a particular overshoot event the following must be done 1 Determine the signal group that the particular signal falls into For AGTL signals operating in the 4x source synchronous domain use Table 18 For AGTL signals operating in the 2x source synchronous domain use Table 19 If the signal is an AGTL signal operating in the common clock domain use Table 20 Finally all other signals reside in the 33MHz domain asynchronous GTL TAP etc and are referenced in Table 21 2 Determine the magnitude of the overshoot or the undershoot relative to Vss 3 Determine the activity factor how often does this overshoot occur 4 Next from the appropriate specification table determine the maximum pulse duration in nanoseconds allowed 5 Compare the specifi

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