Home

Intel S5500HCV

1. 10H 6 5 volt Standy by LED rms HIR H JOJ jelle felle LID sls aj E HIE a e s e 8 s o Figure 48 5 volt Stand by Status LED Location Revision 1 2 121 Intel order number E39529 009 Intel Light Guided Diagnostics Intel Server Board S5520HC S5500HCV TPS 8 2 Fan Fault LED s Fan fault LEDs are present for the two CPU fans and the one rear system fan The fan fault LEDs illuminate when the corresponding fan has fault System Fan 5 Fault LED CPU 1 Fan Fault LED CPU 1 Socket E UO seem J CPU 2 Socket ULV Meo sos CPU 2 Fan Fault LED
2. Callou Description Callout Description t A System Status LED E Video NIC Port 1 1 Gb Default Management B ID LED F Port USB Port 2 top 3 bottom NIC Port 2 1 Gb USB Port 0 top 1 bottom C Diagnostics LED s G D Serial Port A Figure 12 Rear UO Layout 16 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture 3 Functional Architecture The architecture and design of the Intel Server Boards S5520HC and S5500HCV is based on the Intel 5520 5500 and ICH10R chipset The chipset is designed for systems based on the Intel Xeon Processor 5500 Series in an FC LGA 1366 Socket B package with Intel QuickPath Interconnect Intel QPI speed at 6 40 GT s 5 86 GT s and 4 80 GT s The chipset contains two main components Intel 5520 I O Hub or 5500 UO Hub which provides a connection point between various I O components and the Intel QuickPath Interconnect Intel QPI based processors Intel ICH10 RAID ICH10R I O controller hub for the I O subsystem This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards Revision 1 2 17 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS DDR3 mam intel
3. Server Board CPU Socket DIMM Identifier Channel Slot A1 Blue Channel A Slot 0 A2 Black Channel A Slot 1 CPU 4 B1 Blue Channel B Slot 0 B2 Black Channel B Slot 1 C1 Blue Channel C Slot 0 Intel amp Server Board C2 Black Channel C Slot 1 5520HC D1 Blue Channel D Slot 0 D2 Black Channel D Slot 1 E1 Blue Channel E Slot 0 SES E2 Black Channel E Slot 1 F1 Blue Channel F Slot 0 F2 Black Channel F Slot 1 Figure 16 Intel Server Board S5520HC DIMM Slots Arrangement Revision 1 2 Intel order number E39529 009 27 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS o g P i IIl D Ojo CPU 1 Soch DIMM A2 A1 B2 B1C2 C1 DIMM Fi E1 Server Board CPU Socket DIMM Identifier Channel Slot A1 Blue Channel A Slot 0 A2 Black Channel A Slot 1 CPU 1 B1 Blue Channel B Slot 0 Intel S Board B2 Black Channel B Slot 1 ee SES oar C1 Blue Channel C Slot 0 C2 Black Channel C Slot 1 D1 Blue Channel D Slot 0 CPU 2 E1 Blue Channel E Slot 0 F1 Blue Channel F Slot 0 Figure 17 Intel Server Board S5500HCV DIMM Slots Arrangement 3 3 2 Supported Memory 28 Both Intel Server Board S5520HC and Intel Server Board S5500HCV support 1 5 V DDR3 DIMMs Intel Server Board S552
4. DIMM Fault LEDs D2 E2 and F2 DIMM slot and Fault LED s are empty in Intel Server Board S5500HCV Figure 51 DIMM Fault LED s Location Revision 1 2 125 Intel order number E39529 009 Intel amp Light Guided Diagnostics Intel Server Board S5520HC S5500HCV TPS 8 5 Post Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server boards in the rear I O area of the server boards by the serial A connector During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the given POST code to the POST code diagnostic LED s on the back edge of the server boards To assist in troubleshooting a system hang during the POST process you can use the diagnostic LEDs to identify the last POST process executed See Appendix E for a complete description of how these LEDs are read and a list of all supported POST codes 6660 A Diagnostic LED 7 MSB LED E Diagnostic LED 3 B Diagnostic LED 6 F Diagnostic LED 2 C Diagnostic LED 5 G Diagnostic LED 1 D Diagnostic LED 4 0 H Diagnostic LED 0 LSB LED Figure 52 POST Code Diagnostic LED Locations 126 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Design and Environme
5. OxE8 No Usable Memory Error No memory in the system or SPD bad so no memory could be detected or all memory failed Hardware BIST System is halted OxEB Memory Test Error One or memory DIMMs Channels failed Hardware BIST but usable memory remains System continues POST OxED Population Error RDIMMs and UDIMMs cannot be mixed in the system OxEE Mismatch Error more than 2 Quad Ranked DIMMS in a channel Host Processor 0x04 Early processor initialization where system BSP is selected 0x10 Power on initialization of the host processor Boot Strap Processor 0x11 Host processor cache initialization including AP 0x12 Starting application processor initialization 0x13 SMM initialization Chipset 0x21 Initializing a chipset component Memory 0x22 Reading configuration data from memory SPD on DIMM 0x23 Detecting presence of memory 0x24 Programming timing parameters in the memory controller 0x25 Configuring memory parameters in the memory controller 0x26 Optimizing memory controller settings 0x27 Initializing memory such as ECC init 0x28 Testing memory PCI Bus 0x50 Enumerating PCI buses 0x51 Allocating resources to PCI buses 0x52 Hot plug PCI controller initialization 0x53 0x57 Reserved for PCI Bus 164 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Appendix E POST Code Diagno
6. Chassis Intrusion Header AN Update D BMC Force Disable Enable d 1 Figure 47 Jumper Blocks J1E2 J1E4 J1E5 J1E6 J1H1 Table 68 Server Board Jumpers J1E6 J1E2 J1E4 J1E5 J1H1 Jumper Name Pins 1 2 J1E6 CMOS Clear System Results These pins should have a jumper in place for normal system operation Default 2 3 If pins 2 3 are connected when AC power unplugged the CMOS settings clear in 5 seconds Pins 2 3 should not be connected for normal system operation J1E2 ME Force 1 2 ME Firmware Force Update Mode Disabled Default Update 2 3 ME Firmware Force Update Mode Enabled 1 2 These pins should have a jumper in place for normal system operation Default J1E4 Password Clear To clear administrator and user passwords power on the system with pins 2 3 2 3 connected The administrator and user passwords clear in 5 10 seconds after power on Pins 2 3 should not be connected for normal system operation 1 2 Pins 1 2 should be connected for normal system operation Default J1ES BIOS Recovery 2 3 The main system BIOS does not boot with pins 2 3 connected The system only boots from EF I bootable recovery media with a recovery BIOS image present Revision 1 2 117 Intel order number E39529 009 Jumper Blocks Intel Server Board S5520HC S5500HCV TPS Jumper Name Pins System Results J1H1 Force
7. The BSMI Certification Marking and EMC warning is located on the outside rear area of the product TERAK IER RURIDEEUER gt CECT BJBE SHE HATZ isin ERES RIF is EE BUR TRE Revision 1 2 141 Intel order number E39529 009 Regulatory and Certification Information Intel Server Board S5520HC S5500HCV TPS RRL KCC Korea CNCA CCC China This CCC Certification Marking and EMC warning is located on the outside rear area of the product AH WAAR ih Zen Brine MCR ERP AAE m H MFR ITRE 10 4 Product Ecology Change EU RoHS Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002 95 EC Compliance is based on declaration that materials banned in the RoHS Directive are either 1 below all applicable threshold limits or 2 an approved pending RoHS exemption applies RoHS implementation details are not fully defined and may change Threshold limits and banned substances are noted below e Quantity limit of 0 1 by mass 1000PPM for Lead Mercury Hexavalent Chromium Polybrominated Biphenyls Diphenyl Ethers PBDE e Quantity limit of 0 01 by mass 100 PPM for Cadmium 10 5 Product Ecology Change CRoHS CRoHS China RoHS or Ministry of Information Industry Order 39 Management Methods for Controlling Pollution by Electronic Information Products e China bans the same substances and limits as noted for EU RoHS however require
8. 3 Sun Solaris 10 U5 05 08 may fail to boot into graphics display Description Sun Solaris 10 U5 may fail to boot into graphics display with Intel Server Board S5520HC or Intel Server Board S5500HCV onboard video controller Guideline Edit the script usr bin X11 Xserver and modify arguments as following in order to accomplish graphics display SERVERARGS depth 16 fbbpp 16 4 System may experience high power consumption under Microsoft Windows Server 2003 when the processor is idle Description Intel Server Board S5520HC or Intel Server Board S5500HCV based system may experience high power consumption under Microsoft Windows Server 2003 when the processor is idle and there is a discontinuity in the C states Guideline Follow the instructions listed at the following website to apply the hot fix only to systems that are experiencing this problem http support microsoft com kb 94 1838 5 When EFI Shell is selected as the first device on the BIOS boot option list some RAID adapters may not enter their configuration screen before the server board boots into EFI Shell 172 Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Appendix G Installation Guidelines Description In an Intel Server Board S5520HC or S5500HCV based system with EFI shell as first boot device after users press hot keys to enter RAID adapter configuration screen that hooks option ROM on INT 19h the system
9. Base Server Profile Fan Profile Physical Asset Profile Power State Management Profile Profile Registration Profile Record Log Profile Sensor Profile Revision 1 2 59 Intel order number E39529 009 Platform Management Intel Server Boards S5520HC and S5500HCV TPS Software Inventory Profile FW Version Note WS MAN features will be made available after production launch 4 2 5 Embedded Web server The BMC provides an embedded web server for out of band management User authentication is handled by IPMI user names and passwords Base functionality for the embedded web server includes Power Control Sensor Reading SEL Reading KVM Media Redirection Only available when the Intel RMM3 is present IPMI User Management The web server is available on all enabled LAN channels If a LAN channel is enabled properly configured and accessible the web server is available The web server may be contacted via HTTP or HTTPS A user can modify the SSL certificates using the web server You cannot change the web server s port 80 81 For security reasons you cannot use the null user user 1 to access the web server The session inactivity timeout for the embedded web server is 30 minutes This is not user configurable 4 2 6 Local Directory Authentication Protocol LDAP The BMC firmware supports the Linux Local Directory Authentication Protocol LDAP protocol for user authentication IPMI use
10. Main Screen Display 71 Figure 23 Setup Utility Advanced Screen Display 73 Figure 24 Setup Utility Processor Configuration Screen Display ssessssssss 74 Figure 25 Setup Utility Memory Configuration Screen Display 77 Figure 26 Setup Utility Configure RAS and Performance Screen Display 79 Figure 27 Setup Utility Mass Storage Controller Configuration Screen Display 80 Figure 28 Setup Utility Serial Port Configuration Screen Display 82 Figure 29 Setup Utility USB Controller Configuration Screen Display ss 83 Figure 30 Setup Utility PCI Configuration Screen Display sseesee 85 Figure 31 Setup Utility System Acoustic and Performance Configuration Screen Display 86 Revision 1 2 ix Intel order number E39529 009 List of Figures Intel Server Boards S5520HC and S5500HCV TPS Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Setup Utility Security Configuration Screen Display 87 Setup Utility Server Management Configuration Screen Display 89 Setup Utility Console Redirection S
11. rver Boards S5520HC and S5500HCV TPS List of Tables List of Tables Table 1 IOH High Level Summary ssssssssssssssssseeeeeeneeneneenn enne enne enne nnne ener nnns 20 Table 2 Mixed Processor Configurations sssssssssesesseeee ener 23 Table 3 Memory Running Frequency vs Processor SKU cccccccccececeeaeeeseeseseeeeseeeeeeeeeeenes 30 Table 4 Memory Running Frequency vs Memory Population ssssesenneneneneerereereseeeerererereree 30 Table 5 Supported DIMM Population under the Dual Processors Configuration 37 Table 6 Supported DIMM Population under the Single Processor Configuration 37 Table 7 Onboard SATA Storage Mode Mat 40 Table 8 Intel Server Board S5520HC PCI Bus Segment Characteristics s 43 Table 9 Intel Server Board S5500HCV PCI Bus Segment Characteristics 44 Table 10 Intel Server Board S5520HC PCI Riser Slot Slot Ei 44 Table 11 PCI Riser SUpport nriran aaea aa A Eiana aaant abracar int 45 Table 12 Intel SAS Entry RAID Module AXX4SASMOD Storage Mode eee 48 Table 13 Serial B Header Pin out sssssssssssssseseseseeeene enne enne enne nennen entra 51 Table 14 Video ele EE 52 Table 15 Onboard NIC Status LED 53 Table 16 Basic and Advanced Management Features sneneeeeeeeeerenirrtrrrrrrnrnenerereerererrrrrnt 57 Table 17 S5520HC and SS500HCV
12. The Intel 5520 IOH is capable of interfacing with up to 36 PCI Express Gen2 lanes which support devices with the following link width x16 x8 x4 x2 and x1 The Intel 5500 IOH is capable of interfacing with up to 24 PCI Express Gen2 lanes which support devices with the following link width x16 x8 x4 x2 and x1 All ports support PCI Express Gen1 and Gen2 transfer rates 20 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture For a detailed PCI Express Slots definition in the Intel Server Boards S5520HC and S5500HCV see 3 5 PCI Subsystem 3 1 3 Enterprise South Bridge Interface ESI One x4 ESI link interface supporting PCI Express Gen1 2 5 Gbps transfer rate for connecting Intel ICH10R in the Intel Server Boards S5520HC and S5500HCV 3 1 4 Manageability Engine ME An embedded ARC controller is within the IOH providing the Intel Server Platform Services SPS The controller is also commonly referred to as the Manageability Engine ME 3 1 5 Controller Link CL The Controller Link is a private low pin count LPC low power communication interface between the IOH and the ICH10 portions of the Manageability Engine subsystem Revision 1 2 21 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 2 Processor Support The Intel Server Boards S5520HC and S5500HCV support one or two
13. opgoen Figure 49 Fan Fault LED s Location 122 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Intel amp Light Guided Diagnostics 8 3 System ID LED and System Status LED The server boards provide LEDs for both system ID and system status These LEDs are located in the rear I O area of the server board as shown in the following figure l Q DEB SSES il lojo CPUT Socket H o ole at ou ese e BH L A b o Bd ir CPU2Sockt H olll S S ystem ID LED Figure 50 System Status LED Location al alj aii zu KH LUC I O CL ystem Status LED You can illuminate the blue System ID LED using either of the following two mechanisms By pressing the System ID Button on the system front control panel the ID LED displays a solid blue color until the button is pressed again Revision 1 2 123 Intel order number E39529 009 Intel Light Guided Diagnostics Intel Server Board S5520HC
14. 1 Operating system has requested the system to reset ResetSystem has been called Pre EFI Initializatio n Module PEIM Recovery 0x30 Crisis recovery has been initiated because of a user request 0x31 Crisis recovery has been initiated by software corrupt flash 0x34 Loading crisis recovery capsule 0x35 Handing off control to the crisis recovery capsule Ox3F Unable to complete crisis recovery 166 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Appendix F POST Error Messages and Handling Appendix F POST Error Messages and Handling Whenever possible the BIOS outputs the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information The class and subclass fields point to the type of hardware being initialized The operation field represents the specific initialization activity Based on the data bit availability to display progress codes you can customize a progress code to fit the data width The higher the data bit the higher the granularity of information that can be sent on the progress port The system BIOS or option ROMs may report progress codes The Response section in the following table is divided into three types e No Pause The message is displayed on the screen or on the Error Manager screen The system continues boot
15. Table 6 Supported DIMM Population under the Single Processor Configuration CPU1 Socket Populated CPU2 Socket Empty A2 B1 B2 C1 D1 D2 E1 E2 n CH N T EN F2 M gt lt x lt 4 gt lt x lt Ee 234 2 3 X lt Ee Oo cm MESE SS 2 2 x Xx x Xx Ee x lt Pd Z Note The generic principles and guidelines described in the above sections also apply to the above two tables Revision 1 2 37 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 3 11 Memory Error Handling The BIOS classifies memory errors into the following categories Correctable ECC errors This correction could be the result of an ECC correction a successfully retried memory cycle or both Unrecoverable Fatal ECC Errors The ECC engine detects these errors but cannot correct them Address Parity Errors An Address Parity Error is logged as such in the SEL but in all other ways is treated the same as an Uncorrectable ECC Error 38 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture 3 4 ICH10R The ICH10R provides extensive I O support Functions and capabilities include PCI Express Base Specification Revision 1 1 support PCI Local Bus Specification Revision 2 3 support for 33 MHz PCI operations supports up to four RE
16. The plus key on the keypad is used to change the value of the current menu item to the next value This key scrolls through the values in the associated pick list without displaying the full list On 106 key Japanese keyboards the plus key has a different scan code than the plus key on the other keyboards but will have the same effect F9 Setup Defaults Revision 1 2 Pressing F9 causes the following to display Load Optimized Defaults Yes No If Yes is highlighted and Enter is pressed all Setup fields are set to their default values If No is highlighted and Enter is pressed or if the lt Esc gt key is pressed the user is returned to where they were before F9 was pressed without affecting any existing field values 69 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS Key Option lt F10 gt Save and Exit Pressing lt F10 gt causes the following message to display Save configuration and reset Yes No If Yes is highlighted and Enter is pressed all changes are saved and the Setup is exited If No is highlighted and lt Enter gt is pressed or the lt Esc gt key is pressed the user is returned to where they were before lt F10 gt was pressed without affecting any existing values 5 3 1 4 Menu Selection Bar The Menu Selection Bar is located at the top of the BIOS Setup Utility screen
17. The role of the BIOS is limited to describing the wake up sources to the operating system The S5 state is equivalent to the operating system shutdown No system context is saved when going into S5 3 14 Intel Virtualization Technology Intel Virtualization Technology is designed to support multiple software environments sharing the same hardware resources Each software environment may consist of an operating system and applications You can enable or disable the Intel Virtualization Technology in the BIOS Setup The default behavior is disabled Note After changing the Intel Virtualization Technology option disable or enable in the BIOS setup users must perform an AC power cycle before the change takes effect 3 14 1 Intel Virtualization Technology for Directed IO VT d The Intel Server Boards S5520HC and S5500HCV support DMA remapping from inbound PCI Express memory Guest Physical Address GPA to Host Physical Address HPA PCI devices are directly assigned to a virtual machine leading to a robust and efficient virtualization You can enable or disable the Intel Virtualization Technology for Directed I O in the BIOS Setup The default behavior is disabled Note After changing the Intel Virtualization Technology for Directed UO options disable or enable in the BIOS setup users must perform an AC power cycle before the changes can take effect 3 15 Intel UO Acceleration Technology The Intel Server Boards S5520H
18. There are no gear ratio requirements for the Intel Xeon Processor 5500 Series Intel 5500 5520 IOH supports 4 8 GT s 5 86 GT s and 6 4 GT s frequencies for the QPI links During QPI initialization the BIOS configures both endpoints of each QPI link to the same supportable speeds for the correct operation During memory discovery the BIOS arrives at a fastest common frequency that matches the requirements of all components of the memory system and then configures the DDR3 DIMMs for the fastest common frequency In addition rules on the following tables Tables 3 and 4 also decide the global common memory system frequency Revision 1 2 29 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS Table 3 Memory Running Frequency vs Processor SKU DIMM Type DDR3 800 DDR3 1066 DDR3 1333 800 800 800 800 Processor Integrated Memory Memory Running Frequency Hz Controller IMC 1066 800 1066 1066 Fastest Common Frequency of Processor IMC and Max Frequency Memory Hz 1333 800 1066 Table 4 Memory Running Frequency vs Memory Population Memory Running Frequency Ranks Per DIMM DIMM YIN Command SR Single Rank SE ZE l 800MH 1066MH 1333MH ROT ea Har pank ic NE S S QR Quad Rank All RDIMMs run at the fastest common RDIMM 1 Y Y Y 1N SR or DR frequency of processor IMCs and installed memory 800MHz 1066MHz or 133MHz
19. erdt thee een Mi mers rete eee 113 6 6 le le EE 115 ONE Tel ERR 117 7 1 CMOS Clear and Password Reset Usage Procedure ssesiseesereseererererererrenne 118 vi Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Table of Contents 7 1 1 Clearing the CMOS iiss ipee e eC e ee Pen ME RE M nace RR un dna 118 7 1 2 Clearing the Password 118 7 2 Force BMC Update Procedure ssssssssssssssseee eene eene 119 7 3 BIOS Recovery Jumper 119 8 Intel Light Guided Diagnostics ssssssssssssescsssssssesssssssseacacacsescsessssesssacacacseeteessess 121 8 1 b volt Stand by EED diet o era ee ee pa te Oe e eed 121 8 2 F n Fault BR a a Aaien aaa aeee 122 8 3 System ID LED and System Status LED 123 8 4 DIMM ru RE 125 8 5 Post Code Diagn stie LEDS arsimi paini ieten ea EAEE NER EAE E EEA E Eaa EEA KERKEE 126 9 Design and Environmental Specifications eese 127 9 1 Intel Server Boards S5520HC and S5500HCV Design Specifications 127 9 2 MTBI EE 127 9 3 Server Board Power Requirements seeseseeeeeseeeeretrerrrrrrrrrnrnrrereresrerererrte rnnt 129 9 3 1 Processor Power Support yate aeaiaioe naen aa aaaea aA Aae A DAE Aa ARAE 130 9 4 Power Supply Output Reouirements 130 9 4 1 CSFOUMGING RP 131 9 4 2 otand by Oulpults ec ode ete et en ede eA a a REED Ee Rete 131 9 4 3 Remote Sense iae tero epuateee tet perte test
20. 009 BIOS Setup Utility Intel amp Server Board S5520HC S5500HCV TPS Setup Item Options Help Text Comments Memory Size Information only Displays the total physical memory installed in the system in MB or GB The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs Quiet Boot Enabled Enabled Display the logo screen Disabled during POST Disabled Display the diagnostic screen during POST POST Error Pause Enabled Enabled Go to the Error If enabled the POST Error Pause Disabled Manager for critical POST errors option takes the system to the Disabled Attempt to boot and do error manager to review the errors not go to the Error Manager for when major errors occur Minor and critical POST errors fatal error displays are not affected by this setting System Date Day of week System Date has configurable MM DD YYYY fields for Month Day and Year Use Enter or Tab key to select the next field Use or key to modify the selected field System Time HH MM SS System Time has configurable 72 fields for Hours Minutes and Seconds Hours are in 24 hour format Use Enter or Tab key to select the next field Use or key to modify the selected field Intel order number E39529 009 Revision 1 2 Intel Server Boards S5520HC and S5500HCV TPS 5 3 2 2 Advanced Screen BIOS Setup Utility The Advanced screen provid
21. 2 1 Intel amp Server Board S5520HC S5500HCV TPS Processor Configuration Screen The Processor screen allows the user to view the processor core frequency system bus frequency and to enable or disable several processor options This screen also allows the user to view information about a specific processor To access this screen from the Main screen select Advanced Processor 74 Advanced Processor Configuration Processor Socket Processor ID Processor Frequency Microcode Revision L1 Cache RAM L2 Cache RAM L3 Cache RAM Processor 1 Version Processor 2 Version Current Intel QPI Link Speed Intel QPI Link Frequency Intel Turbo Boost Technology Enhanced Intel SpeedStep Tech Intel Hyper Threading Tech Core Multi Processing Execute Disable Bit Intel Virtualization Technology Intel VT for Directed UO Interrupt Remapping Coherency Support ATS Support Pass through DMA Support Hardware Prefetcher Adjacent Cache Line Prefetch Direct Cache Access DCA Enabled Disabled Enabled Disabled Enabled Disabled All 1 2 Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Figure 24 Setup Utility Processor Configuration Screen Display Intel order number E39529 009 Revision 1 2 Intel Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Tab
22. 3 Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel Server Boards S5520HC and S5500HCV including voltage and current specifications and power supply on off sequencing characteristics The following diagram shows the power distribution implemented on these server boards Cem Ga f es f Ee NES a gt d CET EE Lm Figure 53 Power Distribution Block Diagram Revision 1 2 129 Intel order number E39529 009 Design and Environmental Specifications Intel Server Board S5520HC S5500HCV TPS 9 3 1 Processor Power Support The server boards support the Thermal Design Power TDP guideline for Intel Xeon processors The Flexible Motherboard Guidelines FMB were also followed to determine the suggested thermal and current design values for anticipating future processor needs The following table provides maximum values for lcc TDP power and Tease for the compatible Intel Xeon Processor 5500 series Table 72 Intel Xeon Processor Dual Processor TDP Guidelines Max Tcase TDP Power Icc Max Thermal Profile A Thermal Profile B 95 W 75 C 81 C 120A 9 4 Power Supply Output Requirements This section is for reference purposes only The intent is to provide guidance to system designers to determine a power supply to use with these server boards This section specifies the power supply requirements Intel used to d
23. 4 3 Platform ge Tu EE 61 4 3 1 Memory Open and Closed Loop Thermal Throttlmg 62 4 3 2 Fan Speed Control rero eo e ER EE C haw Eegen 62 4 4 Intel Intelligent Power Node Manager 65 4 4 1 Manageability Engine ME 65 GEN S RII DEUM 67 5 1 Logo Diagnostic Gcreen EEN 67 5 2 BIOS Boot Popup Menu ner ter eget dn te vete Rede ks 67 5 3 BIOS Setup Utility Ice Meet ihe dete ed eR a dre epit pee pneu 67 5 3 1 Ree ue ec CREE 68 5 3 2 Server Platform Setup Utility Screens seseeeeeeeeeeeeeesrrrrrrrrnrrrrenesesterererererrrrenen 70 6 Connector Header Locations and Pin outs eere 105 6 1 Board Connector Information 105 6 2 Power Connectors esr ee este pl Are uei ee exe creer vedas 106 6 3 System Management Headers sssssssssssssseeeeeeen 108 6 3 1 Intel Remote Management Module 3 Connector ssssee 108 6 3 2 EGP IPNB EHeader une need 108 0 3 3 SBSBEIHe ader e see TRA i oe tts ct 109 06 3 4 SGPIO Header ii Irene e P WERE ITA DRE RENE 109 6 4 Front Panel Connector aue reise t eee rhe e ee ver eee dee beets 109 6 5 VO CONN EClOFS ore DTI 110 6 5 1 VGA elle 110 6 5 2 NIC CONNECTIONS Em 110 6 5 3 SATA Connectors eR Heu rre rar P ERE eSI DER EERSU E PR dent REPRE E or AS 112 65 4 SAS Module SlOL o e oer eee ee geo dE Sa oe EE 112 6 5 5 Serial Port Connectors er pct te a e ein M REIR EREMO ER eee 113 6 5 6 USB GConrnectoL 5
24. All RDIMMs run at 800MHz or 1066MHz RDIMM 1 Y Y N 1N QR only when Quad Rank RDIMM is installed in any channel SR DR or mixin All RDIMMs run at 800MHz or 1066MHz RDIMM 2 Y Y N 1N eI 9 when two RDIMMs Single Rank or Dual of SR and DR Rank are installed in the same channel QR only or mixing All RDIMMs run at 800MHz when two of SR and QR or RDIMMs either or both are Quad Rank RDIMM 2 i M IN mixing of DR and RDIMMs are installed in the same QR channel UDIMM 1 y Y Y AN SR or DR 5 SE at the c common wl or w o requency of processor IMCs and installed 30 Intel order number E39529 009 Revision 1 2 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture Memory Running Frequency YIN Ranks Per DIMM DIMM Command SR Single Rank EN DIMM Type Populated Address Rate DR Dual Rank Description Per Channel 800MHz 1066MHz 1333MHz QR Quad Rank ECC memory 800MHz 1066MHz or 1333MHz UDIMM T All UDIMMs run at 800MHz or 1066MHz 2 Y Y N 2N SR DR or mixing When two UDIMMs Single or Dual Rank w or w o of SR and DR 9 ECC are installed in the same channel 1N One clock cycle for the DRAM commands arrive at the DIMMs to execute 2N Two clock cycles for the DRAM commands arrive at the DIMMs to execute Revision 1 2 Intel order number E39529 009 31 Functional Architecture Intel Server Boards S
25. Board Connector Information The following section provides detailed information regarding all connectors headers and jumpers on the server boards The following table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen Table 45 Board Connector Matrix Connector Quantity Reference Designators Connector Type Pin Count Main power 24 CPU 1 power 8 CPU 2 Power 8 P S aux IPMB 5 CPU 2 U7J1 U7C1 CPU sockets 1366 J4F1 J5F1 J5F2 J5F3 J6F1 J6F2 J8F1 J8F2 J8F3 J9F1 J9F2 DIMM sockets 240 J9F3 J2B1 J2B2 J3B1 J4B1 Card edge J4B2 Card edge Power supply N Main memory PCI Express x8 PCI Express x16 32 bit PCI J1B2 Card SN SAS Module Slot SATA Software RAID J1F2 Key holder 3 5 Key System fans J1K1 J1K2 J1K4 J1K5 Header 6 Video J7A1 External DSub 15 USB Solid State Drive 1 J2D2 Low profile header 10 Chassis Intrusion Revision 1 2 105 Intel order number E39529 009 Connector Header Locations and Pin outs Intel Server Board S5520HC S5500HCV TPS Connector Quantity Reference Designators Connector Type Pin Count Update J1E4 Password Clear J1E5 jumper 3 BIOS Recovery J1H1 BMC Force P Update Empty on Intel Server Board S5500HCV Configuration jumpers gr m J1E6 CMOS Clear J1E2 ME Force 4 6 2 Power Connectors The main power supply connection uses an SSI c
26. Current Configuration Current Memory Speed Memory RAS and Performance Configuration DIMM Information DIMM A1 DIMM A2 DIMM B1 DIMM B2 DIMM C1 DIMM C2 DIMM D1 DIMM D2 DIMM E1 DIMM E2 DIMM F1 DIMM F2 Figure 25 Setup Utility Memory Configuration Screen Display Revision 1 2 77 Intel order number E39529 009 BIOS Setup Utility Setup Item Total Memory Intel amp Server Board S5520HC S5500HCV TPS Table 23 Setup Utility Memory Configuration Screen Fields Help Text Comments Information only The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB Effective Memory Current Configuration Current Memory Speed Memory RAS and Performance Configuration DIMM XY 78 Configure memory RAS Reliability Availability and Serviceability and view current memory performance information and settings Information only The amount of memory available to the operating system in MB or GB The Effective Memory is the difference between Total Physical Memory and the sum of all memory reserved for internal usage RAS redundancy and SMRAM This difference includes the sum of all DDR3 DIMMs that failed Memory BIST during POST or were disabled by the BIOS during memory discovery phase in order to optimize memory configuration Information only Displays one of the following ndependent Mode System memory is configured for optim
27. Fan Domain Table nnseneseeneneeeeeeeeerrrnrrrrrrrnerennerererere 63 Table 18 BIOS Setup Page Layout 68 Table 19 BIOS Setup Keyboard Command Bar 69 Table 20 Setup Utility Main Screen Fields sssseseeeeeeennnnnnnnnnnn 71 Table 21 Setup Utility Advanced Screen Display Fields ssesssssseseseses 73 Table 22 Setup Utility Processor Configuration Screen Fields 75 Table 23 Setup Utility Memory Configuration Screen Fields 0nnnnnnsneeeesseeesneere rrr ereeeeeee 78 Table 24 Setup Utility Configure RAS and Performance Screen Fields 79 Table 25 Setup Utility Mass Storage Controller Configuration Screen Fields 81 Table 26 Setup Utility Serial Ports Configuration Screen Fields eseesesssssse 82 Table 27 Setup Utility USB Controller Configuration Screen Fields 84 Table 28 Setup Utility PCI Configuration Screen Fields 85 Table 29 Setup Utility System Acoustic and Performance Configuration Screen Fields 87 Table 30 Setup Utility Security Configuration Screen Eielde nssenanenenenne nee eeeeeeeeeresnnene rene 88 Table 31 Setup Utility Server Management Configuration Screen Fields 90 Table 32 Setup Utility Console Redirection Configuration Fields 92 Revision 1 2 xi Intel order number E39529 009 List
28. H Diagnostic LED 0 LSB LED Figure 57 Diagnostic LED Placement Diagram In the following example the BIOS sends a value of EDh to the diagnostic LED decoder The LED s are decoded as follows Table 83 POST Progress Code LED Example Upper Nibble LED s Lower Nibble LED s LED s LED LED LED LED LED LED LED LED 7 6 5 4 3 2 1 0 8h 4h 2h th 8h 4h 2h th Status ON ON ON ON ON ON OFF ON 1 1 1 0 1 1 0 1 Results Eh Dh Revision 1 2 163 Intel order number E39529 009 Appendix E POST Code Diagnostic LED Decoder Intel Server Board S5520HC S5500HCV TPS Upper nibble bits 1110b Eh Lower nibble bits 1101b Dh the two are concatenated as EDh Find the meaning of POST Code EDh in below table Memory Population Error RDIMMs and UDIMMs cannot be mixed in the system Table 84 POST Codes and Messages Progress Code Progress Code Definition Multi use Code This POST Code is used in different contexts OxF2 Seen at the start of Memory Reference Code MRC Start of the very early platform initialization code Very late in POST it is the signal that the OS has switched to virtual memory mode Memory Error Codes Accompanied by a beep code These codes are used in early POST by Memory Reference Code Later in POST these same codes are used for other Progress Codes These progress codes are subject to change as per Memory Reference Code
29. Intel Xeon Processor 5500 Series with a 4 8 GT s 5 86 GT s or 6 4 GT s Intel QPI link interface and Thermal Design Power TDP up to 95 W The server boards do not support previous generations of the Intel Xeon Processors For a complete updated list of supported processors see http support intel com support motherboards server S5520HC On the Support tab look for Compatibility and then Supported Processor List Note Supports only the Inte Xeon Processor 5500 Series with 4 8 GT s 5 86 GT s or 6 4 GT s Intel QPI link interface 3 2 1 Processor Population Rules You must populate processors in sequential order Therefore you must populate Processor socket 1 CPU 1 before processor socket 2 CPU 2 When only one processor is installed it must be in the socket labeled CPU1 which is located near the rear edge of the server board When a single processor is installed no terminator is required in the second processor socket For optimum performance when two processors are installed both must be the identical revision and have the same core voltage and Intel QPl core speed 3 2 2 Mixed Processor Configurations The following table describes mixed processor conditions and recommended actions for the Intel Server Boards S5520HC and S5500HCV Errors fall into one of three categories e Halt If the system can boot it pauses at a blank screen with the text Unrecoverable fatal error found System will not boot
30. It displays the major menu selections available to the user By using the left and right arrow keys the user can select the menus listed here Some menus are hidden and become available by scrolling off the left or right of the current selections 5 3 2 Server Platform Setup Utility Screens The following sections describe the screens available for the configuration of a server platform In these sections tables are used to describe the contents of each screen These tables follow the following guidelines The Setup Item Options and Help Text columns in the tables document the text and values that also display on the BIOS Setup screens In the Options column the default values are displayed in bold These values are not displayed in bold on the BIOS Setup screen The bold text in this document serves as a reference point The Comments column provides additional information where it may be helpful This information does not display on the BIOS Setup screens Information enclosed in angular brackets lt gt in the screen shots identifies text that can vary depending on the option s installed For example Current Date is replaced by the actual current date Information enclosed in square brackets in the tables identifies areas where the user must type in text instead of selecting from a provided option Whenever information is changed except Date and Time the systems requires a save and reboot to take place
31. Main screen select Boot Options CDROM Order Boot Options CDROM 1 lt Available CDROM devices gt CDROM 2 lt Available CDROM devices gt Figure 40 Setup Utility CDROM Order Screen Display 98 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 38 Setup Utility CDROM Order Fields Setupitem Options HeppTet Commens CDROM 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group CDROM 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 5 Floppy Order Screen The Floppy Order screen allows the user to control the floppy drives To access this screen from the Main screen select Boot Options Floppy Order Boot Options Floppy Disk 1 lt Available Floppy Disk gt Floppy Disk 2 lt Available Floppy Disk gt Figure 41 Setup Utility Floppy Order Screen Display Table 39 Setup Utility Floppy Order Fields _ Setup lem Options Help Text Comments Floppy Disk 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Floppy Disk 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Revi
32. Memory Access Direct Platform Control D D D E IDXE Driver eXecution Environment EEPROM Electrically Erasable Programmable Read Only Memory EFUP Environment Friendly Usage Period EHCI Enhanced Host Controller Interface Electromagnetic Compatibility Emergency Management Port 174 Revision 1 2 Intel order number E39529 009 RP TS BS EV MC S yte L CA MA PC XE CC MC MP PS SI MB RB RU Ww WH B Intel amp Server Board S5520HC S5500HCV TPS Glossary GPA HPA HSC Intel Architecture Local Directory Authentication Protocol Light Emitting Diode Low Pin Count Least Significant Bit Logical Unit Number Media Access Control Open Loop Thermal Throttling Physical Address Extension Revision 1 2 175 Intel order number E39529 009 Glossary Intel Server Board S5520HC S5500HCV TPS POST Power on Self Test PWM Pulse Width Modulation Qm QwkPahiteomed RAS _ Reliability Availability and Serviceability Reliability Availability Serviceability Usability and Manageability ROM RedOnyMemmy SSCS RTC Real Time Clock Component of ICH peripheral chip on the server board SAS s SOR SewwDaaReod S S S SEL Sy emEvmlog OOOO S SCSI Enclosure Services EM Server Management Interrupt SMI is the highest priority nonmaskable interrupt S S Server Management Software S SNMP Simple Network Management Protocol Se
33. PN DATALO Differential data line paired with DATAHO USB PP DATAHO Differential data line paired with DATALO Intel amp Server Board S5520HC S5500HCV TPS Two 2x5 connectors on the server boards J1D1 J1D2 provide support for four additional USB ports J1D2 is recommended for front panel USB ports Table 62 Internal USB Connector Pin out J1D1 Pim SignalName Description 6 USB ICH P5P CONN USB port 6 positive signal Ground Ll c 9 Ky Non O Table 63 Internal USB Connector Pin out J1D2 CPin Signal Name USB PWR68 5VSB USB power port 6 2 USB PWR68 5VSB USB power port 8 3 USB ICH P6N CONN USB port 6 negative signal USB ICH P8N CONN USB port 8 negative signal 6 USB ICH PBP CONN USB por 8 positive signal 7 s Te Gem 9 ky Non o One low profile 2x5 connector J2D2 on the server boards provides an option to support a low profile USB Solid State Drive 114 Intel order number E39529 009 Revision 1 2 Intel Server Boards S5520HC and S5500HCV TPS Connector Header Locations and Pin outs Table 64 Pin out of Internal Low Profile USB Connector for Solid State Drive J2D2 2 3 Not Connected 5 USB Data USB port 11 positive signal Not Connected The server boards provide one additional Type A USB port J1H2 to support the installation of a USB device inside the server chassis Table 65 Internal Ty
34. Power down the system and remove the AC power cord Open the server chassis 10 Move the BIOS recovery jumper J1E5 from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 11 Close the server chassis 12 Reconnect the AC power cord and power up the server Warning DO NOT interrupt the BIOS POST during the first boot after the BIOS recovery 120 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Intel amp Light Guided Diagnostics 8 Intel Light Guided Diagnostics Both server boards have several onboard diagnostic LEDs to assist in troubleshooting board level issues This section provides a description of the location and function of each LED on the server boards 8 1 5 volt Stand by LED Several server management features of these server boards require a 5 V stand by voltage supplied from the power supply The features and components that require this voltage must be present when the system is power down include the Integrated BMC onboard NICs and optional Intel RMM3 installed in the Intel RMM3 slot The LED is located near the Intel SAS Entry RAID Module AXX4SASMOD slot in the lower left corner of the server boards and is labeled 5VSB LEID It is illuminated when AC power is applied to the platform and 5 V stand by voltage is supplied to the server board by the power supply
35. Pressing lt ESC gt discards the changes and boots the system according to the boot order set from the last boot 70 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 1 Main Screen Unless an error occurred the Main screen is the first screen displayed when the BIOS Setup is entered If an error occurred the Error Manager screen displays instead Advanced Security Server Management Boot Options Boot Manager Logged in as lt Administrator or User gt Platform ID lt Platform Identification String gt System BIOS Version S5500 86B xx yy zzzz Build Date MM DD YYYY 7 Memory Total Memory How much memory is installed Quiet Boot Enabled Disabled POST Error Pause Enabled Disabled System Date Current Date System Time Current Time Figure 22 Setup Utility Main Screen Display Table 20 Setup Utility Main Screen Fields Setup Item Options Help Text Comments Logged in as Information only Displays password level that setup is running in Administrator or User With no passwords set Administrator is the default mode Platform ID Information only Displays the Platform ID System BIOS Version Information only Displays the current BIOS version xx 7 major version yy minor version ZZZZ build number Build Date Information only Displays the current BIOS build date Revision 1 2 71 Intel order number E39529
36. SN ON o E o E os 0 043 EU DT 20 1 09 u onoo coco CH 0 000 ims M O ERE 0 010 0 00 i 0 251 0 290 DI 1 37 IN 0 840 ide 21 34 29 85 dl men 2 000 50 801 4 2 364 i 8 05 i lt 3 Gei Sa o 5 H Hh 650 92 11 Fil L 4 200 p 4 511 fe USR 114 581 rj T 5 685 2g 2 144 40 SES mem En H elef 6 380 I 162 05 i A 1 015 H Oo 179 711 Hz 1 546 i 1186 59 1 110 J 1 846 197 361 fl lat 199 29 II 8 465 8 500 215 01 vm WS E NP 50 9 104 Aa P 231 241 Ik Bis o 7 L s sic e 11 512 ie 292 411 ic H o 3 d Dun 11 700 a L 297 18 1 750 WW 298 45 Oo 12 420 4 D 12 450 315 41 316 231 12 440 315 98 aS eats Rnatest E a v3 ECKER gs Sz Ss A mm ow zg 2 e Figure 6 Major Connector Pin 1 Locations 2 of 2 10 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS COMPONENT HEIGHT RESTRICTIO 0 185 MAX MEMORY VR HEATSINK KEEPOUT AREA MAX COMPONENT HEIGHT 0 029 INCHES 2 PLACES MEMORY CR HS SIDE FIN KEEPOUT AREA MAX COMPONENT HEIGHT 0 295 INCHS 2PLACES A SS 0 100 2 54MM MAX COMPONENT HEIGHT S SSS COMPONENT HEIGHT RESTRICTION 0 130 MAX 7 GG SEE DETAIL A aN 3 e SO TYLERSBURG NO COMPONENT ZONE SSS 7 Fd m SS TYLERSBURG BARE DIE HEATSINK 0 063 1 6MM MAX COMPONENT HE
37. Server Boards S5520HC and S5500HCV TPS Connector Header Locations and Pin outs Pn SgmiNam 9 NCAMDP NIC LINKA 1000 N LED Revision 1 2 111 Intel order number E39529 009 Connector Header Locations and Pin outs 6 5 3 The server boards provide up to six SATA connectors SATA 0 J1G5 SATA 1 J1G4 SATA SATA Connectors Intel amp Server Board S5520HC S5500HCV TPS 2 J1G1 SATA 3 J4F4 SATA 4 J1F1 and SATA 5 J1E3 The pin configuration for each connector is identical and defined in the following table 6 5 4 The server boards provide one SAS module slot J2J1 to support the Intel SAS Entry RAID Table 57 SATA SAS Connector Pin out J1E3 J1G1 J1G4 J1G5 J1F1 J1F4 Signal Name Ground SATATX P C Positive side of transmit differential pair SATA TX_N_C Negative side of transmit differential pair SATA RX NC Negative side of receive differential pair SATA RX PC Positive side of receive differential pair SAS Module Slot Module AXX4SASMOD card The following table defines the pin out 112 Table 58 SAS Module Slot P3V3 AUX 2 4 SW RAID MODE PE ICH10 SAS SW C TPO 6 PE ICH10 SAS SW C TP1 ND N PE ICH10 SAS SW C TN2 PE ICH10 SAS SW C TN3 PE WAKE N Pin out J2J1 RST LPC SAS N PE ICH10 SAS SW C TNO PE ICH10 SAS SW C TN1 N N PE ICH10 SAS SW C TN2 PE ICH10 SAS SW C TN3 FM SAS RST N PE ICH10 SAS SW RXNO
38. Side Keep out Zone 1 of 2 11 Intel order number E39529 009 Overview Intel amp Server Boards S5520HC and S5500HCV TPS BARE DIE HEATSINK WIRE CLIP AREA MAX COMPONENT HEIGHT 0 078 2MM NO COMPONENT FOR ANCHORS SOLDERING BARE DIE HEATSINK ANCHOR SOLDERING AREA NO COMPONENT ALLOWED DETAIL A SCALE 4 000 Figure 8 Primary Side Keep out Zone 2 of 2 12 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Overview o o o o o i oO Oo 1 fe 0 H 4 H D H A H A H D H A p D H gi H g Max component height 0 0 mil n 4 H 4 p o H H D g A A ni H P 6 o o H H d V gO OF i H D 3 OY 0 GH 4 po j 0 H Mox component height 0 0 mil j 6 places fe se p Q H d di k QzZZZZZZZZZZZZ A i vA N d H f i H N H o fe 4 4 H H 4 Mox component height 50 mil o o S D 4 g o f gl ox component height 250 mil j 9 places o Mox component height 83 mil S Max component height 472 mil 3 o Oo Oo i m 3 EO Oo PSS o Mox component height 4T2mil Oo o o d DI gu LV iN NN ox component height 0 0 mil Figure 9 Primary Side Air Duct Keep out Zone Revision 1 2 13 Intel order number E39529 009 Overview Intel amp Server Boards S5520HC and S5500HCV TPS COMPONENT HEIGHT RESTRICTION 0 200 MAX 2 PLACES COMPONENT HEIGHT RESTRICTION 0 200 MAX 24 PLACES COMPONENT HEIGHT RESTRICT
39. Signal testing support The BMC provides test commands for setting and getting platform signal states The BMC generates diagnostic beep codes for fault conditions System GUID storage and retrieval Front panel management The BMC controls the system status LED and chassis ID LED It supports secure lockout of certain front panel functionality and monitors button presses The chassis ID LED is turned on using a front panel button or a command Power state retention Power fault analysis Intel Light Guided Diagnostics Power unit management Support for power unit sensor The BMC handles power good dropout conditions DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings Address Resolution Protocol ARP The BMC sends and responds to ARPs supported on embedded NICs Dynamic Host Configuration Protocol DHCP The BMC performs DHCP supported on embedded NICs Platform environment control interface PECI thermal management support E mail alerting Embedded web server Integrated KVM Integrated Remote Media Redirection Local Directory Access Protocol LDAP support Intel Intelligent Power Node Manger support 56 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Platform Management 4 2 Optional Advanced Management Feature Support This section
40. Socket Zb Sc SE EHI P l o WU X V T S R Q Callout Description Callout Description A Slot 1 32 bit 33 MHz PCI Keying for 5V and w System Fan 2 Header 6 pin Universal B Intel RMM3 Slot X System Fan 1 Header 6 pin C Slot 2 PCI Express x4 x8 Mechanically Y Main Power Connector D Low profile USB Solid State Drive Header Z LCP IPMB Header E Slot 3 PCI Express Gen2 x8 AA Type A USB Port F Slot 4 PCI Express Gen2 x8 BB SATA SGPIO Header Slot 5 PCI Express Gen2 x8 Empty on Intel G Server Board S5500HCV Ge H S5520HC Slot 6 PCI Express Gen2 x8 x16 DD SATA Port 1 6 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Overview Callout Description Callout Description Mechanically S5500HCV Slot 6 PCI Express Gen x4 x16 Mechanically I Battery EE HSBP B J Back Panel I O Ports FF SATA Port 2 K Diagnostic and Identify LED s GG HSBP A L System Fan 5 Header 4 pin HH SATA Port 3 M Power Connector for Processor 1 and Memory T SATA Software RAID 5 Key Header attached to Processor 1 N Processor 1 Fan Header 4 pin JJ Chassis Intrusion Header O DIMM Sockets of Memory Channel A B and C KK SATA Port 4 P Power Connector for Processor 2 and Memory LL SATA Port 5 attached to Processor 2 HDD Activity LED Header Connect to Q Auxiliary Power Signal Connector MM Add in Card HDD Activity LED Header Ae USB Connector 9 pin fo
41. Trig Offset P1 Therm Ctrl 01h Oth Processor 2 Thermal Dual Temperature Threshold Control processor Non fatal Trig Offset P2 Therm Ctrl 95 only on oih Digital Processor 1 VRD Tem Temperature Limi p p Discrete 01 Limit Fatal ge ge Trig Offset P1 VRD Hot 01h Osh exceeded Digital Processor 2 VRD Tem Dual Temperature H Limi j processor S Discrete et Fatal i gn Trig Offset P2 VRD Hot M exceeded Processor Digital Discrete GES Non fatal i eim Trig Offset 03h CPU Missing Processor Digital 01 State e ang d Discrete Fatal Trig Offset CPU Missing Ban Asserted IOH Thermal Trip Temperature Digital 01 State ne du All Discrete Fatal Trig Offset IOH Thermal Trip 01h Gah Asserted Note 1 Sensor only present on systems that have applicable redundancy for instance a fan or power supply Catastrophic Error CATERR 160 Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Appendix D Platform Specific BMC Appendix Appendix D Platform Specific BMC Appendix Table 82 Platform Specific BMC Features Y Support Intel Server Chassis Intel Server Chassis Intel Server Chassis Intel Server Chassis Intel Server N Not Support SC5650DP SC5650BRP SC5600Base SC5600BRP Chassis SC5600LX Intel Server Board S5520HC Compatible Compatible Compatible Compatible Compatible Intel Server Board S5500HCV Com
42. a menu the parent menu is re entered When the Esc key is pressed in any sub menu the parent menu is re entered When the lt Esc gt key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded If No is selected and the Enter key is pressed or if the Esc key is pressed the user is returned to where they were before Esc was pressed without affecting any existing settings If Yes is selected and the Enter key is pressed the setup is exited and the BIOS returns to the main System Options Menu screen The up arrow is used to select the previous value in a pick list or the previous option in a menu item s option list The selected item must then be activated by pressing the Enter key The down arrow is used to select the next value in a menu item s option list or a value field s pick list The selected item must then be activated by pressing the Enter key The left and right arrow keys are used to move between the major menu pages The keys have no effect if a sub menu or pick list is displayed The lt Tab gt key is used to move between fields For example you can use Tab to move from hours to minutes in the time item in the main menu The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full list
43. acceptances all three marks accepted worldwide will be implemented on Intel s cardboard and fiberboard Examples of marks are shown below lt gt OX fy XS Zi Co we 10 7 CA Perchlorate Warning CA Lithium Perchlorate Warning California Code of Regulations Title 22 Division 4 5 Chapter 33 Best Management Practices for Perchlorate Materials The State of California requires a warning to be included for products containing a device using Lithium Perchlorate Intel understands CA Lithium Perchlorate require a printed warning to be included with all products containing a Lithium battery either as an insert in existing product literature or as part of the shipping memo wording Wording is as follows Perchlorate Material special handling may apply See www dtsc ca gov hazardouswaste perchlorate This notice is required by California Code of Regulations Title 22 Division 4 5 Chapter 33 Best Management Practices for Perchlorate Materials This product part includes a battery that contains Perchlorate material 10 8 End of Life Product Recycling Product recycling and end of life take back systems and requirements vary by country Contact the retailer or distributor of this product for information about product recycling and or take back Revision 1 2 145 Intel order number E39529 009 Appendix A Integration and Usage Tips Intel Server Board S5520HC S5500HCV TPS 146 Appendix A Integration and Usage Ti
44. assor Value Data y Offsets 05 Non redunaant Non fatal insufficient resources 06 Non Redundant degraded from Degraded fully redundant 07 Redundant degraded from Degraded non redundant 00 Presence OK 01 Failure Degraded Sensor 02 Predictive Rewer SUPPI Tersus 50h ern FONET HERE Specific giis Asand Trig Offset A X PS1 Status specifie 08h 6Fh 03 A C lost Degraded De 06 Configuration OK error 00 Presence 01 Failure we Sensor 02 Predictive Power Supply 2 Status is Power Suppl i egraded pply 51h pios PPY Specific Failure E gie Trig Offset PS2 Status H 08h 6Fh 03 A C lost Degraded 06 Configuration error Power Supply 1 d nc is Other Units Threshold AC Power Input 52h Chassis u c nc Degraded Asand Analog R T A x specific OBh 01h e De PS1 Power In c Non fatal 158 Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Full Sensor Name Platform Sensor name in SDR Power Supply 2 AC Power Input PS2 Power In Chassis specific Applicability Contrib T A j Readabl Event Offset ontrib To ssert e Appendix C BMC Sensor Tables System De Triggers Status assert Value Offsets Event Sensor Type Reading Type Other Units Threshold OBh Oth nc Degraded c Non fatal Power Supply 1 12V of Maximum Current Output PS1 Curr Out Power Supply 2 12V of Maximum Current Outp
45. can contain a Host Bridge and several endpoints I O devices The signaling bit rate is 2 5 Gb s one direction per lane for Gen1 and 5 0 Gb s one direction per lane for Gen2 Each port consists of a transmitter and receiver pair A link between the ports of two devices is a collection of lanes x1 x2 x4 x8 x16 and so forth All lanes within a port must transmit data using the same frequency The PCI buses comply with the PCI Local Bus Specification Revision 2 3 The following tables list the characteristics of the PCI bus segments Details about each bus segment follow the tables Table 8 Intel Server Board S5520HC PCI Bus Segment Characteristics PCI Bus Segment Voltage Width Speed PCI I O Card Slots 32 bit PCI32 5V 33 MHz PCI PCI Slot 1 ICH10R PE1 PE2 PE3 10 Gb s PCI x4 PCI Express Gen1 throughput to Slot 2 Express x8 mechanically and Intel SAS Entry Gen1 RAID Module AXX4SASMOD slot Default to Slot 2 and switch to SAS Module slot when Intel SAS Entry RAID Module AXX4SASMOD is detected This PCI Express Gen1 slot is not available when the SAS module slot is in PE4 use and vice versa ICH10R PCI ICH10R PCI 2 5 Gb s PCI x1 PCI Express Gen1 throughput to Express onboard Integrated BMC Express Port Gen1 3 3 V x4 Express Ports PE1 PE2 3 3 V x4 10 Gb s PCI x4 PCI Express Gen1 throughput to 5520 IOH PCI Express onboard NIC 82575EB Express Ports Gen1 PE5 PE3 PE4 40 Gb S PCI x8 PCI Ex
46. component encountered a high voltage error No Pause 0xA421 PCI component encountered a SERR error Halt OxA5A4 PCI Express IBIST error 0xAGAO DXE boot services driver Not enough memory available to shadow a legacy No Pause option ROM 0xB6A3 DXE boot services driver Unrecognized 170 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Appendix F POST Error Messages and Handling POST Error Beep Codes The following table lists the POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users of error conditions The beep code is followed by a user visible code on the POST Progress LED s Table 86 POST Error Beep Codes Error Message POST Progress Description Code Memory error Multiple System halted because a fatal error related to the memory was detected The BMC may generate beep codes upon detection of failure conditions Beep codes are sounded each time the problem is discovered such as on each power up attempt but are not sounded continuously Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 87 BMC Beep Codes Reason for Beep Associated Sensors 1 5 2 1 CPU Empty slot Population error CPU sockets are populated incorrectly CPU1 must be populated before CPU2 1 5 4 2 Power fault DC power unexpectedly lost power good Power unit power unit failure offse
47. finds the DIMM population is not suitable for mirroring it falls back to the default Independent Channel mode with maximum interleaved memory 3 3 9 Memory Population and Upgrade Rules Populating and upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the following factors Current RAS mode of operation Existing DDR3 DIMM population DDR3 DIMM characteristics 34 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture Optimization techniques used by the Intel Xeon Processor 5500 Series to maximize memory bandwidth In the Independent Channel mode all the DDR3 channels operate independently Slot to slot DIMM matching is not required across channels for example A1 and B1 do not have to match each other in terms of size organization and timing DIMMs within a channel do not have to match in terms of size and organization but they operate in the common frequency Also you can use the Independent Channel mode to support single DIMM configuration in Channel A and in the Single Channel mode You must observe and apply the following general rules when selecting and configuring memory to obtain the best performance from the system Mixing RDIMMs and UDIMMs is not supported You must populate CPU1 socket first in order to enable and operate CPU2 socket When CPU2 socket is empty DIMMs populated in slots D1 through F2 are unusable
48. from the BIOS Setup to configure the system for memory throttling and fan speed control If the 62 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Platform Management BIOS fails to get the Thermal SDRs then it uses the Memory Reference Code MRC default settings for the memory throttling settings The F2 BIOS Setup Utility provides options to set the fan profile or operating mode the platform will operate under Each operating mode has a predefined profile for which specific platform targets are configured which in turn determines how the system fans operate to meet those targets Platform profile targets are determined by which type of platform is selected when running the FRUSDR utility and by the BIOS settings configured using the F2 BIOS Setup 4 3 2 2 1 Fan Domains System fan speeds are controlled through pulse width modulation PWM signals which are driven separately for each domain by integrated PWM hardware Fan speed is changed by adjusting the duty cycle which is the percentage of time the signal is driven high in each pulse Refer to Appendix D for system specific fan domains Table 17 S5520HC and S5500HCV Fan Domain Table Fan Domain Onboard Fan Header Fan Domain 0 CPU 1 Fan CPU 2 Fan Fan Domain 1 System Fan 5 Fan Domain 2 System Fan 1 System Fan 2 Fan Domain 3 System Fan 3 System Fan 4 4 3 2 3 Configuring the Fan Profile Using the BIOS Setup Utilit
49. functionality provided by the SPS firmware is different from Intel Active Management Technology Intel AMT provided by the ME on client platforms Revision 1 2 65 Intel order number E39529 009 Platform Management Intel amp Server Boards S5520HC and S5500HCV TPS REPEATER SMBus p 3 3VSB 3 3V Mux CPU 2 pcass15 D j 1 DDR3 DIMMS S x Fi ER 1 CPU2 CH AO CPU1 CH AO amp D CLK509B E 74Mcaos2 1 xn E 0xA0 L 3 r r CPU2 CH A1 CPU1 CH A1 v 0x02 8 XDPO h d azn l OxA2 8 CPU 1 D DB803 CPU2 CH BO CPU1 CH BO e e l OxA4 k l OxAA i 0xDC f d FRU I A CPU2 CH B1 A CPU1 CH B1 l QxA0 1 OxA6 IOH SMBus ISO mn ISL90728 OxEo r 1 L OxAB VREF FOR DIMM PEHPSMB 33vsB 33vsB 4 CHANNEL A B C ME FRONI RANE LII CPU2CH co CPU1 CH CI H U1 CH CO T vie gmail amp SL90727 l Exe T 1 towns VREF FOR DIMM 1 x e CHANNEL DEE CPU2CH C1 CPU1 CH C1 a TEMP SENSOR SS meam 1 AA TMP75 Y Ki Ox9E ICH10R SMBus 0x88 P SMLink REPEATER POWER SUPPLY Bei LO 3 3VSB 5v FRU OXAC PCA9515 PSMI OxBO NIC 82575EB HSBP SMBus Conn A 0xCe l OxC8 L 4 0xco E i HSBP n9 e ri gt ISO A k 5vsB sv j 0xC2 RI IE 5 33v STBY IPM BUS 3 3vse svse j H Si E 2i Soe wi IPMI C i I X Conn 5 4 3 2 1 o SM Bus
50. installation instructions see the documentation accompanying the server boards and the activation key When Intel Embedded Server RAID Technology II of the SATA controller is enabled enclosure management is provided through the SATA SGPIO connector on the server boards when a cable is attached between this connector and the backplane or I C interface See Figure 3 Major Board Components for the locations of Intel RAID Activation Key connector and SATA SGPIO connector Intel Embedded Server RAID Technology II functionality requires the following items e ICH10R I O Controller Hub e Software RAID option is selected on the BIOS menu for the SATA controller Revision 1 2 39 Intel order number E39529 009 Functional Architecture e Intel Embedded Server RAID Technology Il Option ROM Intel Embedded Server RAID Technology II drivers most recent revision e Atleast two SATA hard disk drives 3 4 1 1 1 Intel Embedded Server RAID Technology II Option ROM Intel amp Server Boards S5520HC and S5500HCV TPS The Intel Embedded Server RAID Technology II for SATA Option ROM provides a pre operating system user interface for the Intel Embedded Server RAID Technology II implementation and provides the ability to use an Intel Embedded Server RAID Technology II volume as a boot disk and detect any faults in the Intel Embedded Server RAID Technology Il volume s 3 4 1 2 Onboard SATA Storage Mode Matrix Table 7 Onboard SATA Sto
51. of Tables Intel Server Boards S5520HC and S5500HCV TPS Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 xii Setup Utility Server Management System Information Fields 93 Setup Utility Boot Options Screen Fields sssssssssssseseeee 95 Setup Utility Add New Boot Option Fields sseeeseeeeeeee 96 Setup Utility Delete Boot Option Fields sssssseseeeee 97 Setup Utility Hard Disk Order Fields 98 Setup Utility CDROM Order Fields 99 Setup Utility Floppy Order Fields 99 Setup Utility Network Device Order Fields sssssseseeeee 100 Setup Utility BEV Device Order Fields sssssseeee 101 Setup Utility Boot Manager Screen Fields 101 Setup Utility Error Manager Screen Fields nnnnnneneneeneneeeeeeereerrrrrrrrnrnrneseseene 102 Setup Utility Exit Screen Fields 103 Board Connector Matrix essen enne eter 105 Main Power Connector Pin out LUIR 106 CPU 1 Power Connector Pin out OUOAT 107 CPU 2 Power Connector Pin out O
52. or NIC2 ROMs Warning If Disabled is selected NIC1 and NIC2_ 9 enabled cannot be used to boot or wake the system NIC 1 MAC Address No entry Information only 12 hex allowed digits of the MAC address NIC 2 MAC Address No entry Information only 12 hex allowed digits of the MAC address 5 3 2 2 7 System Acoustic and Performance Configuration The System Acoustic and Performance Configuration screen allows the user to configure the thermal characteristics of the system To access this screen from the Main screen select Advanced System Acoustic and Performance Configuration Advanced System Acoustic and Performance Configuration Set Throttling Mode Auto CLTT OLTT Altitude 300m or less 301m 900m 901m 1500m Higher than 1500m Set Fan Profile Performance Acoustic Figure 31 Setup Utility System Acoustic and Performance Configuration Screen Display 86 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 29 Setup Utility System Acoustic and Performance Configuration Screen Fields Setupltem Options Help Text Set Throttling Auto Auto Throttling mode Mode CLTT Closed Loop Thermal Throttling Mode OLTT Open Loop Thermal Throttling Mode Altitude 300m or less 300m or less 980ft or less 301m 900m Optimal performance setting near sea level 901m 1500m 301m 900m 980ft 2950ft Highe
53. point between various I O components and Intel QPI based processors which includes the following core platform functions Intel QPI link interface for the processor subsystem PCI Express Ports Enterprise South Bridge Interface ESI for connecting Intel ICH10R Manageability Engine ME Controller Link CL SMBus Interface Intel Virtualization Technology for Directed I O Intel VT d The following table shows the high level features of the Intel 5520 and 5500 IOH Table 1 IOH High Level Summary IOH Intel QPI Supported Processor PCI Express Manageability SKU Ports Lanes 5520 2 Intel Xeon Processor 5500 Series 36 Intel Intelligent Power Node Manager 5500 2 Intel Xeon Processor 5500 Series 24 Intel Intelligent Power Node Manager 3 1 1 Intel QuickPath Interconnect The Intel Server Boards S5520HC and S5500HCV provide two full width cache coherent link based Intel QuickPath Interconnect interfaces from Intel 5520 and 5500 IOH for connecting Intel QPI based processors The two Intel QPI link interfaces support full width communication only and have the following main features e Packetized protocol with 18 data protocol bits and 2 CRC bits per link per direction wv Supporting 4 8 GT s 5 86 GT s and 6 4 GT s e Fully coherent write cache with inbound write combining e Read Current command support e Support for 64 byte cache line size 3 1 2 PCI Express Ports
54. product marking and controlled substance information Environmental Friendly Usage Period EFUP Marking Is defined in number of years in which controlled listed substances will not leak or chemically deteriorate while in the product Intel understands the end seller entity placing product into market place is responsible for providing EFUP marking e Intel retail products are provided with EFUP marking e For Business to Business products Intel intends to place EFUP marking on product for customer convenience 142 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Regulatory and Certification Information e EFUP for Intel server products has been determined as 20 years Below is an example of EFUP mark applied to Intel server products 2 CROHS Substance Tables China CRoHS requires products to be provided with controlled substance information Intel understands the end seller entity placing product into market place is responsible for providing the controlled substance information Controlled substance information is required to be in Simplified Chinese Substance table for this board product is as follows Revision 1 2 143 Intel order number E39529 009 Regulatory and Certification Information Intel Server Board S5520HC S5500HCV TPS XT STE EFE SXEBIEIZE HE Management Methods on Control of Pollution from Electronic Information Products China RoHS declaration Pug UBEUREUBRISST
55. supported bus throughput for the given riser card used and the number of add in cards installed Table 11 PCI Riser Support PCI Express Gen2 Slot 6 Riser Support One Add in card Two Add in cards Type 1 Riser Card x8 N A Type 2 Riser Card x4 x4 There are no population rules for installing a single add in card in the Type 2 riser card you can install a single add in card in either PCI Express slot Revision 1 2 Intel order number E39529 009 45 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 6 Intel SAS Entry RAID Module AXX4SASMOD Optional Accessory The Intel Server Boards S5520HC and S5500HCV provide a Serial Attached SCSI SAS module slot J2J1 for the installation of an optional Intel SAS Entry RAID Module AXX4SASMOD Once the optional Intel SAS Entry RAID Module AXX4SASMOD is detected the x4 PCI Express links from the ICH10R to Slot 2 x8 mechanically x4 electrically switches to the SAS module slot The Intel SAS Entry RAID Module AXX4SASMOD includes a SAS1064e controller that supports x4 PCI Express link widths and is a single function PCI Express end point device The SAS controller supports the SAS protocol as described in the Serial Attached SCSI Standard version 1 0 and also supports SAS 1 1 features A 32 bit external memory bus off the SAS1064e controller provides an interface for Flash ROM and NVSRAM Non volatile Static Random
56. the system configuration Only enable for an OS without PAE support Memory Mapped UO Enabled Enable or disable memory mapped I O of 64 bit above 4GB Disabled PCI devices to 4 GB or greater address space Onboard Video Enabled Onboard video controller When disabled the system Disabled Warning System video is completely disabled if requires an add in video this option is disabled and an add in video adapter Card for the video to be is not installed seen Dual Monitor Video Enabled If enabled both the onboard video controller and Disabled an add in video adapter are enabled for system video The onboard video controller becomes the primary video device Onboard NIC1 ROM Enabled If enabled loads the embedded option ROM for Disabled the onboard network controllers Warning If Disabled is selected NIC1 cannot be used to boot or wake the system Revision 1 2 85 Intel order number E39529 009 BIOS Setup Utility Intel amp Server Board S5520HC S5500HCV TPS Setupltem Options h amp HelpText TI Commens Onboard NIC2 ROM Enabled If enabled loads the embedded option ROM for Disabled the onboard network controllers Warning If Disabled is selected NIC2 cannot be used to boot or wake the system Onboard NIC iSCSI Enabled If enabled loads the embedded option ROM for This option is grayed out ROM Disabled the onboard network controllers and not accessible if either the NIC1
57. values from the event reading type code ranges and the generic event reading type code tables in the ntelligent Platform Management Interface Specification Second Generation v2 0 Digital sensors are a specific type of discrete sensors that only have two states Event Offset Triggers Event Thresholds are event generating thresholds for threshold type sensors u nr c nc upper non recoverable upper critical upper non critical lower non recoverable lower critical lower non critical uc Ic upper critical lower critical Event triggers are supported event generating offsets for discrete type sensors You can find the offsets in the generic event reading type code or sensor type code tables in the ntelligent Platform Management Interface Specification Second Generation v2 0 depending on whether the sensor event reading type is generic or a sensor specific response Assertion De assertion Enables Assertion and de assertion indicators reveal the type of events the sensor generates As Assertions De De assertion Readable Value Offsets Readable Values indicate the type of value returned for threshold and other non discrete type sensors Readable Offsets indicate the offsets for discrete sensors that are readable with the Get Sensor Reading command Unless otherwise indicated all event triggers are readable Readable Offsets consist of the reading type offsets that do not generate events Event Data Event d
58. 0HC supports up to 12 DIMMs Inte Server Board S5500HCV supports up to 9 DIMMs Both Intel Server Board S5520HC and Intel Server Board S5500HCV support Registered DDR3 DIMMs RDIMMs and ECC Unbuffered DDR3 DIMMs UDIMMs a Mixing of RDIMMs and UDIMMs is not supported Intel order number E39529 009 Revision 1 2 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture a Mixing memory type size speed and or rank on this platform has not been validated and is not supported a Mixing memory vendors is not supported on this platform by Intel a Non ECC memory is not supported and has not been validated in a server environment e Both Intel Server Board S5520HC and Intel Server Board S5500HCV support the following DIMM and DRAM technologies a RDIMMs Single Dual and Quad Rank x4orx8 DRAM with 1 Gb and 2 Gb technology no support for 2 Gb DRAM based 2 GB or 4 GB RDIMMs DDR3 1333 Single and Dual Rank only DDR3 1066 and DDR3 800 a UDIMMs Single and Dual Rank x8 DRAM with 1 Gb or 2 Gb technology DDR3 1333 DDR3 1066 and DDR3 800 3 3 3 Processor Cores QPI Links and DDR3 Channels Frequency Configuration The Intel Xeon 5500 series processor connects to other Intel Xeon 5500 series processors and Intel 5500 5520 IOH through the Intel QPI link interface The frequencies of the processor cores and the QPI links of Intel Xeon 5500 series processor are independent from each other
59. 2 Intel Server Board S5500HQV steet tte reti t teint eda tee E hn rada 5 Figure 3 Major Board Components nennen enne en nennen 7 Figure 4 Mounting Hole Locations 8 Figure 5 Major Connector Pin 1 Locations 1 of 2 9 Figure 6 Major Connector Pin 1 Locations 2 of 2 10 Figure 7 Primary Side Keep out Zone of2 eene 11 Figure 8 Primary Side Keep out Zone 2 of 2 eene 12 Figure 9 Primary Side Air Duct Keep out Zone 13 Figure 10 Primary Side Card Side Keep out Zone ssssssesiereseseererertitrrrrrrrrnrnrnennnesterererere tt 14 Figure 11 Second Side Keep out Zone 15 Figure 12 Rear l O EEayOUt ierit eerte e Pope Cot oe ee te tr ae EES ege 16 Figure 13 Intel Server Board S5520HC Functional Block Diagramm 18 Figure 14 Intel Server Board S5500HCV Functional Block Diagram ssessiisseresiiess1rer1een 19 Figure 15 Unified Retention System and Unified Back Plate Assembly sususs 25 Figure 16 Intel Server Board S5520HC DIMM Slots Arrangement 27 Figure 17 Intel Server Board S5500HCV DIMM Slots Arrangement 28 Figure 18 Intel SAS Entry RAID Module AXX4SASMOD Component and Connector Layout 46 Figure 19 Intel SAS Entry RAID Module AXX4SASMOD Functional Block Diagram 47 Figure 20 Integrated BMC Hardware 50 Figure 21 SMBUS Block Diagram 2 c c cecccceeceeeeee eee ee cette ee ee tesa ees aaaaeaeaeeseeeeeeeeeeeeeeeeeteeeeee 66 Figure 22 Setup Utility
60. 2 Intel Xeon Processor Dual Processor TDP Guidelines ssssees 130 Table 73 670 W Load Ratings ssssssssssssssssesssenenreneneeenenen nennen nennen nnne nennen 130 Table 74 Voltage Regulation Limits sssssssssseseseseeen nennen 132 Table 75 Transient Load Reourements eene nene 132 Table 76 Capacitive Loading Conditions sss 133 Table 7 7 Ripple and Noise center pne creta p ac ra ep eene eed e e Y coe padres 133 Table 78 Output Voltage Timing 134 Table 79 Turn On Off Timing 135 Table 80 Compatible Chassis Heatsink Matrix nnennnnnsneneeseeeresrerrrrrererrerrserssrerrrrrrrrrrrrene 148 Table 81 Integrated BMC Core Sensors nnne nennen nnns 153 Table 82 Platform Specific BMC Features 161 Table 83 POST Progress Code LED Example eene 163 Table 84 POST Codes and Messages ssssssssssssssseeeeeeeen eene rennes 164 Table 85 POST Error Messages and Handimg 168 Table 86 POST Error Beep Codes enne nnns 171 Table 87 BMG Beep Codes erm ERES Rae th Ra E XR REA EXER RENE Fo LN tena EES 171 Intel order number E39529 009 List of Tables Intel Server Boards S5520HC and S5500HCV TPS This page intentionally left blank gt xiv Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Introduction 1 Introduction This Technical Product Specification TPS provides board specific inform
61. 51 Intel order number E39529 009 Functional Architecture 3 11 1 Video Modes Intel amp Server Boards S5520HC and S5500HCV TPS The integrated video controller supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD Table 14 Video Modes 2D Video Mode Support ep Mode 8 bpp 16 bpp 24 bpp 32 bpp Supported Supported Supported Supported 64030480 60 72 75 85 60 72 75 85 60 72 75 85 60 72 75 85 idc s Supported Supported Supported Supported een 56 60 72 75 85 56 60 72 75 85 56 60 72 75 85 56 60 72 75 85 ae Supported Supported Supported Supported TUCKER 60 70 75 85 60 70 75 85 60 70 75 85 60 70 75 85 DE UE Supported Supported Supported N A VINCE DNE 75 75 75 N A ee Supported Supported Supported N A ee 60 75 85 60 75 85 60 NA probus Supported Supported Supported N A Supported Supported N A N A 1600 x 1200 60 65 70 75 85 60 65 70 N A N A ee 3 11 2 Dual Video The BIOS supports single and dual video modes The dual video mode is enabled by default In single mode the onboard video controller is disabled when an add in video card is detected In dual mode enable Dual Monitor Video in the BIOS setup the onboard video controller is enabled and is the primary video device The add in video card is allocated resources and considered the secondary video devi
62. 520HC and S5500HCV Passive tower processor heatsink s product code FXXRGTHSINK is required when installing the Intel Server Board S5520HC or S5500HCV in the Intel Server Chassis SC5600LX Active processor heatsink s is required when installing the Intel Server Board 5520HC or S5500HCV in any of following Intel Server Chassis Intel Server Chassis SC5600Base Intel Server Chassis SC5600BRP Intel Server Chassis SC5650DP Intel Server Chassis SC5650BRP Table 80 Compatible Chassis Heatsink Matrix Heatsink mae Thermal intel Thermal FXXRGTHSINK S5520HC S5500HCV Chassis SKU ineindes Solution STS100C w Solution STS100A fan Active mode Active Passive Tower Heatsink Y Y SC5600Base No Y Y N Y Y SC5600BRP No Y Y N Y Y SC5600LX No N N Required Y Y SC5650DP No Y Y N Y Y SC5650BRP No Y Y N Y Support Maximum CPU N Not Support Bs Support in 95W 80 W 95 W Intel Server Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Appendix B Compatible Intel amp Server Chassis Intel amp Thermal Intel amp Thermal Heatsink FXXRGTHSINK S5520HC S5500HCV Chassis SKU includes Solution STS100C w Solution STS100A N fan Active mode Active Passive Tower Heatsink Chassis Boxed BXSTS100C BXSTS100A FXXRGTHSINK Product Code Note Must install active processor heatsink with the ai
63. 5500HCV which have no TPM Clear Ownership 5 3 2 4 Server Management Screen The Server Management screen allows the user to configure several server management features This screen also provides an access point to the screens for configuring console redirection and displaying system information To access this screen from the Main screen select Server Management Main Advanced Security Server Management Boot Options Boot Manager Assert NMI on SERR Enabled Disabled Assert NMI on PERR Enabled Disabled Resume on AC Power Loss Stay Off Last state Reset Clear System Event Log Enabled Disabled FRB 2 Enable Enabled Disabled O S Boot Watchdog Timer Enabled Disabled O S Boot Watchdog Timer Policy Power off Reset O S Boot Watchdog Timer Timeout 5 minutes 10 minutes 15 minutes 20 minutes ACPI 1 0 Support Enabled Disabled Plug amp Play BMC Detection Enabled Disabled gt Console Redirection gt System Information Figure 33 Setup Utility Server Management Configuration Screen Display Revision 1 2 89 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS Table 31 Setup Utility Server Management Configuration Screen Fields Setup Item Options Help Text Assert NMI on SERR Enabled On SERR generate an NMI and log an error Disabled Note Enabled must be selected for the Assert NMI on PERR setup option to be visible Assert NMI on PE
64. 5520HC and S5500HCV TPS 3 3 4 Publishing System Memory e The BIOS displays the Total Memory of the system during POST if the Quiet Boot is disabled in the BIOS Setup This is the total size of memory discovered by the BIOS during POST and is the sum of the individual sizes of installed DDR3 DIMMs in the system e The BIOS also provides the total memory of the system in the BIOS setup Main page and Advanced Memory Configuration Page This total is the same as the amount described by the previous bullet e The BIOS displays the Effective Memory of the system in the BIOS Setup Advanced Memory Configuration Page The term Effective Memory refers to the total size of all active DDR3 DIMMs not disabled and not being used as redundant units in Mirrored Channel Mode e If Quiet Boot is disabled the BIOS displays the total system memory on the diagnostic screen at the end of POST This total is the same as the amount described by the first bullet 3 3 4 1 Memory Reservation for Memory mapped Functions A region of size of 40 MB of memory below 4 GB is always reserved for mapping chipset processor and BIOS flash spaces as memory mapped I O regions This region appears as a loss of memory to the operating system This and other reserved regions are reclaimed by the operating system if PAE is enabled in the operating system In addition to this memory reservation the BIOS creates another reserved region for memory m
65. 8 10 12 14 16 18 D 20 S 22 P3V3 24 D 28 30 D 32 34 D 36 38 FM SAS PRSNT N PE RXN 2 D D PEICHIS SAS SW C TNS D D D Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Connector Header Locations and Pin outs Pn Name Pim Name 39 D 43 45 CLK_100M_SAS_DN 46 GND 47 GND 48 P3V3 49 6 5 5 Serial Port Connectors The server boards provide one external DB9 Serial A port J8A1 and one internal 9 pin Serial B header J1B1 The following tables define the pin outs Table 59 External DB9 Serial A Port Pin out J8A1 Pin Signal Name DCD carrier detect RXD receive data TXD Transmit data DTR Data terminal ready DSR data set ready RTS request to send RI Ring Indicate Table 60 Internal 9 pin Serial B Header Pin out J1B1 Pim Signal Name Description DCD carrier detect RXD receive data COINI OD a G il A Ke 6 SPBCTS CTS clear to send DTR Data terminal ready 8 SPB_RI BI Bing indicate 9 SPB ENN Enable 6 5 6 USB Connector The following table details the pin out of the external USB connectors J5A1 J6A1 found on the back edge of the server boards Revision 1 2 113 Intel order number E39529 009 Connector Header Locations and Pin outs Table 61 External USB Connector Pin out J5A1 J6A1 Pin Signal Name USB OC 5VSB USB PWR USB
66. AID opens Enabled or Disable the Intel amp SAS Entry RAID Unavailable if the SAS Module Module Disabled Module AXX4SASMOD is not present Configure Intel Entry IT IR RAID IT IR RAID Supports Entry Level HW RAID 0 Unavailable if the SAS Module SAS RAID Module Intel RAID 1 and RAID 1e as well as native SAS AXX4SASMOD is disabled or ESRTII pass through mode Intel ESRTII Intel not present Embedded Server RAID Technology II which supports RAID 0 RAID 1 RAID 10 and RAID 5 mode RAID 5 support requires optional Software RAID 5 Activation Key Onboard SATA Enabled Onboard Serial ATA SATA controller Controller Disabled SATA Mode Enhanced ENHANCED Supports up to 6 SATA ports No longer displays when the Compatibility with IDE Native Mode Onboard SATA Controller is AHCI COMPATIBILITY Supports up to 4 SATA disabled SW RAID ports 0 1 2 3 with IDE Legacy mode and 2 SATA ports 4 5 with IDE Native Mode Changing this setting requires a AHCI Supports all SATA ports using the reboot before you can set the Advanced Host Controller Interface HDD boot order SW RAID Supports configuration of SATA ports for RAID via RAID configuration software SW RAID option is unavailable when EFI Optimized Boot is Enabled SW RAID can only be used in Legacy Boot mode SATA Port 0 lt Not Information only This field is Installed unavailable when RAID Mode is Drive enabled information gt SATA Port 1 l
67. Access Memory devices The Intel SAS Entry RAID Module AXX4SASMOD provides four SAS connectors that support up to four hard drives with a non expander backplane or up to eight hard drives with an expander backplane The Intel SAS Entry RAID Module AXX4SASMOD also provides a SGPIO Serial General Purpose Input Output connector and a SCSI Enclosure Services SES connector for backplane drive LED control Warning Either the SGPIO or the SES connector supports backplane drive LED control Do not connect both SGPIO and SES connectors at the same time Standoff Mounting SES Holes Software RAID 5 Key Header S SAS Module Connector SAS 0 Figure 18 Intel SAS Entry RAID Module AXX4SASMOD Component and Connector Layout 46 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture Software RAID 5 Activation Key header UART SAS Module Connector conn 4pin 50pin RST PWRGD PS SGPIO FM SAS RESET N SGPIO conn 4pin SW RAID Mode PCI Express x4 LED HDD ACT SES 8SAS PRSNT conn 3pin Sg Re T 1 Figure 19 Intel SAS Entry RAID Module AXX4SASMOD Functional Block Diagram 3 6 1 SAS RAID Support The BIOS Setup Utility provides drive configuration options on the Advanced Mass Storage Controller Configuration setup page for the Intel SAS Entry RAID Module AXX4SASMOD some of which af
68. All Voltage Threshold u I c nc Degraded BB 12 0V pen SC c Non fatal Temperature Threshold Mem P2 Thrm Mrgn only 01h 01h 156 Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Sensor Type Reading Contrib To System Status Full Sensor Name Platform Applicability Event Offset Triggers Sensor name in SDR Appendix C BMC Sensor Tables Event Stand Data by Readabl Assert e De assert Value Offsets Fan Tachometer Sensors ee i SORcBOR Chassis Fan Threshold Ill e nc Degraded As and Analog RT e sote om om mI ezwe De fatal2 Fan Present Sensors 40h 45h Chassis Fan Generic 01 Device OK As and Triggered Auto Fan x Present specific 04h 08h inserted De Offset Fan Redundancy 46h Chassis Fan Generic 00 Fully As and Trig Offset A Fan Redundancy specific 04h OBh redundant ER 01 Redundancy lost Degraded 02 Redundancy degraded Degraded 03 Non redundant Sufficient Degraded resources Transition from redundant 04 Non redundant Sufficient Degraded resources Transition from insufficient Revision 1 2 157 Intel order number E39529 009 Appendix C BMC Sensor Tables Intel Server Board S5520HC S5500HCV TPS Readabl Full Sensor Name Platform Event Offset el eet e Event Stand Tn Sensor Type Reading Tri System De b Sensor name in SDR Applicability riggers Status
69. B 1 8V AUX BB 1 8V AUX nc oe bs ee Jul c nc Degraded c Non fatal nc ae HM JI inc Degraded c Non fatal nc Ke a nee Jul c nc Degraded c Non fatal Revision 1 2 155 Intel order number E39529 009 nc xa JM JI inc Dearadad c Non fatal BB 3 3V BB 3 3V l BB 3 3V STBY BB 3 3V STBY Appendix C BMC Sensor Tables Intel Server Board S5520HC S5500HCV TPS Readabl Contrib To Assert e System De Status assert Value Offsets Full Sensor Name Platform Sensor Tyne Reading Event Offset Sensor name in SDR Applicability Triggers nc BB 3 3V Vbat Voltage Threshold Degraded u l c nc 02h Oth BB 3 3V Vbat c Non fatal nc Been Voltage Threshold Degraded BB 5 0V 02h Oth u l c nc Eo c Non fatal nc BB 5 0V STBY All Voltage Threshold u I c nc Degraded BB 5 0V STBY pen du c Non fatal nc BB 12 0V All Voltage Threshold ul c nc Degraded BB 12 0V 92n om c Non fatal Baseboard Temperature Temperature Threshold bn 5 A u 1 c nc Degraded Baseboard Temp 01h 01h ex Non f tal Front Panel Temperature Temperature Threshold Geng id SE u c nc Degraded Front Panel Temp 01h 01h Nen fatal IOH Thermal Margin 22h Ki Temperature Threshold IOH Therm Margin 01h 01h Processor 1 Memory Thermal Margin Temperature Threshold Mem P1 Thrm Mrgn mis oth Processor 2 Memory Dual Thermal Margin processor nc BB 12 0V
70. BIOS Setup utility without saving User prompted for confirmation only if Exit changes any of the setup fields were modified The Esc key can also be used Save Changes Save changes without exiting the BIOS Setup User prompted for confirmation only if Utility any of the setup fields were modified Note Saved changes may require a system reboot before taking effect Discard Changes Discard changes made since the last Save User prompted for confirmation only if Changes operation was performed any of the setup fields were modified Load Default Values Load factory default values for all BIOS Setup User prompted for confirmation utility options The F9 key can also be used Revision 1 2 103 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS Setup Wem Help Text Save as User Default Save current BIOS Setup utility values as User prompted for confirmation Values custom user default values If needed the user default values can be restored via the Load User Default Values option below Note Clearing the CMOS or NVRAM does not cause the User Default values to be reset to the factory default values Load User Default Load user default values User prompted for confirmation Values 104 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Connector Header Locations and Pin outs 6 Connector Header Locations and Pin outs 6 1
71. BMC 12 BMC Firmware Force Update Mode Disabled Default Update 2 3 BMC Firmware Force Update Mode Enabled 7 1 CMOS Clear and Password Reset Usage Procedure The CMOS Clear J1E6 and Password Reset J1E4 recovery features are designed to achieve the desired operation with minimum system down time The usage procedure for these two features has changed from previous generation Intel server boards The following procedure outlines the new usage model 7 1 1 el SS Qv T Clearing the CMOS Power down the server and unplug the AC power cord Open the server chassis For instructions see your server chassis documentation Move the jumper J1E6 from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 Wait five seconds Move the jumper back to the default position covering pins 1 and 2 Close the server chassis and reconnect the AC power cord Power up the server The CMOS is now cleared and you can reset it by going into the BIOS setup 7 1 2 2 Clearing the Password Power down the server Do not unplug the power cord Open the chassis For instructions see your server chassis documentation Move the jumper J1E4 from the default operating position covering pins 1 and 2 to the password clear position covering pins 2 and 3 Close the server chassis Power up the server and then press F2 to enter the BIOS menu to check if the password is clea
72. BP A GND HSBP B Ground for HSBP B 6 3 4 SGPIO Header Table 53 SGPIO Header Pin out J1G2 Pin Signal Name SGPIO CLOCK SGPIO LOAD SGPIO DATAOUTO SGPIO_DATAOUT1 Description SGPIO Clock Signal SGPIO Load Signal SGPIO Data Out SGPIO Data In AJOJN gt 6 4 Front Panel Connector The server boards provide a 24 pin SSI front panel connector J1B3 for use with Intel and third party chassis The following table provides the pin out for this connector Table 54 Front Panel SSI Standard 24 pin Connector Pin out J1B3 Pi Signal Name Description Pi Signal Name Description n n 1 P3V3 STBY Power LED 2 P3V3 STBY Front Panel Power LED Anode Power Power 3 Key No Connection 4 P5V_STBY ID ID LED LED Oh LED Anode OO LED 5 FP PWR LED N PowerLED 6 FP ID LED BUF IDLED HDD L System N LED Status 7 P3V3 HDD Activity 8 VER LED STATU Status LED HDD ACTIVITY Ano LED S GREEN N Green Power L NIC1 de Button LinkActiviy Te T LED HDD ACTIVITY HDD Activity 10 FP LED STATU Status LED Reset Lag N LED S_AMBER_N Amber Button 4 11 FP PWR BTN N Power Button 12 NIC1 ACT LED NIC 1 Activity IDB Chassis N LED utton Intrusion Temp Sensor 1 NIC 13 GND Power Button Power Button 14 NIC1 LINK LED NIC 1 Link LO e GND Ground N LED NMI O O Activity LED 15 BMC RST BTN N Reset Butto
73. C S5500HCV TPS Progress Code Progress Code Definition 0xB8 Resetting the removable media device OxB9 Disabling the removable media device OxBA Detecting the presence of a removable media device CDROM detection etc OxBC Enabling configuring a removable media device Boot Device Select ion OxDy Trying boot selection y where y 0 to F Pre EFI Initializatio n PEI Core not accompanied by a beep code OxEO Started dispatching early initialization modules PEIM OxE2 Initial memory found configured and installed correctly OxE1 0xE3 Reserved for initialization module use PEIM Driver eXecution E nvironment DXE Core not accompanied by a beep code OxE4 Entered EFI driver execution phase DXE OxE5 Started dispatching drivers OxE6 Started connecting drivers DXE Drivers not accompanied by a beep code OxE7 Waiting for user input OxE8 Checking password OxE9 Entering the BIOS Setup OxEA Flash Update OxEE Calling Int 19 One beep unless silent boot is enabled OxEF Unrecoverable Boot failure Runtime Phase EFI Operating System Boot OxF4 Entering the sleep state OxF5 Exiingtheslepstate OxF8 Operating system has requested EFI to close boot services ExitBootServices has been called OxF9 Operating system has switched to virtual address mode SetVirtualAddressMap has been called OxFA
74. C Beep Codes Updated Figure 21 SMBUS Block Diagram revised components code name Updated Figure 53 Power Distribution Block Diagram revised components code name March 2009 July 2009 Updated Section 2 1 the feature set table Updated Section 3 3 2 supported memory Updated Section 3 3 3 Added Section 3 15 Updated Appendix A adding PCI device SEL event decoding tips Updated Appendix G Updated Section 4 2 2 Keyboard Video and Mouse KVM Redirection Updated Table 2 Table 8 Table 9 and Table 25 Updated Figure 13 14 ii Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not
75. C and S5500HCV support Intel I O Acceleration Technology by default The supported Intel I O Acceleration Technology version varies with the network interface card controllers that attached to the server board Intel UO Acceleration Technology version 2 IOAT 2 is supported with onboard Intel 82575EB NICs 54 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Platform Management 4 Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines Pilot Il The onboard platform management subsystem consists of communication buses sensors and the system BIOS and server management firmware Figure 21 provides an illustration of the Server Management Bus SMBUS architecture as used on these server boards 4 1 Feature Support 4 1 1 IPMI 2 0 Features Baseboard management controller BMC IPMI Watchdog timer Messaging support including command bridging and user session support Chassis device functionality including power reset control and BIOS boot flags support Event receiver device The BMC receives and processes events from other platform subsystems Field replaceable unit FRU inventory device functionality The BMC supports access to system FRU devices using IPMI FRU commands System event log SEL device functionality The BMC supports and provides access to a SEL Sensor data record SDR repository device f
76. CI x1 PCI Express Gen1 throughput to onboard Integrated BMC x4 PCI Express Gen2 throughput to onboard NIC 82575EB x4 PCI Express Gen1 throughput to Slot 6 x16 mechanically 10Gb S PCI Express Gen2 40 Gb S PCI Express Gen2 x 40 Gb S PCI Express Express Ports Gen2 3 5 1 PCI Express Riser Slot S5520HC Slot 6 One PCI Express pin is designated as Riser Card Type pin with the definitions noted in the following table for Intel Server Board S5520HC PCI Express slot 6 x8 PCI Express Gen2 throughput to Slot 4 x8 mechanically x1 2 5 Gb s PCI Express Gen1 x4 10 Gb s PCI Express Gen1 8 x8 PCI Express Gen2 throughput to Slot 3 x8 mechanically Table 10 Intel Server Board S5520HC PCI Riser Slot Slot 6 IOH PEWIDTH 2 PCI Riser Strap PCI Express Gen Slot 6 Setup PCI Express Pin A50 RVSD Type 1 Riser One x8 PCI Express Slot Type 2 Riser Two x4 PCI Express Slot 0 1 Maximum power rating of Slot 6 for riser is 75 W provided no card is in slots 3 4 and 5 2 The type 1 riser card must follow the standard PCI Express Adapter pin out and leave pin A50 as a No Connect NC 44 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Functional Architecture 3 The type 2 riser card must connect the PCI Express pin A50 with a 4 7K ohm resistor to pull up to 3 3 V The following table provides the
77. ED Speed LED Link Activity LED fon AeweComeon Transmit Receive activity ro o o Mm CS Green LED Color On Green Left Off Green 100 Mbps Off Green Amber Right 3 12 1 MAC Address Definition Each Intel Server Board S5520HC or S5500HCV has the following four MAC addresses assigned to it at the Intel factory NIC 1 MAC address NIC 2 MAC address is assigned the NIC 1 MAC address 1 BMC LAN Channel MAC address is assigned the NIC 1 MAC address 2 e Intel Remote Management Module 3 Intel RMM3 MAC address is assigned the NIC 1 MAC address 3 During the manufacturing process each server board has a white MAC address sticker placed on the top of the NIC 1 port The sticker displays the NIC 1 MAC address and Intel RMM3 MAC in both bar code and alphanumeric formats Revision 1 2 53 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 13 ACPI Support The Intel Server Boards S5520HC and S5500HCV support SO S1 and S5 states S1 is considered a sleep state The Intel Server Boards S5520HC and S5500HCV can wake up from S1 state using the USB devices in addition to the sources described in the following paragraph The wake up sources are enabled by the ACPI operating systems with cooperation from the drivers the BIOS has no direct control over the wake up sources when an ACPI operating system is loaded
78. ESR BBE A TA ABS AS MANA Parts R E E He SRK SS ES Pb Hg Cd Cr6 PBB PBDE E Metal Parts ED old 28 fF Printed Board Assemblies PBA o RTRA SURES ARAA PHS BYE SIT 11363 2006 rE ERY PR RAK o Indicates that this hazardous substance contained in all homogeneous materials of this part is below the limit requirement in SJ T 11363 2006 x AURVCBSAEUm SJfuS E S 129 9 H 8 THES BBW SJ T 11363 2006 Er E PATE AY IR EB ESR x Indicates that this hazardous substance contained in at least one of the homogeneous materials of this part is above the limit requirement in SJ T 11363 2006 WHE 2 HB HET m ZR S oa n EI EN e 1 8 Sr m JEDER ER Pri on FA 86 th A ERAS APH A Ph FAY SIE This table shows where these substances may be found in the supply chain of our electronic information products as of the date of sale of the enclosed product Note that some of the component types listed above may or may not be a part of the enclosed product 144 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Regulatory and Certification Information 10 6 China Packaging Recycle Marks or GB18455 2001 Intel EPSD has the following ecological compliances Cardboard and fiberboard packaging will be marked as recyclable in China China Packaging Recycling Marks is required on retail packaging to be marked as recyclable using China s recycling logo Due to regional variances in mark
79. Each occupies a specific area of the screen and has dedicated functionality The following table lists and describes each functional area Table 18 BIOS Setup Page Layout Functional Area Description Title Bar The title bar is located at the top of the screen and displays the title of the form page the user is currently viewing It may also display navigational information Setup Item List The Setup Item List is a set of controllable and informational items Each item in the list occupies the left column of the screen A Setup Item may also open a new window with more options for that functionality on the board Item Specific Help Area The Item Specific Help area is located on the right side of the screen and contains help text for the highlighted Setup Item Help information may include the meaning and usage of the item allowable values effects of the options and so forth Keyboard Command Bar The Keyboard Command Bar is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys 5 3 1 2 Entering BIOS Setup To enter the BIOS Setup press the F2 function key during boot time when the OEM or Intel logo displays The following message displays on the diagnostics screen and under the Quiet Boot logo screen Press F2 to enter setup When the Setup is entered the Main screen displays However serious errors cause the system to display the Erro
80. IGHT ZONE 9 ULL 3 S SES HEATSINK BASE AREA MAX COMPONENT HEIGHT 0 0394 H QQ N an LA A A MAX COMPONENT HEIGHT Q 100 FOR SAS MODULE 22 SS NAX COMPONENT HEIGHT Q 1 FOR N S TAS ARS K Re G Lei Pa 7 M SS SN INS N amp 7 My BU YY 27 d A A 4x 205 NO COMPONENT TONE FOR ADD ON CARD RETENTION MAX COMPONENT HEIGHT 0 137 MAX COMPONENT HEIGHT 0 236 Revision 1 2 Kg A e e RON ZZA LLL LL Sos rr D gt Se EE 9 150 MAX COMPONENT HEIGHT IAX COMPONENT HEIGHT 0 360 FOR SAS MODULE HEATSINK RETENTION MODULE TOUCH AREA NO COMPONENT ZONE 8 PLACES Overview 2 1 0 158 MEMORY VR HEATSINK PUSH PIN KEEPOUT AREA NO COMPONENT ALLOWED 2 PLACES 450 400 GROUND PADS 10 PLACES 110 16 Wi D d i PIN THRU HOLE COMPONENT ZONE 10 PLACES 16 51 SOCKET ILN KEEP IN AREA NO COMPONENT 2 PLACES PU HEATSINK AREA 0 118 3MM MAX COMPONENT HEIGHT RESTRICTION 4 PLACES SOCKET CAVITY 0 070 1 8MM MAX COMPONENT HEIGHT RESTRICTION 2 PLACES 0 276 INM MAX COMPONENT HEIGHT RESTRICTION 2 PLACES PU VR HEATSINK LANDING FEET NO COMPONENT 2 PLACES PU VR HEATSINK 0 033 MAX COMPONENT HEIGHT RESTRICTION 2 PLACES 0 236 CPU ILM MOUNTING HOLE BOARD ROUNTING KEEP OUT ZONE COPPER PAD ON SURFACE 4X2 B PLACES E CPU HEATSING MOUTNIGN HOLE BOARD ROUNTING KEEP QUT ZONE 4X2 8 PLACES Figure 7 Primary
81. IMM configuration with identical DIMMs at A1 A2 B1 B2 C1 and C2 The Intel RMM3 connector is not compatible with the Intel Remote Management Module Product Code AXXRMM or the Intel Remote Management Module 2 Product Code AXXRMM2 Normal BMC functionality is disabled with the Force BMC Update jumper J1H1 set to the enabled position pins 2 3 You should never run the server with the Force BMC Update jumper set in this position and should only use the jumper in this position when the standard BMC firmware update process fails This jumper must remain in the default disabled position pins 1 2 when the server is running normally This server board no longer supports the Rolling BIOS two BIOS banks It implements the BIOS Recovery mechanism instead When performing a normal BIOS update procedure you must set the BIOS Recovery jumper J1E5 to its default position pins 1 2 Locate the device that generates System Event Log SEL PCI device event the SEL PCI device event may not specify which PCI device in the system that generates the event entry users can follow below tips to locate the PCI device s Step1 Identify the PCI device location number the SEL event entry in Hex code see the SEL viewer utility help text instruction for read of Hex code provides the PCI device bus number device number and function number with last two bytes ED2 and ED3 The byte of ED2 provides the PCI device bus number the higher
82. ION 0 250 MAX 5 PLACES o CARD SIDE COMPONENT HEIGHT LIMIT 0 500 MAX Oo Figure 10 Primary Side Card Side Keep out Zone 14 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Overview 450 400 GROUND PADS 10 PLACES 10 16 SOCKEY CAVITY 1 8MM COMPONENT HEIGHT RESTRICTION 2 PLACES 1 8MM COMPONENT HEIGHT RESTRICTION 2 PLACES O PU HEATSINK BACKPLAT E MOUNTING AERA NO COMPONENT IONE 2 PLACES 2 000 TYP OTHER BOARD MOUNTING KEEPOUT AREA NO COMPONENT ZONE 10 PLACES BASEBOARD MOUNTING RESTRICTED AREA H H LIMITED COMPONENT HE IG 0 058 MAX 10 PLACES o 1 000 TYP 25 40 H BASEBOARD MOUNTING KEEPOUT AREA NO COMPONENT ZONE 10 PLACES o UN SN 20 512 gd wa PAD LOCATION 13 001 NO COMPONENT ZONE 5 PLACES 0 236 MOUNTING HOLE AREA 6 00 NO COMPONENT NO ROUTING ZONE 16 PLACES Figure 11 Second Side Keep out Zone Revision 1 2 15 Intel order number E39529 009 Overview Intel amp Server Boards S5520HC and S5500HCV TPS 2 1 3 Server Board Rear UO Layout The following drawing shows the layout of the rear I O components for the server boards O gHO Q
83. If both CPU sockets are populated but Channels A through C are empty the platform can still function with remote memory in Channels D through F However platform performance suffers latency due to remote memory 5 Must always start populating DDR3 DIMMs in the first slot on each memory channel Memory slot A1 B1 C1 D1 E1 or F1 For example if memory slot A1 is empty slot A2 is not available 6 Must always populate the Quad Rank DIMM starting with the first slot Memory slot A1 B1 C1 D1 E1 or F1 on each memory channel For example when installing one Quad Rank RDIMM with one Single or Dual Rank RDIMM in memory channel A you must populate the Quad Rank RDIMM in slot A1 7 Ifan installed DDR3 DIMM has faulty or incompatible SPD data it is ignored during memory initialization and is essentially disabled by the BIOS If a DDR3 DIMM has no or missing SPD information the slot in which it is placed is treated as empty by the BIOS 8 The memory operational mode is configurable at the channel level The following two modes are supported Independent Channel Mode and Mirrored Channel Mode 9 The BIOS selects the mode that enables all the installed memory by default Since the Independent Channel Mode enables all the channels simultaneously this mode becomes the default mode of operation 10 When only CPU1 socket is populated Mirrored Channel mode is selected only if the DIMMs are populated to conform to that channel RAS mod
84. Intel Server Chassis SC5600LX PMBus compliant Power Supply The PCI Express Gen 1 slot x8 Mechanically x4 Electrically is not available when the SAS module slot is in use and vice versa 4 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Overview Server Board Layout Figure 2 Intel Server Board S5500HCV 2 1 1 Server Board Connector and Component Layout The following figure shows the layout of the server board Each connector and major component is identified by a number or letter and a description is given below the figure Revision 1 2 5 Intel order number E39529 009 Overview Intel Server Boards S5520HC and S5500HCV TPS ABCDE F G H J K I Jmm o0 0009 99 L O 4 Po S DO N aa d 8 D ul d all m o Oo PP OI OO Q NN gei MM F Oo LL H d ICH10R KK H JJ F Il HH d CCF el e o FF E EE SPE DD NI IOH fri is mi Le BB S S r HESS AA Sisi Ei ea tu feli e SE al fal Hb al I8 RH s 12 Do DIR W CPU 2
85. Intel Server Boards S5520HC and S5500HCV Technical Product Specification intel X E SERVER BOARD inside Intel order number E39529 009 Revision 1 2 July 2009 Enterprise Platforms and Services Division Revision History Intel Server Boards S5520HC and S5500HCV TPS Revision History Revision Modifications Number February 2008 Preliminary Draft March 2008 Content Update March 2008 Updated sections 2 1 and 3 2 April 2008 Updated product code and processor support related information August 2008 Updated product code and memory support related information S5500HCV DIMM slot population change and Chassis Intrusion header location change September 2008 Jumper block location change February 2009 1 0 Updated Block Diagram Updated Functional Architecture Section added BIOS Setup Utility Section and updated Appendix 1 1 Updated Section 3 3 4 1 Memory Reservation for Memory mapped Functions Updated Section 3 4 1 2 onboard SATA Storage Mode Matrix table Added Fan Domain Table in Section 4 3 2 2 1 Updated Section 9 2 MTBF Added Appendix G Installation Guidelines Added Processor Stepping Mismatching on Table 2 Updated Boot Option BIOS Setup Menu Table 34 and Figure 36 Updated Table 4 Memory Running Frequency Updated Table 12 Intel amp SAS Entry RAID Module AXX4SASMOD Storage Mode Updated Table 47 and Table 48 CPU 1 and CPU2 power connectors pin out Updated Table 84 POST Codes and Messages Updated Table 87 BM
86. L H 8 950 ji 221 331 i i 9 395 1 450 1496 CPU SOCKET ILM MOUNTING HOLE 4X2 8 PLACES 1238 63 i 13 801 9 945 2 x BO 1180 HOLE FOR 1 H 252 601 3 00 10 145 MEMORY VR HEATSINK i 1 251 68 PUSH PIN RETENTION 0 789 10 150 Ge t LB ee ee aen D 11 310 M 282 44 287 271 m T 11 331 REN Q0 1180 2 PLACES 12 300 m e 3 001 312 42 CPU D MEATSIMK MOUNTING HOLES 12 443 L4 320 04 3i6 051 S an Sot ae me 8 3 osa gh Ss Sei Sei Zei X Be Sa Sg Ze fens Ss on WH Le Lo ee en om oo ven Lan ag 2 we ee ae le e a at exes f Figure 4 Mounting Hole Locations 8 Revision 1 2 Intel order number E39529 009 Overview Intel Server Boards S5520HC and S5500HCV TPS 01992 006701 09 3 2 IR 8 312 88 oi rt 02 DER 18 68 Sir 1 te 7011 019 61 ivi KIK 196901 ne Ir ag Hurt 2 99 EN 00 37 gi 83 s2 11971 26 1 eo RU 0000 6 445 163 70 SFY pene dentem o gt o 0 000 1 225 31 12 174 63 6 875 t8 292 Sel Il L9 2121 SEL 0I i 2921 See Ol WER S r 9 Figure 5 Major Connector Pin 1 Locations 1 of 2 Intel order number E39529 009 ision 1 2 Rev Overview Intel amp Server Boards S5520HC and S5500HCV TPS mo om m o 2 59 52 E wom or wh or m oo v EECH w SS we See o e Ten San vm Du we gt e e e e u voe pen codi
87. M Redirection The advanced management features include support for keyboard video and mouse redirection KVM over LAN This feature is available remotely from the embedded web server as a Java applet The client system must have a Java Runtime Environment JRE Version 1 6 JRE6 or later to run the KVM or media redirection applets You can download the latest Java Runtime Environment JRE update http java com en download index jsp This feature is only enabled when the Intel RMM3 is present Note KVM Redirection is only available with onboard video controller and the onboard video controller must be enabled and used as the primary video output Note The BIOS will detect one set of USB keyboard and mouse for the KVM redirection function of Inte RMM3 even if no presence of RMM3 is detected Users will see one set of USB keyboard and mouse in addition to the local USB connection on the BIOS Setup USB screen with or without RMMSG installed 4 2 2 1 Keyboard and Mouse The keyboard and mouse are emulated by the BMC as USB human interface devices 4 2 2 2 Video Video output from the KVM subsystem is equivalent to video output on the local console via onboard video controller Video redirection is available once video is initialized by the system BIOS The KVM video resolutions and refresh rates will always match the values set in the operating system 4 2 2 3 Availability Up to two remote KVM sessions are supported An error displa
88. New Zealand Korea China China Exporting Requirements Regulatory Identification Marking C CANADA ICES 003 CLASS A CANADA NMB 003 CLASSE A igiEFRARBUEUESS TEER te BBS STRESS TERRENT ERAS RE KARA SAR FH WAAR in Z VAP dn ur B 3X TH EF ERAN AD 47 B T8306 e Made in Xxxxx Examples Server Board S5520HC for boxed type boards or Board PB number for non boxed boards typically high end boards 10 3 Electromagnetic Compatibility Notices FCC USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation For questions related to the EMC performance of this product contact Revision 1 2 139 Intel order number E39529 009 Regulatory and Certification Information Intel Server Board S5520HC S5500HCV TPS Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 6497 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with th
89. PS 9 4 9 Residual Voltage Immunity in Stand by Mode The power supply should be immune to any residual voltage placed on its outputs typically a leakage voltage through the system from stand by output up to 500 mV There should be no additional heat generated or stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously It also should not trip the power supply protection circuits during turn on Residual voltage at the power supply outputs for a no load condition should not exceed 100 mV when AC voltage is applied and the PSON signal is de asserted 136 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Regulatory and Certification Information 10 Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations before computer integration make sure that the chassis power supply and other modules have passed EMC testing using a server board with a microprocessor from the same family or higher and operating at the same or higher speed as the microprocessor used on this server board The final configuration of your end system product may require additional EMC compliance testing For more information please contact your local Intel Representative This is an FCC Class A device Integration of it into a Class B chassis does not result in a Class B device 10 1 Product Regulatory Com
90. Ports f Video ISO F Conn Integrated BMC GFX DDC 33v sTBY GFX DOC Ke sv xao Figure 21 SMBUS Block Diagram 66 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 BIOS Setup Utility 5 1 Logo Diagnostic Screen The Logo Diagnostic Screen displays in one of two forms f Quiet Boot is enabled in the BIOS setup a logo splash screen is displayed By default Quiet Boot is enabled in the BIOS setup If the logo displays during POST press Esc to hide the logo and display the diagnostic screen fa logo is not present in the flash ROM or if Quiet Boot is disabled in the system configuration the summary and diagnostic screen is displayed The diagnostic screen displays the following information BIOS ID Platform name Total memory detected Total size of all installed DDR3 DIMMs Processor information Intel branded string speed and number of physical processors identified Keyboards detected if plugged in Mouse devices detected if plugged in 5 2 BIOS Boot Popup Menu The BIOS Boot Specification BBS provides for a Boot Popup Menu invoked by pressing the lt F6 gt key during POST The BBS popup menu displays all available boot devices The list order in the popup menu is not the same as the boot order in the BIOS setup it simply lists all the bootable devices from which the system can be booted When a User Password or A
91. Q GNT pairs ACPI Power Management Logic Support Revision 3 0a Enhanced DMA controller interrupt controller and timer functions Integrated Serial ATA host controllers with independent DMA operation on up to six ports and AHCI support USB host interface with support for up to 12 USB ports six UHCI host controllers and two EHCI high speed USB 2 0 host controllers Integrated 10 100 1000 Gigabit Ethernet MAC with System Defense System Management Bus SMBus Specification Version 2 0 with additional support for l C devices Low Pin Count LPC interface support Firmware Hub FWH interface support Serial Peripheral Interface SPI support 3 4 1 Serial ATA Support The ICH10R has an integrated Serial ATA SATA controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3 0 Gb s The six SATA ports on the server boards are numbered SATA 0 through SATA 5 You can enable disable the SATA ports and or configure them by accessing the BIOS Setup utility during POST 3 4 1 1 Intel Embedded Server RAID Technology II Support The Intel Embedded Server RAID Technology Il Intel ESRTII feature provides RAID modes 0 1 and 10 If RAID 5 is needed with Intel ESRTII you must install the optional Intel RAID Activation Key AXXRAKSWS accessory You must place this activation key on the SATA Software RAID 5 connector located on the Intel Server Boards S5520HC and S5500HCV For
92. QuickPath DDR3 Xeon VO 2 DIMMs per Channel DIMMs per Channel HIE Ed TENTE Slot L Slot 5 Slot 4 Slot 3 5520 IOH Default switch to slot2 SAS Module Slot 5 SATA II x6 w SB x Pi ES Slot1 SS ICH10R OEE RMM3 Slot USB x1 eee SB DVO Floppy USB x2 conn us x Front Panel USB x2 conn A type USB x1 Figure 13 Intel Server Board S5520HC Functional Block Diagram 18 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture i 9 ie d DDR3 DDR3 mam intel Tintel mem QuickPath DDR3 DDR3 Xeon Xeon B inside J Ge 2 DIMMs per Channel CPUZ 1 DIMM per Channel TEE yedin Slot 6 x16 conn mm min 82575EB X2 Gbit MO gt GE sid SAS Module Slot M SATA TI P fA Default switch to slot2 Siot2 Ee hy SP D Slot 1 SSS ICH 10R USB x2 Slot 4 Slot 3 SB x RMM3 Slot LP intemal Serial Conn Serial A USB x1 u eS Sen a t DVD Floppy USB x2 conn A type USB x1 J SPI DOR2 sfo EE o TEE sfs Front Panel USB x2 conn enm Figure 14 Intel Server Board S5500HCV Functional Block Diagram Revision 1 2 19 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 1 Intel 5520 and 5500 UO Hub IOH The Intel 5520 and 5500 I O Hub IOH in the Intel Server Boards S5520HC and S5500HCV provide a connection
93. R CODE SEVERITY INSTANCE Figure 45 Setup Utility Error Manager Screen Display Table 43 Setup Utility Error Manager Screen Fields Setupltem 1 Options Help Text Displays System Errors Information only Displays errors that occurred during POST 102 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 9 Exit Screen The Exit screen allows the user to choose whether to save or discard the configuration changes made on the other screens It also allows the user to restore the server to the factory defaults or to save or restore them to the set of user defined default values If Load Default Values is selected the factory default settings noted in bold in the tables in this chapter are applied If Load User Default Values is selected the system is restored to previously saved user defined default values Error Manager Exit Save Changes and Exit Discard Changes and Exit Save Changes Discard Changes Load Default Values Save as User Default Values Load User Default Values Figure 46 Setup Utility Exit Screen Display Table 44 Setup Utility Exit Screen Fields Setupitem Help Text Save Changes and Exit Exit the BIOS Setup utility after saving changes User prompted for confirmation only if The system reboots if required any of the setup fields were modified The F10 key can also be used Discard Changes and Exit the
94. RR Enabled On PERR generate an NMI and log an error Disabled Note This option is only active if the Assert NMI on SERR option is Enabled selected Resume on AC Power Stay Off System action to take on AC power loss recovery Loss Last state Stay Off System stays off Reset Last State System returns to the same state before the AC power loss Reset System powers on Clear System Event Enabled If enabled clears the System Event Log All current Log Disabled entries will be lost Note This option is reset to Disabled after a reboot FRB 2 Enable Enabled Fault Resilient Boot FRB Disabled If enabled the BIOS programs the BMC watchdog timer for approximately 6 minutes If the BIOS does not complete POST before the timer expires the BMC resets the system O S Boot Watchdog Enabled If enabled the BIOS programs the watchdog timer Timer Disabled with the timeout value selected If the OS does not complete booting before the timer expires the BMC resets the system and an error is logged Requires OS support or Intel Management Software O S Boot Watchdog Power Off If the OS boot watchdog timer is enabled this is the Grayed out when O S Boot Timer Policy Reset system action taken if the watchdog timer expires Watchdog Timer is Reset System performs a reset disabled Power Off System powers off O S Boot Watchdog 5 minutes If the OS watchdog timer is enabled this is the Grayed out when O S Bo
95. S5500HCV TPS Byissuing the appropriate hex IPMI Chassis Identify value the ID LED will either blink nlue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issue to turn it off The bi color green amber System Status LED operates as follows Table 69 System Status LED Color State Criicaity System OK System booted and ready System degraded Non critical temperature threshold asserted Non critical voltage threshold asserted Non critical fan threshold asserted Fan redundancy lost sufficient system cooling maintained This does not apply to non redundant systems Green Blink Degraded Power supply predictive failure Power supply redundancy lost This does not apply to non redundant systems Correctable errors over a threshold of 10 and migrating to a mirrored DIMM memory mirroring This indicates the user no longer has spare DIMMs indicating a redundancy lost condition The corresponding DIMM LED should light up Non fatal alarm system is likely to fail Critical temperature threshold asserted CATERR asserted Critical voltage threshold asserted VRD hot asserted SMI Timeout asserted Amber Blink Non critical Fatal alarm system has failed or shut down CPU Missing Thermal Trip asserted Non recoverable temperature threshold asserted Non recoverable voltage threshold asserted Critical Power fau
96. S5500HCV TPS Regulatory and Certification Information ICES 003 Canada Cet appareil num rique respecte les limites bruits radio lectriques applicables aux appareils num riques de Classe A prescrites dans lanorme sur le mat riel brouilleur Apparelis Num riques NMB 003 dictee par le Ministre Canadian des Communications English translation of the notice above This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications Europe CE Declaration of Conformity This product has been tested in accordance too and complies with the Low Voltage Directive 73 23 EEC and EMC Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance VCCI Japan CORBIS PHUBERSERREAERHBMS VCC 04 CBO VIABIFRRARECT OXBIZ TRERIS C EIH d AIE BHicUCoETEXZ CO0 amp KBP 2LZTOTULULZaLzSMBSUCYHELTC Sait BRB SRCTCEPHVETF BIRR AAS ICH CIEL URMYRUELT RS English translation of the notice above This is a Class B product based on the standard of the Voluntary Control Council for Interference VCCI from Information Technology Equipment If this is used near a radio or television receiver in a domestic environment it may cause radio interference Install and use the equipment according to the instruction manual BSMI Taiwan
97. UT 107 Power Supply Auxiliary Signal Connector Pin out GIOR2 107 Intel RMM3 Connector Pin out LUC 108 LCP IPMB Header Pin out U1G6 eee 108 HSBP Header Pin out J1F5 JiG3t ennenen 109 SGPIO Header Pin out J1G2 sssssssssssessesseeeenee eene nennen 109 Front Panel SSI Standard 24 pin Connector Pin out B 109 VGA Connector Pin out UAT ennemis 110 RJ 45 10 100 1000 NIC Connector Pin out J5A1 J6A1 sesesesssssssss 110 SATA SAS Connector Pin out J1E3 J1G1 J1G4 J1G5 J1F1 J1F4 112 SAS Module Slot Pin out U3In1t nennen ene nenes 112 External DB9 Serial A Port Pin out LAT 113 Internal 9 pin Serial B Header Pin out LU71B7 113 External USB Connector Pin out J5A1 Jean 114 Internal USB Connector Pin out GI1Di1 114 Internal USB Connector Pin out GI1D32 114 Pin out of Internal Low Profile USB Connector for Solid State Drive J2D2 115 Internal Type A USB Port Pin out UH 115 SSI 4 pin Fan Header Pin out J7K1 J9A2 JOAN 115 SSI 6 pin Fan Header Pin out J1K1 J1K2 J1K4 JK 116 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS List of Tables Table 68 Server Board Jumpers J1E6 J1E2 J1E4 JOER JH 117 Table 69 System Status LED 124 Table 70 Server Board Design Specifications ssssssssssssssseeeeeeee 127 Table T MTBE Estiriate ice ee t ede d ree e eig en 128 Table 7
98. al performance and efficiency and no RAS is enabled Mirror Mode System memory is configured for maximum reliability in the form of memory mirroring Information only Displays the speed the memory is running at Select to configure the memory RAS and performance This takes the user to a different screen Displays the state of each DIMM socket present on the board Each DIMM socket field reflects one of the following possible states Installed There is a DDR3 DIMM installed in this slot Not Installed There is no DDR3 DIMM installed in this slot Disabled The DDR3 DIMM installed in this slot was disabled by the BIOS to optimize memory configuration Failed The DDR3 DIMM installed in this slot is faulty malfunctioning Note X denotes the Channel Identifier and Y denote the DIMM Identifier within the Channel Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 8 2 2 2 1 Configure Memory RAS and Performance Screen The Configure Memory RAS and Performance screen allows the user to customize several memory configuration options such as whether to use Memory Mirroring To access this screen from the Main screen select Advanced Memory Configure Memory RAS and Performance Advanced Memory RAS and Performance Configuration Capabilities Memory Mirroring Possible Yes No Select Memory RAS Configuration Maximum Performan
99. apped PCI Express functions including a standard 64 MB or 256 MB of standard PCI Express MMIO configuration space This is based on the setup selection Maximize Memory below 4GB If this is set to Enabled the BIOS maximizes usage of memory below 4 GB for an operating system without PAE capability by limiting PCI Express Extended Configuration Space to 64 buses rather than the standard 256 buses 3 3 4 2 High Memory Reclaim When 4 GB or more of physical memory is installed physical memory is the memory installed as DDR3 DIMMs the reserved memory is lost However the Intel 5500 5520 I O Hub provides a feature called high memory reclaim which allows the BIOS and the operating system to remap the lost physical memory into system memory above 4 GB the system memory is the memory the processor can see The BIOS always enables high memory reclaim if it discovers installed physical memory equal to or greater than 4 GB For the operating system you can recover the reclaimed memory only if the PAE feature in the processor is supported and enabled Most operating systems support this feature For details see your operating system s relevant manuals 3 3 5 Memory Interleaving The Intel Xeon Processor 5500 Series supports the following memory interleaving mode 32 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture Banklnterleaving Interleave cache line da
100. ata is the data included in an event message generated by the sensor For threshold based sensors the following abbreviations are used R Reading value T Threshold value Revision 1 2 151 Intel order number E39529 009 Appendix C BMC Sensor Tables 152 Intel amp Server Board S5520HC S5500HCV TPS Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states You can rearm the sensors manually or automatically This column indicates the type supported by the sensor These abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm Rearm by init agent Default Hysteresis The hysteresis setting applies to all thresholds of the sensor This column provides the count of hysteresis for the sensor which is 1 or 2 positive or negative hysteresis Criticality Criticality is a classification of the severity and nature of the condition It also controls the behavior of the Control Panel Status LED Standby Some sensors operate on standby power You can access these sensors and or generate events when the main system power is off but AC power is present Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Appendix C BMC Sensor Tables Table 81 Integrated BMC Core Sensors Readabl Full Sensor Name Sensor Platform Event Event Offset Contri
101. ation detailing the features functionality and high level architecture of the Intel Server Boards S5520HC and S5500HCV In addition you can obtain design level information for a given subsystem by ordering the External Product Specifications EPS for the specific subsystem EPS documents are not publicly available and you must order them through your local Intel representative 1 1 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Overview Chapter 3 Functional Architecture Chapter 4 Platform Management Chapter 5 BIOS Setup Utility Chapter 6 Connector Header Locations and Pin outs Chapter 7 Jumper Blocks Chapter 8 Intel Light Guided Diagnostics Chapter 9 Design and Environmental Specifications Chapter 10 Regulatory and Certification Information Appendix A Integration and Usage Tips Appendix B Compatible Intel Server Chassis Appendix C BMC Sensor Tables Appendix D Platform Specific BMC Appendix Appendix E POST Code Diagnostic LED Decoder Appendix F POST Error Messages and Handling Appendix G Installation Guidelines Glossary Reference Documents 1 2 Server Board Use Disclaimer Intel Server Boards contain a number of high density VLSI Very large scale integration and power delivery components that require adequate airflow for cooling Intel ensures through its ow
102. ault is enabled The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors The SMBIOS Type 4 structure shows only the installed physical processors It does not describe the virtual processors Because some operating systems are not able to efficiently use the Intel HT Technology the BIOS does not create entries in the Multi Processor Specification Version 1 4 tables to describe the virtual processors 3 2 4 Enhanced Intel SpeedStep Technology EIST If the installed processor supports the Enhanced Intel SpeedStep Technology the BIOS Setup provides an option to enable or disable this feature The Default is enabled 3 2 5 Intel Turbo Boost Technology Intel Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency if the part is operating below power temperature and current limits If the processor supports this feature the BIOS setup provides an option to enable or disable this feature The default is enabled 3 2 6 Execute Disable Bit Feature The Execute Disable Bit feature XD bit can prevent data pages from being used by malicious software to execute code A processor with the XD bit feature can provide memory protection in one of the following modes e Legacy protected mode if Physical Address Extension PAE is enabled e Intel 64 mode when 64 bit extension technology is enabled Entering Intel 64 mode requires enabl
103. b To EES rg Event Stand i Applicabilit Sensor Type Reading T caers System De Rearm b Sensor name in SDR PP y Type gg Status assert hin Data y sets 00 Power down S 04 A C lost ensor re gier Power Unit Status Power Unit Specific 05 Soft power Pwr Unit Status 09h control failure Fatal 06 Power unit failure Power Unit Redundancy1 Chassis Power Unit Generic 00 Fully ime pes As SE Pwr Unit Redund specific 09h OBh Redundant 01 Redundancy Degraded lost 02 Redundancy degraded Degraded Trig Offset Trig Offset Revision 1 2 153 Intel order number E39529 009 03 Non redundant sufficient resources Degraded Transition from full redundant state 04 Non redundant sufficient resources Transition from insufficient state Degraded 05 Non redundant insufficient resources Appendix C BMC Sensor Tables Intel Server Board S5520HC S5500HCV TPS Readabl Contrib To Assert e System De Status assert Value Full Sensor Name Platform Event Offset Applicability 06 Redundant degraded from fully redundant state 07 Redundant Transition from non redundant state 00 Timer expired status only IPMI Watchdog SE 2 cad 01 Hard reset IPMI Watchdog Ben 02 Power down 03 Power cycle 08 Timer interrupt Sensor Type Reading Sensor name in SDR Triggers 00 Chassis Security Specific IRI Trig Offset Physical Sc
104. ce The BIOS Setup utility provides options on Advanced PCI Configuration Screen to configure the feature as follows Onboard Video Dual Monitor Video 52 Enabled default Disabled Enabled Shaded if onboard video is set to Disabled Disabled Default Intel order number E39529 009 Revision 1 2 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture 3 12 Network Interface Controller NIC The Intel Server Boards S5520HC and S5500HCV provide dual onboard LAN ports with support for 10 100 1000 Mbps operation The two LAN ports are based on the onboard Intel 82575EB controller which is a single compact component with two fully integrated GbE Media Access Control MAC and Physical Layer PHY ports The Intel 82575EB controller provides a standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASE TX and 10BASE T applications 802 3 802 3u and 802 3ab and is capable of transmitting and receiving data at rates of 1000 Mbps 100 Mbps or 10 Mbps Each network interface controller NIC port provides two LEDs Link activity LED at the left of the connector Indicates network connection when on and transmit receive activity when blinking The speed LED at the right of the connector indicates 1000 Mbps operation when amber 100 Mbps operation when green and 10 Mbps when off The following table provides an overview of the LEDs Table 15 Onboard NIC Status L
105. ce Mirroring NUMA Optimized Disabled Enabled Figure 26 Setup Utility Configure RAS and Performance Screen Display Table 24 Setup Utility Configure RAS and Performance Screen Fields ene Mirroring Yes No Information only Only displayed Possible on systems with chipsets capable of Memory Mirroring Select Memory Maximum Available modes depend on the current Only available if Mirroring is RAS Configuration Performance memory population possible Mirroring Maximum Performance Optimizes system performance Mirroring Optimizes reliability by using half of physical memory as a backup NUMA Optimized Enabled If enabled BIOS includes ACPI tables Disabled that are required for NUMA aware Operating Systems Revision 1 2 79 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS 5 3 2 2 3 Mass Storage Controller Screen The Mass Storage screen allows the user to configure the SATA SAS controller when it is present on the baseboard module card of an Intel system To access this screen from the Main menu select Advanced Mass Storage Figure 27 Setup Utility Mass Storage Controller Configuration Screen Display 80 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 25 Setup Utility Mass Storage Controller Configuration Screen Fields Help Text Entry SAS R
106. creen Display 91 Setup Utility Server Management System Information Screen Display 93 Setup Utility Boot Options Screen Display 94 Setup Utility Add New Boot Option Screen Display 96 Setup Utility Delete Boot Option Screen Display ssseseeeeeeeeeeeeeee 97 Setup Utility Hard Disk Order Screen Display 98 Setup Utility CDROM Order Screen Display sesssssse 98 Setup Utility Floppy Order Screen Display 99 Setup Utility Network Device Order Screen Display 100 Setup Utility BEV Device Order Screen Display 100 Setup Utility Boot Manager Screen Display 101 Setup Utility Error Manager Screen Display 102 Setup Utility Exit Screen Display 103 Jumper Blocks J1E2 J1E4 J1E5 J1E6 JH 117 5 volt Stand by Status LED Location 121 Fan Fault LED s Location eene nnne nennen 122 System Status LED Location 123 DIMM Fault LED s Location 125 POST Code Diagnostic LED Locations s snsnsneeeeee tetette tee eereetetttttrrrtrrnrnrnenee eee 126 Power Distribution Block Diagramm 129 Output Voltage TIMING KEE 134 Turn On Off Timing Power Supply Gonale ne 135 Active Processor Heatsink Installation Requirement sesssssssssss 150 Diagnostic LED Placement Diagram s esssssesnseserrrrterrrertetertttttetettttrtrtrennnnnn nennen 163 Revision 1 2 Intel order number E39529 009 Intel amp Se
107. d S5500HCV support the following memory channel modes e Independent Channel Mode e Mirrored Channel Mode providing Channel RAS feature These channel modes are used in conjunction with the standard Memory Test Built in Self Test BIST and Memory Scrub engines to provide full RAS support Channel RAS feature are supported only if both CPU sockets are populated and support the right population For more information refer to Section 3 3 9 Revision 1 2 33 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 3 8 2 Independent Channel Mode In the Independent Channel mode you can populate multiple channels on any channel in any order The Independent Channel mode provides less RAS capability but better DIMM isolation in case of errors Moreover it allows the best interleave mode possible and thereby increases performance and thermal characteristics Adjacent slots on a DDR3 Channel from the Intel Xeon Processor 5500 series do not need matching size and organization in independent channel mode However the speed of the channel is configured to the maximum common speed of the DIMMs The Single Channel mode is established using the Independent Channel mode by populating the DIMM slots from Channel A 3 3 8 3 Mirrored Channel Mode The Mirrored Channel mode is a RAS feature in which two identical images of memory channel data are maintained providing maximum redundancy On the Int
108. dministrator Password is active in Setup the password is to access the Boot Popup Menu 5 3 BIOS Setup Utility The BIOS Setup utility is a text based utility that allows the user to configure the system and view current settings and environment information for the platform devices The Setup utility controls the platform s built in devices boot manager and error manager The BIOS Setup interface consists of a number of pages or screens Each page contains information or links to other pages The advanced tab in Setup displays a list of general categories as links These links lead to pages containing a specific category s configuration The following sections describe the look and behavior for platform setup Revision 1 2 67 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS 5 3 1 Operation The BIOS Setup has the following features Localization The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard The Intel server board BIOS is only available in English Console Redirection The BIOS Setup is functional via console redirection over various terminal emulation standards This may limit some functionality for compatibility for example color usage or some keys or key sequences or support of pointing devices 5 3 1 1 Setup Page Layout The setup page layout is sectioned into functional areas
109. ds Setupltem Options Help Text Console Redirection Disabled Console redirection allows a serial port to be used for Serial Port A server management tasks Serial Port B Disabled No console redirection Serial Port A Configure serial port A for console redirection Serial Port B Configure serial port B for console redirection Enabling this option disables the display of the Quiet Boot logo screen during POST Flow Control None Flow control is the handshake protocol RTS CTS Setting must match the remote terminal application None Configure for no flow control RTS CTS Configure for hardware flow control Baud Rate Serial port transmission speed Setting must match m the remote terminal application Terminal Type PC ANSI Character formatting used for console redirection VT100 Setting must match the remote terminal application VT100 VT UTF8 Legacy OS Disabled This option enables legacy OS redirection i e DOS Redirection Enabled on serial port If it is enabled the associated serial port is hidden from the legacy OS 92 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 5 Server Management System Information Screen The Server Management System Information screen allows the user to view part numbers serial numbers and firmware revisions To access this screen from the Main screen select Server Manag
110. e If it fails to comply with the population rule then the BIOS configures the CPU1 socket to default to the Independent Channel mode 11 If both CPU sockets are populated and the installed DIMMs are associated with both CPU sockets then Mirrored Channel Mode can only be selected if both the CPU Sockets are populated to conform to that mode If either or both sockets fail to comply with the population rule the BIOS configures both the CPU sockets to default to the Independent Channel mode 12 DIMM parameters matching requirements for Mirrored Channel Mode is local to the CPU socket For example while CPU1 memory channels A B and C have one match of ae Revision 1 2 35 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 13 14 15 16 17 18 timing technology and size CPU 2 memory channels D E and F can have a different match of the parameters channel RAS still functions The Minimal memory population possible is DIMM A1 In this configuration the system operates in the Independent Channel Mode Mirrored Channel Mode is not possible The minimal population upgrade recommended for enabling CPU 2 socket is DIMM A1 and DIMM D1 This configuration supports only the Independent Channel mode In the Mirrored Channel mode memory population on Channels A and B should be identical including across adjacent slots on the channels memory population on Channels D a
111. e RA eet ro ege ete PET Es 131 9 4 4 Viele IER 132 9 4 5 Dynamic loading te riii en rette et per dee eu etii eo pL et oue cu near Heo 132 9 4 6 Capacitive Loading ssssssssssesessseee eene rerenennnnnnn nnne 133 9 4 7 Ripple NOSE ca ee et et re Reds 133 9 4 8 Timing Requirements ENEE 133 9 4 9 Residual Voltage Immunity in Stand by Mode essseeeesesesseseeererrrrrrrrrnrnrrenesee 136 10 Regulatory and Certification Information ceeeeeeeeeeeeeeeeeeenennnn nnne 137 10 1 Product Regulatory Compliance ssssessssesesesrrrrrrrrestere teret terttrtrtrtrtrrrennnn nenene ne 137 10 1 1 Product Safety Complance nennen 137 10 1 2 Product EMC Compliance Class A Compliance seeseeeeeeeeeeseeeererrrrrren nnns 137 10 1 3 Certifications Registrations Declarations ssssesnseeneneenereenereeeerererernrerrrnen 138 10 2 Product Regulatory Compliance Marking sssssseem 139 10 3 Electromagnetic Compatibility Notices ssssssssseemRRRRRRRR 139 ER EE 139 ei Le Le EE 141 Europe CE Declaration of Contformfbv eene 141 Revsioni 2 Vi Intel order number E39529 009 Table of Contents Intel Server Boards S5520HC and S5500HCV TPS VCCI Japan a tete ere c e oen uaa n e D a i ie eM mE eS 141 SIME VU mS 141 RRE KCC KORG a coii rro oen ieee re naan ore Hb ess e Chee Det ieee E o aee 142 CONO TGCESCnIDS sis tried aote dona oat tae e
112. e device to the server tis possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE IMG and CD ROM or DVD ROM ISO files For more information refer to the Tested supported Operating System List Itis possible to mount at least two devices concurrently The mounted device is visible to and usable by the managed system s operating system and BIOS in both the pre and post boot states The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to boot from this remote device Itis possible to install an operating system on a bare metal server no operating system present using the remotely mounted device This may also require the use of KVM r to configure the operating system during install If either a virtual IDE or virtual floppy device is remotely attached during system boot both virtual IDE and virtual floppy are presented as bootable devices It is not possible to present only a single mounted device type to the system BIOS 4 2 3 1 Availability The default inactivity timeout is 30 minutes and is not user configurable Media redirection sessions persist across system reset but not across an AC power loss 4 2 4 Web Services for Management WS MAN The BMC firmware supports the Web Services for Management WS MAN specification version 1 0 4 2 4 1 Profiles The BMC supports the following DMTF profiles for WS MAN
113. e instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna e Increase the separation between the equipment and the receiver e Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected e Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product Only peripherals computer input output devices terminals printers etc that comply with FCC Class A or B limits may be attached to this computer product Operation with noncompliant peripherals is likely to result in interference to radio and TV reception All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception 140 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC
114. e system then the default boot order is CD DVD ROM Floppy Disk Drive Hard Disk Drive PXE Network Device BEV Boot Entry Vector Device EFI Shell and EFI Boot paths oor amp ON A 5 3 2 6 1 Add New Boot Option Screen The Add Boot Option screen allows the user to remove an EFI boot option from the boot order To access this screen from the Main screen select Boot Options Delete Boot Options Boot Options Add New Boot Option Add boot option label Select File system Available File systems Path for boot option Save Figure 37 Setup Utility Add New Boot Option Screen Display Table 35 Setup Utility Add New Boot Option Fields Setupitem Options Help Text Add boot option label Create the label for the new boot option Select File system Select one from list Select one file system from the list provided Path for boot option Enter the path to boot option in the format path filename efi Save Save the boot option 96 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 6 2 Delete Boot Option Screen The Delete Boot Option screen allows the user to remove an EFI boot option from the boot order Note that while you can delete the Internal EFI Shell in this screen it is restored to the Boot Order on the next reboot You cannot permanently delete the Internal EFI Shell To access this screen from the Main scre
115. e the same then the BIOS Logs the error into the SEL Displays 0197 Processor 0x family is not supported message in the Error Manager Halts the system and will not boot until the fault condition is remedied The BIOS detects the error condition and responds as follows Adjusts all processor QPI frequencies to highest common frequency No error is generated this is not an error condition Continues to boot the system successfully If the link speeds for all QPI links cannot be adjusted to be the same then the BIOS Logs the error into the SEL Displays 0195 Processor 0x Intel QPI speed mismatch message in the Error Manager Halts the system and will not boot until the fault condition is remedied 23 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS Eror Severity System Action Processor microcode Minor The BIOS detects the error condition and responds as follows missing Logs the error into the SEL Does not disable the processor Displays 8180 Processor 0x microcode update not found message in the Error Manager or on the screen The system continues to boot in a degraded state regardless of the setting of POST Error Pause in Setup 3 2 3 Intel Hyper Threading Technology Intel HT If the installed processor supports the Intel Hyper Threading Technology the BIOS Setup provides an option to enable or disable this feature The def
116. ect Serial port A interrupt request IRQ line 4 Serial B Enabled Enable or Disable Serial port B Enable Disabled Address Select Serial port B base I O address Select Serial port B interrupt request IRQ line 4 82 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 2 5 USB Configuration Screen The USB Configuration screen allows the user to configure the USB controller options To access this screen from the Main screen select Advanced USB Configuration Advanced USB Configuration Detected USB Devices USB Controller Enabled Disabled Legacy USB Support Enabled Disabled Auto Port 60 64 Emulation Enabled Disabled Make USB Devices Non Bootable Enabled Disabled USB Mass Storage Device Configuration Device Reset timeout 10 seconds 20 seconds 30 seconds 40 seconds Mass Storage Devices Auto Floppy Forced FDD Hard Disk CD ROM USB 2 0 controller Enabled Disabled Figure 29 Setup Utility USB Controller Configuration Screen Display Revision 1 2 83 Intel order number E39529 009 BIOS Setup Utility Detected USB Devices USB Controller Legacy USB Support Port 60 64 Emulation Make USB Devices Non Bootable Device Reset timeout One line for each mass storage device in system USB 2 0 controller 84 Intel amp Server Board S5520HC S5500HCV TPS Table 27 Setup Utility USB Controller Con
117. ed 9 4 3 Remote Sense The power supply should have remote sense return ReturnS to regulate out ground drops for all output voltages 3 3 V 5 V 12 V1 12 V2 12 V3 12 V4 12 V and 5 VSB The power supply should use remote sense to regulate out drops in the system for the 3 3 V 5 V and 12 V1 outputs The 12 V1 12 V2 12 V3 12 V4 12 V and 5V SB outputs only use remote sense referenced to the ReturnS signal The remote sense input impedance to the power supply must be greater than 200 O on 3 3 VS and 5 VS This is the value of the resistor connecting the remote sense to the output voltage internal to the power supply Remote sense must be able to regulate out a minimum of 200 mV drop The remote sense return ReturnS must be able to regulate out a minimum of 20 Om drop in the power ground return The current in any remote sense line should be less than 5 mA to prevent voltage sensing errors The power supply must operate within specification over the full range of voltage drops from the power supply s output connector to the remote sense points Revision 1 2 131 Intel order number E39529 009 Design and Environmental Specifications Intel Server Board S5520HC S5500HCV TPS 9 4 4 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise All outputs are measur
118. ed with reference to the return remote sense signal ReturnS The 12 V3 12 V4 12 V and 5 VSB outputs are measured at the power supply connectors referenced to ReturnS The 3 3 V 5 V 12 V1 and 12 V2 are measured at its remote sense signal located at the signal connector Table 74 Voltage Regulation Limits Parameter Tolerance Minimum Nominal Maximum Units 3 3 V 5 5 3 14V 3 30V 3 46V Vms 5 V 5 5 44 75V 5 00V 5 25V Vms 12 V1 5 5 11 40V 12 00V 12 60V Vms 12 V2 5 5 11 40V 12 00V 12 60V Vms 12 V3 5 5 11 40V 12 00V 12 60V Vms 12 V4 5 5 11 40V 12 00V 12 60V Vms 12V 5 9 11 40V 12 00V 13 08V Vms 5 VSB 5 5 4 75V 5 00V 5 25V Vims 9 4 5 Dynamic Loading The output voltages remain within limits for the step loading and capacitive loading specified in the following table You should test the load transient repetition rate between 50 Hz and 5 kHz at duty cycles ranging from 10 to 90 The load transient repetition rate is only a test specification The A step load may occur anywhere within the minimum load to the maximum load range Table 75 Transient Load Requirements Output A Step Load Size 1 Load Slew Rate Test Capacitive Load 3 3 V TOA 0 25A usec 4700uF 5V TOA 0 25A usec 1000uF 12V 25A 0 25A usec 4700uF 5VSB 0 5A 0 25A usec 20uF 1 Step loads on each 12 V output may happen simultaneously 132 Revision 1 2 Intel o
119. el Xeon Processor 5500 series based Intel server boards the mirroring is achieved across channels Active channels hold the primary image and the other channels hold the secondary image of the system memory The integrated memory controller in the Intel Xeon Processor 5500 series alternates between both channels for read transactions Write transactions are issued to both channels under normal circumstances The mirrored image is a redundant copy of the primary image therefore the system can continue to operate despite the presence of sporadic uncorrectable errors resulting in 10096 data recovery In Mirrored Channel mode channel A or D and channel B or E function as the mirrors while Channel C or F is unused The effective system memory is reduced by at least one half For example if the system is operating in the Mirrored Channel mode and the total size of the DDR3 DIMMs is 2 GB then the effective memory size is 1 GB because half of the DDR3 DIMMs are the secondary images If Channel C or F is populated the BIOS will disable the Mirrored Channel mode This is because the BIOS always gives preference to the maximization of memory capacity over memory RAS because RAS is an enhanced feature The BIOS provides a setup option to enable mirroring if the current DIMM population is valid for the Mirrored Channel mode of operation When memory mirroring is enabled the BIOS attempts to configure the memory system accordingly If the BIOS
120. ement System Information Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number Asset Tag BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 35 Setup Utility Server Management System Information Screen Display Table 33 Setup Utility Server Management System Information Fields Seuplem Commets HSC Firmware Revision Information only If there is no HSC installed the Firmware Revision Number will appear as 0 00 ME Firmware Revision Information only SDR Revision Information only UUID Information only Revision 1 2 93 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS 5 3 2 6 Boot Options Screen The Boot Options screen displays any bootable media encountered during POST and allows the user to configure the desired boot device To access this screen from the Main screen select Boot Options Main Advanced Security Server Management Boot Options Boot Manager System Boot Timeout Boot Option 1 Boot Option 2 Boot Option x Hard Disk Order CDROM Order Floppy Order Network Device Order BEV Device Order Add New Boot Option gt Delete Boot Option EFI Optimized Boot Enabled Disabled Use Legacy Video for EFI OS Enabled Disabled Boot Option Retry Enabled Disabled USB B
121. en select Boot Options gt Delete Boot Options Boot Options Delete Boot Option Delete Boot Option Select one to Delete Internal EFI Shell Figure 38 Setup Utility Delete Boot Option Screen Display Table 36 Setup Utility Delete Boot Option Fields Delete Boot Option Select one to Delete Remove an EFI boot option from the If the EFI shell is deleted Internal EFI Shell boot order it is restored on the next system reboot It cannot be permanently deleted Revision 1 2 97 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS 5 3 2 6 3 Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks To access this screen from the Main screen select Boot Options gt Hard Disk Order Boot Options Hard Disk 1 lt Available Hard Disks gt Hard Disk 2 lt Available Hard Disks gt Figure 39 Setup Utility Hard Disk Order Screen Display Table 37 Setup Utility Hard Disk Order Fields Setupltem Options Help Text Hard Disk 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Hard Disk 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 4 CDROM Order Screen The CDROM Order screen allows the user to control the CDROM devices To access this screen from the
122. er during turn off The following tables and diagrams show the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied Revision 1 2 133 Intel order number E39529 009 Design and Environmental Specifications Intel Server Board S5520HC S5500HCV TPS Table 78 Output Voltage Timing Item Description Minimum Maximum Units Tout rise Output voltage rise time from each main output 5 0 70 ms Tout rise All main outputs must be within regulation of each other within this N A 50 ms time Tout rise All main outputs must leave regulation within this time N A 400 ms 1 The 5 VSB output voltage rise time is from 1 0 ms to 25 ms V out 10 V out Wb esee e v2 x i v3 i i d V4 i X E Le Tvout off lt gt Tyout rise mo Tvout on TP02313 Figure 54 Output Voltage Timing 134 Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Item Tsb on delay Tac on delay Tyout_holdup Tpwok holdup Tpson on delay Tpson pwok T pwok on T pwok off T pwok low T b vout TsvsB holdup AC Input Tus holdup Tib on delay PWOK 5VSB TAC on delay f Table 79 Turn On Off Timing Description Delay from AC being applied to 5 VSB being within regulation Delay from AC being applied to all output voltage
123. erate an error stating the BMC is still in update mode Power down and remove the AC power cord Open the server chassis Move the jumper J1H1 from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC power cord and power up the server Note When the Force BMC Update jumper is set to the enabled position normal BMC functionality is disabled You should never run the server with the Force BMC Update jumper set in this position You should only use this jumper setting when the standard firmware update process fails When the server is running normally this jumper must remain in the default disabled position 7 3 BIOS Recovery Jumper Power down the system and remove the AC power cord Open the server chassis See your server chassis documentation for instructions Move the BIOS recovery jumper J1E5 from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 Close the server chassis Reconnect the AC power cord and power up the server Perform the BIOS Recovery procedure as documented in the BIOS Recovery Instruction txt file included in the given BIOS recovery image Revision 1 2 119 Intel order number E39529 009 Jumper Blocks Intel Server Board S5520HC S5500HCV TPS 7 After successful completion of the BIOS recovery the BIOS has been updated successfully message displays
124. es an access point to configure several options On this screen the user selects the option they must configure Configurations are performed on the selected screen and not directly on the Advanced screen To access this screen from the Main screen press the right arrow until the Advanced screen is selected Advanced Security gt Processor Configuration Memory Configuration Server Management gt Mass Storage Controller Configuration gt Serial Port Configuration gt USB Configuration gt PCI Configuration Boot Options gt System Acoustic and Performance Configuration Figure 23 Setup Utility Advanced Screen Display Table 21 Setup Utility Advanced Screen Display Fields Setup Item Processor Configuration Memory Configuration Mass Storage Controller Configuration Serial Port Configuration USB Configuration PCI Configuration System Acoustic and Performance Configuration Revision 1 2 Options Help Text View Configure processor information and settings View Configure memory information and settings View Configure mass storage controller information and settings View Configure serial port information and settings View Configure USB information and settings View Configure PCI information and settings View Configure system acoustic and performance information and settings Intel order number E39529 009 Boot Manager Comments 73 BIOS Setup Utility 5 3 2
125. evelop a power supply for its 5U server system The combined power of all outputs should not exceed the rated output power of the power supply The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions Table 73 670 W Load Ratings Voltage Minimum Continuous Maximum Continuous Peak 43 3 V 1 0A 24 A 5 V 2 0A 30A 12 V1 0 5A 16A 18A 12 V2 1 0A 16A 18A 12 V3 0 5A 31A 33A 12 V4 1 0A 16A 18A 12V OA 0 5A 5 VSB 0 1A 3 0A 5A 1 Maximum continuous total output power must not exceed 670 W 2 Maximum continuous load on the combined 12 V output must not exceed 48 A 3 Peak load on the combined 12 V output must not exceed 52 A 4 Peak total DC output power must not exceed 730 W 5 For 12 V peak power and current loading are supported for a minimum of 12 seconds 6 For 5 VSB 5 VSB must withstand 5 A for 500 ms under the first turn on condition 7 Combined 3 3 V and 5 V power must not exceed 170 W 130 Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Design and Environmental Specifications 9 4 1 Grounding The output ground of the pins of the power supply provides the output power return path The output connector ground pins are connected to the safety ground power supply enclosure 9 4 2 Stand by Outputs The 5 VSB output should be present when an AC input is greater than the power supply turn on voltage is appli
126. explains the advanced management features supported by the BMC firmware Table 13 lists basic and advanced feature support Individual features may vary by platform For more information refer to Appendix C Table 16 Basic and Advanced Management Features Advanced Feature O O Acoustic Management Diagnostic Beep Code Support Intel amp Intelligent Power Node Manager Support SMASH CLP X WS Management X Basic management features provided by integrated BMC Advanced management features available with optional Intel amp Remote Management Module 3 Inte amp Intelligent Power Node Manager Support requires PMBus compliant power supply Power State Retention X X X X X X X X ARP DHCP Support x x x X X X X X 4 2 1 Enabling Advanced Management Features BMC will enable advanced management features only when it detects the presence of the Intel Remote Management Module 3 Intel RMM3 card Without the Intel RMM3 the advanced features are dormant 4 2 1 1 Intel Remote Management Module 3 Intel RMM3 The Intel RMM3 provides the BMC with an additional dedicated network interface The dedicated interface consumes its own LAN channel Additionally the Intel RMM3 provides additional flash storage for advanced features such as WS MAN Revision 1 2 57 Intel order number E39529 009 Platform Management Intel Server Boards S5520HC and S5500HCV TPS 4 2 2 Keyboard Video and Mouse KV
127. eyboard component encountered a stuck key error No Pause 0113 Fixed Media The SAS RAID firmware can not run properly The user should attempt to reflash the firmware 0140 0141 0146 0192 0193 0194 0195 0196 0197 0198 BE 5221 5224 8160 8161 8180 Processor 0x microcode update not found 8198 8300 84F2 84F3 Baseboard management controller in update mode B4FF 8500 8520 8521 8522 8523 DIMM B2 failed Self Test BIST 8524 DIMM C1 failed Self Test BIST 5220 CMOS NVRAM Configuration Cleared 2526 8627 8628 8626 862A 8526 8540 DIMM A1 Disabled Pause 8541 DIMM A9 Disabled Pause 168 Revision 1 2 Intel order number E39529 009 8525 DIMM C2 failed Self Test BIST Intel Server Board S5520HC S5500HCV TPS Appendix F POST Error Messages and Handling DIMM C2 Disabled DIMM D1 Disabled 8569 DIMM_E2 Component encountered a Serial Presence Detection SPD fail error Pause 85A2 DIMM B1 Uncorrectable ECC error encountered Pause 85A3 DIMM_B2 Uncorrectable ECC error encountered Pause 9266 Local Console component encountered a controller error Revision 1 2 169 Intel order number E39529 009 Appendix F POST Error Messages and Handling Intel Server Board S5520HC S5500HCV TPS Serial Port component encountered an input error No Pause Serial Port component encountered an output error No Pause 0xA001 TPM device missing or not responding No Pause 0xA028 Processor
128. fect the ability to configure RAID The Intel SAS Entry RAID Module option is enabled by default once the Intel SAS Entry RAID Module AXX4SASMOD is present When enabled you can set the Configure Intel SAS Entry RAID Module to either LSI Integrated RAID or Intel ESRTII mode Revision 1 2 47 Intel order number E39529 009 Functional Architecture SW RAID Intel Embedded Server RAID Technology II ESRTII IT IR RAID IT IR RAID Entry Hardware RAID Intel Server Boards S5520HC and S5500HCV TPS Table 12 Intel SAS Entry RAID Module AXX4SASMOD Storage Mode RAID RAID e ies Description NTR ipa ee d Driver Management Software Gi ie PP Software User s Guide p Native SAS pass through mode without RAID function SAS MPT TSAS Ports Entry Hardware driver Fully Up to 10 SAS RAID open source Intel RAID Web IT IR RAID ITIR RAID or SATA drives RAID 1 IM driver Console 2 SE M AXX6DRV3GR i 7 Ser s Guilde eres mode Broad OS AXX4DRV3GR RAID 10 10E SUPPO AXX6DRV3GEX IME mode P RAIDO IS AXX4DRV3GEX Mode P 4 SAS Ports SW RAID 0 1 10 ESRF Driver Upto8SASor Sander de Intel RAID Web Del RAID SWRAID SATA drives SW RAID 5 with Windows rand ere Software via expander optional eea User s Guide backplanes AXXRAKSW5 Versions only Select in BIOS Setup Configure Intel SAS Entry RAID Option on Advanced Mass Storage Controller Configuration Screen 3 6 1 1 IT R RAID Mode Suppor
129. figuration Screen Fields Setup Item Options Help Text Enabled Disabled Enabled Disabled Auto Enabled Disabled Enabled Disabled Auto Floppy Forced FDD Hard Disk CD ROM Enabled Disabled Enabled All onboard USB controllers are turned on and accessible by the OS Disabled All onboard USB controllers are turned off and inaccessible by the OS USB device boot support and PS 2 emulation for USB keyboard and USB mouse devices Auto Legacy USB support is enabled if a USB device is attached UO port 60h 64h emulation support Note This may be needed for legacy USB keyboard support when using an OS that is USB unaware Exclude USB in Boot Table Enabled This removes all USB Mass Storage devices as Boot options Disabled This allows all USB Mass Storage devices as Boot options USB Mass Storage device Start Unit command timeout Setting to a larger value provides more time for a mass storage device to be ready if needed Auto USB devices less than 530 MB are emulated as floppies Forced FDD HDD formatted drive are emulated as a FDD e g ZIP drive Onboard USB ports are enabled to support USB 2 0 mode Contact your OS vendor regarding OS support of this feature Intel order number E39529 009 Information only Shows the number of USB devices in the system Grayed out if the USB Controller is disabled Grayed out if the USB Controller is disabled Grayed ou
130. four bits of ED3 byte provides the device number and the lower four bits of ED3 byte provides the function number s Step 2 Decide the PCI device with location number Bus number Device number and Function number using PCI map dump from the system generating the PCI Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Appendix A Integration and Usage Tips device SEL event There are multiple means to dump the PCI map For example read the location number from the device general property page in device manager under Microsoft Windows Operating Systems or type PCI and execute under the server board EFI shell s Example of deciding the PCI device that generates SEL event entry 1 Provided a PCI device SEL event entry in Hex code reads the ED2 as 01 and ED3 as 00 that is the PCI device has bus number 1 device number 0 and function number 0 2 The PCI dump from this system indicates the device with bus number 1 device number 0 and function number 0 as Network Controller Ethernet controller and there is no add in NIC inserted thus the PCI device generate the SEL event entry is onboard NIC controller Revision 1 2 147 Intel order number E39529 009 Appendix B Compatible Intel amp Server Chassis Intel Server Board S5520HC S5500HCV TPS Appendix B Compatible Intel Server Chassis Refer to the following table for the compatible Intel Server Chassis of Intel Server Boards S5
131. g of RDIMMs and UDIMMs Intel Server Board S5520HC 12 DIMM slots Two DIMM slots per channel Intel Server Board S5500HCV Nine DIMM slots Two DIMM slots on Channels A B and C One DIMM slot on Channels D E and F Chipset Intel Server Board S5520HC Intel 5520 Chipset Intel 82801JIR I O Controller Hub ICH10R Intel Server Board S5500HCV Intel 5500 Chipset Intel 82801JIR I O Controller Hub ICH10R Cooling Fan Support Support for Two processor fans 4 pin headers Four front system fans 6 pin headers One rear system fans 4 pin header 3 pin fans are compatible with all fan headers 2 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Overview Feature Description Add in Card Slots Hard Drive and Optical Drive Support RAID Support USB Drive Support I O control support Video Support Intel Server Board S5520HC Six expansion slots One full length full height PCI Express Gen2 slot x16 Mechanically x8 Electrically Three full length full height PCI Express Gen2 x8 slots One full length full height PCI Express Gen1 slot x8 Mechanically x4 Electrically shared with SAS Module slot One 32 bit 33 MHz PCI slot keying for 5 V and Universal PCI add in card Intel Server Board S5500HCV Five expansion slots One full length full height PCI Express Gen2 slot x16 Mechanically x4 Electrically Two full length fu
132. ing PAE You can enable and disable the XD bit in the BIOS Setup The default behavior is enabled 3 2 7 Core Multi Processing The BIOS setup provides the ability to selectively enable one or more cores The default behavior is to enable all cores You can do this through the BIOS setup option for active core count 24 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture The BIOS creates entries in the Multi Processor Specification Version 1 4 tables to describe multi core processors 3 2 8 Direct Cache Access DCA Direct Cache Access DCA is a system level protocol in a multi processor system to improve I O network performance thereby providing higher system performance The basic idea is to minimize cache misses when a demand read is executed This is accomplished by placing the data from the I O devices directly into the processor cache through hints to the processor to perform a data pre fetch and install it in its local caches The BIOS setup provides an option to enable or disable this feature The default behavior is enabled 3 2 9 Unified Retention System Support The server boards comply with Unified Retention System URS and Unified Backplate Assembly The server boards ship with Unified Backplate Assembly at each processor socket The URS retention transfers load to the server boards via the Unified Backplate Assembly The URS spring captive in the hea
133. ing in a degraded state The user may want to replace the erroneous unit The POST Error Pause option setting in the BIOS setup does not have any effect on this error e Pause The message is displayed on the Error Manager screen and an error is logged to the SEL The POST Error Pause option setting in the BIOS setup determines whether the system pauses to the Error Manager for this type of error so the user can take immediate corrective action or the system continues booting Note that for 0048 Password check failed the system will halt and then after the next reset reboot it displays the error code in the Error Manager screen e Halt The system halts during post at a blank screen with the text Unrecoverable fatal error found System will not boot until the error is resolved and Press lt F2 gt to enter setup The POST Error Pause option setting in the BIOS setup does not have any effect with this class of error After entering the BIOS setup the error message displays on the Error Manager screen and an error is logged to the SEL with the error code The system cannot boot unless the error is resolved The user must replace the faulty part and restart the system Revision 1 2 167 Intel order number E39529 009 Appendix F POST Error Messages and Handling Intel Server Board S5520HC S5500HCV TPS Table 85 POST Error Messages and Handling Error Code 0012 0048 0108 Keyboard component encountered a locked error 0109 K
134. ith NC SI support 16 bit DDR2 667 MHz interface Dedicated RTC 12 10 bit ADCs Eight Fan Tachometers Four PWMs Battery backed Chassis Intrusion I O Register JTAG Master Six lC interfaces General purpose UO Ports 16 direct 64 serial Additionally the BMC integrates a super I O module with the following features Keyboard style BT interface Two 16550 compatible serial ports Serial IRQ support 16 GPIO ports shared with the BMC LPC to SPI bridge for system BIOS support SMI and PME support The BMC also contains an integrated KVMS subsystem and graphics controller with the following features USB 2 0 for Keyboard Mouse and Storage devices USB 1 1 interface for legacy PS 2 to USB bridging Hardware Video Compression for text and graphics Hardware encryption 2D Graphics Acceleration DDR2 graphics memory interface Up to 1600x1200 pixel resolution PCI Express x1 support Revision 1 2 49 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS Fan Tach ADC LPC Master Interrupt 8 JTAG Master Controller PWM amp 4 SPI Flach ARM926E 5 ioKD amp l Ca RICA Crypto General Purpose UART Fo amp Timars 3 8 Video 3 Accelaralor che Ethernet MAC Kou RMII interface 2 DDR 2 ipto 667 MHz LPC interface to Host Real Time clock LPC to SPI Interface Flash Bridge Welch Tir requires external RTC ubsystem SPI Me
135. itor the fan speed 5 Fan Presence In indicates the fen is preset O O O O O OSOS 6 Fan FautLED Ou Lights thefanfauk LED Z o Note Intel Corporation server boards support peripheral components and can contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits 116 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Jumper Blocks 7 Jumper Blocks The server boards have several 3 pin jumper blocks that you can use to configure protect or recover specific features of the server boards The following symbol identifies Pin 1 on each jumper block on the silkscreen V ME Force CMOS Update Clear Disable Disable Enables Enable Password BIOS Clear Recover Disable Enabe4
136. le 22 Setup Utility Processor Configuration Screen Fields Setup item ei BUDE a ee ae J kee ao amd EE Lo d dan ENS Current Intel QPI Link Speed Intel QPI Link Frequency Intel amp Turbo Boost Technolgy Enabled Disabled Enabled Disabled Enhanced Intel SpeedStep Tech Enabled Disabled Intel amp Hyper Threading Tech Help Text Intel amp Turbo Boost Technology allows the processor to automatically increase its frequency if it is running below power temperature and current specifications Enhanced Intel SpeedStep amp Technology allows the system to dynamically adjust processor voltage and core frequency which can result in decreased average power consumption and decreased average heat production Contact your OS vendor regarding OS support of this feature Intel amp HT Technology allows multithreaded software applications to execute threads in parallel within each processor Contact your OS vendor regarding OS support of this feature Comments Information only Processor CPUID Information only Current frequency of the processor Information only Revision of the loaded microcode Information only Size of the Processor L1 Cache Information only Size of the Processor L2 Cache Information only Size of the Processor L3 Cache Information only ID string from the Processor Information only ID string from the Processor Information o
137. le to direct serial B to the rear of a chassis The serial B interface follows the standard RS232 pin out as defined in the following table Table 13 Serial B Header Pin out Pin Signal Name Serial Port B Header Pin out 1 DCD 2 DSR 1 2 3 RX 3 oo 4 4 RTS OO 5 TX 12160 5 6 CTS 7 OO 8 7 DTR o 8 RI 9 GND 3 9 Floppy Disk Controller The Intel Server Boards S5520HC and S5500HCV do not support a floppy disk controller interface However the system BIOS recognizes USB floppy devices 3 10 Keyboard and Mouse Support The Intel Server Boards S5520HC and S5500HCV do not support PS 2 interface keyboards and mice However the system BIOS recognizes USB Specification compliant keyboards and mice 3 11 Video Support The Intel Server Boards S5520HC and S5500HCV integrated BMC include a 2D SVGA video controller and 8 MB video memory The 2D SVGA subsystem supports a variety of modes up to 1024 x 768 resolution in 8 16 24 32 bpp It also supports both CRT and LCD monitors with up to an 85 Hz vertical refresh rate Video is accessed using a standard 15 pin VGA connector found on the back edge of the server boards You can disable the onboard video controller using the BIOS Setup Utility or when an add in video card is detected The system BIOS provides the option for Dual Monitor Video operation when an add in video card is configured in the system Revision 1 2
138. ll height PCI Express Express Gen2 x8 slots One full length full height PCI Express Gent slot x8 Mechanically x4 Electrically shared with SAS Module slot One 32 bit 33 MHz PCI slot keying for 5 volt and Universal PCI add in card Optical devices are supported Six SATA connectors at 1 5 Gbps and 3 Gbps Four SAS connectors at 3 Gbps through optional Intel SAS Entry RAID Module AXX4SASMOD Intel Embedded Server RAID Technology II through onboard SATA connectors provides SATA RAID 0 1 and 10 with optional RAID 5 support provided by the Intel RAID Activation Key AXXRAKSW5 Intel Embedded Server RAID Technology II through optional Intel SAS Entry RAID Module AXX4SASMOD provides SAS RAID 0 1 and 10 with optional RAID 5 support provided by the Intel RAID Activation Key AXXRAKSW5 IT IR RAID through optional Intel SAS Entry RAID Module AXX4SASMOD provides entry level hardware RAID 0 1 10 10E and native SAS pass through mode 4 ports full featured SAS SATA hardware RAID through optional Intel Integrated RAID Module SROMBSASMR AXXROMBSASMR provides RAID 0 1 5 6 and striping capability for spans 10 50 60 One internal type A USB port with USB 2 0 support that supports a peripheral such as a floppy drive One internal low profile USB port for USB Solid State Drive External connections DB9 serial port A connection One DH 10 serial port connector optional Two RJ 45 NIC connectors for 10 100 1000 Mb con
139. ls for CPU 1 socket are identified as Channels A B and C The memory channels for CPU 2 socket are identified as Channels D E and F e The DIMM identifiers on the silkscreen on the board provide information about which channel CPU Socket they belong to For example DIMM A41 is the first slot on Channel A of CPU 1 socket DIMM D1 is the first slot on Channel D of CPU 2 Socket e Processor sockets are self contained and autonomous However all configurations in the BIOS setup such as RAS Error Management and so forth are applied commonly across sockets The Intel Server Board S5520HC supports six DDR3 memory channels three channels per processor with two DIMM slots per channel thus supporting up to twelve DIMMs in two processor configuration See Figure 16 for the Intel Server Board 5520HC DIMM slots arrangement The Intel Server Board S5500HCV supports six DDR3 memory channels three channels per processor with two DIMM slots per channel at Channels A B and C and one DIMM slot per channel at Channels D E and F thereby supporting up to nine DIMMs in a two processor configuration See Figure 17 for the Intel Server Board S5500HCV DIMM slots arrangement 26 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Functional Architecture OSUS CPU 1 Sod DIMM Fi F2 E1 E2 D1D2
140. lt Power Control Failure recoverable Amber Solid on Fan redundancy lost insufficient system cooling This does not apply to non redundant systems Power supply redundancy lost insufficient system power This does not apply to non redundant systems Note This state also occurs when AC power is first applied to the system This indicates the BMC is booting AC power off if no degraded non critical critical or non recoverable conditions exist Not ready System is powered down or S5 states if no degraded non critical critical or non recoverable conditions exist When the server is powered down transitions to the DC off state or S5 the BMC is still on standby power and retains the sensor and front panel status LED state established before the power down event If the system status is normal when the system is powered down the LED is in a solid green state the system status LED is off 124 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Intel amp Light Guided Diagnostics 8 4 DIMM Fault LEDs The server boards provide memory fault LED for each DIMM socket These LEDs are located as shown in the following figure The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs DIMM Fault LEDs D A2 A 2 Al BEG B1 C2 C1
141. may boot in to EFI shell instead Guideline Type exit and execute under the EFI shell the RAID adapter configuration screen will show up if configuration screen hot keys were pressed during POST 6 See 32MB video memory of onboard video controller after install onboard video driver Description After install driver of Intel Server Boards S5520HC and S5500HCV onboard video controller the video driver will report 32MB video memory instead of 8MB Guideline The memory reported by onboard video driver is attached memory which is accessed by the video controller for internal operations The graphic memory size for display function is still 8MB Revision 1 2 173 Intel order number E39529 009 Glossary Intel amp Server Board S5520HC S5500HCV TPS Glossary Term Definition ACPI Advanced Configuration and Power Interface AHCI Advanced Host Controller Interface Active Management Technology P A Application Processor APIC Advanced Programmable Interrupt Control Address Resolution Protocol A PATS Address Translation Technology O 5 b B C Boot Strap Processor 8 bit quantity ch 7 Controller Link p CLTT Closed Loop Thermal Throttling In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board DHCP Dynamic Host Configuration Protocol DIMM Dual in line memory module Bits per pixel Direct
142. modules required for booting EFl aware Operating Systems Enabled Disabled Boot Option Retry Enabled Disabled USB Boot Priority Enabled Disabled Use Legacy Video for EFI OS If enabled the BIOS will use the legacy video ROM instead of the EFI video ROM If enabled this continually retries non EFI based boot options without waiting for user input If enabled newly discovered USB devices will be put to the top of their boot device category If disabled newly discovered USB devices will be put at the bottom of the respective list Revision 1 2 Intel order number E39529 009 Displays when one or more hard disk drives are in the system Displays when one or more CD ROM drives are in the system Displays when one or more floppy drives are in the system Displays when one or more of these devices are available in the system Displays when one or more of these devices are available in the system This option is only displayed if an EFI bootable device is available to the system for example a USB drive If the EFI shell is deleted it is restored on the next system reboot It cannot be permanently deleted Grayed out when SW RAID SATA Mode is Enabled SW RAID can only be used in Legacy Boot mode Only displays when EFI Optimized Boot is enabled 95 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS If all types of bootable devices are installed in th
143. mory 1x PCI Express Interface to Host Figure 20 Integrated BMC Hardware 3 7 1 BMC Embedded LAN Channel The BMC hardware includes two dedicated 10 100 network interfaces Interface 1 This interface is available from either of the available NIC ports in system that can be shared with the host Only one NIC may be enabled for management traffic at any time The default active interface is onboard NIC1 Interface 2 This interface is available from Intel Remote Management Module 3 Intel RMMS3 which is a dedicated management NIC and not shared with the host For these channels you can enable support for IPMI over LAN and DHCP For security reasons embedded LAN channels have the following default settings P Address Static All users disabled IPMI enabled network interfaces may not be placed on the same subnet This includes the Intel RMM3 s onboard network interface and either of the BMC s embedded network interfaces 50 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture 3 8 Serial Ports The Intel Server Boards S5520HC and S5500HCV provide two serial ports an external DB9 serial port and an internal DH 10 serial header The rear DB9 serial A port is a fully functional serial port that can support any standard serial device Serial B is an optional port accessible through a 9 pin internal DH 10 header You can use a standard DH 10 to DB9 cab
144. n 16 SMB SENSOR 3 SMB Sensor V3STB DATA DATA 17 BND Reset GND Reset Button 18 SMB SENSOR 3 SMB Sensor Ground V3STB CLK Clock 19 FP ID BTN N ID Button 20 FP CHASSIS IN Chassis TRU Intrusion 21 FM SIO TEMP SEN Front Panel 22 NIC2 ACT LED NIC 2 Activity Revision 1 2 109 Intel order number E39529 009 Connector Header Locations and Pin outs Intel amp Server Board S5520HC S5500HCV TPS SOR Temperature N LED Sensor 23 FP NMI BTN N NMI Button 24 NIC2 LINK LED NIC 2 Link N LED 6 5 I O Connectors VGA Connector 6 5 1 The following table details the pin out definition of the VGA connector J7A1 that is part of the stacked video serial port A connector 6 5 2 Table 55 VGA Connector Pin out J7A1 Pim SignalName Descripton Red analog color signal R Green analog color signal G Blue analog color signal B 6 GND Ground 7 GND Ground s ono Joo 9 TP VID CON ES HSYNC horizontal sync VSYNC vertical sync NIC Connectors The server boards provide two stacked RJ 45 2xUSB connectors side by side on the back edge of the board J5A1 J6A1 The pin out for NIC connectors is identical and defined in the following table 110 Table 56 RJ 45 10 100 1000 NIC Connector Pin out J5A1 J6A1 Pin Signal Name 6 MCAMDNN 5 MCAMDHN Intel order number E39529 009 Revision 1 2 Intel
145. n chassis development and testing that when Intel server building blocks are used together the fully integrated system meets the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of the published operating or non operating limits Revision 1 2 1 Intel order number E39529 009 Overview Intel Server Boards S5520HC and S5500HCV TPS 2 Overview The Intel Server Boards S5520HC and S5500HCV are monolithic printed circuit boards PCBs with features designed to support the pedestal server markets 2 1 Intel Server Boards S5520HC and S5500HCV Feature Set reste Deserigton O 1 Processors Support for one or two Intel Xeon Processor s 5500 series 4 8 GT s 5 86 GT s and 6 4 GT s Intel QuickPath Interconnect Intel QPI FC LGA 1366 Socket B Thermal Design Power up to 95 W Enterprise Voltage Regulator Down EVRD 11 1 Six memory channels three channels for each processor socket Channels A B C D E and F Support for 800 166 1333 MT s ECC Registered DDR3 Memory RDIMM ECC Unbuffered DDR3 memory UDIMM No support for mixin
146. nagement Headers 6 3 1 A 34 pin Intel RMM3 connector J1C1 is includ Intel amp Server Board S5520HC S5500HCV TPS Intel Remote Management Module 3 Connector ed on the server boards to support the optional Intel Remote Management Module 3 These server boards do not support third party management cards Note This connector is not compatible with the ntel Remote Management Module Intel RMM or the Intel Remote Management Module 2 Intel RMM2 Table 50 Intel RMM3 Connector Pin out J1C1 P Signal name Pm s m o GND Esas 35 7 Car Pi 17 GND 19 GND 2 2 zi 3V3 AUX 3V3 AUX 2 is ep fo n 2 4 6 8 10 12 13 GND 14 16 18 0 2 24 23 29 NC spare SPI DO SPI CLK 31 8 GND 30 GND 32 D GN 34 LCP IPMB Header 6 3 2 SPI DI RMMS Present N pulled high on baseboard and shorted to ground on the plug in module Table 51 LCP IPMB Header Pin out J1G6 Pin Signal Name SMB IPMB 5VSB DAT _ BMC IMB 5 V standby data line SMB IPMB 5VSB CLK _ BMC IMB 5 V standby clock line P5V_STBY 5 V standby power 108 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Connector Header Locations and Pin outs 6 3 3 HSBP Header Table 52 HSBP Header Pin out J1F5 J1G3 Pin Signal Name 3 SMB IPMB 5V CLK BMC IMB 5V Clock Line j P5V HSBP A 5 V for HS
147. nd E should be identical including across adjacent slots on the channels The DIMMs on successive slots are not required to be identical and can have different sizes and or timings but the overall channel timing reduces according to the slowest DIMM If Channels A and B are not identical or Channels D and E are not identical the BIOS selects default Independent Channel Mode If Channel C or F is not empty the BIOS disables the Mirrored Channel Mode When only CPU1 socket is populated minimal population upgrade for Mirrored Channel Mode is DIMM A1 and DIMM B1 DIMM A1 and DIMM B1 must be identical or will fall back to Independent Channel Mode When both CPU sockets are populated minimal population upgrade for the Mirrored Channel Mode is DIMM A1 DIMM B1 DIMM D1 DIMM EI DIMM A1 and DIMM B1 as a pair must be identical and so must DIMM D1 and DIMM E1 as a pair The DIMMs on different CPU sockets need not be identical in size and or sizing although overall channel timing reduces according to the slowest DIMM 3 3 10 Supported Memory Configuration 3 3 10 1 Supported Memory Configurations The following sections describe the memory configurations supported and validated on the Intel Server Boards S5520HC and S5500HCV 3 3 10 1 1 Levels of support The following categories of memory configurations are supported Supported These configurations were verified by Intel to work but only limited validation was performed Not all po
148. nections Dual GbE through the Intel 82575EB Network Connection Four USB 2 0 ports at the back of the board Internal connections Two 9 pin USB headers each supports two USB 2 0 ports One DH10 serial port B header Six SATA connectors at 1 5 Gbps and 3 Gbps Four SAS connectors at 3 Gbps optional One SSI compliant 24 pin front control panel header ServerEngines LLC Pilot II with 64 MB DDR2 memory 8 MB allocated to graphics Integrated 2D video controller Dual monitor video mode is supported Revision 1 2 Two Gigabit through Intel 82575EB PHYs with Intel I O Acceleration Technology 2 support Intel order number E39529 009 Overview Intel Server Boards S5520HC and S5500HCV TPS Feature Description Server Management e Onboard ServerEngines LLC Pilot II Controller Integrated Baseboard Management Controller Integrated BMC IPMI 2 0 compliant Integrated Super I O on LPC interface e Support for Intel Remote Management Module 3 e Intel Light Guided Diagnostics on field replaceable units e Support for Intel System Management Software 3 1 and beyond e Support for Intel Intelligent Power Node Manager Need PMBus compliant power supply BIOS Flash e Winbond W25X64 Compatible Intel amp e Intel Server Chassis SC5650DP Server Chassis e Intel Server Chassis SC5650BRP PMBus compliant Power Supply e Intel Server Chassis SC5600Base e Intel Server Chassis SC5600BRP PMBus compliant Power Supply e
149. nly Current speed that the QPI Link is using Information only Current frequency that the QPI Link is using This option is only visible if all processors in the system support Intel amp Turbo Boost Technology Core Multi Processing Enabled Disabled Execute Disable Bit Revision 1 2 Enable 1 2 or All cores of installed processors packages Execute Disable Bit can help prevent certain classes of malicious buffer overflow attacks Contact your OS vendor regarding OS support of this feature Intel order number E39529 009 75 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS Setup tem Options Help Text Comments Intel Virtualization Enabled Intel Virtualization Technology allows a Technology Disabled platform to run multiple operating systems and applications in independent partitions Note A change to this option requires the system to be powered off and then back on before the setting takes effect Intel Virtualization Enabled Enable Disable Intel Virtualization Technology for Directed Disabled Technology for Directed I O vO Report the I O device assignment to VMM through DMAR ACPI Tables Interrupt Remapping Enabled Enable Disable Intel VT d Interrupt Only appears when Intel Disabled Remapping support Virtualization Technology for Directed I O is enabled Coherency Support Enabled Enable Disable Intel VT d Coherency Only appears when Intel Disabled support Virtuali
150. ns International e EN55022 Emissions Europe e EN55024 Immunity Europe e CE EMC Directive 89 336 EEC Europe e AS NZS 3548 Emissions Australia New Zealand e VCCI Emissions Japan Revision 1 2 137 Intel order number E39529 009 Regulatory and Certification Information Intel Server Board S5520HC S5500HCV TPS 138 BSMI CNS13438 Emissions Taiwan RRL Notice No 1997 41 EMC amp 1997 42 EMI Korea GOST R 29216 91 Emissions Russia Listed on System License GOST R 50628 95 Immunity Russia Listed on System License Belarus License Belarus Listed on System License Certifications Registrations Declarations UL Certification or NRTL US Canada CB Certifications International CE Declaration of Conformity CENELEC Europe FCC ICES 003 Class A Attestation USA Canada C Tick Declaration of Conformity Australia MED Declaration of Conformity New Zealand BSMI Certification Taiwan RRL KCC Certification Korea Ecology Declaration International Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Regulatory and Certification Information 10 2 Product Regulatory Compliance Markings Regulatory Compliance UL Mark CE Mark EMC Marking Class A BSMI Marking Class A C tick Marking RRL KCC Mark CNCA EFUP Mark Country of Origin Model Designation Country USA Canada Europe Canada Taiwan Australia
151. ns tdt onem Dd o cesis ts cades edd 142 10 4 Product Ecology Change EU Ro 142 10 5 Product Ecology Change Co 142 10 6 China Packaging Recycle Marks or GB18455 2001 sssseessss 145 10 7 CA Perchlorate Warning nennen retener tnn 145 10 8 End of Life Product Recycling ccccceceeceeeeeeeeeeeeeeeeeeeeeceeacaeaaeeeeeeeeeeeeeeeeeeeeees 145 Appendix A Integration and Usage Tips esee eene nnne nennen nnn 146 Appendix B Compatible Intel Server Chassis eese esee 148 Appendix C BMC Sensor Tables cccsssscssseeesesenceeesseeeesnseneesssenesesseeeeenseeeeseseneeessneeeenses 151 Appendix D Platform Specific BMC Appendix eeeeeeeeeeeeeenneneen nnne nnne 161 Appendix E POST Code Diagnostic LED Decoder eere 163 Appendix F POST Error Messages and Handling eere 167 Appendix G Installation Guidelines eeeeeeeeeeeeeeeeeeeeeeeenne enne nnne nnne 172 GOSS ANY A HM 174 Reference Documents eseeeeeeeseeeeeeeeeeee eene ee nnn nn nnn n neta nasse nnn tn aia suse ener n nanus ann KEEN 178 VR Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS List of Figures List of Figures Figure 1 Intel Server Board Spp20HC 5 Figure
152. ntal Specifications 9 Design and Environmental Specifications 9 4 Intel Server Boards S5520HC and S5500HCV Design Specifications Operation of the Intel Server Boards S5520HC and or S5500HCV at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 70 Server Board Design Specifications Operating Temperature 0 C to 55 C 1 32 F to 131 F Non Operating Temperature 40 C to 70 C 40 F to 158 F DC Voltage 5 of all nominal voltages Shock Unpackaged Trapezoidal 50 G 170 inches sec Shock Packaged lt 20 pounds 36 inches 20 to lt 40 pounds 30 inches 40 to lt 80 pounds 24 inches 80 to lt 100 pounds 18 inches 100 to lt 120 pounds 12 inches 120 pounds 9 inches Vibration Unpackaged 5 Hz to 500 Hz 3 13 g RMS random Note Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature Disclaimer Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to u
153. ntel order number E39529 009 Platform Management Intel Server Boards S5520HC and S5500HCV TPS 4 3 2 3 1 Performance Mode Default With the platform running in Performance mode Default several platform control algorithm variables are set to enhance the platform s capability of operating at maximum performance targets for the given system In doing so the platform is programmed with higher fan speeds at lower ambient temperatures This results in a louder acoustic level than is targeted for the given platform but the increased airflow of this operating mode greatly reduces both possible memory throttling from occurring and dynamic fan speed changes based on processor utilization 4 3 2 3 2 Acoustics Mode With the platform running in Acoustics mode several platform control algorithm variables are set to ensure acoustic targets are not exceeded for specified Intel platforms In this mode the platform is programmed to set the fans at lower speeds when the processor does not require additional cooling due to high utilization power consumption Memory throttling is used to ensure memory thermal limits are not exceeded Note Fan speed control for a non Intel chassis as configured after running the FRUSDR utility and selecting the Non Intel Chassis option is limited to only the CPU fans The BMC only requires the processor thermal sensor data to determine how fast to operate these fans The remaining system fans will operate at 100 opera
154. oller sss 49 3 7 1 BMC Embedded LAN Channel 50 3 8 ee LEE 51 3 9 Floppy Disk Controller saider aieiai aar d e eaaa atap ia een 51 3 10 Keyboard and Mouse Gupport 51 3 11 Video SUpport i eter Ee ata ir de d e ee e re eaten ae 51 93 111 Video Modes EE 52 3 112 Dual Vid aene tte ete e EIU de e eet eft o 52 3 12 Network Interface Controller NIC 53 3 12 1 MAC Address Detimtton eene 53 3 13 ACPISUppott E 54 3 14 Intel Virtualization Technology 54 3 14 1 Intel Virtualization Technology for Directed IO ONT 54 3 15 Intel UO Acceleration Technology ee enne 54 4 Platform Manageme nt cccssccccssseeesessneecesseeeeenseeeesesensesseseeeesneeneessesnesesseeeesseeeeesseneeeenss 55 4 1 Feature Support oc esters ertt ere see reden e Sb ie Ede ee Longue re t Le Pads 55 4 1 1 IPMI 2Z 0 Features 17 ute ap e eee eee bei 55 4 1 2 Non IPMI Features AAA 55 4 2 Optional Advanced Management Feature Support 57 4 2 1 Enabling Advanced Management Features 57 Revision 1 2 V Intel order number E39529 009 Table of Contents Intel Server Boards S5520HC and S5500HCV TPS 4 2 2 Keyboard Video and Mouse KVM Redirection ssssssssseseserrreerrrrnrrrrrrenereseere 58 4 2 3 Media Redirection itt aceon ete ete aen be E EET RR RC dete 58 4 2 4 Web Services for Management NG MAN 59 4 2 5 Embedded Web server EEN 60 4 2 6 Local Directory Authentication Protocol DAD 60
155. ompliant 2x12 pin connector J1K3 Three additional power related connectors also exist Two SSl compliant 2x4 pin power connectors J9A1 J9K1 to provide 12 V power to the CPU voltage regulators and memory One SSl compliant 1x5 pin connector J9K2 to provide 1 C monitoring of the power supply The following tables define these connector pin outs Table 46 Main Power Connector Pin out J1K3 Pin Signal Signal Color 2 3 GND 4 5 GND GND 7 GND RSVD 5 V 5Vdc Red 10 12vde Yellow 11 Lotuge Yellow 12 GND 106 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS Connector Header Locations and Pin outs Table 47 CPU 1 Power Connector Pin out J9A1 Pim Signal eor 12 Vdc CPU1 Yellow black 6 12 Vdc CPU1 Yellow black 7 12 Vdc Yellow black DDR3_CPU1 12 Vdc Yellow black DDR3_CPU1 Table 48 CPU 2 Power Connector Pin out J9K1 Pin Signal Color GND of Pin GND of Pin 6 3 GND of Pin 7 Black 4 GNDofPin8 Black 5 442 Vde CPU2 Yellow black 12 Vdc CPU2 Yelow black 7 12 Vdc Yellow DDR3_CPU2 black 12 Vdc Yellow DDR3_CPU2 black Table 49 Power Supply Auxiliary Signal Connector Pin out J9K2 Pin Siona Cer SMB_CLK FP Eu R 33 V SENSE 33 V SENSE Revision 1 2 107 Intel order number E39529 009 Connector Header Locations and Pin outs 6 3 System Ma
156. oot Priority Enabled Disabled Figure 36 Setup Utility Boot Options Screen Display 94 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 34 Setup Utility Boot Options Screen Fields Setup Item Boot Timeout Help Text The number of seconds the BIOS should pause at the end of POST to allow the user to press the F2 key for entering the BIOS Setup utility Valid values are 0 65535 Zero is the default A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot Set system boot order by selecting the boot option for this position 0 65535 Available boot devices Boot Option x Comments After entering the necessary timeout press the Enter key to register that timeout value to the system These settings are in seconds Hard Disk Order Set the order of the legacy devices in this group CDROM Order Set the order of the legacy devices in this group Floppy Order Set the order of the legacy devices in this group Network Device Order Set the order of the legacy devices in this group CG Set the order of the legacy devices in this group BEV Device Order Add New Boot Option Add a new EFI boot option to the boot order Delete Boot Option Remove an EFI boot option from the boot order Enabled Disabled EFI Optimized Boot If enabled the BIOS only loads
157. ors to determine the required fan speeds In order to provide the proper fan speed control for a given system configuration the BMC must have the appropriate platform data programmed Platform configuration data is programmed using the FRUSDR utility during the system integration process and by System BIOS during run time 4 3 2 1 System Configuration Using the FRUSDR Utility The Field Replaceable Unit and Sensor Data Record Update Utility FRUSDR utility is a program used to write platform specific configuration data to NVRAM on the server board It allows the user to select which supported chassis Intel or Non Intel and platform chassis configuration is used Based on the input provided the FRUSDR writes sensor data specific to the configuration to NVRAM for the BMC controller to read each time the system is powered on 4 3 2 2 Fan Speed Control from BMC and BIOS Inputs Using the data programmed to NVRAM by the FRUSDR utility the BMC is configured to monitor and control the appropriate platform sensors and system fans each time the system is powered on After power on the BMC uses additional data provided to it by the System BIOS to determine how to control the system fans The BIOS provides data to the BMC telling it which fan profile the platform is set up for Acoustics Mode or Performance Mode The BIOS uses the parameters retrieved from the thermal sensor data records SDR fan profile setting from BIOS Setup and altitude setting
158. ort The USB controller functionality integrated into the ICH10R provides the server boards with an interface for up to ten USB 2 0 ports All ports are high speed full speed and low speed capable Four external connectors are located on the back edge of the server boards One internal 2x5 header J1D1 is provided capable of supporting two optional USB 2 0 ports One internal 2x5 header J1D2 is provided for Intel Server or Workstation chassis front panel USB ports capable of supporting two optional USB 2 0 ports One internal USB port type A connector J1H2 is provided to support the installation of a USB device inside the server chassis One internal low profile 2x5 header J2D2 is provided to support a low profile USB Solid State Drive Note Each USB port supports a maximum 500 mA current Only supports up to eight USB ports to draw maximum current concurrently 42 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture 3 5 PCI Subsystem The primary I O buses for the Intel Server Board S5520HC are PCI PCI Express Gen1 and PCI Express Gen2 with six independent PCI bus segments The primary I O buses for the Intel Server Board S5500HCV are PCI PCI Express Gen1 and PCI Express Gen2 with five independent PCI bus segments PCI Express Gen and Gen2 are dual simplex point to point serial differential low voltage interconnects A PCI Express topology
159. ot Timer Timeout 10 minutes timeout value used by the BIOS to configure the Watchdog Timer is 15 minutes watchdog timer disabled 20 minutes Plug amp Play BMC Enabled If enabled the BMC is detectable by OSs that support Detection Disabled plug and play loading of an IPMI driver Do not enable if your OS does not support this driver ACPI 1 0 Support Enabled Enabled Publish ACPI 1 0 version of FADT in Root Needs to be Enabled for Disabled System Description Table Microsoft Windows 2000 May be required for compatibility with OS versions support that only support ACPI 1 0 Console Redirection View Configure console redirection information and Takes the user to the settings Console Redirection screen System Information View system information Takes the user to the System Information screen 90 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 4 1 Console Redirection Screen The Console Redirection screen allows the user to enable or disable console redirection and configure the connection options for this feature To access this screen from the Main screen select Server Management gt Console Redirection Figure 34 Setup Utility Console Redirection Screen Display Revision 1 2 91 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS Table 32 Setup Utility Console Redirection Configuration Fiel
160. patible Compatible Compatible Compatible Compatible CPU 1 Fan Sensor 31 Y Y Y Y N d CPU 2 Fan Sensor 30 Y Y Y Y N Q 3 System Fan 1 Sensor 37 Y Y Y Y Y g System Fan 2 Sensor 36 N N N N Y 63 System Fan 3 Sensor 35 Y Y Y Y Y S System Fan 4 Sensor 34 N N N N Y System Fan 5 Sensor 33 Y Y Y Y N System Fan 1 Presence Sensor N N N N Y 4 40 D 3 System Fan 2 Presence Sensor 9 y 441 N N N N Y ao Q v System Fan 3 Presence Sensor 2 E 442 N N N N Y System Fan 4 Presence Sensor N N N N Y 43 Pan EES CPU 1 Fan CPU 2 CPU 1 Fan CPU 2 CPU 1 Fan CPU 2 Fan CPU 1 Fan CPU 2 N A J Fan Fan Fan Fan Domain 1 System Fan 5 System Fan 5 System Fan 5 System Fan 5 N A Si System Fan 1 3 Fan Domain 2 System Fan 1 System Fan 1 System Fan 1 System Fan 1 System Fan2 Fan Domain 3 System Fan 3 System Fan 3 System Fan 3 System Fan 3 EE System Fan 4 Hot plug Fan Support N N N N Y Fan Redundancy Support N N N N Y Hot Swap HDD Backplane HSC Y Y Y Y Y Availability Revision 1 2 Intel order number E39529 009 161 Appendix D Platform Specific BMC Appendix Intel amp Server Board S5520HC S5500HCV TPS Y Support Intel Server Chassis Intel amp Server Chassis Intel amp Server Chassis Intel amp Server Chassis Intel amp Server N Not Support SC5650DP SC5650BRP SC5600Base SC5600BRP Chassis SC5600LX Power Unit Redundancy Support PMBus compliant Power Suppl
161. pe A USB Port Pin out J1H2 ping Signaler USB_PWR7_5V USB_PWR USB ICH P7N USB port 7 negative signal USB ICH P7P USB port 7 positive signal 6 6 Fan Headers The server boards provide three SSI compliant 4 pin and four SSl compliant 6 pin fan headers to use as CPU and I O cooling fans 3 pin fans are supported on all fan headers 6 pin fans are supported on headers J1K1 J1K2 J1K4 and J1K5 4 pin fans are supported on headers J1K1 J1K2 J1K4 J1K5 J7K1 J9A2 and J9A3 The pin configuration for each of the 4 pin and 6 pin fan headers is identical and defined in the following tables Two 4 pin fan headers are designated as processor cooling fans CPU1 fan J9A2 CPU2 fan J7K1 Four 6 pin fan headers are designated as hot swap system fans Hot swap system fan 1 J1K1 Hot swap system fan 2 J1K4 Hot swap system fan 3 J1K2 Hot swap system fan 4 J1K5 One 4 pin fan header is designated as a rear system fan System fan 5 J9A3 Table 66 SSI 4 pin Fan Header Pin out J7K1 J9A2 J9A3 EE Revision 1 2 115 Intel order number E39529 009 Connector Header Locations and Pin outs Intel Server Board S5520HC S5500HCV TPS 3 FanTach in FAN_TACH signal is connected to the BMC to monitor the fan speed Fan PWM FAN PWM signal to control fan speed Table 67 SSI 6 pin Fan Header Pin out J1K1 J1K2 J1K4 J1K5 pir signare 3 FanTad im FAN TACH signals connected o the BMC to mon
162. pliance Intended Application This product was evaluated as Information Technology Equipment ITE which may be installed in offices schools computer rooms and similar commercial type locations The suitability of this product for other product categories and environments such as medical industrial telecommunications NEBS residential alarm systems test equipment etc other than an ITE application may require further evaluation 10 1 1 Product Safety Compliance The Intel Server Boards 5520HC and S5500HCV comply with the following safety requirements UL60950 CSA 60950 USA Canada EN60950 Europe IEC60950 International CB Certificate amp Report IEC60950 report to include all country national deviations GS License Germany GOST R 50377 92 License Russia Listed on System License Belarus License Belarus Listed on System License CE Low Voltage Directive 73 23 EEE Europe IRAM Certification Argentina 10 1 2 Product EMC Compliance Class A Compliance The Intel Server Boards S5520HC and S5500HCV have been tested and verified to comply with the following electromagnetic compatibility EMC regulations when installed a compatible Intel host system For information on compatible host system s refer to http support intel com support motherboards server S5520HC or contact your local Intel representative e FCC ICES 003 Emissions USA Canada Verification e CISPR 22 Emissio
163. press Gen2 throughput to Slot 6 5520 IOH PCI Express x16 mechanically Express Ports Gen2 40 Gb S PCI x8 PCI Express Gen2 throughput to Slot 5 Express x8 mechanically Gen2 40 Gb S PCI x8 PCI Express Gen2 throughput to Slot 4 Express x8 mechanically Gen2 PE5 PE6 5520 IOH PCI Express Ports PE7 PE8 Revision 1 2 43 Intel order number E39529 009 5520 IOH PCI Express Ports Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS PCI Bus Segment Voltage Width Speed Type PCI I O Card Slots PE9 PE10 5520 IOH PCI Express Ports x8 PCI Express Gen2 throughput to Slot 3 x8 mechanically 3 3V x8 40 Gb S PCI Express Gen2 Table 9 Intel Server Board S5500HCV PCI Bus Segment Characteristics PCI Bus Segment Voltage Width Speed Type PCI32 32 bit 33 MHz PCI PCI Slot 1 ICH10R DEI DEZ PES 10 Gb s PCI x4 PCI Express Gen1 throughput to Slot 2 PE4 Express and Intel SAS Entry RAID Module ICH10R PCI Gen1 AXX4SASMOD slot x8 mechanically Express Ports Default to Slot 2 and switch to SAS Module slot when Intel SAS Entry RAID Module AXX4SASMOD is detected This PCI Express Gent slot is not available when the SAS module slot is in use and vice versa PCI UO Card Slots PE5 ICH10R PCI Express Port PE1 PE2 5500 IOH PCI Express Ports PE3 5500 IOH PCI Express Port PE7 PE8 5500 IOH PCI Express Ports PE9 PE10 5500 IOH P
164. ps Prior to adding or removing components or peripherals from the server board you must remove the AC power cord With AC power plugged into the server board 5 V standby is still present even though the server board is powered off This server board supports Intel Xeon Processor 5500 Series only This server board does not support previous generation Intel Xeon processors You must install processors in order CPU 1 socket is located near the back edge of the server board and must be populated to operate the board and enable CPU 2 socket On the back edge of the server board there are EIGHT diagnostic LEDs that display a sequence of amber POST codes during the boot process If the server board hangs during POST the LEDs display the last POST event run before the hang Only Registered DDR3 DIMMs RDIMMs and Unbuffered DDR3 DIMMs UDIMMs are supported on this server board Mixing of RDIMMs and UDIMMs is not supported Must always start populating DDR3 DIMMs in the first slot on each memory channel Memory slot A1 B1 C1 D1 E1 or F1 Must populate Quad Rank RDIMM starting with the first slot Memory slot A1 B1 C1 D1 E1 or F1 on each memory channel For the best performance you should balance the number of DDR3 DIMMs installed across both processor sockets and memory channels For example with two processors installed a 6 DIMM configuration with identical DIMMs in slot A1 B1 C1 D1 E1 and F1 performs better than a 6 D
165. r Manager screen instead of the Main screen 5 3 1 3 Keyboard Commands The bottom right portion of the Setup screen provides a list of commands used to navigate through the Setup utility These commands display at all times 68 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Each Setup menu page contains a number of features Each feature is associated with a value field except those used for informative purposes Each value field contains configurable parameters Depending on the security option selected and in effect by the password a menu feature s value may or may not change If a value cannot be changed its field is made inaccessible and appears grayed out Key Enter Esc Option Execute Command Exit Select Item Select Item Select Menu Select Field Change Value Change Value Table 19 BIOS Setup Keyboard Command Bar The Enter key is used to activate sub menus when the selected feature is a sub menu or to display a pick list if a selected option has a value field or to select a sub field for multi valued features like time and date If a pick list is displayed the Enter key selects the currently highlighted item undoes the pick list and returns the focus to the parent menu The lt Esc gt key provides a mechanism for backing out of any field When the Esc key is pressed while editing any field or selecting features of
166. r front panel R Processor 2 Fan Header 4 pin NN USB ports S DIMM Sockets of Memory Channel D E and F OO USB Connector 9 pin T SAS Module Slot PP Front Control Panel header U System Fan 3 Header 6 pin QQ DH 10 Serial B header V System Fan 4 Header 6 pin Figure 3 Major Board Components Revision 1 2 Intel order number E39529 009 Overview Intel amp Server Boards S5520HC and S5500HCV TPS 2 1 2 Server Board Mechanical Drawings E sts S s 585 s AS sa ae Siete ee wi ot 334 Se 2 82 Se S SAS AB Sa 2239 2 Tas 22 cf o Da 4 502462 wc I XX SS Se 2 X Q0 1180H0LE FOR MEMORY VR HEATSINK PUSH PIN RETENTION 9 400 3 00 10 161 L 6 000 L L amp 10 001 7 fin 351 ER i 906 25m 22 861 BASEBOARD MOUNTING HOLE q l 10 PLACES i i 1 l D U 1 U D J E F d T E 6 2 510 i l 165 29 I i j i i l l R CPU HEATSINK MOUNTING HOLE 4X2 8 PLACES I 1 1 4 351 i i 110 67 D 1 4 980 Liegt Aust i Vie ix H HOLE FOR T 135 891 ADD ON CARD RETENTION 100 v 0 1180 2 PLACES TERM fist 4 CPU VR HEATSINK MOUNTING HOLES 6 865 EVE de Ox 14 31 A gt 7 150 1 000 ei eu 177 801 Li e i z4 PI a a X a ee 0 0382 24254 PLACES dede 1 910 0 37 202 44 PLATED THROUGH HOLES f 8 340 FOR ANCHOR SOLDERING f 211 84 1 1 7 065 179 45
167. r than 1500m Optimal performance setting at moderate elevation 901m 1500m 2950ft 4920ft Optimal performance setting at high elevation Higher than 1500m 4920ft or greater Optimal performance setting at the highest elevations Set Fan Profile Performance Performance Fan control provides primary system If CLTT is enabled Acoustics cooling before attempting to throttle memory this option is hidden Acoustic The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met 5 3 2 3 Security Screen The Security screen allows the user to enable and set the user and administrative password This is done to lock out the front panel buttons so they cannot be used This screen also allows the user to enable and activate the Trusted Platform Module TPM security settings To access this screen from the Main screen select Security Main Advanced Security Server Management Boot Options Boot Manager Administrator Password Status lt Installed Not Installed gt User Password Status Installed Not Installed gt Set Administrator Password 1234aBcD Set User Password 1234aBcD Front Panel Lockout Enabled Disabled Enabled amp Activated Enabled amp Deactivated Disabled amp Activated Disabled amp Deactivated gt TPM Administrative Control No Operation Turn On Turn Off Clear Ownership TPM State Figure 32 Setup Utility Securit
168. rage Mode Matrix SW RAID Intel Embedded Server RAID Technology II ESRTII RAID RAID Storage Storage Description RAID Types and Driver Management Software Compatible Controller Mode Levels Supported User s Backplane Software Guide nbi AA Chipset driver or nboar operating system AXX6DRV3GR Controller Enhanced 6 STANTON QE N A oe aan N A N A ICH10R Native mode AXX4DRV3GR Broad OS support 6 SATA ports port Chipset driver or us 0 1 2 3 at IDE operating system Compatibility Legacy mode port N A embedded N A N A 4 5 at Native mode Broad OS support 6 SATA ports using AHCI driver or OS AHCI the Advanced Host N A embedded N A N A Controller Interface Broad OS support 40 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture RAID RAID Storage Storage Description RAID Types and Driver Management Software Compatible Controller Mode Levels Supported Software User s Backplane Guide SW RAID 0 1 10 ESRTII Driver standard SW RAID 6 SATAP oe Intel RAID Ge orts SW RAID 5 with Windows and Web Console2 Software optional selected Linux User s Guide AXXRAKSW5 Versions only Select in BIOS Setup SATA Mode Option on Advanced Mass Storage Controller Configuration Screen Revision 1 2 Intel order number E39529 009 41 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 4 2 USB 2 0 Supp
169. rder number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Design and Environmental Specifications 9 4 6 Capacitive Loading The power supply should be stable and meet all requirements within the following capacitive loading range Table 76 Capacitive Loading Conditions Output Minimum Maximum Units 3 3V 250 6800 uF 5V 400 4700 uF 12V1 12V2 12V3 12V4 500 each 11 000 uF 12V 1 350 uF 5VSB 20 350 uF 9 4 7 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in the following table This is measured over a bandwidth of 0 Hz to 20 MHZ at the power supply output connectors A 10 uF tantalum capacitor in parallel with a 0 1 uF ceramic capacitor are placed at the point of measurement Table 77 Ripple and Noise 3 3V 5V 412V1 12V2 12V3 12V4 12V 5 VSB 50mVp p 50 mVp p 120 mVp p 120 mVp p 50 mVp p 9 4 8 Timing Requirements The following are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tvout rise within 5 ms to 70 ms 5 VSB is allowed to rise from 1 0 ms to 25 ms 3 3 V 5 V and 12 V output voltages should start to rise approximately at the same time All outputs must rise monotonically Each output voltage should reach regulation within 50 ms Tvout_on of each other during turn on of the power supply Each output voltage should fall out of regulation within 400 msec Tu or of each oth
170. red Power down the server Open the chassis and move the jumper back to its default position covering pins 1 and Close the server chassis Power up the server The password is now cleared and you can reset it by going into the BIOS setup 118 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Jumper Blocks 7 2 Force BMC Update Procedure When performing a standard BMC firmware update procedure the update utility places the BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event the BMC firmware update process fails due to the BMC not being in the proper update state the server boards provide a Force BMC Update jumper J1H 1 that forces the BMC into the proper update state In the event the standard BMC firmware update process fails complete the following procedure 1 Power down and remove the AC power cord Open the server chassis See your server chassis documentation for instructions Move the jumper J1H1 from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 Close the server chassis Reconnect the AC power cord and power up the server Perform the BMC firmware update procedure as documented in the Update Instruction txt file included in the given BMC firmware update package After successful completion of the firmware update process the firmware update utility may gen
171. rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Server Boards S5520HC and S5500HCV may contain design defects or errors known as errata which may cause the product to deviate from published specifications Refer to the Intel Server Boards S5520HC and S5500HCV Specification Update for published errata Intel Corporation server baseboards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright O Intel Corpora
172. rflow direction as shown in the following figure when installing in a compatible Intel Server Chassis Revision 1 2 Intel order number E39529 009 149 Appendix B Compatible Intel amp Server Chassis Intel amp Server Board S5520HC S5500HCV TPS CPU Fan Air Flow Air Flow D saae DC DOL nnanon oe o foo Figure 56 Active Processor Heatsink Installation Requirement Revision 1 2 150 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Appendix C BMC Sensor Tables Appendix C BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose See the ntelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information Sensor Type The Sensor Type references the values in the sensor type codes table in the ntelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information Event Reading Type The event reading type references
173. rial Over LAN Serial Presence Detect Serial Peripheral Interface uge UseDaayamPotd SSCS URS Unified Retention System SSCS USB UmvmaSealBu SCS Universal time coordinate Vi Video Graphic Array 176 Revision 1 2 Intel order number E39529 009 R R R A B D I P U U U U AS OM TC S DR EL ES MI MS OL PD PI PS SD D P M S DP RS SB TC GA Intel amp Server Board S5520HC S5500HCV TPS Glossary XD bit Execute Disable Bit Revision 1 2 177 Intel order number E39529 009 Reference Documents Intel amp Server Board S5520HC S5500HCV TPS Reference Documents See the following documents for additional information Intel Server Boards S5520HC and S5500HCV Specification Update 178 Revision 1 2 Intel order number E39529 009
174. rs passwords and sessions are not supported over LDAP A user can configure LDAP usage through the embedded web server for authentication of future embedded web sessions Note Supports LDAP for Linux only 60 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Platform Management 4 3 Platform Control This server platform has embedded platform control which is capable of automatically adjusting system performance and acoustic levels Performance Performance Management Throttling Integrated Acoustic Control Thermal Management Monitoring Fan Speed Control Platform control optimizes system performance and acoustics levels through Performance management Performance throttling Thermal monitoring Fan speed control Acoustics management The platform components used to implement platform control include Integrated baseboard management controller Platform sensors Variable speed system fans System BIOS BMC firmware Sensor data records as loaded by the FRUSDR Utility Memory type Revision 1 2 61 Intel order number E39529 009 Platform Management Intel Server Boards S5520HC and S5500HCV TPS 4 3 1 Memory Open and Closed Loop Thermal Throttling Open Loop Thermal Throttling OLTT Throttling is a solution to cool the DIMMs by reducing memory traffic allowed on the memory bus which reduces power consumption and thermal output With OLTT the sys
175. rty chassis obt SCH 04 LAN leash specific lost Chassis i Physical Security Intrusion is Physical Sensor Critical Sensor 00 Front panel Interrupt Specific NMI diagnostic Trig Offset 13h 6Fh interrupt FP Interrupt Chassis FP NMI Diag Int specific Digital SMI Timeout SMI Timeout 3 Z SE pore Trig Offset asserted SMI Timeout F3h 03h System Event Lo Sei Sensor y 9 gging Specific 02 Log area System Event Log Disabled GER reset cleared 10h Trig Offset 154 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Appendix C BMC Sensor Tables Readabl Contrib To Assert e System De Status assert Value Offsets Full Sensor Name Platform Event Offset E Sensor Type Readin i Sensor name in SDR Applicability P 9 Triggers System Sensor Event Specific 04 PEF action OK 12h 6Fh System Event Reg ri se System Event g nc Ec i i E u I c nc Degraded BB 1 1V IOH BB 1 1V IOH c Non fatal All All Volt Threshold Gre oltage resho Dearaded All 02h 01h u 1 cnc 9 c Non fatal Volt Threshold bap oltage resho Dearaded All 02h 01h u I c nc 9 c Non fatal Volt Threshold b oltage resho Dearaded All 02h 01h u I cnc 9 c Non fatal BB 1 1V P1 Vccp BB 1 1V P1 Vecp 08h 10h BB 1 1V P2 Vccp BB 1 1V P2 Vecp BB 1 5V P1 DDR3 BB 1 5V P1 DDR3 BB 1 5V P2 DDR3 BB 1 5V P2 DDR3 B
176. s as follows Logs the error into the system event log SEL Alerts the Integrated BMC about the configuration error Does not disable the processor Displays 0194 Processor 0x family mismatch detected message in the Error Manager Halts the system and will not boot until the fault condition is remedied The BIOS detects the stepping difference and responds as follows Checks to see whether the steppings are compatible typically one stepping If so no error is generated this is not an error condition Continues to boot the system successfully Otherwise this is a stepping mismatch error and the BIOS responds as follows Displays 0193 Processor 0x stepping mismatch message in the Error Manager and logs it into the SEL Takes Minor Error action and continues to boot the system The BIOS detects the error condition and responds as follows Logs the error into the SEL Alerts the Integrated BMC about the configuration error Does not disable the processor Displays 0192 Processor 0x cache size mismatch detected message in the Error Manager Halts the system and will not boot until the fault condition is remedied The BIOS detects the error condition and responds as follows Adjusts all processor frequencies to the highest common frequency No error is generated this is not an error condition Continues to boot the system successfully If the frequencies for all processors cannot be adjusted to b
177. s being within regulation Time all output voltages stay within regulation after loss of AC Delay from loss of AC to de assertion of PWOK Delay from PSON active to output voltages within regulation limits Delay from PSON deactivate to PWOK being de asserted Delay from output voltages within regulation limits to PWOK asserted at turn on Delay from PWOK de asserted to output voltages 3 3 V 5 V 12 V and 12 V dropping out of regulation limits Duration of PWOK being in the de asserted state during an off on cycle using AC or the PSON signal Delay from 5 VSB being in regulation to O Ps being in regulation at AC turn on Time the 5 VSB output voltage stays within regulation after loss of AC Tpwok_low gt le Tpwok_off Tpwok_on e To on delay Tpwok_holdup je j Tsb_vout T5vsB_holdup Minimum N A N A 21 20 5 100 100 50 70 Maximum 1500 2500 N A N A 400 50 500 N A N A 1000 N A K Revision 1 2 AC turn on off cycle __ Figure 55 Turn On Off Timing Power Supply Signals Intel order number E39529 009 Tpson on delay j PSON turn on off cycle gt Design and Environmental Specifications Units ms ms ms ms ms ms ms ms ms ms ms E Tpowok ort Tpson_pwok 135 Design and Environmental Specifications Intel Server Board S5520HC S5500HCV T
178. se Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits 9 2 MTBF The following is the calculated Mean Time Between Failures MTBF 30 C ambient air These values are derived using a historical failure rate and multiplied by factors for application electrical and or thermal stress and for device maturity You should view MTBF estimates as reference numbers only e Calculation Model Telcordia Issue 1 method case 3 e Operating Temperature Server in 30 C ambient air Revision 1 2 127 Intel order number E39529 009 Design and Environmental Specifications Intel amp Server Board S5520HC S5500HCV TPS e Operating Environment Ground Benign Controlled e Duty Cycle 100 e Quality Level II Table 71 MTBF Estimate S5520HC MTBF S5500HCV MTBF Ambient Air Temperature Air Temp at Board for 10 9C rise hours hours eC eC 79 000 89 000 45 55 99 000 111 000 40 50 124 000 140 000 35 45 158 000 178 000 30 40 201 000 227 000 25 35 128 Revision 1 2 Intel order number E39529 009 Intel Server Board S5520HC S5500HCV TPS Design and Environmental Specifications 9
179. sion 1 2 99 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS 5 3 2 6 6 Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices To access this screen from the Main screen select Boot Options Network Device Order Boot Options Network Device 1 Available Network devices Network Device 2 lt Available Network devices gt Figure 42 Setup Utility Network Device Order Screen Display Table 40 Setup Utility Network Device Order Fields Setupitem Options HepTet Commens Network Device 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Network Device 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 7 BEV Device Order Screen The BEV Device Order screen allows the user to control the BEV bootable devices To access this screen from the Main screen select Boot Options gt BEV Device Order Boot Options BEV Device 1 lt Available BEV devices gt BEV Device 2 lt Available BEV devices gt Figure 43 Setup Utility BEV Device Order Screen Display 100 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Table 41 Setup Utility BEV Device Order Fields _ Set
180. ssible DDR3 DIMM configurations were validated due to the large number of possible configuration combinations Supported configurations are highlighted in light gray in Tables 5 and 6 Validated These configurations have received broad validation by Intel Intel can provide customers with information on specific configurations that were validated Validated configurations are highlighted in dark gray in Tables 5 and 6 All populated DIMMs are identical The following is a description of the columns in Tables 5 and 6 36 X Indicates the DIMM is populated M Indicates whether the configuration supports the Mirrored Channel mode of operation It is one of the following Y indicating Yes N indicating No Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture N Identifies the total number of DIMMs that constitute the given configuration Table 5 Supported DIMM Population under the Dual Processors Configuration N CPU1 Socket Populated CPU2 Socket Populated M Al A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 1 1 X N ES Ten roe rr voe ee intem e ue ENT 3 2 X X N 5 3 X X X N 6 3 x X X N 7 3 x X X 8 4 X X X X N KIEA E A een em e E 10 6 X X X X X X Y 12 7 X X X X X X X N EE en Ph PA Pa a ea ee fe TT 14 8 X X X X X X X X N EAA fg 12 x X X N o x x x x x x x x x
181. stic LED Decoder Progress Code Progress Code Definition USB 0x58 Resetting USB bus 0x59 Reserved for USB devices ATA ATAPI SATA 0x5A Resetting SATA bus and all devices 0x5B Reserved for ATA SMBUS 0x5C Resetting SMBUS 0x5D Reserved for SMBUS Local Console 0x70 Resetting the video controller VGA 0x71 Disabling the video controller VGA 0x72 Enabling the video controller VGA Remote Console 0x78 Resetting the console controller 0x79 Disabling the console controller Ox7A Enabling the console controller Keyboard only USB 0x90 Resetting the keyboard 0x91 Disabling the keyboard 0x92 Detecting the presence of the keyboard 0x93 Enabling the keyboard 0x94 Clearing keyboard input buffer 0x95 Instructing keyboard controller to run Self Test PS 2 only Mouse only USB 0x98 Resetting the mouse 0x99 Detecting the mouse Ox9A Detecting the presence of mouse Ox9B Enabling the mouse Fixed Media OxBO Resetting fixed media device OxB1 Disabling fixed media device 0xB2 Detecting the presence of a fixed media device hard drive detection etc 0xB3 Enabling configuring a fixed media device Removable Media Revision 1 2 Intel order number E39529 009 165 Appendix E POST Code Diagnostic LED Decoder Intel Server Board S5520H
182. t dropout 1 5 4 4 Power control fault power good assertion timeout Power unit soft power control failure offset Revision 1 2 171 Intel order number E39529 009 Appendix G Installation Guidelines Intel Server Board S5520HC S5500HCV TPS Appendix G Installation Guidelines 1 Drivers for Sun Solaris 10 U5 05 08 Device Description Chipset No driver required under Sun Solaris Enhanced SATA mode Onboard SATA No driver required under Sun Solaris AHCI Onboard SATA No driver required under Sun Solaris Onboard NIC Intel amp 82575EB No driver required under Sun Solaris AXX4SASMOD Native SAS pass through mode No driver required under Sun Solaris AXXROMBSASMR Driver is available from http support intel com support motherboards server S5520HC ESRTII Onboard SATA AXX4SASMOD Not currently supported under Sun Solaris Onboard Video ServerEngines No driver required under Sun Solaris Intel amp Hot Swap Hard Drive back plane No driver required under Sun Solaris 2 Sun Solaris 10 U5 05 08 hangs during early boot when EHCI 2 is enabled Description Sun Solaris 10 U5 may hang during early boot in the Intel Server Board S5520HC or S5500HCV when USB 2 0 is Enabled Guideline Disable USB 2 0 Controller option in BIOS Setup Menu or follow the instructions listed at the following website in order to accomplish this http bugs opensolaris org view bug do bug id 6681221
183. t Not Information only This field is Installed unavailable when RAID Mode is Drive enabled information gt SATA Port 2 lt Not Information only This field is Installed unavailable when RAID Mode is Drive enabled information gt SATA Port 3 lt Not Information only This field is Installed unavailable when RAID Mode is Drive enabled information gt SATA Port 4 lt Not Information only This field is Installed unavailable when RAID Mode is Drive enabled information gt SATA Port 5 lt Not Information only This field is Installed unavailable when RAID Mode is Drive enabled information gt Revision 1 2 81 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS 5 3 2 2 4 Serial Ports Screen The Serial Ports screen allows the user to configure the Serial A COM 1 and Serial B COM2 ports To access this screen from the Main screen select Advanced gt Serial Port Advanced Serial Port Configuration Serial A Enable Enabled Disabled Address 3F8h 2F8h 3E8h 2E8h IRQ 3or4 Serial B Enable Enabled Disabled Address 3F8h 2F8h 3E8h 2E8h IRQ 3or4 Figure 28 Setup Utility Serial Port Configuration Screen Display Table 26 Setup Utility Serial Ports Configuration Screen Fields Setup Item Help Text Enable or Disable Serial port A Options Serial A Enabled Enable Disabled Address Select Serial port A base I O address Sel
184. t if the USB Controller is disabled Grayed out if the USB Controller is disabled Hidden if no USB Mass storage devices are installed Grayed out if the USB Controller is disabled This setup screen can show a maximum of eight devices on this Screen If more than eight devices are installed in the system the USB Devices Enabled displays the correct count but only the first eight devices can display here Grayed out if the USB Controller is disabled Revision 1 2 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 2 6 PCI Screen The PCI Screen allows the user to configure the PCI add in cards onboard NIC controllers and video options To access this screen from the Main screen select Advanced PCI Advanced PCI Configuration Maximize Memory below 4GB Enabled Disabled Memory Mapped I O above 4GB Enabled Disabled Onboard Video Enabled Disabled Dual Monitor Video Enabled Disabled Onboard NIC1 ROM Enabled Disabled Onboard NIC2 ROM Enabled Disabled Onboard NIC iSCSI ROM Enabled Disabled NIC 1 MAC Address MAC gt NIC 2 MAC Address MAC gt Figure 30 Setup Utility PCI Configuration Screen Display Table 28 Setup Utility PCI Configuration Screen Fields Setupltem Options Help Text Commens Maximize Memory Enabled BIOS maximizes memory usage below 4GB for an below 4GB Disabled OS without PAE support depending on
185. ta between participant ranks Channel Interleaving Interleave between channel when not in Mirrored Channel Mode Socket Interleaving Interleaved memory can spread between both CPU sockets when NUMA mode is disabled given both CPU sockets are populated and DDR3 DIMMs are installed in slots for both sockets 3 3 6 Memory Test 3 3 6 1 Integrated Memory BIST Engine The Intel Xeon Processor 5500 series incorporate an integrated Memory Built in Self Test BIST engine enabled to provide extensive coverage of memory errors at both the memory cells and the data paths emanating from the DDR3 DIMMs The BIOS also uses the Memory BIST to initialize memory at the end of the memory discovery process 3 3 7 Memory Scrub Engine The Intel Xeon Processor 5500 Series incorporates a memory scrub engine which performs periodic checks on the memory cells and identifies and corrects single bit errors Two types of scrubbing operations are supported Demand scrubbing Executes when an error is encountered during normal read write of data Patrol scrubbing Proactively walks through populated memory space seeking soft errors The BIOS enables both demand scrubbing and patrol scrubbing by default Demand scrubbing is not possible when memory mirroring is enabled Therefore if the memory is configured for mirroring the BIOS disables it automatically 3 3 8 Memory RAS 3 3 8 1 RAS Features The Intel Server Boards S5520HC an
186. tem throttles in response to memory bandwidth demands instead of actual memory temperature Since there is no direct temperature feedback from the DDR3 DIMMs the throttling behavior is preset rather than conservatively based on the worst cooling conditions for example high inlet temperature and low fan speeds Additionally the fans that provide cooling to the memory region are also set to conservative settings for example higher minimal fan speed OLTT produces a slightly louder system than CLTT because minimal fan speeds must be set high enough to support any DDR3 DIMMs in the worst memory cooling conditions Closed Loop Thermal Throttling CLTT CLTT works by throttling the DDR3 DIMMs response directly to memory temperature via thermal sensors integrated on the Serial Presence Detect SPD of the DDR3 DIMMs This is the preferred throttling method because this approach lowers limitations on both memory power and thermal threshold therefore minimizing throttling impact on memory performance This reduces the utilization of high fan speeds because CLTT does not have to accommodate for the worst memory cooling conditions with a higher thermal threshold CLTT enables memory performance to achieve optimal levels 4 3 2 Fan Speed Control BIOS and BMC software work cooperatively to implement system thermal management support During normal system operation the BMC will retrieve information from the BIOS and monitor several platform thermal sens
187. ting limits due to unknown variables associated with the given chassis and its fans Therefore regardless of whether the system is configured for Performance Mode or Acoustics Mode the system fans will always run at 100 operating levels providing for maximum airflow In this scenario the Performance and Acoustic mode settings only affect the allowable performance of the memory higher BW for the Performance mode 64 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Platform Management 4 4 Intel Intelligent Power Node Manager Intel Intelligent Power Node Manager is a platform system level solution that provides the system with a method of monitoring power consumption and thermal output and adjusting system variables to control those factors The BMC supports Intel Intelligent Power Node Manager specification version 1 5 Additionally the platform must have an Intel Intelligent Power Node Manager capable Manageability Engine ME firmware installed The BMC firmware implements power management features based on the Power Management Bus PMBus 1 1 Specification Note Intelligent Power Node Manager is only available on platforms that support PMBus compliant power supplies 4 4 1 Manageability Engine ME An embedded ARC controller is within the IOH providing the Intel Server Platform Services SPS The controller is also commonly referred to as the Manageability Engine ME The
188. tion 2008 2009 Revision 1 2 iii Intel order number E39529 009 Table of Contents Intel Server Boards S5520HC and S5500HCV TPS Table of Contents TEE Idee Ee Un EE 1 1 1 Chapter Outline o certet ERR re FEE AAEN EA AAA EE EX EUR e IA EUR 1 1 2 Server Board Use Disclaimer 1 2 OVONVICW E E 2 2 1 Intel Server Boards S5520HC and S5500HCV Feature Set 2 The PCI Express Gen 1 slot x8 Mechanically x4 Electrically is not available when the SAS module slot is in use and vice versa Server Board Layout 4 Server Board e 5 2 1 1 Server Board Connector and Component Layout 5 2 1 2 Server Board Mechanical Drawings cccccccececeeeeeeeceeeeeeeeeeeeaeaeeeeeeeeeeeeeeeeeeeetenes 8 2 1 3 Server Board Rear I O Layout 16 3 Functional ArchitectUre c geet nire rena cuo rnb n pee Fa a Ine EES EE REDE eye Ype Gaius a iUa 17 3 1 Intel 5520 and 5500 I O Hub OH 20 3 1 1 Intel QuickPath nter eoHfe6t oe Dato D re e e a dde Di edu 20 3 1 2 PCI Express Ports ite iet eet hte does Dee aee e asad ENEE e eee rt ent xe ep aua 20 3 1 3 Enterprise South Bridge Interface EI 21 3 1 4 Manageability Engine ME 21 3 1 5 Controller Link CL tere va feet caine zr eee a e e Oe M eta LA BR DRE MEE EE 21 3 2 tele elen EE ER 3 2 1 Processor Population Rules 20 ccccccccceceeeeeeeeeeeeteseeeeececeeaeaeaaeaeaeeeeeeeeeeeeeeeetenes 22 3 2 2 Mixed Processor Configura
189. tions cccccccececeeeeeeeeeeeeeeeeeceeeeaeaaeaeaeeeeeeeeeeeeeeeeeetes 22 3 23 Intel Hyper Threading Technology Intel HT 24 3 2 4 Enhanced Intel SpeedStep Technology EIST 24 3 2 5 Intel Turbo Boost Technology cosi tete ina Leen Van EE 24 3 2 6 Execute Disable Bit Feature EE 24 3 2 7 Core Multi Processihg e rotor treiber eene pce e a nde vede calo Aree des 24 3 2 8 Direct Cache Access DCA EE 25 3 2 9 Unified Retention System Support 25 3 3 Memory Subsystem E 26 3 3 1 Memory Subsystem Nomenclature 26 3 3 2 ee Bue 28 3 3 3 Processor Cores QPI Links and DDR3 Channels Frequency Configuration 29 do Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Table of Contents 3 3 4 Publishing System Memory ssssssssseee eee enne nnns 32 3 3 5 Memory Interleaving A 32 3 3 6 ISRAEL EE 33 3 3 7 Memory Scrub ul LTE 33 3 3 8 Memory RASH p 33 3 3 9 Memory Population and Upgrade Hules sneneeneneeeeeereeeeeererereteterrrnrnrnrnnneseeeene 34 3 3 10 Supported Memory Configuration enne 36 3 3 11 Memory Error Handling 38 3 4 eeh TEE 39 3 4 1 Serial ATA SUPPO cicuta ect ee eoo rep ree te ee o nre AE eaae 39 3 4 2 USB 20 lee e EE 42 3 5 PGI Ke 43 3 5 1 PCI Express Riser Slot 85520HC Glorp 44 3 6 Intel SAS Entry RAID Module AXX4SASMOD Optional Accessory 46 3 6 1 NEE len EE 47 3 7 Baseboard Management Contr
190. ts entry hardware RAID 0 RAID 1 and RAID 1E and native SAS pass thorugh mode 3 6 1 2 Intel ESRTII Mode The Intel Embedded Server RAID Technology II Intel ESRTII feature provides RAID modes 0 1 and 10 If RAID 5 is needed with Intel ESRTII you must install the optional Intel RAID Activation Key AXXRAKSWS accessory This activation key is placed on the SAS Software RAID 5 connector located on the Intel SAS Entry RAID Module AXX4SASMOD For installation instructions see the documentation included with the SAS Module AXX4SASMOD and the activation key When Intel Embedded Server RAID Technology II is enabled with the SAS Module AXX4SASMOD enclosure management is provided through the SAS_SGPIO or SES connector on the SAS Module AXX4SASMOD when a cable is attached between this connector and the backplane or DC interface 48 Intel order number E39529 009 Revision 1 2 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture 3 7 Baseboard Management Controller The Intel Server Boards S5520HC and S5500HCV have an integrated BMC controller based on ServerEngines Pilot Il The BMC controller is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI based server management The following is a summary of the BMC management hardware features used by the BMC 250 MHz 32 bit ARM9 Processor Memory Management Unit MMU Two 10 100 Ethernet Controllers w
191. tsink provides the necessary compressive load for the thermal interface material TIM All components of the URS heatsink solution are captive to the heatsink and only require a Phillips screwdriver to attach to the Unified Backplate Assembly See the following figure for the stacking order of URS components The Unified Backplate Assembly is removable allowing for the use of non Intel heatsink retention solutions SCREW HEATSINK COMPRESSION SPRING Y w RETENTION CUP dut g ON MOSS nette d h Ir e TIM ILM amp SOCKET MOTHERBOARD ILM ATTACH STUDS HEATSINK ATTACH STUDS UNIFIED BACK PLATE ES Figure 15 Unified Retention System and Unified Back Plate Assembly Revision 1 2 25 Intel order number E39529 009 Functional Architecture Intel Server Boards S5520HC and S5500HCV TPS 3 3 Memory Subsystem The Intel Xeon Processor 5500 Series on the Intel Server Boards S5520HC and S5500HCV are populated on CPU sockets Each processor installed on the CPU socket has an integrated memory controller IMC which supports up to three DDR3 channels and groups DIMMs on the server boards into autonomous memory 3 3 1 Memory Subsystem Nomenclature The nomenclature for DIMM sockets implemented in the Intel Server Boards S5520HC and S5500HCV is represented in the following figures e DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets e The memory channe
192. unctionality The BMC supports storage and access of system SDRs Sensor device and sensor scanning monitoring The BMC provides IPMI management of sensors It polls sensors to monitor and report system health PMl interfaces Host interfaces include system management software SMS with receive message queue support and server management mode SMM IPMB interface LAN interface that supports the IPMI over LAN protocol RMCP RMCP Serial over LAN SOL ACPI state synchronization The BMC tracks ACPI state changes provided by the BIOS BMC Self test The BMC performs initialization and run time self tests and makes results available to external entities See also the ntelligent Platform Management Interface Specification Second Generation v2 0 4 1 2 Non IPMI Features The BMC supports the following non IPMI features This list does not preclude support for future enhancements or additions Jjn circuit BMC firmware update Fault resilient booting FRB FRB2 is supported by the watchdog timer functionality Revision 1 2 55 Intel order number E39529 009 Platform Management Intel Server Boards S5520HC and S5500HCV TPS Chassis intrusion detection dependant on platform support Basic fan control using TControl version 2 SDRs Fan redundancy monitoring and support Power supply redundancy monitoring and support Hot swap fan support Acoustic management Supports multiple fan profiles
193. until the error is resolved and Press F2 to enter setup regardless of if the Post Error Pause setup option is enabled or disabled After entering setup the error message displays on the Error Manager screen and an error is logged to the System Event Log SEL with the error code The system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system e Pause If the Post Error Pause setup option is enabled the system goes directly to the Error Manager screen to display the error and log the error code to SEL Otherwise the system continues to boot and no prompt is given for the error although the error code is logged to the Error Manager and in a SEL message e Minor The message is displayed on the screen or on the Error Manager screen The system continues booting in a degraded state regardless of if the Post Error Pause setup option is enabled or disabled The user may want to replace the erroneous unit 22 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Functional Architecture Processor family not identical Processor stepping mismatch Processor cache not identical Processor frequency speed not identical Processor Intel amp QuickPath Interconnect speeds not identical Revision 1 2 Table 2 Mixed Processor Configurations Eror Severity System Action The BIOS detects the error condition and respond
194. upltem Options Help Text BEV Device 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group BEV Device 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 7 Boot Manager Screen The Boot Manager screen allows the user to view a list of devices available for booting and to select a boot device for immediately booting the system To access this screen from the Main screen select Boot Manager Main Advanced Security Server Management Boot Options Boot Manager Internal EFI Shell lt Boot device 1 gt lt Boot Option x gt Figure 44 Setup Utility Boot Manager Screen Display Table 42 Setup Utility Boot Manager Screen Fields Setup Item Internal EFI Shell Help Text Comments Select this option to boot now Note This list is not the system boot option order Use the Boot Options menu to view and configure the system boot option order Select this option to boot now Note This list is not the system boot option order Use the Boot Options menu to view and configure the system boot option order Boot Device x Revision 1 2 101 Intel order number E39529 009 BIOS Setup Utility Intel Server Board S5520HC S5500HCV TPS 5 3 2 8 Error Manager Screen The Error Manager screen displays any errors encountered during POST Error Manager ERRO
195. user password This option is only to control access to the setup Administrator has full access to all the setup items Clearing the Administrator password also clears the user password Available only if the administrator password is installed This option only protects the setup User password only has limited access to the setup items Information only Shows the current TPM device state A disabled TPM device does not execute commands that use the TPM functions and TPM security operations are not available An enabled and deactivated TPM is in the same state as a disabled TPM except setting of the TPM ownership is allowed if not present already An enabled and activated TPM executes all commands that use the TPM functions and TPM security operations are also available Revision 1 2 Intel amp Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility Help Text Comments Administrative No Operation No Operation No changes to Control current state Turn Off Turn On Enables and activates TPM Turn Off Disables and deactivates TPM Clear Ownership Removes the TPM ownership authentication and returns the TPM to a factory default state Note The BIOS setting returns to No Operation on every boot cycle by default Not Available in Intel Server Boards 85520HC and S5500HCV which have no TPM Grayed out at No Operation state in Intel Server Boards S5520HC and S
196. ut PS2 Curr Out Power Supply 1 Temperature Chassis specific Chassis specific Chassis specific PS1 Temperature P Power Supply 2 Temperature Chassis specific PS2 Temperature Processor 1 Status P1 Status Dual processor only Processor 2 Status P2 Status Processor 1 Thermal Margin P1 Therm Margin Processor 2 Thermal Margin P2 Therm Margin Dual processor only Revision 1 2 nc Threshold Degraded o c Non fatal 03h nc Current Threshold u c nc Degraded Ge c Non fatal nc Threshold u c nc Degraded m c Non fatal Event Data Analog R T Current De Analog R T As and Temperature E As and Analog R T 01h De Threshold bo Temperature u c nc Degraded 01h c Non fatal As and 01 Thermal trip As and De Trig Offset 07 Presence OK 01 Thermal trip A d DS Trig Offset 07 Presence OK e Sensor Specific 6Fh Processor 07h Processor 07h Temperature 01h Sensor Specific 6Fh Threshold Oth Threshold Oth Intel order number E39529 009 Temperature 01h 159 Appendix C BMC Sensor Tables Intel Server Board S5520HC S5500HCV TPS Readabl Full Sensor Name Platform Event Event Offset Contrib To Assert e Tn Sensor Type Reading e System De Sensor name in SDR Applicability Type Triggers Status assert Value Offsets Processor 1 Thermal Temperature Threshold Control 96 All Non fatal
197. y The BIOS uses options set in the F2 BIOS Setup Utility to determine what fan profile the system should operate under These options include THROTTLING MODE ALTITUDE and SET FAN PROFILE Refer to Section 5 3 2 2 7 System Acoustic and Performance Configuration for details of the BIOS options The ALTITUDE option is used to determine appropriate memory performance settings based on the different cooling capability at different altitudes At high altitude memory performance must be reduced to compensate for thinner air Be advised selecting an Altitude option to a setting that does not meet the operating altitude of the server may limit the system fans ability to provide adequate cooling to the memory If the air flow is not sufficient to meet the needs of the server even after throttling has occurred the system may shut down due to excessive platform thermals By default the Altitude option is set to 301 m 900 m which is believed to cover the majority of the operating altitudes for these server platforms You can set the SET FAN PROFILE option to either the Performance mode Default or Acoustics mode Refer to the following sections for details describing the differences between each mode Changing the fan profile to Acoustics mode may affect system performance The SET FAN PROFILE BIOS option is hidden when CLTT is selected as the THROTTLING MODE option Revision 1 2 63 I
198. y Configuration Screen Display Revision 1 2 87 Intel order number E39529 009 BIOS Setup Utility Administrator Password Status User Password Status Set Administrator Password Set User Password Front Panel Lockout TPM State 88 Installed Not Installed Installed Not Installed 123aBcD 123aBcD Enabled Disabled Enabled and Activated Enabled and Deactivated Disabled and Activated Disabled Deactivated and Intel amp Server Board S5520HC S5500HCV TPS Help Text Administrator password is used to control change access in BIOS Setup Utility Only alphanumeric characters can be used Maximum length is 7 characters It is case sensitive Note Administrator password must be set in order to use the user account User password is used to control entry access to BIOS Setup Utility Only alphanumeric characters can be used Maximum length is 7 characters It is case sensitive Note Removing the administrator password also automatically removes the user password If enabled locks the power button and reset button on the system s front panel If Enabled is selected power and reset must be controlled via a system management interface Intel order number E39529 009 Table 30 Setup Utility Security Configuration Screen Fields Comments Information only Indicates the status of the administrator password Information only Indicates the status of the
199. y N Y N Y Y Support 162 Revision 1 2 Intel order number E39529 009 Intel amp Server Board S5520HC S5500HCV TPS Appendix E POST Code Diagnostic LED Decoder Appendix E POST Code Diagnostic LED Decoder During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process you can use the Diagnostic LEDs to identify the last POST process executed Each POST code is represented by eight amber Diagnostic LEDs The POST codes are divided into two nibbles an upper nibble and a lower nibble The upper nibble bits are represented by Diagnostic LED s 4 5 6 and 7 The lower nibble bits are represented by Diagnostics LED s 0 1 2 and 3 If the bit is set in the upper and lower nibbles the corresponding LED lights up If the bit is clear the corresponding LED is off Diagnostic LED 7 is labeled MSB Most Significant Bit and Diagnostic LED 0 is labeled LSB Least Significant Bit YY eoo Q o e 00000 d O A Doue MSB LED E Diagnostic LED 3 B Diagnostic LED 6 F Diagnostic LED 2 C Diagnostic LED 5 G Diagnostic LED 1 D Diagnostic LED 4
200. ys on the web browser attempting to launch more than two KVM sessions The default inactivity timeout is 30 minutes but you may change the default through the embedded web server Remote KVM activation does not disable the local system keyboard video or mouse Unless the feature is disabled locally remote KVM is not deactivated by local system input KVM sessions will persist across system reset but not across an AC power loss 4 2 3 Media Redirection The embedded web server provides a Java applet to enable remote media redirection You may use this in conjunction with the remote KVM feature or as a standalone applet The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD ROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears as a local device to the server allowing system 58 Revision 1 2 Intel order number E39529 009 Intel amp Server Boards S5520HC and S5500HCV TPS Platform Management administrators or users to boot the server or install software including operating systems copy files update the BIOS and so forth or boot the server from this device The following capabilities are supported The operation of remotely mounted devices is independent of the local devices on the server Both remote and local devices are usable in parallel You can mount either IDE CD ROM floppy or USB devices as a remot
201. zation Technology for Directed I O is enabled ATS Support Enabled Enable Disable Intel VT d Address Only appears when Intel Disabled Translation Services ATS support Virtualization Technology for Directed I O is enabled Pass through Enabled Enable Disable Intel VT d Pass through Only appears when Intel Support Disabled DMA support Virtualization Technology for Directed I O is enabled Hardware Prefetcher Enabled Hardware Prefetcher is a speculative Disabled prefetch unit within the processor s Note Modifying this setting may affect system performance Adjacent Cache Line Enabled Enabled Cache lines are fetched in pairs Prefetch Disabled even line odd line Disabled Only the current cache line required is fetched Note Modifying this setting may affect system performance Direct Cache Access Enabled Allows processors to increase the I O DCA Disabled performance by placing data from I O devices directly into the processor cache 76 Revision 1 2 Intel order number E39529 009 Intel Server Boards S5520HC and S5500HCV TPS BIOS Setup Utility 5 3 2 2 2 Memory Screen The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed This screen also allows the user to open the Configure Memory RAS and Performance screen To access this screen from the Main screen select Advanced Memory Advanced Memory Configuration Total Memory Effective Memory

Intel S5500HCV

Contents

Download Pdf Manuals

Related Search

Related Contents