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Intel Atom Processor N270

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1. Symbol Parameter Min Typ Max Unit Figure Notes Vin Input High Voltage 1 15 V 7 8 Von Input Low Voltage 0 3 V 7 8 Vcnoss Crossing Voltage 0 3 0 55 V 2 7 9 AM cRoss Range of Crossing Points 140 mV 2 7 5 VswiNG Differential Output Swing 300 mV 6 lu Input Leakage Current 5 T5 HA 3 Cpad Pad Capacitance 1 2 1 45 2 0 pF 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing Voltage is defined as absolute voltage where rising edge of BCLKO is equal to the falling edge of BCLK1 3 For Vin between 0 V and Vin 4 Cpad includes die capacitance only No package parasitics are included 5 AVcnossis defined as the total variation of all crossing voltages as defined in note 2 6 Measurement taken from differential waveform 7 Measurement taken from single ended waveform 8 Steady state voltage not including Overshoots or Undershoots 9 Only applies to the differential rising edge BCLKO rising and BCLK1 falling Datasheet 29 intel Table 9 AGTL Signal Group DC Specifications Electrical Specifications Symbol Min Typ Max Unit Notes Vecp 1 0 Voltage 1 00 1 05 1 10 V GTLREF GTL Reference Voltage 2 3 Vcce V 6 Rcomp Compensation Resistor 27 23 27 5 27 78 Q 10 Ropr Termination Resistor 55 Q 11 Vin Input Hi
2. 4 2 Processor Pin out Assignment Figure are graphic representations of the processor pin out assignments Table 12 lists the pin out by signal name 34 Datasheet Package Mechanical Specifications and Pin I nformation Figure 6 Pin out Diagram Top View Left Side Datasheet 1 3 10 1 12 13 14 15 16 17 18 19 20 21 CORED RED 1 E CO SE ASV 2 es ASVD 3 18S SE NC NSE NC EQ B2 A 29 No 3 BPM B2 ABE ABI BPM_B3 PREQ B BPM BI A Br Abts REO BI nca NCS TRST B BPM 0 PRDY B A B14 s Nc7 WS ABI A B16 Ncc 10 TOK aP Bi ABIO A BS T ABB AB5 REQ BO REQ B3 ABB REQ BA A 86 BRIB 35 36 intel Package Mechanical Specifications and Pin I nformation Table 12 Pin out Arranged by Signal Name Signal Name Ball Signal Name Ball Signal Name Ball A 10 M19 A 7 J19 D 13 W13 A 11 H21 A 8 N19 D 14 AA9 A 12 L20 A 9 G20 D 15 W9 A 13 M20 A20M U18 D 16 AA5 A 14 K19 ACLKPH U5 D 17 Y8 A 15 J20 ADS V19 D 18 W3 A 16 L21 ADSTB 0 K20 D 19 U1 A 17 C19 ADSTB 1 B19 D 2 Y12 A 18 F19 BCLK 0 V11 D 20 W7 A 19 E21 BCLK 1 V12 D 21 W6 A 20 A16 BNR Y19 D 22 Y7 A 21 D19 BPM 0 K17 D 23 AA6 A 22 C14 BPM 1 J18 D 24 Y3 A 23
3. NOTES 1 This rating applies to the processor and does not include any tray or packaging 2 Contact Intel for storage requirements in excess of one year Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Chapter 4 for the pin signal definitions and signal pin assignments Most of the signals on the FSB are in the AGTL signal group The DC specifications for these signals are listed in Table 9 DC specifications for the CMOS group are listed in Table 10 Table 9 through Table 11 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages The Highest Frequency Mode HFM and Lowest Frequency Mode LFM refer to the highest and lowest core operating frequencies supported on the processor Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states Vcc goo is the default voltage driven by the voltage regulator at power up in order to set the VID values Unless specified otherwise all specifications for the processor are at T 90 C Note Care should be taken to read all notes associated with each parameter 26 Datasheet Electrical Specifications Table 7 Voltage and Current Specifications for the Processors
4. Symbol Parameter Min Typ Max Unit Notes FSB BCLK Frequency 132 63 133 33 133 37 MHz Frequency VccHFM Vcc at Highest Frequency Mode HFM AVID 1 10 V 1 2 11 VccLFM Vcc at Lowest Frequency Mode LFM 0 75 AVID V 1 2 Visa TEN Vcc Voltage for Initial Power ET 1 20 V 2 6 Vcce AGTL Termination Voltage 1 00 1 05 1 10 V Vcca PLL Supply voltage 1 425 1 5 1 575 V VccppnsiP Vcc at Deeper Sleep C4 0 75 1 0 V 1 2 Vccr Fuse Power Supply 1 00 1 05 1 10 V Icc for Processors Recommended Nu _ 4 0 A eum Design Target Estimated i Icc for Processors Processor l un Z E cc Number Core Frequency Voltage N270 1 6GHz 1 10V 3 A 3 4 lcc Auto Halt amp Stop Grant l AH HFM 1 6 GHz 1 10 Volts I por 2 2 A 3 4 l sont LFM 0 8 1 2 GHz 0 75 1 00 1 5 Volts lcc Deep Sleep sp HFM 1 6 GHz 1 10 Volts i 1 4 A At 50 C 3 4 LFM 0 8 GHz 0 75 1 00 Volts _ B 0 6 pensi Icc Deeper Sleep C4 0 2 A At 50 C 3 4 Vcc Power Supply Current Slew Rate _ u dl cc at at Processor Package Pin Estimated 2 adu 5 7 cca lcc for Veca Supply 130 mA ccp Icce before Vcc Stable 2 5 A 8 ccp Icce after Vcc Stable 1 5 A 9 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same f
5. I O D 63 0 Data are the data signals These signals provide a 64 bit data path between the FSB agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Quad Pumped Signal Groups Data Group DSTBN DSTBP DINV D 15 0 0 0 D 31 16 1 aL D 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high 42 Datasheet Package Mechanical Specifications and Pin I nformation Datasheet intel Signal Name Type Description DBSY 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the FSB to indicate that the data bus is in use The data bus is released after DBSY is de asserted This signal must connect the appropriate pins on both FSB agents DEFER DEFER is asserted by an agent to indicate that a transaction
6. See Section 4 2 for a pin listing of the processor and the location of all RSVD pins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active low AGTL inputs may be left as no connects if AGTL termination is provided on the processor silicon Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 These signals should be connected to the clock chip and the appropriate chipset on the platform The BSEL encoding for BCLK 1 0 is shown in Table 4 Table 4 BSEL 2 0 Encoding for BCLK Frequency Datasheet BSEL 2 BSEL 1 BSEL 0 BCLK Frequency L L H 133 MHz 23 intel 3 7 Electrical Specifications FSB Signal Groups To simplify the following discussion the FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timi
7. C18 BPM 2 H15 D 25 W2 A 24 C20 BPM 3 J15 D 26 V3 A 25 E20 BPRI U21 D 27 U2 A 26 4 D20 BRO T20 D 28 T3 A 27 B18 BR1 V15 D 29 AA8 A 28 C15 BSEL 0 J6 D 3 AA14 A 29 B16 BSEL 1 H5 D 30 V2 A 3 P21 BSEL 2 G5 D 31 WA A 30 B17 COMP 0 TI D 32 R3 A 31 C16 COMP 1 T2 D 33 R2 A 32 A17 COMP 2 F20 D 34 P1 A 33 B14 COMP 3 F21 D 35 N1 A 34 B15 D 0 Y11 D 36 M2 A 35 A14 D 1 W10 D 37 P2 A 4 H20 D 10 W15 D 38 J3 A 5 N20 D 11 AA13 D 39 N3 A 6 R20 D 12 Y16 D 4 AA11 Datasheet Package Mechanical Specifications and Pin I nformation Datasheet intel Signal Name Ball Signal Name Ball Signal Name Ball D 40 G3 DEFER T21 NC K4 D 41 H2 DINV 0 W16 NC K5 D 42 N2 DINV 1 Y6 NC M15 D 43 L2 DINV 2 L1 NC L16 D 44 M3 DINV 3 C5 PRDY3 K18 D 45 J2 DPRSTP R18 PREQ J16 D 46 H1 DPWR U4 PROCHOT G17 D 47 J1 DRDY T19 PWRGOOD V17 D 48 C2 DSTBN 0 Y14 REQ 0 N21 D 49 G2 DSTBN 1 Y4 REQ 1 J21 D 5 W12 DSTBN 2 K2 REQ 2 G19 D 50 F1 DSTBN 3 E2 REQ 3 P20 D 51 D3 DSTBP 0 Y15 REQ 4 R19 D 52 B4 DSTBP 1 Y5 RESET D15 D 53 E1 DSTBP 2 K3 RS 0 W18 D 54 A5 DSTBP 3 F3 RS 1 Y17 D 55 C3 FERR T16 RS 2 U20 D 56 A6 FOR
8. Leakage u _ lio Current 200 HA a Cpad Pad Capacitance 1 9 2 2 2 45 pF 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 Vccp 3 Vou is determined by value of the external pull up resistor to Vccp 4 For Vin between 0 V and Von 5 Cpad includes die capacitance only No package parasitics are included Datasheet m Package Mechanical Specifications and Pin Information In tel 4 Package Mechanical Specifications and Pin I nformation This chapter provides the package specifications pin out assignments and signal description 4 1 Package Mechanical Specifications The processor is available in 512 KB 437 pins in FCBGA8 package The package dimensions are shown in Figure Datasheet 33 intel 4 1 1 Package Mechanical Drawings Figure 5 Package Mechanical Drawing Package Mechanical Specifications and Pin I nformation 8 1 6 5 4 3 2 ca SIENTO THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS WAY NOT BE DISCLOSED REPRODUCED DISPLAYED O
9. N tel Table 10 Legacy CMOS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vece 1 0 Voltage 1 00 1 05 1 10 Vin Input High Voltage 0 7 Vccp Vccp VCCP 0 1 2 Input Low Voltage _ Vu CMOS 0 10 0 00 0 3 Vccp V 2 3 Von Output High Voltage 0 9 Vecp Vccp Vcce 0 1 2 Vo Output Low Voltage 0 10 0 0 1 Vccp 2 lou Output High Current 1 5 4 1 mA 5 lot Output Low Current 1 5 4 1 mA 4 Input Leakage lu Current E E SUP n 8 Cpad1 Pad Capacitance 1 6 2 1 2 55 pF 7 Pad Capacitance for Cpad2 CMOS Input 0 95 1 2 1 45 8 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies The Vccp referred to in these specifications refers to instantaneous Vccp 3 Reserved 4 Measured at 0 1 Vccp 5 Measured at 0 9 Vccp 6 For Vin between OV and Vccp Measured when the driver is tri stated 7 Cpad1 includes die capacitance only for DPRSTP DPSLP PWRGOOD No package parasitics are included 8 Cpad2 includes die capacitance for all other CMOS input signals No package parasitics are included Datasheet 31 intel Table 11 Open Drain Signal Group DC Specifications 32 Electrical Specifications Symbol Parameter Min Typ Max Unit Notes Von Output High Voltage Vccp 5 Vecp Vecp 5 3 Vo Output Low Voltage 0 0 20 lot Output Low Current 16 50 mA 2 Output
10. cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of both FSB agents DINV 3 0 DINV 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 assignment to data bus signals is shown below Bus Signal Data Bus Signals DINV 3 D 63 48 DINV 2 D 47 32 DINV 1 DINV 0 D 31 16 D 15 0 DPRSTP DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state In order to return to the Deep Sleep State DPRSTP must be de asserted DPRSTP is driven by the South Bridge chipset DPSLP DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state In order to return to the Sleep State DPSLP must be de asserted DPSLP is driven by the South Bridge chipset DPWR DPWR is a control signal from the Intel 945GSE chipset used to reduce power on the processor data bus input buffers DRDY I O DRDY Data Ready is asserted by the data dri
11. intel Mobile Intel Atom Processor N270 Single Core Datasheet May 2008 Document Number 320032 001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain des
12. on occasion through an MWAIT C4 sub state field If shrink prevention is enabled the processor does not enter Intel Enhanced Deeper Sleep state since the L2 cache remains valid and in full size Datasheet Low Power Features n te 2 3 Datasheet Enhanced Intel SpeedStep Technology The processor features Enhanced Intel SpeedStep Technology Following are the key features of Enhanced Intel SpeedStep Technology Multiple voltage and frequency operating points provide optimal performance at the lowest power Voltage and frequency selection is software controlled by writing to processor MSRs Ifthe target frequency is higher than the current frequency Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency Ifthe target frequency is lower than the current frequency the PLL locks to the new frequency and the Vcc is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition completes The processor controls voltage ramp rates internally to ensure glitch free transitions Low transition latency and large number of transitions possible per second Processor core including L2 cache is unavailable for up to 10 us during the frequency transition The bus protocol BNR mechanism is used to block snooping Improved Intel
13. strobe signals are operating in GTL mode The reason to use GTL is to improve signal integrity 19 i n tel Electrical Specifications 3 1 3 2 3 3 Electrical Specifications Power and Ground Pins For clean on chip power distribution the processor will have a large number of VCC power and VSS ground inputs All power pins must be connected to Vcc power planes while all VSS pins must be connected to system ground planes Use of multiple power and ground planes is recommended to reduce I R drop The processor VCC pins must be supplied the voltage determined by the VID Voltage ID pins FSB Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor uses a differential clocking implementation Voltage Identification The processor uses seven voltage identification pins VID 6 0 to support automatic selection of power supply voltages The VID pins for the processor are CMOS outputs driven by the processor VID circuitry Table 3 specifies the voltage level corresponding to the state of VID 6 0 A 1 in this refers to a high voltage level and a 0 refers to low voltage level Table 3 Voltage Identification Definition 20 VID6 VID5 VIDA VID3 VID2 VID1 V
14. the processor s Intel Thermal Monitor 1 or Intel Thermal Monitor 2 are triggered and the temperature remains high an Out Of Spec status and sticky bit are latched in the status MSR register and generates thermal interrupt PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its maximum operating temperature If Intel Thermal Monitor 1 or Intel Thermal Monitor 2 is enabled then the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOTZ The processor implements a bi directional PROCHOT capability to allow system designs to protect various components from overheating situations The PROCHOT signal is bi directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Only a single PROCHOT pin exists at a package level of the processor When the core s thermal sensor trips the PROCHOT signal will be driven by the processor package If only Intel Thermal Monitor 1 is enabled PROCHOTZ will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated If Intel Thermal Monitor 2 is enabled and the core is above TCC temperat
15. 12 2 1 2 Package Low power State Descriptions sssssssssnee 13 2 2 Dynamic Cache SIZIDng t Lect ener a a ec AU ERAN aa RAM i e a a Pe 16 2 3 Enhanced Intel SpeedStep Technology essen 17 2 4 Enhanced Low Power States ce eee eee eee nea aaa 18 2 5 FSB Low Power Enhancements cece eee eee nennen memes nnne 19 2 5 1 Front Side BUS ssepe neni ra aaa Sa i 19 Electrical Specifications rone ERE E RELAR E ER UA EN RMNM RR i anaes 20 3 1 Power and Ground Pins oun EE once inc a II ONT MEI ate 20 3 2 FSB Clock BCLK 1 0 and Processor Clocking eceeeeeeeeeeeeea eee eneas 20 3 3 Voltage Identification eee mm emen meme emen senes 20 3 4 Catastrophic Thermal Protection aaa nana 23 3 5 Reserved and Unused Pins nenea aaa nara ea 23 3 6 FSB Frequency Select Signals BSEL 2 0 sse 23 3 7 FSB Signal Groups iioii i eR Du d 0 i a DU RP NAME a 24 3 8 CMOS Asynchronous Signals eee meses nnn 25 3 9 Maximum Ratings esi ERR a i ER aa Aa RO RUE 25 3 10 Processor DC Specifications sss 26 Package Mechanical Specifications and Pin Information nenea 33 4 1 Package Mechanical Specifications eee eee anaes 33 4 1 1 Package Mechanical Drawings c eee 34 4 2 Processor Pin out Assignment eee Imm 34 4 3 Sign l De eripti On isa e ina pice eer oen ce rtt eee Pone dubai e du b pa 41 Thermal Specifications a
16. 75 1 0 1 0 0 1 0 0 4750 1 0 1 0 0 1 1 0 4625 1 0 1 0 1 0 0 0 4500 1 0 1 0 1 0 1 0 4375 1 0 1 0 1 1 0 0 4250 1 0 1 0 1 1 1 0 4125 1 0 1 1 0 0 0 0 4000 1 0 1 1 0 0 1 0 3875 1 0 1 1 0 1 0 0 3750 1 0 1 1 0 1 1 0 3625 1 0 1 1 1 0 0 0 3500 1 0 1 1 1 0 1 0 3375 1 0 1 1 1 1 0 0 3250 1 0 1 1 1 1 1 0 3125 1 1 0 0 0 0 0 0 3000 Datasheet Electrical Specifications N tel 3 4 3 5 3 6 Catastrophic Thermal Protection The processor supports the THERMTRIP signal for catastrophic thermal protection An external thermal sensor should also be used to protect the processor and the system against excessive temperatures Even with the activation of THERMTRIP which halts all processor internal clocks and activity leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor If the external thermal sensor detects a catastrophic processor temperature of 125 C maximum or if the THERMTRIP signal is asserted the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor THERMTRIP functionality is not ensured if the PWRGOOD signal is not asserted Reserved and Unused Pins All other RSVD signals can be left as No Connect Connection of these pins to Vcc Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors
17. CEPR N15 AP 0 D17 D 57 F2 GTLREF A7 DPSLP R17 D 58 C6 HIT AA17 AP 1 M18 D 59 B6 HITM V20 BNT T17 D 6 AA16 IERR F16 CMREF B7 D 60 B3 IGNNE J4 CORE DET A13 D 61 C4 INIT V16 EDM R6 D 62 C7 LINTO T15 HPPLL N6 D 63 D2 LINT1 R15 RSP T6 D 7 Y10 LOCK W20 RSVD A3 D 8 4 Y9 MCERR P17 RSVD C1 D 9 Y13 NC D6 RSVD C21 DBSY Y18 NC G6 VCCPC61 E13 DCLKPH V5 NC H6 VCCPC62 E14 37 38 ntel Package Mechanical Specifications and Pin Information Signal Name Ball Signal Name Ball Signal Name Ball VCCPC63 F13 VCC F11 VCCQO A9 VCCPC64 F14 VCC F12 VCCQO B9 SLP N18 VCC G10 VCCSENSE C13 SMI U17 VCC G11 VID 0 F15 STPCLK R16 VCC G12 VID 1 D16 TCK M17 VCC H10 VID 2 E18 TDI N16 VCC H11 VID 3 G15 TDO M16 VCC H12 VID 4 G16 EXTREF M6 VCC J10 VID 5 E17 THERMTRI P H17 VCC J11 VID 6 G18 THRMDA E4 VCC J12 VSS A2 THRMDC E5 VCC K10 VSS A4 TMS L17 VCC K11 VSS A8 TRDY W19 VCC K12 VSS A15 TRST K16 VCC L10 VSS A18 VCC A10 VCC L11 VSS A19 VCC A11 VCC L12 VSS A20 VCC A12 VCC M10 VSS B1 VCC B10 VCC M11 VSS B2 VCC B11 VCC M12 VSS B5 VCC B12 VCC N10 VSS B8 VCC C10 VCC N11 VSS B13 VCC C11 VCC N12 VSS B20 VCC C12 VCC P10 VSS B21 VCC D10 VCC P11 VSS C8 VCC D11 VCC P12 VSS C17 VCC D12 VCC R10 VSS D1 VCC E10 VCC R11 VSS D5 VCC Evi VCC R12 VSS D8 VCC E12 VCCA D7 VSS
18. CO state See the Intel 64 and IA 32 Architectures Software Developer s Manuals Volume 2A Instruction Set Reference A M and Volume 2B Instruction Set Reference N Z for more information Thread C2 State Individual threads of the dual threaded processor can enter the C2 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C2 instruction but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK pin is also asserted While in the C2 state the processor will process bus snoops and snoops from the other thread The processor thread will enter a snoopable sub state not shown in Figure 1 to process the snoop and then return to the C2 state Thread C4 State Individual threads of the processor can enter the C4 state by initiating a P LVL4 I O read to the P BLK or an MWAIT C4 instruction If both processor threads are in C4 the central power management logic will request that the entire processor enter the Deeper Sleep package low power state see Section 2 1 2 6 To enable the package level Intel Enhanced Deeper Sleep state Dynamic Cache Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software programmable MSR bit Package Low power State Descriptions The following state descriptions assume that both threads are in a common low power state For cases when only one thread is in a low power state see Section 2 1 1 Normal State This is the normal o
19. D14 VCC F10 VCCF V10 VSS D18 Datasheet Package Mechanical Specifications and Pin I nformation Datasheet intel Signal Name Ball Signal Name Ball Signal Name Ball VSS D21 VSS J13 VSS P3 VSS E3 VSS j17 VSS P4 VSS E6 VSS K1 VSS P5 VSS E7 VSS K6 VSS P6 VSS E8 VSS K7 VSS P7 VSS E15 VSS K9 VSS P9 VSS E16 VSS K13 VSS P13 VSS E19 VSS K15 VSS P15 VSS F4 VSS K21 VSS P16 VSS F5 VSS L3 VSS P18 VSS F6 VSS L4 VSS P19 VSS F7 VSS L5 VSS R1 VSS F17 VSS L6 VSS R5 VSS F18 VSS L7 VSS R7 VSS G1 VSS L9 VSS R9 VSS G4 VSS L13 VSS R13 VSS G7 VSS L15 VSS R21 VSS G9 VSS L18 VSS T4 VSS G13 VSS L19 VSS T5 VSS G21 VSS M1 VSS T7 VSS H3 VSS M5 VSS T9 VSS H4 VSS M7 VSS T10 VSS H7 VSS M9 VSS T11 VSS H9 VSS M13 VSS T12 VSS H13 VSS M21 VSS T13 VSS H16 VSS N4 VSS T18 VSS H18 VSS N5 VSS U3 VSS H19 VSS N7 VSS U6 VSS J5 VSS N9 VSS U7 VSS J7 VSS N13 VSS U15 VSS J9 VSS N17 VSS U16 39 40 ntel Package Mechanical Specifications and Pin Information Signal Name Ball Signal Name Ball Signal Name Ball VSS U19 VSS AA4 VTT L14 VSS V1 VSS AA7 VTT M8 VSS V4 VSS AA10 VTT M14 VSS V6 VSS AA12 VTT N8 VSS V7 VSS AA15 VTT N14 VSS V8 VSS AA18 VTT P8 VSS V13 VSS AA19 VTT P14 VSS V14 VSS AA20 VTT R8 VSS V18 VSSSENSE D13 VTT R14 VS
20. IDO Vcc V 0 0 1 1 0 0 0 1 2000 0 0 1 1 0 0 1 1 1875 0 0 1 1 0 1 0 1 1750 0 0 1 1 0 1 1 1 1625 0 0 1 I 1 0 0 1 1500 0 0 1 1 1 0 1 1 1375 0 0 1 1 1 1 0 1 1250 0 0 1 1 1 1 1 1 1125 0 1 0 0 0 0 0 1 1000 0 1 0 0 0 0 1 1 0875 0 1 0 0 0 1 0 1 0750 Datasheet intel Electrical Specifications Vcc V 1 0625 1 0500 1 0375 1 0250 1 0125 1 0000 0 9875 0 9750 0 9625 0 9500 0 9375 0 9250 0 9125 0 9000 0 8875 0 8750 0 8625 0 8500 0 8375 0 8250 0 8125 0 8000 0 7875 0 7750 0 7625 0 7500 0 7375 0 7250 0 7125 0 7000 0 6875 0 6750 0 6625 0 6500 0 6375 VIDO 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Ji 0 1 0 1 0 1 0 I 0 1 0 1 0 1 0 1 0 1 0 1 VID1 VID2 VID3 VIDA VID5 VI D6 21 Datasheet 22 Electrical Specifications VID6 VID5 VID4 VID3 VID2 VID1 VIDO Vcc V 1 0 0 0 1 1 0 0 6250 1 0 0 0 1 1 1 0 6125 1 0 0 1 0 0 0 0 6000 1 0 0 1 0 0 1 0 5875 1 0 0 1 0 1 0 0 5750 1 0 0 1 0 1 1 0 5625 1 0 0 1 1 0 0 0 5500 1 0 0 1 1 0 1 0 5375 1 0 0 1 1 1 0 0 5250 1 0 0 1 1 1 1 0 5125 1 0 1 0 0 0 0 0 5000 1 0 1 0 0 0 1 0 48
21. Port TAP logic TRST must be driven low during power on Reset Please contact your Intel representative for more implementation details VCCA PWR VCCA provides isolated power for the internal processor core PLLs Please contact your Intel representative for more implementation details VCC PWR Processor core power supply VSS GND Processor core ground node VSS NCTF GND Non Critical to Function VID 6 0 VID 6 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the processor The voltage supply for these pins must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations See Table 3 for definitions of these pins The VR must supply the voltage that is requested by the pins or disable itself VCCP PWR Processor I O Power Supply Datasheet Package Mechanical Specifications and Pin I nformation Datasheet intel Signal Name Type Description VCC_SENSE VCCSENSE is an isolated low impedance connection to processor core power Vcc It can be used to sense or measure power near the silicon with little noise Please contact your Intel represe
22. R MODIFIED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION H H g 5 5 1 see ocru B Eram 5 e ep RE 6 E o u d 0000000000000 00 0 0 o4 li rp G 1 40000000006000000006 60000000000000000000 000000000040000000000 000000000040000000000 1 000000000060000000000 000000000040000000000 000000000090000000000 000000000090000000000 d 0600000000000000000000 F iater metus cM ig i e e e 6 e e e e o 9 coo eco A F 1 00000000000000000000 i 000000000060000000000 000000000000000000000 000000000090000000000 i o00o0000000 0000000000 amp 000000000000000000000 000000000090000000000 600000000000000000000 s4400000000000000000000 g i 84 020000009000000004 51 t q T L224 ETESPIRD MBE RIB a lm ai TOP VIEW SIDE VIEW BOTTOM VIEW D D WEEE 5 swa PE comers Y 5i 21 95 22 05 ns s A E T EE uo soma A FRONT VIEW Lu UE tm 5 E M d A 0 808 E c 5 ias ran C Fe 3 2 T s s Lil 20 BASIC D EPOXY UNDERFILL amr BO 4140 02 10 BASIC We 10 BASIC 50 00 a oan B SME 15 n ET p A IE 8 r wx ws a t B D O O C3 O OU Is ora DL DEPARTE TNOENURTAUS hnc S NE Sto Rees intel pei IT atte ant vec Savin Lah ta stem ij AE POM UNA oma Ci wm A ge AE Mitta Latt T SCALE as DIMENSIONS 2 2 CEILI w THIRD ANGLE POETIN EMTS DRAWING A omori si ne SHE Tun etr w uc DI Al 21210 2 SCALE T DO KOT SCALE DRAWING Jer or 8 1 6 5 4 3 2
23. S V21 VIT C9 VTT T8 VSS W1 VTT D9 VTT T14 VSS w5 VTT E9 VTT U8 VSS W8 VIT F8 VTT U9 VSS W11 VIT F9 VTT U10 VSS W14 VIT G8 VTT U11 VSS W17 VIT G14 VTT U12 VSS W21 VIT H8 VTT U13 VSS Y1 VTT H14 VTT U14 VSS Y2 VTT J8 DP 0 v9 VSS Y20 VTT J14 DP 1 R4 VSS Y21 VTT K8 DP 2 M4 VSS AA2 VTT K14 DP 3 D4 VSS AA3 VIT L8 Datasheet Package Mechanical Specifications and Pin I nformation In tel 4 3 Signal Description Table 13 Signal Description Signal Name Type Description A 31 3 1 0 A 31 3 Address defines a 2 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents on the processor FSB A 31 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before RESET is de asserted A20M If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting AZOM emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an input output write ins
24. TDI TMS TRST Datasheet Electrical Specifications n te 3 8 3 9 Datasheet Signal Group Type Signals1 Open Drain Output Synchronous TDO to TCK FSB Clock Clock BCLK 1 0 Power Other COMP 3 0 HFPLL old name is DBR 2 CMREF GTLREF TEST2 Dclk TEST1 Aclk THERMDA THERMDC VCC VCCA VCCP VCC_SENSE VSS VSS_SENSE VCCQ 1 0 VCCPC6 NOTES 1 Refer to Chapter 4 for signal descriptions and termination requirements 2 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 PROCHOT signal type is open drain output and CMOS input CMOS Asynchronous Signals CMOS input signals are shown in Table 5 Legacy output FERR IERR and other non AGTL signals THERMTRIP and PROCHOT use Open Drain output buffers These signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the CMOS signals are required to be asserted for more than 5 BCLKs for the processor to recognize them See Section 3 10 for the DC specifications for the CMOS signal groups Maximum Ratings Table 6 specifies absolute maximum and minimum ratings Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limit
25. Table 12 Pin out Arranged by Signal Name mene 36 Table 13 Signal Description esses Imm esses enne 41 Table 14 Power Specifications for the Processor ceea 50 Table 15 Thermal Diode Interface eee eee eee eed 52 Table 16 Thermal Diode Parameters using Transistor Model sssssss 52 Datasheet Revision History Document Revision Description Revision Date Number Number Datasheet 5 intel ranean 1 1 1 Note Introduction The Intel Atom Processor N270 code named Mobile Diamondville is built on 45 nanometer process technology the first generation of low power IA 32 micro architecture specially designed for Netbook 08 Platform In this platform the processor supports Intel 945GSE chipset with the I O Controller Hub Intel 82801GBM Throughout this document the Intel Atom Processor N270 is referred as processor Major Features The following list provides some of the key features on this processor e New single core processor for mobile devices e On die primary 32 kB instructions cache and 24 kB write back data cache e 533 MHz source synchronous front side bus FSB e 2 Threads support e On die 512 kB 8 way L2 cache e Support for IA 32 bit architecture e Intel Streaming SIMD Extensions 2 and 3 Intel SSE2 and Intel SSE3 support and Supplemental Streaming SIMD Extension 3 SSSE3 support e Micro FCBGA8 packaging technologie
26. Thermal Monitor mode When the on die thermal sensor indicates that the die temperature is too high the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR The processor waits for a fixed time period If the die temperature is down to acceptable levels an up transition to the previous frequency and voltage point occurs An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management Enhanced thermal management features Digital Thermal Sensor and Out of Specification detection Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of unsuccessful Intel Thermal Monitor 2 transition 17 N le Low Power Features 2 4 18 Enhanced Low Power States Enhanced low power states CIE C2E CAE optimize for power by forcibly reducing the performance state of the processor when it enters a package low power state Instead of directly transitioning into the package low power state the enhanced package low power state first reduces the performance state of the processor by performing an Enhanced Intel SpeedStep Technology transition down to the lowest operating point Upon receiving a break event from the package low power state control will be returned to software while an Enhanced Intel SpeedStep Technology transition up to the initial operating point occurs The ad
27. Type Description TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support Please contact your Intel representative for more implementation details TEST 1 4 Refer to the appropriate platform design guide for further TESTI TEST2 TEST3 and TEST4 termination requirements and implementation details All TEST signals can be left as No Connects THRMTRI P4 The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 125 C This condition is signaled to the system by the THERMTRIP Thermal Trip pin For termination requirements please contact your Intel representative for more implementation details THRMDA PWR Thermal Diode Anode THRMDC PWR Thermal Diode Cathode TMS TMS Test Mode Select is a J TAG specification support signal used by debug tools Please contact your Intel representative for more implementation details TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both FSB agents TRST TRST Test Reset resets the Test Access
28. active THERMTRIP activation is independent of processor activity and does not generate any bus cycles When THERMTRIP is asserted the processor core voltage must be shut down within the time specified in Chapter 3 Digital Thermal Sensor The processor also contains an on die Digital Thermal Sensor DTS that is read via an MSR no I O interface The DTS is only valid while the processor is in the normal operating state the Normal package level low power state Unlike traditional thermal devices the DTS outputs a temperature relative to the maximum supported operating temperature of the processor T max It is the responsibility of software to convert the relative temperature to an absolute temperature The temperature returned by the DTS will always be at or below T max Catastrophic temperature conditions are detectable via an Out Of Spec status bit This bit is also part of the DTS MSR When this bit is set the processor is operating out of specification and immediate shutdown of the system should occur The processor operation and code execution is not ensured once the activation of the Out of Spec status bit is set The DTS relative temperature readout corresponds to the Intel Thermal Monitor 1 and Intel Thermal Monitor 2 trigger point When the DTS indicates maximum processor core temperature has been reached the Intel Thermal Monitor 1 or Intel Thermal Monitor 2 hardware thermal control mechanism will activate The DTS and Inte
29. al Specifications and Pin I nformation in tel Signal Name Type Description IERR IERR Internal Error is asserted by a processor as the result of an internal error Assertion of ERR is usually accompanied by a SHUTDOWN transaction on the FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep ERR asserted until the assertion of RESET BINIT or INIT IGNNE IGNNE 4 Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute non control floating point instructions If GNNE is de asserted the processor generates an exception on a non control floating point instruction if a previous floating point instruction caused an error IGNNEZ has no effect when the NE bit in control register 0 CRO is set IGNNEZ is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous
30. asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port Please contact your Intel representative for more implementation details TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support Please contact your Intel representative for more implementation details Datasheet 47 48 Package Mechanical Specifications and Pin I nformation Signal Name
31. calculated with the equation Terror nt Tmeasured 1 Nactua Ntrim Where Terror nf IS the offset in degrees C Tmeasurea iS in Kelvin Nactuai is the measured ideality of the diode and Nntrim is the diode ideality assumed by the temperature sensing device Datasheet m Thermal Specifications and Design Considerations In tel 5 2 Datasheet Intel Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC Thermal Control Circuit when the processor silicon reaches its maximum operating temperature The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the clocks are on while the TCC is active With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be ca
32. cterized data from silicon measurements at a later date Figure 3 Active VCC and I CC Processor Loadline Vcc V Slope 5 9 mV A at package VCC SENSE VSS SENSE pins Differential Remote Sense required Vcc Max HFMILFM 13 mV Ripple Voc oc Max HFM LFM Voc Nom HFM LFM Vcc oc Min HEM LFM Voc Min HFM LFM Vo nom1 5 VR ST Pt Error 1 p Ico A lcc max HFM LFM Note 1 Vcc Set Point Error Tolerance is per below Tolerance Voc Active Mode VID Code Range 1 5 Vcc gt 0 7500 V VID 0111100 FNLS MN Voc lt 0 7500 V VID 0111100 Datasheet Electrical Specifications Figure 4 Deeper Sleep VCC and I CC Processor Loadline Table 8 FSB Differential BCLK Specifications Vcc cone V Vcc core Max Deeper Sleep Vcc core oc Max Deeper Sleep Vcc core Nom Deeper Sleep Vcc_core oc Min Deeper Sleep Vcc cone Min Deeper Sleep Vcc come Tolerance VR ST Pt Error 1 Slope 5 9 mV A at package VCC SENSE VSS SENSE pins Differential Remote Sense required 13 mV Ripple for PSI4 Asserted T 0 Note 1 Deeper Sleep VCC CORE Set Point Error Tolerance is per below Tolerance PSI Ripple VID 1 5 3 mV 11 5 mV 3 mV 25 mV 3 mV Vcc cone VID Voltage Range Vcc cone gt 0 7500 V 0 7500 V Vcc cone 0 5000 V 0 5000 V Vcc conc 0 4125 V P dcc core A lcc cone Max Deeper Sleep
33. e appropriate pins of both FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction 1 0 When the priority agent asserts BPRI to arbitrate for ownership of the FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock PRDY Probe Ready signal used by debug tools to request debug O operation of the processor Please contact your Intel representative for more implementation details PREQ Probe Request signal used by debug tools to request debug l operation of the processor Please contact your Intel representative for more implementation details PROCHOT As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC 1 0 O has been activated if enabled As an input assertion of DP PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT This signal may require voltage translation on the motherboard Please contact your Intel representative for more implementation details PWRGOOD PWRGOOD Power Good is a processor input The processor requires this
34. e monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all FSB agents This includes debug or performance monitoring tools BPRI BPRI Bus Priority Request is used to arbitrate for ownership of the FSB It must connect the appropriate pins of both FSB agents Observing BPRI active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BRO I O BRO is used by the processor to request the bus The arbitration is done between the processor Symmetric Agent and Intel 945GSE High Priority Agent BSEL 2 0 BSEL 2 0 Bus Select are used to select the processor input clock frequency Table 4 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For Intel Atom processor N270 the BSEL is fixed to operat at 133 MHz BCLK frequency COMP 3 0 PWR COMP 3 0 must be terminated on the system board using precision 196 tolerance resistors D 63 0
35. ep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the FSB while the processor is in Sleep state Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be de asserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence Datasheet Low Power Features n tel 2 1 2 5 2 1 2 6 2 1 2 6 1 Datasheet While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin see Section 2 1 2 5 While the processor is in the Sleep state the SLP pin must be de asserted if another asynchronous FSB event needs to occur Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP pin while in the Sleep state BCLK may be stopped durin
36. erating point or running idle at a high operating point Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases Datasheet Low Power Features n te 2 5 2 5 1 Datasheet FSB Low Power Enhancements The processor incorporates FSB low power enhancements e BPRI control for address and control input buffers e Dynamic Bus Parking e Dynamic On Die Termination disabling e Low VCCP I O termination voltage The processor incorporates the DPWR signal that controls the data bus input buffers on the processor The DPWRZ signal disables the buffers when not used and activates them only when data bus activity occurs resulting in significant power savings with no performance impact BPRI control also allows the processor address and control input buffers to be turned off when the BPRI signal is inactive Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor de asserts its BRO pin The on die termination on the processor FSB buffers is disabled when the signals are driven low resulting in additional power savings The low I O termination voltage is on a dedicated voltage plane independent of the core voltage enabling low I O switching power at all times Front Side Bus The processor has only one signaling mode where the data and address buses and the
37. fied by design characterization 4 The ideality factor nQ represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current lc ls e QVpg ngkT 1 where ls saturation current q electronic charge Vs voltage across the transistor base emitter junction same nodes as VD k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Rr provided in the Diode Model Table Table 16 can be used for more accurate readings as needed When calculating a temperature based on the thermal diode measurements a number of parameters must be either measured or assumed Most devices measure the diode ideality and assume a series resistance and ideality trim value although are capable of also measuring the series resistance Calculating the temperature is then accomplished using the equation listed under Table 16 In most sensing devices an expected value for the diode ideality is designed in to the temperature calculation equation If the designer of the temperature sensing device assumes a perfect diode the ideality value also called niis will be 1 000 Given that most diodes are not perfect the designers usually select an Nim value that more closely matches the behavior of the diodes in the processor If the processor diode ideality deviates from that of the ntrim each calculated temperature will be offset by a fixed amount This temperature offset can be
38. free air Under these conditions processor landings should not Storage be connected to any supply voltages have any I Os biased or receive any AGTL Conditions clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Enhanced Intel SpeedStep Technology Technology that provides power management capabilities to low power devices Processor core die with integrated L1 and L2 cache All AC timing and signal integrity specifications are at the pads of the processor core Datasheet 7 Processor Core ntel Introduction Definition lec for Mobile Intel Atom Processor N270 Recommended Design Target Estimated lcc for Mobile Intel Atom Processor N270 is the number that can be use as a reflection on a battery life estimates lcc Stop Grant lcc Deep Sleep Vcc Power Supply Current Slew Rate at Processor Package Pin Estimated Junction Temperature Datasheet I ntroduction n tel 1 3 References Material and concepts available in the following documents may be beneficial when reading this document Table 1 References Document Document No Location Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com p roducts processor man e Intel 64 and IA 32 Architectures Sof
39. g the Deep Sleep state for additional platform level power savings BCLK stop restart timings on appropriate chipset based platforms with the CK505 clock chip are as follows e Deep Sleep entry the system clock chip may stop tri state BCLK within 2 BCLKs of DPSLP assertion It is permissible to leave BCLK running during Deep Sleep e Deep Sleep exit the system clock chip must start toggling BCLK within 10 BCLK periods within DPSLP de assertion To re enter the Sleep state the DPSLP pin must be de asserted BCLK can be re started after DPSLP de assertion as described above A period of 15 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin must be de asserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state When the processor is in Deep Sleep state it will not respond to interrupts or snoop transactions Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels One of the potential lower core voltage levels is achieved by entering the base Deeper Slee
40. gh Voltage GTLREF 0 10 Vecp Vcce 0 10 V 3 6 Vit Input Low Voltage 0 10 0 GTLREF 0 10 V 2 4 Vou Output High Voltage Vccpe 0 10 Vecp Vecp V 6 a 46 SS 61 SS Rit Termination Resistance 55 Q 7 12 46 CC 64 CC Ron GIL GTL Buffer on Resistance 21 25 29 Q 5 mode lu Input Leakage Current 100 pA 8 Cpad Pad Capacitance 1 8 2 1 2 75 pF 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vitis defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 3 Vin is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vin and Von may experience excursions above Vcce However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance 6 GTLREF should be generated from VCCP with a 196 tolerance resistor divider 7 RTT is the on die termination resistance measured at VOL of the AGTL output driver 8 Specified with on die RTT and RON are turned off 9 Cpad includes die capacitance only No package parasitics are included 10 There are external resistor on the compO and comp2 pins 11 On die termination resistance measured at 0 33 Vccp 12 SS source synchronous pins such as quad pumped data bus and double pumped address bus which require a clock strobe CC Common clock pins 30 Datasheet Electrical Specifications
41. hermal control circuit This temperature offset must be taken into account when using the processor thermal diode to implement power management events This offset is different than the diode Torse value programmed into the processor Model Specific Register MSR Table 15 and Table 16 provide the diode interface and specifications Transistor model parameters shown in Table 16 provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits Contact your external sensor supplier for their recommendation The thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor 51 a intel Thermal Specifications and Design Considerations Table 15 Thermal Diode I nterface Signal Name Pin Ball Number Signal Description THERMDA E4 Thermal diode anode THERMDC E5 Thermal diode cathode Table 16 Thermal Diode Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes IFW Forward Bias Current 5 200 uA 1 IE Emitter Current 5 200 uA 1 nQ Transistor Ideality 0 997 1 001 1 015 2 3 4 Beta 0 25 0 65 2 3 Rr Series Resistance 2 79 4 52 6 24 Q 2 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Characterized across a temperature range of 50 100 C 3 Not 100 tested Speci
42. ign defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Enhanced Intel SpeedStep Technology for specified units of this processor available Q2 06 See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel Atom Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2008 Intel Corporation All rights reserved 2 Datasheet Contents Datasheet Introductio ot 6 1 1 Maior Features tree E Ree e et a ERIRE ERE d n PRX E e Sa EO REV NK a arx RUNE 6 1 2 Terminology 3x eO A Hr RE UP I RI a LIKE RI 7 1 3 BETE Eli COS ape aea a adi uM e aa Ei ed apa aici ET d set IE iS 9 Low Power Features si iai ata hee a n a aa a a ra a a ata a at 10 2 1 Clock Control and Low power States sss 10 2 1 1 Thread Low power State Descriptions ssssessssee
43. l Thermal Monitor 1 Intel Thermal Monitor 2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS Additionally the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power mechanical and thermal attach and software application The system designer is required to use the DTS to ensure proper operation of the processor within its temperature operating specifications Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs These thresholds have the capability of generating interrupts via the core s local APIC 55 a intel Thermal Specifications and Design Considerations 5 3 1 5 3 2 56 Note The digital thermal sensor DTS accuracy is in the order of 5 C 10 C around 90 C it deteriorates to 10 C at 50 C The DTS temperature reading saturates at some temperature below 50 C Any DTS reading below 50 C should be considered to indicate only a temperature below 50 C and not a specific temperature External thermal sensor with BJT model is required to read thermal diode temperature Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient This feature is intended for graceful shut down before the THERMTRIP is activated If
44. l the Intel Thermal Monitor 2 event has been completed e Ifthe processor load based Enhanced Intel SpeedStep technology transition target frequency is lower than the Intel Thermal Monitor 2 transition based target frequency the processor will transition to the processor load based Enhanced Intel SpeedStep technology target frequency point The TCC may also be activated via on demand mode If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1 the TCC will be activated immediately independent of the processor temperature When using on demand mode to activate the TCC the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Intel Thermal Monitor control register In automatic mode the duty cycle is fixed at 5096 on 5096 off however in on demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 596 on 12 5 off in 12 5 increments On demand mode may be used at the same time automatic mode is enabled however if the system tries to enable the TCC via on demand mode at the same time automatic mode is enabled and a high temperature condition exists automatic mode will take precedence An external signal PROCHOT processor hot is asserted when the processor detects that its temperature is above the thermal trip point Bus snooping and interrupt latching are also active while the TCC is active Besides the thermal sensor and thermal control circuit the Intel Thermal Monit
45. nd Design Considerations c ccceceeeee eset teeta eee ea ene 50 5 1 Eis 51 5 2 Intel Thermal Monitor nmm memes eee nnne 53 5 3 Digital Thermal Sensor cie Urn perenne Pepe beate en ep PR pr T e aa eed 55 5 3 1 Out of Specification Detection sesesssssss m 56 5 3 2 PROCHOT Signal Pii eicere er rne et emite ronde ger tees meres 56 3 Tables Figure 1 Thread Low power States sss e meses 11 Figure 2 Package Low power States c eee mmm 11 Figure 3 Active VCC and ICC Processor Loadline c eee 28 Figure 4 Deeper Sleep VCC and ICC Processor Loadline sse 29 Table T References scs pica tema aa HERE E ea KENN EUR a aa a 9 Table 2 Coordination of Thread Low power States at the Package Level 12 Table 3 Voltage Identification Definition sss emm 20 Table 4 BSEL 2 0 Encoding for BCLK Frequency esses 23 Table 5 ESB Pin Groups iiic e eer pari acea mi Pei oret e bore aiba desde bale Desain 24 Table 6 Processor Absolute Maximum Ratings csssesssessssn ee 26 Table 7 Voltage and Current Specifications for the Processors sssssseees 27 Table 8 FSB Differential BCLK Specifications esses 29 Table 9 AGTL Signal Group DC Specifications nea 30 Table 10 Legacy CMOS Signal Group DC Specifications sss 31 Table 11 Open Drain Signal Group DC Specifications nenea nenea 32
46. ng parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 5 identifies which signals are common clock source synchronous and asynchronous Table 5 FSB Pin Groups 24 Signal Group Type Signals1 AGTL Common Synchronous BPRI 2 DEFER PREQ 4 RESET RS 2 0 Clock Input to BCLK 1 0 TRDY DPWR AGTL Common Synchronous ADS BNR BPM 3 0 BRO DBSY DRDY Clock I O to BCLK 1 0 HIT HITM LOCK PRDY Signals Associated Strobe REQ 4 0 A ADSTBO AGTL Source MR 16 3 Synchronous 1 0 d iia A 31 17 ADSTB1 D 15 0 DSTBPO DSTBNO D 31 16 DSTBP1 DSTBN1 D 47 32 DSTBP2 DSTBN2 D 63 48 DSTBP3 DSTBN3 Synchronous i AGTL Strobes to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 DPRSTP DPSLP IGNNE INIT LINTO INTR EOS TRUE Asynchronous 1 init1 NMI PWRGOOD SMI SLP STPCLK Open Drain Output Asynchronous FERR THERMTRIP IERRZ Open Drain I O Asynchronous PROCHOT 3 CMOS Output Asynchronous VID 6 0 BSEL 2 0 Synchronous CMOS Input to TCK TCK
47. ntative for more implementation details VSS SENSE VSS SENSE is an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise Please contact your Intel representative for more implementation details 49 a intel Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits A complete thermal solution includes both component and system level thermal management features The system processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature Tj specifications at the corresponding thermal design power TDP value listed in Table 14 through Table 16 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system Attempts to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system Table 14 Power Specifications for the Processor Processor Core Frequency and Thermal Design Symbol Number Voltage Power Unit Notes At 90 C TDP N270 1 6 GHz HFM Vcc 2 5W W 1 4 Symbol Parameter Min Typ Max Unit Notes Auto Halt Stop Grant P
48. ooling for the VR and rely on bi directional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Datasheet 57
49. or also includes one ACPI register one performance counter register three MSR and one I O pin PROCHOT All are available to monitor and control the state of the Intel Datasheet m Thermal Specifications and Design Considerations in tel 5 3 Datasheet Thermal Monitor feature The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT PROCHOTZ will not be asserted when the processor is in the Stop Grant Sleep Deep Sleep and Deeper Sleep low power states hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification the system must initiate an orderly shutdown to prevent damage If the processor enters one of the above low power states with PROCHOT already asserted PROCHOTZ will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point If Intel Thermal Monitor automatic mode is disabled the processor will be operating out of specification Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 125 C At this point the THERMTRIP signal will go
50. or implements two software interfaces for requesting low power states MWAIT instruction extensions with sub state hints and P LVLx reads to the ACPI P BLK register block mapped in the processor s I O address space The P LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads on the processor FSB The monitor address does not need to be setup before using the P LVLx I O read interface The sub state hints used for each P LVLx read can be configured in a software programmable MSR If a thread encounters a chipset break event while STPCLK is asserted then it asserts the PBE output signal Assertion of PBE when STPCLK is asserted indicates to system logic that individual threads should return to the CO state and the processor should return to the Normal state Figure 1 shows the thread low power states Figure 2 shows the package low power states Table 2 provides a mapping of thread low power states to package low power states Datasheet Low Power Features N tel Figure 1 Thread Low power States Grant STPCLK u STPCLK asserted de asserted STPCLK STPCLK m de asserted STPCLK asserted T de asserted C1 STPCLK C1 Auto asserted MWAIT Core state BS a Halt break instruction MWAIT C1 Halt break CO P LVL2 or MWAIT C2 Core State br ak Core state P_LVL4 or MWAIT C4 t break ___ C2 y halt break A20M t
51. ower PAH At 70 C at HFM Vcc 1 0 Ww PSGNT 2 at LFM Vec 0 7 W At 50 C PDSLP Deep Sleep Power 0 5 Ww 35 At 50 C PDPRSLP Deeper Sleep Power 0 5 Ww 38 TJ Junction Temperature 0 90 8C 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 10096 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached Refer to Section Error Reference source not found for more details 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 Deep Sleep state is mapped to Deeper Sleep State 50 Datasheet m Thermal Specifications and Design Considerations In tel 5 1 Datasheet The processor incorporates three methods of monitoring die temperature the Digital Thermal Sensor Intel Thermal Monitor and the Thermal Diode The Intel Thermal Monitor detailed in Section 5 2 must be used to determine when the maximum specified processor junction temperature has been reached Thermal Diode The processor incorporates an on die PNP transistor whose base emit
52. p state The Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep state The following lower core voltage level is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub state of Deeper Sleep state Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep only when the L2 cache has been completely shut down Refer to Section 2 1 2 6 1 for further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep state In response to entering Deeper Sleep the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID 6 0 pins Exit from Deeper Sleep or Intel Enhanced Deeper Sleep state is initiated by DPRSTP de assertion when the core requests a package state other than C4 or the core requests a processor performance state other than the lowest operating point I ntel Enhanced Deeper Sleep State Intel Enhanced Deeper Sleep state is a sub state of Deeper Sleep that extends power saving capabilities by allowing the processor to further reduce core voltage once the 15 N le Low Power Features 2 2 16 L2 cache has been reduced to zero ways and completely shut down The following events occur when the processor enters Intel Enhanced Deeper Sleep state e The processor issues a P_LVL4 I O read or an MWAIT C4 instruction and then progressively reduces the L2 cache to zero e The processor d
53. pable of cooling the processor even when the TCC is active continuously The Intel Thermal Monitor controls the processor temperature by modulating starting and stopping the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature The Intel Thermal Monitor uses two modes to activate the TCC automatic mode and on demand mode If both modes are activated automatic mode takes precedence There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal Monitor 2 These modes are selected by writing values to the MSRs of the processor After automatic mode is enabled the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation The Intel Thermal Monitor automatic mode must be enabled through BIOS for the processor to be operating within specifications Intel recommends Intel Thermal Monitor 1 and Intel Thermal Monitor 2 be enabled on the processor When Intel Thermal Monitor 1 is enabled and a high temperature situation exists the clocks will be modulated by alternately turning the clocks off and on at a 5096 duty cycle Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase Once the temperature has returned to a non critical level modulation ceases and TCC goes inactive A small amount of hysteresis has been included to prevent ra
54. perating state for the processor The processor remains in the Normal state when the threads are in the CO C1 AutoHALT or C1 MWAIT state Stop Grant State When the STPCLK pin is asserted each thread of the processors enters the Stop Grant state within 1384 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle When the STPCLK pin is de asserted the core returns to its previous low power state Since the AGTL signal pins receive power from the FSB these pins should not be driven allowing the level to return to Vccp for minimum power drawn by the 13 N le Low Power Features 2 1 2 3 2 1 2 4 14 termination resistors in this state In addition all other input pins on the FSB should be driven to the inactive state RESET causes the processor to immediately initialize itself but the processor will stay in Stop Grant state When RESET is asserted by the system the STPCLK SLP DPSLP and DPRSTP pins must be de asserted prior to RESET de assertion When re entering the Stop Grant state from the Sleep state STPCLK should be de asserted after the de assertion of SLP While in Stop Grant state the processor will service snoops and latch interrupts delivered on the FSB The processor will latch SMI INIT and LINT 1 0 interrupts and will service only one of each upon return to the Normal state The PBE signal may be driven when the processor is in Stop Grant sta
55. pid active inactive transitions of the TCC when the processor temperature is near the trip point The duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardware software drivers or interrupt handling routines Processor performance will be decreased by the same amount as the duty cycle when the TCC is active When Intel Thermal Monitor 2 is enabled and a high temperature situation exists the processor will perform an Enhanced Intel SpeedStep Technology transition to the LFM When the processor temperature drops below the critical level the processor will make an Enhanced Intel SpeedStep Technology transition to the last requested operating point The processor also supports Enhanced Multi Threaded Thermal Monitoring EMTTM EMTTM is a processor feature that enhances Intel Thermal Monitor 2 with a processor throttling algorithm known as Adaptive Intel Thermal Monitor 2 Adaptive Intel Thermal Monitor 2 transitions to intermediate operating points rather than directly to the LFM once the processor has reached its thermal 53 54 ntel Thermal Specifications and Design Considerations limit and subsequently searches for the highest possible operating point Please ensure this feature is enabled and supported in the BIOS Also with EMTTM enabled the operating system can request the processor to throttling to any point between Intel Dynamic Acceleration frequency and Super LFM frequenc
56. ransition INIT INTR NMI PREQ RESET SMI or APIC interrupt core state break halt break OR Monitor event AND STPCLK high not asserted T STPCLK assertion and de assertion have no effect if a core is in C2 or C4 Figure 2 Package Low power States Datasheet i N STPCLIG asserted Z w SLP asserted x C N DPSLP asserted RV asserted 7 B T Stop y Deeper Deep Normal Sleep _ Grant A Sleep Sleep j NL E deasserted s vs SLP de asserted d DPSLP de asse eN oe A Snoop Snoop serviced occurs lor Stop Grant Snoop gu T Deeper Sleep includes the Deeper Sleep state and the Intel Enhanced Deeper Sleep state 11 N le Low Power Features Table 2 Coordination of Thread Low power States at the Package Level Package State Thread State CO C1 c2 C4 CO Normal Normal Normal Normal CI Normal AutoHalt AutoHalt AutoHalt C2 Normal AutoHalt Stop Grant Stop Grant Deeper Sleep C4 Normal AutoHalt Stop Grant Intel Enhanced Deeper Sleep NOTES 1 AUtoHALT or MWAIT CI1 2 Toenter a package state both threads must be in a common low power state If the threads are not in a common low power state the package state will resolve to the highest power C state 2 1 1 Thread Low power State Descriptions 2 1 T7 1 Thread CO State This is the normal operating state for threads in
57. requency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Enhanced Halt State Typical AVID range is 0 8 V to 0 85 V 2 The voltage specifications are assumed to be measured across VCC SENSE and VSS SENSE pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum Datasheet 27 28 N le Electrical Specifications impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 90 C Ty Specified at the nominal Vcc Measured at the bulk capacitors on the motherboard Vcc goor tolerance is shown in Figure 3 and Figure 4 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested This is a power up peak current specification which is applicable when Vccp is high and Vcc cose is low This is a steady state Icc current specification which is applicable when both Vcce and Vcc cose are high The Vcc max supported by the process is 1 1 V but the parameter can change burnin voltage is higher Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data These specifications will be updated with chara
58. rives the VID code corresponding to the Intel Enhanced Deeper Sleep state core voltage on the VID 6 0 pins Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions e The CO timer that tracks continuous residency in the Normal package state has not expired This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed e The FSB speed to processor core speed ratio is below the predefined L2 shrink threshold If the FSB speed to processor core speed ratio is above the predefined L2 shrink threshold then L2 cache expansion will be requested If the ratio is zero then the ratio will not be taken into account for Dynamic Cache Sizing decisions Upon STPCLK de assertion the core exiting Intel Enhanced Deeper Sleep state will expand the L2 cache to two ways and invalidate previously disabled cache ways If the L2 cache reduction conditions stated above still exist when the core returns to C4 then package enters Intel Enhanced Deeper Sleep state then the L2 will be shrunk to zero again If the core requests a processor performance state resulting in a higher ratio than the predefined L2 shrink threshold the CO timer expires then the whole L2 will be expanded upon the next interrupt event L2 cache shrink prevention may be enabled as needed
59. s e Thermal management support via Intel Thermal Monitor 1 and Intel Thermal Monitor 2 e FSB Lane Reversal for flexible routing e Supports CO C1 e C2 e C4 e e L2 Dynamic Cache Sizing e Advanced power management features including Enhanced Intel SpeedStep Technology e Execute Disable Bit support for enhanced security Datasheet I ntroduction n tel 1 2 Terminology Definition A 4 symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESETZ is low a reset has been requested Conversely when NMI is high a non maskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus Refers to the interface between the processor and system core logic also FSB known as the GMCH chipset components Advanced Gunning Transceiver Logic Used to refer to Assisted GTL signaling technology on some Intel processors CMOS Complementary metal Oxide semiconductor Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to
60. s but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields 25 i n tel Electrical Specifications Table 6 Processor Absolute Maximum Ratings 3 10 Symbol Parameter Min Max Unit Notes T STORAGE Processor Storage Temperature 40 85 C 2 Wiese Any Processor Supply Voltage with 0 3 1 10 v 1 Respect to Vss AGTL Buffer DC Input Voltage with Respect to Vss RU ey M 1 2 VinAGTL CMOS Buffer DC Input Voltage with Respect to Vss 0 1 1 10 V 1 2 VinAsynch_CMOS
61. signal However to ensure recognition of this signal following an Input Output Write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must connect the appropriate pins of both FSB agents If INIT is sampled active on the active to inactive transition of RESET the processor reverses its FSB data and address signals internally to ease motherboard layout for systems where the chipset is on the other side of the motherboard D 63 0 gt D 0 63 A 31 3 gt A 3 31 DINV 3 0 is also reversed LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a non maskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration Datasheet 45 Package Mechanical Specifications and Pin I nformation Signal Name Type Description LOCK Lock indicates to the system that a transaction must occur atomically This signal must connect th
62. signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must l again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification and be followed by a 2 ms minimum RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation For termination requirements please contact your Intel representative for more implementation details REQ 4 0 REQ 4 0 Request Command must connect the appropriate pins of both FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 0 I O 46 Datasheet m Package Mechanical Specifications and Pin I nformation In tel Signal Name Type Description RESET Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a po
63. ssor should be returned to the Normal state When FERR PBE is asserted O indicating a break event it will remain asserted until STPCLK is de asserted Assertion of PREQ when STPCLK is active will also cause an FERR break event For additional information on the pending break event functionality including identification of support of the feature and enable disable information refer to Volume 3 of the Intel 64 and IA 32 Architectures Software Developer s Manuals and the Intel Processor Identification and CPUID Instruction Application Note For termination requirements please contact your Intel representative CMREF CMREF determines the signal reference level for CMOS input pins CMREF should be set at 1 2 Vcce CMREF is used by the CMOS PWR receivers to determine if a signal is a logical O or logical 1 NOTE Because of not using CMOS CMREF and GTLREF should be provided with 2 3 Vccp GTLREF GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 Vcce GTLREF is used by the AGTL receivers to determine if a signal is a logical O or logical 1 PWR HIT HITM HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Either FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together I O 44 Datasheet m Package Mechanic
64. te PBE will be asserted if there is any pending interrupt or Monitor event latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that the entire processor should return to the Normal state A transition to the Stop Grant Snoop state occurs when the processor detects a snoop on the FSB see Section 2 1 2 3 A transition to the Sleep state see Section 2 1 2 4 occurs with the assertion of the SLP signal Stop Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop Grant state by entering the Stop Grant Snoop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB or the interrupt has been latched The processor returns to the Stop Grant state once the snoop has been serviced or the interrupt has been latched Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and stops all internal clocks The Sleep state is entered through assertion of the SLP signal while in the Stop Grant state The SLP pin should only be asserted when the processor is in the Stop Grant state SLP assertion while the processor is not in the Stop Grant state is out of specification and may result in unapproved operation In the Sle
65. ter junction is used as a thermal diode with its collector shorted to ground The thermal diode can be read by an off die analog digital converter a thermal sensor located on the motherboard or a stand alone measurement kit The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached When using the thermal diode a temperature offset value must be read from a processor MSR and applied See Section 5 2 for more details See Section 5 3 for thermal diode usage recommendation when the PROCHOT signal is not asserted The reading of the external thermal sensor on the motherboard connected to the processor thermal diode signals will not necessarily reflect the temperature of the hottest location on the die This is due to inaccuracies in the external thermal sensor on die temperature gradients between the location of the thermal diode and the hottest location on the die and time based variations in the die temperature measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the T temperature can change Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor s Automatic mode activation of the t
66. the processor 2 1 1 2 Thread C1 AutoHALT Power down State C1 AutoHALT is a low power state entered when a thread executes the HALT instruction The processor thread will transition to the CO state upon occurrence of SMI INIT LINT 1 0 NMI INTR or FSB interrupt messages RESET will cause the processor to immediately initialize itself A System Management Interrupt SMI handler will return execution to either Normal state or the AutoHALT Power down state See the Intel 64 and IA 32 Architectures Software Developer s Manuals Volume 3A 3B System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the AutoHALT Power down state When the system de asserts the STPCLK interrupt the processor will return execution to the HALT state While in AutoHALT Power down state the processor threads will process bus snoops and snoops from the other thread The processor will enter a snoopable sub state not shown in Figure 1 to process the snoop and then return to the AutoHALT Power down state 12 Datasheet Low Power Features n tel 2 1 1 3 2 1 1 4 2 1 1 5 2 1 2 2 1 2 1 2 1 2 2 Datasheet Thread C1 MWAI T Power down State C1 MWAIT is a low power state entered when the processor thread executes the MWAIT C1 instruction Processor behavior in the MWAIT state is identical to the AutoHALT state except that Monitor events can cause the processor to return to the
67. truction it must be valid along with the TRDY assertion of the corresponding input output Write bus transaction ADS I O ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 31 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal loop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 I O Address strobes are used to latch A 31 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 2 A 16 3 ADSTB 0 A 31 17 ADSTB 1 BCLK 1 0 The differential pair BCLK Bus Clock determines the FSB frequency All FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing VCROSS BNR I O BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Datasheet 41 Package Mechanical Specifications and Pin I nformation Signal Name Type Description BPM 0 BPM 1 I O BPM 2 BPM 3 I O BPM 3 0 Breakpoint Monitor are breakpoint and performanc
68. tware Developer s Manual uals tp Volume 1 Basic Architecture e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A Instruction Set Reference A M e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference N Z e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide e Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Mobile Intel 945 Express Chipset Family Datasheet 309219 Mobile Intel 945 Express Chipset Family Specification Update 309220 Intel 1 O Controller Hub 7 ICH7 Family Datasheet 307013 Intel 1 O Controller Hub 7 ICH7 Family Specification Update 307014 AP 485 Intel Processor Identification and CPUID Instruction tnt 241618 Application Note Datasheet 9 N le Low Power Features 2 1 10 Low Power Features Clock Control and Low power States The processor supports low power states at the thread level and the package level A thread may independently enter the C1 AutoHALT C1 MWAIT C2 C3 and C4 low power states Package low power states include Normal Stop Grant Stop Grant Snoop Sleep and Deep Sleep When both threads are in a common low power state the central power management logic ensures the entire processor enters the respective package low power state by initiating a P LVLx P LVL2 and P LVL3 I O read to the chipset The process
69. ure trip point it will enter the lowest programmed Intel Thermal Monitor 2 performance state It is important to note that Intel recommends both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 to be enabled When PROCHOT is driven by an external agent and if only Intel Thermal Monitor 1 is enabled on the core then the processor core will have the clocks modulated If Intel Thermal Monitor 2 is enabled then the processor core will enter the lowest programmed Intel Thermal Monitor 2 performance state It should be noted that Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2 enabled via BIOS does not have any effect on external PROCHOT If PROCHOT is driven by an external agent when Intel Thermal Monitor 1 Intel Thermal Monitor 2 and Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2 are all enabled then the processor will still apply only Intel Thermal Monitor 2 PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power Datasheet m Thermal Specifications and Design Considerations in tel consumption Bi directional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper c
70. vantage of this feature is that it significantly reduces leakage while in the Stop Grant and Deeper Sleep states Note Long term reliability cannot be assured unless all the Enhanced Low Power States are enabled The processor implements two software interfaces for requesting enhanced package low power states MWAIT instruction extensions with sub state hints and via BIOS by configuring a software programmable MSR bit to automatically promote package low power states to enhanced package low power states Enhanced Intel SpeedStep Technology transitions are multi step processes that require clocked control These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states Enhanced Deeper Sleep is an exception to this rule when the Hard C4E configuration is enabled in a software programmable MSR bit This Enhanced Deeper Sleep state configuration will lower core voltage to the Deeper Sleep level while in Deeper Sleep and upon exit will automatically transition to the lowest operating voltage and frequency to reduce snoop service latency The transition to the lowest operating point or back to the original software requested point may not be instantaneous Furthermore upon very frequent transitions between active and idle states the transitions may lag behind the idle state entry resulting in the processor either executing for a longer time at the lowest op
71. ver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be de asserted to insert idle clocks This signal must connect the appropriate pins of both FSB agents DSTBN 3 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV 0 DSTBN 0 D 31 16 DINV 1 DSTBN 1 D 47 32 DINV 2 DSTBN 2 D 63 48 DINV 3 DSTBN 3 43 intel Package Mechanical Specifications and Pin I nformation Signal Name Type Description DSTBP 3 0 Data strobe used to latch in D 63 0 Signals Associated Strobe 1 0 D 15 0 DINV 0 DSTBP 0 D 31 16 DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 D 63 48 DINV 3 DSTBP 3 FERR PBE FERR Floating point Error PBE Pending Break Event is a multiplexed signal and its meaning is qualified with STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MSDOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the proce
72. wer on Reset RESET must stay active for at least two milliseconds after Vcc and BCLK have reached their proper specifications On observing active RESET both FSB agents will de assert their outputs within two clocks All processor straps must be valid within the specified setup time before RESET is de asserted Please contact your Intel representative for more implementation details RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both FSB agents RSVD Reserved All other RSVD signals can be left as No Connects SLP SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal de assertion of SLP and removal of the BCLK input while in Sleep state If SLP is de asserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state SMI SMI System Management Interrupt is
73. y as long as these features are enabled in the BI OS and supported by the processor The I ntel Thermal Monitor automatic mode and Enhanced Multi Threaded Thermal Monitoring must be enabled through BI OS for the processor to be operating within specifications ntel recommends Intel Thermal Monitor 1 and Intel Thermal Monitor 2 be enabled on the processors Intel Thermal Monitor 1 Intel Thermal Monitor 2 and EMTTM features are collectively referred to as Adaptive Thermal Monitoring features Intel Thermal Monitor 1 and Intel Thermal Monitor 2 can co exist within the processor If both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 bits are enabled in the auto throttle MSR Intel Thermal Monitor 2 will take precedence over Intel Thermal Monitor 1 However if Force Intel Thermal Monitor 1 over Intel Thermal Monitor 2 is enabled in MSRs via BIOS and Intel Thermal Monitor 2 is not sufficient to cool the processor below the maximum operating temperature then Intel Thermal Monitor 1 will also activate to help cool down the processor If a processor load based Enhanced Intel SpeedStep Technology transition through MSR write is initiated when a Intel Thermal Monitor 2 period is active there are two possible results e If the processor load based Enhanced Intel SpeedStep technology transition target frequency is higher than the Intel Thermal Monitor 2 transition based target frequency the processor load based transition will be deferred unti

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