ADATA Extreme Edition DDR2 1066+ 2GB-kit
Contents
1. voo 28 Dass s no se von paw 19 vas azo as 29 vss zo ves 601 as fof vey mam pon 80 as 20 ox 21 pato er m m sa vay pas aan vona 221 voro 2 pam ee vooa 02 mo esr re vss 182 as 22 vss B ves es a vos ves 143 Doo aas art 223 om 2a cae es vo 14 mase aa pani a84 voo 24 NG Dow es ves 105 pase 145 vss aas cko 225 vss vss 66 vs frof ves e om 186 sow 226 Dosa 2 masz er vo ton paso er no aar voo 227 pass ase os No 18 oasi 148 vas fas ao 28 vss vss er won 09 vss to paz 189 voo 2 naso lso cars 70 awae mo pase 150 Daz 190 Ba 230 Das 3 Daw i Bao am pas a81 ves 191 vona 231 vss 32 ves mf va fa vss ts aza 192 mas 232 om 33 ooa ra me ma masr 153 pazo 193 so 288 no 34 cae za icas ma pasz dea vas 19 voa 28a vss s vss 75 va ms vss__ 155 pm mes opto 285 pase mass re s ne vas mee NG 196 AB z pas ar pas 77 oom mr pase is ves 197 voo 87 vss ss vss z vwa ws ves 158 paso 198 vss 238 voDsPD naze ro vss mo soa 159 boss 19 pas 239 sao 40 Daz s Das 12 so io vss 200 Dos 240 sa ADQYE1A08 DDR2 1066 CL5 1GB 128Mx8 Pb free Re2. Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 8V 0 1V Tc 0 to 85 C Symbo CIA ET Supply Voltage CCT va w w 0 kwe es w w ve asie AO mw sw v aae O wee wwe v 8 Note 1 There is no specific device VDD supply voltage requirement for SSTL 1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF ac 4 VTT of transmitting device must track VREF of receiving device 5 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDL tied together ADQYE1A08_DDR2 1066 CL5 1GB 128Mx8 Pb free Rev 2008 09 15 Page 5 of 6 e e DA A A Wonderful Memory Package Dimensions 4 00 lt 0 157 0 80 Q105 C0 0al W002 BESE EREN 2 i 1 64 165 120 121 184 185 240 2 4 2 C Q 50 0 020 gt LIIV EDU min 4 00 c0 197 min Y E en B 55 00 2 1657 A l ON ON NO ITI 1 E 1 63 00 2 480 112 7 0 10 60 05 t 00045 3 00 0 118 gt 10 00 0 394 17 8000 70 N
3. DATA Memory Module Data Sheet A Wonderful Memory ADQYE1A08 DDR2 1066 CL5 240 Pin EPP U DIMM 1GB 128M x 64 bits General Description The ADATAs ADQYE1A08 is a 128Mx64 bits 1GB 1024MB DDR2 1066 CL5 SDRAM EPP memory module The SPD is programmed to JEDEC standard latency 800Mbps timing of 5 5 5 18 at 1 8V The module is composed of eight 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP TSOP package on a 240pin glass epoxy printed circuit board The ADQYE1A08 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply Normal VDD amp VDDQ 1 8V 0 1V e 18V SSTL 18 compatible I O e EPP Enhanced Performance Profiles support e Timing Reference DDR2 800 CL5 5 5 18 at 1 8V DDR2 800 CL4 4 4 12 at 2 0V EPP Profile 1 DDR2 1066 CL5 5 5 15 at 2 3V EPP Profile 2 e Burst Length 4 8 e Programmable Additive Latency 0 1 2 3 4 e Bi directional differential data strobe DQS and DQS e Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition e Double data rate archit
4. DM5 DM CS DQS DQS DM CS DOS DOS DOS voo 100 DQ9 W4l 01 ol DS DQ10 UO 2 102 DQ11 LO 3 UO 3 DQ12 Lo 4 DQ13 ai DQ14 WM LO 6 DQI5 MAG LO 7 DQS DQS2 Q DM2 FW DM6 DM CS DOS DOS DOIS M uN 0 DQ17 VO 1 D6 DQ13 d 2 DQ19 on DQ20 LO DQ21 M nka pan TAGA DQ23 DQS7 DQS3 DQS3 DQS7 g yi DM7 DM3 DM CS DQS DOS DM CS DOS DOS DQ24 MW IIOO LO 0 DQ25 UO 1 D3 DQ26 LO 2 DQ27 LO 3 DQ28 ILO 4 DQ29 W IO 5 DQ30 LO 6 DQ31 LO Serial PD SDA Clock Wiring Clock Input DDR2 SDRAMs CKO CKO 2 DDR2 SDRAMs SAO SAI SA2 CK1 CK1 3 DDR2 SDRAMs CK2 CK2 3 DDR2 SDRAMs BAO BA2 w gt BA0 BA2 SDRAMs DO D7 E Wire per Clock Loading A0 A15 W A0 A15 SDRAMs DO D7 TableWiring Diagrams RAS wo RAS SDRAMs DO D7 CAS W CAS SDRAMs DO D7 VppSPD SPD CKEO CKE SDRAMs DO D7 Vpp Vppo DO D8 en ce Notes L rer il VREF DO DS 1 DQx DMx DQSx DQSx resistors 22 Q 596 ODTO ODT SDRAMs DO D7 y DO D8 2 BAx Ax RAS CAS ANE resistors 100 5 SS ADQYE1A08_DDR2 1066 CL5 1GB 128Mx8 Pb free Rev 2008 09 15 Page 4 of 6 KOANA Absolute Maximum Ratings Voltage on VDD supply relative to Vss A 1 0 2 3 Ovo Voltage on VDDL supply relative to Vss az NN Note DDR2 SDRAM component specification Operation Temperature Condition sme vane ont Nae Note 1 If the DRAM case temperature is above 85 C the
5. ecture e Auto 8 Self refresh e Average Refresh period 7 8us e Off Chip Driver OCD Impedance Adjustment e On Die Termination ODT e Lead free products are ROHS compliant e EEPROM VDDSPD 3 3V Typical e PCB Height 30 00mm 1 181 Single sided component e Clock Cycle Time tCk DDR2 800 tCK 2 5ns DDR2 1066 tCK 1 875ns e Refresh to Active Refresh Command Time tRFC 127 5ns Pin Assignment E O EC O VREF pas 121 en NG CB4 CB4 201 DR AO IA af a as ncc Ba masa 128 Dos 163 vss 28 no a naro a vss se pasa 12 vas 164 NG DMS 204 vss 5 vss as mo mass s vss 125 pmo 165 nc 20s pas e maso 46 mo pass se pass 126 NG 166 vss z06 Das z paso ar vss ar Das 127 vss ser Ne cse 207 ves e vss 4s nose es ves 128 nas 168 NG CB7 208 pasa e pazo 4 nowss s Dow 19 par 169 vss 209 pas to Das so vas oo pan mao vss io voa 210 vss _ m vys s va ar vss aan pare im coer am oms ta Dos se cko o mass naz Dos 12 von a2 NO da De sa von o pass 13 vas a oms 28 vss ta vss fsa Baz o vss ia DW ama aa za Do s most ss no 9 Dos 15 ne ars vona 215 Dar m past se vooa ee Dos 136 vas are an 216 ves ar yss s an o vs aar ek amr ao a Dom n s nc s a es pos naa ext 78
6. ote CJ Co 1 Tolerance 10 127mm 0 005 Inches OS UO OO S 11008039 28 4 000 157 DO So oJ HI 0 20MM Ma x 0 0SMM Min2 1 5010 10 D059710 0047 0 2O0MMCMax Q 05MM MIm X 3 80 0157 Detail A Detail B VIEW C E Uptional ADQYE1A08_DDR2 1066 CL5 1GB 128Mx8 Pb free Rev 1 2008 09 15 Page 6 of 6
7. v 1 2008 09 15 Page 2 of 6 RATA Pin Description CKO CK2 NAME FUNCTION System Clock Active on the positive and negative edge to sample all inputs ICKO CK2 CKEO Clock Enable T Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address AO A13 Column Address A0 A9 Auto precharge A10 AP AO A13 Address BAO BA2 Banks Select DQO DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQSO DQST Bi directional Data Strobe Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device ADQYE1A08_DDR2 1066 CL5 1GB 128Mx8 Pb free Rev 1 2008 09 15 Page 3 of 6 Block Diagram e e DATA A Wondertul Memary Hz SO DQSO DQS4 DQSO AN aa DMO 5 DNA DM CS DQS DQS DQO roo DQI DQ2 DQ3 DQ4 DOS DQ6 md DQS5 DOSI FN DOSS DQSI E DMI
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