ADATA Extreme Edition DDR2 800+ 4GB-kit
Contents
1. vs s an o vss fiir oe far ao 27 ooo n s No 55 A es pos jc voo 28 pos 19 No s vo poo 19 vss as a vss zo vss as fof vss 40 pon as 20 oo z poo ot m tor sw vay pas ter vo 221 icke 2 Dan e vooa 102 nomesti w2 vss 182 as 222 vss vss 63 a wes vss__ 143 Doo tes 223 pw 2 cae amp vo 14 mase 4 paz a84 voo za NG 25 por 6 vss 105 pose 145 vss tes cko 225 vss vss e vs fie vss 146 om sow z Dosa 2 masz amp vo ton paso v7 no 17 voo 227 oos 25 Das e No 18 pos 148 vss ao 228 vss 20 vss e vob 09 vss 149 paz 189 voo 2 ooo 30 bat 70 awae wo pase 150 Daz 10 BA 29 Das pst poe i Bao t boy 151 vss 191 vo 231 vss s vss 72 va fa vss ts pom mas 22 DW 33 pom r me ma ios 153 pom 193 so 28 wo s Das za icas 18 pasz 154 vss 1 voa 24 vss s vss 75 va 15 vss__ 155 pm 5 opto 25 Doo 36 mass s me Dos 56 NG 196 AB 23 Dae sr poss 77 oor rz bos vss 197 voo zy vss ss vss 7 vwa e vss 158 paso vss 238 vopseD ss poe z vss me soa pos 19 poe 239 so o Daz s pas 12 sc j io vss zo Dos2. Vpp SPD VDD VDDQ r VREF Vss BAO BA2 A0 A15 CKE1 CKEO RAS CAS WE ODTO ODTI DQ16 DQ17 DQ18 DQ19 DQ20 DQ 1 DQ22 DQ23 DM CS DOS DOS DQ32 roo DQ33 VO 1 D12 DO DS DQ34 WHO 2 S DQ35 103 DQ36 VO 4 DQ37 WO LO 5 DQ38 IO 6 DQ39 UO 7 ELM urn eem en E DM CS DQS DOS roo Vol D5 D13 LO 2 j LO 3 DO 4 DO 5 YO 6 D9 D2 D10 BM DM CS DOS DOS DQ24 LO 0 DQ25 D11 Vol D7 y D15 DQ26 WM yO 2 j DQ27 VO 3 DQ28 LO 4 DQ29 DQ30 DQ31 e s gt m AN gt Los LO 6 VO7 a dt MT DO D15 7 Clock Wiring DO D15 DO DIS po Clock Input DDR2 SDRAMs CKO CKO 4 DDR2 SDRAMs S CK1 CK1 6 DDR2 SDRAMs BA2 SDRAMs DO D15 O p CEDE CK2 CK2 6 DDR2 SDRAMs A0 A15 SDRAMs DO D15 Wire per Clock Loading CKE SDRAMs D D15 Table Wiring Diagrams CKE SDRAMs DO D7 RAS SDRAMs DO D15 CAS SDRAMs DO D15 Notes 1 DQx DMx DOSx DQSx resistors 22 Q x 596 WE SDRAMs DO D15 2 BAx Ax RAS CAS ANE resistors 7 5 Q 596 ODT SDRAMs D0 D7 ODT SDRAMs D8 D15 ADQVDIBI6 DDR2 800 CL4 2GB 128Mx8 Pb free Rev 1 2008 09 17 Page 4 of 6 KOANA Absolute Maximum Ratings Voltage on VDD supply relative to Vss BEEN 1 0 2 3 Ovo Voltage on VDDL supply relative to Vss OD 42 5 pv Note DDR2 SDRAM component specification Operation Temperature Condition amm me uw N
3. 2z0 SM ADQVDIB16 DDR2 800 CL4 2GB 128Mx8 Pb free Rev 1 2008 09 17 Page 2 of 6 RATA Pin Description CKO CK2 NAME FUNCTION System Clock Active on the positive and negative edge to sample all inputs ICKO CK2 Clock Enable Chip Select Banks Select DQ0 DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address AO A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQSO DQS7 Bi directional Data Strobe Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO ODT1 On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device ADQVD1B16 DDR2 800 CL4 2GB 128Mx8 Pb free Rev 1 2008 09 17 Page 3 of 6 e e DATA A Wonderful Memary Block Diagram DQS0 m DOS4 A ae a NENNEN DOSO G Best a DOS2 D S2 DM2 35 QQ AN UJU DM3 A
4. DATA Memory Module Data Sheet A Wonderful Memory ADQVD1B16 DDR2 800 CL4 240 Pin EPP U DIMM 2GB 256M x 64 bits General Description The ADATAs ADQVD1B16 is a 256Mx64 bits 2GB 2048MB DDR2 800 CL4 SDRAM EPP memory module The SPD is programmed to JEDEC standard latency 800Mbps timing of 5 5 5 18 at 1 8V The module is composed of sixteen 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP TSOP package on a 240pin glass epoxy printed circuit board The ADQVD1B16 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data l O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply Normal VDD amp VDDQ 1 8V 0 1V e 1 8V SSTL 18 compatible I O e EPP Enhanced Performance Profiles support Timing Reference DDR2 800 CL5 5 5 18 at 1 8V DDR2 800 CL4 4 4 12 at 2 0V EPP Profile 1 DDR2 800 CL4 4 4 11 at 2 0V EPP Profile 2 Burst Length 4 8 Programmable Additive Latency 0 1 2 3 4 Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition Double data rate archit
5. ae Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 8V 0 1V Tc 0 to 85 C Symbo CIA ee Supply Voltage DO ee CCT OS INC o ar oom o o Eny ve ow 9 Y O9 ume AO Seem C Gee OY oM CCT m oves Xem Y o9 Note 1 There is no specific device VDD supply voltage requirement for SSTL 1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF ac 4 VTT of transmitting device must track VREF of receiving device 5 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDL tied together ADQVDIB16 DDR2 800 CL4 2GB 128Mx8 Pb free Rev 1 2008 09 17 Page 5 of 6 Package Dimensions HEE t mn 4 00 lt 0 157 2 9010 20 0 098 0 008 0 890 05 0 0311 0 002 Detail A ADQVDIB16 DDR2 800 CL4 2GB 128Mx8 Pb free 184 185 a BEEN EE US Note e DA A A Wondertul Memory lit b 641165 e Lili 0 50 0 020 min 4 00 C0 157 2
6. ecture Auto amp Self refresh Average Refresh period 7 8us Off Chip Driver OCD Impedance Adjustment On Die Termination ODT Lead free products are RoHS compliant e EEPROM VDDSPD 3 3V Typical PCB Height 30 00mm 1 181 Double sided component Clock Cycle Time tCK DDR2 800 tCK 2 5ns Refresh to Active Refresh Command Time tRFC 127 5ns Pin Assignment pin romt pon ren Pin reont pie Baek Pin Baek Pin Boek VREF pos 121 461 NC CB4 CB4 201 DR AO me tate tet te 9 a as No cB s3 masa 12s pas 163 vss 28 wo 4 oar a vss ee pasa 1a vss 164 NG DMS 204 vss 5 vss 4 Nc oss s vss 125 pmo 165 nc 20s pas 6 maso 4e Nc Dose se Dos 126 NG 166 vss 206 Dos 7 pase ar vss s pos ur vss 17 Ne cse 207 vss 8 vss 45 Noce2 es vss 128 Doe 168 NG CB7 208 Dou 9 noz 4 woes s poo 19 par 169 vss 209 pas to Dos so vss o pow 130 vss io voa 210 vss vss s va es vss isi Dor im ck 2 oms 2 pa s ceo s moss 2 pais 12 von a2 wo ta Dos ss von o poss 13 vss a oms 213 vss ta vss 5 sm o f vss t ow za AM ata Doo 15 mos 55 wo 9 poc 15 Ne pos voa 215 bou 16 Dos se vooa s Dos 136 vss 176 A2 6 vss v
7. min LALEALIBU UU UBL DO e a A E ET E lt 5 55 00 2 165 4 1 210 10 0 035 29 008 72 3 00 0 1189 10 00 0 394 17 8000 70 1 Tolerance 0 127mm 0 005 Inches 4 00 0 15 7 0 2 0MM Mo x 0 05MMCMin is 1 500 10 4 4 0 20MM lt Max gt S 0 059 0 004 mee E O 00 e Detoil B VIEW C C CUptionald Rev 1 2008 09 17 Page 6 of 6
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