ADATA Extreme Edition DDR2 800+ 2GB-kit
Contents
1. NAME FUNCTION System Clock Active on the positive and negative edge to sample all inputs ICKO CK2 CKEO Clock Enable T Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address AO A13 Column Address A0 A9 Auto precharge A10 AP AO A13 Address BAO BA2 Banks Select DQO DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQSO DQST Bi directional Data Strobe Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device ADQVDIAO8 DDR2 800 CL4 IGB 128Mx8 Pb free Rev 2008 09 17 Page 3 of 6 Block Diagram S0 DQSO DQS4 DQSO AN DOS DMO a DM4 DQO DQI DQ DQ3 DQ4 DO DOS DQS5 DOSI DOSS DQSI s DM1 DM5 DM CS DOS DOS DOS roo Deo AW ILO1 DQ10 UO 2 DQ11 LO 3 DQ12 DQ13 DQ14 DQ15 Toc DOS DQS2 Q DM2 w DM62. 2 1657 D 0 50 0 020 min 4 00 0 137 min Ie 7 0 10 60 05 t 000489 3 00 0 118 gt 10 00 0 394 17 8000 707 1 Tolerance 0 127mm 0 005 Inches 4 00 0 15 7 0 20MM Ma x 0 0SMM Min2 1 5010 10 0 059 0 004 0 ZOMMCMgx O 05MM lt Min X Detail B VIEW ETE Uptional Rev l 2008 09 17 Page 6 of 6
3. DQ16 M DQ17 DQI8 DQ19 DQ20 DQ21 M DQ22 DQ23 DQS3 Q DQS7 DQS3 DQS7 a Ax DM7 DM3 DM CS DOS DOS DQ24 W 1 00 DQ25 VO1 D3 DQ26 UO 7 DQ27 LO 3 DQ28 W104 DQ29 TW LO 5 DQ30 LO 6 DQ31 LO 7 Serial PD lt gt SDA SAO SAl SA2 BAO BA2 W BA0 BA2 SDRAMs DO D7 A0 A15 W A0 A15 SDRAMs DO D7 RAS W RAS SDRAMs DO D7 CAS wW gt CAS SDRAMsDO D7 VppSPD SPD CKEO LD CKE SDRAMsD0 D7 Vpp Vppo x DO D8 WE NE WE SDRAMs DO D7 VREF DO DS a D7 ODTO y ODT SDRAMs D0 D Ves x x ch SES ADQVD1A08 DDR2 800 CL4 1GB 128Mx8 Pb free Rev e e DATA A Wondertul Memory DM CS DOS DOS LO 0 DM CS DOS DOS LO 0 Loi UO 2 LO 3 LO 4 LO 5 LO 6 LO D5 DM CS DQS DOS LO 0 Vol LOJ LO 3 LO 4 LOS LO 6 UO 7 D6 DM CS DOS DOS LO 0 Clock Wiring Clock Input DDR2 SDRAMs CRU CKO 2 DDR2 SDRAMs CK1 CK1 3 DDR2 SDRAMs CK2 CK2 3 DDR2 SDRAMs Wire per Clock Loading Table VViring Diagrams Notes 1 DQx DMx DQSx DQSx resistors 22 Q 5 2 BAx Ax RAS CAS ANE resistors 100 5 2008 09 17 Page 4 of 6 KOANA Absolute Maximum Ratings Voltage on VDD supply relative to Vss ven 1 0 2 3 Ovo Voltage on VDDL supply relative to Vss az V Note DDR2 SDRAM component specification Operation Temperature Condition s me mim Note 1 If the DRAM case temperature is above 85 C the Auto Refre
4. sh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 8V 0 1V Tc 0 to 85 C Sumbo MADI IL m mim Supply Voltage eeng va w we Cv kwe es w w v s asie 1 mw sw v aae 7 w wee wwe v 8 Note 1 There is no specific device VDD supply voltage requirement for SSTL 1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF ac 4 VTT of transmitting device must track VREF of receiving device 5 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDL tied together ADQVDIAO8 DDR2 800 CL4 IGB 128Mx8 Pb free Rev 2008 09 17 Page 5 of 6 e e DA A A Wonderful Memory Package Dimensions EEE GREE 2 i 133 Us rre pl LT TT HTHH UH 1 NT d 63 00 2 480 4 000 157 Note LC e E CO Oo US E an 100486 0397 2S DO Os r I WES I 4 w 0 80 Q105 0 021 2 002 3 80 0157 Detail A ADQVDIAO8 DDR2 800 CL4 IGB 128Mx8 Pb free 1 64 165 120 121 184 185 240 2 2 C 55 00
5. ure e Auto amp Self refresh e Average Refresh period 7 8us e Off Chip Driver OCD Impedance Adjustment e On Die Termination ODT e Lead free products are ROHS compliant e EEPROM VDDSPD 3 3V Typical e PCB Height 30 00mm 1 181 Single sided component e Clock Cycle Time tCk DDR2 800 tCK 2 5ns e Refresh to Active Refresh Command Time tRFC 127 5ns Pin Assignment Pir Front pon Front L L LELE LR Pin Boek O VREF pas 121 e NC cB4 CB4 om EE me tate E te m zl a as ncc Ba masa 12s pos 163 vss 28 nc a oar a vss ee pasa leiwe 164 NG DMS 204 vss 5 vss 4 mo mass s vss 125 pmo 15 nc Lal pas e maso 46 mo pass se pass 126 NG ml vss 206 nas z paso ar vss s pas 127 vss ser nc cee 207 we e vss aa nose s vss 128 pas 168 mo cer 208 mu e oe 4 nowss s caw 19 par 169 vss Lal pas w oo o vss Lal pan 130 vss ml vona 210 vss _ nl vys s va ar vss isi pare im op Lal oms m2 oo se cko o mass naz ars 12 von 22 ne _ da De sa von o pass 13 vss ml oms 213 vss nl vss a Baz Lal vss daa DW ama AM za Do s mas ss nc 9 paw 15 Ne ars vona 215 mm ml pas se vooa ee pos 136 vss are a 216 ves ar ves s an o vs aar ek far ao a me s nc a a es pos naa sekt as
6. voo 218 Dass ml nc se v paw 19 vss azo as 29 vss al vss ai as ml me 40 pon 10 as 220 ck al pato er m ei sa vay Dot aan vona 221 oe 2 Dan ee vooa 12 NC TEST re vss el as 222 vss al ves es a vos vss 143 pazo aas art 223 pme al cae ea vo ml mase aa nemmi voo 2a nc zl cai es ves vos pase 145 vss 185 cko 225 vss vss ee vs fie ves 146 om ml om ll Dosa 27 masz er vo tor paso er NG aar voo 227 pass 28 ase os Ne 18 oasi maa vss ml ao 228 vss sl vss er won 09 vss 149 paz 189 voo 2 naso al cars 70 awae mo pase 150 Daz ml Ba 280 Das al oos i sa am pas 151 ves 191 vona 231 vss sl vss mf va 42 vss 52 aza mas 282 om sl me ra me ma nee 153 pazo 193 sa 233 nec al ms za icas ml me asa vss 19 voa 24 vss s vss 75 va me ves 155 pm mes opto 285 me mass re sn me vas mee NG 196 AB z pas zl pas 77 on mr pase a7 ves 197 voo Lal vss sl vss ma vona tis ves Ulm paso 198 vss 238 VDDSPD sl Daz ro vss mo soa Lil nem 199 pas 239 sao 40 Daz s case 12 so io vss 200 pasz Lal sa ADQVDIAO8 DDR2 800 CL4 IGB 128Mx8 Pb free Rev 2008 09 17 Page 2 of 6 KATA cooo Pin Description CKO CK2
7. x DATA Memory Module Data Sheet A Wonderful Memory ADQVD1A08 DDR2 800 CL4 240 Pin EPP U DIMM 1GB 128M x 64 bits General Description The ADATAs ADQVD1A08 is a 128Mx64 bits 1GB 1024MB DDR2 800 CL4 SDRAM EPP memory module The SPD is programmed to JEDEC standard latency 800Mbps timing of 5 5 5 18 at 1 8V The module is composed of eight 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP TSOP package on a 240pin glass epoxy printed circuit board The ADQVD1A08 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply Normal VDD 8 VDDQ 1 8V 0 1V e 1 8V SSTL 18 compatible I O e EPP Enhanced Performance Profiles support e Timing Reference DDR2 800 CL5 5 5 18 at 1 8V DDR2 800 CL4 4 4 12 at 2 0V EPP Profile 1 DDR2 800 CL4 4 4 11 at 2 0V EPP Profile 2 e Burst Length 4 8 e Programmable Additive Latency 0 1 2 3 4 e Bi directional differential data strobe DQS and DQS e Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition e Double data rate architect
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