ADATA Extreme Edition DDR3 1600X 4GB-kit
Contents
1. 31938 12 00 4 72 44 gt ON X LN MS OU Hole 30 00 1181 10 gt A TTT 5175 203 74 2X 47 00 1850 39 IL ILUS TANZA 47 0001850 39 A e O Od oF o O Lo FP BB o CN N NY Nu O CU e 0 80 9 05 631 501 97 Detail A ras 3 80 149 61 Dow 2 10 82 68 4X Note 1 Tolerance 0 15mm 5 91mils MI64G1B16 DDR3 1600X CL 7 2GB 128Mx8 Pb free Detail B Rev aan DUTO 2 00 196 85 1 90 0 10 59 06 3 94 3 00 0 10 118 1143 94 4X MN la QU Y y ur Qul A elc 00 Oo Viv OS NIM Mm A e e DATA vosuu 0 90 19 69 min 1 27t0 10 50 00 3 94 0 20MMCMa x 0 09MMCMin 0 20MM lt Ma x gt 0 0S5MMCMin gt VIEW ES 2008 10 13 UP TIONAL Page 6 of 62. se a 9 Do vss 176 voo 216 pog 7 vs s vo o oos sr pais far as am vss 8s vaio ss as vss 138 pas ve as ze Dor 19 Dom so m poe 19 vss 1 voo 29 pos vss 60 vwm 10 po 140 Dom 180 as 220 vss z poe 61 a m vss vay pon er Mm zat om 2 var c vom 102 mase 2 vss 182 voo 22 wo 25 vss e cnc 103 pase 143 pm 185 voo 23 vss 2 mas amp ikinc 104 vss M4 NO 184 cko 24 Dow 25 Dos 65 vno 105 pos 145 vss 185 cko 225 Dos vss 66 vob 106 bos 146 pom 186 voo 226 vss 2 Dois 67 vrerca 107 vss wr Dazs ser wc EvENT 227 Doo 25 Daio 68 NO 108 pos 148 vss 188 ao 228 Do vss e vom 109 pasz 149 pos 189 voo ze vss 30 Dam 70 mom wo vss 150 paz 190 BA 29 om 5 pos fpr bw m masr isi vss 11 voo 21 wo s vss 72 vw n pos ts us 152 mas 232 vss 3 moss 7s me ns vss 153 No 193 so 233 oo s Dass za icas 114 Dos 154 vss 194 voo 234 Dae s vss 75 v 15 pos 155 pos 195 opo 23 vss 36 Baz 76 sinc we vss 156 DOM 196 A 25 voDSPD 5r pox 77 ovino nz sw 57 vss 197 voo 2v sm ss vss 78 vw nsf sco 158
3. DATA vosuu Block Diagram S1 penis E pena DQSO 3 DQS4 7 ici TSE Da o Nu ue EE dus DM CS DOS DOS DM CS DOS DOSA DM CS2 DOS DQS DM CS DOS DOS DQO DQ DQ DO1 DQ e xl UA U12 DO4 DO DOS DO DO6 DO DO7 DO DOS14 Vss Vss DQS1 DM1 mmu DM CS DOS DOS DQS8 DQ DO9 DO DQ10 DQ DQ11 DQ DQ12 DQ DQ13 DQ DQ14 DQ DQ15 DQ Vss Vss DQS2 a pase EN DM2 EIN BE DM CS DOS DOS DM CS2 DOS DOSA DM CS2 DOS DQS DM CS DOS DQS DO16 DQ DQ17 pa DQ18 DQ DQ19 po U6 U14 DQ20 lpg DQ21 pa DQ22 DQ DQ23 loa pasas YS ib x DQS3 o DM3 ri 5 E DM CS DOS DQS DM CS DOS DOSA DQ24 DQ DQ25 Da DQ26 DQ DQ27 loa U11 DQ28 po DQ29 pa DQ30 DO DQ31 Ipaq Vss Vss Vss Vss a A E V BAO BA2 BAO BA2 SDRAMs UO U15 DDSPD SPD A0 A15 e A0 A15 SDRAMs UO U15 Vpp VppqQ UO U15 Rank1 U8 U18 CKE1 gt CKE SDRAMs U8 U15 V UO U15 REFDQ So ae CKEO CKE SDRAMs UO U7 Vss UO U15 a CK1 RAS RAS SDRAMs UO U15 TRON su UO U15 cki o n CAS CAS SDRAMs UO U15 WE gt WE SDRAMs UO U15 E E ODTO gt ODT SDRAMs UO U7 WP SDA ODT1 gt ODT SDRAMs U8 U15 AO A1 A2 CKO gt CK SDRAMs UO U7 OUS CK1 CK SDRAMs U8 U15 Note 1 For each DRAM a unique ZQ resistor is connected to ground The ZQ resistor is 240 Ohm 1 2 Address mirroring MI64G
4. neces 198 No 295 soa 39 Noceo0 r9 No mo sw 159 Nocss 199 vss 239 vss 4 woos so vss 120 vrm io vss 20 poe 240 vr MI64GIB16 DDR3 1600X CL 7 2GB 128Mx8 Pb free Rev 1 2008 10 13 Page 2 of 6 Kon Pin Description CKO CK1 NAME FUNCTION System Clock Active on the positive and negative edge to sample all inputs CKO CK1 Clock Enable Chip Select Banks Select DQ0 DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address A0 A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQSO DQS7 Bi directional Data Strobe Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO ODT1 On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device MI64G1B16 DDR3 1600X CL 7 2GB 128Mx8 Pb free Rev 1 2008 10 13 Page 3 of 6 gt
5. DAT Memory Module Data Sheet A Wonderful Memory MI64G1B16 DDR3 1600X CL7 240 Pin XMP U DIMM 2GB 256M x 64 bits General Description The ADATA s MI64G1B16 is a 256Mx64 bits 2GB 2048MB DDR3 1600 CL7 SDRAM XMP memory module The SPD is programmed to JEDEC standard latency 1333Mbps timing of 9 9 9 24 at 1 5V The module is composed of sixteen 128Mx8 bits CMOS DDR3 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TDFN package on a 240pin glass epoxy printed circuit board The MI64G1B16 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply Normal VDD amp VDDQ 1 5V x 0 075V e 1 5V SSTL 15 compatible I O e XMP Extreme Memory Profile support Timing Reference DDR3 1333 CL9 9 9 24 at 1 5V DDR3 1600 CL 7 7 7 20 at 1 8V XMP Profile 1 Burst Length 4 8 Programmable Additive Latency 0 CL 2 or CL 1 clock Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and DOS transition with CK transition Addresses are mirrored for second rank Average Refresh Peri
6. I1IB16 DDR3 1600X CL 7 2GB 128Mx8 Pb free Rev 1 2008 10 13 Page 4 of 6 RATA Absolute Maximum Ratings Voltage on VDD supply relative to Vss 0 4 1 975 Voltage on VDDQ pin relative to Vss VDDQ 0 4 1 975 Voltage on any pin relative to Vss VIN Vout 0 4 1 975 Storage temperature TStg 55 100 Note DDR3 SDRAM component specification Operation Temperature Condition amm vane um e Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 5V 0 075V Tc 0 to 85 C omes veac orvon exem v oa eee 7 7 vw wem owwme v Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 The AC peak noise on VREF may not allow VREF to deviate from VREF DC by more than 1 VDD for reference approx 15mV 4 For reference approx VDD 2 15mV MI64G1B16 DDR3 1600X CL 7 2GB 128Mx8 Pb free Rev 2008 10 13 Page 5 of 6 Package Dimensions UO U1 U2 U3 U4 U5 U6 U7 a O O O ol 9 o O O El 1 48 49 120 j Us U14 U13 U12 U11 U10 U9 Us C hi O O O O O O O O 240 169 168 121 1 53 506 0c 30 905 128 95 076 77 m e S
7. od 7 8us at lower then TCASE 85 C 3 9us at 85 C TCASE s 95 C 8 bit pre fetch On Die Termination using ODT pin Internal self calibration Internal self calibration through ZQ pin RZQ 240 ohm x 1 e EEPROM VDDSPD 3 3V Typical PCB Height 30 00mm 1 181 Double sided component Clock Cycle Time tCK DDR3 1333 tCK 1 5ns DDR2 1600 tCK 1 25ns Refresh to Active Refresh Command Time tRFC 110ns Lead free products are ROHS compliant Pin Assignment nf Erom pem romi Pin mont fpr Baek Pin Baek Pin Baek VREFDQ pos EEN 461 NC DM8 DM8 201 pox el me tate ee tee tet a Doo 4 wo js vss v3 pos 18 vss 203 om a oar a vss 84 mos ta vss 164 NocBe 204 nc 5 vss 4 noose a5 pasa 125 pmo 165 noosr 205 vss 6 maso 46 Noces se vss 126 NO 166 vss 206 Dos 7 vaso ar vss j bow vr vss 17 no 207 pas 8 vss 48 nc 88 pos 128 pas 16 meser 208 ves 9 no s wo a vss 19 par 169 ckernc 209 Dom Das so ceo s Dow 130 vss 10 voo 20 Do vss st vo je com i ar im ms an vss Dos s sa vss Das 12 ma a oms 1 Dos ss No o mas 13 vss 43 voo 213 wo m vss 54 vo o pos 134 om a A2 aa ves 15 mos ss an 9 vss 15 wc 5 ao 25 poe s Das
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