ADATA Extreme Edition DDR2 800G 4GB-kit
Contents
1. EEE HEHE _ 64 165 _ _ 120 1841185 80 E pE an 0 500 020 min F cxt ON Yu o Ne eee E A GEA A C J 2 55 002 165 1 97 0 10 0 05 9 004 45 3 00 0 118 10 00 0 394 17 8000 70 1 Tolerance 0 127mm 0 005 Inches 4 00 0 157 0 2 0MM Mo x 0 OSMMC Min gt u ipid is E 0 COMMCMax a Qa C 0 059 0 004 ores que e Detail B MME dE L CUptional Rev 0 2009 02 12 Page 7 of 72. vs s an js vss r oe mr a 217 poo s No ss mw pas 138 ext voo zt pos 19 No s vo je poo 9 vss as 219 vss m vss o a 10 vss no Dow 180 as 20 oe a poo ot ror sw tay pos 181 vooo 221 ike DQ11 VDDQ 102 NC TEST 142 182 222 ws e e ww vw e ma e m e 2 cae voo 194 mase 4 paz 184 voo 2a wo por 6 vss 105 pose 14s vss 188 cko 225 vss vss e vss 106 vss 146 pm 186 ico 226 pasa 27 masz amp vo tor paso j v7 wo 187 voo 227 pos 25 pos e No 108 pos 148 vss 188 ao 228 ves vss e vo 109 ves voz 189 voo 22 poo 30 cars 70 AP ro Dos 150 paz 190 BA 230 Das pst poe hr bo im pov 151 vss 191 vooa 231 vss s vss f vwa 2 vss t pom 192 mas 232 DW 33 pom r me ns mos 153 pom 193 so 238 nec s bas za iow 114 pos 154 vss 194 voa 234 vss s vss 75 von ns ves 155 pm 195 opm 23 poo mass s e pos Nc 196 as 236 Doo sr poss 77 oor nz bos vss 197 voo zr vss 38 vss 7s vooa 118 vss tse paso 198 vss 238 vopseD poe z vss ne soa__ 159 pos 199 poe 239 so 4 caer so pos wo sc vss 20 pov j z0 SM HYQV
3. 37 WH 110 5 DQ38 LO 6 DQ39 1O 7 a a re d a ae RE DM CS DQs DQS E roo roo VO1 D5 D13 ro LO 3 1O 4 LO 5 VO6 D9 DM CS DQS DQS roo UO D6 j D14 Lo2 l LO 3 LO 4 LO 5 L O 6 LO 7 a a DM CS DQs DQS B DQ56 W 1 0 0 D11 DQ57 r01 D7 D15 DQ58 1 110 2 DQs9 LO 3 DQ60 DQ61 I DQ62 DQ63 cc Ie aie VDD VDDQ M o Clock Wiring B SDA VgEF LI DO D15 WP Clock Input DDR2 SDRAMs AO Al A2 Ves DO D15 CK0 CK0 4 DDR2 SDRAMs SAO SAI SA2 CK1 CK1 6 DDR2 SDRAMs BAO BA2 BAO BA2 SDRAMs DO D15 CK2 ICK2 6 DDR2 SDRAMs A0 A15 9 A0 A15 SDRAMs DO D15 D2 D10 TS Wire per Clock Loading CKE gt CKE SDRAMs D8 D15 Tabien iing Diagramme CKE0 gt CKE SDRAMs D0 D7 RAS wW RAS SDRAMs DO D15 CAS wW CAS SDRAMs D0 D15 Notes E 1 DQx DMx DOSx DQSx resistors 22 Q 5 WE W gt WE SDRAMs D0 D15 2 BAX Ax RAS CAS ANE resistors 7 5 Q 5 ODTO _ gt ODT SDRAMs DO D7 ODT ODT SDRAMs D D15 HYQVEI1B16 DDR2 800G CL 5 2GB 128Mx Pb free Rev 0 2009 02 12 Page 5 of 7 PONTA oa Absolute Maximum Ratings Voltage on VDD supply relative to Vss VDD 1 0 2 3 NEN Voltage on VDDQ supply relative to Vss 0 5 2 3 EE NN Voltage on VDDL supply relative to Vss 0 5 2 3 pv Voltage on any pin relative to Vss 0 5 2 3 pv Note DDR2 SDRAM component specificat
4. EIBI6 DDR2 800G CL 5 2GB 128Mx 8 Pb free Rev 0 2009 02 12 Page 3 of 7 PONTA ooi Pin Description CK0 CK2 FUNCTION System Clock Active on the positive and negative edge to sample all inputs CK0 CK2 Clock Enable SO S1 Chip Select Banks Select DQ0 DQ63 Data Data and check bit inputs outputs are multiplexed on the same pins Masks system clock to freeze operation from the next clock cycle CKE should be enabled at least on cycle prior new command Disable input buffers for power down in standby Disables or Enables device operation by masking or enabling all input except CK CKE and L U DQM Row Column address are multiplexed on the same pins Row Address AO A13 Column Address A0 A9 Auto precharge A10 AP Selects bank to be activated during row address latch time Selects bank for read write during column address latch time DQS0 DQS Data Strobe Bi directional Data Strobe DQS0 DQS7 When high termination resistance is enabled for all DQ DQ and DM pins assuming the ODTO ODT 1 On Die Termination function is enabled in the Extended Mode Register Set This pin is recommended to be left No Connection on the device HYQVEIBI6 DDR2 800G CL 5 2GB 128Mx8_Pb free Rev 0 2009 02 12 Page 4 of 7 DATA vosuu Block Diagram DQS4 w E PM Y e DM CS DQS DQS DQ32 lOO DQ33 LO 1 2 DO a D8 DQ34 W4 ro 2 d DQ35 L O 3 DQ36 1O 4 DQ
5. e r DA A A Wonderful Memory DATA Memory Module Data Sheet A Wonderful Memory HYQVE1B16 DDR2 800G CL5 240 Pin O C U DIMM 2GB 256M x 64 bits General Description The ADATA s HYQVE1B16 is a 256Mx64 bits 2GB DDR2 800 CL5 SDRAM over clocking memory module The SPD is programmed to JEDEC standard latency 800Mbps timing of 5 5 5 18 at 1 8V The module is composed of sixteen 128Mx8 bits CMOS DDR2 SDRAMs in FBGA package and one 2Kbit EEPROM in 8pin TSSOP TSOP package on a 240pin glass epoxy printed circuit board The HYQVE1B16 is a Dual In line Memory Module and intended for mounting onto 240 pins edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operating frequencies programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply Normal VDD amp VDDQ 1 8V 0 1V e 1 8V SSTL 18 compatible I O Timing Reference DDR2 800 CL5 5 5 18 at 1 8V DDR2 800 CL5 5 5 12 at 2 0V Burst Length 4 8 Programmable Additive Latency 0 1 2 3 4 Bi directional differential data strobe DQS and DQS Differential clock input CK CK operation e DLL aligns DQ and DQS transition with CK transition Double data rate architecture Auto amp Self refresh e Average Refresh period 7 8us Of
6. f Chip Driver OCD Impedance Adjustment On Die Termination ODT Lead free products are RoHS compliant e EEPROM VDDSPD 3 3V Typical e PCB Height 30 00mm 1 181 Double sided component Clock Cycle Time tCK DDR2 800 tCK 2 5ns Refresh to Active Refresh Command Time tRFC 127 5ns HYQVEIBI6 DDR2 800G CL 5 2GB 128Mx 8 Pb free Rev 0 2009 02 12 Page 2 of 7 PONTA Pin assignment Front Front Front Back Back Back Gila el ee lial mT e 2 vss 42 Noc s vss 122 poas 162 wo ces 202 DW 9 Do as Noc 83 masa 1s pas 163 vss 203 wo o a vss ee pos ta vss 164 No Due 204 vss 5 vss 4 No ose ss vss 125 ovo 165 nc 205 pass 6 maso 4e Nc Dose se pass 126 Nc 166 vss 206 Dos 7 pos ar vss 87 pos j v7 vss ser no cee 207 vss 8 vss 4s Nocm2 s vss 18 Doe 168 wo ce 208 pou 9 paz 4 noces s Doo 19 por 169 vss 20 pas w Dos s vss 9 pou 10 vss 1 vooo 210 vss vss s va o vss ist paz n ck 2n oms 12 poe 52 creo s moss pam 172 woo a wo s Dos ss vo o poss 13 vss 18 As 213 vss u vss 54 sa 94 vss 1 ow AM ata Doo s most 55 nc o poc 15 wc urs voo zs pog 6 pas se vooa pass 136 vss ie A2 216 vss piv
7. ion Operation Temperature Condition Soi me um a Note 1 If the DRAM case temperature is above 85 C the Auto Refresh command interval has to be reduced to tREFI 3 9us DC Operating Condition Voltage referenced to Vss OV VDD amp VDDQ 1 8V 0 1V Tc 0 to 85 C Parameter Symbol Min Max Unit Note Supply Voltage VDD 1 7 V Input Reference Voltage 0 49 x VDDQ 0 51 x VDDQ pov 1 2 Termination Voltage VTT VREF 0 04 VREF 0 04 v 3 Note 1 There is no specific device VDD supply voltage requirement for SSTL_1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 2 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 3 Peak to peak ac noise on VREF may not exceed 2 VREF ac 4 VTT of transmitting device must track VREF of receiving device 5 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDDL tied together HYQVEIBI6 DDR2 800G CL 5 2GB 128Mx8_Pb free Rev 0 2009 02 12 Page 6 of 7 Package Dimensions p a B 133 3545250 t Dm 4 00 0 157 2 o 90t0 20 0 098 0 008 0 8940 05 0 031 0 002 Detail A HYQVEIB16 DDR2 800G CL 5 2GB 128Mx8 Pb free Note Li DA A A Wondertul Memory
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