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Intel Core Core™2 Quad Processor Q9400 (6M Cache, 2.66 GHz, 1333 MHz FSB)

1. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VID SEL VSS_MB_ VCC MB VSS_ VCC_ MES ves VOG VEG vss VEG MEE ECT REGULATION REGULATION SENSE SENSE vas ves VCC vss VCC VCC VSS VCC VCC VID7 FC40 VID6 VSS VID2 VIDO vss VCC vss VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VRDSEL PROCHOT FC25 VCC vss VCC VCC VSS VCC VCC VSS FC8 vss VID4 ITP CLKO vss FC24 VCC vss VCC VCC VSS VCC VCC VSS A35 A34 VSS ITP CLK1 BPMO BPM1 VCC vss VCC VCC VSS VCC VCC VSS VSS A33 A32 vss RSVD vss VCC VSS VCC VCC VSS VCC VCC VSS A29 A31 A30 BPM5 BPM3 TRST VCC VSS VCC VCC VSS VCC VCC VSS VSS A27 A28 VSS BPM4 TDO VCC vss VCC VCC VSS VCC SKTOCC VSS RSVD VSS RSVD FC18 VSS TCK VCC VSS A22 ADSTB1 VSS FC36 BPM2 TDI VCC VSS VSS A25 RSVD VSS DBR TMS VCC VSS A17 A24 A26 FC37 IERR vss VIT OUT VCC VSS VSS A23 A21 VSS FC39 RIGHT FCO BOOT VCC VSS A19 vss A20 PSI VSS EIECT VCC VSS A18 A16 VSS TESTHI1 TDI M MSIDO VCC VSS VSS A14 A15 vss RSVD MSID1 VCC VSS A10 A12 A13 FC30 FC29 TDO_M VCC VSS VSS AQ A1 vss DPRSTP COMP1 VCC VSS ADSTBO vss AS pERDS vss COMP3 PBE VCC VSS A4 RSVD vss INIT SMI DPSLP VCC VSS VSS RSVD RSVD VSS IGNNE PWRGOOD THER VCC VSS REQ2 Abi AT STPCLK rpg vss VCC VSS VSS A3 AGH vss SLP LINT1 VCC VSS REQ3 VSS REQO A20M vss LINTO VTT_OUT VCC VCC VCC VCC VCC VCC VCC VSS REQ4 R
2. Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment n Land Name igi oos Direction cu Land Name gi edad Direction AH30 VCC Power Other AK16 VSS Power Other AJ1 BPM1i Common Clock Input Output AK17 VSS Power Other AJ2 BPMO Common Clock Input Output AK18 vcc Power Other AJ3 ITP CLK1 TAP Input AK19 VCC Power Other AJ4 VSS Power Other AK20 VSS Power Other AJ5 A343 Source Synch Input Output AK21 VCC Power Other AJ6 A35 Source Synch Input Output AK22 VCC Power Other AJ7 VSS Power Other AK23 VSS Power Other AJ8 VCC Power Other AK24 VSS Power Other AJ9 Vcc Power Other AK25 VCC Power Other AJ10 VSS Power Other AK26 VCC Power Other AJ11 VCC Power Other AK27 VSS Power Other AJ12 VCC Power Other AK28 VSS Power Other AJ13 VSS Power Other AK29 VSS Power Other AJ14 VCC Power Other AK30 VSS Power Other AJ15 VCC Power Other AL1 FC25 Power Other AJ16 VSS Power Other AL2 PROCHOT Asynch CMOS Input Output AJ17 VSS Power Other AL3 VRDSEL Power Other AJ18 VCC Power Other AL4 VID5 Asynch CMOS Output AJ19 VCC Power Other AL5 VID1 Asynch CMOS Output AJ20 VSS Power Other AL6 VID3 Asynch CMOS Output AJ21 VCC Power Other AL7 VSS Power Other AJ22 VCC Power Other AL8 vcc Power Other AJ23 VSS Power Other AL9 VCC Power Other AJ24 VSS Power Other AL10 VSS Power Other AJ25 VCC Power Other AL11 VCC Power Oth
3. Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land Miss oc Direction Land Name Land Mir sei ind Direction VCC AF9 Power Other VCC AK12 Power Other Vcc AG11 Power Other VCC AK14 Power Other VEC AG12 Power Other VCC AK15 Power Other VCC AG14 Power Other VEG AK18 Power Other VCC AG15 Power Other VCC AK19 Power Other Vcc AG18 Power Other VCC AK21 Power Other VCC AG19 Power Other VCC AK22 Power Other Vcc AG21 Power Other VCC AK25 Power Other VCC AG22 Power Other VCC AK26 Power Other YCC AG25 Power Other Vcc AK8 amp Power Other Vcc AG26 Power Other VCC AK9 Power Other VCC AG27 Power Other VCC AL11 Power Other VCC AG28 Power Other VCC AL12 Power Other VCC AG29 Power Other VCC AL14 Power Other VCC AG30 Power Other VCC AL15 Power Other VCC AG8 Power Other vcc AL18 Power Other VCC AG9 Power Other VCC AL19 Power Other VCC AH11 Power Other VCC AL21 Power Other Vcc AH12 Power Other VCC AL22 Power Other VCC AH14 Power Other VCC AL25 Power Other VCC AH15 Power Other VCC AL26 Power Other VCC AH18 Power Other vcc AL29 Power Other VCC AH19 Power Other VCC AL30 Power Other Vcc AH21 Power Other vcc AL8 Power Other VCC AH22 Power Other VCC AL9 Power Other Vcc AH25 Power Other VCC AM11 Power Other Vcc AH26 Power Other VCC AM12 Power Other VCC AH27 Power Other VCC AM14 Power Other VCC AH28 Power Other VEE AM15 Power Other WCC A
4. 2 6 2 DC Voltage and Current Specification Table 2 3 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 10 VID Range VID 0 8500 a 1 3625 V 1 Processor Number V QX9770 3 20 GHz 12 MB Cache Processor Number Vcc for 775 VR CONFIG 05B V QX9650 3 00 GHz 12 MB Cache Processor Number Vcc for 775_VR_CONFIG_OSA Q9650 3 0 GHz 12 MB Cache Q9550 2 83 GHz 12 MB Cache Vie Core Q9550S 2 83 GHz 12 MB Cache Refer to Table 2 4 and O Q9505 2 83 GHz 8 MB Cache Figure 2 1 dii Q9505S 2 83 GHz 8 MB Cache Q9450 2 66 GHz 12 MB Cache Q9400 2 66 GHz 6 MB Cache Y Q9400S 2 66 GHz 6 MB Cache Q9300 2 50 GHz 6 MB Cache Q8400 2 66 GHz 8 MB Cache Q8300 2 50 GHz 4 MB Cache Q8200 2 33 GHz 4 MB Cache Q8400S 2 66 GHz 8 MB Cache Q8200S 2 33 GHz 4 MB Cache Vcc Boor Default Vcc voltage for initial power up 1 10 V VccPLL PLL Vcc 5 1 50 5 20 Datasheet Electrical Specifications intel Table 2 3 Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes 10 Processor Number A QX9770 3 20 GHz 12 MB Cache 140 Processor Number Icc for 775 VR CONFIG 05B A QX9650 3 00 GHz 12 MB Cache 125 Processor Number Icc for 775 VR CONFIG 05A Q9650 3 0 GHz 12 MB Cache 100 Q9550 2 83 GHz 12 MB Cache 100 I Q9550S 2 83 GHz 12 MB
5. sssss 98 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view 99 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view 99 Boxed Processor Fan Heatsink Set Points ccceceececece nent eee nnne 100 Space Requirements for the Boxed Processor side view s ssssssessrssrsssrsseresrrerrrsers 102 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view 102 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 2 view 103 5 Tables 1 rige M P s 14 2 1 Voltage Identification Definition ei eee eeeeiseee eee s ehe naga a ka nan hana RR RR AR aa 17 2 2 Absolute Maximum and Minimum Ratings ssssssssessseseenm eene eem nne 19 2 3 Voltage and Current Specifications cccceceee eee eee eee eee eee ener eene mene eser enn 20 2 4 Vee Static and Transient Tolerance resorte renean ben rena ie dn hr rnm er P ERE R E REX 23 2 5 Voe Overshoot Specifications 2 0 0 danni ences eens nese ee eee ee eee nese nennen nne nena 25 2 6 FSB Signal Groups een a inue kh XR nade dad andaie Mal EAI Ere aRK REI IFE PMREefa vi EEA 26 2 7 Signal Characteristics caisso aeren e eas Dese eue wage ra Seabees da Ert cided OM REPE P RPR NENS 27 2 8 Signal Reference Voltages i csssxe ke iine nai eget ua E ERES RE ce RO ARR ADETE ERREUR 27 2 9 GIL Signal Group
6. Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows trade offs to be made between performance and power consumptions based on processor utilization This may lower average power consumption in conjunction with OS support Intel virtualization Technology Intel VT A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions Intel VT will provide a foundation for widely deployed virtualization solutions and enables more robust hardware assisted virtualization solutions More information can be found at http www intel com technology virtualization Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT is a security technology by Intel and requires for operation a computer system with Intel Virtualization Technology a Intel Trusted Execution Technology enabled Intel processor chipset BIOS Authenticated Code Modules and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor In addition Intel Trusted Execution Technology requires the system to contain a TPMv1 2 as defined by the Trusted Computing Group and specific software for some uses Platform Environment Control Interface PECI A proprietary one wire bus interface that provides a communication channel between the processor and chipset components to external monitoring devices 13 Table 1 1
7. DBI 3 0 Assignment To Data Bus Data Bus Bus Signal Signals DBI3 D 63 48 DBI2 D 47 32 DBI1 D 31 16 DBIO DI15 014 DBR Output DBR Debug Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBSY Input Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is de asserted This signal must connect the appropriate pins lands on all processor FSB agents 66 Datasheet Land Listing and Signal Descriptions Table 4 3 Datasheet intel Signal Description Sheet 4 of 10 Name DEFER Type Input Description DEFER is asserted by an agent to indicate that a transaction cannot be ensured in order completion Assertion of DEFER is normally the responsibility of the addressed memory or input output agent This signal must connect the appropriate pins lands of all processor FSB agents DPRSTP DPSLP Input Input DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state To return to the Deep Sleep State DPRSTP m
8. If bit 4 of the ACPI P_CNT Control Register located in the processor IA32 THERM CONTROL MSR is written to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI P CNT Control Register In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor If the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode 83 m e n tel Thermal Specifications and Design Considerations Note 5 2 5 84 PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has reached its maximum operating temperature If the Thermal Monitor is enabled note that the Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT PROCHOT is a bi directional signal As an output PROCHOT Processor Hot will go active when the processor temperature mon
9. eene then nga iih oe dux Ee x IR Ex aang sabe a RACE Ke xus 93 6 2 8 Enhanced Intel SpeedStep Technology cccccssessssscccssssssscceevevseesensenaneans 94 6 3 Processor Power Status Indicator PSI Signal ssssesesee mmn 94 Boxed Processor Specifications sssssssssssssseeeenemememememe nemen 95 ZA IMGFODUCHON e 95 74 2 Mechanical Specifications riisiin thou kae ta Rant Bes ok ak ioca e biu ER OA nE i Pia RUE de 96 7 2 1 Boxed Processor Cooling Solution Dimensions ssseseenenen 96 7 2 2 Boxed Processor Fan Heatsink Weight ceeeeeeee ee eee este ee ee ee eeeeeeaeeeeeeeeas 97 7 2 3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly 97 7 3 Electrical Requirements 2 o etie mienne saben blestahaeesdeendgtendeeamia ie Rar eoweedads 97 7 3 1 Fan Heatsink Power Supply ease kien ten nay aso eu han R3 Ra ex ERRARE AR RR eun 97 7 4 Thermal Specifications eee coniecit e neri rie gam d code eb xa aA Fa RR Ck da RNV REPE RENE 99 7 4 1 Boxed Processor Cooling Requirements sssssseeeennene 99 74 2 Mariable Speed Fan ueeiisvee sitae rng t nbn npa n RR RUE Aa RERA KERN FRAN 100 7 5 Boxed Intel Core 2 Extreme Processor QX9650 Specifications cecssse 101 7 5 1 Boxed Intel Core 2 Extreme Processor QX9650 Fan Heatsink Weight 102 Debug Tools Specifications ssss
10. v Stop Grant State Snoop Event Occurs BCLK running Snoops and interrupts allowed Le gt Stop Grant Snoop State BCLK running Snoop Event Serviced Service Snoops to caches Normal State This is the normal operating state for the processor HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state The Extended HALT Powerdown state must be configured and enabled via the BIOS for the processor to remain within specification The Extended HALT state is a lower power state as compared to the Stop Grant State If Extended HALT is not enabled the default Powerdown state entered will be HALT Refer to the sections below for details about the HALT and Extended HALT states HALT Powerdown State HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions When one of the processor cores executes the HALT instruction that processor core is halted however the other processor continues normal operation The halted core will transition to the Normal state upon the occurrence of SMI INIT or LINT 1 0 NMI INTR RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT Power Down state See the Intel Architecture Software Developer s Manual Volume 3B System Programming Guide Part 2 for
11. 0 1 V7 Vp p NOTES 1 V supplies the PECI interface PECI behavior does not affect V7 min max specifications Refer to Table 2 3 for V specifications 2 The leakage specification applies to powered devices on the PECI bus 3 The input buffers use a Schmitt triggered input design for improved noise immunity 4 One node is counted for each client and one node for the system host Extended trace lengths might appear as additional nodes 2 7 3 2 GTL Front Side Bus Specifications In most cases termination resistors are not required as these are integrated into the processor silicon See Table 2 7 for details on which GTL signals do not include on die termination Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF Table 2 13 lists the GTLREF specifications The GTL reference voltage GTLREF should be generated on the system board using high precision voltage divider circuits Table 2 13 GTL Bus Resistance Definitions Symbol Parameter Min Typ Max Units Notes GTLREF_PU GTLREF pull up resistor 57 6 0 99 57 6 57 6 1 01 Q 2 GTLREF_PD GTLREF pull down resistor 100 0 99 100 100 1 01 Q 2 Rrt Termination Resistance 45 50 55 Q 3 COMP 3 0 COMP Resistance 49 40 49 90 50 40 Q 4 COMP8 COMP Resistance 24 65 24 90 25 15 Q 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all proc
12. 2 Quad processor Q9000 and Q9000S series and Intel Core 2 Quad processors Q8400 and Q8400S support Intel virtualization Technology Intel VT Further the Intel Core 2 Quad processor Q9000 and Q9000S series support Intel Trusted Execution Technology Intel TXT The processor s front side bus FSB uses a split transaction deferred reply protocol The FSB uses Source Synchronous Transfer of address and data to improve performance by transferring data four times per bus clock 4X data transfer rate Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 12 4 GB s 11 m n tel Introduction 1 1 1 12 The processor uses some of the infrastructure already enabled by 775 VR CONFIG 05 platforms including heatsink heatsink retention mechanism and socket Manufacturability is a high priority hence mechanical assembly may be completed from the top of the baseboard and should not require any special tooling Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply
13. 9 Leakage to Vr with land held at 300 mV 2 7 3 1 Platform Environment Control Interface PECI DC Specifications PECI is an Intel proprietary one wire interface that provides a communication channel between Intel processors chipsets and external thermal monitoring devices The processor contains Digital Thermal Sensors DTS distributed throughout die These sensors are implemented as analog to digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal fan speed control More detailed information may be found in the Platform Environment Control Interface PECI Specification Datasheet 29 im e n t el Electrical Specifications Table 2 12 PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 15 Vit V Vnysteresis Hysteresis 0 1 Vr V 2 Vn Negative edge threshold voltage 0 275 V 0 500 Vr V Vp Positive edge threshold voltage 0 550 V4 0 725 Vr V High level output source ls Vou 0 75 Vir 6 0 N A mA las aa 2e 0 5 1 0 mA a High impedance state leakage to Vm NA 50 uA lleak High impedance leakage to GND N A 10 pA Chus Bus capacitance per node 10 pF 4 Vnoise Signal noise immunity above 300 MHz
14. C W Tc C w Tc C 0 44 8 26 52 1 52 59 4 78 66 6 2 45 4 28 52 6 54 59 9 80 67 2 4 45 9 30 53 2 56 60 5 82 67 8 6 46 5 32 53 8 58 61 0 84 68 3 8 47 0 34 54 3 60 61 6 86 68 9 10 47 6 36 54 9 62 62 2 88 69 4 12 48 2 38 55 4 64 62 7 90 70 0 14 48 7 40 56 0 66 63 3 92 70 6 16 49 3 42 56 6 68 63 8 94 71 1 18 49 8 44 57 1 70 64 4 95 71 4 20 50 4 46 57 7 72 65 0 22 51 0 48 58 2 74 65 5 24 51 5 50 58 8 76 66 1 Figure 5 3 Intel Core 2 Quad Processor Q9000 and Q8000 Series Thermal Profile 72 0 68 0 64 0 y 0 28x 44 8 Tcase C o o o a o o 52 0 48 0 44 0 20 30 40 50 Power W 60 70 80 90 Datasheet 79 intel Thermal Specifications and Design Considerations Table 5 5 Intel Core 2 Quad Processor Q9000S and Q8000S Series Thermal Profile Power Maximum Power Maximum Power Maximum Power Maximum W Tc C W Tc C W Tc C W Tc C 0 49 6 18 57 0 36 64 4 54 71 7 2 50 4 20 57 8 38 65 2 56 72 6 4 51 2 22 58 6 40 66 0 58 73 4 6 52 1 24 59 4 42 66 8 60 74 2 8 52 9 26 60 3 44 67 6 62 75 0 10 53 7 28 61 1 46 68 5 64 75 8 12 54 5 30 61 9 48 69 3 65 76 3 14 55 3 32 62 7 50 70 1 16 56 2 34 63 5 52 70 9 Figure 5 4 Intel Core 2 Quad Processor Q9000S and Q8000S Series Thermal Profile Tcase C 80 75 70 65 6
15. Configuration Option Signal Output tristate SMI Execute BIST A3 Disable dynamic bus parking A25 Symmetric agent arbitration ID BRO RESERVED A 24 4 A 35 26 NOTE 1 Asserting this signal during RESET will select the corresponding option 2 Address signals not identified in this table as configuration options should not be asserted during RESET 3 Disabling of any of the cores within a processor must be handled by configuring the EXT_CONFIG Model Specific Register MSR This MSR allows for the disabling of a single core per die within the processor package Clock Control and Low Power States The processor allows the use of AUtoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 6 1 for a visual representation of the processor low power states 89 i n tel Features Figure 6 1 6 2 1 6 2 2 6 2 2 1 90 Processor Low Power State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated gt Extended HALT or HALT Normal State INIT INTR NMI SMI RESET State Normal Execution FSB interrupts BCLK running Snoops and interrupts allowed A Snoop Snoop STPCLK STPCLK Rte 2m Occurs Serviced Asserted De asserted STPCLK Asserted STPCLK De asserted Extended HALT Snoop or HALT Snoop State BCLK running Service Snoops to caches
16. 32 Datasheet Electrical Specifications Table 2 17 FSB Differential Clock Specifications 1600 MHz FSB Table 2 18 Datasheet T Parameter Min Nom Max Unit Figure Notes BCLK 1 0 Frequency 397 962 400 037 MHz T1 BCLK 1 0 Period 2 499766 a 2 512800 ns 2 3 2 T2 BCLK 1 0 Period Stability S 150 ps 2 3 3 4 7 T5 BCLK 1 0 Rise and Fall Slew 2 5 n 8 v ns 2 4 5 Rate Slew Rate Matching N A N A 20 9o E 6 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor core frequencies based on a 400 MHz BCLK 1 0 2 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 Min period specification is based on 100 PPM deviation from a 3 ns period Max period specification is based on the summation of 100 PPM deviation from a 3 ns period and a 0 5 maximum variance due to spread spectrum clocking 3 For the clock jitter specification refer to the CK505 Clock Synthesizer Specification 4 In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability 5 Slew rate is measured through the VSWING voltage range centered about differential zero Measurement taken from differential waveform 6
17. In order to determine a processor s case temperature specification based on the thermal profile it is necessary to accurately measure processor power dissipation Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions Refer to the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 for the details of this methodology 75 intel Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 5 1 instead of the maximum processor power consumption The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time For more details on the usage of this feature refer to Section 5 2 In all cases the Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to remain within specification Table 5 1 Processor Thermal Specifications Core Thermal Extended Deeper Processor Fre Design HALT Sleep 775 WR CO Minimum Maximum Tc Notes Number es Power Power Power NFIG Tc
18. Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of processor systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a processor system that can make use of an LAI mechanical and electrical Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI lands plug into the processor socket while the processor lands plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processors heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical
19. VCC J13 Power Other vcc P8 Power Other VCC J14 Power Other VCC R8 Power Other VCC J15 Power Other Vcc T23 Power Other VCC J18 Power Other vcc T24 Power Other VCC J19 Power Other YCC T25 Power Other VCC J20 Power Other VCC T26 Power Other VCC J21 Power Other Vcc T27 Power Other VCC J22 Power Other VCC T28 Power Other VCC J23 Power Other Vcc T29 Power Other VCC J24 Power Other VCC T30 Power Other VCC J25 Power Other vcc T8 Power Other VCC J26 Power Other Vcc U23 Power Other VCC J27 Power Other YCC U24 Power Other VEC J28 Power Other VCC u25 Power Other VCC J29 Power Other Vcc U26 Power Other VCC J30 Power Other Vcc U27 Power Other VCC J8 Power Other vcc U28 Power Other VCC J9 Power Other VCC U29 Power Other VCC K23 Power Other Vcc U30 Power Other VCC K24 Power Other VCC U8 Power Other VCC K25 Power Other VCC V8 Power Other VCC K26 Power Other VCC W23 Power Other VCC K27 Power Other Vcc W24 Power Other VCC K28 Power Other vcc W25 Power Other VCC K29 Power Other YCC W26 Power Other VCC K30 Power Other VCC W27 Power Other VCC K8 Power Other VCC W28 Power Other VCC L8 Power Other vcc W29 Power Other VCC M23 Power Other YCC w30 Power Other VCC M24 Power Other vcc ws Power Other VCC M25 Power Other Vcc Y23 Power Other VCC M26 Power Other VEC Y24 Power Other VCC M27 Power Other Vcc Y25 Power Other VCC M28 Power Other vcc Y26 Power Other VCC M29 Power Other VCC Y27 Power Other VCC M30 Power Other vcc Y28 Power Other
20. and Q8000S series will also be offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from baseboards and standard components The boxed processor will be supplied with a cooling solution This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor This chapter is particularly important for OEMs that manufacture baseboards for system integrators Note The Intel Core 2 Extreme processor QX9770 requires a special liquid cooling thermal solution It will not be offered with the processor Refer to the appropriate Thermal and Mechanical Design Guidelines see Section 1 2 for further guidance Note Unless otherwise noted all figures in this chapter are dimensioned in millimeters and inches in brackets Figure 7 1 shows a mechanical representation of a boxed processor Note Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platforms and chassis Refer to the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 for further guidance Contact your local Intel Sales Representative for this document Figure 7 1 Mechanic
21. n t el 5 5 1 Note 5 1 1 Datasheet Thermal Specifications and Design Considerations Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5 1 1 Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting For more information on designing a component level thermal solution refer to the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 The boxed processor will ship with a component thermal solution Refer to Chapter 7 for details on the boxed processor Thermal Specifications To allow for the optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed such that the processor remains within the mini
22. 000000000 00000000 i Fi 0000000001 _ 060606000 hs T 000000600 T 000000600 E sa ss j 000000000 96000000 E T 3252s g j 600000060 60000000 Em 233 g E 000000000 0000000 z EzpBzs _ s 800060660 _ i 00000000 ole EE 000000000 g 00000000 s E 000000000 000000000 N imal fase 85 00000000000000000000000000000000 i z E MES 00000000000000006000000000000000 3 F Sagde as OOOO0O0000000000000000000000000000 E ate ee g 0000000000000000060000000000000060 2 ri Ee ae t A a 00000000000000000000000000000000 z 2 Fe EEELELEIEI 600000000000000090000000000000000 2 S8g082 e t4 000000000000000600000000000000064 Fi z5295 e 6 4 66660666666 666666 sof SeRES E i ES ea be z T s 5 le al B is x ale ala TMT z NIFFERMEPMPRERNEERE o c gl il ei o sw i e x alala T E SSS 5 T AY gi f o o o 1 i Z z mum p a ane aon a bani ior eee s a 1 Ez E a N mg l ae l O00 A E i L i 1 te X E lt co E e oO Lu Lu Qa oO a id Datasheet Package Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 3 in te REY 2 C88285 77 p te 0 021 e M DETAIL F SCALE 60 1 a d Y 000000000000000000000000000 6000 OOOOO0O0O0O0O0O0O0O0O0000QOOOOOOOOOO0000000 O00000000000000090000000
23. C C w 34 w w See Table 5 2 QX9770 3 20 136 16 E 5 and 8 Figure 5 1 See Table 5 3 QX9650 3 00 130 16 775_VR_CO 5 and 7 8 NFIG_05B Figure 5 2 Q9650 3 0 95 12 8 5 6 Q9550 2 83 95 12 8 5 6 Q9550 2 83 95 12 5 7 Q9505 2 83 95 12 5 7 Q9450 2 66 95 12 775_VR_CO 5 See bus 5 4 7 Q9400 2 66 95 12 8 NFIG 05A 5 Figure 5 3 6 Q9300 2 50 95 12 5 7 Q8400 2 66 95 12 8 5 6 Q8300 2 50 95 12 8 5 6 Q8200 2 33 95 12 5 7 Q9550S 2 83 65 12 8 5 6 9505S 2 83 65 12 8 5 2 6 Q 775_VR_CO See Table 5 5 Q9400S 2 66 65 12 8 5 and 6 NFIG_06 Q8400S 2 66 65 12 8 5 Figure 5 4 6 Q8200S 2 33 65 12 8 5 6 NOTES 1 Specification is at 37 C Tc and minimum voltage loadline Specification is ensured by design characterization and not 100 tested 2 Specification is at 34 C Tc and minimum voltage loadline Specification is ensured by design characterization and not 100 tested 3 Thermal Design Power TDP should be used for processor thermal solution design targets The TDP is not the maximum power that the processor can dissipate 4 This table shows the maximum TDP for a given frequency range Individual processors may have a lower TDP Therefore the maximum Tc will vary depending on the TDP of the individual processor Refer to thermal profile figure and associated table for the allowed combinations of power and Tc 5 775 VR CONFIG 05 guidelines provide a design target for meeting future thermal requirements 6 These proces
24. Cache 100 6 as Q9505 2 83 GHz 8 MB Cache 100 Q9505S 2 83 GHz 8 MB Cache 100 Q9450 2 66 GHz 12 MB Cache 100 Q9400 2 66 GHz 6 MB Cache D ES 100 Q9400S 2 66 GHz 6 MB Cache 100 Q9300 2 50 GHz 6 MB Cache 100 Q8400 2 66 GHz 8 MB Cache 100 Q8300 2 50 GHz 4 MB Cache 100 Q8200 2 33 GHz 4 MB Cache 100 Q8400S 2 66 GHz 8 MB Cache 100 Q8200S 2 33 GHz 4 MB Cache 100 FSB termination on Intel 3 series L ii iasi V voltage Chipset family boards T T we DC AC on Intel 4 series m a 1 26 specifications Chipset family boards i VTT_OUT_LEFT and DC Current that may be drawn from E 580 mA VTT_OUT_RIGHT VIT OUT LEFT and VTT_OUT_RIGHT per land Icc I Icc for V supply before Vcc stable B u 8 0 A 9 TE Icc for V supply after Vcc stable 7 0 Tec_VCCPLL Icc for PLL land 260 mA Icc_GTLREF Icc for GTLREF 200 HA NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID Datasheet which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep Technology or Extended HALT State Unless otherwise noted all specifications in this table are based on estimates and simulations or em
25. DC Specification sssr iere tete nete tke nn napa nete rand epo dna presi e REIS 28 2 10 Open Drain and TAP Output Signal Group DC Specifications sess 28 2 11 CMOS Signal Group DC Specifications ccceceee cece eee eee eee eee eee eee eee ee eee nens 29 2 12 PECI DG Electrical Limits oie ibi aE a E piminany omouedl EASIER ADR EMEN 30 2 13 GTL Bus Resistance Definitions i eese sisse sesesdesunekuknu nu nkka n na ERR YER A ERE KRRARREA EYE AA 30 2 14 Core Frequency to FSB Multiplier Configuration essssssssesemm mm 31 2 15 BSEL 2 0 Frequency Table for BCLK 1 0 ssesesen m mmm 32 2 16 Front Side Bus Differential BCLK Specifications esssssssseee mmn 32 2 17 FSB Differential Clock Specifications 1600 MHz FSB cssssee me 33 2 18 FSB Differential Clock Specifications 1333 MHz FSB eceeeeeeeee eens eset eens ea eeeeeeaes 33 3 1 Processor Loading Specifications sies rore eir mene esae k tnm N nE ERE RE KE 39 3 2 Package Handling Guidelines iii iiiter ede kn et erret shiaanecuacesense Pi ePieIa AR Rae MEET 39 3 3 Processor Materials ies cxx reaa savait o xa ipia REEDE AE tines DE TRAM AFER Pe Rbema is ua DERE 40 4 1 Alphabetical Land Assignments ioter nse Sete dade Soot veda a dae es Ra Ed ERRARE REA 46 4 2 Numerical Land ASSIGNMONE arosinu sends Da aA Ux E PR KR eR RR ERA Ta UE 55 4 3 SIQNAl DESCHPTOM eer 64 5 1 Processor The
26. Datasheet Package Mechanical Specifications 3 2 3 3 Table 3 1 3 4 Table 3 2 Datasheet intel Processor Component Keep Out Zones The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to either the topside or land side of the package substrate See Figure 3 2 and Figure 3 3 for keep out zones The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep in Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution The minimum loading specification must be maintained by any thermal and mechanical solutions Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N 17 Ibf 311 N 70 Ibf 1 2 3 Dynamic 756 N 170 Ibf 1 3 4 NOTES 1 These specifications apply to uniform compressive loading in a direction no
27. GTLREFO Power Other Input F15 D30 Source Synch Input Output H2 GTLREF1 Power Other Input F16 VSS Power Other H3 VSS Power Other F17 D37 Source Synch Input Output H4 FC35 Power Other F18 D38 Source Synch Input Output H5 TESTHI10 Power Other Input F19 VSS Power Other H6 VSS Power Other F20 D41 Source Synch Input Output H7 VSS Power Other F21 D43 Source Synch Input Output H8 VSS Power Other F22 VSS Power Other H9 VSS Power Other F23 RESERVED H10 VSS Power Other F24 TESTHI7 Power Other Input H11 VSS Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment n Land Name SU Direction rang Land Name gi ead Direction H12 VSS Power Other J27 VCC Power Other H13 VSS Power Other J28 VCC Power Other H14 VSS Power Other J29 VCC Power Other H15 FC32 Power Other J30 VCC Power Other H16 FC33 Power Other Ki LINTO Asynch CMOS Input H17 VSS Power Other K2 VSS Power Other H18 VSS Power Other K3 A20M Asynch CMOS Input H19 VSS Power Other K4 REQO Source Synch Input Output H20 VSS Power Other K5 VSS Power Other H21 VSS Power Other K6 REQ3 Source Synch Input Output H22 VSS Power Other K7 VSS Power Other H23 VSS Power Ot
28. Input Output AD2 BPM2 Common Clock Input Output AA5 A233 Source Synch Input Output AD3 FC36 Power Other ARG VSS Power Other AD4 VSS Power Other BAT VSS Power Other AD5 ADSTB1 Source Synch Input Output AAS vec Power Other AD6 A22 Source Synch Input Output AA23 VSS Power Other AD7 VSS Power Other AA24 VSS Power Other AD8 VCC Power Other AA25 VSS Power Other AD23 VCC Power Other BAG S POWET Other AD24 VCC Power Other BAAT yes Power Other AD25 VCC Power Other Ene Mee pe Mer MICE AD26 VCC Power Other ane V39 Power other AD27 VCC Power Other AA30 VSS Power Other AD28 VCC Power Other ABI VSS Powen Other AD29 VCC Power Other AB2 IERR Asynch CMOS Output AD30 VCC Power Other AB3 FC37 Power Other AEL TCK TAP Input AB4 A26 Source Synch Input Output AE2 VSS Power Other AB5 A24 Source Synch Input Output AE3 FC18 Power Other AB6 A173 Source Synch Input Output AE4 RESERVED ABI VSS Power Other AE5 VSS Power Other AB8 VCC Power Other AEG RESERVED AB23 VSS Power Other AE7 vss Power Other AB24 VSS Power Other AE8 SKTOCC Power Other Output AB25 VSS Power Other AES VCC Power Other AB26 VSS Power Other AE10 VSS Power Other BRIT Sm POWEI GNIISI AE11 VCC Power Other A VSS Power Other AE12 vec Power Other AB29 NSS Power Other AE13 VSS Power Other Rea NES Power Other AE14 VCC Power Other ACI INS TOR Input AE15 VCC Power Other AC2 DBR Power Other Output AE16 VSS Power Other ACS Power Other AE17 VSS Power Other ACA RESERVED AE18 VCC Power Other AC
29. Matching applies to rising edge rate for Clock and falling edge rate for Clock It is measured using a 75mV window centered on the average cross point where Clock rising meets Clock falling The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations 7 Duty Cycle High time Period must be between 40 and 60 FSB Differential Clock Specifications 1333 MHz FSB T Parameter Min Nom Max Unit Figure Notes BCLK 1 0 Frequency 331 633 333 367 MHz i 6 T1 BCLK 1 0 Period 2 99970 3 01538 ns 2 3 2 T2 BCLK 1 0 Period Stability 150 ps 2 3 3 T5 BCLK 1 0 Rise and Fall Slew Rate 2 5 8 V ns 2 4 4 Slew Rate Matching N A N A 20 9o 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor core frequencies based on a 333 MHz BCLK 1 0 2 The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 Min period specification is based on 300 PPM deviation from a 3 ns period Max period specification is based on the summation of 300 PPM deviation from a 3 ns period and a 0 5 maximum variance due to spread spectrum clocking 3 In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adja
30. Other C12 D14 Source Synch Input Output D28 VTT Power Other C13 VSS Power Other D29 VTT Power Other C14 D52 Source Synch Input Output D30 VTT Power Other C15 D51 Source Synch Input Output E2 VSS Power Other C16 VSS Power Other E3 TRDY Common Clock Input C17 DSTBP3 Source Synch Input Output E4 HITM Common Clock Input Output C18 D54 Source Synch Input Output E5 FC20 Power Other C19 VSS Power Other E6 RESERVED 59 60 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Land Land Name Signal Buffer Direction Type Type E7 RESERVED F25 TESTHI2 Power Other Input E8 VSS Power Other F26 TESTHIO Power Other Input E9 D19 Source Synch Input Output F27 VIT SEL Power Other Output E10 D21 Source Synch Input Output F28 BCLKO Clock Input E11 VSS Power Other F29 RESERVED E12 DSTBP1 Source Synch Input Output G1 BPMbO Common Clock Input Output E13 D26 Source Synch Input Output G2 COMP2 Power Other Input E14 VSS Power Other G3 BPMb3 Common Clock Input Output E15 D334 Source Synch Input Output G4 BPMb2 Common Clock Input Output E16 D34 Source Synch Input Output G5 PECI Power Other Input Output E17 VSS Power Other G6 RESERVED E18 D39 So
31. PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Request Command must connect the appropriate pins lands of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTBO RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all FSB agents will de assert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 6 1 This signal does not have on die termination and must be terminated on the system board RESERVED RS 2 0 Input All RESERVED lands must remain unconnected Connection of these lands to Vec Vss Vr or to any other signal including each other can
32. Power Other vss AK23 Power Other VSS C4 Power Other VSS AK24 Power Other VSS C7 Power Other VSS AK27 Power Other VSS D12 Power Other VSS AK28 Power Other VSS D15 Power Other VSS AK29 Power Other VSS D18 Power Other VSS AK30 Power Other VSS D21 Power Other VSS AK5 Power Other VSS D24 Power Other VSS AK7 Power Other VSS D3 Power Other VSS AL10 Power Other VSS D5 Power Other Datasheet Land Listing and Signal Descriptions intel Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land Ms rod Direction Land Name Land Mia aed Direction VSS D6 Power Other VSS L23 Power Other VSS D9 Power Other VSS L24 Power Other VSS E11 Power Other VSS L25 Power Other VSS E14 Power Other VSS L26 Power Other VSS E17 Power Other VSS L27 Power Other VSS E2 Power Other VSS L28 Power Other VSS E20 Power Other VSS L29 Power Other VSS E25 Power Other VSS L3 Power Other VSS E26 Power Other VSS L30 Power Other VSS E27 Power Other VSS L6 Power Other VSS E28 Power Other VSS L7 Power Other VSS E8 Power Other VSS Mi Power Other VSS F10 Power Other VSS M7 Power Other VSS F13 Power Other VSS N3 Power Other VSS F16 Power Other VSS N6 Power Other VSS F19 Power Other VSS N7 Power Other VSS F22 Power Other VSS P23 Power Other VSS F4 Power Other VSS P24 Power O
33. Processor QX9650 Thermal Profile Power Maximum Power Maximum Power Maximum Power Maximum W Tc C W Tc C w Tc C W Tc C 0 42 4 34 48 2 68 54 0 102 59 7 2 42 7 36 48 5 70 54 3 104 60 1 4 43 1 38 48 9 72 54 6 106 60 4 6 43 4 40 49 2 74 55 0 108 60 8 8 43 8 42 49 5 76 55 3 110 61 1 10 44 1 44 49 9 78 55 7 112 61 4 12 44 4 46 50 2 80 56 0 114 61 8 14 44 8 48 50 6 82 56 3 116 62 1 16 45 1 50 50 9 84 56 7 118 62 5 18 45 5 52 51 2 86 57 0 120 62 8 20 45 8 54 51 6 88 57 4 122 63 1 22 46 1 56 51 9 90 57 7 124 63 5 24 46 5 58 52 3 92 58 0 126 63 8 26 46 8 60 52 6 94 58 4 128 64 2 28 47 2 62 52 9 96 58 7 130 64 5 30 47 5 64 53 3 98 59 1 32 47 8 66 53 6 100 59 4 Figure 5 2 Intel Core 2 Extreme Processor QX9650 Thermal Profile 65 0 63 0 61 0 59 0 57 0 55 0 o y 0 17x 424 53 0 ivi o e 51 0 49 0 47 0 45 0 43 0 41 0 t 1 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power W 78 Datasheet Thermal Specifications and Design Considerations Table 5 4 intel Intel Core 2 Quad Processor Q9000 and Q8000 Series Thermal Profile Power Maximum Power Maximum Power Maximum Power Maximum W Tc C W Te
34. Temperature Fan Speed RPM Temperature not intended to depict actual implementation 85 im e n tel Thermal Specifications and Design Considerations 5 3 2 5 3 2 1 5 3 2 2 5 3 2 3 5 3 2 4 Table 5 6 86 PECI Specifications PECI Device Address The PECI register resides at address 30h PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification Refer to this document for details on supported PECI command function and codes PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is know to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not assured to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host c
35. VTT A26 Power Other VSS V29 Power Other VTT A27 Power Other VSS V3 Power Other VTT A28 Power Other VSS V30 Power Other VTT A29 Power Other VSS V6 Power Other VTT A30 Power Other VSS V7 Power Other VTT C25 Power Other VSS W4 Power Other VTT C26 Power Other VSS W7 Power Other VTT C27 Power Other VSS Y2 Power Other VTT C28 Power Other VSS Y5 Power Other VTT C29 Power Other VSS Y7 Power Other VTT C30 Power Other RECIEN AN6 Power Other Output VIE D25 Power Other VTT D26 Power Other VSS SENSE ANA Power Other Output VIT D27 Power Other VSSA B23 Power Other VIT D28 Power Other VTT B25 Power Other VIT D29 Power Other 7 ee VTT D30 Power Other ower Other VIT B28 ee vi ped LE Ji Power Other Output VTT B29 Power Other ae AAL Power Other Output VTT B30 Power Other VIT A25 Power Other VTT SEL F27 Power Other Output Datasheet Land Listing and Signal Descriptions Datasheet intel Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment n Land Name icis oes Direction 2 Land Name ligi end Direction AA1 e da Power Other Output AC28 VCC Power Other AC29 VCC Power Other AA FC39 Power Other AC30 VCC Power Other AA3 VSS Power Other AD1 TDI TAP Input ANT A21 Source Synch
36. agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these signals as LINT 1 0 is the default configuration LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins lands of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor FSB it will wait until it observes LOCK de asserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MSID 1 0 Output On the processor these signals are not connected on the package they are floating As an alternative to MSID Intel has implemented the Power Segment Identifier PSID to report the maximum Thermal Design Power of the processor Refer to Section 2 5 for additional information regarding PSID PECI Input Output PECI
37. an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Front Side Bus refers to the interface between the processor and system core logic a k a the chipset components The FSB is a multiprocessing interface to processors memory and I O Processor Terminology Definitions Commonly used terms are explained here for clarification e Intel Core 2 Extreme processor QX9000 series Quad core Extreme Edition processor in the FC LGA6 package with two 6 MB L2 cache e Intel Core 2 Quad processor Q9000 series Quad core processor in the FC LGA8 package with two 6 MB L2 caches or two 3 MB L2 caches e Intel Core 2 Quad processor Q8000 Series Quad core processor in the FC LGA8 package with two 4 MB L2 caches or two 2 MB L2 caches e Intel Core 2 Quad processor Q9000S series Low power Quad core processor in the FC LGA8 package with two 6 MB L2 caches or two 3 MB L2 caches e Intel Core 2 Quad Processor Q8000S Series Low power Quad core processor in the FC LGA8 package with two 4 MB L2 caches or two 2 MB L2 caches caches e Processor For this document the term processor is the generic form of the Intel Core 2 Extreme processor QX9000 series the Intel Core 2 Quad proces
38. boxed processor keep out zones This is done intentionally and with the understanding that Extreme Edition systems will be integrated into larger capacity chassis 101 m n t el Boxed Processor Specifications Figure 7 10 Space Requirements for the Boxed Processor side view 7 5 1 Boxed Intel Core 2 Extreme Processor QX9650 Fan Heatsink Weight The Boxed Intel Core 2 Extreme processor QX9650 fan heatsink weight will complies with the socket specifications See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 for details on the processor weight and heatsink requirements Figure 7 11 Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view 102 Datasheet Boxed Processor Specifications nn T P sil to AUG LA ll Toh Mh V n LLLI if M DN Fy 1 D hj bb5 Datasheet 103 n t e Boxed Processor Specifications 104 Datasheet m e Debug Tools Specifications l n t el 8 8 1 8 1 1 8 1 2 Datasheet Debug Tools Specifications Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Intel Core 2 Extreme processor QX9000 series
39. intel Figure 3 4 Processor Package Drawing Sheet 3 of 3 38 Package Mechanical Specifications TEV 3 C88285 77 13 1 O00000000 OOOOOOOOO OO00000000 O00000000 OOOOOOOOO OOOOOOOOO 000000000 000000000 0000o O00000 O00000 O00000 O00000 OOOOOOQOOOOO OOOOOOQOOOOO O00000000000 900000900000 O00000 o0000 O00000 O00000 OOOOOOOOO Oooooooooo OOOOOOOOO OOOOOOOOO OO0000000 O00000000 1 ye 0000 O000000000 0000000000 0000000000 OOOOOOOOOO OOOOOOOOOO 0000000000 o000000000 OO00000000 OOOOOOOOO OOOOOOOOO OOOOOOOOO OOOOOOOOO 000000000 000000000 0000 13 7 6 195 000000000 000000000 OOO0000000 000000000 000000000 OO00000000 OOoOoOoOoOOOOOOOOOOO OOOOOO0O0O000000000 OOOO0O000000000000 OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOO O000000000000000 000000000 000000000 OOOOOOOOO 000000000 000000000 O000000000000000 OO0O00000000000000 0000000000 000 7 0 115 L O00 1 5 MAX ALLOWABLE COMPONENT HEIGHT BOTTOM VIEW SIDE VIEW TOP VIEW aw l DO NOT SCALE DRAWING Deer 3 oF 3 SANTA CLARA CA 95052 8119 ene e 2200 MISSION COLLEGE BLVD P O BOX 58119 com intel DEPARTMENT ATD
40. intel Intel Core 2 Extreme Processor QX9000 Series Intel Core 2 Quad Processor Q9000 Q9000S Q8000 and Q8000S Series Datasheet on 45 nm process in the 775 land package August 2009 Document Number 318726 010 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Intel Corporation may have patents or pending patent applications trademarks copyrights or other intellectual property rights that relate to the presented subject matter The furnishing of documents and other materials and information does not provide any license express or implied by estoppel or otherwise to any su
41. is a proprietary one wire bus interface See Chapter 5 3 for details PROCHOT Input Output As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled The TCC will remain active until the system de asserts PROCHOT See Section 5 2 4 for more details PSI Output Processor Power Status Indicator Signal This signal may be asserted when the processor is in the Deeper Sleep State PSI can be used to improve load efficiency of the voltage regulator resulting in platform power savings Datasheet 69 intel Table 4 3 Land Listing and Signal Descriptions Signal Description Sheet 7 of 10 Name PWRGOOD REQ 4 0 Type Input Input Output Description PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state
42. more information Datasheet Features 6 2 2 2 6 2 3 6 2 3 1 Datasheet intel The system can generate a STPCLK while the processor is in the HALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state While in HALT Power Down state the processor will process bus snoops Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled using the BIOS When one of the processor cores executes the HALT instruction that logical processor is halted however the other processor continues normal operation The Extended HALT Powerdown must be enabled using the BIOS for the processor to remain within its specification The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID While in Extended HALT state the processor will process bus snoops The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus ratio back to
43. n a a b o a la la la la la la fa la la la fa la fa la la la la lo lo lo lo lo Jo Jo Jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo JH a o9 Ln ln Ln Ln Ln Ln Ln ln Ln Ln Ln Ln Ln ln Ln Ln Ln ln Ln Ln ln in D in In in In in in in in Ln Ln in LL N N Jin IN N N N fin IN N N N fin IN N N N fin IN N N N fin IN N N N jin S fae J Joo mo m m a i Y fo se for S a X Joo IS xo jm fon f m Joo N fo jc JN a A Joo A Jo Ja m JN S 7 o 5 Jo Jo a Om nm fe PED fr Se PSS eS fr fd ie Oe Oe 9 pr IN IN IN Jt eS et ft tt 19 e a Hu Hd Hu Hd Hd Hu Hu Hd Hd Hu Hu a Bo o o Jo o o Jo o jo o o Jo Jo o o o o Jo o lo Jo o Jo Jo o Jo Jo o lo o Jo o o jo Jo o o o o jo bo jo o o lo lo o a ST Q n O ju JO f O ju JO O f JO f O a JO af JO a O O O f O a O a JO a O a O 3 O if O a O ju JO a JO n a EN o lo la la lo Jo la la Jo lo la la lo Jo la la Jo Jo la la lo Jo la la Jo Jo la la Jo Jo la la Jo Jo la la Jo Jo la JH lo Jo la la lo Jo a Em o jo Jo lo la x JX l lo Jo Jo Jo la la la l Jo Jo lo Jo la Ja l JH lo Jo lo Jo la la l JH Jo Jo Jo Jo la la l l Jo Jo Jo Jo A89 a EN o lo Jo Jo Jo Jo Jo Jo la la Ja la la la la l Jo Jo lo Jo Jo Jo Jo Jo la la la la Ja la a Ja lo Jo Jo Jo Jo Jo Jo Jo Ja x Ja Ja fa fa a O O o jo JO JO JO JO JO JO JO JO JO JO JO JO jm a a ju a f fe a f a m m i i a a O o JO JO jo JO jo jo JO jo JO JO JO JO a E o o o o o o o o jo o o o Jo o o o o Jo o lo Jo o Jo Jo o J
44. only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss Refer to the Voltage Regulator Design Guide for details on implementing the bi directional PROCHOT feature THERMTRIP Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Table 4 3 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 4 3 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Datasheet m e Thermal Specifications and Design Considerations n t el 5 3 5 3 1 5 3 1 1 Figure 5 7 Datasheet Platform Environment Control Interface PECI Introduction PECI offers an interface for thermal monitoring of Inte
45. 0 55 50 45 y O 41x 49 6 10 30 Power W 40 50 60 80 Datasheet m e Thermal Specifications and Design Considerations n t el 5 1 2 Figure 5 5 5 2 5 2 1 Datasheet Thermal Metrology The maximum and minimum case temperatures Tc for the processor is specified in Table 5 1 This temperature specification is meant to help ensure proper operation of the processor Figure 5 5 illustrates where Intel recommends Tc thermal measurements should be made For detailed guidelines on temperature measurement methodology refer to the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 Case Temperature Tc Measurement Location Measure T at this point geo metric center of the package 37 5 mm Processor Thermal Features Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption by modulating starting and stopping the internal processor core clocks The Thermal Monitor feature must be enabled for the processor to be operating within specifications The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interr
46. 0000000000 OOOOOOO0O0O0O0O000000QO0OOOOOOOO0O0O000000 OOO0000000000000090000000000000000 OOoOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OO0O0O000000000000000000000000000000 000000000000000000000000000000000 000000000 000000000 000000000 600000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 90000090000 000000000 0000000060 000000000 000000000 000000000 000000000 0000060606 000000000 000000000 000000000 000000000 5 i 000000000 000000000 000000000 000000000000000000000000000000000 OOOOOOOOOOOOOOOO0OOOOOOOOOO0O000000 OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OOO0O000000000000000000000000000000 OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOQOOOOOOOOOOOOOOOO OOOOOOOOOOOOCOOOOQOOOOOOOOOO0000000 000000000000000090000000009 QOO BOTTOM VIEW TN bes omi C SCALE 20 1 xm D SCALE 20 1 COMMENTS MAX MILLIMETERS MIN RI 4 BASIC RI 4 BASIC 0 2 BASIC 6 215 BASIC 0 2 BASIC 6 215 BASIC SYNBOL 8 T 1 Y 1 Y oa DRAWING WINGER C88285 DO NOT SCALE DRAWING uter 2 oF 3 2200 MISSION COLLEGE BLVD P O BOX 58119 intel SANTA CLARA CA 95052 8119 cac 6 T coi DEPARTMENT ATD Datasheet 37
47. 14 References Introduction Material and concepts available in the following documents may be beneficial when reading this document References Document Location Intel Core 2 Extreme Processor QX9000 Series Intel Core 2 Quad Processor Q9000 Q9000S Q8000 and Q8000S Series Specification Update http www intel com design processor specupdt 318727 htm Intel Core 2 Extreme Processor and Intel Core 2 Quad Processor Thermal and Mechanical Design Guidelines http www intel com design processor designex 315594 htm Intel Core 2 Extreme Processor QX6800 and Intel Core 2 Extreme Processor QX9770 Thermal and Mechanical Design Guidelines http www intel com design processor designex 316854 htm Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket http www intel com design processor applnots 313214 htm Balanced Technology Extended BTX System Design Guide www formfactors org LGA775 Socket Mechanical Design Guide http intel com design Pentium4 guides 302666 htm Intel 64 and IA 32 Intel Architecture Software Developer s Manuals Volume 1 Basic Architecture Volume 2A Instruction Set Reference A M Volume 2B Instruction Set Reference N Z Volume 3A System Programming Guide Volume 3B System Programming Guide http www intel com products processor manuals Datashe
48. 23 VCC Power Other J26 VCC Power Other M24 VCC Power Other 61 62 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Land Land Name Signal Buffer Direction Type Type M25 VCC Power Other R23 vss Power Other M26 VCC Power Other R24 VSS Power Other M27 VCC Power Other R25 VSS Power Other M28 VCC Power Other R26 VSS Power Other M29 VCC Power Other R27 vss Power Other M30 VCC Power Other R28 VSS Power Other N1 PWRGOOD Power Other Input R29 VSS Power Other N2 IGNNE Asynch CMOS Input R30 VSS Power Other N3 VSS Power Other T1 COMP1 Power Other Input N4 RESERVED T2 DPRSTP Asynch CMOS Input N5 RESERVED T3 VSS Power Other N6 VSS Power Other T4 A11 Source Synch Input Output N7 VSS Power Other T5 A093 Source Synch Input Output N8 VCC Power Other T6 VSS Power Other N23 VCC Power Other T7 VSS Power Other N24 VCC Power Other T8 VCC Power Other N25 VCC Power Other T23 VCC Power Other N26 VCC Power Other T24 VCC Power Other N27 VCC Power Other T25 VCC Power Other N28 VCC Power Other T26 VCC Power Other N29 VCC Power Other T27 VCC Power Other N30 VCC Power Other T28 VCC Power Other P1 DPSLP Asynch CMOS Input T29 VC
49. 30 VTT Power Other B5 VSS Power Other D1 RESERVED B6 DO5 Source Synch Input Output D2 ADS Common Clock Input Output B7 DO6 Source Synch Input Output D3 VSS Power Other B8 VSS Power Other D4 HIT Common Clock Input Output B9 DSTBPO Source Synch Input Output DS VSS Power Other B20 VSS Power Other D6 VSS Power Other B21 D59 Source Synch Input Output D7 D20 Source Synch Input Output B22 D63 Source Synch Input Output D8 D12 Source Synch Input Output B23 VSSA Power Other D9 VSS Power Other B24 VSS Power Other D10 D22 Source Synch Input Output B25 VTT Power Other D11 D15 Source Synch Input Output B26 VTT Power Other D12 VSS Power Other B27 VTT Power Other D13 D25 Source Synch Input Output B28 VTT Power Other D14 RESERVED B29 VTT Power Other D15 VSS Power Other B30 VTT Power Other D16 RESERVED Ci DRDY Common Clock Input Output D17 D49 Source Synch Input Output C2 BNR Common Clock Input Output D18 VSS Power Other C3 LOCK Common Clock Input Output D19 DBI2 Source Synch Input Output C4 VSS Power Other D20 D48 Source Synch Input Output c5 DO1 Source Synch Input Output D21 VSS Power Other C6 DO3 Source Synch Input Output D22 D46 Source Synch Input Output C7 vss Power Other D23 VCCPLL Power Other C8 DSTBNO Source Synch Input Output D24 VSS Power Other C9 BPMb1i Common Clock Input Output D25 VTT Power Other C10 VSS Power Other D26 VTT Power Other C11 D11 Source Synch Input Output D27 VTT Power
50. 4 3 Signal Description Sheet 3 of 10 Name Type Description D 63 0 DBI 3 0 Input Output Input Output D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins lands on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DBI Quad Pumped Signal Groups DSTBN DSTBP DBI Data Group D 15 0 D 31 16 D 47 32 D 63 48 WN e O WN e O Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted If more than half the data bits within a 16 bit group would have been asserted electrically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group
51. 5 0 3 74 NOTES 1 Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation 96 Datasheet m e Boxed Processor Specifications n t e I Figure 7 4 Space Requirements for the Boxed Processor overall view 7 2 2 7 2 3 7 3 7 3 1 Datasheet Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 for details on the processor weight and heatsink requirements Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket The boxed processor will ship with the heatsink attach clip assembly Electrical Requirements Fan Heatsink Power Supply The boxed processor s fan heatsink requires a 12 V power supply A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard The power cable connector and pinout are shown in Figure 7 5 Baseboards must provide a matched power header to support the boxed processor Table 7 1 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal which is an open collector output that pulses at a rate of 2 pulses p
52. 5 A25 Source Synch Input Output AE19 VCC Power Other REG VSS Power Other AE20 VSS Power Other AGT kii Rowen Oter AE21 vec Power Other ACS Mire Power Mer AE22 vec Power Other AC23 vec Power Other AE23 VCC Power Other AC24 vec Power Other AE24 VSS Power Other AC25 vec Power Other AE25 VSS Power Other AC26 vec Power Other AE26 VSS Power Other Bon vec Power Other AE27 VSS Power Other 55 56 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Land Land Name Signal Buffer Direction Type Type AE28 VSS Power Other AG14 VCC Power Other AE29 VSS Power Other AG15 VCC Power Other AE30 VSS Power Other AG16 VSS Power Other AF1 TDO TAP Output AG17 VSS Power Other AF2 BPM4 Common Clock Input Output AG18 VCC Power Other AF3 VSS Power Other AG19 VCC Power Other AF4 A28 Source Synch Input Output AG20 VSS Power Other AF5 A27 Source Synch Input Output AG21 VCC Power Other AF6 VSS Power Other AG22 VCC Power Other AF7 VSS Power Other AG23 VSS Power Other AF8 VCC Power Other AG24 VSS Power Other AF9 VCC Power Other AG25 VCC Power Other AF10 VSS Power Other AG26 VCC Power Other AF11 VCC Power Other AG27 VCC Power Other AF12 VCC Power Other AG28 VCC Power Other AF13 VSS Power Other AG29 VCC Power Other A
53. 6 Power Other VSS B20 Power Other VSS AE27 Power Other VSS B24 Power Other VSS AE28 Power Other VSS BS Power Other VSS AE29 Power Other VSS B8 Power Other VSS AE30 Power Other VSS A12 Power Other VSS AE5 Power Other VSS A15 Power Other VSS AE7 Power Other VSS A18 Power Other VSS AF10 Power Other VSS A2 Power Other VSS AF13 Power Other VSS A21 Power Other VSS AF16 Power Other Me AG _ Power Other VSS AF17 Power Other Ven A9 Power Other VSS AF20 Power Other V35 AA23 _Power Other VSS AF23 Power Other VSS AA24 Power Other VSS AF24 Power Other VSS AA25 Power Other VSS AF25 Power Other NES Bad Power orner VSS AF26 Power Other VSS AA27 Power Other VSS AF27 Power Other vss ARAS Power Other VSS AF28 Power Other wee RA29 PUWEHTARS VSS AF29 Power Other VSS AA3 Power Other VSS AF3 Power Other v35 BASS PoWgT OmEr vss AF30 Power Other VSS BAG Power Other VSS AF6 Power Other VSS PAZ Power Other VSS AF7 Power Other VSS ABI Power Other VSS AG10 Power Other Datasheet 51 52 intel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land ki ei Direction Land Name Land T Direction vss AG13 Power Other VSS AL13 Power Other vss AG16 Power
54. 8 2 FSB Frequency Select Signals BSEL 2 0 sesesememmI 32 2 8 3 Phase Lock Loop PLL and Filter ccccecceee eee ee nsec ee eee tees mmn 32 2 8 4 BCLK 1 0 Specifications eese etre oc rue rc seeds tan rta ox ees ddekcaaoems DERE UNA 32 3 Package Mechanical Specifications ssssssssssssseeeee meme 35 3 1 Package Mechanical Drawing 5 ccs ene nir nd ene aa su nes iena ERR E x RAD ERR E pe RET aE iaa 35 3 2 Processor Component Keep Out Zones sssssssssssesee mese enne nenne nnn 39 3 9 Package Loading Specifications ruis essees tires rnn rhkx ri ea E an AER sa RR ERR PEE RR 39 3 4 Package Handling Guidelines iiiter seme secte tnn ete atu ean nca reas Haga E nre Va FER Dn sees 39 3 5 Package Insertion Specifications ee eee nannte sena nena nnne ni naa rank dna Fa n ERA a Fn K A 40 3 6 Processor Mass Specification cceccceceecseecseseedebecsaseeeaeeceseennerseretehecseeeteaeeeeneceaeeeans 40 3 7 Processor MaterialSux iere utor penehepa td names aE E E A EDI RULES taped RI aus 40 3 9 Processor Matkirigsusuesexesocevd ose stash s in sus uisu Peu A EE Ka p n URDU NDA Ee DER EDAM LAE 40 4 Land Listing and Signal Descriptions ssssssssssse meme 43 4 1 Processor Land AssightneHhts eoe ieo atero ters t po tees eateries quiet ada Vieayetealveasateaaay e eh 43 4 2 Alphabetical Signals Reference 0 cccceccsereenee namine ana a R 64 5
55. C Power Other P2 SMI Asynch CMOS Input T30 VCC Power Other P3 INIT Asynch CMOS Input U1 TDO_M TAP Output P4 VSS Power Other U2 FC29 Power Other P5 RESERVED U3 FC30 Power Other P6 A043 Source Synch Input Output U4 A13 Source Synch Input Output P7 VSS Power Other U5 A123 Source Synch Input Output P8 VCC Power Other U6 A10 Source Synch Input Output P23 VSS Power Other U7 VSS Power Other P24 VSS Power Other U8 VCC Power Other P25 VSS Power Other U23 VCC Power Other P26 VSS Power Other U24 VCC Power Other P27 VSS Power Other U25 VCC Power Other P28 VSS Power Other U26 VCC Power Other P29 VSS Power Other U27 VCC Power Other P30 VSS Power Other U28 VCC Power Other R1 COMP3 Power Other Input U29 VCC Power Other R2 VSS Power Other U30 VCC Power Other R3 FERR PBE Asynch CMOS Output Vi MSID1 Power Other Output R4 A08 Source Synch Input Output V2 RESERVED R5 VSS Power Other V3 VSS Power Other R6 ADSTBO Source Synch Input Output V4 A15 Source Synch Input Output R7 VSS Power Other V5 A14 Source Synch Input Output R8 VCC Power Other V6 VSS Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment n Land Name igi oig Direction E Land Name m Direction V7 vss Power Other W26 VGE Power Other V8 VCC Power Ot
56. DY ci Common Clock Input Output EINES Kt Asynch CMOS Input DSTBNO C8 Source Synch Input Output DIET ET Asynich CMOS Input DSTBN1 G12 Source Synch Input Output ROEM c3 Common Clock Input Output DSTBN2 G20 Source Synch Input Output MSIDA Wi Power Other Output DSTBN3 A16 Source Synch Input Output SIT Li Pow r oth r Output 47 Land Listing and Signal Descriptions intel 48 Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land i ei Direction Land Name Land dh 22d Direction PECI G5 Power Other Input Output TESTHI5 G26 Power Other Input PROCHOT AL2 Asynch CMOS Input Output TESTHI6 G24 Power Other Input PWRGOOD N1 Power Other Input TESTHI7 F24 Power Other Input PSI Y3 Asynch CMOS Output THERMTRIP M2 Asynch CMOS Output REQO K4 Source Synch Input Output TMS AC1 TAP Input REQ1 J5 Source Synch Input Output TRDY E3 Common Clock Input REQ2 M6 Source Synch Input Output TRST AG1 TAP Input REQ3 K6 Source Synch Input Output VCC AA8 Power Other REQ4 J6 Source Synch Input Output VCC AB8 Power Other RESERVED V2 VCC AC23 Power Other RESERVED A20 VCC AC24 Power Other RESERVED AC4 VCC AC25 Power Other RESERVED AE4 VCC AC26 Power Other RESERVED AE6 VCC AC27 Power Other RESERVED AH2 VCC AC28 Power O
57. Datasheet e Land Listing and Signal Descriptions n t el Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land Mis oci Direction Land Name Land Mir sein Direction VCC Y29 Power Other VSS AB23 Power Other VCC Y30 Power Other VSS AB24 Power Other VCC Y8 Power Other VSS AB25 Power Other ESEON AN5 Power Other Output VSS AB26 Power Other VSS AB27 Power Other VCC SENSE AN3 Power Other Output VSS AB28 Power Other VCCA A23 Power Other VSS AB29 Power Other VCCIOPLL C23 Power Other VSS AB30 Power Other VCCPLL D23 Power Other VSS AB Power Other VID SELECT AN7 Power Other Output VSS AC3 Power Other VIDO AM2 Asynch CMOS Output VSS AC6 Power Other VID1 AL5 Asynch CMOS Output VSS AC7 Power Other VID2 AM3 Asynch CMOS Output VSS AD4 Power Other VID3 AL6 Asynch CMOS Output VSS AD Power Other VID4 AK4 Asynch CMOS Output VSS AE10 Power Other VID5 AL4 Asynch CMOS Output VSS AE13 Power Other VID6 AM5 Asynch CMOS Output VSS AE16 Power Other VID7 AM7 Asynch CMOS Output VSS AE17 Power Other VRDSEL AL3 Power Other VSS AED Power Other VSS B1 Power Other VSS AE20 Power Other VSS B11 Power Other VSS AE24 Power Other VSS B14 Power Other VSS AE25 Power Other VSS B17 Power Other VSS AE2
58. EQ1 vss FC22 FC3 VERTO vss vss vss vss vss vss vss vss vss TESTHI10 FC35 vss GTLREF1 GTLREFO D29 D27 DSTBN1 DBI1 GTLREF3 D16 BPRI DEFER RSVD PECI BPMb2 BPMb3 COMP2 BPMbO D28 VSS D24 D23 VSS D18 D17 VSS FC21 RS1 vss BRO GTLREF2 vss D26 DSTBP1 VSS D21 D19 vss RSVD RSVD FC20 HITM TRDY vss RSVD D25 vss D15 D22 vss D12 D20 vss vss HIT vss ADS RSVD D52 vss D14 D114 VSS BPMb1 DSTBNO VSS D3 D1 VSS LOCK BNR DRDY VSS COMP8 D13 vss D10 DSTBPOR VSS D6 D5 VSS DO RSO DBSY vss D50 COMPO vss D9 D8 VSS DBIO D7 VSS D4 D2 RS2 VSS 14 13 12 1 10 9 8 7 6 5 4 3 2 1 Datasheet 45 AN AM AL AK AJ AH AG AF AE AD AC AB 4 c lt s 46 intel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land m Direction Land Name Land dd od Direction A3 L5 Source Synch Input Output BPMbO G1 Common Clock Input Output A4 P6 Source Synch Input Output BPMb1i C9 Common Clock Input Output A5 M5 Source Synch Input Output BPMb2 G4 Common Clock Input Output A6 L4 Source Synch Input Output BPMb3 G3 Common Clock Input Output A7 M4 Source Synch Input Output BPRI G8 Common Clock Input A8 R4 S
59. F14 VCC Power Other AG30 VCC Power Other AF15 VCC Power Other AH1 VSS Power Other AF16 VSS Power Other AH2 RESERVED AF17 VSS Power Other AH3 VSS Power Other AF18 VCC Power Other AH4 A32 Source Synch Input Output AF19 VCC Power Other AH5 A333 Source Synch Input Output AF20 VSS Power Other AH6 VSS Power Other AF21 VCC Power Other AH7 VSS Power Other AF22 VCC Power Other AH8 VCC Power Other AF23 VSS Power Other AH9 VCC Power Other AF24 VSS Power Other AH10 VSS Power Other AF25 VSS Power Other AH11 VCC Power Other AF26 VSS Power Other AH12 VCC Power Other AF27 VSS Power Other AH13 VSS Power Other AF28 VSS Power Other AH14 VCC Power Other AF29 VSS Power Other AH15 VCC Power Other AF30 VSS Power Other AH16 VSS Power Other AG1 TRST TAP Input AH17 VSS Power Other AG2 BPM3 Common Clock Input Output AH18 VCC Power Other AG3 BPM5 Common Clock Input Output AH19 VCC Power Other AG4 A30 Source Synch Input Output AH20 VSS Power Other AG5 A31 Source Synch Input Output AH21 VCC Power Other AG6 A29 Source Synch Input Output AH22 VCC Power Other AG7 VSS Power Other AH23 VSS Power Other AG8 VCC Power Other AH24 VSS Power Other AG9 VCC Power Other AH25 VCC Power Other AG10 VSS Power Other AH26 VCC Power Other AG11 VCC Power Other AH27 VCC Power Other AG12 VEG Power Other AH28 VCC Power Other AG13 VSS Power Other AH29 VCC Power Other Datasheet Land Listing and Signal Descriptions Datasheet intel
60. FSB 1600 MHz FSB 1 6 2 GHz 2 6 GHz 1 7 2 33 GHz 2 8 GHz E 1 7 5 2 50 GHz 3 0 GHz 1 8 2 66 GHz 3 2 GHz 1 8 5 2 83 GHz 3 4 GHz 1 9 3 GHz 3 6 GHz 7 1 9 5 3 16 GHz 3 8 GHz 1 10 3 33 GHz 4 0 GHz 1 10 5 3 50 GHz 4 2 GHz 1 11 3 66 GHz 4 4 GHz E 1 11 5 3 83 GHz 4 6 GHz 1 12 4 GHz 4 8 GHz 1 12 5 4 16 GHz 5 0 GHz z 1 13 4 33 GHz 5 2 GHz 1 13 5 4 50 GHz 5 4 GHz 1 14 4 66 GHz 5 6 GHz z 1 15 5 GHz 5 8 GHz E NOTES 1 Individual processors operate only at or below the rated frequency 2 Listed frequencies are not necessarily committed production frequencies 31 im e n tel Electrical Specifications 2 8 2 FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 Table 2 15 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The Intel Core 2 Extreme processor QX9650 Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series operate at a 1333 MHz FSB frequency selected by a 333 MHz BCLK 1 0 frequency The Intel Core 2 Extreme processor QX9770 operates at a 1600 MHz FSB frequency selected by a 400 MHz BCLK 1 0 frequency Individual processors will
61. H29 Power Other VCC AM18 Power Other VCC AH30 Power Other VEG AM19 Power Other vcc AH8 Power Other VCC AM21 Power Other VEC AH9 Power Other VCC AM22 Power Other WCC AJ11 Power Other NEC AM25 Power Other VCC AJ12 Power Other WEG AM26 Power Other Vcc AJ14 Power Other VCC AM29 Power Other VCC AJ15 Power Other VCC AM30 Power Other vcc AJ18 Power Other VCC AM8 Power Other VCC AJ19 Power Other VEG AM9 Power Other Vcc AJ21 Power Other VCC AN11 Power Other VCC AJ22 Power Other VEC AN12 Power Other WCC AJ25 Power Other VCC AN14 Power Other VCC AJ26 Power Other VCC AN15 Power Other vcc AJ8 Power Other VCC AN18 Power Other VCC AJ9 Power Other VEC AN19 Power Other WCC AK11 Power Other VCC AN21 Power Other Datasheet 49 50 intel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land em s Direction Land Name Land d nad Direction VCC AN22 Power Other vcc M8 Power Other VCC AN25 Power Other VCC N23 Power Other VCC AN26 Power Other vcc N24 Power Other VCC AN29 Power Other VCC N25 Power Other VCC AN30 Power Other YCC N26 Power Other VCC AN8 Power Other vcc N27 Power Other VCC AN9 Power Other VCC N28 Power Other VCC J10 Power Other VCC N29 Power Other VCC J11 Power Other Vcc N30 Power Other VCC J12 Power Other vcc N8 Power Other
62. LK 1 0 BSEL 2 0 A 35 3 ADS ADSTB 1 0 BNR BPRI COMP 8 3 0 FERR PBE IERR IGNNE D 63 0 DBI 3 0 DBSY DEFER INIT ITP_CLK 1 0 LINTO INTR LINT1 DRDY DSTBN 3 0 DSTBP 3 0 HIT NMI MSID 1 0 PWRGOOD RESET SMI HITM LOCK PROCHOT REQ 4 0 STPCLK TDO TDO_M TESTHI 10 7 0 RS 2 0 TRDY THERMTRIP VID 7 0 GTLREF 3 0 TCK TDI TDI M TMS TRST VTT SEL Open Drain Signals THERMTRIP FERR PBE IERR BPM 5 0 BPMb 3 0 BRO TDO TDO_M FCx NOTES 1 Signals that do not have R y nor are actively driven to their high voltage level Signal Reference Voltages GTLREF V11 2 BPM 5 0 BPMb 3 0 RESET BNR HIT HITM BRO A 35 0 ADS ADSTB 1 0 BPRI D 63 0 DBI 3 0 DBSY DEFER DRDY DSTBN 3 0 DSTBP 3 0 LOCK REQ 4 0 RS 2 0 TRDY A20M LINTO INTR LINT1 NMI IGNNE INIT PROCHOT PWRGOOD SMI STPCLK TCK TDI TDI M TMS TRST NOTE 1 See Table 2 10 for more information 27 2 7 3 Table 2 9 Table 2 10 28 n t el Electrical Specifications CMOS and Open Drain Signals Legacy input signals such as A20M IGNNE INIT SMI and STPCLK use CMOS input buffers All of the CMOS and Open Drain signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Se
63. Other VSS AL16 Power Other vss AG17 Power Other VSS AL17 Power Other VSS AG20 Power Other VSS AL20 Power Other vss AG23 Power Other VSS AL23 Power Other vss AG24 Power Other VSS AL24 Power Other VSS AG7 Power Other VSS AL27 Power Other VSS AH1 Power Other VSS AL28 Power Other VSS AH10 Power Other VSS AL7 Power Other VSS AH13 Power Other VSS AM1 Power Other vss AH16 Power Other VSS AM10 Power Other VSS AH17 Power Other VSS AM13 Power Other VSS AH20 Power Other VSS AM16 Power Other vss AH23 Power Other VSS AM17 Power Other VSS AH24 Power Other VSS AM20 Power Other VSS AH3 Power Other VSS AM23 Power Other VSS AH6 Power Other VSS AM24 Power Other VSS AH7 Power Other VSS AM27 Power Other VSS AJ10 Power Other VSS AM28 Power Other VSS AJ13 Power Other VSS AMA Power Other VSS AJ16 Power Other VSS AN1 Power Other VSS AJ17 Power Other VSS AN10 Power Other VSS AJ20 Power Other VSS AN13 Power Other vss AJ23 Power Other VSS AN16 Power Other VSS AJ24 Power Other VSS AN17 Power Other VSS AJ27 Power Other VSS AN2 Power Other VSS AJ28 Power Other VSS AN20 Power Other VSS AJ29 Power Other VSS AN23 Power Other VSS AJ30 Power Other VSS AN24 Power Other VSS AJ4 Power Other VSS AN27 Power Other VSS AJ7 Power Other VSS AN28 Power Other VSS AK10 Power Other VSS C10 Power Other VSS AK13 Power Other VSS C13 Power Other VSS AK16 Power Other VSS C16 Power Other vss AK17 Power Other VSS C19 Power Other VSS AK2 Power Other VSS C22 Power Other vss AK20 Power Other VSS C24
64. Output D12 D8 Source Synch Input Output A30 AG4 Source Synch Input Output D13 B12 Source Synch Input Output A31 AG5 Source Synch Input Output D14 C12 Source Synch Input Output A323 AH4 Source Synch Input Output D15 Dil Source Synch Input Output A33 AH5 Source Synch Input Output D16 G9 Source Synch Input Output A34 AJ5 Source Synch Input Output D17 F8 Source Synch Input Output A35 AJ6 Source Synch Input Output D18 F9 Source Synch Input Output A20M K3 Asynch CMOS Input D19 E9 Source Synch Input Output ADS D2 Common Clock Input Output D20 D7 Source Synch Input Output ADSTBO R6 Source Synch Input Output D21 E10 Source Synch Input Output ADSTB1 AD5 Source Synch Input Output D22 D10 Source Synch Input Output BCLKO F28 Clock Input D23 Fil Source Synch Input Output BCLK1 G28 Clock Input D24 F12 Source Synch Input Output BNR c2 Common Clock Input Output D25 D13 Source Synch Input Output BPMO AJ2 Common Clock Input Output D26 E13 Source Synch Input Output BPM1 AJi Common Clock Input Output D27 G13 Source Synch Input Output BPM2 AD2 Common Clock Input Output D28 F14 Source Synch Input Output BPM3 AG2 Common Clock Input Output D29 G14 Source Synch Input Output BPM4 AF2 Common Clock Input Output D30 F15 Source Synch Input Output BPM5 AG3 Common Clock Input Output D31 G15 Source Synch Input Output Datasheet Land Listing and Signal Descriptions Datash
65. P1 DSTBN1 DSTBP2 DSTBN2 DSTBP3 DSTBN3 Datasheet Electrical Specifications Table 2 6 Table 2 7 Table 2 8 Datasheet intel FSB Signal Groups Sheet 2 of 2 Signal Group Type Signals Synchronous to GTL Strobes BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 A20M DPSLP DPRSTP IGNNE INIT LINTO CMOS INTR LINT1 NMI SMI 3 STPCLK PWRGOOD SLP TCK TDI TDI M TMS TRST BSEL 2 0 VID 7 0 PSI Open Drain FERR PBE IERR THERMTRIP TDO TDO_M Output Open Drain 4 Input Output PROCHOT FSB Clock Clock BCLK 1 0 ITP_CLK 1 0 2 VCC VTT VCCA VCCIOPLL VCCPLL VSS VSSA GTLREF 3 0 COMP 8 3 0 RESERVED TESTHI 10 7 0 Power Other VCC_SENSE VCC_MB_REGULATION VSS_SENSE VSS_MB_REGULATION DBR 2 VTT_OUT_LEFT VTT_OUT_RIGHT VTT_SEL FCx PECI MSID 1 0 NOTES 1 Refer to Section 4 2 for signal descriptions 2 In processor systems where no debug port is implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 3 The value of these signals during the active to inactive edge of RESET defines the processor configuration options See Section 6 1 for details 4 PROCHOT signal type is open drain output and CMOS input Signal Characteristics Signals with Ry Signals with No R t A20M BC
66. PECI Fault Handling Requirements s ssssssssssrsrrrerrnrrrerrrrrrrsrrrrrens 87 5 3 2 4 PECI GetTempO Error Code Support ssesseseee 87 FeatU res occid HR SE DREAR ANM CUENTA FXERIANE ERA VM NEREA ra a ethos REN PIXL KAMERA ome ERA MER 89 6 1 Power On Configuration Options ccececeee cece eee e eee memes enemememe nemen nen 89 6 2 Clock Control and Low Power StatesS cccceeeee eens ee eee eee e ee eee nent neta eene eene 89 6 2 1 Normal State i ice ea e dena esee Ru deine vipat RI Ker SU DAE CEA RICE E 90 6 2 2 HALT and Extended HALT Powerdown States sssssssesee enn 90 6 2 2 1 HALT Powerdown State sessssssssssseseenenenee menn 90 6 2 2 2 Extended HALT Powerdown State ssssssssesee nne 91 6 2 3 Stop Grant and Extended Stop Grant States sssessssssseeeeers 91 6 2 3 1 Stop Grdht States iocus ote nube a hatamas etenbeagazenteberenas oases 91 6 2 3 2 Extended Stop Grant State erra a ie eee naa gane kx as 92 6 2 4 Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State cceeeeeeeeeeeeeeeee ees 92 6 2 4 1 HALT Snoop State Stop Grant Snoop State ceceeeeeee ener ee ee eee 92 6 2 4 2 Extended HALT Snoop State Extended Stop Grant Snoop State 92 6 2 5 SIGE P State T 92 6 2 6 Deep Sleep State eee sonal sas dekve din aia ties a sura ks vated N er N 93 6 2 7 D eper Sleep State
67. Power Other A22 D62 Source Synch Input Output AN6 a ot Power Other Output A23 VCCA Power Other AN7 VID_SELECT Power Other Output A24 FGS Powernother AN8 VCC Power Other A25 MU Power Other AN9 VCC Power Other A26 MEE Power Other ANio VSS Power Other A27 Y Power Orner ANII vec Power Other AZB va Boner aie ANi2 VCC Power Other A23 ym Power Diner AN13 VSS Power Other nee NT Power other AN14 VCC Power Other Bi Ss Power Other AN15 VCC Power Other B10 D10 Source Synch Input Output AN16 VSS Power Other B ss Fowerother Datasheet Land Listing and Signal Descriptions Datasheet intel Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment n Land Name P Direction 2 Land Name ici d Direction B12 D13 Source Synch Input Output C20 DBI3 Source Synch Input Output B13 COMP8 Power Other Input C21 D58 Source Synch Input Output B14 VSS Power Other C22 VSS Power Other Bi5 D53 Source Synch Input Output C23 VCCIOPLL Power Other B16 D55 Source Synch Input Output C24 VSS Power Other B17 VSS Power Other C25 VTT Power Other B18 D57 Source Synch Input Output C26 VTT Power Other B19 D60 Source Synch Input Output C27 VTT Power Other B2 DBSY Common Clock Input Output C28 VTT Power Other B3 RSO Common Clock Input C29 VTT Power Other B4 DOO Source Synch Input Output C
68. S VSS VSS VSS AA VSS VSS VSS VSS VSS VSS VSS VSS Y VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC w V VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS VSS P VSS VSS VSS VSS VSS VSS VSS VSS N VCC VCC VCC VCC VCC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VCC L VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC FC34 FC31 VCC BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC33 FC32 G BSEL2 BSELO BCLK1 TESTHI4 TESTHIS TESTHI3 TESTHI6 RESET D47 D44 DSTBN2 DSTBP2 D35 D36 D32 D31 FC26 VSS VSS VSS VSS FC10 RSVD D45 D42 VSS D40 D39 VSS D34 D33 NTT VTT VTT VTT VTT VSS VCCPLL D46 VSS D48 DBI2 VSS D49 RSVD VSS VSS SEI VSS D58 DBI3 VSS D54 DSTBP3 VSS D51 5 3 3 j VSS VSSA D63 D59 VSS D60 D57 VSS D55 D53 F RSVD BCLKO VTT SEL TESTHIO TESTHI2 TESTHI7 RSVD VSS D43 D41 VSS D38 D37 VSS D30 VTT VTT VTT VTT E FC23 VCCA D62 VSS RSVD D61 VSS D56 DSTBN3 VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 44 Datasheet Land Listing and Signal Descriptions Figure 4 2 land out Diagram Top View Right Side
69. SB while the processor is in Sleep Datasheet Features 6 2 6 6 2 7 Datasheet intel state Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through the Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin See Section 6 2 6 While the processor is in the Sleep state the SLP pin must be deasserted if another asynchronous FSB event needs to occur PECI is not available and will not respond while in the Sleep State Deep Sleep State The Deep Sleep state is entered through assertion of the DPSLP pin while in the Sleep state BCLK may be stopped during the Deep Sleep state for additional platform level power savings BCLK stop restart timings on appropriate chipset based platforms with the CK505 clock chip are as f
70. STBP2 D 63 48 DBI3 DSTBP3 FCO BOOTSELECT FCx Other Other FCO BOOTSELECT is not used by the processor When this land is tied to Vss previous processors based on the Intel NetBurst microarchitecture should be disabled and prevented from booting FC signals are signals that are available for compatibility with other processors 67 intel Land Listing and Signal Descriptions Table 4 3 Signal Description Sheet 5 of 10 Name FERR PBE GTLREF 3 0 Type Output Input Description FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer
71. Thermal Specifications and Design Considerations cccceeeeeee eee eee eens ee eaees 75 5 1 Processor Thermal Specifications si icc esiccasccserscarcrsivetetecescetsedeanecesaasnaeshed sesvaneaia eed 75 Bill Thermal Specification iere odd tae ca ose vote ted aeo aan xa icu AEN E 75 5 1 2 Thermal Metrology i e rero ritatis sao qo senes ka tea e e a aa 82 5 2 Processor Thermal Features i eiii coii teet tse i ene tea Desa sna aaa Reap xL D bd bna RUE Ed 82 5 2 1 Thermal MONItO isesi anyana naaa EEEE SR Eana TA AME aa REGE 82 5 2 2 Thermal Monitor 2 ose eran retue rores qeu Te ERA ax Re a Ka init aC RR RUD AME EAE 83 Datasheet 3 ntel 5 2 3 On Demand Modes pdade upelire Meteegden da cipia siege Hadeglaaielied decrees 84 52 4 lt PROGHOT SIGNAL 2 exuti intuetur a a Dameck bae ee st n bue REM AKTE EAR rn AER iow AREE A 85 5 2 5 TTHERMTRIP 3 Signal 5 toria Peek xoc genet ula eR E NTDRNAS aves anke ERA Mi pM EM OTROS 85 5 3 Platform Environment Control Interface PECI sssessssssseeeem mnn 86 53d TntrodUCtioMeni T 86 5 3 1 1 TCONTROL and TCC activation on PECI Based Systems 86 5 3 2 PECI Specifications n iiie prece eee eh na nata n EERIAR EINER dane PIRE PA EDI ence Bes 87 5 3 2 1 PECL Device Address ise xix rsen ce Feier ka xa boae ka RR EREFRA RR TRAR 87 5 3 2 2 PECI Command SUpDpOFt i cene smaidi Ean exa E x nna nace 87 5 3 2 3
72. Voltage Identification Definition Table 2 1 o9 Ln Ln Ln in Ln Ln Ln Ln Ln Ln Ln Ln Ln in Ln in Ln Ln Ln in Ln Ln 2 Is la ia P UR fee feo IS E IN la IS HR e eo f IRIN oo IN IRIN JO IR IR I IN IN IR IL 0 IN RIA oo IS IR e o IN IRIN lin u S JX Ja J Joo x le o m IQ fa 9 e Ts xo Joo Joo Gi 9 Joo N Joo JIN e JN Ja I Joo 5 ko ko Ion QI Ja Joo 5 xo fun Joo FA Ja e fic el le DY e IY Jos JO Jae OS L J 1 ls 2 1B JO IA Ye IA Joo JA Je IP JO JS JL JO jo JO J IO JO Oe ID Ig JM J ID JO JO S Hr o O lo o O jo o O jo o O jo o O jo o O jo o O jo o O jo o O jo o O jo a Ee o jo Jo Jo Ja Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo lo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo o Jo Jo o Jo Jo o Jo Jo a Bt lo l Je f fe f7 le e le l7 J Jt fe J JO ft e le l le f7 fe Jr e I JO le l7 le f7 fe r e J JO Fo JO Jr le j7 Jr a En ald lo o JA la o lo la ia JO lo la ia 10 JO la la JO lo lia la lo o la la lo lo la la lo lbo la la lo lo la la lo lo liu la lo lo iw a did O JO JO O n n et I O JO JO JO m n n n O O JO JO Q1 n et J O JO JO JO mM et n ot O JO O O XA m m Jo O JO a a EM rd r4 O JO JO JO JO JO JO JO n n n n n n n n O JO O JO JO JO JO JO n n n m et n et JO O O JO JO JO JO O n
73. Voltage Regulator Design Guide for more information This input should be left as a no connect in order for the processor to boot The processor will not boot on legacy platforms where this land is connected to Vss VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane VSSA Input VSSA provides isolated ground for internal PLLs on previous generation processors It may be left as a No Connect on boards supporting the processor VSS_SENSE Output VSS_SENSE is an isolated low impedance connection to processor core Vss It can be used to sense or measure ground near the silicon with little noise VSS_MB_ REGULATION Output This land is provided as a voltage regulator feedback sense point for Vss It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator Design Guide VTT Miscellaneous voltage supply VTT OUT LEFT VTT OUT RIGHT VTT SEL Output Output The VTT OUT LEFT and VTT OUT RIGHT signals are included to provide a voltage supply for some signals that require termination to Vz on the motherboard The VTT SEL signal is used to select the correct Vr voltage level for the processor This land is connected internally in the package to Vss 73 74 Land Listing and Signal Descriptions Datasheet e Thermal Specifications and Design Considerations
74. XT is a key element in Intel s safer computing initiative that defines a set of hardware enhancements that operate with an Intel TXT enabled operating system to help protect against software based attacks It creates a hardware foundation that builds on Intel s Virtualization Technology to help protect the confidentiality and integrity of data stored created on the client PC 10 Datasheet Introduction 1 Note Note Datasheet intel Introduction The Intel Core 2 Extreme processor QX9000 series and Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series are based on the Enhanced Intel Core microarchitecture The Enhanced Intel Core microarchitecture combines the performance of previous generation Desktop products with the power efficiencies of a low power microarchitecture to enable smaller quieter systems The Intel Core 2 Extreme processor QX9000 series and Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series are 64 bit processors that maintains compatibility with IA 32 software The processors use a Flip Chip Land Grid Array FC LGA6 package technology and plugs into a 775 land surface mount Land Grid Array LGA socket referred to as the LGA775 socket In this document the Intel Core 2 Extreme processor QX9000 series and the Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series may be referred to simply as the processor The following pro
75. able 2 5 Vcc Overshoot The processor can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max is the maximum allowable overshoot voltage The time duration of the overshoot event must not exceed Tos max Tos max is the maximum allowable time duration above VID These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands Vcc Overshoot Specifications Symbol Parameter Min Max Unit Figure Notes Vos maX ME of Vcc overshoot above m 50 mV 2 2 1 Time duration of Vcc overshoot above Tos Max VID es m 25 Hs 2 2 NOTES 1 Adherence to these specifications is required to ensure reliable processor operation Figure 2 2 Vcc Overshoot Example Waveform 2 6 4 Datasheet Example Overshoot Waveform VID 0 050 Vos o o S 9 gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID NOTES 1 Vos is measured overshoot voltage 2 Tos is measured time duration above VID Die Voltage Validation Overshoot events on processor must meet the specifications in Table 2 5 when measured across the VCC SENSE and VSS SENSE lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot must be ta
76. al Representation of the Boxed Processor 66 0 2 6 fete nh NOTE The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Datasheet 95 m n tel Boxed Processor Specifications 7 2 Mechanical Specifications 7 2 1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor The boxed processor will be shipped with an unattached fan heatsink Figure 7 1 shows a mechanical representation of the boxed processor Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7 2 Side View and Figure 7 3 Top View The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 7 7 and Figure 7 8 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning Figure 7 2 Space Requirements for the Boxed Processor side view 95 0 It pa A 81 3 3 2 10 0 25 0 1039 0 98 y Figure 7 3 Space Requirements for the Boxed Processor top view a 9
77. al input needed for JTAG specification support TDI connects to core 0 TDI M connects to core 1 TDO TDO M Output TDO and TDO M Test Data Out transfers serial test data out of the processor TDO and TDO M provide the serial output needed for JTAG specification support TDO connects to core 1 TDO M connects to core 0 TESTHI 10 7 0 Input TESTHI 10 7 0 must be connected to the processor s appropriate power source refer to VTT OUT LEFT and VIT OUT RIGHT signal description through a resistor for proper processor operation See Section 2 4 for more details Datasheet Z1 im e n tel Land Listing and Signal Descriptions Table 4 3 Signal Description Sheet 9 of 10 Name Type Description In the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature approximately 20 C above the maximum Tc Assertion of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Driving of the THERMTRIP signal is enabled within 10 us of the assertion of PWRGOOD provided Vr and Vcc are asser
78. and system Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology e Voltage Frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency If the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals after which the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals Processor Power Status Indicator PSI Signal The processor incorporates the PSI signal that is asserted when the processor is in a reduced power consumption state PSI can be used to improve efficiency of the voltage regulator resulting in platform power savings PSI may be asserted only when the processor is in the Deeper Sleep state Datasheet m Boxed Processor Specifications l n t e 7 Boxed Processor Specifications 7 1 Introduction The Intel Core 2 Extreme processor QX9650 Intel Core 2 quad core processor Q9000 Q9000S Q8000
79. cations The processor can be inserted into and removed from a LGA775 socket 15 times The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide Processor Mass Specification The typical mass of the processor is 21 5 g 0 76 oz This mass weight includes all the components that are included in the package Processor Materials Table 3 3 lists some of the package components and associated materials Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings Figure 3 5 and Figure 3 6 show the topside markings on the processor This diagram is to aid in the identification of the processor Processor Top Side Markings Example Intel Core 2 Extreme Processor QX9650 INTEL 06 QX9650 INTEL CORE 2 EXTREME SLAN3 XXXX 3 00GHA 2 3337 058 FPO 94 Datasheet Package Mechanical Specifications Figure 3 6 Processor Top Side Markings Example Intel Core 2 Quad Processor Q9000 Datasheet Series INTEL 06 Q9550 INTEL CORE 2 Quad SLANS SOK 2 83GHZ 2M 1333 05A FPO 4 41 Package Mechanical Specifications 1 Figure 3 7 shows the top view of the processor land coordinates The coordinates are referred to throughout the document to identify processor lands Processor Land Coord
80. ce must be added to the motherboard to properly decouple the return currents from the front side bus Bulk decoupling must also be provided by the motherboard for proper A GTL bus operation Voltage Identification The Voltage Identification VID specification for the processor is defined by the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC lands see Chapter 2 6 3 for Vcc overshoot specifications Refer to Table 2 11 for the DC specifications for these signals Voltages for each processor frequency is provided in Table 2 3 To support the Deeper Sleep State the platform must use a VRD 11 1 compliant solution The Deeper Sleep State also requires additional platform support For further information on Voltage Regulator Down solutions contact your Intel field representative Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings This is reflected by the VID Range values provided in Table 2 3 Refer to the Intel Core 2 Extreme Processor QX9000 Series and Intel Core 2 Quad Processor Q9000 Q9000S Q8000 and Q8000S Series Specification Update for further details on specific valid core frequency and VID values of the processor Note that this differs from the VID employed by the
81. cent clock periods must be less than the period stability 4 Slew rate is measured through the VSWING voltage range centered about differential zero Measurement taken from differential waveform 5 Matching applies to rising edge rate for Clock and falling edge rate for Clock It is measured using a 75 mV window centered on the average cross point where Clock rising meets Clock falling The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations 6 Duty Cycle High time Period must be between 40 and 60 33 m n t el Electrical Specifications Figure 2 3 Differential Clock Waveform Overshoot VH Rising Edge Ringback MERE oe i Ringback Threshold f j Verossiass V Margin Region ee eet eS 1 int Falling Edge udi pAotQqeseee Eeyeegeeeee rtpeebe eI Ringback VL Undershoot Tp T1 BCLK 1 0 period T2 BCLK 1 0 period stability not shown Tph T3 BCLK 1 0 pulse high time Tpl T4 BCLK 1 0 pulse low time T5 BCLK 1 0 rise time through the threshold region T6 BCLK 1 0 fall time through the threshold region Figure 2 4 Measurement Points for Differential Clock Waveforms Slew_rise Slew _fall T5 BCLK 1 0 rise and fall time through the swing region 34 Datasheet m e Package Mechanical Specifications n t el 3 Figure 3 1 3 1 Datasheet Package Mechanical Specifications T
82. ch patents trademarks copyrights or other intellectual property rights The Intel Core 2 Extreme processor QX9000 series and Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor number for details Intel 64 requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 Processor will not operate including 32 bit operation without an Intel 64 enabled BIOS Performance will vary depending on your hardware and software configurations See http www intel com info em64t for
83. chassis that provide good thermal management For the boxed processor fan heatsink to operate properly it is critical that the airflow provided to the fan heatsink is unimpeded Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life Figure 7 7 and Figure 7 8 illustrate an acceptable airspace clearance for the fan heatsink The air temperature entering the fan should be kept below 38 C Again meeting the processor s temperature specification is the responsibility of the system integrator Boxed Processor Fan Heatsink Airspace Keepout Requirements side 1 view R55 2 2 17 81 3 3 2 99 Figure 7 9 Table 7 2 100 n t el Boxed Processor Specifications Variable Speed Fan If the boxed processor fan heatsink 4 pin connector is connected to a 3 pin motherboard header it will operate as follows The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures This allows the processor fan to operate at a lower speed and noise level while internal chassis temperatures are low If internal chassis temperature increases beyond a lower set point the fan speed will rise linearly with the internal t
84. ction 2 7 3 for the DC specifications See Section 6 2 for additional timing requirements for entering and leaving the low power states Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless otherwise stated All specifications apply to all frequencies and cache sizes unless otherwise stated GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0 10 GTLREF 0 10 V 2 5 Vin Input High Voltage GTLREF 0 10 Vr 0 10 V 3 4 5 VoH Output High Voltage Vr 0 10 VTT V 4 5 V I Output Low Current N A TTE A oL j R r_min 2 Ron_min Input Leakage Ij Currant N A 100 HA 6 Output Leakage ILo Currant N A 100 HA 7 Ron Buffer On Resistance 7 5 11 Q NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 3s Vin is defined as the voltage range at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above V The V referred to in these specifications is the instantaneous V Leakage to Vss with land held at V Leakage to V with land held at 300 mV SLO mo Open Drain and TAP Output Signal Group DC Specifications Symbol Pa
85. ding low power state requires chipset support and may not be available on all platforms NOTE Some processors may not have the Sleep State enabled refer to the Specification Update for specific sku and stepping guidance SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the de assertion of RESET the processor will tri state its outputs STPCLK TCK Input Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is de asserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI M Input TDI and TDI M Test Data In transfers serial test data into the processor TDI and TDI M provide the seri
86. dition for the processor Under this condition the core frequency to FSB multiple utilized by the processor is that contained in the CLK GEYSIII STAT MSR and the VID is that specified in Table 2 3 These parameters represent normal system operation The second operating point consists of both a lower operating frequency and voltage When the TCC is activated the processor automatically transitions to the new frequency This transition occurs very rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will likely be one VID table entry see Table 2 3 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is
87. ducts are covered in this document e The Intel Core 2 Extreme processor QX9000 series refers to the QX9770 and QX9650 e The Intel Core 2 Quad processor Q9000 series refers to the Q9650 Q9550 Q9505 Q9450 Q9400 and Q9300 e The Intel Core 2 Quad processor Q9000S series refers to the Q9550S Q9505S and Q9400S e The Intel Core 2 Quad processor Q8000 series refers to the Q8200 Q8300 Q8400 e The Intel Core 2 Quad processor Q8000S series refers to the Q8200S and Q8400S The processor is based on 45 nm process technology The processor features the Intel Advanced Smart Cache a shared multi core optimized cache that significantly reduces latency to frequently used data The processors feature 1600 MHz and 1333 MHz front side bus FSB frequencies The processors also feature two independent but shared 12 MB of L2 cache 2x6M two independent but shared 8 MB of L2 cache 2x4M two independent but shared 6 MB of L2 cache 2x3M or two independent but shared 4 MB of L2 caches 2x2M The processor supports all the existing Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 Supplemental Streaming SIMD Extension 3 SSSE3 and the Streaming SIMD Extensions 4 1 SSE4 1 The processor supports several Advanced Technologies Execute Disable Bit Intel 64 architecture Intel 64 and Enhanced Intel SpeedStep Technology In addition the Intel Core 2 Extreme processor QX9000 series Intel Core
88. e bus signals For unused GTL input or I O signals use pull up resistors of the same value as the on die termination resistors Rrr For details see Table 2 13 TAP and CMOS signals do not include on die termination Inputs and used outputs must be terminated on the motherboard Unused outputs may be terminated on the motherboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing All TESTHI 10 7 0 lands should be individually connected to V via a pull up resistor which matches the nominal trace impedance The TESTHI signals may use individual pull up resistors or be grouped together as detailed below A matched resistor must be used for each group e TESTHI 1 0 e TESTHI 7 2 e TESTHI10 cannot be grouped with other TESTHI signals Terminating multiple TESTHI pins together with a single pull up resistor is not recommended for designs supporting boundary scan for proper Boundary Scan testing of the TESTHI signals For optimum noise margin all pull up resistor values used for TESTHI 10 7 0 lands should have a resistance value within 20 of the impedance of the board transmission line traces For example if the nominal trace impedance is 50 Q then a value between 40 Q and 60 Q should be used Power Segment Identifier PSID Power Segment Identifier PSID is a mechanism to prevent booting under mismatched power requi
89. eatures 6 2 3 2 6 2 4 6 2 4 1 6 2 4 2 6 2 5 92 Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK signal is asserted and Extended Stop Grant has been enabled using BIOS The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state When entering the low power state the processor will first switch to the lower bus ratio and then transition to the lower VID The processor exits the Extended Stop Grant state when a break event occurs When the processor exits the Extended Stop Grant state it will resume operation at the lower frequency transition the VID to the original value and then change the bus ratio back to the original value Extended HALT Snoop State HALT Snoop State Extended Stop Grant Snoop State and Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the Extended HALT state If Extended HALT state is not enabled in the BIOS the default Snoop State entered will be the HALT Snoop State Refer to the sections below for details on HALT Snoop State Stop Grant Snoop State Extended HALT Snoop State Extended Stop Grant Snoop State HALT Snoop State Stop Grant Snoop State The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT powerdown state During a snoop transaction the processor enters the HALT Snoop State Stop Grant S
90. eeper Sleep is initiated by DPRSTP de assertion PECI is not available and will not respond while in the Deeper Sleep State 93 n tel Features 6 3 94 In response to entering Deeper Sleep the processor drives the VID code corresponding to the Deeper Sleep core voltage on the VID pins Unlike typical Dynamic VID changes where the steps are single VID steps the processor will perform a VID jump on the order of 100 mV To support the Deeper Sleep State the platform must use a VRD 11 1 compliant solution Enhanced Intel SpeedStep Technology The processor supports Enhanced Intel SpeedStep Technology This technology enables the processor to switch between frequency and voltage points which may result in platform power savings In order to support this technology the system must support dynamic VID transitions Switching between voltage frequency states is software controlled Enhanced Intel SpeedStep Technology is a technology that creates processor performance states P states P states are power consumption and capability states within the Normal state as shown in Figure 6 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor
91. eet Table 4 1 Alphabetical Land Table 4 1 intel Alphabetical Land Assignments Assignments Land Name Land Vise odd Direction Land Name Land S e Direction D32 G16 Source Synch Input Output DSTBPO B9 Source Synch Input Output D33 E15 Source Synch Input Output DSTBP1 E12 Source Synch Input Output D34 E16 Source Synch Input Output DSTBP2 G19 Source Synch Input Output D35 G18 Source Synch Input Output DSTBP3 C17 Source Synch Input Output D36 G17 Source Synch Input Output Lu ES Yi Power Other D37 F17 Source Synch Input Output D38 F18 Source Synch Input Output FCS J2 Power Other D39 E18 Source Synch Input Output FCB AK6 Power Other D40 E19 Source Synch Input Output FC10 E24 Power Other D41 F20 Source Synch Input Output FCIS H29 Power Dther D42 E21 Source Synch Input Output POLS AES Power Other D43 F21 Source Synch Input Output FC2D ES Power Other D44 G21 Source Synch Input Output peat F6 Power Other D45 E22 Source Synch Input Output FC22 J3 Power Other D46 D22 Source Synch Input Output FC23 A24 Power Other D47 G22 Source Synch Input Output FC24 AKI Power Dther D48 D20 Source Synch Input Output FC25 ALE Power O
92. egulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details 4 Adherence to this loadline specification is required to ensure reliable processor operation Datasheet 23 intel Figure 2 1 24 Electrical Specifications Vcc Static and Transient Tolerance Vcc V ES EL XO eS cR Ide SS ao X E We EC c ce de E e U O UU UU UU cO Uc UvcUvcgc Ug Icc A 0 10 20 30 40 50 60 70 80 90 100 110 120 0 000 i i i l i i i 0 013 4 0 025 4 0 038 Vcc Maximum 0 050 4 0 063 4 0 075 4 0 088 4 0 100 4 Oia Vcc Typical 0 125 4 0 138 P 0 150 4 Vcc Minimum 0 163 4 0 175 4 0 188 4 0 200 4 0 213 4 0 225 4 NOTES 1 2 3i The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 This loadline specification shows the deviation from the VID set point The loadlines specify voltage limits at the die measured at the VCC SENSE and VSS SENSE lands Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands Refer to the Voltage Regulator Design Guide for socket loadline guidelines and VR implementation details Datasheet m Electrical Specifications n t el 2 6 3 T
93. emperature until the higher set point is reached At that point the fan speed is at its maximum As fan speed increases so does fan noise levels Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler then lower set point These set points represented in Figure 7 9 and Table 7 2 can vary by a few degrees from fan heatsink to fan heatsink The internal chassis temperature should be kept below 38 C Meeting the processor s temperature specification see Chapter 5 is the responsibility of the system integrator The motherboard must supply a constant 12 V to the processor s power header to ensure proper operation of the variable speed fan for the boxed processor Refer to Table 7 1 for the specific requirements Boxed Processor Fan Heatsink Set Points Higher Set Point Highest Noise Level Increasing Fan Speed amp Noise Lower SetPoint Lowest Noise Level X Y Z Internal Chassis Temperature Degrees C Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Boxed Processor Fan Speed Notes Point C When the internal chassis temperature is below or equal to this set point the fan operates at its lowest speed Recommended 1 maximum internal chassis temperature for nominal operating environment X lt 30 When the internal chassis temperature is at this point the fan operates between its lowest and highes
94. er AJ26 VCC Power Other AL12 VCC Power Other AJ27 VSS Power Other AL13 VSS Power Other AJ28 VSS Power Other AL14 VCC Power Other AJ29 VSS Power Other AL15 VCC Power Other AJ30 VSS Power Other AL16 VSS Power Other AK1 FC24 Power Other AL17 VSS Power Other AK2 VSS Power Other AL18 VCC Power Other AK3 ITP_CLKO TAP Input AL19 VCC Power Other AK4 VID4 Asynch CMOS Output AL20 VSS Power Other AK5 VSS Power Other AL21 VCC Power Other AK6 FC8 Power Other AL22 VCC Power Other AK7 VSS Power Other AL23 VSS Power Other AK8 VCC Power Other AL24 VSS Power Other AK9 VCC Power Other AL25 VCC Power Other AK10 VSS Power Other AL26 VCC Power Other AK11 VCC Power Other AL27 VSS Power Other AK12 Vcc Power Other AL28 VSS Power Other AK13 VSS Power Other AL29 VCC Power Other AK14 VCC Power Other AL30 VCC Power Other AK15 VCC Power Other AM1 VSS Power Other 57 58 intel Land Listing and Signal Descriptions Table 4 2 Numerical Land Table 4 2 Numerical Land Assignment Assignment Land Land Name Signal Buffer Direction Land Land Name Signal Buffer Direction Type Type AM2 VIDO Asynch CMOS Output AN17 VSS Power Other AM3 VID2 Asynch CMOS Output AN18 VCC Power Other AM4 VSS Power Other AN19 VCC Power Other AM5 VID6 Asynch CMOS Out
95. er fan revolution A baseboard pull up resistor provides Voy to match the system board mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL The boxed processor s fanheat sink requires a constant 12 V supplied to pin 2 and does not support variable voltage control or 3 pin PWM control 97 intel Boxed Processor Specifications The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentation or on the system board itself Figure 7 6 shows the location of the fan power connector relative to the processor socket The baseboard power header should be positioned within 110 mm 4 33 inches from the center of the processor socket Figure 7 5 Boxed Processor Fan Heatsink Power Cable Connector Description Pin AUN Signal GND 12 V SENSE CONTROL H vH of L AE Num Straight square pin 4 pin terminal housing with polarizing ribs and friction locking ramp 0 100 pitch 0 025 square pin width Match with straight pin friction lock header on mainboard Table 7 1 Fan Heatsink Power and Signal Specificat
96. ernal processor FSB PLLs VCC SENSE is an isolated low impedance connection to processor VCC SENSE Output core power Vcc It can be used to sense or measure voltage near the silicon with little noise This land is provided as a voltage regulator feedback sense point for Vcc It is connected internally in the processor package to the Output sense point land U27 as described in the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket VCC_MB_ REGULATION 72 Datasheet Land Listing and Signal Descriptions Table 4 3 Datasheet intel Signal Description Sheet 10 of 10 Name VID 7 0 Type Output Description The VID Voltage ID signals are used to support automatic selection of power supply voltages Vcc Refer to the Voltage Regulator Design Guide for more information The voltage supply for these signals must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID signals becomes valid The VID signals are needed to support the processor voltage specification variations See Table 2 1 for definitions of these signals The VR must supply the voltage that is requested by the signals or disable itself VID_SELECT VRDSEL Output Input This land is tied high on the processor package and is used by the VR to choose the proper VID table Refer to the
97. essor QX9000 series Intel Q8200S Core 2 Quad processor Q9650 Q9550 e FSB frequency at 1333 MHz Intel Core 2 Q9550S and Q9450 Extreme processor QX9650 Intel Core 2 e Two 4 MB Level 2 caches Intel Core 2 Quad Q9000 Q9000S Q8000 and Q8000S Quad processor Q9505 95055 Q8400 series only and Q8400S e FSB frequency at 1600 MHz Intel Core 2 two 3 MB Level 2 caches Intel Core 2 Extreme processor QX9770 only Quad processor Q9400 Q9400S and e Enhanced Intel SpeedStep Technology Q9300 Supports Intel 64 architecture e Two 2 MB Level 2 caches Intel Core 2 e Supports Intel virtualization Technology Quad processor Q8200 Q8200S and Intel Core 2 Extreme processor QX9650 Q8300 Intel Core 2 Quad processor Q9000 and e Intel HD Boost utilizing new SSE4 Q9000S series Intel Core 2 Quad instructions for improved multimedia processors Q8400 and Q8400S only performance especially for video encoding e Supports Intel Trusted Execution and photo processing Technology Intel Core 2 Quad processor e System Management mode Q9000 and Q9000S series only e 12 way cache associativity provides e Low power processor Intel Core 2 Quad improved cache hit rate on load store processor Q9000S and Q8000S series only operations e 775 land Package The Intel Core 2 Extreme processor QX9000 series and Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series deliver Intel s advanced p
98. essor frequencies 2 GTLREF is to be generated from VTT by a voltage divider of 1 resistors If an Variable GTLREF circuit is used on the board the GTLREF lands connected to the Variable GTLREF circuit may require different resistor values Each GTLREF land must be connected 3 Rrr is the on die termination resistance measured at V7 3 of the GTL output driver 4 COMP resistance must be provided on the system board with 1 resistors COMP 3 0 and COMPS resistors are to Vss 30 Datasheet Electrical Specifications 2 8 2 8 1 Table 2 14 Datasheet Clock Specifications intel Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier will be set at its default ratio during manufacturing The processor supports Half Ratios between 7 5 and 13 5 see Table 2 14 for the processor supported ratios The processor uses a differential clocking implementation For more information on the processor clocking contact your Intel field representative Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency Core Frequency Core Frequency to FSB 333 MHz BCLK 400 MHz BCLK Notes 2 Frequency 1333 MHz
99. et m Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals DC electrical characteristics are provided 2 1 Power and Ground Lands The processor has VCC power VTT and VSS ground inputs for on chip power distribution All power lands must be connected to Vcc while all VSS lands must be connected to a system ground plane The processor VCC lands must be supplied the voltage determined by the Voltage IDentification VID lands ntel The signals denoted as VTT provide termination for the front side bus and power to the I O buffers A separate supply must be implemented for these lands that meets the V specifications outlined in Table 2 3 2 2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large current swings This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate Larger bulk storage Cgy x such as electrolytic or aluminum polymer capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition The motherboard must be designed to ensure that the voltage provided to the processor remains within the specif
100. gnals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processor samples a subset of the A 35 3 signals to determine power on configuration See Section 6 1 for more details A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 signals All bus agents observe the ADS activation to begin protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 Input Output Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 BCLK 1 0 Input The differential pair BCLK B
101. he processor is packaged in a Flip Chip Land Grid Array FC LGA6 package that interfaces with the motherboard via an LGA775 socket The package consists of a processor core mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket The package components shown in Figure 3 1 include the following e Integrated Heat Spreader IHS e Thermal Interface Material TIM e Processor core die e Package substrate e Capacitors Processor Package Assembly Sketch Core die TIM IHS Substrate on Capacitors LGA775 Socket 4 System Board i NOTE T Socket and motherboard are included for reference and are not part of processor package Package Mechanical Drawing The package mechanical drawings are shown in Figure 3 2 and Figure 3 3 The drawings include dimensions necessary to design a thermal solution for the processor These dimensions include e Package reference with tolerances total height length width etc e IHS parallelism and tilt e Land dimensions e Top side and back side component keep out dimensions e Reference datums e All drawing dimensions are in mm
102. her K8 vcc Power Other H24 VSS Power Other K23 VCC Power Other H25 VSS Power Other K24 VCC Power Other H26 VSS Power Other K25 YOE Power Other H27 VSS Power Other K26 VCC Power Other H28 VSS Power Other K27 VCC Power Other H29 FC15 Power Other K28 VCC Power Other H30 BSEL1 Asynch CMOS Output K29 VCC Power Other JA dx Power Other Output K30 VCC Power Other L1 LINT1 Asynch CMOS Input J2 FC3 Power Other L2 SLP Asynch CMOS Input J3 FC22 Power Other L3 VSS Power Other J4 VSS Power Other L4 A06 Source Synch Input Output J5 REQ1 Source Synch Input Output L5 A034 Source Synch Input Output J6 REQ4 Source Synch Input Output L6 VSS Power Other J7 VSS Power Other L7 VSS Power Other J8 VCC Power Other L8 VCC Power Other J9 VCC Power Other L23 VSS Power Other J10 VCC Power Other L24 VSS Power Other J11 VCC Power Other L25 VSS Power Other J12 VCC Power Other L26 VSS Power Other J13 VCC Power Other L27 VSS Power Other J14 VCC Power Other L28 VSS Power Other J15 VCC Power Other L29 VSS Power Other J16 FC31 Power Other L30 VSS Power Other J17 FC34 Power Other M1 VSS Power Other J18 vec Power Other M2 THERMTRIP Asynch CMOS Output J13 vee Power Other M3 STPCLK Asynch CMOS Input J20 vec Power Other M4 A073 Source Synch Input Output J21 vee Power Other M5 A05 Source Synch Input Output J22 vec Power Other M6 REQ2 Source Synch Input Output J23 VCC Power Other M7 VSS Power Other J24 VCC Power Other M8 VCC Power Other J25 VCC Power Other M
103. her W27 VCC Power Other V23 VSS Power Other W28 vcc Power Other V24 VSS Power Other W29 VCC Power Other V25 VSS Power Other w30 vcc Power Other V26 VSS Power Other Yi E MS Power Other V27 VSS Power Other V28 VSS Power Other Y2 VSS Power Other V29 VSS Power Other Y3 PSI Asynch CMOS Output V30 VSS Power Other Y4 A20 Source Synch Input Output Wi MSIDO Power Other Output Y5 VSS Power Other W2 TDI M Power Other Input Y6 A193 Source Synch Input Output W3 TESTHH Power Other Input d VSS Power Other WA VSS Power Other Y8 vcc Power Other W5 A16 Source Synch Input Output Yes vee Power Other W6 A18 Source Synch Input Output his vec Power Other W7 VSS Power Other Y25 VCC Power Other ws VCC Power Other Y26 vcc Power Other W23 VCC Power Other Y27 YGE Power Other W24 VCC Power Other Y28 VCC Power Other W25 VCC Power Other Y29 VET Power Other Y30 Vcc Power Other 63 intel Land Listing and Signal Descriptions 4 2 Alphabetical Signals Reference Table 4 3 Signal Description Sheet 1 of 10 Name Type Description A 35 3 amp Input Output A 35 3 Address define a 236 pyte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins lands of all agents on the processor FSB A 35 3 are source synchronous si
104. ications listed in Table 2 3 Failure to do so can result in timing violations or reduced lifetime of the component 2 2 1 Vcc Decoupling Vcc regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications This includes bulk capacitance with low effective series resistance ESR to keep the voltage rail within specifications during large swings in load current In addition ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity Consult the Voltage Regulator Down VRD 11 0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket 2 2 2 Vr Decoupling Decoupling must be provided on the motherboard Decoupling solutions must be sized to meet the expected load To ensure compliance with the specifications various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors Datasheet 15 m e n tel Electrical Specifications Note 16 FSB Decoupling The processor integrates signal termination on the die In addition some of the high frequency capacitance required for the FSB is included on the processor package However additional high frequency capacitan
105. iiia e ete a E E cadi e ERAT DM ERR NE tuat Aran AERE 16 2 3 Voltage Identification iecore Seen traxere iratum etras les esa ta waGeittns xp a Dau e nE MEE Erga aA 16 2 4 Reserved Unused and TESTHI Signals csse nemen ns 18 2 5 Power Segment Identifier PSID wcciiecscticnscssecsd nate rented teneen ben EXE IeR sa sumer PAR ES RPe Rr Ya 18 2 6 Voltage and Current Specification ccceec cece cece centre e eee eee eee aa a eens nene 19 2 6 1 Absolute Maximum and Minimum Ratings esses mme 19 2 6 2 DC Voltage and Current Specification ecsssssssessssseeeen nene 20 pace GEO Idol 25 2 6 4 Die Voltage Validation iieeceee cere enn nennt ern I rna mika de nae Ra n EI ERR 25 2 7 Signaling Specificatio MS isss uisi i ceiee veneta waned apre Dinan e eon DER Ke NDA XE EUR RR CRT DE DR 26 2 7 4 RSB Sigal Groups iscsi oer rst n a EE uu IRa DNE DURNEN DERE DI a APR MEN ne 26 2 7 2 CMOS and Open Drain Signals cccceceee cence eee eee eee teense nemen 28 2 7 3 Processor DC Specification cetur recie de soa E ERR ERI E SEXE SEE E 28 2 7 3 1 Platform Environment Control Interface PECI DC Specifications 29 2 7 3 2 GTL Front Side Bus Specifications esesseesseeenen 30 2 8 Clock SpecificatiOns sessionaris caaederpananncie esa reg eaa dx Xa sun E EREXRR E TENRUR E EEES 31 2 8 1 Front Side Bus Clock BCLK 1 0 and Processor Clocking 31 2
106. in e Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines 35 Figure 3 2 Processor Package Drawing Sheet 1 of 3 36 intel Package Mechanical Specifications ze eo lei wu Vv a o ea lt E s mh S 87 a S ER E t Sza E E ed EE H coz i e els px cog zi 3 sl 2 AN g sz E t i m al E 1 E E 0009 es g 0000000000000006000000000000000 B tE 0000000000000000 9909980990000906 Ee 5 00000000000000006000000000000000 Tu 2 4 000000000000000000000000000000006 B E 5 z nd OO00000000000000090000000000000000 _ wei 00000000000000000000000000000000 lt i OOOOOOOOOOOOOOOO000000000000000009 m 000000000 r 00000000 za 2 sz 000000000 00000000 Ez s s E 600000000 60000000 5 lS Sl l i 000000000 1 00000000 Essa Z Z O00000000 00000000 E
107. in some cases may result in a Tc that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor When Thermal Monitor 2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for Thermal Monitor 2 includes two operating points each consisting of a specific operating frequency and voltage The first operating point represents the normal operating con
108. inates and Quadrants Top View Veg Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 intel Figure 3 7 Address Common Clock Async Za4X21945Uu9099 3 z 225 razzocorouvuaoomc NN OO0000000000000000000000000 000 OOOOOO0000000000000000000000000000 44 OOOOOOOOOOOOOO000 OOOOOOOOOOOOOQ oOo00000000000000000000000000000090 200000000 000000 OOOOOC 2006 Seca 3600 z j C OOV ooo SN NO of JUN 000000 VY O V OOOOOO IOOO0O000 OOOO 5000000000006 200 00000 9000000 oo 000Q O OOOO O OOOO O o gt 0100101010101010 OO00000 ls B oO OO DOOOO000 OOOOO0O0000 e dU dm OOIOOOOOOO 000000000 O o gt OQOCOO0CO0O OOOOO0O0000 O co OOIOO00000 000000000 5 2 0 OODOOOO000 OO0000000 nar OQ0000000 000000000 OAOCOOCOO 000000000 YOCOOCO 000000000 O00000 000000000 00000 OOOOOO000000000000000000 O00000000000000000 0000000000000 oe 200000 00000 00000000000C 2 000000000 O00000000 00000000000 556 O e e O000000000000 66606 00000000000 C0000 50000000 OOO00000000000000060000000 OOOOOOOOOOO0O00000000000000 S 200 t ZZEa4X2I9uuQoo z225 wcoazzoxorouwwuwoomc Datasheet 1 Data 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 111009 8 7 6 54 3 2 V Clocks 42 m e Land Listing and Signal Descriptions n t el 4 Land Listing and Signal Descriptions This chapter provides the processor
109. ions Description Min Typ Max Unit Notes 12 V 12 volt fan power supply 11 4 12 12 6 V IC Maximum fan steady state current draw 1 2 A Average fan steady state current draw 0 5 A _ Maximum fan start up current draw 2 2 A Fan start up current draw maximum 1 0 Second duration pulses per SENSE SENSE frequency 2 fan 1 revolution CONTROL 21 25 28 kHz 2 3 NOTES 1 Baseboard should pull this pin up to 5 V with a resistor 2 Open drain type pulse width modulated 3 Fan will have pull up resistor for this signal to maximum of 5 25 V Figure 7 6 Baseboard Power Header Placement Relative to Processor Socket R110 4 33 Y C 98 Datasheet m Boxed Processor Specifications n t el 7 4 7 4 1 Figure 7 7 Figure 7 8 Datasheet Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink However meeting the processor s temperature specification is also a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is in Chapter 5 The boxed processor fan heatsink is able to keep the processor temperature within the specifications see Table 5 1 in
110. itoring sensor detects that one or both cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC if enabled for both cores The TCC will remain active until the system de asserts PROCHOT PROCHOT will not be asserted as an output or observed as an input when the processor is in the Stop Grant Sleep Deep Sleep and Deeper Sleep low power states hence the thermal solution must be designed to ensure the processor remains within specification If the processor enters one of the above low power states with PROCHOT already asserted PROCHOT will remain asserted until the processor exits the low power state and the processor DTS temperature drops below the thermal trip point PROCHOT allows for some protection of various components from over temperature situations The PROCHOT signal is bi directional in that it can either signal when the processor either core has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Bi directional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely on bi directional PROCHOT
111. ken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit 25 intel 2 7 1 Table 2 6 26 Electrical Specifications Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic GTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates Platforms implement a termination voltage level for GTL signals defined as V m Because platforms implement separate power planes for each processor and chipset separate Vcc and V supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families The GTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the motherboard see Table 2 13 for GTLREF specifications Termination resistors Rrr for GTL signals are provided on the processor silicon and are terminated to Vy Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the motherboard for most GTL signals FSB Signal Groups The front side bus signals have been combined into groups by buffer t
112. l Core 2 Quad processor Q8300 December 2008 E Added Intel Core 2 Quad processor Q9000S and Q8000S series Q9550S 007 Q9400S and Q8200S January 2003 008 Added Intel Core 2 Quad processors Q8400 and Q8400S April 2009 2 Corrected list of Intel VT supported processors Intel Core 2 Quad 003 processors Q8400 and Q8400S Mayo 010 Added Intel Core 2 Quad processors Q9505 and Q9505S August 2009 Datasheet Datasheet Intel Core 2 Extreme Processor QX9000 Series and Intel Core 2 Quad Processor Q9000 Q9000S Q8000 Q8000S Series Features e Available at 3 20 GHz and 3 00 GHz Intel e Binary compatible with applications running Core 2 Extreme processor QX9000 series on previous members of the Intel e Available at 3 0 GHz 2 83 GHz 2 66 GHz microprocessor line and 2 50 GHz Intel Core 2 Quad e Supports Execute Disable Bit capability Duro Q9505 Q9450 e Intel Wide Dynamic Execution e Available at 2 66 GHz 2 50 GHz and iei ie edes oh 2 33 GHz Intel Core 2 Quad processor Intel Smart Memory Access Q8400 Q8300 and Q8200 e Intel Intelligent Power Capability e Available at 2 83 GHz and 2 66 GHz Intel e Intel Advanced Digital Media Boost Core 2 Quad processor Q9550S Q9505S e Optimized for 32 bit applications running on and Q94005 a advanced 32 bit operating systems UL S a GHz and ee e Two 6 MB Level 2 caches Intel Core 2 ore 2 Quad processor Q an Extreme proc
113. l processor and chipset components It uses a single wire thus alleviating routing congestion issues PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices Also data transfer speeds across the PECI interface are negotiable within a wide range 2Kbps to 2Mbps The PECI interface on the processor is disabled by default and must be enabled through BIOS More information can be found in the Platform Environment Control Interface PECI Specification TcontroL and TCC activation on PECI Based Systems Fan speed control solutions based on PECI utilize a TcontroL Value stored in the processor IA32 TEMPERATURE TARGET MSR The TcowrRo MSR uses the same offset temperature format as PECI though it contains no sign bit Thermal management devices should infer the Tcontrot Value as negative Thermal management algorithms should utilize the relative temperature value delivered over PECI in conjunction with the TcowrRoL MSR value to control or optimize fan speeds Figure 5 7 shows a conceptual fan control diagram using PECI temperatures The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT assertions As the temperature approaches TCC activation the PECI value approaches zero TCC activates at a PECI count of zero Conceptual Fan Control Diagram on PECI Based Platforms TcowurRoL TCC Activation Setting
114. land assignment and signal descriptions 4 1 Processor Land Assignments This section contains the land listings for the processor The land out footprint is shown in Figure 4 1 and Figure 4 2 These figures represent the land out arranged by land number and they show the physical location of each signal on the package land array top view Table 4 1 is a listing of all processor lands ordered alphabetically by land signal name Table 4 2 is also a listing of all processor lands the ordering is by land number Datasheet 43 m l n t e Land Listing and Signal Descriptions Figure 4 1 land out Diagram Top View Left Side 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AK VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VCC VCC VCC VCC VCC VCC AB VSS VSS VSS VSS VS
115. more information including details on which processors support Intel 64 or consult with your system vendor for more information Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Intel virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security t Not all specified units of this processo
116. mum and maximum case temperature Tc specifications when operating at or below the Thermal Design Power TDP value listed per frequency in Table 5 1 Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design refer to the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 5 3 If the value reported via PECI is less than Tcowrao then the case temperature is permitted to exceed the Thermal Profile If the value reported via PECI is greater than or equal to Tcowrno then the processor case temperature must remain at or below the temperature as specified by the thermal profile The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 5 2 Systems that implement fan speed control must be designed to take these conditions in to account Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications
117. n a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Functional operation Refers to normal operating conditions in which all processor specifications including DC AC system bus signal quality mechanical and thermal are satisfied Execute Disable Bit Allows memory to be marked as executable or non executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system See the Intel Architecture Software Developer s Manual for more detailed information Intel 64 Architecture An enhancement to Intel s IA 32 architecture allowing the processor to execute operating systems and applications written to take advantage of Intel 64 architecture Further details on Intel 64 architecture and programming model can be found in the Software Developer Guide at http developer intel com technology 64bitextensions
118. near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to ensure proper operation once the processor reaches its normal operating frequency Refer to Figure 5 6 for an illustration of this ordering Datasheet e Thermal Specifications and Design Considerations n t el Figure 5 6 Thermal Monitor 2 Frequency and Voltage Ordering 5 2 3 Datasheet TM2 Temperature MAX m Frequency VID VID u2 PROCHOT The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode The Thermal Monitor TCC however can be activated through the use of the on demand mode On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor feature On Demand mode is intended as a means to reduce system level power consumption Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature
119. noop state The processor will stay in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB After the snoop is serviced the processor will return to the Stop Grant state or HALT powerdown state as appropriate Extended HALT Snoop State Extended Stop Grant Snoop State The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state or Extended Stop Grant state While in the Extended HALT Snoop State or Extended Stop Grant Snoop State snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State After the snoop is serviced the processor will return to the Extended HALT state or Extended Stop Grant state Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and stops all internal clocks The Sleep state is entered through assertion of the SLP signal while in the Extended Stop Grant or Stop Grant state The SLP pin should only be asserted when the processor is in the Extended Stop Grant or Stop Grant state SLP assertions while the processor is not in these states is out of specification and may result in unapproved operation In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the F
120. o Jo o Jo o Jo o o Ja la JH Ja Ja Ja a Il I fa a EN o o Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo lo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo Jo 17 Datasheet m n tel Electrical Specifications 2 5 18 Reserved Unused and TESTHI Signals All RESERVED lands must remain unconnected Connection of these lands to Vcc Vss Vr or to any other signal including each other can result in component malfunction or incompatibility with future processors See Chapter 4 for a land listing of the processor and the location of all RESERVED lands In a system level design on die termination has been included by the processor to allow signals to be terminated within the processor silicon Most unused GTL inputs should be left as no connects as GTL termination is provided on the processor silicon However see Table 2 6 for details on GTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 20 of the impedance of the motherboard trace for front sid
121. ollows e Deep Sleep entry the system clock chip may stop tristate BCLK within two BCLKs of DPSLP assertion It is permissible to leave BCLK running during Deep Sleep e Deep Sleep exit the system clock chip must drive BCLK to differential DC levels within 2 3 ns of DPSLP de assertion and start toggling BCLK within 10 BCLK periods To re enter the Sleep state the DPSLP pin must be deasserted BCLK can be restarted after DPSLP de assertion as described above A period of 15 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin must be deasserted to re enter the Stop Grant state While in the Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the processor is in the Deep Sleep state When the processor is in the Deep Sleep state it will not respond to interrupts or snoop transactions Any transition on an input signal before the processor has returned to the Stop Grant state will result in unpredictable behavior PECI is not available and will not respond while in the Deep Sleep State Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but the core voltage is reduced to a lower level The Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep state Exit from D
122. olution is connected to an older 3 pin baseboard processor fan header it will default back to a thermistor controlled mode allowing compatibility with existing 3 pin baseboard designs Under thermistor controlled mode the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet For more details on specific motherboard requirements for 4 wire based fan speed control see the appropriate Thermal and Mechanical Design Guidelines See Section 1 2 Boxed Intel Core 2 Extreme Processor QX9650 Specifications This section documents the mechanical specifications of the Boxed Intel Core 2 Extreme processor QX9650 The boxed processor will be shipped with an unattached fan heatsink Figure 7 10 shows a mechanical representation of the boxed processor Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 7 3 top view and Figure 7 4 side view The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs Airspace requirements are shown in Figure 7 11 and Figure 7 12 Note that some figures have centerlines shown marked with alphabetic designations to clarify relative dimensioning The Boxed Intel Core 2 Extreme processor QX9650 cooling solution violates the
123. onal operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes 2 Wee Core voltage with respect to 0 3 1 45 V E Vss Vr FSB termination voltage with 0 3 1 45 V E respect to Vss T Processor case temperature See Section 5 see eC CASE P Section 5 Processor storage E o TsroRAGE temperature 40 85 c 3 4 5 NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation refer to the processor case temperature specifications 4 This rating applies to the processor and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor 19 Electrical Specifications intel
124. only operate at their specified FSB frequency For more information about these signals refer to Section 4 2 Table 2 15 BSEL 2 0 Frequency Table for BCLK 1 0 BSEL2 BSEL1 BSELO FSB Frequency L L L RESERVED L L H RESERVED L H H RESERVED L H L RESERVED H H L 400 MHz H H H RESERVED H L H RESERVED H L L 333 MHz 2 8 3 Phase Lock Loop PLL and Filter An on die PLL filter solution will be implemented on the processor The VCCPLL input is used for the PLL Refer to Table 2 3 for DC specifications 2 8 4 BCLK 1 0 Specifications Table 2 16 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes VL Input Low Voltage 0 30 N A N A V 2 3 3 Vu Input High Voltage N A N A 1 15 V 223 3 VcRoss abs Absolute Crossing Point 0 300 N A 0 550 V 253 2 AVcnoss Range of Crossing Points N A N A 0 140 V 2 3 Vos Overshoot N A N A 1 4 V 2 3 4 Vus Undershoot 0 300 N A N A V 2 3 4 Vswinc Differential Output Swing 0 300 N A N A V 2 4 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLKO equals the falling edge of BCLK1 3 Steady state voltage not including overshoot or undershoot 4 Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage 5 Measurement taken from differential waveform
125. ontroller should take action to protect the system from possible damage It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive GetTemp s or for a one second time interval The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO Error Code Support The error codes supported for the processor GetTemp command are listed in Table 5 6 GetTempO Error Codes Error Code Description 8000h General sensor error Sensor is operational but has detected a temperature below its operational 8002h range underflow Datasheet Features 6 6 1 Table 6 1 6 2 Datasheet intel Features Power On Configuration Options Several configuration options can be configured by hardware The processor samples the hardware configuration at reset on the active to inactive transition of RESET For specifications on these options refer to Table 6 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for configuration purposes the processor does not distinguish between a warm reset and a power on reset Power On Configuration Option Signals
126. ource Synch Input Output BRO F3 Common Clock Input Output A93 T5 Source Synch Input Output BSELO G29 Asynch CMOS Output A105 U6 Source Synch Input Output BSEL1 H30 Asynch CMOS Output All T4 Source Synch Input Output BSEL2 G30 Asynch CMOS Output A125 U5 Source Synch Input Output COMPO A13 Power Other Input A135 U4 Source Synch Input Output COMP1 Ti Power Other Input A143 V5 Source Synch Input Output COMP2 G2 Power Other Input A155 V4 Source Synch Input Output COMP3 R1 Power Other Input A163 W5 Source Synch Input Output COMP8 B13 Power Other Input A173 AB6 Source Synch Input Output DO B4 Source Synch Input Output A18 W6 Source Synch Input Output Di C5 Source Synch Input Output A195 Y6 Source Synch Input Output D2 A4 Source Synch Input Output A20 Y4 Source Synch Input Output D3 C6 Source Synch Input Output A21 AA4 Source Synch Input Output D4 A5 Source Synch Input Output A223 AD6 Source Synch Input Output D5 B6 Source Synch Input Output A23 AA5 Source Synch Input Output D6 B7 Source Synch Input Output A24 AB5 Source Synch Input Output D7 A7 Source Synch Input Output A25 AC5 Source Synch Input Output D8 A10 Source Synch Input Output A263 AB4 Source Synch Input Output D9 A11 Source Synch Input Output A273 AF5 Source Synch Input Output D10 B10 Source Synch Input Output A28 AF4 Source Synch Input Output D11 Cii Source Synch Input Output A29 AG6 Source Synch Input
127. owerful processors for desktop PCs The processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance These applications include Internet audio and streaming video image processing video content creation speech 3D CAD games multimedia and multitasking user environments Intel 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture The processor supporting Enhanced Intel Speedstep technology allows tradeoffs to be made between performance and power consumption The Intel Core 2 Extreme processor QX9000 series Intel Core 2 Quad processor Q9000 Q9000S Q8000 and Q8000S series also includes the Execute Disable Bit capability This feature combined with a supported operating system allows memory to be marked as executable or non executable Datasheet 9 intel The Intel Core 2 Extreme processor QX9000 series Intel Core 2 Quad processor Q9000 and Q9000S series and Intel Core 2 Quad processors Q8400 and Q8400S support Intel Virtualization Technology Virtualization Technology provides silicon based functionality that works together with compatible Virtual Machine Monitor VMM software to improve on software only solutions The Intel Core 2 Quad processor Q9000 and Q9000S series support Intel Trusted Execution Technology Intel TXT Intel T
128. performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides 105 n t el Debug Tools Specifications 106 Datasheet
129. pirical data These specifications will be updated with characterized data from silicon measurements at a later date These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 3 and Table 2 1 for more information The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe 21 22 BUD 10 Electrical Specifications capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe Refer to Table 2 4 and Figure 2 1 for the minimum typical and maximum Vec allowed for a given current The processor should not be subjected to any Vcc and Icc combination wherein Vec exceeds Vec max for a given current Icc max Specification is based on Vcc max loadline Refer to Figure 2 1 for details V must be provided via a separate voltage source and not be connected to Vcc This specification is measured at the land Baseboard bandwidth is limited to 20 MHz This is the maximum total current drawn from the V plane by only the processor This specification does not include the current coming from on board termination Rrr through the signal line Refer to the Voltage Regulator Design Guide to determine the total Irr drawn by the s
130. processor during a power management event Thermal Monitor 2 Enhanced Intel SpeedStep technology or Extended HALT State The processor uses eight voltage identification signals VID 7 0 to support automatic selection of power supply voltages Table 2 1 specifies the voltage level corresponding to the state of VID 7 0 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the processor socket is empty VID 7 0 11111110 or the voltage regulation circuit cannot supply the voltage that is requested it must disable itself The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 3 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 4 and Figure 2 1as measured across the VCC SENSE and VSS SENSE lands The VRM or VRD used must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are included in Table 2 3 and Table 2 4 Refer to the Voltage Regulator Design Guide for further details Datasheet intel Electrical Specifications
131. put AN20 VSS Power Other AM6 FC40 Power Other AN21 VCC Power Other AM7 VID7 Asynch CMOS Output AN22 VCC Power Other AM8 VCC Power Other AN23 VSS Power Other AM9 VCC Power Other AN24 VSS Power Other AM10 VSS Power Other AN25 VCC Power Other AM11 VCC Power Other AN26 VCC Power Other AM12 VCC Power Other AN27 VSS Power Other AM13 VSS Power Other AN28 VSS Power Other AM14 VCC Power Other AN29 VCC Power Other AM15 VCC Power Other AN30 VCC Power Other AM16 VSS Power Other A2 VSS Power Other AM17 VSS Power Other A3 RS2 Common Clock Input AM18 VCC Power Other A4 DO2 Source Synch Input Output AM19 VCC Power Other A5 DO4 Source Synch Input Output AM20 VSS Power Other A6 VSS Power Other AM21 VCC Power Other A7 DO7 Source Synch Input Output AM22 VCC Power Other A8 DBIO Source Synch Input Output AM23 VSS Power Other A9 VSS Power Other AM24 VSS Power Other A10 DO8 Source Synch Input Output AM25 VCC Power Other A11 DO9 Source Synch Input Output AM26 VCC Power Other A12 VSS Power Other AM27 VSS Power Other A13 COMPO Power Other Input AM28 VSS Power Other A14 D50 Source Synch Input Output AM29 VCC Power Other A15 VSS Power Other AM30 VCC Power Other A16 DSTBN3 Source Synch Input Output AN1 VSS Power Other A17 D56 Source Synch Input Output AN2 VSS Power Other A18 VSS Power Other AN3 VCC SENSE Power Other Output A19 D61 Source Synch Input Output AN4 VSS_SENSE Power Other Output A20 RESERVED AN5 eee Power Other Output A21 VSS
132. r support Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Not all specified units of this processor support Thermal Monitor 2 Enhanced HALT State and Enhanced Intel SpeedStep Technology See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Intel Pentium Intel Core Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2007 2009 Intel Corporation All Rights Reserved 2 Datasheet Contents 1 geenrsImEexece PL 11 LA TEMINY e Tc 12 1 1 1 Processor Terminology Definitions esses mme 12 1 2 References ee ectesexiisa sd a phctianaicl e Festus Aa c Nx RATER CURE ed GU RID MC at 14 2 Electrical Specifications ssssssssssssssseseeseensene mese enemies 15 2 Power and Ground Eands rore ara basse ed aide E ARMES DC ERE FROM EE 15 2 2 Decoupling Guidelines eid isimna aa aa a EM Sb de UM ED 15 2 2 4 VCC Decoulbplitng cuerno mete pedss ku dnd ade xao exi Rr CE Rie dice UR NR o eite 15 2 2 2 Vtt Decouplitig 5 rti e ied kei PraxRac bate NE Oa T Ka RUE E nE dar OMEN 15 2 2 3 FSB Decoupling
133. rameter Min Max Unit Notes VoL Output Low Voltage 0 0 20 V Ig Output Low Current 16 50 mA 2 ILo Output Leakage Current N A 200 HA 3 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at Vr 0 2V 3 For Vin between 0 and Voy Datasheet Electrical Specifications Table 2 11 CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vi Input Low Voltage 0 10 Vr 0 30 V 3 6 Vin Input High Voltage Vr 0 70 Vr 0 10 V 4 5 6 VoL Output Low Voltage 0 10 Vr 0 10 V 6 Vou Output High Voltage 0 90 V Vr 0 10 V 2 5 6 Io Output Low Current Voz 0 10 67 Vj 0 10 27 A 6 7 Ion Output Low Current Vr 0 10 67 Vr 0 10 27 A 6 7 Ij Input Leakage Current N A 100 HA 8 ILo Output Leakage Current N A 100 HA 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 All outputs are open drain 3 Vi is defined as the voltage range at a receiving agent that will be interpreted as a logical low value 4 Vip is defined as the voltage range at a receiving agent that will be interpreted as a logical high value 5 Vin and Voy may experience excursions above VT 6 The V referred to in these specifications refers to instantaneous Vr 7 Ig is measured at 0 10 V Igy is measured at 0 90 V 8 Leakage to Vss with land held at V
134. rement situations The PSID mechanism enables BIOS to detect if the processor in use requires more power than the platform voltage regulator VR is capable of supplying For example a 130 W TDP processor installed in a board with a 65 W or 95 W TDP capable VR may draw too much power and cause a potential VR issue Datasheet Electrical Specifications n t e I 2 6 2 6 1 Table 2 2 Datasheet Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 2 2 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor Within functional operation limits functionality and long term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functi
135. result in component malfunction or incompatibility with future processors RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins lands of all processor FSB agents SKTOCC 70 Output SKTOCC Socket Occupied will be pulled to ground by the processor System board designers may use this signal to determine if the processor is present Datasheet Land Listing and Signal Descriptions intel Table 4 3 Signal Description Sheet 8 of 10 Name SLP SMI Type Input Input Description SLP Sleep when asserted in Extended Stop Grant or Stop Grant state causes the processor to enter the Sleep state In the Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Extended Stop Grant or Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state Use of the SLP pin and correspon
136. rmal Specifications cccccceceeeseeseteeneseeesneeceseeeeesaeeetesneneeeseeaeenensense 76 5 2 Intel Core 2 Extreme Processor QX9770 Thermal Profile ccs 78 5 3 Intel Core 2 Extreme Processor QX9650 Thermal Profile cese 79 5 4 Intel Core 2 Quad Processor Q9000 and Q8000 Series Thermal Profile 80 5 5 Intel Core 2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 5 6 GetTrempO Error Codes race c rrr naan ape en xanax rt ase naa Ry aas Rl AE IMRIAR PIX REG RFPET REP anaes 87 6 1 Power On Configuration Option Signals c ccceeee eee e eee e eee eee eee enne 89 7 1 Fan Heatsink Power and Signal SpecificationS ccceeceeee este eee e tees eee e este nnne 98 7 2 Fan Heatsink Power and Signal Specifications esses 100 6 Datasheet Revision History intel Revision Description Revision Date Number 001 Initial release November 2007 002 Added Intel Core 2 Quad processors Q9550 Q9450 and Q9300 January 2008 Added 1600 MHz FSB March 2 003 Added Intel Core 2 Extreme processor QX9770 aren 2099 Added Intel Core 2 Quad processors Q9650 and Q9400 Added PSI signal 004 A t 2 ee Updated Sections 6 2 3 6 2 4 6 2 5 6 2 6 6 2 7 and 6 3 Hgust 2008 Updated FSB termination voltage in Table 2 3 005 Added Intel Core 2 Quad processor Q8200 August 2008 006 Added Inte
137. rmal to the processor IHS 2 This is the maximum force that can be applied by a heatsink retention clip The clip must also provide the minimum specified load on the processor package 3 These specifications are based on limited testing for design characterization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement Package Handling Guidelines Table 3 2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 Ibf 1 4 Tensile 111 N 25 Ibf 2 4 Torque 3 95 N m 35 Ibf in 3 4 NOTES 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization 39 m e n tel Package Mechanical Specifications 3 5 3 6 3 7 Table 3 3 3 8 Figure 3 5 40 Package Insertion Specifi
138. s Manual and the Intel Processor Identification and the CPUID Instruction application note GTLREF 3 0 determine the signal reference level for GTL input signals GTLREF is used by the GTL receivers to determine if a signal is a logical O or logical 1 HIT HITM Input Output Input Output HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Output IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination Refer to Section 2 6 2 for termination requirements IGNNE Input IGNNE Ignore Numeric Error is asserted to the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is de asserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchrono
139. sor Q9000 Q9000S Q8000 and Q80008 series e Enhanced Intel Core microarchitecture A new foundation for Intel architecture based desktop mobile and mainstream server multi core processors For additional information refer to http www intel com technology architecture coremicro e Keep out zone The area on or near the processor that system design can not utilize e Processor core Processor die with integrated L2 cache e LGA775 socket The processor mates with the system board through a surface mount 775 land LGA socket e Integrated heat spreader IHS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface e Retention mechanism RM Since the LGA775 socket does not include any mechanical features for heatsink attach a retention mechanism is required Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket e FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All Datasheet Introduction Datasheet intel memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Storage conditions Refers to a non operational state The processor may be installed in a platform i
140. sors have CPUID 1067Ah 7 These processors have CPUID 10677h 8 These processors have CPUID 10676h 76 Datasheet Thermal Specifications and Design Considerations Table 5 2 Figure 5 1 Intel Core 2 Extreme Processor QX9770 Thermal Profile Intel Core 2 Extreme Processor QX9770 Thermal Profile intel Power Maximum Power Maximum Power Maximum Power Maximum W Tc C W Tc C W Te C W Te C 0 37 8 34 42 2 68 46 6 102 51 1 2 38 1 36 42 5 70 46 9 104 51 3 4 38 3 38 42 7 72 47 2 106 51 6 6 38 6 40 43 0 74 47 4 108 51 8 8 38 8 42 43 3 76 47 7 110 52 1 10 39 1 44 43 5 78 47 9 112 52 4 12 39 4 46 43 8 80 48 2 114 52 6 14 39 6 48 44 0 82 48 5 116 52 9 16 39 9 50 44 3 84 48 7 118 53 1 18 40 1 52 44 6 86 49 0 120 53 4 20 40 4 54 44 8 88 49 2 122 53 7 22 40 7 56 45 1 90 49 5 124 53 9 24 40 9 58 45 3 92 49 8 126 54 2 26 41 2 60 45 6 94 50 0 128 54 4 28 41 4 62 45 9 96 50 3 130 54 7 30 41 7 64 46 1 98 50 5 132 55 0 32 42 0 66 46 4 100 50 8 134 55 2 136 55 5 55 53 51 49 A N y 0 13x 37 8 Tcase C A a 43 41 39 37 Datasheet 20 30 40 50 60 70 Power W 80 90 100 110 120 130 77 im e n tel Thermal Specifications and Design Considerations Table 5 3 Intel Core 2 Extreme
141. ssssssssssssssenemeenememen enemies 105 8 1 Logic Analyzer Interface LAL d ueeser esset erit ae Lun iRekieba tenor aaa etaataaad ayers 105 8 1 1 Mechanical Considerations ssssssssssssseeene emm 105 8 1 2 Electrical Considerations ecrit nonne ken sena edendum ma naa aa RA aA 105 Datasheet Figures WYN YN NNN NNN NOAAAAAAARRWWWWWWWNNNNDY eee DOONAU A UNeeN OAAR UN eN eN OAAR UN e AUNE NFO Datasheet Veg Static and Transient Tolerance einen reina enn n e TERRI REA EXER ERE UE EE OE LEE TEE 24 Vcc Overshoot Example Waveform esee treten an seni nasa ru oa Sa RI Rd Ra 25 Differential Clock Waveform ssssssssssssesseeeee nennen nennen nnne 34 Measurement Points for Differential Clock Waveforms ccceceeeeee eect etna teats mne 34 Processor Package Assembly Sketch ssssssssssssssssssseeeeenenemen nemen 35 Processor Package Drawing Sheet 1 of 3 cececececeeee cece eee eee eee e eet nates eae nnn 36 Processor Package Drawing Sheet 2 Of 3 cceceeeeeeeeeee eect eens ee ee eens ee menm 37 Processor Package Drawing Sheet 3 of 3 cceceececeeeee eee estes eee eens eee nt eats ease ten eaees 38 Processor Top Side Markings Example Intel Core 2 Extreme Processor QX9650 40 Processor Top Side Markings Example Intel Core 2 Quad Processor Q9000 Series 41 Processor Land Coordinates and Quadrants Top View eese nnne 42 land out Diagram Top Vie
142. t speeds Recommended maximum internal chassis temperature for worst case operating environment 7 gt 39 When the internal chassis temperature is above or equal to this 9 set point the fan operates at its highest speed NOTES 1 Set point variance is approximately 1 C from fan heatsink to fan heatsink Datasheet Boxed Processor Specifications n t e I 7 5 Note Datasheet If the boxed processor fan heatsink 4 pin connector is connected to a 4 pin motherboard header and the motherboard is designed with a fan speed controller with PWM output CONTROL see Table 7 1 and remote thermal diode measurement capability the boxed processor will operate as follows As processor power has increased the required thermal solutions have generated increasingly more noise Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage The 4th wire PWM solution provides better control over chassis acoustics This is achieved by more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors DTS and PECI Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures If the new 4 pin active fan heat sink s
143. ted and is disabled on de assertion of PWRGOOD if V or Vcc are not valid THERMTRIP may also be disabled Once activated THERMTRIP remains latched until PWRGOOD V or Vcc is de asserted While the de assertion of the PWRGOOD V or Vec signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD provided V and Vcc are valid THERMTRIP Output TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Target Ready is asserted by the target to indicate that it TRDY Input is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins lands of all FSB agents TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset TMS Input TRST Input VCC are the power pins for the processor The voltage supplied to vee Input these pins is determined by the VID 7 0 pins VCCA provides isolated power for internal PLLs on previous VCCA Input generation processors It may be left as a No Connect on boards supporting the processor VCCIOPLL provides isolated power for internal processor FSB PLLs VCCIOPLL Input on previous generation processors It may be left as a No Connect on boards supporting the processor VCCPLL Input VCCPLL provides isolated power for int
144. termination requirements BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB It must connect the appropriate pins lands of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by de asserting BPRI BRO Input Output BRO drives the BREQO signal in the system and is used by the processor to request the bus During power on configuration this signal is sampled to determine the agent ID 0 This signal does not have on die termination and must be terminated BSEL 2 0 Output The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2 15 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency For more information about these signals including termination recommendations refer to Section 2 8 2 COMP 3 0 COMP8 Analog COMP 3 0 and COMP8 must be terminated to Vss on the system board using precision resistors 65 intel Land Listing and Signal Descriptions Table
145. the original value Stop Grant and Extended Stop Grant States The processor supports the Stop Grant and Extended Stop Grant states The Extended Stop Grant state is a feature that must be configured and enabled using BIOS Refer to the sections below for details about the Stop Grant and Extended Stop Grant states Stop Grant State When the STPCLK signal is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Since the GTL signals receive power from the FSB these signals should not be driven allowing the level to return to V4 for minimum power drawn by the termination resistors in this state In addition all other input signals on the FSB should be driven to the inactive state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB see Section 6 2 4 While in the Stop Grant State SMI INIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal State Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process a FSB snoop 91 i n tel F
146. ther D49 D17 Source Synch Input Output FC26 E29 Power Other D50 A14 Source Synch Input Output FC29 u2 Power Other D51 C15 Source Synch Input Output FC30 U3 Power Other D52 C14 Source Synch Input Output Fe J16 Power Other D53 B15 Source Synch Input Output sus H15 Power Other D54 C18 Source Synch Input Output FC33 H16 Power Other D55 B16 Source Synch Input Output FC34 J17 Power Dther D56 A17 Source Synch Input Output FC35 id Power Other D57 B18 Source Synch Input Output FC36 AD3 Power Other D58 C21 Source Synch Input Output FC37 AB3 Power Other D59 B21 Source Synch Input Output FC39 ANS Power Other D60 B19 Source Synch Input Output FC40 AM6 Power Other D61 A19 Source Synch Input Output FERRA DEE n3 Asynch CMOS Output D62 A22 Source Synch Input Output one Hl Power Other Input D63 B22 Source Synch Input Output GTEREFI H2 Power Other Input DBIO A8 Source Synch Input Output oper F2 Power Other Input DBI1 G11 Source Synch Input Output GILREF3 SM Power other Input DBI2 D19 Source Synch Input Output nate D4 Common lee Input Output DBI3 C20 Source Synch Input Output HITM E4 Common Clock Input Output DBR AC2 Power Other Output IERR AB2 Asynch CMOS Output DBSY B2 Common Clock Input Output IGNNET N2 Asynch CMOS Input DEFER G7 Common Clock Input INIT P3 Asynch CMOS Input DPRSTP T2 AsynchCMOS Input RS TAP Input DPSLP P1 Asynch CMOS Input MEZCIKI ANS lid Input DR
147. ther RESERVED D1 VCC AC29 Power Other RESERVED D14 VCC AC30 Power Other RESERVED D16 VCC AC8 Power Other RESERVED E23 YCC AD23 Power Other RESERVED E6 VCC AD24 Power Other RESERVED E7 VCC AD25 Power Other RESERVED F23 VCC AD26 Power Other RESERVED F29 VCC AD27 Power Other RESERVED G6 VCC AD28 Power Other RESERVED N4 Vcc AD29 Power Other RESERVED N5 VCC AD30 Power Other RESERVED P5 VCC AD8 Power Other RESET G23 Common Clock Input VCC AE11 Power Other RSO B3 Common Clock Input Vcc AE12 Power Other RS1 F5 Common Clock Input VCC AE14 Power Other RS2 A3 Common Clock Input YCC AE15 Power Other SKTOCC AE8 Power Other Output VCC AE18 Power Other SLP L2 Asynch CMOS Input VCC AE19 Power Other SMI P2 Asynch CMOS Input VCC AE21 Power Other STPCLK M3 Asynch CMOS Input VCC AE22 Power Other TCK AE1 TAP Input VCC AE23 Power Other TDI AD1 TAP Input Vcc AE9 Power Other TDI M w2 Power Other Input Vcc AF11 Power Other TDO AF1 TAP Output Vcc AF12 Power Other TDO M U1 TAP Output VCC AF14 Power Other TESTHIO F26 Power Other Input Vcc AF15 Power Other TESTHI1 w3 Power Other Input VCC AF18 Power Other TESTHI10 H5 Power Other Input YCC AF19 Power Other TESTHI2 F25 Power Other Input VCC AF21 Power Other TESTHI3 G25 Power Other Input VCC AF22 Power Other TESTHI4 G27 Power Other Input VCC AF8 Power Other Datasheet Land Listing and Signal Descriptions intel
148. ther VSS F7 Power Other VSS P25 Power Other VSS H10 Power Other VSS P26 Power Other VSS H11 Power Other VSS P27 Power Other VSS H12 Power Other VSS P28 Power Other VSS H13 Power Other VSS P29 Power Other VSS H14 Power Other VSS P30 Power Other VSS H17 Power Other VSS P4 Power Other VSS H18 Power Other VSS P7 Power Other VSS H19 Power Other VSS R2 Power Other VSS H20 Power Other VSS R23 Power Other VSS H21 Power Other VSS R24 Power Other VSS H22 Power Other VSS R25 Power Other VSS H23 Power Other VSS R26 Power Other VSS H24 Power Other VSS R27 Power Other VSS H25 Power Other VSS R28 Power Other VSS H26 Power Other VSS R29 Power Other VSS H27 Power Other VSS R30 Power Other VSS H28 Power Other VSS R5 Power Other VSS H3 Power Other VSS R7 Power Other VSS H6 Power Other VSS T3 Power Other VSS H7 Power Other VSS T6 Power Other VSS H8 Power Other VSS T7 Power Other VSS H9 Power Other VSS U7 Power Other VSS J4 Power Other VSS V23 Power Other VSS J7 Power Other VSS V24 Power Other VSS K2 Power Other VSS V25 Power Other VSS K5 Power Other VSS V26 Power Other VSS K7 Power Other VSS V27 Power Other Datasheet 53 54 intel Land Listing and Signal Descriptions Table 4 1 Alphabetical Land Table 4 1 Alphabetical Land Assignments Assignments Land Name Land Ba og Direction Land Name Land d s Direction VSS V28 Power Other
149. upt requests are latched and serviced during the time that the clocks are on while the TCC is active When the Thermal Monitor feature is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Clocks often will not be off for more than 3 0 microseconds when the TCC is active Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief 81 m e n tel Thermal Specifications and Design Considerations 5 2 2 82 periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and
150. urce Synch Input Output G7 DEFER Common Clock Input E19 D40 Source Synch Input Output G8 BPRI Common Clock Input E20 VSS Power Other G9 D16 Source Synch Input Output E21 D42 Source Synch Input Output G10 GTLREF3 Power Other Input E22 D45 Source Synch Input Output Gil DBI1 Source Synch Input Output E23 RESERVED G12 DSTBN1 Source Synch Input Output E24 FC10 Power Other G13 D27 Source Synch Input Output E25 VSS Power Other G14 D29 Source Synch Input Output E26 VSS Power Other Gi5 D31 Source Synch Input Output E27 VSS Power Other G16 D32 Source Synch Input Output E28 VSS Power Other G17 D36 Source Synch Input Output E29 FC26 Power Other G18 D35 Source Synch Input Output F2 GTLREF2 Power Other Input G19 DSTBP2 Source Synch Input Output F3 BRO Common Clock Input Output G20 DSTBN2 Source Synch Input Output F4 VSS Power Other G21 D44 Source Synch Input Output F5 RS1 Common Clock Input G22 D47 Source Synch Input Output F6 FC21 Power Other G23 RESET Common Clock Input F7 VSS Power Other G24 TESTHI6 Power Other Input F8 D17 Source Synch Input Output G25 TESTHI3 Power Other Input F9 D18 Source Synch Input Output G26 TESTHIS Power Other Input F10 VSS Power Other G27 TESTHI4 Power Other Input F11 D23 Source Synch Input Output G28 BCLK1 Clock Input F12 D24 Source Synch Input Output G29 BSELO Asynch CMOS Output F13 VSS Power Other G30 BSEL2 Asynch CMOS Output F14 D28 Source Synch Input Output H1
151. us Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions 64 Datasheet Land Listing and Signal Descriptions Table 4 3 Datasheet intel Signal Description Sheet 2 of 10 Name BPM 5 0 BPMb 3 0 Type Input Output Description BPM 5 0 and BPMb 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 and BPMb 3 0 should connect the appropriate pins lands of all processor FSB agents BPM 3 0 are associated with core 0 BPMb 3 0 are associated with core 1 BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processor These signals do not have on die termination Refer to Section 2 6 2 for
152. us signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT 68 Input INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins lands of all processor FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST Datasheet Land Listing and Signal Descriptions intel Table 4 3 Signal Description Sheet 6 of 10 Name ITP_CLK 1 0 Type Input Description ITP_CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board ITP_CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system ITP_CLK 1 0 are no connects in the system These are not processor signals LINT 1 0 LOCK Input Input Output LINT 1 0 Local APIC Interrupt must connect the appropriate pins lands of all APIC Bus
153. ust be deasserted Use of the DPRSTP pin and corresponding low power state requires chipset support and may not be available on all platforms NOTE Some processors may not have the Deeper Sleep State enabled refer to the Specification Update for specific sku and stepping guidance DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state To return to the Sleep State DPSLP must be deasserted Use of the DPSLP pin and corresponding low power state requires chipset support and may not be available on all platforms NOTE Some processors may not have the Deep Sleep State enabled refer to the Specification Update for specific sku and stepping guidance DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be de asserted to insert idle clocks This signal must connect the appropriate pins lands of all processor FSB agents DSTBN 3 0 Input Output DSTBN 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI24 DSTBN2 D 63 48 DBI3 DSTBN3 DSTBP 3 0 Input Output DSTBP 3 0 are the data strobes used to latch in D 63 0 Signals Associated Strobe D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI24 D
154. w Left Side cceceeeee cette eee eee eee ee ee nmm nnen 44 land out Diagram Top View Right Side cceeeeeee eee e ee eee eee ee ee ee eee eee tees nena eae 45 Intel Core 2 Extreme Processor QX9770 Thermal Profile cccccceceeeeeeeeeaeeeeeeaees 78 Intel Core 2 Extreme Processor QX9650 Thermal Profile ccccceceeeeeeseeeeeeeeeaees 79 Intel Core 2 Quad Processor Q9000 and Q8000 Series Thermal Profile 80 Intel Core 2 Quad Processor Q9000S and Q8000S Series Thermal Profile 81 Case Temperature TC Measurement Location cee eee ee ee eee eterna nennen 82 Thermal Monitor 2 Frequency and Voltage Ordering ccccceeeeeeeee eens estate eee ee eeeeeeeeaes 84 Conceptual Fan Control Diagram on PECI Based Platforms eee 86 Processor Low Power State Machine csessssesseseeeeee nennen nennen nennen nnn nnn 90 Mechanical Representation of the Boxed Processor cesssssseseeeee nennen 95 Space Requirements for the Boxed Processor side view seen 96 Space Requirements for the Boxed Processor top view ssssssssssssssrssrrerrrerrnrrrnsrneres 96 Space Requirements for the Boxed Processor overall view sssssssssssrrerrrssrersresrrerens 97 Boxed Processor Fan Heatsink Power Cable Connector Description ssseses 98 Baseboard Power Header Placement Relative to Processor Socket
155. ype GTL input signals have differential input buffers which use GTLREF 3 0 as a reference level In this document the term GTL Input refers to the GTL input group as well as the GTL I O group when receiving Similarly GTL Output refers to the GTL output group as well as the GTL I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals which are dependent upon the rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 2 6 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Sheet 1 of 2 Signal Group Type Signals GTL Common Synchronous to Clock Input BCLK 1 0 BPRI DEFER RESET RS 2 0 TRDY GTL Common Synchronous to ADS BNR BPM 5 0 BPMb 3 0 BRO S DBSY Clock I O BCLK 1 0 DRDY HIT HITM LOCK GTL Source Synchronous I O Synchronous to assoc strobe Signals Associated Strobe REQ 4 0 A 16 3 2 ADSTBO A 35 17 2 ADSTB1 D 15 0 DBIO D 31 16 DBI1 D 47 32 DBI2 D 63 48 DBI3 DSTBPO DSTBNO DSTB
156. ystem This parameter is based on design characterization and is not tested Adherence to the voltage specifications for the processor are required to ensure reliable processor operation Datasheet Electrical Specifications intel Table 2 4 Vcc Static and Transient Tolerance Voltage Deviation from VID Setting V 2 3 4 Icc A Maximum Voltage Typical Voltage Minimum Voltage 1 30 mo 1 38 mo 1 45 mo 0 0 000 0 019 0 038 5 0 007 0 026 0 045 10 0 013 0 033 0 053 15 0 020 0 040 0 060 20 0 026 0 047 0 067 25 0 033 0 053 0 074 30 0 039 0 060 0 082 35 0 046 0 067 0 089 40 0 052 0 074 0 096 45 0 059 0 081 0 103 50 0 065 0 088 0 111 55 0 072 0 095 0 118 60 0 078 0 102 0 125 65 0 085 0 108 0 132 70 0 091 0 115 0 140 75 0 098 0 122 0 147 80 0 101 0 126 0 151 85 0 111 0 136 0 161 90 0 117 0 143 0 169 95 0 124 0 150 0 176 100 0 130 0 157 0 183 105 0 137 0 163 0 190 110 0 143 0 170 0 198 115 0 150 0 177 0 205 120 0 156 0 184 0 212 125 0 163 0 191 0 219 NOTES 1 The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2 6 3 2 This table is intended to aid in reading discrete points on Figure 2 1 3 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage r

Intel Core Core™2 Quad Processor Q9400 (6M Cache, 2.66 GHz, 1333 MHz FSB)

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Intel Core Core&trade;2 Quad Processor Q9400 (6M Cache, 2.66 GHz, 1333 MHz FSB)

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Intel Core Core™2 Quad Processor Q9400 (6M Cache, 2.66 GHz, 1333 MHz FSB)