Kingston Technology ValueRAM 2GB 800MHz DDR2 ECC Fully Buffered CL5 DIMM Dual Rank, x8
Contents
1. 124 Vss 34 PN4 154 SN4 64 PN10 184 SN10 94 PS5 214 SS5 5 Voo 125 Vpp 35 PN4 155 SN4 65 Vss 185 Vss 95 Vss 215 Vss 6 Voo 126 Vpp 36 Vss 156 Vss 66 PN11 186 SN11 96 Ps6 216 Ss6 7 Vpop 127 Vop 37 PN5 157 SN5 67 PN11 187 SN11 97 PS6 217 S56 8 Vss 128 Vss 38 PN5 158 SN5 68 Vss 188 Vss 98 Vss 218 Vss 9 Vec 129 Vec 39 Vss 159 Vss EY 99 PS7 219 SS7 10 Vee 130 Voc 40 PN13 160 SN13 69 Vss 189 Vss 100 Ps7 220 SS7 11 Vss 131 Vss 41 PN13 161 SN13 70 PSO 190 sso 101 Vss 221 Vss 12 Voc 132 Vcc 42 Vss 162 Vss 71 PS0 191 sso 102 PS8 222 Ss8 13 Voc 133 Voc 43 Vss 163 Vss 72 Vss 192 Vss 103 PS8 223 Ss8 144 Vss 134 Vss 44 RFU 164 RFU 73 PS1 193 ss1 104 Vss 224 Vss 145 Ver 11135 Vor 45 RFU 165 RFU 74 PS1 194 Sst 105 RFU 225 RFU 16 VID1 136 VIDO 46 Vss 166 Vss 75 Vss 195 Vss 106 RFU 226 RFU 17 RESET 137 DNU M_Test 47 Vss_ 167 Vss 76 PS2 196 SS2 107 Vss 227 Vss 18 Vss l 138 Vss 48 PN12 168 SN12 77 PS2 197 S52 108 Vpp 228 SCK 19 RFU 139 RFU 49 PN12 169 SN12 78 Vss 198 Vss 109 Vpp 229 SCK 20 RFU 140 RFU 50 Vss__ 170 Vss 79 PS3 199 Ss3 110 Vss 230 Vss 21 Vss 141 Vss 51 PN6 171 SN6 80 PS3 200 553 111 Vpp 231 Vpp 22 PNO 142 SNO 52 PN6 172 SN6 81 Vss 201 Vss 112 Vpp 232 Vpp 23 PNO 143 SNO 53 Vss 173 Vss 82 PS4 202 ss4 113 VDD 233 Vpp 24 Vss 144 Vss 54 PN7 174 SN7 83 Ps4 203 S84 114 Vss 234 Vss2. 25 PN1 145 SN1 55 PN7 175 SN7 84 Vss 204 Vss 115 Vpp 235 VDD 26 PN1 146 SN1 56 Vss 176 Vss 85 Vss 205 Vss 116 Vop 236 VDD 27 Vss 147 Vss 57 PN8 177 SN8 86 RFU 206 RFU 117 Vit 237 Vor 28 PN2 148 SN2 58 PN8 178 SN8 87 RFU 207 RFU 118 SA2 238 VDDSPD 29 PN2 149 SN2 59 Vss l179 Vss 88 Vss 208 Vss 119 SDA 239 SA0 30 Vss 150 Vss 60 PN9 180 SN9 89 Vss 209 Vss 120 SCL 240 SA1 90 PS9 210 sso RFU Reserved Future Use These pin positions are reserved for forwarded clocks to be used in future module implementations These pin positions are reserved for future architecture flexibility a _ _ _ 1 The following signals are CRC bits and thus appear out of the normal sequence PN12 PN12 SN12 SN12 PN13 PN13 SN13 SN13 PS9 PS9 SS9 SS9 VALUERAM0651 001 A00 Page 2 DIMM Connector Pin Description kingston Pin Name Pin Description Count SCK System Clock Input positive line 1 SCK System Clock Input negative line 1 PN 13 0 Primary Northbound Data positive lines 14 PN 13 0 Primary Northbound Data negative lines 14 PS 9 0 Primary Southbound Data positive lines 10 PS 9 0 Primary Southbound Data negative lines 10 SN 13 0 Secondary Northbound Data positive lines 14 SN 13 0 Secondary Northbound Data negative lines 14 SS 9 0 Secondary Southbound Data positive
3. ground and an unpopulated resistor pullup to VCC These resistors can be replaced on production DIMMs with a direct connection to ground VALUERAM0651 001 A00 Page 6 kingston Package Dimensions Units millimeters x 133 35 R 0 75 8 PLACES e g a g o 1 19 DIA o 2 a oe Di 0 10 2 a te 24 40 23 15 19 62 H H 1210 E 12 10 au zoo oii 7 s 30 35 4 PLACES 4 39 L Io TeS O a i 7 5 20 n 120 0 i 2 PLACES 2 fo wom DETAIL A Ss ma 1 50 DIA e695 iat l mA eee own 2 PLACES AS Se PS 2 PLACES on ooo NAO 0 346 8 8 MAX with heat sink Units inches millimeters 45 x 0 0071 0 18 K i 0 042 1 06 0 047 1 19 7 ae 0 042 1 06 0 054 1 37 Detail A 0 046 1 17 VALUERAM0651 001 A00 Page 7
4. lines 10 SS 9 0 Secondary Southbound Data negative lines 10 SCL Serial Presence Detect SPD Clock Input 1 SDA SPD Data Input Output 1 SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB 3 viene Voltage ID These pins must be unconnected for DDR2 based Fully Buffered DIMMs 3 1 0 VID 0 is Vpp value OPEN 1 8 V GND 1 5 V VID 1 is Vcc value OPEN 1 5 V GND 1 2 V RESET AMB reset signal 1 RFU Reserved for Future Use 16 Vec AMB Core Power and AMB Channel Interface Power 1 5 Volt 8 Vpp DRAM Power and AMB DRAM I O Power 1 8 Volt 24 VTT DRAM Address Command Clock Termination Power V pp 2 4 Vop p SPD Power 1 Vss Ground 80 The DNU M_Test pin provides an external connection on R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It DNU M Test is not intended to be used in normal system operation and must not be 1 connected DNU in a system This test pin may have other features on future card designs and if it does will be included in this specification at that time 1 Total 240 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 Eight pins reserved for forwarded clocks eight pins reserved for future architecture flexibility Absolute Maximum Ratings Symbol Parameter MIN MAX Units VIN VOUT Voltage on any pin relative to V ss 0 3 1 75 V VCC Voltage on V ccpin relative to V ss 0 3 1 75 V VDD Voltage V DD pin relative to Vss 0 5 2
5. 1 04 vO 4 pa36 1 04 04 DQ5 1 05 1 05 DQ37 1 05 105 DQ6 1 0 6 1 0 6 DQ38 1 06 06 DQ7 1 07 O7 DQ39 1 07 1 07 basi r DQS5 DQS1 Dass r DQS10 DQS14 Ras NUL cs Das Das Ras NUL Cs Das Das DW NUL_ tS pas Das RMAs NUL_ CS Das Bas Das 1 00 DQ40 1 00 00 DQ9 I 01 D1 1 01 D10 DQ41 1 01 D5 O1 p14 DQ10 I 02 vo 2 DQ42 1 02 1 02 DQ1 I 03 v03 DQ43 1 03 1 03 DQ12 _ 1 04 vO 4 DQ44 1 04 1 04 DQ13 I 05 Vo 5 DQ45 1 05 H 1 05 DQ14 I 06 O 6 DQ46 1 0 6 1 06 DQ15 1 07 O7 DQ47 1 07 1 07 DQS2 1 pase DQSs2 pase DQS11 DAS15 Ras NUL TS Das Das Rias pogs CS Das Das Ros SUL cs Das Das RBas NUL Cs Das DaS DQ16 1 00 O0 DQ48 1 0 0 00 DQ17 1 0 1 D2 01 D11 DQ49 1 01 D6 01 D15 DQ18 1 02 O 2 DQ50 1 02 02 DQ19 03 VO 3 DQ51 1 03 0 3 DQ20 04 1 0 4 DQ52 1 0 4 V04 DQ21 1 05 1 05 Da53 1 0 5 H 1 05 DQ22 0 6 1 0 6 DQ54 1 06 06 pa23 1 07 1 07 Da55 1 07 VO7 DQS3 DQs7 DQS3 DQS7 1 DQS12 DQS16 pa24 1 00 1 00 pass 1 00 00 DQ25 I 01 D3 01 D12 Da57 1 01 D7 O1 D16 DQ26 1 02 1 02 DQ58 1 02 02 DQ27 1 03 1 03 pas9 1 03 03 DQ28 1 04 1 0 4 pa6o 1 04 VO 4 DQ29 0 5 1 05 DQ61 1 05 05 DQ30 0 6 H 1 06 DQ62 1 06 06 DQ31 1 07 1 07 DQ63 1 07 O7 pa
6. 3 V VTT Voltage on V TT pin relative to V SS 0 5 2 3 V Teste Storage temperature 55 100 C Tease DDR2 SDRAM device operating temperature Ambient 0 95 1 C AMB device operating temperature Ambient 0 110 C Note 1 Above 85 C DRAM case temperature the Auto Refresh command interval has to be reduced to tREFI 3 9 us VALUERAM0651 001 A00 Page 3 kingston Functional Block Diagram 31 A So paso r DQS4 n Daso T DQS4 R DQS9 DQS13 RBGs pas CS PAS BAS RDAs Rogs CS PAS DAS Bilas NUL Gs Das Das RMLs NUL cs Das Das DQO 1 00 1 0 0 DQ32 1 00 1 00 DQI 01 DO 1 01 D9 DQ33 1 01 D4 V01 D413 DQ2 1 02 1 0 2 DQ34 1 02 0 2 DQ3 _ 1 0 3 1 03 DQ35 1 03 03 DQ4
7. Kingston iaa Memory Module Specifications KVR800D2D8F5 2G 2GB 256M x 72 Bit PC2 6400 CL5 ECC 240 Pin FBDIMM Description This document describes ValueRAM s 2GB 256M x 72 bit PC2 6400 CL5 SDRAM Synchronous DRAM fully buffered ECC dual rank memory module This module is based on eighteen 128M x 8 bit 800MHz DDR2 FBGA components The module also includes an AMB device Advanced Memory Buffer The electrical and mechanical specifications are as follows Feature FBDIMM Module 240 pin JEDEC Standard R C B Memory Organization 2 rank of x8 devices e DDR2 DRAM Interface SSTL_18 e DDR2 Speed Grade 800 Mbps e CAS Latency 5 5 5 Module Bandwidth 6 4 GB s e DRAM VDD VDDQ 1 8V e AMB VCC VCCFBD 1 5V e EEPROM VDDSPD 3 3V typical Heat Spreader Full DIMM Heat Spreader FDHS PCB Height 30 35mm double side RoHS Compliant VALUERAM0651 001 A00 03 31 08 Page 1 DDR2 240 pin FBDIMM Pinout kingston Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Side Side Side Side Side Side Side Side 1 Voo 121 Vpp 31 PN3 151 SN3 61 PNO 181 SNO 91 PS9 211 ss9 2 Vpop 122 Vpp 32 PN3 152 SN3 62 Vss 182 Vss 92 Vss 212 Vss 3 Vpp 123 Vpp 33 Vss 153 Vss 63 PN10 183 SN10 93 PS5 213 Ss5 4 Vss
8. connected to common return pin DDRC_C14 1 DDRC_B12 DDR Compensation Resistor connected to Vss 1 DDRC_C12 DDR Compensation Resistor connected to Vpp 1 VALUERAM0651 001 A00 Page 5 Advanced Memory Buffer Pin Description i Kingston SPD Bus Interface Signals 5 SCL Serial Presence Detect SPD Clock Input 1 SDA SPD Data Input Output 1 SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB 3 Miscellaneous Signals 163 PLLTSTO PLL Clock Observability Output 1 VCCAPLL Analog VCC for the PLL Tied with low pass filter to VCC 1 VSSAPLL Analog VSS for the PLL Tied to ground on the AMB die Do not tie to ground on the DIMM 1 TEST_pin Leave floating on the DIMM 6 TESTLO_pin Tie to ground on the DIMM2 5 BFUNC Tie to ground to set functionality as buffer on DIMM 1 RESET AMB reset signal 1 NC No connect Many NC are connected to VDD on the DIMM to lower the impedance of the VDD power 129 islands RFU Reserved for Future Use 18 Power Ground Signals 213 Vec AMB Core Power 1 5 Volt 24 VcecFBD AMB Channel I O Power 1 5 Volt 8 VDD AMB DRAM I O Power 1 8 Volt 24 Vppspp SPD Power 3 3 Volt 1 Vss Ground 156 Total 655 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on prototype DIMMs each pin should have a zero ohm resistor pulldown to
9. gative lines 10 SN 13 0 Secondary Northbound Data positive lines 14 SN 13 0 Secondary Northbound Data negative lines 14 SS 9 0 Secondary Southbound Data positive lines 10 SS 9 0 Secondary Southbound Data negative lines 10 FBDRES To an external precision calibration resistor connected to Vcc 1 DDR2 Interface Signals 175 DQS 8 0 Data Strobes positive lines 9 DQSI 8 0 Data Strobes negative lines 9 DQS 17 9 DM 8 0 Data Strobes x4 DRAM only positive lines These signals are driven low to x8 DRAM on writes 9 DQS 17 9 Data Strobes x4 DRAM only negative lines 9 DQ 63 0 Data 64 CB 7 0 Checkbits 8 A 15 0JA A 15 0 JB Addresses A10 is part of the pre charge command 32 BA 2 0 A BA 2 0 B Bank Addresses 6 RASA RASB Part of command with CAS WE and CS 1 0 2 CASA CASB Part of command with RAS WE and CS 1 0 2 WEA WEB Part of command with RAS CAS and CS 1 0 2 2 4 4 ODTA ODTB On die Termination Enable CKE 1 0 A CKE 1 0 B Clock Enable one per rank CS 1 0 A CS 1 0 B Chip Select one per rank CLK 1 0 used on 9 and 18 device DIMMs CLK 3 0 used on 36 device DIMMs CLK 3 2 should be out CLKI3 0 put disabled when not in use E CLK 3 0 Negative lines for CLK 3 0 4 DDRC_C14 DDR Compensation Common return pin for DDRC_B18 and DDRC_C18 1 DDRC_B18 DDR Compensation Resistor connected to common return pin DDRC_C14 1 DDRC_C18 DDR Compensation Resistor
10. ss g Dass N DQS17 PNO PN13 SNO SN13 PNO PN13 SNo SN13 Rbas NUL cs Das Das Roos Sess CS DAS DAS PS0 PS9 SS0 SS9 CBO 1 00 1 0 0 ee yp 880 889 CB1 0 1 D8 O1 D17 A 50 gt CTS D0 D8 CB2 02 1 02 M CKEO gt CKE D0 D8 CB3 1 03 1 0 3 M S1 gt CS D9 D17 CB4 1 0 4 04 B CKE1 gt CKE D9 D17 CB5 05 05 SCL M ODT gt ODT all SDRAMs CB6 06 06 SDA BAO BA2 all SDRAMs CB7 SA1 SA2 A0 A15 all SDRAMs 1 07 O7 SA0 RAS all SDRAMs a 1 CAS all SDRAMs RESET WE all SDRAMs Vt ___ Terminators SCK SCK CK CK all SDRAMs ass i Vcc AMB 1 8250 220 All address command control clock V VTT Vopspp te SPD AMB Notes T 1 DQ to I O wiring may be changed within a byte Seralkp VoD D0 D17 AMB 2 There are two physical copies of each so p gt SDA V T D0 D17 WP AO A1 A2 REF A address command control clock l T 1 SAO SAT SA2 Vss p0 D17 SPD AMB VALUERAM0651 001 A00 Page 4 ie Kingston Architecture Advanced Memory Buffer Pin Description Pin Name Pin Description Count FB DIMM Channel Signals 99 SCK System Clock Input positive line 1 SCK System Clock Input negative line 1 PN 13 0 Primary Northbound Data positive lines 14 PN 13 0 Primary Northbound Data negative lines 14 PS 9 0 Primary Southbound Data positive lines 10 PS 9 0 Primary Southbound Data ne
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