Infineon DDR2 2GB 667MHz CL5
Contents
1. Max Voltage on Vppq pin relative to Vss Vopo 0 5 2 3 V 2 3 Voltage on Vpp pin relative to Vss VbpL 0 5 2 3 V 2 3 Voltage on any pin relative to Vss Vin Vout 0 3 41 75 V 2 Voltage on Vy pin relative to Vss Vir 0 5 2 3 Vv Storage Temperature Tet 55 100 C 2 3 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 When Vp5p and Vp59 and Vpp are less than 500 mV Vreer may be equal to or less than 300 mV 3 Storage Temperature is the case surface temperature on the center top side of the DRAM Attention Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability LP N e FB DIMM Latency Range Parameter DDR2 800D DDR2 667D Unit Note Min Nom Max Min Typ Max tc2D_DIMM Tbd 19 35 Tbd 17 5 21 21 5 ns 1 2 RESAMPLE_DIMM_SB Tbd 1 68 Tbd 1 4 1 692. 2 4 ns 2 3 tresyNC_DIMM_SB Tbd 2 66 Tbd 2 5 2 8 3 7 ns 2 5 tresYNC_DIMM_NB Tbd 2 54 Tbd 2 4 2 8 3 6 ns 2 6 1 For DDR 800D and DDR 800E no industry standard values are avalible for Min and Max parameter 2 Measured delay at FB DIMM gold finger between the center of the1ist UI of command frame on the primary southbound lane 81 connector pins 102 amp 103 and the center of the 1st UI of return data on the primary northbound lane 0 connector pins 22 amp 23 CL DRAM CAS latency value frame clock period AL DRAM additional latency value frame clock period 3 Measured delay at FB DIMM gold finger between the center of the 1st UI of a frame on the primary southbound lane 8 connector pins 102 amp 103 and the center of the 1st UI of the same frame on the secondary southbound lane 8 connector pins 222 amp 223 4 Measured delay at FB DIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 connector pins 142 amp 143 and the center of the ist UI of the same frame on the primary northbound lane 0 connector pins 22 amp 23 AENEON Data Sheet 4 Revision 1 10 2008 05 A Qimonda AG Brand Doc 12272007 OKYD PLKJ by Qimonda SAENEDM oa 5 Measured delay at FB DIMM gold finger between the center of the 1st UI of a frame on the secondary northbound lane 0 connector pins 142 amp 143 and the center of the 1st UI of the same frame on the primary northbound lane 0 connec
3. Doc 12272007 OKYD PLKJ AENEOM by Qimonda DDR2 Fully Buffered Memory Module Operating conditions This chapter describes the operating conditions TABLE 3 DC Operating Conditions Parameter Symbol Limit Values Unit Notes Min Nom Max AMB Supply Voltage DC Vec 1 455 1 5 1 575 V 1 AMB Supply Voltage DC AC 1 425 1 5 1 590 V 2 DRAM Supply Voltage Vop 1 7 1 8 1 9 V Termination Voltage Vir 0 48 xVbp 0 50 xVpp 0 52 xVbp V EEPROM Supply Voltage Voppspp 3 0 3 3 3 6 V DC Input Logic High SPD Vino 2 1 VARA V 3 DC Input Logic Low SPD Vioc 0 8 V 3 DC Input Logic High RESET Vin oc 1 0 V 4 DC Input Logic Low RESET Vioc 0 5 V 3 Leakage Current RESET I 90 90 pa 9 Leakage Current Link I 5 5 pa gt 1 At OKHz 30KHz 2 AT 30KHz 1 MHz 3 Applies for SMB and SPD Bus Signals 4 Applies for AMB CMOS Signal RESET 5 For all other AMB related DC parameters contact AENEON technical staff TABLE 4 Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Min Max Voltage on any SMbus interface signal pin relative to Vss Vin Vout 0 5 4 00 V 1 Voltage on Vpp pin relative to Vss Vop 0 5 2 4 V 2 Voltage on Vec pin relative to Vss Vec 0 3 1 75 V AENEON Data Sheet 3 Revision 1 10 2008 05 A Qimonda AG Brand Doc 12272007 OKYD PLKJ AENEOM by Qimonda DDR2 Fully Buffered Memory Module Parameter Symbol Rating Unit Notes Min
4. SAENEDM OG by Qimonda AETx61FBxx 30D 25D xxxX 512MB 1GB 2GB and 4GB This Data Sheet describes AENEON DDR2 Fully Buffered DIMM on 240 pin modules with parity bit for address and control bus and its main characteristics Key features Fully buffered DDR2 memory modules Available in single pack of densities 512MB 1GB 2GB 4GB Standard JEDEC pin configuration Validated by major motherboard vendors Fully ROHS compliant MBIST and IBIST test function Uses Advanced Memory Buffer AMB to effectively control and manages memory traffic Supports channel initialisation Supports the forwarding of southbound and northbound frames servicing requests directed to a specific AMB or DIMM and merging the data in northbound frames Detects errors on the channel and reports them to the host memory controller Supports FB DIMM configuration register set Acts as DRAM memory buffer for all operations Provides logic to support MEMBIST and IBIST design for test functions Module size of 133 35 x 30 35 x 8 2 mm e Fully buffered DIMMs comes with heat sink TABLE 1 Ordering Information 64M x 72 PC2 5300 555 133 35 x 1GB 128M x 72 2Rx8 18 30 35 x 8 2 1GB 128M x 72 2Rx4 18 256M x 72 36 256M x 72 18 4GB 512M x 72 2Rx4 36 512M x 72 133 35 x 36 30 35 x 8 2 256M x 72 PC2 6400 555 512M x 72 1 Full Product Type Sales Descr
5. and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered AENEON Data Sheet A Qimonda AG Brand Revision 1 10 2008 05 Doc 12272007 OKYD PLKJ
6. iption AENEON Data Sheet 1 Revision 1 10 2008 05 A Qimonda AG Brand Doc 12272007 OKYD PLKJ SAENEDM OG by Qimonda TABLE 2 Speed Grade Definition 8 1 2 3 4 8 1 2 3 4 CL 5 tck 2 5 8 3 ns 1 2 3 4 CL 6 tex 2 5 8 ns 1 2 3 4 CL 7 tck 2 5 8 ns 1 2 3 4 5 tras 45 70k 45 70k ns 1 2 3 4 5 6 40 70k 40 70k ns 1 2 3 4 5 7 1 2 3 4 tec 52 5 55 ns 1 2 3 4 1 2 3 4 trp 12 5 15 ns 1 2 3 4 1 Timings are guaranteed with CK CK differential Slew Rate of 2 0 V ns For DQS signals timings are guaranteed with a differential Slew Rate of 2 0 V ns in differential strobe mode and a Slew Rate of 1 V ns in single ended mode 2 The CK CK input reference level for timing reference to CK CK is the point at which CK and CK cross The DQS DQS RDQS RDQS input reference level is the crosspoint when in differential strobe mode 3 Inputs are not recognized as valid until Ve stabilizes During the period before Vpe stabilizes CKE 0 2 x Vong 4 The output timing reference voltage level is Vyr 5 tras max is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 X fpery 6 Products released after 2007 08 01 can support fans min 40 ns for all DDR2 speed sort 7 For products released after 2007 08 01 AENEON Data Sheet 2 Revision 1 10 2008 05 A Qimonda AG Brand
7. tor pins 22 amp 23 6 Measured delay at FB DIMM gold finger between the center of the1ist UI of command frame on the primary southbound lane 81 connector pins 102 amp 103 and the center of the 1st UI of return data on the primary northbound lane 0 connector pins 22 amp 23 CL DRAM CAS latency value frame clock period AL DRAM additional latency value frame clock period Information To obtain more information about these products please contact your AENEON representative Please Note The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest distribution partner Components may only be used in life support devices or systems with the express written approval of Qimonda AG if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain
Download Pdf Manuals
Related Search