Transcend JetRam 512MB SDRAM 168pin DIMM
Contents
1. JM366S643A 75 Dimensions Pin Identification Side Millimeters Inches Symbol EUNGUGN A 133 35 0 40 5 250 0 016 A0 A12 BAO BA1 Address input B 65 67 2 585 DQ0 DQ63 Data Input Output C 23 49 0 925 CLKO CLK3 Clock Input D 8 89 0 350 E 3 00 0 118 CKEO CKE1 Clock Enable Input F 29 21 0 20 1 150 0 008 CS0 CS3 Chip Select Input G 19 80 0 788 RAS Row Address Strobe H 15 80 0 622 CAS Column Address Strobe 1 27 0 10 0 050 0 004 Refer Placement WE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Refer Block Diagram AND Pinouts Transcend information Inc 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT Pinouts Pin Name No Name No Name No Name Transcend information Inc 3 JM366S643A 75 512MB 168PIN PC133 CL3 SDRAM DIMM With 32M X 8 3 3VOLT JM366S643A 75 Block Diagram A0 A12 BAO BA1 DQ0 DQ63 RAS CAS WE CS0 CKEO CS2 CLKO CLK2 CS1 CKE1 CS3 CLK1 CLK3 DQ0 DQ7 RAS CAS CAS WE A0 A12 BAO BA1 DQ0 DQ7 RAS CAS A0 A12 BAO BAt DQ0 DQ7 RAS CAS WE 32Mx8 32Mx8 SDRAM SDRAM DQ0 DQ7 RAS DQ0 DQ7 RAS CAS WE ICS CKE 32Mx8 SDRAM 32Mx8 SDRAM 32Mx8 SDRAM c a SDRAM e ICKE e Serial EEPROM SCL SCL SDA SDA A0 A1 A2 SA02. 23 SDRAM Cycle Time 2 highest CL po o 00 f 24 SDRAM Access from Clock 2 highest CL 00 25 SDRAM Cycle Time 3 highest CL po o 00 ef 26 SDRAMAccessfromClock 3 highest CL 00 33 Command Address Hold Time 1 1 O8ns 08 O 35 Data Signal Hold Time 1 1 O8ns 08 O 3661 Supersetinformation Cid o y 00 OE 63 ChecksumforBytes0 62 CE Ct 72 ManufacturingLocaton o0 75 90 Manufacturers Part Number 0 9 7 91 92 Revision Code 00 E Transcend information Inc 10 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT 93 94 Manufacturing Date L0 00 95 98 Assembly Serial Number 9e ip dor 4 99 125 Manufacturer Specific Data Lu 77 126 Intel Specification Frequenc 100MHz Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 128 Unused Storage Locations Transcend information Inc 11
3. down mode liccsPS CKE amp CLKSVIL ICKE amp CLKsViumax tcc si tCC lt Icc3N CKE2ViHimin CS ViH min tcc 10ns Active Standby Current Input signals M changed one time during 20ns Bi in non power down mode lie Bane Icc3NS_ CKE Vin min CLKsViL max toc Input signals are stable Operating Current Icc4 lOL 0 mA 1360 mA Bust Mode Page Burst tccp 2CLKs Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 6 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT AC OPERATING TEST CONDITIONS voo 3 3V 110 3V Ta 0 to 7 C Paameer Clue Unt AC Input levels VIH VIL 2 4 0 4 flv Input timing measurement reference level Input rise and fall time tr tf 1 1 Output timing measurement reference level NENNT es CEN Output load condition SeeFip2 o O ot 1 4V 1200 Ohm 50 Ohm Vou DC 2 4V lonz 2mA Output Q Z0 80 Ohm Q9 Vot DC 0 4V lo 2mA 50pF ETE 50pF 870 Ohm e A T TN UI Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit g OPERATING AC PARAMETER AC operating conditions unless otherwise noted a DRM RR meia mn m m a RN RR P ER PT NNI ce tae od Row cycle time EXL ewe Last data in to new col address delay pues or Last data in to row precharge tRDL m Last data in to burst stop tBDL min afe a eae 7A e a Col address
4. to col address delay omn tf ck og Number of valid CAS MEAS 3 4 output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 n case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module CLK cycle time tcc CLK to valid output delay CAS latency 3 isao s4 ms tow 27 ns HiKWehpukeweh o Dcus a EE eiie a cKlowpkewan w 25 m Input setup time tss ee e sa o8 m i xo 3 ee ee CLK to outputin Hiz castatency s ez sa ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf Ins If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT SIMPLIFI
5. 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT Description Placement The JM366S643A 75 is a 64M bit x 64 Synchronous Dynamic RAM high densities for PC 133 The O JM366S643A 75 consists of 16pcs CMOS 32Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The JM366S643A 75 is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allows the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Conformed to JEDEC Standard 4 clocks e Burst Mode Operation e Auto and Self Refresh o EF e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave PCB 09 7303 e Allinputs are sampled at the positive going edge of the system clock Transcend information Inc 1 512MB 168PIN PC133 CL3 SDRAM DIMM With 32M X 8 3 3VOLT
6. ED TRUTH TABLE m aux He KCN ES Refresh Auto Refresh Refresh Sel Refresh ama ata Seen one Bank Active amp Row Addr Row Address Read amp Auto Auto Precharge Disable Disable ESQ Column Add Column Address Ato eee Enable oH AowAa 5 Write amp Auto Precharge Disable Column Column Address Address Auto Auto Precharge Enable Enable oH Ao As 4 5 Burst Stop J J O Eur i eens i8 Precharge ae Selection Esters Both Banks sd Banks m RE X No RM Command a V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BAt1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BAt Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and both banks a
7. ME oa ei IOL 2mA i 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 Dout is disabled OV lt VOUT lt VDDQ Transcend information Inc 5 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT CAPACITANCE vDo 3 3V TA 20 C f 1MHz vREF 1 4V 1200 mV Parameter Input capacitance Ao A11 BAo BA1 Input capacitance RAS CAS WE Input capacitance CKEO Input capacitance CLKO CLK3 Input capacitance CSO CS2 Input capacitance DQM0 DQM7 Data input output capacitance DQ0 DQ63 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 7 C Parameter Symbol CAS Latency Valve yp Unit Note Operating Current Burst Length 1 Icc1 tRC gt tRC min 1 200 mA 1 One Bank Active loL 0mA Precharge Standby Current icceP CKE Vi max tcc 10ns in power down mode iccePS CKE amp CLK lt ViLma tcc a Icc2N CKE ViH min CS2ViH min tcc 10ns Input signals are changed one time during 20ns Precharge Standby Current in non power down mode CKE ViH min CLK lt VIL max tCC Icc2NS Input signals 2 stable Active Standby Current estes yn estos _ max tcc 10ns in power
8. SA1 SA2 A0 A12 BAO BA1 DQ0 DQ7 RAS BAO BA1 DQ0 DQ7 RAS CAS WE ICS CKE 32Mx8 SDRAM S a DQ0 DQ7 RAS souxs SDRAM DQ0 DQ7 RAS CAS WE ICS CKE This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT ABSOLUTE MAXIMUM RATINGS symbol value Unt Voltage on any pin relative to Vss 1 0 4 6 V Voltage on VDD supply to Vss 1 0 4 6 55 4150 Power dissipation t cin w O Short circuit current los Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Sym Mn Typ max unt moe Supply voltage Von Input high voltage Vi Input low voltage m os o j os v Output high voltage VOH lm MR md LI IOH 2mA Output low voltage VOL sen A
9. re selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DOM latency is 2 Transcend information Inc 9 512MB 168PIN PC133 CL3 JM366S643A 75 SDRAM DIMM With 32M X 8 3 3VOLT Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Vendor Part Specification 0 fofBytesWritteninto Serial Memory 128bytes 3 jf amp ofRowAddressesonthis Assembly 13 OD 6 Data Width of thisAssembly 64bts 40 7 DataWidth Continuation 1 o Z 200 8 Voltage Interface Standard of this Assembly LVTTLS 3V 01 9 SDRAM Cycle Time highest CAS latency 75ns amp 75 11 DIMM configuration type non parity ECC Nonpaity OO 138 Primary SDRAM Width J X8 08 14 Error Checking SDRAMWidh Noe X 00 X 21 SDRAM Module Attributes NonBuffer 00 Prec R W Burst
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