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1. Pin Name Pin No Nor m Direction Pin Name Pin No sitter Tv Direction vss P23 Power Other VSS V29 Power Other vss P25 Power Other VSS V31 Power Other VSS P27 Power Other VSS W2 Power Other VSS P29 Power Other VSS WA Power Other vss P31 Power Other VSS W24 Power Other vss R2 Power Other VSS W26 Power Other VSS R4 Power Other VSS W28 Power Other VSS R6 Power Other VSS W30 Power Other vss R8 Power Other VSS Y1 Power Other VSS R24 Power Other VSS Y5 Power Other VSS R26 Power Other VSS Y7 Power Other VSS R28 Power Other VSS Y13 Power Other VSS R30 Power Other VSS Y19 Power Other VSS T1 Power Other VSS Y25 Power Other VSS T3 Power Other VSS Y31 Power Other VSS 5 Power Other vss AA2 Power Other vss T7 Power Other VSS Power Other vss T9 Power Other VSS 15 Power Other vss T23 Power Other VSS 17 Power Other VSS T25 Power Other VSS AA23 Power Other VSS T27 Power Other VSS AA30 Power Other VSS T29 Power Other VSS 1 Power Other VSS T31 Power Other VSS AB5 Power Other VSS U2 Power Other VSS AB11 Power Other VSS U4 Power Other VSS AB21 Power Other VSS U6 Power Other VSS AB27 Power Other VSS U8 Power Other VSS AB31 Power Other VSS U24 Power Other VSS AC2 Power Other VSS U26 Power Other VSS AC7 Power Other VSS U28 Power Other VSS AC13 Power Other VSS U30 Power Other VSS AC19 Power Other VSS V1 Power Other VSS AC25 Power Other
2. Pin Name Pin No Ne orm Direction Pin Name Pin No dm Direction BR1 F12 Common Clk Input D32 AB16 Source Sync Input Output BR2 E11 Common Input D33 AA16 Source Sync Input Output BR3 D10 Common Clk Input D34 AC17 Source Sync Input Output BSELO AA3 Power Other Output D35 AE13 Source Sync Input Output BSEL1 AB3 Power Other Output D36 AD18 Source Sync Input Output COMPO AD16 Power Other Input D37 AB15 Source Sync Input Output 1 E16 Power Other Input D38 AD13 Source Sync Input Output D0 Y26 Source Sync Input Output D39 AD14 Source Sync Input Output D1 AA27 Source Sync Input Output D40 AD11 Source Sync Input Output D2 Y24 Source Sync Input Output D41 AC12 Source Sync Input Output D3 AA25 Source Sync Input Output D42 AE10 Source Sync Input Output D4 AD27 Source Sync Input Output D43 AC11 Source Sync Input Output D5 Y23 Source Sync Input Output D44 AE9 Source Sync Input Output D6 AA24 Source Sync Input Output D45 AD10 Source Sync Input Output D7 AB26 Source Syne Input Output D46 AD8 Source Sync Input Output D8 AB25 Source Sync Input Output D47 AC9 Source Sync Input Output D9 AB23 Source Sync Input Output D48 AA13 Source Sync Input Output D10 AA22 Source Sync Input Output D49 AA14 Source Sync Input Output D11 AA21 Source Sync Input Output D50 AC14 Source Sync Inp
3. TEKELER 006060008 Oeooeooeooceoolocee eoeooeooeooeclooee 000 00 00 0080008 Oeooeooeooeoolooee eoeooeooeooeojooee 0008600000800000 16 18 20 22 24 26 28 DATA SMBus SM VCC GTLREF Reserved lt c S Z gt m D 2 lt SSA 99A 65 Intel Xeon Processor with 512 KB L2 Cache Figure 36 66 Processor Pin Out Diagram Bottom View Async COMMON COMMON JTAG CLOCK REDRESS CLOCK 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 eeeeoo eoocee B eeeoceo oeoeo B eeeooe eeoee c D eooee D E eeeoeo Ooooee E F eeecoce oecoeoee F G eee eeee H eco eeee H J eee eeee J lt K eee eeee K y iL eee eeee L2 lt M eco eeee M S 2 N eco eeee N P eee eeee R eee eeeel R T eee eeee U eeee V eee e eee v eoee w Y eoolooeoo eoo ooee v AA eoooeooe Oeo 6 AA AB eoo oeo ooe AB eoo eeebo Aleeoojoeooe Oeo O e 0 Ap AE Oeo eee AE 28 26 24 22 20 18 16 14 12 0 8 6 4 2 SMBus DATA CLOCKS O Signal SM_VCC Power GTLREF Ground Reserved Datasheet 5 0 Intel Xeon Processor with 512 KB L2 Cache
4. 105 45 Read Byte SMBus Packet ertet tet Dr etate eua eret ui Ea 107 46 Write Byte SMBus Packet rennen nasa 107 47 Write Byte SMBUS Packet etr ater mede Fer edt e reel 108 48 Read Byte SMBus Packet L n a 108 49 Send Byte SMBus PacketReceive Byte SMBus 109 50 5 u unu er e RR ax 109 51 SMBus Thermal Sensor Command Byte Bit 109 52 Thermal Reference Register 110 53 SMBus Thermal Sensor Status Register eene 111 54 SMBus Thermal Sensor Configuration 112 55 SMBus Thermal Sensor Conversion Rate 112 Datasheet 7 E Contents ntel Thermal Sensor SMBus Addressing n 114 Memory Device SMBus Addressing n n 114 Fan Cable Connector 122 Fan Power and Signal Specifications nnns 122 Datasheet intel Revision History Date of Release Description January 2002 001 Initial datasheet release April 2002 002 Addition of 2 40 GHz Data May 2002 003 Updated Figures 10
5. na 38 8 Differential Clock Crosspoint Specification a 38 9 Front Side Bus Common Clock Valid Delay Timing 39 10 Front Side Bus Source Synchronous 2X Address Timing 39 11 Front Side Bus Source Synchronous 4X Data Timing 40 12 Front Side Bus Reset and Configuration Timing 22 41 13 Power On Reset and Configuration Timing Waveform 41 14 TAP Valid Delay Timing 42 15 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform 42 16 THERMTRIP to TIMING 2 etr etc tee te Eu pe ute 42 17 SMBus Timing 43 18 SMBus Valid Delay Timing Waveform n 43 19 Example 3 3 VDC SM_VCC Sequencing a 44 20 BCLK 1 0 Signal Integrity Waveform n 46 21 Low to High Front Side Bus Receiver Ringback Tolerance for AGTL and Asynchronous GTL BUl E Y 47 22 High to Low Front Side Bus Receiver Ringback Tolerance for AGTL and Asynchronous GTL
6. 48 23 Low to High Front Side Bus Receiver Ringback Tolerance for PWRGOOD Buffers 48 24 High to Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers 49 25 Maximum Acceptable Overshoot Undershoot Waveform 55 26 INT mPGA Processor Package Assembly Drawing Includes Socket 57 27 INT mPGA Processor Package View Component Placement Detail 58 28 INT mPGA Processor Package Drawing L 59 29 INT mPGA Processor Package Top View Component Height Keep in 60 30 INT mPGA Processor Package Cross Section View Pin Side Component 60 31 INT mPGA Processor Package Pin Detail sss nnns 61 32 IHS Flatness and Tilt Drawing cose tor ette rix rado 62 33 Processor Top Side Markings nennen nennen entente nns 64 34 Processor Bottom Side Markings nnne 64 35 Processor Pin Out Diagram Top View nennen enne nnne nns 65 36 Processor Pin Out Diagram Bottom View L 66 37 Processor with Thermal and Mechanical Components Exploded 95 38 Processor Thermal Design Power vs Electrica
7. 1007751 Det nd sean xz 2 1920761 241 056 2 997721 209 er 2l 19 NvsT 8 61 DOSL 0 8 000 9 TITLE IPWT VOLUMETRIC PROCESSOR WIND TUNNEL xt Datasheet Intel Xeon Processor with 512 KB L2 Cache 123 Intel Xeon Processor with 512 KB L2 Cache I ntel Figure 50 Processor Wind Tunnel Detailed Dimensions 124 Datasheet I ntel Intel Xeon Processor with 512 KB L2 Cache 1U Rack Mount Server Solution The 1U solution contains a passive heatsink and a foam pad in addition to the retention solution included with the other options Because of the small form factor the 1U heatsink is not as efficient at dissipating heat as the general purpose heatsink In order to ensure maximum thermal efficiency the foam pad must be attached to the top of the 1U heatsink blocking airflow between the heatsink and the chassis cover This will force air through the heatsink fins instead of allowing it to bypass over the top See Figure 51 and Figure 52 for more detail on installation Figure 51 Exploded View of the 1U Thermal Solution Datasheet 125 Intel Xeon Processor with 512 KB L2 Cache Figure 52 Assembled View of the 1U Thermal Solution 126 Datasheet E ntel Intel Xeon Processor with 512 L2 Cache 8 4 8 4 1
8. Datasheet 31 Intel Xeon Processor with 512 KB L2 Cache n Table 13 AGTL Bus Voltage Definitions 2 13 COMP 1 0 New COMP Resistance 49 55 50 50 45 Q 5 7 8 Design NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The tolerances for this specification have been stated generically to enable system designer to calculate the minimum values across the range of Vcc 3 GTLREF is generated from Vcc on the baseboard by a voltage divider of 1 percent resistors Refer to the appropriate platform design guidelines for implementation details 4 Rrr is the on die termination resistance measured from Vcc to 1 3 at the AGTL output driver Refer to the Inte Xeon Processor with 512 KB L2 Cache Signal Integrity Models for I V characteristics 5 COMP resistors are pull downs to Vss provided on the baseboard with 1 tolerance See the appropriate platform design guidelines for implementation details 6 The referred to in these specifications refers to instantaneous Vcc 7 The COMP resistance value varies by platform Refer to the appropriate platform design guideline for the recommended COMP resistance value 8 The values for and COMP noted as New Designs apply to designs that are optimized for the Intel Xeon processor with 512 KB 12 cache Refer to the appropriate platform design guideline for the rec
9. Fan connector 643815 3 header 640456 3 Walden Molex Fan connector 22 01 3037 header 22 23 2031 Pin Out See Figure Above Fan cable length Pin 1 Ground black wire Pin 2 Power 12 V yellow wire Pin 3 Signal Open collector tachometer output signal requirement 2 pulses per revolution green wire The fan cable connector must reach a mating mainboard connector at any point within a radius of 110 mm 4 33 2 measured from the central datum planes of the enabled assembly datum planes A B amp C on Drawing AXXXXX Fan power cable must be routed in such a way to prevent it from Fan cable ina the fan i i di b tioned i routing contacting the fan impellor and it must be positioned in a consistent location from unit to unit Table 59 Fan Power and Signal Specifications Description Min Typ Max Unit Notes 12V 12 Vot Fan Power Supply 6 0 12 0 13 2 V IC Fan Current Draw 1 5 400 A mA Pulses per fan SENSE Frequency 2 r volution 1 NOTE 1 Baseboard should pull this pin up to with a resistor 2 1 5A is required for 3 GHz and 400 mA is required for frequencies 1 80 GHz and 2 80 GHz 122 Datasheet intel Figure 49 Processor Wind Tunnel General Dimensions a 00679 9251 INTI e d 95161 122098 821 91 r2 1 4001 TOP OF BOARD
10. 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 3 All common clock AC timings for AGTL signals are referenced to the Crossing Voltage Vcross of the Not 100 tested Specified by design characterization BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at GTLREF at the processor core Valid delay timings for these signals are specified into the test circuit described in Figure 5 and with GTLREF at 2 3 Voc 2 Specification is for a minimum swing defined between AGTL Vi max to This assumes an edge rate of 0 3 V nS to 4 0 V nS RESET can be asserted active asynchronously but must be deasserted synchronously This should be measured after and BCLK 1 0 become stable Maximum specification applies only while PWRGOOD is asserted Front Side Bus Source Synchronous AC Specifications Page 1 of 2 T Parameter Min Max Unit Figure Notes T20 Source Sync Output Valid Delay first data 0 20 1 30 ns 10 11 1 2 3 4 address only 5 T21 Tygp Source Sync Data Output Valid Before 1 2 3 4 Data Strobe 9 99 ns nN 5 8 T22 Tyap Source Sync Data Output Valid After 1 2 3 4 Data Strobe 9 89 ns 5 8 T23 Tyga Source Sync Address Output Valid 1 88 ns 10 1 2 3 4 Before Address Strobe 5 8 T24 Source Sync Address Output
11. Figure 13 Power On Reset and Configuration Timing Waveform X X XX X X X X XXX veo PWRGOOD u T Resets MAN T37 PWRGOOD Inactive Pluse Width Tb T36 PWRGOOD to RESET de assertion time Datasheet 41 a Intel Xeon Processor with 512 KB L2 Cache ntel Figure 14 TAP Valid Delay Timing Waveform TCK Tx Ts T HA Tx T63 Valid Time Ts T61 Setup Time Th T62 Hold Time V 0 5 Vec Signal Figure 15 Test Reset TRST Async GTL Input and PROCHOT Timing Waveform T 164 TRST Pulse Width V 0 5 Vcc T38 PROCHOT Pulse Width V GTLREF Figure 16 THERMTRIP to Timing THERMTRIP Power Down Sequence T39 THERMTRIP 7 Vcc T39 lt 0 5 seconds Note THERMTRIP is undefined when RESET is active 42 Datasheet Intel Xeon Processor with 512 KB L2 Cache t tip t HD STA HD DAT taia Data t LOW T73 t HIGH T72 R tF 2775 STOP t T80 SU STA 81 t T78 t sussTD 82 t BUF 179 t su pat 177 Figure 18 SMBus Valid Delay Timing Waveform SM_CLK 4 gt DATA VALID SM_DAT E DATA OUTPUT gt TAA 176 Datasheet 43 Intel Xeon Processor with 512 KB L2 Cache 44 Figure 1
12. Datasheet 47 a Intel Xeon Processor with 512 KB L2 Cache ntel Figure 22 High to Low Front Side Bus Receiver Ringback Tolerance for AGTL and Asynchronous GTL Buffers Voc 10 Vcc GTLREF 10 Vcc Vss Figure 23 Low to High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers Vcc A Threshold Region to switch receiver to a logic 1 Vt max Vt min 0 5 Vcc gt Vt max 4 Allowable Ringback Vss 48 Datasheet E ntel Intel Xeon Processor with 512 KB L2 Cache Figure 24 High to Low Front Side Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers Vcc Allowable Ringback Vt min 0 5 Vcc Vt max Vt min Threshold Region to switch receiver to a logic 0 Vss Datasheet 49 a Intel Xeon Processor with 512 KB L2 Cache ntel 3 3 3 3 1 3 3 2 3 3 3 50 Front Side Bus Signal Quality Specifications and Measurement Guidelines Overshoot Undershoot Guidelines Overshoot or undershoot is the absolute value of the maximum voltage above or below The overshoot undershoot specifications limit transitions beyond or Vss due to the fast signal edge rates The processor can be damaged by single and or repeated overshoot or undershoot events on any input output or I O buffer if the charge is large enough 1 if the ov
13. SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present SLP SLP Sleep when asserted in Stop Grant state causes processors to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units SM_ALERT SM_ALERT is an asynchronous interrupt line associated with the SMBus Thermal Sensor device It is an open drain output and the processor includes a 10 KQ pull up resistor to SM_Vcc for this signal For more information on the usage of the SM_ALERT pin see Section 7 4 5 90 Datasheet n Intel Xeon TM Processor with 512 KB L2 Cache Table 41 Signal Definitions Page 8 of 10 Name Type Description Notes The SM_CLK SMBus Clock signal is an input clock to the system management logic which is required for operation of the system management features of the SM_CLK y o processor This clock is driven by the SMBus controller and is asynchronous to other clocks in the pr
14. Signals on the front side bus use Assisted GTL AGTL level voltages which are fully described in the appropriate platform design guide refer to Section 1 3 Terminology A symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 refers to a hex A and D 3 0 also refers to a hex A H High logic level L Low logic level Front Side Bus FSB refers to the electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Processor Packaging Terminology Commonly used terms are explained here for clarification 603 pin socket The connector which mates the Intel Xeon processor with 512 KB L2 cache to the baseboard The 603 pin socket is a surface mount technology SMT zero insertion force ZIF socket utilizing solder ball attachment to the platform See the 603 Pin Socket Design Guidelines for detail
15. 1500 705271 SWMWIXYN SNOISN3HIQ e 81207569 xz 32N383438 NON TV Q3141234S ISIMYIHLO SS3TND P 078 11 110 00661 pl OF 870467908 NOISNSWIG NOI1ON04 OL 19911199 Cool EJ NIN 272 H19N31 NI 0007 1 752 2 WILY Q3831N32 03211Y201 38 AYW 11 H19N31 1006721 0S 9 331143 ISYJAYYL OL 3AYH LON 300 1015 2 5 Me li NOlIVOl Tdd 32V3u31NI 1VW33Hl ANY 5N128383J34 805532084 303 43811038 SI Y INOZ SSINLYTA 1 1061 1 9 p x2 153100 V 11 130 33 TE S 8701 80112181838 MOTINIY ANY 9NIZINININ WHHL HONOYHL MO13UlV HOTTY LSnW S39V390S 000 2 806 ES XG Figure 47 Multiple View Space Requirements for the Boxed Processor 1 5886 r B 3 n 9 uml one Intel Xeon Processor with 512 12 Cache Datasheet 120 E ntel Intel Xeon Processor with 512 L2 Cache Note 8 2 5 8 2 6 Processor Wind Tunnel The boxed processor ships with an active duct cooling solution called the Processor Wind Tunnel or PWT This is an optional cooling solution that is designed to meet the thermal requirements of a diverse combination of baseboards and chassis It ships with the processor in order to reduce the burden on the c
16. Datasheet Thermal Specifications This section describes the cooling requirements of the heatsink solution utilized by the boxed processor Boxed Processor Cooling Requirements The boxed processor will be directly cooled with a passive heatsink For the passive heatsink to effectively cool the boxed processor it is critical that sufficient unimpeded cool air flow over the heatsink of every processor in the system Meeting the processor s temperature specification is a function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specification is found in Chapter 6 0 It is important that system integrators perform thermal tests to verify that the boxed processor is kept below its maximum temperature specification in a specific baseboard and chassis At an absolute minimum the boxed processor heatsink will require 500 Linear Feet per Minute LFM of cool air flowing over the heatsink The airflow must be directed from the outside of the chassis directly over the processor heatsinks in a direction passing from one retention mechanism to the other It also should flow from the front to the back of the chassis Directing air over the passive heatsink of the boxed Product Name processor can be done with auxiliary chassis fans fan ducts or other techniques It is also recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The
17. L2 Power Other VCC R7 Power Other L4 Power Other R9 Power Other VCC L6 Power Other VCC R23 Power Other VCC L8 Power Other R25 Power Other VCC L24 Power Other R27 Power Other L26 Power Other VCC R29 Power Other VCC L28 Power Other R31 Power Other VCC L30 Power Other T2 Power Other VCC M1 Power Other T4 Power Other Power Other VCC T6 Power Other 5 Power Other VCC T8 Power Other VCC M7 Power Other T24 Power Other VCC M9 Power Other T26 Power Other M23 Power Other VCC T28 Power Other M25 Power Other T30 Power Other VCC M27 Power Other Power Other M29 Power Other VCC U3 Power Other M31 Power Other VCC U5 Power Other 1 Power Other VCC U7 Power Other VCC N3 Power Other U9 Power Other VCC N5 Power Other 023 Power Other 7 Power Other VCC U25 Power Other N9 Power Other 027 Power Other VCC N23 Power Other U29 Power Other VCC N25 Power Other 031 Power Other N27 Power Other VCC V2 Power Other VCC N29 Power Other V4 Power Other N31 Power Other VCC V6 Power Other VCC P2 Power Other V8 Power Other 4 Power Other VCC V24 Power Other VCC P6 Power Other VCC V26 Power Other VCC P8 Power Other V28 Power Other Datasheet 71 Intel Xeon Processor with 512 KB L2 Cache Table 38 Pin Listing by Pin Name intel Table
18. Processor with 512 KB L2 Cache ntel Note The SMBus thermal sensor and its associated thermal diode are not related to and are completely independent of the precision on die temperature sensor and thermal control circuit TCC of the Thermal Monitor feature discussed in Section 7 3 The processor SMBus implementation uses the clock and data signals of the V1 1 System Management Bus Specification It does not implement the SMBSUS signal Layout and routing guidelines are available in the appropriate platform design guidelines document For platforms which do not implement any of the SMBus features found on the processor all of the SMBus connections to the socket pins except SM_V cc may be left unconnected SM_ALERT SM_CLK SM_DAT SM_EP_A 2 0 SM_TS_A 1 0 SM_WP SM_V cc provides power to the VID generation logic in addition to supplying the SMBus and must be supplied with 3 3 volt power to assure correct setting of the processor core voltage Vcc Figure 42 Logical Schematic of SMBus Circuitry 7 4 1 104 SM_VCC SM_TS_A0 SM TS AI vcc SM_EP_AQ 0 Processor CLK A0 SM_EP_A Al EE DATA Al m SM Tema SM WP ERE Scratch EEPROM 1 Kbit each ma VSS as SM_CLK SM_DAT SM_ALERT NOTE Actual implementation may vary For use in general understanding of the architecture All SMBus pull up and pull down resistors are 10K ohms and located on the processor Proce
19. 17h 2 Processor Core Type From CPUID 4 Processor Core Family From CPUID 4 Processor Core Model From CPUID 4 Processor Core Stepping From CPUID 2 Reserved Reserved 18 19h 16 Reserved Reserved 1A 1Bh 16 Front Side Bus Speed 16 bit binary number in MHz 1Ch 2 Multiprocessor Support 00b UP 01b DP 10b RSVD 11b MP 6 Reserved Reserved 1D 1Eh 16 Maximum Core Frequency 16 bit binary number in MHz 1F 20h 16 Processor VID Voltage ID Voltage requested by VID outputs in mV 21 22h 16 Core Voltage Minimum Minimum processor DC Vcc spec in mV 23h 8 TcAse Maximum Maximum case temperature spec in C 24h 8 Checksum 1 byte checksum Cache Data 25 26h 16 Reserved Reserved 27 28h 16 L2 Cache Size 16 bit binary number in KB 105 Intel Xeon Processor with 512 KB L2 Cache Table 44 Processor Information ROM Format Page 2 of 2 Offset Section sa Function Notes 29 2Ah 16 L3 Cache Size 16 bit binary number in KB 2B 30h 48 Reserved Reserved 31h 8 Checksum 1 byte checksum Package Data 32 35h 32 Package Revision Four 8 bit ASCII characters 36h 8 Reserved Reserved 37h Checksum 1 byte checksum Part Number Data 38 3Eh 56 Processor Part Number Seven 8 bit ASCII characters 4Ch 112 Reserved Reserved 4D 54h 64 5 Electronic 64 bit identification number 55 6Eh 208 Reserved Reserved 6Fh 8 Checksum 1 byte che
20. 6 Referenced to the falling edge of TCK 7 Specification for a minimum swing defined between TAP 20 to 80 This assumes a minimum edge rate of 0 5 V nS 8 TRST must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor 9 It is recommended that TMS be asserted while TRST is being deasserted SMBus Signal Group AC Specifications Page 1 of 2 T Parameter Min Max Unit Figure Notes T70 SM CLK Frequency 10 100 KHz 1 2 3 T71 SM_CLK Period 10 100 uS 1 2 3 T72 SM_CLK High Time 4 0 N A uS T 1 2 3 T73 SM CLK Low Time 4 7 N A uS 17 1 2 3 T74 SMBus Rise Time 0 02 1 0 uS 17 1 2 3 5 T75 SMBus Fall Time 0 02 0 3 uS T 1 2 3 5 T76 SMBus Output Valid Delay 0 1 4 5 uS 18 1 2 3 T77 SMBus Input Setup Time 250 N A ns d 1 2 3 T78 SMBus Input Hold Time 300 N A ns 17 1 2 3 35 a Intel Xeon Processor with 512 KB L2 Cache ntel Table 20 SMBus Signal Group AC Specifications Page 2 of 2 2 14 36 Note T Parameter Min Max Unit Figure Notes T79 Bus Free Time 47 N A uS 7 x 80 Hold Time after Repeated Start Condition 4 0 N A uS 17 1 2 3 T81 Repeated Start Condition Setup Time 4 7 N A uS 17 1 2 3 T82 Stop Condition Setup Time 4 0 N A uS 17 1 2 3 1 2 3 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes These parameters are based on design characterization and are not tested
21. 69 Intel Xeon Processor with 512 KB L2 Cache Table 38 Pin Listing by Pin Name intel Table 38 Pin Listing by Pin Name Pin Name Pin No Direction Pin Name Pin No sitter tess Direction TESTHI4 AA7 Power Other Input E26 Power Other TESTHI5 AD5 Power Other Input VCC E28 Power Other TESTHI6 AE5 Power Other Input VCC E30 Power Other THERMTRIP F26 Async GTL Output VCC F1 Power Other TMS A25 TAP Input VCC F4 Power Other TRDY E19 Common Clk Input VCC F10 Power Other TRST F24 TAP Input VCG F16 Power Other VCC A2 Power Other VCC F22 Power Other 8 Power Other VCC F29 Power Other 14 Power Other VCC F31 Power Other VCC A18 Power Other G2 Power Other VCC A24 Power Other G4 Power Other VCC A28 Power Other VCC G6 Power Other VCC A30 Power Other G8 Power Other VCC B4 Power Other G24 Power Other B6 Power Other VCC G26 Power Other VCC B12 Power Other G28 Power Other VCC B20 Power Other G30 Power Other VCC B26 Power Other H1 Power Other 29 Power Other VCC H3 Power Other VCC B31 Power Other 5 Power Other VCC C2 Power Other VCC H7 Power Other C4 Power Other VC
22. All AC timings for the SMBus signals are referenced at or and measured at the processor pins Refer to Figure 17 Minimum time allowed between request cycles Rise time is measured from max 0 15V to 0 15 Fall time is measured from 0 9 SM_Vcc to 0 15V DC parameters are specified in Table 11 Following a write transaction an internal device write cycle time of 10ms must be allowed before starting the next transaction Processor AC Timing Waveforms The following figures are used in conjunction with the AC timing tables Table 14 through Table 20 For Figure 6 through Figure 15 the following apply 1 All common clock AC timings for signals are referenced to the Crossing Voltage Vcnoss of the BCLK 1 0 at rising edge of BCLKO All common clock AGTL signal timings are referenced at at the processor core pads All source synchronous AC timings for AGTL signals are referenced to their associated strobe address or data at GTLREF Source synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at GTLREF at the processor core pads AC timings for AGTL strobe signals are referenced to BCLK 1 0 at Vcgoss AGIL
23. Input Output B20 Power Other B21 REQ1 Input Output B22 REQ4 Common Input Output B23 VSS Power Other B24 LINTO Async GTL Input B25 PROCHOT Power Other Output B26 Power Other B27 VCCSENSE Power Other Output B28 vss Power Other B29 Power Other B30 vss Power Other B31 VCC Power Other C1 VSS Power Other C2 VCC Power Other C3 VID3 Power Other Output Datasheet intel Table 39 Pin Listing by Pin Number Intel Xeon TM Processor with 512 KB L2 Cache Table 39 Pin Listing by Pin Number Signal Pin No Pin Name Buffer Type Direction C4 VCC Power Other C5 Reserved Reserved Reserved C6 RSP Common Clk Input C7 VSS Power Other C8 5 Source Sync Input Output C9 A34 Source Sync Input Output C10 VCC Power Other C11 A30 Source Sync Input Output C12 A23 Source Sync Input Output C13 VSS Power Other C14 A16 Source Sync Input Output C15 A15 Source Sync Input Output C16 VCC Power Other C17 A8 Source Sync Input Output C18 A6 Source Sync Input Output C19 vss Power Other C20 REQ3 Common Clk Input Output C21 REQ2 Common Clk Input Output C22 VCC Power Other C23 DEFER Common Clk Input C24 TDI TAP Input C25 VSS
24. Input Output E15 vss Power Other E16 COMP1 Power Other Input E17 VSS Power Other E18 DRDY Common Input Output 77 Intel Xeon TM Processor with 512 KB L2 Cache Table 39 Pin Listing by Pin Number Signal intel Table 39 Pin Listing by Pin Number Pin No Pin Name Buffer Type Direction E19 TRDY Common Clk Input E20 VCC Power Other E21 RS0 Common Clk Input E22 HIT Common Input Output E23 VSS Power Other E24 TCK TAP Input E25 TDO TAP Output E26 VCC Power Other E27 FERR Async GTL Output E28 VCC Power Other E29 vss Power Other E30 VCC Power Other E31 vss Power Other F1 VCC Power Other F2 VSS Power Other F3 VIDO Power Other Output F4 VCC Power Other F5 BPM3 Common Clk Input Output F6 BPMO Common Input Output F7 VSS Power Other F8 BPM1 Common Clk Input Output F9 GTLREF Power Other Input F10 VCC Power Other F11 BINIT Common Input Output F12 BR1 Common Clk Input F13 VSS Power Other F14 ADSTB1 Source Sync Input Output F15 A19 Source Sync Input Output F16 VCC Power Other F17 ADSTB0 Source Sync Input Output F18 DBSY Common Clk Input Output F19 VSS Power Other F20 BNR Common Clk Input Output F
25. Table 41 Signal Definitions Page 5 of 10 Name Type Description Notes FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to volume 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note This signal does not have on die termination and must be terminated at the end agent See the appropriate Platform Design Guideline for additional information GTLREF GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3Vcc GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 o
26. The LAI is installed between the processor socket and the processor The LAI pins plug into the socket while the processor pins plug into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the Electrical Considerations The LAI will also affect the electrical performance of the front side bus therefore it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide Datasheet Datasheet Intel Xeon Processor with 512 KB L2 Cache 129
27. 3 These parameters are based on design characterization and not tested 4 Dynamic loading specifications are defined assuming a maximum duration of 11ms 5 The heatsink weight is assumed to be one pound Shock input to the system during shock testing is assumed to be 50 G s AF is the amplification factor Datasheet 4 4 Table 30 4 5 Datasheet Intel Xeon Processor with 512 KB L2 Cache Insertion Specifications The processor can be inserted and removed 15 times from a 603 pin socket meeting the 603 Pin specification is based on design Socket Design Guidelines document Note that this characterization and is not tested Mass Specifications Table 30 specifies the processors mass This includes all components which make up the entire processor product Processor Mass Processor Mass grams Intel Xeon processor with 512 KB L2 cache 25 Materials The processor is assembled from several components The basic material properties are described in Table 31 Table 31 Processor Material Properties Component Material Integrated Heat Spreader Nickel plated copper FC BGA BT Resin Interposer FR4 Interposer pins Kovar with Gold over nickel 63 Intel Xeon Processor with 512 KB L2 Cache I ntel 4 6 Markings The following section details the processor top side laser markings It is provided to aid in the identificati
28. However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction ADS yo ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must connect the appropriate pins on all front side bus agents 0 yo Address strobes are used to latch 35 3 and REQ 4 0 on their rising and falling edge 1 0 yo AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 pins A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This allows parity to be high when all the covered signals are high AP 1 0 should connect the appropriate pins of all front side bus agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 A 35 24 AP0 AP1 A 23 3 AP1 AP0 REQ 4 0 1 APO BCLK 1 0 The differential pair BCLK Bus Clock determines the bus frequency All processor front side bus agents must rece
29. Measure T se at this point geometric center of IHS Thermal grease should cover entire area of IHS Measure from edge of processor interposer 26 67 mm 1 05 in 7 26 67 mm 1 05 in m m Intef Xeon Processor with 512KB L2 Cache 35 mm x 35 mm FC BGA Core 53 34 mm x 53 34 mm interposer Figure is not to scale and is for reference only Datasheet 7 0 Intel Xeon Processor with 512 KB L2 Cache Features 7 1 Table 43 7 2 7 2 1 Datasheet Power On Configuration Options The Intel Xeon processor with 512 KB L2 cache has several configuration options that are determined by the state of specific processor pins at the active to inactive transition of the processor RESET signal These configuration options cannot be changed except by another reset Both power on and software induced resets reconfigure the processor s Power On Configuration Option Pins Configuration Option Pin Notes Output tri state SMI Execute BIST Built In Self Test INIT In Order Queue de pipelining set IOQ depth to 1 A7 Disable MCERR observation AQ Disable BINIT observation A10 APIC cluster ID 0 3 12 11 2 Disable bus parking A15 Disable Hyper Threading Technology A31 Symmetric agent arbitration ID BR 3 0 3 NOTES 1 Asserting this signal during active to inactive edge of RESET will selec
30. VSS V3 Power Other VSS AC30 Power Other VSS V5 Power Other VSS AD3 Power Other VSS V7 Power Other VSS AD9 Power Other VSS v9 Power Other VSS AD15 Power Other VSS V23 Power Other VSS AD17 Power Other VSS V25 Power Other VSS AD23 Power Other VSS V27 Power Other VSS AD31 Power Other 74 Datasheet intel Table 38 Pin Listing by Pin Name Intel Xeon TM Processor with 512 KB L2 Cache Table 38 Pin Listing by Pin Name 5 Signal Signal i Pin Name Pin No Buffer Type Direction Pin Name Pin No Buffer Type Direction VSS AE2 Power Other VSSSENSE D26 Power Other Output VSS AE11 Power Other 1 These are Reserved pins on the Intel Xeon processor In vss AE21 Power Other systems utilizing the Intel Xeon processor the system designer must terminate these signals to the processor Vcc VSS AE27 Power Other 2 Baseboard treating AA3 and AB3 as Reserved will operate VSSA AA5 Power Other Input correctly with a bus clock of 100 MHz Datasheet 75 Intel Xeon Processor with 512 KB L2 Cache 5 1 2 Pin Listing by Pin Number Table 39 Pin Listing by Pin Number Table 39 Pin Listing by Pin Number Pin No Pin Name Sutter Type Direction Al Reserved Reserved
31. falling voltage limits This specification is an absolute value 45 Intel Xeon Processor with 512 KB L2 Cache n Figure 20 BCLK 1 0 Signal Integrity Waveform 3 2 Table 22 46 Overshoot BCLK1 VH Rising Edge Ringback V MI Crossing Crossing Ringback Threshold Voltage Voltage Margin Region a gt Falling Edge Ringback BCLK0 VL Undershoot Front Side Bus Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of layout guidelines which are available in the appropriate platform design guidelines Table 22 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor pads Maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 24 through Table 27 Figure 21 shows the front side bus ringback tolerance for low to high transitions and Figure 22 shows ringback tolerance for high to low transitions Ringback Specifications for AGTL and Asynchronous GTL Buffers Maximum Ringback Notes Signal Group Transition with Input Diodes Present Unit Figure AGTL Asynch GTL LH GTLREF 0 100 GTLREF V 21 1 2 3 4 5 6 7 AGTL Asynch GTL HoL GTLREF 0 100 GTLREF V 22 1 2 3 4 5 6 7 NOTES All signal integrity specifications are measured at the processor core pads Unles
32. 10 00 10 20 ns z 1 3 T2 BCLK 1 0 Period Stability N A 150 ps 1 4 5 T3 BCLK 1 0 Pulse High Time 3 94 5 6 12 nS 7 1 T4 Tp BCLK 1 0 Pulse Low Time 3 94 5 6 12 ns 7 1 T5 BCLK 1 0 Rise Time 175 700 ps 7 1 6 T6 BCLK 1 0 Fall Time 175 700 pS 7 1 6 1 Unless otherwise noted all specifications this table apply to all processor frequencies and cache sizes Datasheet Table 15 Table 16 Datasheet Intel Xeon Processor with 512 KB L2 Cache The processor core clock frequency is derived from BCLK The period specified here is the average period A given period may vary from this specification as governed by the period stability specification T2 For the clock jitter specification refer to the CK00 Clock Synthesizer Driver Design Guidelines In this context period stability is defined as the worst case timing difference between successive crossover voltages In other words the largest absolute difference between adjacent clock periods must be less than the period stability Slew rate is measured between the 35 and 65 points of the clock swing and Vp Front Side Bus Common Clock AC Specifications T Parameter Min Max Unit Figure Notes 2 3 T10 Common Clock Output Valid Delay 0 12 1 27 ns 9 4 T11 Common Clock Input Setup Time 0 65 N A ns 9 5 T12 Common Clock Input Hold Time 0 40 N A ns 9 5 T13 RESET Pulse Width 1 00 10 00 mS T 6 7 8
33. 2 0 micrometer Ni 2 0 254 Diametric true position pin to pin Datasheet 61 Intel Xeon Processor with 512 KB L2 Cache n Figure 32 4 2 62 Table 29 Figure 32 details the flatness and tilt specifications for the IHS of the Intel Xeon processor respectively Tilt is measured with the reference datum set to the bottom of the processor interposer IHS Flatness and Tilt Drawing A LATNESS IS SPEC ED AS OVERALL NOT PER UN Processor Package Load Specifications Table 29 provides dynamic and static load specifications for the processor IHS These mechanical load limits should not be exceeded during heat sink assembly mechanical stress testing or standard drop and shipping conditions The heat sink attach solutions must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heat sink to processor thermal interface It is not recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions Package Dynamic and Static Load Specifications Parameter Max Unit Unit Static 50 Ibf 1 2 3 Dynamic 50 1 lb e hal 1 8 AF 12 45 NOTES 1 This specification applies to a uniform compressed load 2 This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface
34. 38 Pin Listing by Pin Name Pin Name Pin No Direction Pin Name Pin No sitter Direction V30 Power Other VCG AE18 Power Other VCC W1 Power Other VCC AE24 Power Other VCG W25 Power Other VCCA AB4 Power Other Input VCG W27 Power Other VCCIOPLL AD4 Power Other Input VCG W29 Power Other VCCSENSE B27 Power Other Output VCG W31 Power Other VID0 F3 Power Other Output VCG Y10 Power Other VID1 E3 Power Other Output VCG Y16 Power Other VID2 D3 Power Other Output VCG Y2 Power Other VID3 C3 Power Other Output VCC Y22 Power Other VID4 B3 Power Other Output Y30 Power Other VSS 5 1 Power Other VSS A11 Power Other 4 Power Other VSS 21 Power Other Power Other VSS A27 Power Other VCC AA12 Power Other VSS A29 Power Other VCC AA20 Power Other VSS A31 Power Other 26 Power Other VSS B2 Power Other 1 Power Other VSS 9 Power Other VCC AB2 Power Other VSS B15 Power Other VCC AB8 Power Other VSS B17 Power Other 14 Power Other VSS B23 Power Other VCC AB18 Power Other VSS B28 Power Other VCC AB24 Power Other VSS B30 Power Other VCC AB30 Power Other VSS C1 Power Other VCC AC3
35. Data Bus Signals DBI0 D 15 0 DBI1 D 31 16 DBI2 D 47 32 DBI3 D 63 48 DBSY y o DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor front side bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor front side bus agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor front side bus agents DP 3 0 yo 0 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0 and must connect the appropriate pins of all processor front side bus agents DRDY y o DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor front side bus agents DSTBN 3 0 amp y o Data strobe used to latch in D 63 0 DSTBP 3 0 Data strobe used to latch in D 63 0 Datasheet 87 Intel Xeon Processor with 512 KB L2 Cache
36. KB L2 Cache 2 5 1 Datasheet 2 DC 1 Hz fpeak 1 MHz 66 MHz fcore lt passband high frequency band NOTES 1 Diagram not to scale 2 No specifications for frequencies beyond core frequency if existent should be less than 0 05 MHz Mixing Processors Intel only supports those processor combinations operating with the same front side bus frequency core frequency VID settings and cache sizes Not all operating systems can support multiple processors with mixed frequencies Intel does not support or validate operation of processors with different cache sizes Mixing processors of different steppings but the same model as per CPUID instruction is supported and is outlined in the Intel Xeon Processor Specification Update Additional details are provided in AP 485 the Intel Processor Identification and the CPUID Instruction application note Unlike previous Intel Xeon processors the Intel Xeon processor with 512 KB L2 cache does not sample the pins IGNNE LINT OJ INTR LINT 1 NMI and A20M to establish the core to front side bus ratio Rather the processor runs at its tested frequency at initial power on If the processor needs to run at a lower core frequency as must be done when a higher speed processor is added to a system that contains a lower frequency processor the system BIOS is able to effect the change in the core to front side bus ratio 19 a I
37. Other V3 VSS Power Other V4 Power Other V5 VSS Power Other V6 VCC Power Other V7 VSS Power Other V8 VCC Power Other V9 vss Power Other V23 VSS Power Other V24 VCC Power Other V25 VSS Power Other V26 VCC Power Other V27 VSS Power Other V28 VCC Power Other 29 VSS Power Other V30 VCC Power Other V31 vss Power Other W1 VCC Power Other W2 vss Power Other W3 Reserved Reserved Reserved W4 VSS Power Other W5 BCLK1 Sys Bus Clk Input W6 TESTHIO Power Other Input W7 Power Other Input W8 TESTHI2 Power Other Input W9 GTLREF Power Other Input W23 GTLREF Power Other Input W24 vss Power Other W25 VCC Power Other W26 vss Power Other Datasheet Pin No Pin Name Type Direction W27 VCC Power Other W28 vss Power Other W29 VCC Power Other W30 vss Power Other W31 VCC Power Other Y1 VSS Power Other Y2 VCC Power Other Y3 Reserved Reserved Reserved Y4 BCLKO Sys Bus Clk Input Y5 VSS Power Other Y6 TESTHI3 Power Other Input Y7 VSS Power Other Y8 RESET Common Clk Input Y9 D62 Source Sync Input Output Y10 VCC Power Other Y11 DSTBP3 Source Sync Input Output Y12 DSTBN3 Source Sync Input Output Y13 vss Power Other Y14 DSTBP2 Source Sync Input Output Y15 DSTBN2 Source Sync Input Output Y16 VCC Power Other Y17 DSTBP1 Source Sync Input Output Y18 DSTBN1 Source Sync Input Output Y19 VSS Power Other Y20 DSTBPO Source Sync Input Outp
38. Other AC11 D43 Source Sync Input Output AC12 D41 Source Sync Input Output AC13 vss Power Other AC14 D50 Source Sync Input Output AC15 DP2 Common Input Output AC16 VCC Power Other AC17 D34 Source Sync Input Output AC18 DPO Common Input Output AC19 VSS Power Other Datasheet intel Table 39 Pin Listing by Pin Number Intel Xeon TM Processor with 512 KB L2 Cache Table 39 Pin Listing by Pin Number Signal Pin No Pin Name Buffer Type Direction AD26 VCC Power Other AD27 D4 Source Sync Input Output AD28 SM_ALERT SMBus Output AD29 SM_WP SMBus Input AD30 VCC Power Other AD31 VSS Power Other AE2 VSS Power Other VCC Power Other AE4 Reserved Reserved Reserved AE5 TESTHI6 Power Other Input AE6 SLP Async GTL Input AE7 D58 Source Sync Input Output AE8 VCC Power Other D44 Source Sync Input Output AE10 D42 Source Sync Input Output AE11 vss Power Other AE12 DBI2 Source Sync Input Output AE13 D35 Source Sync Input Output AE14 VCC Power Other AE15 Reserved Reserved Reserved AE16 Reserved Reserved Reserved AE17 DP3 Common Input Output AE18 VCC Power Other AE19 DP1 Common Input Output AE20 D28 Source Sync Input Output AE21 VSS
39. Output AA25 D3 Source Sync Input Output AA26 VCC Power Other AA27 D1 Source Sync Input Output AA28 SM_TS1_A0 SMBus Input AA29 SM_EP_AO SMBus Input AA30 VSS Power Other AA31 VCC Power Other AB1 VSS Power Other AB2 VCC Power Other AB3 BSEL1 Power Other Output AB4 VCCA Power Other Input AB5 VSS Power Other AB6 D63 Source Sync AB7 PWRGOOD Power Other Input AB8 Power Other 9 DBI3 Source Sync Input Output AB10 D55 Source Sync Input Output AB11 VSS Power Other 82 Pin No Pin Name ities Tyee Direction AB12 D51 Source Sync Input Output AB13 D52 Source Sync Input Output AB14 VCC Power Other AB15 D37 Source Sync Input Output AB16 D32 Source Sync Input Output AB17 D31 Source Sync Input Output AB18 VCC Power Other AB19 D14 Source Sync Input Output AB20 D12 Source Sync Input Output AB21 VSS Power Other AB22 D13 Source Sync Input Output AB23 D9 Source Sync Input Output AB24 VCC Power Other AB25 D8 Source Sync Input Output AB26 D7 Source Sync Input Output AB27 VSS Power Other AB28 SM_EP_A2 SMBus Input AB29 5 1 SMBus Input AB30 VCC Power Other AB31 VSS Power Other AC1 Reserved Reserved Reserved AC2 VSS Power Other AC3 VCC Power Other AC4 VCC Power Other AC5 D60 Source Sync Input Output AC6 D59 Source Sync Input Output AC7 VSS Power Other AC8 056 Source Sync Input Output 9 D47 Source Sync Input Output AC10 VCC Power
40. Page 10 of 10 Name Type Description Notes VID 4 0 VID 4 0 Voltage ID pins can be used to support automatic selection of power supply voltages Vcc Unlike previous processor generations these pins are driven by processor logic Hence the voltage supply for these pins SM Voc must be valid before the VRM supplying Vcc to the processor is enabled Conversely the VRM output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 3 for definitions of these pins The power supply must supply the voltage that is requested by these pins or disable itself VssA Vssa provides an isolated internal ground for internal PLL s Do not connect directly to ground This pin is to be connected to and VcciopLL through a discrete filter circuit NOTES 1 Intel Xeon processors only support BRO and BR1 However the Intel Xeon processors must terminate BR2 and BR3 to the processor Voc 2 For this pin on Intel XeonTM processors the maximum number of symmetric agents is one Maximum number of Central Agents is zero 3 For this pin on Intel Xeon processors the maximum number of symmetric agents is two Maximum number of Central Agents is zero 4 For this pin on Intel Xeon processors the maximum number of symmetric agents is two Maximum number of Central Agents is o
41. Power Other AE22 D27 Source Sync Input Output AE23 D22 Source Sync Input Output AE24 VCC Power Other AE25 D19 Source Sync Input Output AE26 D16 Source Sync Input Output AE27 VSS Power Other AE28 SM_Vcc Power Other AE29 SM_Vcc Power Other Pin No Pin Name Bufar Tyee Direction AC20 D25 Source Sync Input Output AC21 D26 Source Sync Input Output AC22 VCC Power Other AC23 D23 Source Sync Input Output AC24 D20 Source Sync Input Output AC25 vss Power Other AC26 D17 Source Sync Input Output AC27 DBI0 Source Sync Input Output AC28 SM_CLK SMBus Input AC29 SM_DAT SMBus Output AC30 vss Power Other AC31 VCC Power Other AD1 Reserved Reserved Reserved AD2 VCC Power Other AD3 VSS Power Other AD4 VCCIOPLL Power Other Input AD5 TESTHI5 Power Other Input AD6 Power Other AD7 D57 Source Sync Input Output AD8 D46 Source Sync Input Output AD9 VSS Power Other AD10 D45 Source Sync Input Output AD11 D40 Source Sync Input Output AD12 Power Other AD13 D38 Source Sync Input Output AD14 D39 Source Sync Input Output AD15 vss Power Other AD16 COMP0 Power Other Input AD17 vss Power Other AD18 D36 Source Sync Input Output AD19 D30 Source Sync Input Output AD20 VCC Power Other AD21 D29 Source Sync Input Output AD22 DBI1 Source Sync Input Output AD23 vss Power Other AD24 D21 Source Sync Input Output AD25 D18 Source Sync Input Output Datasheet 1 T
42. Power Other Input C26 IGNNE GTL Input C27 GTL Input C28 VCC Power Other C29 VSS Power Other C30 VCC Power Other C31 VSS Power Other D1 Power Other D2 VSS Power Other D3 VID2 Power Other Output D4 STPCLK Async GTL Input D5 VSS Power Other D6 INIT Async GTL Input D7 MCERR Common Input Output D8 VCC Power Other D9 AP1 Common Clk Input Output D10 BR3 Common Clk Input 011 VSS Power Other Datasheet Pin No Pin Name ities Tyee Direction D12 A29 Source Sync Input Output D13 A25 Source Sync Input Output D14 VCC Power Other D15 A18 Source Sync Input Output D16 A17 Source Sync Input Output D17 A9 Source Sync Input Output D18 VCC Power Other D19 ADS Input Output D20 BR0 Input Output D21 vss Power Other D22 RS1 Common Clk Input D23 BPRI Common Clk Input D24 VCC Power Other D25 Reserved Reserved Reserved D26 VSSSENSE Power Other Output D27 VSS Power Other D28 vss Power Other D29 VCC Power Other D30 VSS Power Other D31 VCC Power Other E1 VSS Power Other E2 VCC Power Other E3 VID1 Power Other Output E4 BPM5 Common Clk Input Output E5 IERR Common Clk Output E6 VCC Power Other E7 BPM2 Common Input Output E8 BPM4 Common Input Output E9 vss Power Other E10 AP0 Input Output E11 2 Common Clk Input E12 VCC Power Other E13 A28 Source Sync Input Output E14 A24 Source Sync
43. Processor with 512 KB L2 Cache Table 41 Signal Definitions Page 4 of 10 Name Type Description Notes D 63 0 y o D 63 0 Data are the data signals These signals provide 64 bit data path between the processor front side bus agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and The following table shows the grouping of data signals to strobes and DBI DSTBN DSTBP Data Group D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DBI pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high DBI 3 0 yo DBI 3 0 are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within a 16 bit group change logic level in the next cycle DBI 3 0 Assignment To Data Bus Bus Signal
44. RS1 D22 Common Clk Input GTLREF F23 Power Other Input RS2 F21 Common Clk Input GTLREF F9 Power Other Input RSP C6 Common Input HIT E22 Common Clk Input Output SKTOCC A3 Power Other Output HITM A23 Common Clk Input Output SLP AE6 Async GTL Input IERR E5 Async GTL Output SM_ALERT AD28 SMBus Output IGNNE C26 Async GTL Input SM_CLK AC28 SMBus Input INIT D6 GTL Input SM_DAT AC29 SMBus Input Output LINTO B24 GTL Input SM_EP_AO AA29 SMBus Input LINT1 G23 Async GTL Input SM EP A1 AB29 SMBus Input LOCK 17 Common Clk Input Output SM_EP_A2 AB28 SMBus Input MCERR D7 Common Clk Input Output 5 51 0 28 SMBus Input ODTEN B5 Power Other Input 5 51 1 Y29 SMBus Input PROCHOT B25 Async GTL Output SM_VCC AE28 Power Other PWRGOOD AB7 Async GTL Input SM VCC AE29 Power Other REQ0 B19 Source Sync Input Output SM_WP AD29 SMBus Input REQ1 B21 Source Syne Input Output SMI C27 Async GTL Input REQ2 C21 Source Sync Input Output STPCLK D4 Async GTL Input REQ3 C20 Source Sync Input Output TCK E24 TAP Input REQ4 B22 Source Input Output TDI C24 TAP Input Reserved Al Reserved Reserved TDO E25 TAP Output Reserved A4 Reserved Reserved TESTHIO W6 Power Other Input Reserved A15 Reserved Reserved W7 Power Other Input Reserved A16 Reserved Reserved TESTHI2 ws Power Other Input Reserved A26 Reserved Reserved TESTHIS Y6 Power Other Input Datasheet
45. RUN STOP bit is clear low then the thermal sensor enters auto conversion mode This register is accessed by using the thermal sensor Command Register The RC command register is used for read commands and the WC command register is used for write commands See Table 51 111 Intel Xeon Processor with 512 KB L2 Cache n Table 54 SMBus Thermal Sensor Configuration Register Bit Name Reset State Function Mask SM_ALERT bit Clear bit to allow interrupts via SM_ALERT and allow the thermal sensor to respond to the ARA command when an alarm is active Set the bit to disable 7 MSB 0 interrupt mode The bit is not used to clear the state of the SM_ALERT output An ARA command may not be recognized if the mask is enabled Stand by mode control bit If set the device immediately stops converting and enters stand by mode If cleared the device 6 RUN STOP 0 converts in either one shot mode or automatically updates on a timed basis 5 0 RESERVED RESERVED Reserved for future use 7 4 6 5 Conversion Rate Registers The contents of the Conversion Rate Registers determine the nominal rate at which analog to digital conversions happen when the SMBus thermal sensor is in auto convert mode There are two Conversion Rate Registers RCR for reading the conversion rate value and WCR for writing the value Table 55 shows the mapping between Conversion Rate Register values and the conversion rate As in
46. Reserved A2 Power Other A3 SKTOCC Power Other Output A4 Reserved Reserved Reserved A5 vss Power Other A6 A32 Source Sync Input Output A7 A33 Source Sync Input Output A8 VCC Power Other A9 A26 Source Sync Input Output A10 A20 Source Sync Input Output 11 VSS Power Other A12 A14 Source Sync Input Output A13 A10 Source Sync Input Output A14 VCC Power Other A15 Reserved Reserved Reserved A16 Reserved Reserved Reserved A17 LOCK Common Clk Input Output A18 VCC Power Other A19 A7 Source Sync Input Output A20 A4 Source Sync Input Output A21 vss Power Other A22 A3 Source Sync Input Output A23 HITM Common Input Output A24 VCC Power Other A25 TMS TAP Input A26 Reserved Reserved Reserved A27 vss Power Other A28 VCC Power Other A29 vss Power Other A30 VCC Power Other 1 vss Power Other B1 Reserved Reserved Reserved 76 Pin No Pin Name Direction B2 VSS Power Other B3 VID4 Power Other Output B4 VCC Power Other B5 OTDEN Power Other Input B6 VCC Power Other B7 A31 Source Sync Input Output B8 A27 Source Sync Input Output B9 vss Power Other B10 A21 Source Sync Input Output B11 A22 Source Sync Input Output B12 VCC Power Other B13 A13 Source Sync Input Output B14 A12 Source Sync Input Output B15 VSS Power Other B16 A11 Source Sync Input Output B17 vss Power Other B18 A5 Source Sync Input Output B19 REQ0 Common
47. Valid After 1 88 ns 10 1 2 3 4 Address Strobe i 5 9 1 2 3 4 T25 Tsuss Source Sync Input Setup Time 0 21 ns 10 11 6 1 2 3 4 T26 Source Sync Input Hold Time 0 21 nS 10 11 6 T27 Tsucc Source Sync Input Setup Time to 1 2 3 4 BCLK 0 65 nS 10 11 7 T28 First Address Strobe to Second Address 1 2 BCLKs 10 1 2 3 4 Strobe 10 14 33 a Intel Xeon Processor with 512 KB L2 Cache ntel 34 Table 16 Front Side Bus Source Synchronous AC Specifications Page 2 of 2 Table 17 T Parameter Min Max Unit Figure Notes T29 Tepss First Data Strobe to Sub nt TASA 4 BCLKs 11 11 12 Strobes 14 T30 Data Strobe DSTBN Output Valid Delay 8 80 10 20 ns 11 2 T31 Address Strobe Output Valid Delay 2 27 4 23 ns 10 1 2 3 4 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 Not 100 tested Specified by design characterization 3 All source synchronous AC timings are referenced to their associated strobe at GTLREF Source 8 9 synchronous data signals are referenced to the falling edge of their associated data strobe Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe All source synchronous AGTL signal timings are referenced at GTLREF at the processor core Unless otherwise noted these specificati
48. address data and associated strobes the activity factor is in reference to the strobe edge The highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe So an AF 1 indicates that the specific overshoot or undershoot waveform occurs every strobe cycle The specifications provided in Table 24 through Table 27 show the maximum pulse duration allowed for a given overshoot undershoot magnitude at a specific activity factor Each table entry is independent of all others meaning that the pulse duration reflects the existence of overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just meets the pulse duration for a specific magnitude where the AF lt 1 means that there can be no other overshoot undershoot events even of lesser magnitude note that if AF 1 then the event occurs at all times and no other events can occur NOTE 1 Activity factor for common clock AGTL signals is referenced to BCLK 1 0 frequency 2 Activity factor for source synchronous 2x signals is referenced to ADSTB 1 0 3 Activity factor for source synchronous 4x signals is referenced to DSTBP 3 0 and DSTBNJ 3 0 Reading Overshoot Undershoot Specification Tables The processor overshoot undershoot specification is not a simple single value Instead many factors are needed to determine what the overshoot undershoot specification is In addition to the magnitude
49. and Figure 44 show a mechanical representation of a boxed processor heatsink Drawings in this section reflect only the specifications on the Intel boxed processor product These dimensions should not be used as a generic keep out zone for all cooling solutions It is the system designer s responsibility to consider their proprietary cooling solution when designing to the required keep out zone on their system platform and chassis Figure 43 Mechanical Representation of the Boxed Processor Passive Heatsink for 3 Datasheet GHz processors 115 a Intel Xeon Processor with 512 KB L2 Cache ntel Figure 44 Mechanical Representation of the Boxed Processor Passive Heatsink for 2 8 2 8 2 1 8 2 2 116 2 80 GHz processors Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive heatsink and the PWT Proper clearance is required around the heatsink to ensure proper installation of the processor and unimpeded airflow for proper cooling Heatsink Dimensions The boxed processor is shipped with an unattached passive heatsink Clearance is required around the heatsink to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed Intel Xeon processor with 512KB L2 cache assembled heatsink are shown in Figure 47 Multiple Views The airflow requirements for the boxed proc
50. baseboard The power cable connector and pinouts are shown in Figure 48 and the fan cable connector requirements are detailed in Table 58 Platforms must provide a matched power header to support the boxed processor Table 59 contains specifications for the input and output signals at the fan heatsink connector The fan heatsink outputs a SENSE signal an open collector output that pulses at a rate of two pulses per fan revolution A baseboard pull up resistor provides Voy to match the baseboard mounted fan speed monitor requirements if applicable Use of the SENSE signal is optional If the SENSE signal is not used pin 3 of the connector should be tied to GND The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it The power header identification and location should be documented in the platform documentation or on the baseboard itself The baseboard power header should be positioned within 7 inches from the centre of the processor socket Figure 48 Fan Connector Electrical Pin Sequence Datasheet 121 a Intel Xeon Processor with 512 KB L2 Cache ntel PIN 3 PIN 2 PIN 1 WIRE Table 58 Fan Cable Connector Requirements Specification Connector Type Fan connector must be a straight square pin 3 pin terminal housing with polarizing ribs and friction locking ramp Match with a straight pin friction lock header on the mainboard Manufacturer and part number or equivalent
51. clock frequency and input voltages Care should be taken to read all notes associated with each parameter 25 Intel Xeon Processor with 512 KB L2 Cache 26 Intel Table 6 Voltage and Current Specifications Symbol Parameter mee Min Typ Max VID Unit Notes 1 80 GHz 1 361 1 465 1 5 V 2 3 4 11 12 2 0 GHz 1 357 1 463 1 5 V 2 3 4 11 12 Voc for Intel Xeon 2 20 GHz 1 352 1 46 1 5 V 2 3 4 11 12 Vcc processor with 2 40 GHz 1 347 Ens 1458 1 5 V 2 3 4 11 12 512 KBL2 cache 2 60 GHz 1 339 1 453 1 5 2 3 4 11 12 2 80 GHz 1 335 1 450 1 5 V 2 3 4 11 12 3 GHz 1 356 1 467 1 525 V 2 3 4 11 12 SMBus supply SM voltage All freq 3 135 3 30 3 465 V 8 1 8 GHz 424 A 4 5 2 GHz 45 3 A 4 5 for Intel Xeon 2 20 GHz 48 1 Ac 45 loc processor with 2 40 GHz 51 4 5 512 KB L2 cache 2 60 GHz 56 1 A 4 5 2 80 GHz 59 1 A 4 5 3 GHz 69 1 A 4 5 los pii lcc for PLL power teo 60 mA 9 a pins a power all freq 100 0 122 5 mA 8 lcc for GTLREF pins All 15 10 15 Icc Stop Grant Sleep All freq 25 6 Icc TCC active All freq 18 6 7 NOTES 1 Unless otherwise noted all specifications in this table apply to all processors 2 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 6 and Table
52. minimum voltage level at a receiving agent that will be interpreted as a logical high value 4 Vi is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value 5 and Vor may experience excursions above However input signal drivers must comply with the signal quality specifications in Chapter 3 0 6 Refer to the Inte Xeon Processor with 512 KB L2 Cache Signal Integrity Models for V characteristics 7 The referred to in these specifications refers to instantaneous Vcc 8 The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load 9 VoL max Of 0 450 V is guaranteed when driving into a test load as indicated in Figure 5 with Rrr enabled 10 Leakage to Vcc with Pin held at 300 mV 11 Leakage to Vss with pin held at Table 11 SMBus Signal Group DC Specifications Symbol Parameter Min Max Unit Notes 1 2 3 Vi Input Low Voltage 0 30 0 30 SM Voc V Vin Input High Voltage 0 70 SM_Vcc 3 465 V VoL Output Low Voltage 0 0 400 V loL Output Low Current N A 3 0 mA lu Input Leakage Current N A t10 pA lio Output Leakage Current N A 10 SMBus Pin Capacitance 15 0 pF 4 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 These parameters are based on design char
53. nennen nnne 36 3 0 Front Side Bus Signal Quality Specifications I 45 3 1 Front Side Bus Clock BCLK Signal Quality Specifications and Measurement Guidelines aqasha 45 3 2 Front Side Bus Signal Quality Specifications and Measurement Guidelines 46 3 3 Front Side Bus Signal Quality Specifications and Measurement Guidelines 50 4 0 Mechanical n 57 4 1 Mechanical Specifications 58 4 2 Processor Package Load 62 4 3 Insertion SPSCiHICATIONS asa erae 63 44 Mass Specifications sos 1 RE restes Rogue 63 4 5 S 63 4 6 u 64 4 7 Piti OUt 65 5 0 Pin Listing and Signal Definitions 67 5 1 Processor Pin Assignimients uuu k u 67 5 2 Signal Br e E Eaa 84 6 0 Therrmal SpecifieationS uuu uuu rete eret cut Sasak E AEEA aAa 95 6 1 Thermal amp 96 6 2 Measurements for Thermal Speci
54. returns a value with the sign bit set 1 and the data 1s 000 0000 through 111 1110 the temperature should be interpreted as 0 C Thermal Reference Register Values Temperature Register Value C binary 127 0 111 1111 126 0 111 1110 100 0 110 0100 50 0011 0010 25 0 001 1001 1 0 000 0001 0 0 000 0000 Thermal Limit Registers The SMBus thermal sensor has four Thermal Limit Registers RRHL is used to read the high limit RRLL is read for the low limit WRHL is used to write the high limit and the WRLL to write the low limit These registers allow the user to define high and low limits for the processor core thermal diode reading The encoding for these registers is the same as for the Thermal Reference Register shown in Table 52 If the processor thermal diode reading equals or exceeds one of these limits then the alarm bit RHIGH or RLOW in the Thermal Sensor Status Register is triggered Datasheet In 7 4 6 3 Intel Xeon Processor with 512 2 Cache Status Register The Status Register shown in Table 53 indicates which Gf any thermal value thresholds for the processor core thermal diode have been exceeded It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection Once set alarm bits stay set until they are cleared by a Status Register read A successful read to the Status Register will
55. specification is required to ensure reliable processor operation Datasheet E ntel Intel Xeon Processor with 512 KB L2 Cache Figure 3 Intel Xeon Processor with 512 KB L2 Cache Voltage Current VID 1 5V 1 51 1 50 1 49 1 48 1 47 1 46 1 45 1 44 Maximum Processor Voltage VDC 10 20 30 40 50 60 70 Processor Current A Datasheet 27 Intel Xeon Processor with 512 KB L2 Cache 28 intel Figure 4 Intel XeonTM Processor with 512 KB L2 Cache Voltage Current VID 1 525V 1 33 a 1 52 E i 1 51 gt 450 a 1749 E n 1 48 147 1 46 0 10 20 60 TU Processor Current Table 7 Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes Input Low 150 0 000 N A L Voltage Input High Voltage 0 660 0 710 0 850 V 7 VcRoss Absolute P Crossing Point 0 250 N A 0 550 V 7 8 2 8 V Relative 0 250 0 550 CROSS i N A V 7 8 2 3 8 9 rel Crossing Point Eu uc AV Range of N A N A 0 140 v 78 210 Crossing Points Voy Overshoot N A N A Vu 0 3 V 7 4 Vus Undershoot 0 300 N A N A 7 5 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCL
56. strobe signal timings are referenced at GTLREF at the processor core pads All AC Timing for he TAP signals are referenced to the TCK signal at 0 5 Vcc at the processor pins All TAP signal timings TMS TDI etc are referenced at the 0 5 Vcc at the processor core pads All AC timings for the SMBus signals are referenced to the SM CLK signal at 0 5 SM at the processor pins All SMBus signal timings SM DAT SM ALERTS etc are referenced at MAX OF min at the processor pins Datasheet Figure 5 Electrical Test Circuit Intel Xeon Processor with 512 KB L2 Cache Vtt Vtt Zo 50 ohms d 420mils So 169ps in Rioad AC Timings specified at pad 50 ohms Figure 6 TCK Clock Waveform CLK 156 T58 Rise Time T T57 T59 Fall Time T 55 Period V1 V2 For rise and fall times TCK is measured between 20 to 80 points on the waveform V3 TCK is referenced to 0 5 Vcc Datasheet 37 Intel Xeon Processor with 512 KB L2 Cache 38 Figure 7 Differential Clock Waveform Tph Overshoot BOK Rising Edge ice E TEENS Ringback ________________ ___ Crossing Crossing j Ringback Threshold j Voltage Voltage j Margin Region T m N _ Falling Edge Simus PYRO 5 9 es Sars gt Ringback BCLK0 VL Undershoot Tp T1 BCLK 1 0
57. the mechanical design database and are nominal dimensions with no tolerance information applied Reference Dimensions are NOT checked as part of the processor manufacturing process Unless noted as such dimensions in parentheses without tolerances are Reference Dimensions 4 Drawings are not to scale Figure 26 INT mPGA Processor Package Assembly Drawing Includes Socket This drawing is not to scale and is for reference only The 603 pin socket is supplied as a reference only 1 Integrated Heat Spreader IHS Thermal Interface Material TIM between processor die and IHS Processor die Flip Chip interconnect FCBGA Flip Chip Ball Grid Array package FCBGA solder joints Processor interposer 608 pin socket 608 pin socket solder joints O OQ G 57 a Intel Xeon Processor with 512 KB L2 Cache ntel 4 1 Mechanical Specifications Figure 27 INT mPGA Processor Package Top View Component Placement Detail Pin Al gt CPU EXE 58 Datasheet B ntel 8 Intel Xeon Processor with 512 KB L2 Cache Figure 28 INT mPGA Processor Package Drawing 30X K 31 COLUMNS 4 INTBRPOSBR INTBRPOSBR M fgg om T Table 28 INT mPGA Processor Package Dimensions Not
58. these pins to Vss to any other signal including one another can result in component malfunction or incompatibility with future processors See Chapter 5 0 for a pin listing of the processor and for the location of all Reserved pins For reliable operation unused inputs or bidirectional signals should always be connected to an appropriate signal level In a system level design on die termination has been included on the processor to allow signal termination to be accomplished by the processor silicon Most unused AGTL inputs should be left as no connects as termination is provided on the processor silicon However see Table 4 for details on AGTL signals that do not include on die termination Unused active high inputs should be connected through a resistor to ground Vgg Unused outputs can be left unconnected however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability For unused AGTL input or I O signals use pull up resistors of the same value for the on die termination resistors Rrr See Table 13 TAP Asynchronous GTL inputs and Asynchronous GTL outputs do not include on die termination Inputs and all used outputs must be terminated on the baseboard Unused outputs may be terminated on the b
59. up and pull down resistor values used for the ODTEN pin should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces For example if the trace impedance is 50 Q then a value between 40 and 60 Q should be used The processor s on die termination must be enabled for the end agent only Please refer to Table 13 for termination resistor values For more details on platform design see the appropriate platform design guidelines Valid high and low levels are determined by the input buffers via comparing with a reference voltage called GTLREF Table 13 lists the GTLREF specifications The AGTL reference voltage GTLREF should be generated on the baseboard using high precision voltage divider circuits It is important that the baseboard impedance is held to the specified tolerance and that the intrinsic trace capacitance for the signal group traces is known and well controlled For more details on platform design see the appropriate platform design guidelines Table 13 AGTL Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes GTLREF Bus Reference Voltage 2 3 Voc 2 2 3 Voc 2 3 2 V 2 3 6 Bus Reference Voltage 0 63 2 0 63 Vcc 0 63 Vcc 2 V 2 3 6 New Design Termination Resistance 36 41 46 Q 4 New Termination Resistance 45 50 55 Q 4 8 Design COMP 1 0 COMP Resistance 42 77 43 2 43 63 Q 5 7
60. voltage that is requested it must disable its voltage output For further details see the Dual Intel Xeon Processor Voltage Regulator Down VRD Design Guidelines or VRM 9 0 DC DC Converter Design Guidelines or the VRM 9 1 DC DC Converter Design Guidelines Datasheet n Intel Xeon Processor with 512 KB L2 Cache Table 3 Voltage Identification Definition Processor Pins VID4 VID3 VID2 VID1 VID0 Vcc vin V 1 1 1 1 1 VRM output off 1 1 1 1 0 1 100 1 1 1 0 1 1 125 1 1 1 0 0 1 150 1 1 0 1 1 1 175 1 1 0 1 0 1 200 1 1 0 0 1 1 225 1 1 0 0 0 1 250 1 0 1 1 1 1 275 1 0 1 1 0 1 300 1 0 1 0 1 1 325 1 0 1 0 0 1 350 1 0 0 1 1 1 375 1 0 0 1 0 1 400 1 0 0 0 1 1 425 1 0 0 0 0 1 450 0 1 1 1 1 1 475 0 1 1 1 0 1 500 0 1 1 0 1 1 525 0 1 1 0 0 1 550 0 1 0 1 1 1 575 0 1 0 1 0 1 600 0 1 0 0 1 1 625 0 1 0 0 0 1 650 0 0 1 1 1 1 675 0 0 1 1 0 1 700 0 0 1 0 1 1 725 0 0 1 0 0 1 750 0 0 0 1 1 1 775 0 0 0 1 0 1 800 0 0 0 0 1 1 825 0 0 0 0 0 1 850 2 6 1 Mixing Processors of Different Voltages Mixing processors operating with different VID settings voltages is not supported and will not be validated by Intel Datasheet 21 a Intel Xeon Processor with 512 KB L2 Cache ntel 2 7 2 8 22 Reserved Or Unused Pins All Reserved pins must remain unconnected on the system baseboard Connection of
61. with 512 KB L2 Cache 56 Datasheet Intel Xeon Processor with 512 KB L2 Cache Mechanical Specifications Note Datasheet The Intel Xeon processor with 512 KB L2 cache uses Interposer Micro Pin Grid Array INT mPGA package technology Components of the package include a flip chip ball grid array FC BGA package containing the processor die covered by an integrated heat spreader IHS mounted to a pinned FR4 interposer Mechanical specifications for the processor are given in this section See Section 1 1 for terminology definitions Figure 26 provides a basic assembly drawing and includes the components which make up the entire processor In addition to the package components several components are located on the FR4 interposer including an EEPROM and a thermal sensor Package dimensions are provided in Table 28 The Intel Xeon processor with 512 KB L2 cache utilizes a surface mount 603 pin zero insertion force ZIF socket for installation into the baseboard See the 603 Pin Socket Design Guidelines for further details on the processor socket For Figure 28 through Figure 32 the following notes apply 1 Unless otherwise specified the following drawings are dimensioned in millimeters 2 All dimensions are not tested but are guaranteed by design characterization 3 Figures and drawings labelled as Reference Dimensions are provided for informational purposes only Reference Dimensions are extracted from
62. 21 RS2 Common Clk Input F22 Power Other F23 GTLREF Power Other Input F24 TRST TAP Input F25 VSS Power Other F26 ilr Async GTL Output 78 Pin No Pin Name Type Direction F27 A20M Async GTL Input F28 VSS Power Other F29 VCC Power Other F30 VSS Power Other F31 VCC Power Other G1 VSS Power Other G2 VCC Power Other G3 VSS Power Other G4 VCC Power Other G5 VSS Power Other G6 VCC Power Other G7 VSS Power Other G8 VCC Power Other G9 VSS Power Other G23 LINT1 Async GTL Input G24 VCC Power Other G25 VSS Power Other G26 VCC Power Other G27 VSS Power Other G28 VCC Power Other G29 VSS Power Other G30 VCC Power Other 931 vss Power Other H1 VCC Power Other H2 VSS Power Other H3 VCC Power Other H4 VSS Power Other H5 VCC Power Other H6 VSS Power Other H7 Power Other H8 vss Power Other H9 VCC Power Other H23 VCC Power Other H24 VSS Power Other H25 VCC Power Other H26 VSS Power Other H27 VCC Power Other H28 VSS Power Other H29 VCC Power Other Datasheet intel Table 39 Pin Listing by Pin Number Signal Intel Xeon TM Processor with 512 KB L2 Cache Table 39 Pin Listing by Pin Number Pin No Pin Name Buffer Type Direction H30 VS
63. 3 for more information 3 The voltage specification requirements are measured across vias on the platform for the Voc sense and Vss sense Pins close to the socket with 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 milliohm minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 4 The processor should not be subjected to any static Vcc level that exceeds the Voc associated with any particular current Moreover Vcc should never exceed Vcc yip Failure to adhere to this specification can shorten the processor lifetime 5 Maximum current is defined at Vcc max 6 The current specified is also for AutoHALT State 7 The maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of PROCHOT 8 5 is required for correct operation of the processor VID logic Refer to Figure 19 for details 9 This specification applies to the PLL power pins VCCA and VCCIOPLL See Section 2 5 for details This parameter is based on design characterization and is not tested 10 This specification applies to each GTLREF pin 11 The loadlines specify voltage limits at the die measured at sense and Vss sense pins Voltage regulation feedback for voltage regulator circuits must be taken from processor Voc and Vgs pins 12 Adherence to this loadline
64. 8 Power Other VSS L5 Power Other VSS 0 Power Other VSS L7 Power Other VSS G1 Power Other VSS 19 Power Other vss G3 Power Other VSS L23 Power Other VSS G5 Power Other VSS L25 Power Other VSS G7 Power Other VSS L27 Power Other VSS G9 Power Other VSS 129 Power Other VSS G25 Power Other VSS L31 Power Other VSS G27 Power Other VSS M2 Power Other VSS G29 Power Other VSS M4 Power Other VSS G31 Power Other VSS M6 Power Other VSS H2 Power Other VSS M8 Power Other VSS H4 Power Other VSS M24 Power Other VSS H6 Power Other VSS M26 Power Other VSS H8 Power Other VSS M28 Power Other VSS H24 Power Other VSS M30 Power Other VSS H26 Power Other VSS N2 Power Other VSS H28 Power Other VSS N4 Power Other VSS H30 Power Other vss N6 Power Other vss J1 Power Other VSS N8 Power Other VSS J3 Power Other VSS N24 Power Other VSS J5 Power Other VSS N26 Power Other VSS J7 Power Other VSS N28 Power Other VSS 49 Power Other VSS N30 Power Other VSS J23 Power Other VSS 1 Power Other VSS J25 Power Other VSS P3 Power Other VSS J27 Power Other VSS P5 Power Other VSS J29 Power Other VSS P7 Power Other VSS J31 Power Other VSS P9 Power Other Datasheet 73 Intel Xeon Processor with 512 KB L2 Cache Table 38 Pin Listing by Pin Name intel Table 38 Pin Listing by Pin Name
65. 9 Example 3 3 VDC SM_Vcc Sequencing 3 3 VDC SM_VCC PWR_OK OUTEN i gt Ty 100ms VID_OUT 10 VRM PWRGD Processor gt 10ms Processor I I I PWRGOOD i I I RESET i I VID 4 0 PWRGD VRM OUTEN PWR_OK Power Supply 3 3 VDC 95 3 3 volt level 3 3 VDC SM Power Down PWROK OUTEN gt Power Down Warning gt ims ims lt T lt 10ms I PWRGOOD Processor SM VCC Datasheet Intel Xeon Processor with 512 KB L2 Cache Front Side Bus Signal Quality Specifications 3 1 Table 21 Datasheet This section documents signal quality metrics used to derive topology and routing guidelines through simulation All specifications are made at the processor core pad measurements Source synchronous data transfer requires the clean reception of data signals and their associated strobes Ringing below receiver thresholds non monotonic signal edges and excessive voltage swing will adversely affect system timings Ringback and signal non monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines Excessive signal swings overshoot and undershoot are detrimental to silicon gate oxide integrity and can cause device failure if absolute voltage limits are exceeded Additionally overshoot and undershoot can degr
66. C H9 Power Other VCC C10 Power Other 23 Power Other C16 Power Other VCC H25 Power Other VCC C22 Power Other 27 Power Other VCC C28 Power Other VCC H29 Power Other VCC C30 Power Other H31 Power Other VCC D1 Power Other VCC J2 Power Other VCC D8 Power Other J4 Power Other VCC D14 Power Other 46 Power Other VCC D18 Power Other VCC J8 Power Other VCC D24 Power Other 424 Power Other VCC D29 Power Other 426 Power Other 031 Power Other VCC J28 Power Other E2 Power Other J30 Power Other VCC E6 Power Other VCC K1 Power Other VCC E12 Power Other K3 Power Other VCC E20 Power Other K5 Power Other 70 Datasheet intel Table 38 Pin Listing by Pin Name Intel Xeon TM Processor with 512 KB L2 Cache Table 38 Pin Listing by Pin Name Pin Name Pin No A OR Direction Pin Name Pin No n RS Direction K7 Power Other VCC P24 Power Other VCC K9 Power Other VCC P26 Power Other 23 Power Other VCC P28 Power Other VCC K25 Power Other P30 Power Other 27 Power Other VCC R1 Power Other VCC K29 Power Other VCC R3 Power Other VCC K31 Power Other R5 Power Other
67. C requirements as signals however the outputs are not driven high during the logical 0 to 1 transition by the processor the major difference between GTL and Asynchronous signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the asynchronous signals are required to be asserted for at least two BCLKs in order for the processor to recognize them See Table 10 and Table 17 for the DC and AC specifications for the asynchronous signal groups SMBus signals are derived from components mounted on the processor interposer along with the processor silicon The required SM_Vcc for these signals is 3 3 volts See Section 7 4 for further details Maximum Ratings Table 5 lists the processor s maximum environmental stress ratings Functional operation at the absolute maximum and minimum is neither implied nor guaranteed The processor should not receive a clock while subjected to these conditions Functional operating parameters are listed in the AC and DC tables Extended exposure to the maximum ratings may affect device reliability Furthermore although the processor contains protective circuitry to resist damage from static electric discharge one should always take precautions to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Proces
68. EL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Xeon processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Pentium Pentium Xeon Intel Xeon and Intel NetBurst are trademark or registered trademarks of Intel Corporation or its subsidiar
69. Intel Xeon Processor with 512 KB L2 Cache at 1 80 GHz to GHz Product Features Available at 1 80 2 2 20 2 40 2 60 2 80 and 3 GHz Dual processing server workstation support Binary compatible with applications running on previous members of Intel s IA32 microprocessor line Intel NetBurst micro architecture Hyper Threading Technology Hardware support for multithreaded applications 400 MHz Front Side Bus Bandwidth up to 3 2 GB second Rapid Execution Engine Arithmetic Logic Units ALUs run at twice the processor core frequency Hyper Pipelined Technology Advance Dynamic Execution Very deep out of order execution Enhanced branch prediction Level 1 Execution Trace Cache stores 12 K micro ops and removes decoder latency from main execution loops Includes 8 KB Level 1 data cache Datasheet 512 KB Advanced Transfer L2 Cache on die full speed Level 2 cache with 8 way associativity and Error Correcting Code ECC Enables system support of up to 64 GB of physical memory Streaming SIMD Extensions 2 SSE2 144 new instructions for double precision floating point operations media video streaming and secure transactions Enhanced floating point and multimedia unit for enhanced video audio encryption and 3D performance Power Management capabilities System Management mode Multiple low power states Advanced System Management Fe
70. KB L2 Cache 54 Maximum Maximum Pulse Pulse Pulse Overshoot Undershoot oe aay M V V 1 80 0 320 0 06 0 58 5 77 1 75 0 270 0 12 1 25 12 49 1 70 0 220 0 35 3 50 20 00 1 65 0 170 1 01 10 12 20 00 1 60 0 120 3 04 20 00 20 00 1 55 0 07 10 16 20 00 20 00 NOTES 1 These specifications are measured at the processor pad 2 BCLK period is 10 nS 3 WIRED OR processor signals can tolerate upto 1 V of overshoot undershoot 4 AF is referenced to BCLK 1 0 Tolerance Maximum Maximum Pulse Pulse Pulse Overshoot Undershoot aN V V 1 80 0 320 0 17 1 73 17 30 1 75 0 270 0 37 3 75 37 48 1 70 0 220 1 05 10 51 60 00 1 65 0 170 3 04 30 37 60 00 1 60 0 120 9 13 60 00 60 00 1 55 0 07 30 48 60 00 60 00 NOTES 1 These specifications are measured at the processor pad 2 These signals are assumed in a 33 MHz time domain Table 26 Common Clock 100 MHz AGTL Signal Group Overshoot Undershoot Tolerance Table 27 Asynchronous GTL PWRGOOD and TAP Signal Groups Overshoot Undershoot Datasheet Intel Xeon Processor with 512 KB L2 Cache Figure 25 Maximum Acceptable Overshoot Undershoot Waveform Datasheet Maximum Absolute Overshoot Time dependent Overshoot Time dependent Maximum Undershoot Absolute Undershoot 000588 55 Intel Xeon Processor
71. KO equals the falling edge of BCLK1 3 is the statistical average of the measured by the oscilloscope Datasheet Intel Xeon Processor with 512 KB L2 Cache Overshoot is defined as the absolute value of the maximum voltage Undershoot is defined as the absolute value of the minimum voltage Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches It includes input threshold hysteresis The crossing point must meet the absolute and relative crossing point specifications simultaneously be measured directly using Vtop Agilent scopes High Tektronix scopes 10 AVcnoss is defined as the total variation of all crossing voltages as defined in note 2 Table 8 AGTL Signal Group DC Specifications Symbol Parameter Min Max Unit new Vin Input High Voltage 1 10 GTLREF Voc V 2 4 6 Vit Input Low Voltage 0 0 0 90 GTLREF V 3 6 Vou Output High Voltage N A Voc V 4 6 Voc lo Output Low Current N A 0 50 Rrr min RoN min mA 6 50 Pin Leakage High N A 100 9 lLo Pin Leakage Low N A 500 8 Ron Buffer On Resistance 7 11 Q 5 7 NOTES Unless otherwise noted all specif
72. NT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state HALT Grant Snoop State State 4 The processor will respond to snoop transactions on the front side bus while in Stop Grant state or in AutoHALT Power Down state During a snoop transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus After the snoop is serviced the processor will return to the Stop Grant state or AutoHALT Power Down state as appropriate Sleep State State 5 The Sleep state is a very low power state in which each processor maintains its context maintains the phase locked loop PLL and has stopped most of internal clocks The Sleep state can only be entered from Stop Grant state Once in the Stop Grant state the SLP pin can be asserted causing the processor to enter the Sleep state The SLP pin is not recognized in the Normal or AutoHALT states Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior 101 a Intel Xeon Processor with 512 KB L2 Cache ntel 7 2 6 7 3 102 In the Sleep state the processor is incapable of responding to snoop transactions or latching interrup
73. Pin Listing and Signal Definitions 5 1 5 1 1 Processor Pin Assignments Section 2 8 contains the front side bus signal groups in Table 4 for the Intel Xeon processor with 512 KB L2 cache This section provides a sorted pin list in Table 38 and Table 39 Table 38 is a listing of all processor pins ordered alphabetically by pin name Table 39 is a listing of all processor pins ordered by pin number Pin Listing by Pin Name Table 38 Pin Listing by Pin Name Table 38 Pin Listing by Pin Name Pin Name Pin No te Direction A3 A22 Source Sync Input Output A4 A20 Source Sync Input Output Abit B18 Source Sync Input Output A6 C18 Source Sync Input Output A7 A19 Source Sync Input Output A8 C17 Source Sync Input Output A9 D17 Source Sync Input Output A10 A13 Source Sync Input Output A11 B16 Source Sync Input Output A12 B14 Source Sync Input Output A13 B13 Source Sync Input Output A14 A12 Source Sync Input Output A15 C15 Source Sync Input Output A16 C14 Source Sync Input Output A17 D16 Source Sync Input Output A18 D15 Source Sync Input Output A19 F15 Source Sync Input Output A20 A10 Source Sync Input Output A21 B10 Source Sync Input Output A22 B11 Source Sync Input Output A23 C12 Source Sync Input Outpu
74. Power Other M27 VCC Power Other M28 VSS Power Other M29 VCC Power Other M30 VSS Power Other M31 VCC Power Other N1 VCC Power Other N2 vss Power Other N3 VCC Power Other N4 vss Power Other 79 Intel Xeon TM Processor with 512 KB L2 Cache Table 39 Pin Listing by Pin Number Signal intel Table 39 Pin Listing by Pin Number Pin No Pin Name Buffer Type Direction N5 VCC Power Other N6 vss Power Other N7 VCC Power Other N8 vss Power Other N9 VCC Power Other N23 VCC Power Other N24 vss Power Other N25 VCC Power Other N26 VSS Power Other N27 Power Other N28 VSS Power Other N29 VCC Power Other N30 VSS Power Other N31 Power Other P1 VSS Power Other P2 Power Other P3 vss Power Other P4 VCC Power Other P5 vss Power Other P6 VCC Power Other P7 VSS Power Other P8 VCC Power Other P9 vss Power Other P23 vss Power Other P24 VCC Power Other P25 VSS Power Other P26 VCC Power Other P27 vss Power Other P28 VCC Power Other P29 vss Power Other P30 VCC Power Other P31 vss Power Other R1 VCC Power Other R2 vss Power Other R3 VCC Power Other R4 VSS Power Other R5 VCC Power Other R6 vss Power Other R7 VCC Power Other 80 Pin No Pi
75. Power Other VSS C7 Power Other VCC AC4 Power Other VSS C13 Power Other VCC AC10 Power Other VSS C19 Power Other VCC AC16 Power Other VSS C25 Power Other 22 Power Other VSS C29 Power Other AC31 Power Other VSS C31 Power Other VCC AD2 Power Other VSS D2 Power Other VCC AD6 Power Other vss D5 Power Other AD12 Power Other VSS D11 Power Other AD20 Power Other VSS D21 Power Other AD26 Power Other vss D27 Power Other VCC AD30 Power Other VSS D28 Power Other VCC AE3 Power Other VSS D30 Power Other VCC AE8 Power Other VSS E1 Power Other VCC AE14 Power Other VSS E9 Power Other 72 Datasheet C ntel Intel Xeon TM Processor with 512 12 Cache Table 38 Pin Listing by Pin Name Table 38 Pin Listing by Pin Name Pin Name Pin No i cns Direction Pin Name Pin No BR I Direction vss E15 Power Other VSS K2 Power Other VSS E17 Power Other VSS K4 Power Other VSS E23 Power Other VSS K6 Power Other VSS E29 Power Other VSS K8 Power Other VSS E31 Power Other VSS K24 Power Other VSS F2 Power Other VSS K26 Power Other VSS F7 Power Other VSS K28 Power Other VSS F13 Power Other VSS K30 Power Other VSS F19 Power Other VSS L1 Power Other vss F25 Power Other VSS L3 Power Other VSS F2
76. S Power Other H31 VCC Power Other J1 VSS Power Other J2 Power Other J3 VSS Power Other J4 VCC Power Other J5 VSS Power Other J6 VCC Power Other J7 VSS Power Other J8 VCC Power Other J9 VSS Power Other J23 VSS Power Other J24 Power Other J25 VSS Power Other J26 Power Other J27 VSS Power Other J28 Power Other J29 VSS Power Other J30 VCC Power Other J31 VSS Power Other K1 VCC Power Other K2 VSS Power Other K3 VCC Power Other K4 VSS Power Other K5 VCC Power Other K6 VSS Power Other K7 VCC Power Other K8 VSS Power Other K9 VCC Power Other K23 Power Other K24 VSS Power Other K25 VCC Power Other K26 vss Power Other K27 VCC Power Other K28 vss Power Other K29 VCC Power Other K30 vss Power Other K31 VCC Power Other L1 vss Power Other Datasheet Pin No Pin Name Bufar Type Direction L2 VCC Power Other L3 VSS Power Other L4 VCC Power Other L5 VSS Power Other L6 VCC Power Other L7 VSS Power Other L8 VCC Power Other 19 vss Power Other L23 vss Power Other L24 VCC Power Other L25 VSS Power Other L26 VCC Power Other L27 VSS Power Other L28 VCC Power Other L29 vss Power Other L30 VCC Power Other L31 VSS Power Other M1 VCC Power Other M2 VSS Power Other M3 VCC Power Other M4 VSS Power Other M5 VCC Power Other M6 VSS Power Other M7 VCC Power Other M8 VSS Power Other Mg VCC Power Other M23 VCC Power Other M24 VSS Power Other M25 VCC Power Other M26 VSS
77. Section 7 1 and the appropriate Platform Design Guidelines These signals do not have on die termination Refer to corresponding Platform Design Guidelines for termination requirements Note that Reset initialization function of these pins is now a software function on the Intel Xeon processor with 512 KB L2 cache The value of these pins during the active to inactive edge of RESET to determine processor configuration options See Section 7 1 for details These signals may be driven simultaneously by multiple agents wired or These signals are not terminated by the processor s on die termination However some signals in this group include termination on the processor interposer See Section 7 4 for details 23 a Intel Xeon Processor with 512 KB L2 Cache ntel 2 9 2 10 24 Table 5 9 SM Vcc is required for correct VID logic operation of the Intel Xeon processor with 512 KB L2 cache Refer to Figure 19 for details Asynchronous GTL Signals The Intel Xeon processor with 512 KB L2 cache does not utilize CMOS voltage levels on any signals that connect to the processor silicon As a result legacy input signals such as A20Mff IGNNE INIT LINTO INTR LINTI NMI SMI SLP and STPCLK utilize GTL input buffers Legacy output FERR PBE and other non AGTL signals IERR THERMTRIP and PROCHOT utilize GTL output buffers All of these asynchronous GTL signals follow the same D
78. Sequencing on page 44 for further details WP Write Protect can be used to write protect the Scratch EEPROM The Scratch SM WP EEPROM is write protected when this input is pulled high to SM processor includes a 10 KQ pull down resistor to Vss for this signal SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is SMI l issued and the processor begins program execution from the SMM handler 3 If SMI is asserted during the deassertion of RESET the processor will tri state its outputs STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the front STPCLK side bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provide
79. a bus stall the current bus owner cannot issue any new transactions BNR yo Since multiple agents might need to request a bus stall at the same time BNR is a wire OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges 5 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 5 0 should connect the appropriate pins of all front side bus agents BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a processor output used by debug tools to determine processor debug readiness BPM5 provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors 5 4 must be bussed to all bus agents These signals do not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information 5 0 VO BPRI Bus Priority Request is used to arbitrate for ownership of the processor front side bus It must connect the appropriate pins of all processor front side bus agents Ob
80. acterization and are not tested 3 All DC specifications for the SMBus signal group are measured at the processor pins 4 Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals Datasheet E ntel Intel Xeon Processor with 512 KB L2 Cache Table 12 BSEL 1 0 and VID 4 0 DC Specifications Symbol Parameter Min Max Unit Notes Buffer On Ron BSEL 9 2 14 3 Q 2 Ron Buffer On VID Resistance 17 12 9 Pin Leakage Hi N A 100 3 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 These parameters are not tested and are based on design simulations 3 Leakage to Vss with pin held at 2 50V 2 12 AGTL Front Side Bus Specifications Routing topologies are dependent on the number of processors supported and the chipset used in the design Please refer to the appropriate platform design guidelines In most cases termination resistors are not required as these are integrated into the processor See Table 4 for details on which AGTL signals do not include on die termination The termination resistors are enabled or disabled through the ODTEN pin To enable termination this pin should be pulled up to through a resistor and to disable termination this pin should be pulled down to Vss through a resistor For optimum noise margin all pull
81. ade timing due to the build up of inter symbol interference ISI effects For these reasons it is crucial that the designer assure acceptable signal quality across all systematic variations encountered in volume manufacturing Specifications for signal quality are for measurements at the processor core only and are only observable through simulation The same is true for all front side bus AC timing specifications in Section 2 13 Therefore proper simulation of the processor front side bus is the only means to verify proper timing and signal quality metrics Front Side Bus Clock BCLK Signal Quality Specifications and Measurement Guidelines Table 21 describes the signal quality specifications at the processor pads for the processor front side bus clock BCLK signals Figure 20 describes the signal quality waveform for the front side bus clock at the processor pads BCLK Signal Quality Specifications Parameter Min Max Unit Figure Notes BCLK 1 0 Overshoot N A 0 30 V 20 1 BCLK 1 0 Undershoot N A 0 30 V 20 1 BCLK 1 0 Ringback Margin 0 20 N A V 20 1 BCLK 1 0 Threshold Region N A 0 10 V 20 1 2 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 The rising and falling edge ringback voltage specified is the minimum rising or maximum falling absolute voltage the BCLK signal can dip back to after passing the rising or
82. air passing directly over the processor heatsink should not be preheated by other system components such as another processor and should be kept at or below 45 C Again meeting the processor s temperature specification is the responsibility of the system integrator The processor temperature specification is found in Chapter 6 0 127 Intel Xeon Processor with 512 KB L2 Cache ntel 9 0 Debug Tools Specifications 9 1 9 1 1 128 The Debug Port design information has been moved This includes all information necessary to develop a Debug Port on this platform including electrical specifications mechanical requirements and all In Target Probe ITP signal layout guidelines Please reference the TP700 Debug Port Design Guide for the design of your platform Logic Analyzer Interface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging systems Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of systems the LAI is critical in providing the ability to probe and capture front side bus signals There are two sets of considerations to keep in mind when designing a system that can make use of an LAI mechanical and electrical Mechanical Considerations
83. als of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK y o LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor front side bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor front side bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock MCERR y o MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor front side bus agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by
84. and 11 x Made PWRGOOD updates Addition of 2 60 and 2 80 GHz Data September 2002 004 Updated Thermal Requirements Updated Thermal Requirements September 2002 005 Updated Table 6 7 Added Table 12 Added 3 GHz information Edited definitions with current terminology February 2003 006 Added two TDP loadline figures in chapter 6 Added notes to signal definition tables for symmetric agents Changed text figures and tables for the boxed processor section Datasheet Datasheet Intel Xeon Processor with 512 KB L2 Cache Introduction Datasheet The Intel Xeon processor with 512 KB L2 cache is based on the Intel NetBurst micro architecture which operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA 32 processors While based on the Intel NetBurst micro architecture it maintains the tradition of compatibility with IA 32 software The Intel NetBurst micro architecture features begin with innovative techniques that enhance processor execution such as Hyper Pipelined Technology a Rapid Execution Engine Advanced Dynamic Execution enhanced Floating Point and Multimedia unit and Streaming SIMD Extensions 2 SSE2 The Hyper Pipelined Technology doubles the pipeline depth in the processor allowing the processor to reach much higher core frequencies The Rapid Execution Engine allows the two integer ALUs in the processor to
85. any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide Since multiple agents may drive this signal at the same time MCERR is a wire OR signal which must connect the appropriate pins of all processor front side bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers MCERR is activated on specific clock edges and sampled on specific clock edges ODTEN ODTEN On die termination enable should be connected to Vcc to enable on die termination for end bus agents For middle bus agents pull this signal down via a resistor to ground to disable on die termination Whenever ODTEN is high on die termination will be active regardless of other states of the bus PROCHOT PROCHOT processor hot indicates that the processor Thermal Control Circuit TCC has been activated Under most conditions PROCHOT will go active when the processor s thermal sensor detects that the processor has reached its maximum safe operating temperature See Section 7 3 for more details These signals do not have on die termination and must be terminated at the end agent See the appropriate Platform Design Guideline for additional information Datasheet 89 Intel Xeon Processor with 512 KB L2 Cache Table 41 Signal Definitio
86. aseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the ITP700 Debug Port Design Guide All TESTHI 6 0 pins should be individually connected to Vcc via a pull up resistor which matches the trace impedance within 10 Q TESTHI 3 0 and TESTHI 6 5 may all be tied together and pulled up to Vcc with a single resistor if desired However utilization of boundary scan test will not be functional if these pins are connected together TESTHI4 must always be pulled up independently from the other TESTHI pins For optimum noise margin all pull up resistor values used for TESTHI 6 0 pins should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces For example if the trace impedance is 50 Q then a pull up resistor value between 40 and 60 should be used The TESTHI 6 0 termination recommendations provided in the Intel Xeon Processor Datasheet are also suitable for the Intel Xeon processor with 512 KB L2 cache However Intel recommends new designs or designs undergoing design updates follow the trace impedance matching termination guidelines outlined in this section Front Side Bus Signal Groups In order to simplify the following discussion the front side bus signals have been combined into groups by buffer type AGTL
87. asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all front side bus agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset See the appropriate Platform Design Guideline for additional information Voca VCCA provides isolated power for the analog portion of the internal PLL s Use a discrete RLC filter to provide clean power Use the filter defined in Section 2 5 to provide clean power to the PLL The tolerance and total ESR for the filter is important Refer to the appropriate platform design guidelines for complete implementation details VccioPLL VociopLL provides isolated power for digital portion of the internal PLL s Follow the guidelines for Section 2 5 and refer to the appropriate platform design guidelines for complete implementation details VGCSENSE VsssENSE The Vccsense and Vsssense pins are the points for which processor minimum and maximum voltage requirements are specified Uniprocessor designs may utilize these pins for voltage sensing for the processor s voltage regulator However multi processor designs must not connect these pins to sense logic but rather utilize them for power delivery validation 92 Datasheet Intel Intel Xeon TM Processor with 512 KB L2 Cache Table 41 Signal Definitions
88. ation of THERMTRIP Thermal Trip indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through internal thermal sensor which is configured to trip at approximately 135 C To properly protect the processor power must be removed upon THERMTRIP becoming active See Figure 16 and Table 20 for the appropriate power down sequence and timing requirement In parallel the processor will attempt to reduce its temperature by shutting off internal clocks and stopping all program execution Once activated THERMTRIP remains latched and the processor will be stopped until RESET is asserted A RESET pulse will reset the processor and execution will begin at the boot vector If the temperature has not dropped below the trip level the processor will assert THERMTRIP and return to the shutdown state The processor releases THERMTRIP when is activated even if the processor is still too hot This signal do not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information TMS TMS Test Mode Select is a JTAG specification support signal used by debug tools This signal does not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information TRDY TRDY Target Ready is
89. atures System Management Bus Processor Information ROM PIROM OEM Scratch EEPROM Thermal Monitor Machine Check Architecture MCA The Intel Xeon processor with 512 KB L2 cache is designed for high performance dual processor workstation and server applications Based on the Intel NetBurst micro architecture and the new Hyper Threading Technology it is binary compatible with previous Intel Architecture 32 processors The Intel Xeon processor with 512 KB L2 cache is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP Windows 2000 Linux and UNIX The Intel Xeon processor with 512 L2 cache delivers compute power at unparalleled value and flexibility for powerful workstations internet infrastructure and departmental server applications The Intel NetBurst micro architecture and Hyper Threading Technology deliver outstanding performance and headroom for peak internet server workloads resulting in faster response times support for more users and improved scalability Order Number 298642 006 March 2003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INT
90. cksum Thermal Ref Data 70h 8 Thermal Reference Byte See Section 7 4 4 for details 71 72h 16 Reserved Reserved 73h 8 Checksum 1 byte checksum Feature Data 74 77h 32 io Gorg Feature From CPUID function 1 EDX contents 7 Reserved 6 Serial Signature 5 Electronic Signature Present Tam Processor Feature Flags Thermal Sense Prose 2 OEM EEPROM Present 1 Core VID Present 0 L3 Cache Present 79 7Bh 24 Reserved 7Ch 8 Reserved Reserved 7Dh 8 Checksum 1 byte checksum Other Data 7Fh 16 Reserved Reserved 106 Datasheet Intel 7 4 2 7 4 3 Table 45 Table 46 7 4 4 Datasheet Intel Xeon Processor with 512 KB L2 Cache Scratch EEPROM Also available in the memory component on the processor SMBus is an EEPROM which may be used for other data at the system or processor vendor s discretion The data in this EEPROM once programmed can be write protected by asserting the active high SM_WP signal This signal has a weak pull down 10 kW to allow the EEPROM to be programmed in systems with no implementation of this signal The Scratch EEPROM resides in the upper half of the memory component addresses 80 FFh The lower half comprises the Processor Information ROM address 00 7Fh which is permanently write protected by Intel PIROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM PIR responds to two SMBus packet types Read Byt
91. clear any alarm bits that may have been set unless the alarm condition persists If the SM_ALERT signal is enabled via the Thermal Sensor Configuration Register and a thermal diode threshold is exceeded an alert will be sent to the platform via the SM_ALERT signal This register is read by accessing the RS Command Register Table 53 SMBus Thermal Sensor Status Register 7 4 6 4 Datasheet Bit Name Reset State Function 7 MSB BUSY N A be indicates that the device s analog to digital converter is 6 RESERVED RESERVED Reserved for future use 5 RESERVED RESERVED Reserved for future use If set indicates the processor core thermal diode high RHIGH o temperature alarm has activated If set indicates the processor core thermal diode low 3 REOW 0 temperature alarm has activated 2 OPEN 0 If set indicates an open fault in the connection to the processor core diode 1 RESERVED RESERVED Reserved for future use 0 LSB RESERVED RESERVED Reserved for future use Configuration Register The Configuration Register controls the operating mode stand by vs auto convert of the SMBus thermal sensor Table 54 shows the format of the Configuration Register If the RUN STOP bit is set high then the thermal sensor immediately stops converting and enters stand by mode The thermal sensor will still perform analog to digital conversions in stand by mode when it receives a one shot command If the
92. d PLL Filter Veca and are power sources required by the processor PLL clock generator This requirement is identical to that of the Intel Xeon processor Since these PLLs are analog in nature they require quiet power supplies for minimum jitter Jitter is detrimental to the system it degrades external I O timings as well as internal core timings i e maximum frequency To prevent this degradation these supplies must be low pass filtered from A typical filter topology is shown in Figure 1 17 a Intel Xeon Processor with 512 KB L2 Cache ntel The AC low pass requirements with input at Vcc and output measured across the capacitor C4 or in Figure 1 is as follows 02 dB gain in pass band 0 5 dB attenuation in pass band lt 1 Hz see DC drop in next set of requirements gt 34dB attenuation from 1 MHz to 66 MHz 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 2 For recommendations on implementing the filter refer to the appropriate platform design guidelines Figure 1 Typical Veciopit VccA and Power Distribution Trace 0 02 Q VCC 11 12 a Processor interposer pin R Socket WEE Baseboard via that connects R Socket filter to VCC plane Socket pin Processor VSSA C P Socket L1 L2 Datasheet ntel Intel Xeon Processor with 512
93. d all specifications in this table apply to all processor frequencies and cache sizes All outputs are open drain 29 Intel Xeon Processor with 512 KB L2 Cache n 30 Table 10 TAP signal group must meet the system signal quality specification in Chapter 3 0 Refer to the Inte Xeon Processor with 512 L2 Cache Signal Integrity Models tor V V characteristics The Vcc referred to in these specifications refers to instantaneous Vcc The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load VoL max Of 0 300V is guaranteed when driving a test load represents the amount of hysteresis nominally centered about 0 5 Vcc for all TAP inputs Leakage to with Pin held at 300 mV 10 Leakage to with pin held at Vcc ow Asynchronous GTL Signal Group DC Specifications Symbol Parameter Min Max Unit Notes Vin Input High Voltage 1 10 GTLREF Voc V 3 5 7 Vit Input Low Voltage 0 0 0 90 GTLREF V 4 6 Vou Output High Voltage N A Vcc V 2 5 7 loL Output Low Current 50 mA 8 9 lui Pin Leakage High N A 100 11 lio Pin Leakage Low N A 500 10 RoN Buffer On Resistance 7 11 Q 6 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 All outputs are open drain 3 is defined as the
94. dicated in Table 51 the Conversion Rate Register is set to its default state of 02h 0 25 Hz nominally when the thermal sensor is powered up There is a 30 error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate Table 55 SMBus Thermal Sensor Conversion Rate Registers Register Value Conversion Rate Hz 00h 0 0625 01h 0 125 02h 0 25 03h 0 5 04h 1 0 05h 2 0 06h 4 0 07h 8 0 08h to FFh Reserved for future use 7 4 7 SMBus Thermal Sensor Alert Interrupt The SMBus thermal sensor located on the processor includes the ability to interrupt the SMBus when a fault condition exists The fault conditions consist of 1 a processor thermal diode value measurement that exceeds a user defined high or low threshold programmed into the Command Register or 2 disconnection of the processor thermal diode from the thermal sensor The interrupt can be enabled and disabled via the thermal sensor Configuration Register and is delivered to the baseboard via the SM ALERT open drain output Once latched the SM ALERT should only be cleared by reading the Alert Response byte from the Alert Response Address of the thermal sensor The Alert Response Address is a special slave address shown in Table 50 The SM_ALERT will 112 Datasheet 7 4 8 Datasheet Intel Xeon Processor with 512 KB L2 Cache be cleared once the SMBus master device first reads the s
95. e the Intel Xeon processor with 512 KB L2 cache includes a groundbreaking new technology called Hyper Threading technology which enables multi threaded software to execute tasks in parallel within the processor resulting in a more efficient simultaneous use of processor resources Server applications can realize increased performance from Hyper Threading technology today while workstation applications are expected to benefit from Hyper Threading technology in the future through software and processor evolution The combination of Intel NetBurst micro architecture and Hyper Threading technology delivers outstanding performance throughput and headroom for peak software workloads resulting in faster response times and improved scalability The Intel Xeon processor with 512 KB L2 cache is intended for high performance workstation and server systems with up to two processors on a single bus The processor supports both uni and dual processor designs and includes manageability features Components of the manageability features include an OEM EEPROM and Processor Information ROM that are accessible through a SMBus interface The Processor Information ROM includes information that is relevant to the particular processor and system in which it is installed The Intel Xeon processor with 512 KB L2 cache is packaged in a 603 pin interposer micro PGA INT mPGA package and utilizes a surface mount ZIF socket with 603 pins Mechanical components used for attac
96. e System Compatibility 298645 Intel Xeon Processor with 512 KB L2 Cache Signal Integrity Models http developer intel com2 Intel Xeon Processor with 512 KB L2 Cache Mechanical Models in ProE Format http developer intel com Intel Xeon Processor with 512 KB L2 Cache Mechanical Models in IGES Format http developer intel com Intel Xeon Processor with 512 KB L2 Cache Thermal Models FloTherm ICEPAK format http developer intel com Intel Xeon Processor with 512 KB L2 Cache Core Boundary Scan Descriptor Language BSDL Model http developer intel com System Management Bus Specification rev 1 1 http Awww sbs forum org smbus Wired for Management 2 0 Design Guide http developer intel com Boxed Integration Notes http support intel com support processors xeon NOTES 1 Contact your Intel representative for the latest revision of documents without order numbers 2 The signal integrity models are in IBIS format Datasheet E ntel Intel Xeon Processor with 512 KB L2 Cache 2 0 Electrical Specifications 2 1 Note 2 2 2 3 Datasheet Front Side Bus and GTLREF Most Intel Xeon processor with 512 KB L2 cache front side bus signals use Assisted Gunning Transceiver Logic AGTL signaling technology This signaling technology provides improved noise margins and reduced ringing through low voltage sw
97. e and Write Byte However since the PIR is write protected it will acknowledge a Write Byte command but ignore the data The Scratch EEPROM responds to Read Byte and Write Byte commands Table 45 diagrams the Read Byte command Table 46 diagrams the Write Byte command Following a write cycle to the scratch ROM software must allow a minimum of 10ms before accessing either ROM of the processor In the tables 5 represents the SMBus start bit P represents a stop bit represents a read bit W represents a write bit represents an acknowledge ACK and represents a negative acknowledge NACK The shaded bits are transmitted by the Processor Information ROM or Scratch EEPROM and the bits that aren t shaded are transmitted by the SMBus host controller In the tables the data addresses indicate 8 bits The SMBus host controller should transmit 8 bits with the most significant bit indicating which section of the EEPROM is to be addressed the Processor Information ROM MSB 0 or the Scratch EEPROM MSB 1 Read Byte SMBus Packet Slave Command Slave Rea s Address vis A Code A s Address d A Dal III 1 7 bits 1 1 8 bits 1 1 7 bits 1 1 8bits 1 1 Write Byte SMBus Packet S Write A Command Code A Data P 1 7 bits 1 1 8 bits 1 8 bits 1 1 SMBus Thermal Sensor The processor s SMBus thermal sensor provides a mea
98. e for BSEL 1 0 17 3 Voltage Identification Definition 21 4 Front Side Bus Signal Groups 23 5 Processor Absolute Maximum 24 6 Voltage and Current Specifications n 26 7 Front Side Bus Differential Specifications 28 8 AGTL Signal Group DC Specifications a 29 9 and PWRGOOD Signal Group DC 29 10 Asynchronous GTL Signal Group DC 30 11 SMBus Signal Group DC Specifications 30 12 BSEL 1 0 and VID 4 0 DC Specifications 31 13 AGTL Bus Voltage A nnne 31 14 Front Side Bus Differential Clock Specifications 32 15 Front Side Bus Common Clock AC 33 16 Front Side Bus Source Synchronous AC Specifications 2 33 17 Miscellaneous Signals AC Specifications nennen 34 18 Front Side Bus AC Specifications Reset 35 19 Signal G
99. e processor dependent addresses for the thermal sensor Table 57 Memory Device SMBus Addressing gg Peu Device Select R W SM A2 SM 1 SM 0 bits 7 4 bit 3 bit 2 bit 1 bit 0 AOh A1h 1010 0 0 0 X A2h A3h 1010 0 0 1 X A4h A5h 1010 0 1 0 X A6h A7h 1010 0 1 1 X A8h A9h 1010 1 0 0 X AAh ABh 1010 1 0 1 X ACh ADh 1010 1 1 0 X AEh AFh 1010 1 1 1 X NOTES 1 This addressing scheme will support up to 8 processors a single SMBus Datasheet I ntel Intel Xeon Processor with 512 KB L2 Cache 8 0 Boxed Processor Specifications 8 1 Note Introduction The Intel Xeon processor with 512 KB L2 cache is also offered as an Intel boxed processor Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The boxed processor is supplied with an unattached passive heatsink It also contains an optional active duct solution called Processor Wind Tunnel PWT to provide adequate airflow across the heatsink If the chassis or baseboard used contains an alternate cooling solution that has been thermally validated the PWT may be discarded This chapter documents baseboard and platform requirements for the cooling solution that is supplied with the boxed processor This chapter is particularly important for OEM s that manufacture baseboards and chassis for integrators Figure 43
100. easserted once the processor is in the Stop Grant state Both logical processors of the Intel Xeon processor with 512 KB L2 cache must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vcc for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will be recognized while the processor is in Stop Grant state If STPCLK is still asserted at the completion of the BINIT bus initialization the processor will remain in Stop Grant mode If the STPCLK is not asserted at the completion of the BINIT bus initialization the processor will return to Normal state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the deassertion of the STPCLK signal When re entering the Stop Grant state from the sleep state STPCLK should only be deasserted one or more bus clocks after the deassertion of SLP A transition to the HALT Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 A transition to the Sleep state see Section 7 2 5 will occur with the assertion of the SLP signal While in the Stop Grant state SMI INIT BINIT and LI
101. ed Strobe REQ 4 0 A 16 3 ADSTB0 35 17 ADSTB1 D 15 0 DBI0 DSTBP0 DSTBN0 D 31 16 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 AGTL Strobes Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 20 5 IGNNE INIT LINTO INTR Asynchronous GTL Asynchronous SMIg SLP STPCLK Asynchronous GTL Output Asynchronous FERR IERR THERMTRIP PROCHOT Front Side Bus Clock Clock BCLK1 BCLKO TAP Input 2 Synchronous to TCK TCK TDI TMS TRST TAP Output 2 Synchronous to TCK TDO SMBus Interface 8 Synchronous to SM_CLK SM_EP_A 2 0 SM TS A 1 0 SM DAT SM CLK SM_ALERT SM WP Power Other Power Other BSEL 1 0 COMP 1 0 GTLREF ODTEN Reserved SKTOCC TESTHI 6 0 VIDI4 0 Voc SM_Vcc Veca VocIoPLL VssA Vss VsssENSE OD Datasheet The Intel 1 Refer to Section 5 2 for signal descriptions 2 These signal groups are not terminated by the processor Refer the TP700 Debug Port Design Guide and corresponding Design Guide for termination requirements and further details Xeon processor with 512 KB L2 cache utilizes only BRO and BR1 BR2 and BR3 are not driven by the processor but must be terminated to Vcc For additional details regarding the BR 3 0 signals see Section 5 2 and
102. egarding the processor s features This device is shared with a scratch EEPROM The PIROM is programmed during the manufacturing and is write protected See Section 7 4 for details on the PIROM Retention mechanism The support components that are mounted through the baseboard to the chassis to provide mechanical retention for the processor and heatsink assembly Scratch EEPROM Electrically Erasable Programmable Read Only Memory An SMBus accessible memory device located on the processor interposer This memory device can be used by the OEM to store information useful for system management See Section 7 4 for details on the Scratch EEPROM SMBus System Management Bus A two wire interface through which simple system and power management related devices can communicate with the rest of the system It is based on the principals of the operation of the I2C two wire serial bus from Philips Semiconductor Note I2C is a two wire communications bus protocol developed by Philips SMBus is a subset of the I2C bus protocol and was developed by Intel Implementations of the I2C bus protocol or the SMBus bus protocol may require licenses from various entities including Philips Electronics N V and North American Philips Corporation Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are kno
103. er If a Receive Byte packet was preceded by a Write Byte or send Byte packet more recently than a Read Byte packet then the behavior is undefined Table 47 through Table 50 diagram the five packet types In these figures S represents the SMBus start bit P represents a stop bit Ack represents an acknowledge and represents a negative acknowledge The shaded bits are transmitted by the thermal sensor and the bits that aren t shaded are transmitted by the SMBus host controller Table 51 shows the encoding of the command byte Table 47 Write Byte SMBus Packet Slave Comman S Address Write Ack d Code Ack Data Ack P 1 7 bits 1 1 8 bits 1 8 bits 1 1 Table 48 Read Byte SMBus Packet Slave Slave S Addres write Comman Ack Addres Rea ack Data m P d Code 3 d 1 7 bits 1 1 8 bits 1 1 755 1 1 1 1 bits 108 Datasheet Intel Xeon Processor with 512 KB L2 Cache Table 49 Send Byte SMBus PacketReceive Byte SMBus Packet Table 50 s Slave Address Read Ack Command Code Ack P 1 7 bits 1 1 8 bits 1 1 s Slave Address Read Ack Data III P 1 7 bits 1 1 8 bits 1 1 ARA SMBus Packet s ARA Read Ack Address Ill P 1 0001 100 1 1 Device Address 1 1 NOTE 1 This is an 8 bit field The device which sent the aler
104. er undershoot is great enough Determining the impact of an overshoot undershoot condition requires knowledge of the magnitude the pulse direction and the activity factor AF Permanent damage to the processor is the likely result of excessive overshoot undershoot When performing simulations to determine impact of overshoot and undershoot ESD diodes must be properly characterized ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection ESD diodes modeled within Intel s signal integrity models do not clamp undershoot or overshoot and will yield correct simulation results If other signal integrity models are being used to characterize the processor front side bus care must be taken to ensure that ESD models do not clamp extreme voltage levels Intel s signal integrity models also contain I O capacitance characterization Therefore removing the ESD diodes from a signal integrity model will impact results and may yield excessive overshoot undershoot Overshoot Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level Vss It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently Overshoot undershoot magnitude levels must observe the absolute maximum specifications listed in Table 24 through Table 27 These specifications must not be violated at any time regard
105. es 519 5334 8411 349 35 00 18 20 26 93 O Y 4s so 54 i88 1905 i92 74 73 74 1897 i4z 178 1450 1463 1476 i 191 1836 96 oj C Figure 29 details the keep in zone for components mounted to the top side of the processor interposer The components include the EEPROM thermal sensor resistors and capacitors Datasheet 59 Intel Xeon Processor with 512 KB L2 Cache n Figure 29 INT mPGA Processor Package Top View Component Height Keep in RE KEEPOUT KEEPOUT IN 2X 4 344 ONENT 55 HATCHED AREA Figure 30 details the keep in specification for pin side components The processor may contain pin side capacitors mounted to the processor package These capacitors will be exposed within the opening of the interposer cavity Figure 30 INT mPGA Processor Package Cross Section View Pin Side Component Keep in 5 Interposer OOOO OOOO m nm Component Keepin 13 411mm gt Component Keepin Socket must allow clearance for pin shoulders and mate flush with this surface 60 Datasheet n Intel Xeon Processor with 512 KB L2 Cache Figure 31 INT mPGA Processor Package Pin Detail 20 3051 0 031 1 Kovar with plating of 0 2 micrometers Au over
106. essor heatsink must also be taken into consideration when designing new baseboards and chassis The airflow requirements are detailed in the Thermal Specifications Section 8 4 Heatsink Weight The boxed processor heatsink weighs no more than 450 grams See Chapter 4 0 and Chapter 6 0 of this document along with the Intel Xeon Processor Family Thermal Design Guidelines for details on the processor weight and heatsink requirements Datasheet E ntel Intel Xeon Processor with 512 L2 Cache 8 2 3 Datasheet Retention Mechanism and Heatsink Supports The boxed processor requires processor retention solution to secure the processor the baseboard and the chassis The retention solution contains one retention mechanisms and two retention clips per processor The boxed processor ships with retention mechanism cooling solution retention clips and direct chassis attach screws Baseboards and chassis designed for use by system integrators should include holes that are in proper alignment with each other to support the boxed processor Refer to the Server System Infrastructure Specification SSI EEB at http www ssiforum org for details on the hole locations Please refer to the Boxed integration notes at http support intel com support processors xeon for retention mechanism installation instructions Please reference Figure 45 for the dimmensions of the retention mechanism that ships with the boxed processor Please refe
107. fications 98 720 uu 99 7 1 Power On Configuration 99 7 2 Clock Control and Low Power States 022 40 0 99 7 3 Thermial Non lor 102 7 4 System Management Bus SMBus 103 8 0 Boxed Processor Specifications aa aa aaa 115 8 1 OM T CE 115 8 2 Mechanical nnne nnn nennen 116 8 3 10 Rack Mount Server Solution sss ener 125 Datasheet 3 E Contents ntel 8 4 Thermal Specifications abe nea anne 127 9 0 Debug Tools Specifications a 128 9 1 Logic Analyzer Interface LAI uuu R una nnne 128 4 Datasheet ntel Contents Figures 1 Typical VCCIOPLL VCCA and VSSA Power Distribution 18 2 Phase Lock Loop PLL Filter Requirements uu 19 3 Intel Xeon Processor with 512 L2 Cache Voltage Current VID 1 5V 27 4 Intel Xeon Processor with 512 KB L2 Cache Voltage Current VID 1 525V 28 5 Electrical Test u u uku uuu ua eq 37 6 He Nee SEMI 37 7 Differential Clock Waveform
108. fications Intel Table 42 specifies the thermal design power dissipation envelope for the Intel Xeon processor with 512 KB L2 cache The processor power listed in Table 42 is described in thermal design power Analysis indicates that real applications are unlikely to cause the processor to consume the maximum possible power consumption Intel recommends that system thermal designs utilize the Thermal Design Power indicated in Table 42 Thermal Design Power recommendations are chosen through characterization of server and workstation applications on the processor The Thermal Monitor feature is intended to protect the processor from overheating on any high power code that exceeds the recommendations in this table For more details on the Thermal Monitor feature refer to Section 7 3 In all cases the Thermal Monitor feature must be enabled for the processor to be operating within specification Table 42 also lists the minimum and maximum processor Tcasg temperature specifications A thermal solution should be designed to ensure the temperature of the processor never exceeds these specifications Table 42 Processor Thermal Design Power Core Frequency i a oem TCASE Notes W 1 80 GHz 55 5 69 2 3 2 GHz 58 5 70 2 3 2 20 GHz 61 5 75 2 3 2 40 GHz 65 5 74 2 3 2 60 GHz 71 5 74 2 3 2 80 GHz 74 5 75 2 3 3 GHz 85 5 2 3 1 Intel recommends that thermal solutions be designed ut
109. hassis manufacture to provide adequate airflow across the processor heatsink Manufacturers may elect to use their own cooling solution Although Intel will be testing a select number of baseboard and chassis combinations for thermal compliance this is in no way a comprehensive test It is ultimately the system integrator s responsibility to test that their solution meets all of the requirements specified in this document The PWT is meant to assist in processor cooling but additional cooling techniques may be required in order to ensure that the entire system meets the thermal requirements See Figure 49 and Figure 50 for the Processor Wind Tunnel dimensions Fan The Processor Wind Tunnel includes a 25mm fan for use with processors lt 2 8 GHz or a 38mm fan for use with processors running at 3 GHz The 38mm fan provides the high performance required to meet the demanding thermal requirements of processors running at 3 GHz The 38mm fan provides local fan speed control There is a temperature diode on the fan that measures the inlet temperature to the fan and adjusts the speed accordingly The benefit is that system manufacturers can pass acoustical requirements while still being able to pass thermal requirements at maximum ambient temperature Fan Power Supply The Processor Wind Tunnel includes a fan which requires a constant 12V power supply A fan power cable is shipped with the boxed processor to draw power from a power header on the
110. hese are Reserved pins on the Intel Xeon processor In systems utilizing the Intel Xeon processor the system designer must terminate these signals to the processor Vcc 2 Baseboards treating AA3 and AB3 as Reserved will operate correctly with a bus clock of 100 MHz 83 Intel Xeon Processor with 512 KB L2 Cache 5 2 Signal Definitions Table 41 Signal Definitions Page 1 of 10 Name Type Description Notes 35 3 yo A 35 3 Address define a 236 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of all agents on the front side bus A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 35 3 pins to determine their power on configuration See Section 7 1 A20M If A2ZOM Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MByte boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal
111. hing thermal solutions to the baseboard should have a high degree of commonality with the thermal solution components enabled for the Intel Xeon processor Heatsinks and retention mechanisms have been designed with manufacturability as a high priority Hence mechanical assembly can be completed from the top of the baseboard 11 a Intel Xeon Processor with 512 KB L2 Cache ntel 1 1 The Intel Xeon processor with 512 KB L2 cache uses a scalable front side bus protocol referred to as the front side bus in this document The processor front side bus utilizes a split transaction deferred reply protocol similar to that introduced by the Pentium Pro processor front side bus but is not compatible with the Pentium Pro processor front side bus The Intel Xeon processor with 512 KB L2 cache front side bus is compatible with the Intel Xeon processor front side bus The front side bus uses Source Synchronous Transfer SST of address and data to improve performance and transfers data four times per bus clock 4X data transfer rate Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or 2X address bus In addition the Request Phase completes in one clock cycle Working together the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3 2 Gigabytes per second Finally the front side bus also introduces transactions that are used to deliver interrupts
112. ications in this table apply to all processor frequencies and cache sizes is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value and Voy may experience excursions above However input signal drivers must comply with the signal quality specifications in Chapter 3 0 Refer to the Inte Xeon Processor with 512 KB L2 Cache Signal Integrity Models for I V characteristics The referred to in these specifications refers to instantaneous Vcc VoL max Of 0 450 V is guaranteed when driving into a test load as indicated in Figure 5 with enabled Leakage to Vcc with pin held at 300 mV Leakage to Vss with pin held at Vcc Table 9 TAP and PWRGOOD Signal Group DC Specifications Datasheet Symbol Parameter Min Max Unit Notes Vuys TAP Input Hysteresis 200 300 8 TAP input low to high 0 5 Vcc Vuvs 0 5 Voc Vuvs MAX 5 input high to low x Vr 2 Vollage 0 5 Voc Vuvs 0 5 Voc 5 Vou Output High Voltage N A Voc V 3 5 lo Output Low Current 40 mA 6 7 Pin Leakage High N A 100 10 lio Pin Leakage Low N A 500 9 Ron Buffer On Resistance 8 75 13 75 Q 4 NOTES 1 2 Unless otherwise note
113. ies in the United States and other countries Copyright Intel Corporation 2002 2003 Datasheet E ntel Contents Contents 1 0 11 1 1 12 1 2 SEITLICH 13 1 3 nile em 14 2 0 Electrical Specifications usa 15 2 1 Front Side Bus and GTLREF uu un eerte tentat bL heh Desde 15 2 2 Power and Gro rnd PIMs sis u U repete be 15 2 3 Decoupling G idelimes 15 2 4 Front Side Bus Clock BCLK 1 0 and Processor Clocking 16 2 5 Quum aan 17 2 6 Voltage Id ntitiealleo uuu 20 2 7 Reserved Or Unused Ping u uuu vin tte te cete ten ate habe neo Er Ra eda 22 2 8 Front Side Bus Signal Groups 22 2 9 Asynchronous GTLE Signals tient edet tnnt tt ta nea e eate Fede 24 2 10 Maium RAINS oe uu u yr es da Du 24 2 11 Processor DO Specifications carte En 25 2 12 Front Side Bus Specifications sse 31 2 13 Front Side Bus AC Specifications a 32 2 14 Processor AC Timing Waveforms
114. ilizing the Thermal Design Power values Refer to the Intel Xeon Processor Thermal Design Guidelines 2 TDP values are specified at the point on Vcc_max loadline corresponding to Icc_TDP 3 Systems must be designed to ensure that the processor is not subjected to any static Vcc and combination wherein Vcc exceeds Vcc_max at specified Icc Please refer to the loadline specifications in Chapter 2 0 Figure 38 Processor Thermal Design Power vs Electrical Projections for VID 1 500V Datasheet Intel Xeon Processor with 512 KB L2 Cache 1 525V Figure 39 Processor Thermal Design Power vs Electrical Projections for VID RES ESL SS UD ee ee LIS IIO BARE ta eek See ERE 75 aay E El EHS M MALI I 97 Datasheet Intel Xeon Processor with 512 KB L2 Cache 6 2 6 2 98 1 Measurements for Thermal Specifications Processor Case Temperature Measurement intel The minimum and maximum case temperatures for processors are specified in Table 42 of the previous section These temperature specifications are meant to ensure correct and reliable operation of the processor Figure 40 illustrates the thermal measurement point for lt This point is at the geometric center of the integrated heat spreader IHS Figure 40 Thermal Measurement Point for Processor TcasE Note
115. ings and controlled edge rates The processor termination voltage level is the operating voltage of the processor core The use of a termination voltage that is determined by the processor core allows better voltage scaling on the processor front side bus Because of the speed improvements to data and address busses signal integrity and platform design methods become more critical than with previous processor families Front side bus design guidelines are detailed in the appropriate platform design guide refer to Section 1 3 AGTL inputs require a reference voltage GTLREF which is used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF must be generated on the baseboard See Table 13 for GTLREF specifications Termination resistors are provided on the processor silicon and are terminated to its core voltage Vcc The on die termination resistors are a selectable feature and can be enabled or disabled via the ODTEN pin For end bus agents on die termination can be enabled to control reflections on the transmission line For middle bus agents on die termination must be disabled Intel chipsets will also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Refer to Section 2 12 for details on ODTEN resistor termination requirements Some signals do not include on die termination and must be terminated on the baseboard See Table 4 f
116. input signals have differential input buffers which use GTLREF as a reference level In this document the term Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the I O group when driving With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as Datasheet rising edge of BCLK0 Asynchronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 4 identifies which signals are common Intel Xeon Processor with 512 KB L2 Cache clock source synchronous and asynchronous Table 4 Front Side Bus Signal Groups Signal Group Type Signals AGTL Common Clock Input Synchronous to BCLK 1 0 BPRI BR 3 1 7 DEFER RESET RS 2 0 RSP TRDY AGTL Common Clock I O Synchronous to BCLK 1 0 ADS 0 BINIT 5 0 BR0 2 DBSY 3 0 DRDY HIT 7 HITM LOCK MCERR AGTL Source Synchronous Synchronous to assoc strobe Signals Associat
117. ith 512 KB L2 Cache ntel 2 3 1 2 3 2 2 4 Care must taken in the baseboard design to ensure that the voltage provided to the remains within the specifications listed in Table 6 Failure to do so can result in timing violations or reduced lifetime of the component For further information and guidelines refer to the appropriate platform design guidelines Vcc Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must ensure a low interconnect resistance from the regulator or VRM pins to the 603 pin socket Bulk decoupling may be provided on the voltage regulation module VRM to meet help meet the large current swing requirements The remaining decoupling is provided on the baseboard The power delivery path must be capable of delivering enough current while maintaining the required tolerances defined in Table 6 For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Front Side Bus AGTL Decoupling The Intel Xeon processor with 512 KB L2 cache integrates signal termination on the die as well as part of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus Bulk decoupling must a
118. ive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing the falling edge of BCLK1 84 Datasheet n Intel Xeon TM Processor with 512 KB L2 Cache Table 41 Signal Definitions Page 2 of 10 Name Type Description Notes BINIT Bus Initialization may be observed and driven by all processor front side bus agents and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future information If BINIT observation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity BINIT yo and bus request arbitration state machines The bus agents do not reset their OQ 4 and transaction tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the front side bus and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a central agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During
119. l Projections for VID 1 500V 96 39 Processor Thermal Design Power vs Electrical Projections for VID 1 525V 97 40 Thermal Measurement Point for Processor 98 41 Stop Clock State Machine sse enne enne trenen nnns nnn tnter 100 42 Logical Schematic of SMBUS Circuitry narrar 104 43 Mechanical Representation of the Boxed Processor Passive Heatsink for 3 GHz processors Datasheet 5 E Contents ntel 44 Mechanical Representation of the Boxed Processor Passive Heatsink for 2 2 80 GHz proces CoU 116 45 Retention Mechan Si 118 46 Boxed Processor Glipu EET 119 47 Multiple View Space Requirements for the Boxed 120 48 Fan Connector Electrical Pin Sequence 121 49 Processor Wind Tunnel General Dimensions nennen 123 50 Processor Wind Tunnel Detailed 124 51 Exploded View of the 10 Thermal Solution nnne 125 52 Assembled View of the 10 Thermal 126 6 Datasheet ntel Contents Tables 1 Front Side Bus to Core Frequency Ratio n 17 2 Front Side Bus Clock Frequency Select Truth Tabl
120. le 20 Datasheet Intel Xeon Processor with 512 KB L2 Cache Front Side Bus AC Specifications Reset Conditions T Parameter Min Max Unit Figure Notes T45 Reset Configuration Signals A 31 3 BR 3 0 INIT SMI Setup Time 5 BOERS m 1 T46 Reset Configuration Signals A 31 3 BR 3 0 INIT SMI Hold Time 2 2D 1 Before the de assertion of RESET 2 After the clock that de asserts RESET TAP Signal Group AC Specifications 2 a Notes T Parameter Min Max Unit Figure 1 2 3 9 T55 TCK Period 60 0 ns 6 T56 TCK Rise Time 9 5 ns 6 4 T57 TCK Fall Time 9 5 nS 6 4 T58 TMS TDI Rise Time 8 5 nS 6 4 T59 TMS TDI Fall Time 8 5 nS 6 4 T61 TDI TMS Setup Time 0 nS 14 5 7 T62 TDI TMS Hold Time 3 0 nS 14 5 7 T63 TDO Clock to Output Delay 0 5 3 5 nS 14 6 T64 TRST Assert Time 2 0 Trck 19 8 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 2 Not 100 tested Specified by design characterization 3 All AC timings for the TAP signals are referenced to the TCK signal at 0 5 Vcc at the processor pins All TAP signal timings TMS TDI etc are referenced at the 0 5 processor pins 4 Rise and fall times are measured from the 2096 to 8096 points of the signal swing 5 Referenced to the rising edge of TCK
121. less of bus activity or system state Within these specifications are threshold levels that define different allowed pulse duration Provided that the magnitude of the overshoot undershoot is within the absolute maximum specifications the pulse magnitude duration and activity factor must all be used to determine if the overshoot undershoot pulse is within specifications Overshoot Undershoot Pulse Duration Pulse duration describes the total time an overshoot undershoot event exceeds the overshoot undershoot reference voltage The total time could encompass several oscillations above the reference voltage Multiple overshoot undershoot pulses within a single overshoot undershoot event may need to be measured to determine the total pulse duration Note 1 Oscillations below the reference voltage can not be subtracted from the total overshoot undershoot pulse duration Datasheet In 3 3 4 3 3 5 Datasheet Intel Xeon Processor with 512 KB L2 Cache Activity Factor Activity Factor AF describes the frequency of overshoot or undershoot occurrence relative to a clock Since the highest frequency of assertion of any common clock signal is every other clock an AF 1 indicates that the specific overshoot or undershoot waveform occurs every other clock cycle Thus an AF 0 01 indicates that the specific overshoot or undershoot waveform occurs one time in every 200 clock cycles For source synchronous signals
122. llowing tables specify the allowable overshoot undershoot for a single overshoot undershoot event However most systems will have multiple overshoot and or undershoot events that each have their own set of parameters duration AF and magnitude While each overshoot on its own may meet the overshoot specification when the total impact of all overshoot events are considered the system may fail A guideline to ensure a system passes the overshoot and undershoot specifications is shown below Ensure that no signal ever exceeds or 0 25 V OR If only one overshoot undershoot event magnitude occurs ensure it meets the overshoot undershoot specifications in the following tables OR If multiple overshoots and or multiple undershoots occur measure the worst case pulse duration for each magnitude and compare the results against the AF 1 specifications If all of these worst case overshoot or undershoot events meet the specifications measured time specifications in the table where AF 1 then the system passes The following notes apply to Table 24 through Table 27 Absolute Maximum Overshoot magnitude of 1 8V must never be exceeded Absolute Maximum Overshoot is measured referenced to Vgg Pulse Duration of overshoot is measured relative to Vcc Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to V ss Ringback below cannot be subtracted from overshoots undershoots Lesser undersh
123. lso be provided by the baseboard for proper AGTL bus operation Decoupling guidelines are described in the appropriate platform design guidelines Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the front side bus interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The maximum processor bus ratio multiplier will be set during manufacturing The default setting will equal the maximum speed for the processor The BCLK 1 0 inputs directly control the operating speed of the front side bus interface The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction at which the particular processor can operate Clock multiplying within the processor is provided by the internal PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking Processor DC and AC specifications for the BCLK 1 0 inputs are provided in Table 7 and Table 14 respectively These specifications must be met while also meeting signal integrity requirements as outlined in Chapter 3 0 The processor utilizes a differential clock Details regarding BCLK 1 0 driver specifications are provided in the CK00 Clock Synthesizer Driver Design Guidelines Table 1 contains the supported bus fraction ratios a
124. n Name Type Direction R8 VSS Power Other R9 VCC Power Other R23 VCC Power Other R24 VSS Power Other R25 VCC Power Other R26 VSS Power Other R27 VCC Power Other R28 VSS Power Other R29 VCC Power Other R30 VSS Power Other R31 VCC Power Other T1 VSS Power Other T2 VCC Power Other T3 VSS Power Other T4 VCC Power Other T5 VSS Power Other T6 VCC Power Other 7 VSS Power Other T8 VCC Power Other T9 VSS Power Other T23 VSS Power Other T24 VCC Power Other T25 VSS Power Other T26 VCC Power Other T27 VSS Power Other T28 VCC Power Other T29 VSS Power Other T30 VCC Power Other T31 VSS Power Other U1 Power Other U2 vss Power Other U3 VCC Power Other U4 VSS Power Other U5 VCC Power Other U6 VSS Power Other U7 Power Other U8 VSS Power Other 09 VCC Power Other U23 VCC Power Other Datasheet intel Table 39 Pin Listing by Pin Number Signal Intel Xeon TM Processor with 512 KB L2 Cache Table 39 Pin Listing by Pin Number Pin No Pin Name Buffer Type Direction U24 VSS Power Other U25 Power Other U26 VSS Power Other U27 Power Other U28 VSS Power Other U29 VCC Power Other U30 VSS Power Other 031 VCC Power Other V1 vss Power Other V2 Power
125. nd their corresponding core frequencies Datasheet intel Table 1 2 4 1 Table 2 2 5 Datasheet Intel Xeon Processor with 512 KB L2 Cache Front Side Bus to Core Frequency Ratio Fmt Se Cot co raion 1 16 1 60 GHz 1 17 1 70 GHz 1 18 1 80 GHz 1 19 1 90 GHz 1 20 2 GHz 1 21 2 10 GHz 1 22 2 20 GHz 1 24 2 40 GHz 1 26 2 60 GHz 1 28 2 80 GHz 1 30 3 GHz Bus Clock The front side bus frequency is set to the maximum supported by the individual processor BSEL 1 0 are outputs used to select the front side bus frequency Table 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All front side bus agents must operate at the same frequency Individual processors will only operate at their specified front side bus clock frequency 100 MHz for present generation processors Baseboards designed for the Intel Xeon processor employ a 100 MHz front side bus clock On these baseboards BSEL 1 0 are considered reserved at the processor socket No change is required for operation with the Intel Xeon processor with 512 KB L2 cache Operation will default to 100 MHz Front Side Bus Clock Frequency Select Truth Table for BSEL 1 0 BSEL1 BSELO Bus Clock Frequency L L 100 MHz L H Reserved H L Reserved H H Reserve
126. ne Datasheet 93 Intel Xeon Processor with 512 KB L2 Cache 94 Datasheet Intel Xeon Processor with 512 KB L2 Cache Thermal Specifications Note This chapter provides the thermal specifications necessary for designing a thermal solution for the Intel Xeon processor with 512 KB L2 cache Thermal solutions should include heatsinks that attach to the integrated heat spreader IHS The IHS provides a common interface intended to be compatible with many heatsink designs Thermal specifications are based on the temperature of the IHS top referred to as the case temperature or Tease Thermal solutions should be designed to maintain the processor within Tcasg specifications For information on performing Tease measurements refer to the Intel Xeon Processor Thermal Design Guidelines See Figure 37 for an exploded view of the processor package and thermal solution assembly The processor is either shipped alone or with a heatsink boxed processor only All other components shown in Figure 37 must be purchased separately Figure 37 Processor with Thermal and Mechanical Components Exploded View Note Datasheet Heat sink clip Heat sink EMI ground frame Retention mechanism This is a graphical representation For specifications see each component s respective documentation listed in Section 1 3 95 Intel Xeon Processor with 512 KB L2 Cache 6 1 96 Thermal Speci
127. nformation ROM The thermal reference byte represents the approximate thermal byte reading that is obtained when the processor is operating at its maximum specified The TRB is derived for each individual processor during Intel s manufacturing process The processor SMBus thermal sensor and thermal reference byte may be used to monitor long term temperature trends but can not be used to manage the short term temperature of the processor or predict the activation of the thermal control circuit As mentioned earlier the processors high thermal ramp rates make this infeasible Refer to the Intel Xeon Processor Family Thermal Design Guidelines for more details The SMBus thermal sensor feature in the processor cannot be used to measure The Tease specification in Chapter 6 0 must be met regardless of the reading of the processor s thermal sensor in order to ensure adequate cooling for the processor The SMBus thermal sensor feature is only available while and SM are at valid levels and the processor is not in a low power state Thermal Sensor Supported SMBus Transactions The thermal sensor responds to five of the SMBus packet types Write Byte Read Byte Send Byte Receive Byte and Alert Response Address ARA The Send Byte packet is used for sending one shot commands only The Receive Byte packet accesses the register commanded by the last Read Byte packet and can be used to continuously read from a regist
128. noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction INIT INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor front side bus agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST 88 Datasheet In Intel Xeon TM Processor with 512 KB L2 Cache Table 41 Signal Definitions Page 6 of 10 Name Type Description Notes LINT 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all front side bus agents When the APIC functionality is disabled the LINT0 signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the sign
129. ns Page 7 of 10 Name Type Description Notes PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state Figure 13 illustrates the relationship of PWRGOOD to the RESET signal PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 16 and be followed by a 1 mS RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation 4 0 y o REQ 4 0 4 Request Command must connect the appropriate pins of all processor front side bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals RESET Asserting the RESET signal resets all processors to known states and invalida
130. ns of acquiring thermal data from the processor The thermal sensor is composed of control logic SMBus interface logic a precision analog to digital converter and a precision current source The sensor drives a small current through the p n junction of a thermal diode located on the processor core The forward bias voltage generated across the thermal diode is sensed and the precision A D converter derives a single byte of thermal reference data or a thermal byte reading The nominal precision of the least significant bit of a thermal byte is 1 C The processor incorporates the SMBus thermal sensor and thermal reference byte onto the processor package as was previously done on Intel Xeon processor family Upper and lower thermal reference thresholds can be individually programmed for the SMBus thermal sensor Comparator circuits sample the register where the single byte of thermal data thermal byte 107 a Intel Xeon Processor with 512 KB L2 Cache ntel 7 4 5 reading is stored These circuits compare the single byte result against programmable threshold bytes If enabled the alert signal on the processor SMBus SM_ALERT will be asserted when the sensor detects that either threshold is reached or crossed Analysis of SMBus thermal sensor data may be useful in detecting changes in the system environment that may require attention During manufacturing the thermal reference byte TRB is programmed into the Processor I
131. ntel Xeon Processor with 512 KB L2 Cache ntel 2 6 20 Voltage Identification The VID specification for the processor is defined in this datasheet and is supported by power delivery solutions designed according to the Dual Intel Xeon TM Processor Voltage Regulator Down VRD Design Guidelines VRM 9 0 DC DC Converter Design Guidelines and VRM 9 1 DC DC Converter Design Guidelines The minimum voltage is provided in Table 6 and varies with processor frequency This allows processors running at a higher frequency to have a relaxed minimum voltage specification The specifications have been set such that one voltage regulator design can work with all supported processor frequencies Note that the VID pins will drive valid and correct logic levels when the Intel Xeon processor with 512 KB L2 cache is provided with a valid voltage applied to the SM_Vcc pins SM_Vcc must be correct and stable prior to enabling the output of the VRM that supplies Similarly the output of the must be disabled before SM_Vcc becomes invalid Refer to Figure 19 for details The processor uses five voltage identification pins VID 4 0 to support automatic selection of processor voltages Table 3 specifies the voltage level corresponding to the state of VID 4 0 A 1 in this table refers to a high voltage and a 0 refers to low voltage level If the processor socket is empty VID 4 0 11111 or the VRD or VRM cannot supply the
132. o Second Address Strobe Ts T20 Source Sync Output Valid Delay Ta T31 Address Strobe Output Valid Delay Datasheet 39 Intel Xeon Processor with 512 KB L2 Cache Figure 11 Front Side Bus Source Synchronous 4X Data Timing Waveform TO 1 4 BOLK BCLK1 T1 T2 1 2 3 4 BOLK BOLK BCLK0 DSTBp driver DSTBn driver D driver DSTBp receiver DSTBn receiver D receiver T21 Source Sync T T22 Source Sync 27 Source Sync T30 Source Sync T25 Source Sync T26 Source Sync f WI H H H I T20 Source Sync Data Output Valid Delay Before Data Strobe Data Output Valid Delay After Data Strobe Setup Time to BCLK Data Strobe N DSTBN Output Valid Delay Input Setup Time Input Hold Time T29 First Data Strobe to Subsequent Strobes Data Output Valid Delay 40 Datasheet ntel Intel Xeon Processor with 512 KB L2 Cache Figure 12 Front Side Bus Reset and Configuration Timing Waveform pick X X X X X X JOOOO0O0000000000X T RESET Tx apa onos K X Valid SMI INIT lt Ty P jee Valid INIT 113 RESET Pluse Width 1 145 Reset Configuration Signals 14 5 BRO SMI INIT Setup Time Te T46 Reset Configuration signals A 14 5 BRO SMI INIT Hold Time
133. ocessor The processor includes a 10 pull up resistor to SM for this signal The SM DAT SMBus Data signal is the data signal for the SMBus This signal SM DAT VO provides the single bit mechanism for transferring data between SMBus devices The processor includes 10 pull up resistor to SM_Vec for this signal The SM_EP_A EEPROM Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors To set an SM_EP_A line high a pull up resistor should be used that is no larger than 1 The processor includes a 10 pull down resistor to Vss for each of these signals For more information on the usage of these pins see Section 7 4 8 The SM TS A Thermal Sensor Select Address pins are decoded on the SMBus in conjunction with the upper address bits in order to maintain unique addresses on the SMBus in a system with multiple processors The device s addressing as implemented includes a Hi Z state for both address pins The use of the Hi Z state is achieved by leaving the input floating unconnected For more information on the usage of these pins see Section 7 4 8 SM EP A 2 0 SM TS A 1 0 Provides power to the SMBus components on the processor as well as to the SM processor VID logic The baseboard MUST provide SM Vcc to the processor Figure 19 Example 3 3 VDC SM
134. of the overshoot the following parameters must also be known the width of the overshoot and the activity factor AF To determine the allowed overshoot for a particular overshoot event the following must be done 1 Determine the signal group that particular signal falls into For AGTL signals operating in the 4X source synchronous domain Table 24 should be used For AGTL signals operating in the 2X source synchronous domain Table 25 should be used If the signal is an AGTL signal operating in the common clock domain Table 26 should be used Finally for all other signals residing in the 33 MHz domain asynchronous etc Table 27 should be used 2 Determine the magnitude of the overshoot the undershoot relative to V ss 3 Determine the activity factor how often does this overshoot occurs 4 Next from the appropriate specification table determine the maximum pulse duration in nanoseconds allowed 5 Compare the specified maximum pulse duration to the signal being measured If the pulse duration measured is less than the pulse duration shown in the table then the signal meets the specifications Undershoot events must be analyzed separately from overshoot events as they are mutually exclusive 51 a Intel Xeon Processor with 512 KB L2 Cache ntel 3 3 6 52 Determining if a System Meets the Overshoot Undershoot Specifications The overshoot undershoot specifications listed in the fo
135. ommended COMP resistance value 9 This specification applies to the Intel Xeon Processor with 512 KB L2 Cache when implemented in platforms that do not include forward compatibility with future processors 10 This specification applies to the Intel Xeon Processor with 512 KB L2 Cache when implemented in platforms that include forward compatibility with future processors Front Side Bus AC Specifications The processor front side bus timings specified in this section are defined at the processor core pads See Section 5 0 for the pin listing and signal definitions Table 14 through Table 20 list the AC specifications associated with the processor front side bus AGTL timings are referenced to GTLREF for both 0 and 1 logic levels unless otherwise specified The timings specified in this section should be used in conjunction with the signal integrity models provided by Intel These signal integrity models which include package information are available for the Intel Xeon processor with 512 KB L2 cache in IBIS format AGTL layout guidelines are also available in the appropriate platform design guidelines Note Care should be taken to read all notes associated with a particular timing parameter Table 14 Front Side Bus Differential Clock Specifications 32 T Parameter Min Nom Max Unit Figure Notes Front Side Bus Clock Frequency 100 0 MHz 1 2 T1 BCLK 1 0 Period
136. on of the processor Figure 33 Processor Top Side Markings INTEL CONFIDENTIAL c 00 ATPO NOTE 1 Character size for laser markings is height 0 050 1 27mm width 0 032 0 81mm 2 All characters will be in upper case Figure 34 Processor Bottom Side Markings 64 Datasheet 4 7 Figure 35 Datasheet Pin Out Diagram Intel Xeon Processor with 512 KB L2 Cache This section provides two view of the processor pin grid Figure 35 and Figure 36 detail the coordinates of the processor pins Processor Pin Out Diagram Top View Vcc Vss COMMON CLOCK ADDRESS 1 3 5 7 9 11 13 Aeeooeocoeooeooe Boeoeoe ocoeooeoo Cceeoeeo ooeocoeo Deeooeooeocoeooe Eeeocooeoco ooeoo Heeeeeeeee Neeeeeeeee Reeeeeeeee Weeoeocoooo0 Yeeooeloeooeooeo ABeeooeooceooeooe Acoe eeojjoeooceooeo ADoeeoocileooeooeoo AE eeeoclooeooeooe 2 4 6 8 0 12 14 CLOCKS O Signal Power Ground COMMON CLOCK JTAG 15 17 19 21 23 25 27 99 31 o00oelooeocleooeeeee eoeocloeooelooeoceeee oeoocleooeoloeooeeee oooeiooeooeooeeeee eoeooeooeooeoeeee
137. ons apply to both data and address timings Valid delay timings for these signals are specified into the test circuit described in Figure 5 and with GTLREF at 2 3 Voc 2 Specification is for a minimum swing defined between AGTL Vii max to This assumes an edge rate of 0 3 V nS to 4 0 V nS All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each respective strobe This specification represents the minimum time the data or address will be valid before its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications This specification represents the minimum time the data or address will be valid after its strobe Refer to the appropriate platform design guidelines for more information on the definitions and use of these specifications 10 The rising edge of ADSTB must come approximately 1 2 BCLK period 5 nS after the falling edge of 11 ADSTB For this timing parameter n 1 2 and 3 for the second third and last data strobes respectively 12 The second data strobe the falling edge of DSTBn must come approximately 1 4 BCLK period 2 5 nS after the first falling edge of DSTBp The third data strobe the falling edge of DSTBp must come approximately 2 4 BCLK period 5 nS after the first falling edge of DSTBp The last data strobe the falling edge of DSTBn must come approxima
138. oot does not allocate longer or larger overshoot System designers are strongly encouraged to follow Intel s layout guidelines All values specified by design characterization Datasheet In Table 24 Source Synchronous 400 MHz AGTL Signal Group Overshoot Undershoot Table 25 Source Synchronous 200 MHz AGTL Signal Group Overshoot Undershoot Datasheet Intel Xeon Processor with 512 KB L2 Cache Tolerance Sia Pulse Duration Pulse Duration Pulse Duration Overshoot V Undershoot V QUT MH 1 80 0 320 0 01 0 15 1 58 1 75 0 270 0 03 0 45 4 60 1 70 0 220 0 09 1 28 5 00 1 65 0 170 0 25 3 71 5 00 1 60 0 120 0 76 5 00 5 00 1 55 0 070 2 54 5 00 5 00 NOTES 1 These specifications are measured at the processor pad 2 Assumes a BCLK period of 10 nS 3 AF is referenced to associated source synchronous strobes Tolerance Maximum Maximum Pulse Duration Pulse Duration Pulse Duration Overshoot V Undershoot V is 1 80 0 320 0 03 0 29 2 88 1 75 0 270 0 06 0 62 6 25 1 70 0 220 0 18 1 75 10 00 1 65 0 170 0 51 5 06 10 00 1 60 0 120 1 52 10 00 10 00 1 55 0 07 5 08 10 00 10 00 NOTES 1 These specifications are measured at the processor pad 2 Assumes a BCLK period of 10 ns 3 AF is referenced to associated source synchronous strobes Intel Xeon Processor with 512
139. or details regarding these signals The AGTL signals depend on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the front side bus including trace lengths is highly recommended when designing a system Please refer to http developer intel com to obtain the Intel Xeon Processor with 512 KB L2 Cache Signal Integrity Models Power and Ground Pins For clean on chip power distribution the Intel Xeon processor with 512 KB L2 cache has 190 power and 189 Vss ground inputs All Vcc pins must be connected to the system power plane while all pins must be connected to the system ground plane The processor pins must be supplied the voltage determined by the processor VID Voltage ID pins Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the processor is capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cgy x such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle condition from a running condition 15 a Intel Xeon Processor w
140. period T2 BCLK 1 0 Period stability not shown T3 BCLK 1 0 pulse high time 4 BCLK 1 0 pulse low time T5 BCLK 1 0 rise time through the threshold region T6 BCLK 1 0 fall time through the threshold region Figure 8 Differential Clock Crosspoint Specification Crosspoint Specification ae Crossing Point mV 888888888 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 Vhavg mV Datasheet Intel Xeon Processor with 512 KB L2 Cache Figure 9 Front Side Bus Common Clock Valid Delay Timing Waveform TO T2 BCLK1 BCLK0 Common Clock Signal driver Common Clock Signal receiver T T10 Common Clock Output Valid Delay T11 Common Clock Input Setup 112 Common Clock Input Hold Time Figure 10 Front Side Bus Source Synchronous 2X Address Timing Waveform 14 172 T T2 BQLK BOLK BOLK BCLK1 BCLKO ADSTB driver A driver ADSTB receiver valid valid Xn Ait receiver T23 Source Sync Address Output Valid Before Address Strobe T T24 Source Sync Address Output Valid After Address Strobe T T27 Source Sync Input Setup to BCLK T26 Source Sync Input Hold Time T T25 Source Sync Input Setup Time T T28 First Address Strobe t
141. put Output 68 Datasheet intel Table 38 Pin Listing by Pin Name Intel Xeon TM Processor with 512 KB L2 Cache Table 38 Pin Listing by Pin Name Pin Name Pin No ae oe Direction Pin Name Pin No ce Direction DP1 AE19 Common Clk Input Output Reserved B1 Reserved Reserved DP2 AC15 Common Clk Input Output Reserved C5 Reserved Reserved DP3 AE17 Clk Input Output Reserved D25 Reserved Reserved DRDY E18 Input Output Reserved W3 Reserved Reserved DSTBNO Y21 Source Sync Input Output Reserved Reserved Reserved DSTBN1 Y18 Source Sync Input Output Reserved Y27 Reserved Reserved DSTBN2 Y15 Source Sync Input Output Reserved Y28 Reserved Reserved DSTBN3 Y12 Source Sync Input Output Reserved AC1 Reserved Reserved DSTBP0 Y20 Source Sync Input Output Reserved AD1 Reserved Reserved DSTBP1 Y17 Source Sync Input Output Reserved AE4 Reserved Reserved DSTBP2 Y14 Source Sync Input Output Reserved AE15 Reserved Reserved DSTBP3 Y11 Source Sync Input Output Reserved AE16 Reserved Reserved FERR E27 Async GTL Output RESET Y8 Common Clk Input GTLREF W23 Power Other Input RS0 E21 Common Clk Input GTLREF W9 Power Other Input
142. r Normal Mode or the AutoHALT Power Down state See the Intel Architecture Software Developer s Manual Volume III System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the AutoHALT Power Down state When the system deasserts the STPCLK interrupt the processor will return execution to the HALT state Figure 41 Stop Clock State Machine 100 HALT Instruction and HALT Bus Cycle Generated 2 Power Down State INIT BINIT INTR NMI 1 Normal State running RESET Normal execution Snoops and interrupts allowed 5 STPCLK STPCLK Asserted De asserted kas Snoop Snoop Event Event Occurs Serviced 4 5 9 Y Y 4 HALT Grant Snoop State Snoop Event Occurs 3 Stop Grant State BCLK running x lt running Service snoops to caches Snoop Event Serviced gt Snoops and interrupts allowed SLP SLP Asserted De asserted 5 Sleep State BCLK running No snoops or interrupts allowed Datasheet In 7 2 3 7 2 4 7 2 5 Datasheet Intel Xeon Processor with 512 KB L2 Cache Stop Grant State State 3 When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only be d
143. r a logical 1 HIT HITM yo yo HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any front side bus agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together Since multiple agents may deliver snoop results at the same time HIT and HITM are wire OR signals which must connect the appropriate pins of all processor front side bus agents In order to avoid wire OR glitches associated with simultaneous edge transitions driven by multiple drivers HIT and HITM are activated on specific clock edges and sampled on specific clock edges IERR IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor front side bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT This signal does not have on die termination and must be terminated at the end agent See the appropriate Platform Design Guideline for additional information IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a
144. rence Figure 46 for a representation of the retention mechanism clip Retention mechanism clips must interface with the boxed processor retention mechanism area shown in Detail A in Figure 45 117 Intel Xeon Processor with 512 KB L2 Cache Figure 45 Retention Mechanism gt lt gt RE IN INCHES s 3 2 E E E 5 2 5 5 EIL 2 HE E RMPGA6035KTINT3D REY 2 C22044 TITLE X SI CASE CODE ORAWING NUMBER D SCALE DO NOT SCALE DRAWING SHEET OF 1 gt k 1 E y e ae z u 3 a e E m m E 118 Datasheet E ntel Intel Xeon Processor with 512 L2 Cache Figure 46 Boxed Processor Clip Datasheet 119 Y s y l L 3 291 13398 31 25 LON Gd 1 1 3096 el 00 han 3943134 zie E 67056759 1 1 8 3128 v Wiad Y 3NOZ SS3N1Y13 p xui a 1 18 2506 duos mul 5101 1 00 01210 7 418 3931102 NOISSIN 0022 a 9670817
145. requencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the trip point Once the temperature has returned to a non critical level and the hysteresis timer has expired modulation ceases and the TCC goes inactive Processor performance will be decreased by 50 when the TCC is active assuming a duty cycle that varies from 30 50 however with a properly designed and characterized thermal solution the TCC most likely will only be activated briefly during the most power intensive applications while at maximum chassis ambient temperature Datasheet 7 3 1 7 4 Datasheet Intel Xeon Processor with 512 KB L2 Cache For automatic mode the duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardware software drivers or interrupt handling routines The TCC may also be activated via On Demand mode If bit 4 of the ACPI Thermal Monitor Control Register is written to a 1 the TCC will be activated immediately independent of the processor temperature When using On Demand mode to activate the TCC the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Thermal Monitor Control Register In automatic mode the duty cycle is fixed anywhere within a range of 30 to 50 however in On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off
146. roup AC Specifications U 35 20 SMBus Signal Group AC Specifications nennen 35 21 BCLK Signal Quality Specifications nana 45 22 Ringback Specifications for AGTL and Asynchronous GTL Buffers 46 23 Ringback Specifications for TAP 47 24 Source Synchronous 400 MHz AGTL Signal Group Overshoot Undershoot Tolerance 53 25 Source Synchronous 200 MHz AGTL Signal Group Overshoot Undershoot Tolerance 53 26 Clock 100 MHz AGTL Signal Group Overshoot Undershoot Tolerance 54 27 Asynchronous GTL PWRGOOD and TAP Signal Groups Overshoot Undershoot Tolerance 54 28 INT mPGA Processor Package Dimensions sss nnne 59 29 Package Dynamic and Static Load Specifications sese 62 30 Processor Nap 63 31 Processor Material Properties 244424 63 38 Listing by Pin 22 eet tenetur 67 39 Listing by Pin Number 76 41 Signal aiaa 84 42 Processor Thermal Design 96 43 Power On Configuration Option Pins n 99 44 Processor Information ROM Formal
147. run at twice the core frequency which allows many integer instructions to execute in one half of the internal core clock period The Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The floating point and multi media units have been improved by making the registers 128 bits wide and adding a separate register for data movement Finally SSE2 adds 144 new instructions for double precision floating point SIMD integer and memory management for improvements in video multimedia processing secure transactions and visual internet applications Also part of the Intel NetBurst micro architecture the front side bus and caches on the Intel Xeon processor with 512 KB L2 cache provide tremendous throughput for server and workstation workloads The 400 MHz front side bus provides a high bandwidth pipeline to the system memory and I O It is a quad pumped bus running off a 100 MHz front side bus clock making 3 2 Gigabytes per second 3 200 Megabytes per second data transfer rates possible The Execution Trace Cache is a level 1 cache that stores approximately twelve thousand decoded micro operations which removes the decoder latency from the main execution path and increases performance The Advanced Transfer Cache is a 512 KB on die level 2 cache running at the speed of the processor core providing increased bandwidth over previous micro architectures In addition to the Intel NetBurst micro architectur
148. s otherwise noted all specifications in this table apply to all processor frequencies and cache sizes Specifications are for the edge rate of 0 3 4 0 V nS at the receiver All values specified by design characterization Please see Section 3 0 for maximum allowable overshoot Ringback between GTLREF 100 mV and GTLREF 100 mV is not supported Intel recommends simulations not exceed a ringback value of GTLREF 200 mV to allow margin for other sources of system noise O N Datasheet Table 23 Figure 21 Low to High Front Side Bus Receiver Ringback Tolerance for AGTL and Intel Xeon Processor with 512 KB L2 Cache Ringback Specifications for TAP Buffers Maximum Ringback 5 Transition with Input Diodes Present Unit Figure Notes TAP and oe LH VT max TO VT max V 23 1 2 3 4 5 TAP and L V min TO VT min Vz min V 24 i 2 3 4 5 NOTES 1 All signal integrity specifications are measured at the processor core pads 2 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes 3 Specifications are for the edge rate of 0 3 4 0 V nS 4 All values specified by design characterization 5 Please see section 3 3 for maximum allowable overshoot Asynchronous GTL Buffers Voc 10 Vcc GTLREF 10 Vcc Vss 4 Noise Margin
149. s regarding this socket Central Agent The central agent is the host bridge to the processor and is typically known as the chipset Flip Chip Ball Grid Array FCBGA Microprocessor packaging using flip chip design where the processor is attached to the substrate face down for better signal integrity more efficient heat removal and lower inductance Front Side Bus Front Side Bus FSB is the electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Intel Xeon processor with 512 KB L2 cache The entire processor in its INT nPGA package including processor core in its FC BGA package integrated heat spreader IHS and interposer Datasheet 1 2 Datasheet Intel Xeon Processor with 512 KB L2 Cache Integrated Heat Spreader IHS The surface used to attach a heatsink or other thermal solution to the processor Interposer The structure on which the processor core package and I O pins are mounted OEM Original Equipment Manufacturer Processor core The processor s execution engine All AC timing and signal integrity specifications are to the pads of the processor core Processor Information ROM PIROM An SMBus accessible memory device located on the processor interposer This memory device contains information r
150. s the serial input needed for JTAG specification support TDO Test Data Out transfers serial test data out of the processor provides the serial output needed for JTAG specification support Datasheet 91 Intel Xeon Processor with 512 KB L2 Cache Table 41 Signal Definitions Page 9 of 10 Name Type Description Notes TESTHI 6 0 All TESTHI 6 0 pins should be individually connected to VCC via a pull up resistor which matches the trace impedance within a range of 10 ohms TESTHI 3 0 and TESTHI 6 5 may all be tied together and pulled up to VCC with a single resistor if desired However utilization of boundary scan test will not be functional if these pins are connected together TESTHI4 must always be pulled up independently from the other TESTHI pins For optimum noise margin all pull up resistor values used for TESTHI 6 0 pins should have a resistance value within 20 percent of the impedance of the baseboard transmission line traces For example if the trace impedance is 50 Q then a value between 40 and 60 Q should be used The TESTHI 6 0 termination recommendations provided in the Intel Xeon processor datasheet are still suitable for the Intel Xeon processor with 512 KB L2 cache However Intel recommends new designs or designs undergoing design updates follow the trace impedance matching termination guidelines given in this section THERMTRIP Activ
151. serving BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BPRI Datasheet 85 Intel Xeon Processor with 512 KB L2 Cache Table 41 Signal Definitions Page 3 of 10 Name Type Description Notes BR0 BR 1 3 y o BR 3 0 Bus Request drive the BREQ S3 0 signals in the system The BREQ 3 0 signals are interconnected in a rotating manner to individual processor pins BR2 and BR3 must not be utilized in a dual processor platform design The table below gives the rotating interconnect between the processor and bus signals for dual processor systems BR 1 0 Signals Rotating Interconnect dual processor system Bus Signal Agent 0 Pins Agent 1 Pins BREQO BRO 1 BREQ1 BR1 BR0 During power up configuration the central agent must assert the BR0 bus signal All symmetric agents sample their BR 1 0 pins on active to inactive transition of RESETH The pin on which the agent samples an active level determines its agent ID All agents then configure their pins to match the appropriate bus signal protoco as shown below BR 1 0 Signal Agent IDs BR 1 0 Signals Rotating Interconnect dual proce
152. sor storage temperature 40 85 C 2 Any processor supply voltage with Voc respect to Vss oa hs u 1 AGTL buffer DC input voltage with 3 respect to Vss Bi 1479 Y Async GTL buffer DC input voltage Viena with respect to Vss 94 15 9 Y SMBus buffer DC input voltage with Vinsugus respect to Vss he 6 0 V 5 Max VID pin current 5 mA 1 This rating applies to any pin of the processor 2 Contact Intel for storage requirements in excess of one year Datasheet a ntel Intel Xeon Processor with 512 KB L2 Cache Datasheet Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Section 5 1 for the processor pin listings and Section 5 2 for the signal definitions The voltage and current specifications for all versions of the processor are detailed in Table 6 For platform planning refer to Figure 3 Notice that the graphs include Thermal Design Power TDP associated with the maximum current levels The DC specifications for the AGTL signals are listed in Table 8 The front side bus clock signal group and the SMBus interface signal group are detailed in Table 7 and Table 11 respectively The DC specifications for these signal groups are listed in Table 9 Table 6 through Table 11 list the processor DC specifications and are valid only while meeting specifications for case temperature Tcasg as specified in Chapter 6 0
153. ssor Information ROM PIROM The lower half 128 bytes of the SMBus memory component is an electrically programmed read only memory with information about the processor This information is permanently write protected Table 44 shows the data fields and formats provided in the Processor Information ROM Datasheet Table 44 Datasheet Intel Xeon Processor with 512 KB L2 Cache Processor Information ROM Format Page 1 of 2 Offset Section Ii Function Notes its Header 00h 8 Data Format Revision Two 4 bit hex digits 01 02h 16 EEPROM Size Size in bytes MSB first 03h 8 Processor Data Address Byte pointer 00 if not present 04h 8 2 Core Data Byte pointer 00h if not present 05h 8 L3 Cache Data Address Byte pointer 00h if not present 06h 8 Package Data Address Byte pointer 00h if not present 07h 8 Part Number Data Address Byte pointer if not present 08h 8 e Byte pointer 00h if present 09h 8 Feature Data Address Byte pointer 00h if not present 0Ah 8 Other Data Address Byte pointer 00h if not present OBh 16 Reserved Reserved ODh 8 Checksum 1 byte checksum Processor Data OE 13h 48 S spec Number Six 8 bit ASCII characters i h 6 Reserved Reserved most significant bits 2 Sample Production 00b Sample only 01 11b Production 15h 8 Checksum 1 byte checksum Processor Core Data 16
154. ssor system BR0 0 BR1 1 Agent ID During power on configuration the central agent must assert the BR0 bus signal All symmetric agents sample their BR 3 0 pins on the active to inactive transition of RESET The pin which the agent samples asserted determines it s agent ID These signals do not have on die termination and must be terminated at the end agent See the appropriate platform design guidelines for additional information BSEL 1 0 These output signals are used to select the front side bus frequency A BSEL 1 0 00 will select a 100 MHz bus clock frequency The frequency is determined by the processor s chipset and frequency synthesizer capabilities All front side bus agents must operate at the same frequency Individual processors will only operate at their specified front side bus FSB frequency On baseboards which support operation only at 100 MHz bus clocks these signals can be ignored On baseboards employing the use of these signals a 1 KQ pull up resistor be used See Table 2 Front Side Bus Clock Frequency Select Truth Table for BSEL 1 0 on page 17 for output values COMPT 1 0 0 must be terminated to Vss on the baseboard using precision resistors These inputs configure the AGTL drivers of the processor Refer to the appropriate platform design guidelines and Table 13 for implementation details 86 Datasheet In Intel Xeon TM
155. t A24 E14 Source Sync Input Output A25 D13 Source Sync Input Output A26 A9 Source Sync Input Output A27 B8 Source Sync Input Output Pin Name Pin No EM Direction A28 E13 Source Sync Input Output A29 D12 Source Sync Input Output A30 C11 Source Sync Input Output A31 B7 Source Sync Input Output A32 A6 Source Sync Input Output A33 A7 Source Sync Input Output A34 C9 Source Sync Input Output A35 C8 Source Sync Input Output A20M F27 GTL Input ADS D19 Common Input Output ADSTBO F17 Source Sync Input Output ADSTB1 F14 Source Sync Input Output APO E10 Common Clk Input Output AP1 D9 Common Clk Input Output BCLKO 4 Sys Bus Input BCLK1 W5 Sys Bus Clk Input BINIT F11 Common CIk Input Output BNR F20 Common Clk Input Output BPMO F6 Common Clk Input Output BPM1 F8 Common Clk Input Output BPM2 E7 Common Clk Input Output BPM3 F5 Common Clk Input Output BPM4 E8 Common CIk Input Output BPM5 E4 Common Input Output BPRI D23 Common Input BRO D20 Common Input Output Datasheet 67 Intel Xeon Processor with 512 KB L2 Cache Table 38 Pin Listing by Pin Name intel Table 38 Pin Listing by Pin Name
156. t signals No transitions or assertions of signals with the exception of SLP or RESET are allowed on the front side bus while the processor is in Sleep state Any transition on an input signal before the processor has returned to Stop Grant state will result in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor will reset itself ignoring the transition through Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the reset sequence Once in the Sleep state the SLP pin can be deasserted if another asynchronous front side bus event occurs The SLP pin should only be asserted when the processor and all logical processors within the physical processor is in the Stop Grant state SLP assertions while the processors are not in the Stop Grant state is out of specification and may result in illegal operation Bus Response During Low Power States While in AutoHALT Power Down and Stop Grant states the processor will process a front side bus snoop When the processor is in Sleep state the processor will not process interrupts or snoop transactions Thermal Monitor Thermal Monitor is a feature of the processor that allows system designers to lower the cost of
157. t will respond to the ARA Packet with its address in the seven most signifi cant bits The least significant bit is undefined and may return as a 1 or 0 See Section 7 4 8 for details on the Thermal Sensor Device addressing Table 51 SMBus Thermal Sensor Command Byte Bit Assignments Register Command Reset State Function RESERVED 00h RESERVED Reserved for future use TRR 01h 0000 0000 Read processor core thermal diode RS 02h N A Read status byte flags busy signal RC 03h 00XX XXXX Read configuration byte RCR 04h 0000 0010 Read conversion rate byte RESERVED 05h RESERVED Reserved for future use RESERVED 06h RESERVED Reserved for future use RRHL 07h 0111 1111 processor core thermal diode THIGH RRLL 08h 1100 1001 ud processor core thermal diode ow WC 09h N A Write configuration byte WCR 0Ah N A Write conversion rate byte RESERVED 0Bh RESERVED Reserved for future use RESERVED 0Ch RESERVED Reserved for future use WRHL ODh N A dia processor core thermal diode Tyigy WRLL OEh N A Mig processor core thermal diode ow OSHT OFh N A One shot command use send byte packet RESERVED 10h N A Reserved for future use Datasheet 109 a Intel Xeon Processor with 512 KB L2 Cache ntel Note 7 4 6 7 4 6 1 Table 52 7 4 6 2 110 All of the commands in Table 51 are for reading or writing registers in the SMBus thermal sensor except
158. tatus register then reads the slave ARA unless the fault condition persists Reading the Status Register alone or setting the mask bit within the Configuration Register does not clear the interrupt SMBus Device Addressing Of the addresses broadcast across the SMBus the memory component claims those of the form 1010XXXZb The XXX bits are defined by pullups and pulldowns on the system baseboard These address pins are pulled down weakly 10 KQ on the processor substrate to ensure that the memory components are in a known state in systems which do not support the SMBus or only support a partial implementation The Z bit is the read write bit for the serial bus transaction The thermal sensor internally decodes one of three upper address patterns from the bus of the form 001 IXXXZb 1001XXXZb or 0101 XXXZb The device s addressing as implemented uses the SM TS A 1 0 pins in either the HI LO or Hi Z state Therefore the thermal sensor supports nine unique addresses To set either pin for the Hi Z state the pin must be left floating As before the Z bit is the read write bit for the serial transaction Note that addresses of the form 0000XXXXb are Reserved and should not be generated by an SMBus master The thermal sensor samples and latches the SM TS A 1 0 signals at power up and at the starting point of every conversion System designers should ensure that these signals are at valid input levels before
159. tely 3 4 BCLK period 7 5 nS after the first falling edge of DSTBp 13 This specification applies only to DSTBN 3 0 and is measured to the second falling edge of the strobe 14 This specification reflects a typical value not a minimum or maximum Miscellaneous Signals AC Specifications T Parameter Min Max Unit Figure Notes T35 Async GTL input pulse width 2 N A BCLKs 1 2 3 4 T36 PWRGOOD to RESET de assertion time 1 10 mS 12 1 2 3 4 T37 PWRGOOD inactive pulse width 10 N A BCLKs ie i 1 2 3 4 T38 PROCHOT pulse width 500 us 15 6 T39 THERMTRIP to Vcc Removal 0 5 s 16 1 Unless otherwise noted all specifications in this table apply to all processor frequencies and cache sizes G gt All AC timings for the Asynchronous GTL signals are referenced to the BCLKO rising edge at Crossing Voltage Vcnoss All Asynchronous GTL signal timings are referenced at GTLREF These signals may be driven asynchronously Refer to Section 7 2 for additional timing requirements for entering and leaving low power states Refer to the PWRGOOD signal definition in Section 5 2 for more detail information on behavior of the signal Length of assertion for PROCHOT does not equal internal clock modulation time Time is allocated after the assertion of PROCHOT for the processor to complete current instruction execution Datasheet intel Table 18 Table 19 Tab
160. tes their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least one millisecond after Vcc and BCLK have reached their proper specifications On observing active RESET all front side bus agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10ms A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated at the end agent See the appropriate Platform Design Guideline for additional information RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor front side bus agents RSP RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor front side bus agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity
161. the one shot command OSHT register The one shot command forces the immediate start of a new conversion cycle If a conversion is in progress when the one shot command is received then the command is ignored If the thermal sensor is in stand by mode when the one shot command is received a conversion is performed and the sensor returns to stand by mode The one shot command is not supported when the thermal sensor is in auto convert mode Writing to a read command register or reading from a write command register will produce invalid results The default command after reset is to a reserved value 00h After reset Receive Byte SMBus packets will return invalid data until another command is sent to the thermal sensor SMBus Thermal Sensor Registers Thermal Reference Registers Once the SMBus thermal sensor reads the processor thermal diode it performs an analog to digital conversion and stores the result in the Thermal Reference Register TRR The supported range is 127 to 0 decimal and is expressed as an eight bit number representing temperature in degrees Celsius This eight bit value consists of seven data bits and a sign bit MSB as shown in Table 52 The values shown are also used to program the Thermal Limit Registers The values of these registers should be treated as saturating values Values above 127 are represented as 127 decimal while values of zero and below may be represented as 0 to 127 decimal If the thermal sensor
162. the thermal sensor powers up This should be done by pulling the pins to SM_Vcc or Vss via a 1 or smaller resistor or leaving the pins floating to achieve the Hi Z state If the designer desires to drive the TS A 1 0 pins with logic the designer must ensure that the pins are at input levels of 3 3V or OV before SM_V cc begins to ramp The system designer must also ensure that their particular implementation does not add excessive capacitance to the address inputs Excess capacitance at the address inputs may cause address recognition problems Refer to the appropriate platform design guidelines document and the System Management Bus Specification Figure 42 on page 104 shows a logical diagram of the pin connections Table 56 and Table 57 describe the address pin connections and how they affect the addressing of the devices 113 Intel Xeon Processor with 512 KB L2 Cache 114 Table 56 Thermal Sensor SMBus Addressing Note Intel Address Hex 2 Device Select 8 bit Address Word on Serial Bus SM TS A1 SM TS 0 b 7 0 0 0011000Xb 3Xh 0011 72 0011001Xb 1 0011010Xb 0 72 0101001Xb 5Xh 0101 72 72 0101010Xb 1 72 0101011Xb 0 1 1001100Xb 9Xh 1001 72 1 1001101Xb 1 1 1001110Xb NOTES 1 Upper address bits are decoded in conjunction with the select pins 2 A tri state or Z state on this pin is achieved by leaving this pin unconnected System management software must be aware of th
163. thermal solutions without compromising system integrity or reliability By using a factory tuned precision on die temperature sensor and a fast acting thermal control circuit TCC the processor without the aid of any additional software or hardware can control the processors die temperature within factory specifications under typical real world operating conditions Thermal Monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications instead of being designed to the much higher maximum processor power envelopes Thermal Monitor controls the processor temperature by modulating starting and stopping the internal processor core clocks The processor clocks are modulated when the thermal control circuit TCC is activated Thermal Monitor uses two modes to activate the TCC Automatic mode and On Demand mode Automatic mode must be enabled via BIOS which is required for the processor to operate within specifications Once automatic mode is enabled the TCC will activate only when the internal die temperature is very near the temperature limits of the processor When the TCC is enabled and a high temperature situation exists i e TCC is active the clocks will be modulated by maintaining a duty cycle within a range of 30 50 Clocks will not be off or on more than 3 0 ms when the TCC is active Cycle times are processor speed dependent and will decrease as processor core f
164. to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used at the same time Automatic mode is enabled however if TCC is enabled via On Demand mode at the same time automatic mode is enabled AND a high temperature condition exists the fixed duty cycle of the automatic mode will override the duty cycle selected by the On Demand mode An external signal PROCHOT processor hot is asserted at any time TCC is active either in Automatic or On Demand mode Bus snooping and interrupt latching are also active while the TCC is active The temperature at which the thermal control circuit activates is not user configurable and is not software visible In an MP system Thermal Monitor must be configured identically for each processor within the system Besides the thermal sensor and thermal control circuit the Thermal Monitor feature also includes one ACPI register one performance counter register three model specific registers MSR and one pin PROCHOT All are available to monitor and control the state of the Thermal Monitor feature Thermal Monitor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT i e upon the activation deactivation of TCC Refer to Volume 3 of the 1A32 Intel Architecture Software Developer s for specific register and programming details If automatic mode is disabled the processor will be operating out of specification and cannot be guaranteed to provide reliable res
165. ts the corresponding option 2 The Intel Xeon processor with 512 KB L2 cache does not support this feature therefore platforms utilizing this processor should not use these configuration pins 3 Intel Xeon processor with 512 KB L2 cache utilize only BRO and BR1 signals 2 way platforms must not utilize BR2 and BR3 signals Clock Control and Low Power States The processor allows the use of AutoHALT Stop Grant and Sleep states to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 41 for a visual representation of the processor low power states Due to the inability of processors to recognize bus transactions during the Sleep state multiprocessor systems are not allowed to simultaneously have one processor in Sleep state and the other processor in the Normal or Stop Grant state Normal State State 1 This is the normal operating state for the processor 99 Intel Xeon Processor with 512 KB L2 Cache n 7 2 2 AutoHALT Powerdown State State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to eithe
166. ults Regardless of enabling of the automatic or On Demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 135 C At this point the front side bus signal THERMTRIP will go active and stay active until the processor has cooled down and RESET has been initiated THERMTRIP activation is independent of processor activity and does not generate any bus cycles If THERMTRIP is asserted processor core voltage Vcc must be removed within the timeframe defined in Figure 16 Thermal Diode The processor incorporates an on die thermal diode A thermal sensor located on the processor may be used to monitor the die temperature of the processor for thermal management long term die temperature change purposes This thermal diode is separate from the Thermal Monitor s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor See Section 7 4 4 for details System Management Bus SMBus Interface The processor includes an SMBus interface which allows access to a memory component with two sections referred to as the Processor Information ROM and the Scratch EEPROM and a thermal sensor on the substrate The SMBus thermal sensor may be used to read the thermal diode mentioned in Section 7 3 1 These devices and their features are described below See Chapter 4 0 for the physical location of these devices 103 a Intel Xeon
167. ut Y21 DSTBNO Source Sync Input Output Y22 Power Other Y23 D5 Source Sync Input Output Y24 D2 Source Sync Input Output Y25 vss Power Other Y26 D0 Source Sync Input Output Y27 Reserved Reserved Reserved Y28 Reserved Reserved Reserved Y29 SM_TS1_A1 SMBus Input Y30 VCC Power Other Y31 VSS Power Other AA1 VCC Power Other AA2 vss Power Other AA3 BSEL0 Power Other Output2 81 Intel Xeon TM Processor with 512 KB L2 Cache Table 39 Pin Listing by Pin Number Signal intel Table 39 Pin Listing by Pin Number Pin No Pin Name Buffer Type Direction AA4 VCC Power Other AA5 VSSA Power Other Input AA6 VCC Power Other AA7 TESTHI4 Power Other Input AA8 D61 Source Sync Input Output AA9 VSS Power Other AA10 054 Source Sync Input Output 11 053 Source Input Output 12 Power Other AA13 D48 Source Sync Input Output AA14 D49 Source Sync Input Output 15 vss Power Other AA16 D33 Source Sync Input Output AA17 vss Power Other AA18 D24 Source Sync Input Output AA19 D15 Source Sync Input Output AA20 VCC Power Other AA21 D11 Source Sync Input Output AA22 D10 Source Sync Input Output AA23 VSS Power Other AA24 D6 Source Sync Input
168. ut Output D12 AB20 Source Sync Input Output D51 AB12 Source Sync Input Output D13 AB22 Source Sync Input Output D52 AB13 Source Sync Input Output D14 AB19 Source Sync Input Output D53 AA11 Source Sync Input Output D15 AA19 Source Sync Input Output D54 AA10 Source Sync Input Output D16 AE26 Source Sync Input Output D55 AB10 Source Sync Input Output D17 AC26 Source Input Output 056 AC8 Source Sync Input Output D18 AD25 Source Syne Input Output D57 AD7 Source Sync Input Output D19 AE25 Source Sync Input Output D58 AE7 Source Sync Input Output D20 AC24 Source Syne Input Output D59 AC6 Source Sync Input Output D21 AD24 Source Sync Input Output D60 5 Source Sync Input Output D22 AE23 Source Sync Input Output D61 AA8 Source Sync Input Output D23 AC23 Source Syne Input Output D62 Y9 Source Sync Input Output D24 AA18 Source Sync Input Output D63 AB6 Source Sync Input Output D25 AC20 Source Sync Input Output DBSY F18 Common Clk Input Output D26 AC21 Source Syne Input Output DEFER C23 Common Input D27 AE22 Source Sync Input Output DBIO AC27 Source Sync Input Output D28 AE20 Source Sync Input Output DBI1 AD22 Source Sync Input Output D29 AD21 Source Sync Input Output DBI2 AE12 Source Sync Input Output D30 AD19 Source Sync Input Output DBI3 AB9 Source Sync Input Output D31 AB17 Source Syne Input Output DPO AC18 Common Clk In
169. wn as Symmetric Multiprocessing SMP systems Intel Xeon DP Dual Processor processors should only be used in SMP systems which have two or fewer symmetric agents State of Data The data contained in this document is subject to change It is the best information that Intel is able to provide at the publication date of this document 13 Intel Xeon Processor with 512 KB L2 Cache 1 3 14 References Intel The reader of this specification should also be familiar with material and concepts presented in the following documents Guidelines Document Intel Order Number AP 485 Intel Processor Identification and the CPUID Instruction 241618 IA 32 Intel Architecture Software Developer s Manual Volume I Basic Architecture 245470 Volume II Instruction Set Reference 245471 Volume System Programming Guide 245472 Intel Xeon Processor and Inte 860 Chipset Platform Design Guide 298252 Intel Xeon Processor Thermal Design Guidelines 298348 603 Pin Socket Design Guidelines 249672 Intel Xeon Processor Specification Update 249678 CKO00 Clock Synthesizer Driver Design Guidelines 249206 VRM 9 0 DC DC Converter Design Guidelines 249205 VRM 9 1 DC DC Converter Design Guidelines 298646 Dual Intel Xeon Processor Voltage Regulator Down VRD Design Hali 298644 Guidelines ITP700 Debug Port Design Guide 249679 Intel Xeon Processor with 512 KB L2 Cach

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