Kingston Technology ValueRAM 512MB 533MHz DDR2 ECC Fully Buffered CL4 DIMM Single Rank, x8
Contents
1. KING OI Memory Module Specifications ue AMA KVR533D2S8F4 512 512MB 64M x 72 Bit PC2 4200 CL4 ECC 240 Pin FBDIMM Description This document describes ValueRAM s 512MB 64M x 72 bit PC2 4200 CL4 SDRAM Synchronous DRAM fully buffered ECC single rank memory module This module is based on nine 64M x 8 bit 533MHz DDR2 FBGA components The module also includes an AMB device Advanced Memory Buffer The electrical and mechanical specifications are as follows Feature e FBDIMM Module 240 pin e JEDEC Standard R C A e Memory Organization 1 rank of x8 devices e DDR2 DRAM Interface SSTL 18 o DDR2 Speed Grade 533 Mbps e CAS Latency 4 4 4 o Module Bandwidth 4 2 GB s o FBDIMM Channel Peak Throughput 6 4 GB s e DRAM VDD VDDQ 1 8V e AMB VCC VCCFBD 1 5V e EEPROM VDDSPD 3 3V typical e Heat Spreader AMB only heat sink o PCB Height 30 35mm double side e RoHS Compliant VALUERAMO478 001 A00 02 28 06 Page 1 ie Kingst Ston DDR2 240 pin FBDIMM Pinout GEHE pere GERE ee Side Side Side Side Side Side Side Side E ives Tep en CI em CINA BLU HEURE 32 PNS wa SNS fef yss fise Ves dam a 3 Y t9 Y Pos ves wo vs fef emo jus sw ffos rss fats sso Ves jji Vos Pos eno fisa sma fej Pwo ies smo fos Pos zw ss 5 Y t5 Y os Pre fos Sw e we ies Vss s de mel Me Vm t5 Yoo e en e O pun e swa pse ze ss T Y t Yoo ens per m IM or Ps TE 8 Ves res2. ii N N O e Y N N N si co al o O o SS2 O 00 N N 00 N 29 e N amp N N O N e wo co Se C2 O eo e e A E NIN O amp oa A N O These pin positions are reserved for future architecture flexibility 1 The following signals are CRC bits and thus appear out of the normal sequence PN12 PN12 SN12 SN12 PN13 PN13 SN13 SN13 PS9 PS9 SS9 SS9 VALUERAMO478 001 A00 Page 2 R Kingston DIMM Connector Pin Description PinName PinDescription System Clock Input positive line nro secondary Nerhbound Daa postie Ines M so secondary Nontiwouna Data neg nes h ste secondary Southbound Data poste nes SSS AAA Ue Voltage ID These pins must be unconnected for DDR2 based Fully Buffered DIMMs VID 0 is Vpp value OPEN 1 8 V GND 1 5 V VID 1 is Vcc value OPEN 1 5 V GND 12V RESET The DNU M Test pin provides an external connection on R Cs A D for testing the margin of Vref which is produced by a voltage divider on the module It is not intended to be used in normal system operation and must not be VID 1 0 DNU M Test connected DNU in a system This test pin may have other features on future card designs and if it does will be included in this specification at that time N N d 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 Eight pins
3. 16 65 16 62 12 10 3 00 DIA 4 PLACES 4 30 0 1 30 2 15 5 20 WY LJ e o DETAIL A rr o 1 50 DIA R 0 75 000 m B ow 0 10 can 2 PLACES EE Tu 2 PLACES oo Dm DO CJ Coco 0 346 8 8 MAX with heat sink le Units inches millimeters 45 x 0 0071 0 18 NM 0 047 1 19 ene 08 y 0 042 1 06 0 054 1 37 Detail A 0 046 1 17 VALUERAMO478 001 A00 Page 7
4. vos f Ps js 2 Ves 12 vec fel vos 10 Vos fiso Veo f4 Pms eo 11 Ve ro ys e e 12 Veo wz Yee Paz Ves fpe 1 Veo t99 Veo se e ve E Ves ros Ves e nr pe mr s Ver ms Wer fas m ros m aj 104 551 e vor fise voo Pas Vos e vss rs we 17 RESET 137 onum rest ar ves fier ves ve Ps2 196 DADES pia is sm faj Ps2 jio 19 meu aso Reue ao PN roo sn e vos 196 2 rt lao meo so ves mo Vos 7o eso no ve e ve si eno ari sne eo Ps 20 sss 22 eno reo sno sj Pm we SNe DN RN n 2 mel wo S9 Ves wa Vos fef Pse 22 24 Ves t Vos OEA CEN es Ps s e m x we oe ae os mr jus svo e vos jm ve rs 2 PNT e 5 DETON OEA eo DETS 3 27 Ves wr Vss LIE ALONE NN 86 mr 2061 Reu er EI sn se vs rm rare ea ser n os PNZ ue sa Poo ves mo vs Ye ves fff Vos ro soa zo so 00 Ves iso ves eo eno wo sw eo ves 2o9 ves wo scr o sa ojo ELI di ivwi re fre 9 f d RFU Reserved Future Use These pin positions are reserved for forwarded clocks to be used in future module implementations UU Z Z i Z Z SN5 Co Vss 8 Vss lt N Oo 00 co o o PS7 220 SS7 c o BES e IE amp oo te NN N uum O al co 9 co N o wo PS8 223 SS8 oO e e o O O gt N N N IN 3 e e al FU 225 RFU
5. S DQS PSO PS9 SS0 SS9 CBO I O 0 DQ0 DQ63 A 80 5 CS all SDRAMs CB1 I O 1 D8 CB0 CB7 CKEO gt CKE all SDRAMs CB2 1 0 2 paso pasi7____ M CB3 1 0 3 Dasopass B CB4 I O 4 scl ODT gt ODT all SDRAMs CB5 1 0 5 SDA L BAO0 BA2 all SDRAMs CB6 1 0 6 RA A0 A15 all SDRAMs SA1 SA2 2 CB7 1 0 7 SA0 NM RAS all SDRAMs LL CAS all SDRAMs RESET L WE all SDRAMs l SCK SCK H CK CK all SDRAMs VTT Terminators Vcc L AMB All address command control clock y VT SPD AMB Notes Serial PD DO D8 AMB 1 DQ to I O wiring may be changed within a byte SCL WEM DO D8 2 There are two physical copies of each address command con WP A0 A1 A2 trol clock SA0 SA1 SA2 DO D8 SPD AMB VALUERAMO478 001 A00 Page 4 E kingston Architecture Advanced Memory Buffer Pin Description FB DIMMChamelSigals 89 DDR2 Interface Signals passu pat seres peste me B raso Date Saves regains e baspireyoMes pau Swobes 4 DRAM onb pose Ines These signals ae driven ow io x8 DRAM on wes o _ pasa pata Steve DRAM ony negate Ines ko A TN Ceao sazo eenas Sid Op KE Ot Enable ne prank SONT CLK 1 0 used on 9 and 18 device DIMMs CLK 3 0 used on 36 device DIMMs CLK 3 2 should be out CLK 5 0 put disabled when not in use GLK 0 DDRC C14 DDRC B18 DDRC C18 VALUERAMO478 001 A00 Page 5 ie kingston Advanced Memory Buffer Pin Descripti
6. on SPD Bus Interface Signals SCL Serial Presence Detect SPD Clock Input SDA SPD Data Input Output SA 2 0 SPD Address Inputs also used to select the DIMM number in the AMB Miscellaneous Signals PLLTSTO VCCAPLL Analog VCC for the PLL Tied with low pass filter to VCC 1 VSSAPLL Analog VSS for the PLL Tied to ground on the AMB die Do not tie to ground on the DIMM 1 TEST pin Leave floating on the DIMM TESTLO pin Tie to ground on the DIMM 9 BFUNC Tie to ground to set functionality as buffer on DIMM 1 RESET AMB reset signal No connect Many NC are connected to VDD on the DIMM to lower the impedance of the VDD power islands R Reserved for Future Use Power Ground Signals D O 3 163 1 1 1 NC FU a 1 System Clock Signals SCK and SCK switch at one half the DRAM CK CK frequency 2 TESTLO AB20 and TESTLO AC20 should be configured for debug purposes on prototype DIMMs each pin should have a zero ohm resistor pulldown to ground and an unpopulated resistor pullup to VCC These resistors can be replaced on production DIMMs with a direct connection to ground N S N Jal g C9 VALUERAMO478 001 A00 Page 6 ie kingston Package Dimensions Units 7 millimeters La 133 35 d R 0 75 8 PLACES 0 mM 5 ce O O a uw M OY co co st F iis dis S o wo d e 1 19 DIA o 3 a o m un S 0 10 M ni i n p 24 40 S
7. reserved for forwarded clocks eight pins reserved for future architecture flexibility VALUERAMO478 001 A00 Page 3 E kingston Functional Block Diagram SO DQSO DQSO DQS9 o DM NU ae DOS BML NULL cs pas DaS Bos DOS RDAS ERRE DQ33 1104 D4 Dus 1102 Dus 1 03 nos 110 4 ae cO oo 106 BO 107 DQS1 DQS5 DQS1 DQS5 DQS10 DQS14 DM DM NU aa SO RDOS ADOS CS DQS DAS T Das ADOS CS DOS Das Dae o DQ41 O1 D 1 01 D1 DQ42 5 DQ10 1 0 2 DO43 I O 2 DQ11 1 0 3 DO44 0 3 DQ12 O 4 DO45 I O 4 DQ13 1 0 5 DOQ46 I O 5 DQ14 1 0 6 DQ47 I O 6 DQ15 1107 O 7 DQS2 DQS6 DQS2 DQS6 DQS11 DQS15 aS DM A SOS RDas peas CS DAS DAS RDQS spas CS DOS Das DQ16 1 00 DQ48 1 0 0 DQ17 1 0 1 D2 DQ49 O 1 D6 DQ18 1 0 2 DQ50 I O 2 DQ19 1 0 3 DQ51 1 0 3 DQ20 3 1 0 4 DQ52 I O 4 DQ21 1 0 5 DQ53 1 0 5 DQ22 1 0 6 DQ54 I O 6 DQ23 1 0 7 DQ55 1 0 7 DQS3 DQS7 DQS3 DQS7 DQS12 DQS16 gt DM NU cs DOS ADOS Nes CS Das DAS RDQS gpas CS PAS DAS DQ24 l O 0 DQ56 I O 0 DQ25 1 0 1 D3 DQ57 O 1 D7 DO27 1 03 DQ59 1 0 3 DQ31 41 1 0 7 DQ63 O7 DQS8 DQS8 PNO PN13 SNO SN13 ES PNO PN13 SNO SN13 PSO PS9 SS0 SS9 RDQS ADOS CS DQ
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