takeMS Ddr 512mb / 400 PC3200 Bulk
Contents
1. 512M Bytes for Unbuffered amp Non ECC Module DDR400 use 32Mx8 16pcs Byte Description Function Hex Value No 0 Number of Serial PD Bytes used 128 bytes 80h 1 Total number of Bytes in Serial PD device 256 bytes 08h 2 Fundamental Memory Type DDR SDRAM 07h 3 of Row Addresses on this assembly 13 ODh 4 of Column Addresses on this assembly 10 OAh 5 of Physical Banks on DIMM 2 ROWS 02h 6 Data Width of this assembly 64 bit 40h 7 Data Width of this assembly Continued 0 00h 8 Voltage Interface Level of this assembly SSTL_2 5V 04h 9 DDRAM Cycle time at CAS Latency 2 5 5ns 50h 10 DDRAM Access from Clock at CAS Latency 2 5 0 7 ns 70h 11 DIMM configuration type Non parity Parity or ECC Non parity 00h 12 Refresh Rate Type 7 8 US 82h 13 Primary SDRAM Width X8 bit 08h 14 Error Checking SDRAM Width None 00h 15 Min Clock Delay Back to Back Random Column Access Tecd 1 clk Oth 16 Burst Lengths Supported 2 4 8 Deh 17 Number of Banks on SDRAM Device 4 Banks 04h 18 CAS Latency 2 5 08h 19 Chip Select Latency 0 clk Oih 20 Write Latency 1 clk 02h 21 DDR SDRAM Module Attributes Unbuffer 20h o 0 2v voltage 22 DDRAM Device Attributes General tolerahce 00h 23 _ DDRAM Cycle time at CAS Latency 2 7 5ns 75h 24 DDRAM Access from Clock at CAS Latency 2 0 7 ns 70h 25 _ DDRAM2. 256M Bytes for Unbuffered amp Non ECC Module DDR400 use 32Mx8 8pcs Byte Description Function Hex Value No 0 Number of Serial PD Bytes used 128 bytes 80h 1 Total number of Bytes in Serial PD device 256 bytes 08h 2 Fundamental Memory Type DDR SDRAM 07h 3 of Row Addresses on this assembly 13 ODh 4 of Column Addresses on this assembly 10 OAh 5 of Physical Banks on DIMM 1 ROWS Oth 6 Data Width of this assembly 64 bit 40h 7 Data Width of this assembly Continued 0 00h 8 Voltage Interface Level of this assembly SSTL_2 5V 04h 9 DDRAM Cycle time at CAS Latency 2 5 5ns 50h 10 DDRAM Access from Clock at CAS Latency 2 5 0 7 ns 70h 11 DIMM configuration type Non parity Parity or ECC Non parity 00h 12 Refresh Rate Type 7 8 US 82h 13 Primary SDRAM Width X8 bit 08h 14 Error Checking SDRAM Width None 00h 15 Min Clock Delay Back to Back Random Column Access Tecd 1 clk Oth 16 Burst Lengths Supported 2 4 8 Deh 17 Number of Banks on SDRAM Device 4 Banks 04h 18 CAS Latency 2 5 08h 19 Chip Select Latency 0 clk Oih 20 Write Latency 1 clk 02h 21 DDR SDRAM Module Attributes Unbuffer 20h o 0 2v voltage 22 DDRAM Device Attributes General tolerahce 00h 23 _ DDRAM Cycle time at CAS Latency 2 7 5ns 75h 24 DDRAM Access from Clock at CAS Latency 2 0 7 ns 70h 25 _ DDRAM Cycle ti
3. Pin Pin Description Pin Pin Description CKO CKO CK1 CK1 CK2 CK2 Differential Clock Inputs VDDQ DQs Power Supply CSO Chip Select Input VSS Ground CKEO Clock Enable Input VREF Reference Power Supply RAS CAAS WE Command Sets Inputs VDDSPD Power Supply for SPD AO ATI Address SAO SA2 EEPROM Address Inputs BAO BA1 Bank Address SCL EEPROM Clock DQO DQ63 Data Inputs Outputs SDA EEPROM Data I O DQS0 DQS7 Data Strobe Inputs Outputs VDDID VDD Identification Flag DMO DM7 Data in Mask DU Do not Use VDD Power Supply NC No Connection PIN ASSIGNMENT PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME 1 VREF 32 A5 62 VDDQ 93 VSS 124 VSS 154 RAS 2 DQO 33 DQ24 63 JANE 94 DQ4 125 A6 155 DQ45 3 VSS 34 VSS 64 DQ41 95 DQ5 126 DQ28 156 VDDQ 4 DQ1 35 DQ25 65 CAS 96 VDDQ 127 DQ29 157 CSO 5 DQSO 36 DQS3 66 VSS 97 DMO 128 VDDQ 158 CS1 6 DQ2 37 A4 67 DQS5 98 DQ6 129 DM3 159 DM5 Ti VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS 8 DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46 9 NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47 10 NC 41 A2 71 NC 102 NC 133 DQ31 163 NC 11 VSS 42 Vss 72 DQ48 103 A13 134 CB4 164 VDDQ 12 DQ8 43 Al 73 DQ49 104 VDDQ 135 CB5 165 DQ52 13 DQ9 44 CBO 74 VSS 105 DQ12 136 VDDQ 166 DQ53 14 DQS1 45 CB1 75 CK2 106 DQ13 137 CK1 167 NC 15 VDDQ 46 VDD 76 CK2 107 DM1 138 CK1 168 VDD 16 CKO 47 DQS8 77 VDDQ 108 VDD 139 VSS 169 DM6 17 CKO 48 AO 78 DQS6 109 DQ14 140 DM8 170 D
4. CK1 CK1 Wire per clock loading table wiring diagrams BA0 BA1 BA0 BA1 SDRAMs D0 D7 Notes ERY 1 DQ to I O wiring is shown as recommended AQ A114 A0 A11 SDRAMs DO D7 but may be changed IRAS IRAS SDRAMs DO D7 2 DQ DQS DMICKE S relationships must be maintained as shown ICAS ICAS SDRAMs DO D7 CKEOQ CKE SDRAMs D0 D7 ANE WE SDRAMs DO D7 3 DQ DQS DM DQS resistors 22 Ohms 4 VDDID strap connections for memory device VDD VDDQ Strap out open VDD VDDQ Strap In Vss VDD VDDQ 184 PIN x64 DDR SDRAM DIMM 1 Bank with x8 DDR SDRAMs 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM BLOCK DIAGRAM DM wo 10 6 won D4 VOO 05 0 4 0 3 02 DOIT Ach DQ1g DO dg DQ20 2 DL a DU A A DO DOG DM3 DM DQ24 CH Won VO7 DC Cl UO VO DQ26 vOo6 VO 1 DQ2 vO7 OO DQ28 vo2 V05 DQ29 Web UO 4 DQ30 vo4 0 3 DOG vO5 V02 Serial PD DO D15 DO D15 CKOJCKO DO D15 CK1 CK1 CK2 CK2 Wire per clock loading tabla wiring diagrams Notes BA0 BA1 gt BAD BA1 SDRAMs DO D15 1 DQ to V O wiring is shown as recommended AQ A11 _ AO A11 SDRAMs DO D15 but may be changed maintained as shown IRAS RAS SDRAMs D0 D15 3 DQ DQS DM DQS resistors 22 Ohms ICAS CAS SDRAMs DO D15 4 VDDID strap connections
5. for memory device VDD VDDQ CKEO gt CKE SDRAMs D0 D7 Strap out open VDD VDDQ WE ANE SDRAMs DO D15 Strap In Vss VDD VDDQ 184 PIN x64 DDR SDRAM DIMM 2 Bank with x8 DDR SDRAMs 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM Electrical Characteristics Operating Conditions Absolute Maximum Ratings Parameter Symbol Note Test Tmax _ Condition Voltage on I O pins relative to Veg En Your 0 5 Vona m 0 5 Voltage on Inputs relative to Veg Kw Jes f jee v Voltage on Vpn supply relative to Veg ee E C a Voltage on Vono supply relative to Vss Koa fes Lag V S Operating Temperature Ambient a Ce CC Storage Temperature Tss lss LL konn J e l Power dissipation per SDRAM component fb LD Lt w Short Circuit Output Current Kaze Jon jm j Attention Permanent device damage may occur if Absolute Maximum Ratings are exceeded Functional operation should be restricted to recommended operation conditions Exceeding only one of these values for extended periods of time affect device reliability and may cause irreversible damage to the integrated circuit Supply Voltage Levels Parameter Limit Values e Note Test Condition VN fox 166 MHz IV few gt 166 MHz fag 3166 MHz Be o al PS in zu jej sup Device Supply Voltage Foo Device Supply Voltage Output Supply Voltage Vona Output Supply Voltage ona zr DER for gt 166 MHz 1 Input Reference Voltage Vig
6. timing but they are not necessarily tested on each device 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM 7 Aus and fz transitions occur in the same access time windows as valid data transitions These parameters are not referred to a specific voltage level but specify when the device is no longer driving HZ or begins driving LZ 8 The specific requirement is that DOS be valid HIGH LOW or some point on a valid transition on or before this CK edge A valid transition is defined as monotonic and meeting the input slew rate specifications of the device When no writes were previously in progress on the bus DOS will be transitioning from Hi Z to logic LOW If a previous write was in progress DOS could be HIGH LOW or transitioning from HIGH to LOW at this time depending on pass 9 The maximum limit for this parameter is not a device limit The device operates with a greater value for this parameter but system performance bus turnaround degrades accordingly 10 Fast slew rate gt 1 0 Vins slow slew rate gt 0 5 V ns and lt 1 Vins for command address and CK amp CK slew rate gt 1 0 Wns measured between Tous and Tote 11 For each of the terms if not already an integer round to the next highest integer fog is equal to the actual system clock cycle time 12 A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device Serial Presence Detect 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM
7. 4 5 3 S H DQ output access time from CK CK ns m idili O A Ea aolo n oD St CH CH DOS output access time from CK CK 0 5 Ins 745 CK high level width ton 0 45 0 55 ty Inn CK low level width R 0 45 0 55 DO S min o Lui 29 SE le ez CL 2 0 945 Clock Half Period Clock cycle time K N 9j oj N ra ej Sjo N 5 Ku DQ and DM input hold time ns 2 3 4 5 DO and DM input setup time Be 2 3 4 5 Sta ns a ET a Control and Addr input pulse width each fipy input DQ and DM input pulse width each input fop tbd Jee Loo Data out high impedance time from CK CK coe Boe lar 2 3 4 5 7 Data out low impedance time from CK CK fz Log 06 jns 279457 Write command to 1 DOS latching tooss 0 75 1125 IG P9 transition DQS DQ skew DOS and associated DQ fhoso 0 40 TSOPII 79415 signals Data hold skew factor Ka 0 50 TSOP 255 DODAS output hold time tons fup Z 27345 fans 2y3 4 5 D W a DOS input low high pulse width write foosLH tow cycle 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM AC Timing Absolute Specifications contd Parameter DOG falling edge to CK setup time write cycle DOG falling edge hold time from CK write cycle Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time Address and control input hold time Read pr
8. Cycle time at CAS Latency 1 5 None 00h 26 DDRAM Access from Clock at CAS Latency 1 5 None 00h 27 Minimum Row Precharge Time tRP 15 ns 3Ch 28 Minimum Row Active to Row Active delay tRRD 10 ns 28h 29 Minimum RAS to CAS delay tRCD 15 ns 3Ch 30 Minimum Active to Precharge Time tRAS 40 ns 28h 31 Module Bank Density 256M of 1 row 40h 32 Address and Command Input Setup Time Before Clock 0 6 ns 60h 33 Address and Command Input Hold Time After Clock 0 6 ns 60h 34 Data Data Mask Input Setup Time Before Data Strobe 0 4 ns 40h 35 Data Data Mask Input Hold Time After Data Strobe 0 4 ns 40h 36 40 Reserved Reserved 00h 41 Minimum active auto refresh time tRC 55 ns 37h 42 Minimum auto refresh to active command period tRFC 70 ns 46h 43 Maximum cycle time Tck max 10 ns 28h 44 Maximum DQS DQ skew time tDQSQ 0 4 ns 28h 45 Maximum read data hold skew factor tQHS 0 50 ns 50h 46 61 Reserved Reserved 00h 62 SPD Revision Rev0 0 00h 63 _ Checksum for Bytes 0 62 BEh 64 71 Manufacturer s JEDEC ID Code 7F 7F 7F 58h 72 Module Manufacturing Location 31h 42 44 35 31 32 73 90 Module Part Number BD512TEC500 54 45 43 35 30 30h 91 92 Module Revision Code Reserved 00h 93 94 Module Manufacturing Date YY WW 95 98 Module Serial Number Reserved 00h 99 127 Manufacturer s Specific Data Reserved 00h 128 255 Open for customer use Reserved 00h 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM PACKAGE DIMENSIO
9. NS lt 33 44mm 0 15mm gt gt _ 2 86mm 4 1lmm 29 55mm 4 0 15mm k 3 58mm 4 1mm K 1 32mm 4 1mm mmm e J _ 73 2mm 4 1lmm gt 60 2mm 1mm BE 3 97mm 4 1mm Ta s 18 0mm 4 1mm 10mm 1mm j 4 R121mm 1mm O CETUS ag COUT CCC 184 145 144 93 EA 8 1 76mm 4 1mm gt lt 2 3mm 1mm 2 5mm 4 0 5mm 184 H 0 27mm 4 0 5mm J
10. Q54 18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55 19 DQ10 50 VSS 80 DQ51 111 CKE1 142 CB6 172 VDDQ 20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC 21 CKEO 52 BA1 82 VDDID 113 BA2 144 CB7 174 DQ60 22 VDDQ KEY 83 DQ56 114 DQ20 KEY 175 DQ61 23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176 VSS 24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DM7 25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62 26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63 27 A9 57 DQ34 88 DQ59 119 DM2 149 DM4 180 VDDQ 28 DQA8 58 VSS 89 VSS 120 VDD 150 DQ38 181 SAO 29 A7 59 BAO 90 WP 121 DQ22 151 DQ39 182 SA1 30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2 31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD BLOCK DIAGRAM ICS0 DQSO DMO A DD DQ1 DQ2 DQ3 DQ4 DQ5 DQG DQ7 DQs1 DM1 ics DOS D1 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM ics DOS D5 DASE Ah DM6 DQ16 V DQ48 DA1 A DQ49 A DQ18 DQ50 1A DQ1S DQ51 DQ20 DQ52 Ach DQ21 DQ53 DQ22 DQ54 A DQ23 1A DOP Ach DQS3 DQS7 DMD Ach DM7 cs DOS DQ24 DQ56 DQ25 M A DQ57 A DQ2 D3 DQ58 DO MA DQ59 A DQ28 DQ60 A DQ29 DOG Ach DQ30 A DA62 DQ31 VA DQ63 A Serial PD Sonn 1 ms na SCL SS pa Clock Input SDRAMs VREF DO D7 in A0 A1 A2 CKO CKO Vss DO D7
11. V i emn Technical Datasheet BD256TEC400 256MB PC3200 BD512TEC500 512MB PC3200 Rev 1 1 Breisach 07 2005 DESCRIPTION The takeMS 184pin DDR SDRAM DIMM series is unbuffered 184 pin double data rate Synchronous DRAM Dual In Line Memory Modules which are organized as 32 64Mx64 high speed memory arrays The modules Single Side or Double Side consists of eight or sixteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass epoxy substrate It is suitable for easy interchange and addition The takeMS 184pin DDR SDRAM DIMM series is designed for high speed of up to 200MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs While all addresses and control inputs are latched on the rising edges of the clock Data DQ Data strobes DQS and Write data masks inputs are sampled on both rising and falling edges of it The data paths are internally pipelined and 2 bit prefetched to achieve very high bandwidth All input and output voltage levels are compatible with SSTL_2 High speed frequencies programmable latencies and burst lengths allow variety of device operation in high performance memory system The takeMS 184pin DDR SDRAM DIMM series incorporates SPD serial presence detect Serial presence detect function is implemented via a serial 2 048 bit EEPROM The first 128 bytes of serial PD data are programmed by takeMS to identify DIMM type capacity and othe
12. eamble Read postamble Active to Precharge command Active to Active Auto refresh command period Auto refresh to Active Auto refresh command period Active to Read or Write delay Precharge command period Active to Autoprecharae delay Active bank Ato Active bank B command Write recovery time Auto precharge write recovery precharge time Internal write to read command delay Exit self refresh to non read command Exit self refresh to read command Average Periodic Refresh Interval Note DDR400 Test Condition 1 mA Min yes K IER all lb tis 0 6 ns fast slew rate 3 4 5 6 10 NA ns slow slew rate 3 4 5 6 10 fy 0 6 ns fast slew rate 3 4 6 6 10 NA n S slow slew rate 3 4 5 6 10 2 3 4 5 2 3 4 5 Zsy4 5 2 3 4 5 o e e EIN EIN 2 3 4 5 RRD DAL 2 3 4 5 t 2 3 4 5 11 fan E lee TE eu 75 In 705 bam 200 L ix 2 ter 78 jes 224 1 0 C lt Tq lt 70 C Vong 2 6 V 0 1 V Vopn 2 6 V0 1 V DDR400 2 Input slewrate 1 V ns for DDR400 3 The CK CK input reference level for timing reference to CK CK is the point at which CK and CK cross the input reference level for signals other than CK CK is Vor CK CK slew rate are gt 1 0 Wns 4 Inputs are not recognized as valid until Mp stabilizes 5 The Output timing reference level as measured atthe timing reference point indicated in AC Characteristics note 3 is Te 6 These parameters quarantee device
13. er FTI Wf Lt Ge 0 51 x afl E fox 166 MHz 7 Input Reference Voltage Fog t 2 b0 T fox gt 166 MHz 1 nv EE F EE 1 DDR400 conditions apply for all clock frequencies above 166 MHz 2 Under all conditions Voog must be less than or equal to Vpop 3 Peak to peak AC noise on Tur may not exceed 2 Vir ypc Maer iS also expected to track noise variations in Fr 4 rr of the transmitting device must track Viper of the receiving device CH 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM DC Operating Conditions SSTL_ 2 Inputs Parameter Symbol Values Unit Note Test Condition 1 min mes DE Trp Lolo HR e Yr 078 Yoga 23 KR OC ext Locietow Meo 00 rer 0 V E Input Leakage Current 3 Output Leakage Current 3 1 Fogo 2 5V Ta 70 C Voltage Referenced to Vss 2 The relationship between the Vpn of the driving device and the Tor of the receiving device is what determines noise margins However in the case of My max input overdrive itis the Top of the reosiving device that is referenced In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs such as a translator and therefore no Hr supply voltage connection inputs must tolerate input overdrive to 3 0 V High corner Popa 300 mv 3 Forany pin under test input of 0 V HIN op 0 3 V Values are shown per DDR SDRAM component AC Timing Absolute Specifications Parameter S Note DDR400 Test Condition 1 2 3
14. me at CAS Latency 1 5 None 00h 26 DDRAM Access from Clock at CAS Latency 1 5 None 00h 27 Minimum Row Precharge Time tRP 15 ns 3Ch 28 Minimum Row Active to Row Active delay tRRD 10 ns 28h 29 Minimum RAS to CAS delay tRCD 15 ns 3Ch 30 Minimum Active to Precharge Time tRAS 40 ns 28h 31 Module Bank Density 256M of 1 row 40h 32 Address and Command Input Setup Time Before Clock 0 6 ns 60h 33 Address and Command Input Hold Time After Clock 0 6 ns 60h 34 Data Data Mask Input Setup Time Before Data Strobe 0 4 ns 40h 35 Data Data Mask Input Hold Time After Data Strobe 0 4 ns 40h 36 40 Reserved Reserved 00h 41 Minimum active auto refresh time tRC 55 ns 37h 42 Minimum auto refresh to active command period tRFC 70 ns 46h 43 Maximum cycle time Tck max 10 ns 28h 44 Maximum DQS DQ skew time tDQSQ 0 4 ns 28h 45 Maximum read data hold skew factor tQHS 0 50 ns 50h 46 61 Reserved Reserved 00h 62 SPD Revision Rev0 0 00h 63 _ Checksum for Bytes 0 62 BDh 64 71 Manufacturer s JEDEC ID Code 7F 7F 7F 58h 72 Module Manufacturing Location 31h 42 44 32 35 36 73 90 Module Part Number BD256TEC400 54 45 43 34 30 30h 91 92 Module Revision Code Reserved 00h 93 94 Module Manufacturing Date YY WW 95 98 Module Serial Number Reserved 00h 99 127 Manufacturer s Specific Data Reserved 00h 128 255 Open for customer use Reserved 00h Serial Presence Detect 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM
15. r information of DIMM FEATURES 256 512MB Unbuffered DDR DIMM based on Data DQ Data strobes A Write masks latched 32Mx8 DDR SDRAM on both rising amp falling edges of the clock JEDEC Standard 184pin dual in line memory module DIMM 2 6V 0 2V VDD amp VDDQ Power supply Data inputs on DQS centers when write centered DQ Programmable CAS Latency 2 2 5 supported Data strobes synchronized with output data for read amp input Internal four bank operations with single pulsed data for write RAS All inputs amp outputs are compatible with SSTL_2 interface Auto refresh amp self refresh supported Fully differential clock operations CLK amp CLK with Programmable Burst Length 2 4 8 with both 200MHz sequential 7 interleave mode All addresses amp control inputs except Data Data strobes amp 4096 refresh cycles 64ms Data masks latched on the rising edges of the clock Clock Interface Power SDRAM Frequency Supply Package 200MHz PC3200 DDR 400 CL2 5 200 SSTL_2 VDD 2 6V 400mil 66pin DDR 333 CL2 5 166 VDDQ 2 6V TSOP II DDR 266 CL2 133 Jul 2005 This document is a general product description and is subject to change without notice takeMS does not assume any responsibility for use of circuits described No patent licenses are implied takems is a trademark of Memorysolution GmbH 184 PIN 64 BIT DDR SDRAM DIMM PIN DESCRIPTION 32 64Mx64 bits 184PIN PC3200 DDR SDRAM DIMM
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