Transcend 1 GB DDR DDR333 Non-ECC Memory
Contents
1. 00 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 0D 0B 00 15 Min Clock Delay for Back to Back Random Column Address tCCD 1CLK 01 16 17 of banks on each DDR SDRAM device 4 bank 27 Minimum Row Precharge Time tRP 18ns 48 28 Minimum Row Active to Row Activate delay tRRD 12ns 18ns 48 30 Minimum active to Precharge time tRAS 4 of Column Addresses on this Assembly 11 Burst Lengths Supported 2 4 8 0E 30 29 Minimum RAS to CAS Delay tRCD 5 of Module Rows on this Assembly 2bank 02 04 18 CAS Latency supported 42ns 2A 6 Data Width of this Assembly 64bits 2 5 2 0C 31 Module ROW density 40 7 Data Width of this Assembly 19 CS Latency 0 CLK 01 512MB 80 32 0 00 20 WE Latency Command Address Input Setup Time 0 75ns 75 8 VDDQ and Interface Standard of this Assembly SSTL 2 1 CLK 02 33 Command Address Input Hold Time 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 21 DDR SDRAM Module Attributes Differential Clock Input 0 75ns 75 34 6ns 60 20 22 Data Signal Input Setup Time 0 45ns 45 10 DDR SDRAM Access Time from Clock at CL 2 5 0 70ns DDR SDRAM Device Attributes General Fast current AP 00 35 Data Signal Input Hold Time Transcend Information Inc 11 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 52. 42 53 DDR SDRAM Minimum Auto Refresh to Active Auto Refresh Command Period tRFC 00 44 36 34 43 DDR SDRAM Maximum Device Cycle Time tCK max 56 33 00 44 DDR SDRAM DQS DQ Skew for DQS and associated DQ signals tDQSQ max 00 45 46 PLL Relock Time 00 47 61 Superset Information 41 00 00 00 00 00 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number DDR SDRAM Read Data Hold Skew Factor tQHS 00 91 92 Revision Code 00 By Manufacturer 62 SPD Data Revision Code 00 Variable 99 127 Manufacturer Specific Data 63 Checksum for Bytes 0 62 7D 128 255 Unused Storage Locations Undefined 64 71 Manufacturers JEDEC ID Transcend 7F 4F 72 Manufacturing Location T 54 54 73 90 Manufacturers Part Number TS128MSD64V3A 53 31 32 38 4D Transcend Information Inc 12
3. 17 94 VDD 162 VSS 36 VDD 104 VSS 181 DQ57 46 VDD 123 DU 191 VDD DQ26 133 DQS4 Name Pin No 75 VSS 143 DQ3 85 27 172 DQ54 114 VDD 56 DQ28 Pin Name Pin No VDD 08 DQ5 76 DU 153 DQ43 18 VSS 95 CKE1 163 37 CK0 105 182 DQ61 47 124 DU 192 VDD 66 DQ30 134 DM4 Pin Name Pin VSS 144 VDD DQ7 86 DU DQ48 28 VSS 96 A7 173 VSS 38 DQS2 115 A10 183 57 VDD 125 67 No Pin Name Pin 09 VDD 77 154 DQ47 19 CKE0 164 DQ52 VSS 106 A6 DQS7 48 DM2 VSS 193 SDA DQ27 135 DQ34 No Pin Name DQS8 145 DQ41 DQ8 87 VSS 29 DQ10 174 VSS 116 BA1 184 58 VDD 126 68 Pin No Pin 10 VDD 78 155 VDD 20 97 A13 165 39 VSS 107 A5 DM7 49 DQ18 VSS 194 SA0 DQ31 136 DQ38 Name 01 VREF DM8 146 DQ45 DQ12 88 VSS 156 DQ49 30 DQ14 98 175 DQ51 40 117 BA0 185 59 DQ25 127 Please refer Block Diagram 69 VDD 137 11 DQS0 79 VDD 21 DU 166 DQ53 VSS 108 A4 VSS 50 DQ22 DQ32 195 SCL VSS 02 VREF CB2 147 DQS5 VDD 89 CK2 31 DQ11 176 DQ55 41 118 RAS 186 VSS 60 DQ29 128 DQ36 70 VDD 138 VSS 12 DM0 80 CB6 157 VDD 22 VDD 99 A12 167 VDD DQ16 109 A3 51 VSS 196 SA1 03 VSS 148 DM5 90 VSS 158 32
4. BA0 is High and BA1 is Low at read write row active and precharge bank B is selected 4 Address A0 A9 V L L Note 1 OP Code Operand Code A0 A12 amp BA0 BA1 Program keys EMRS MRS 2 EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS 3 Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state X 9 X Transcend Information Inc 10 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 Serial Presence Detect Specification 70 11 DIMM configuration type non parity Parity ECC 23 DDR SDRAM Cycle Time CL 2 0 7 5ns 0 45ns 45 36 40 Serial Presence Detect Byte No Function Described NON ECC 00 75 24 Superset Information 00 Standard Specification Vendor Part 12 Refresh Rate Type 7 8us Self Refresh DDR SDRAM Access from Clock CL 2 0 0 70ns 70 41 DDR SDRAM Minimum Active Auto Refresh Time tRC 0 of Bytes Written into Serial Memory 128bytes 82 13 Primary DDR SDRAM Width 25 DDR SDRAM Cycle Time CL 1 5 00 80 1 Total of Bytes of S P D Memory X8 08 00 26 256bytes 08 14 Error Checking DDR SDRAM Width DDR SDRAM Access from Clock CL 1 5
5. TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Value 26 26 26 Unit Note Input reference voltage for Clock 12 12 pF pF 0 5 VDDQ V pF pF pF Input signal maximum peak swing 1 5 pF VTT V ZO 50ohm VTT 0 5 VDDQ RT 50ohm CLOAD 30pF Output Output Load circuit VREF 0 5 VDDQ Transcend Information Inc 7 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component tCK tCK ns Parameter Symbol Min Col Address to Col Address delay tCCD 1 CK to valid DQS in tDQSS 0 75 Address and Control input hold time tIH 0 75 Max Unit Note tCK 1 25 tCK ns Row cycle time tRC 60 Clock cycle time tCK 6 DQS in setup time tWPRES 0 Data out high impedance time from CK CK tHZ 0 70 ns 12 ns 4 ns 2 0 70 ns Refresh row cycle time tRFC 72 ns 0 45 0 55 tCK tCK Row active time tRAS Clock low level width tCL DQS falling edge to CK rising setup time tDSS Mode register set cycle time tMRD 42 120K ns 0 45 0 55 tCK 0 2 tCK 2 tck RAS to CAS delay tRCD DQS out access time from CK CK tDQSCK DQS falling edge from CK rising hold time tDSH DQ amp DM setup time to DQS tDS 18 ns 0 70 0 75 ns 0 2 tCK 0 45 ns Row active
6. tRC tRC min CL 2 5 tCK tCK min VIN VREF fro DQ DQS and DM IDD1 1625 mA Four bank interleaving with BL 4 Refer to the following page for detailed test condition IDD7 3 774 Percharge power down standby current All banks idle mA power down mode CKE lt VIL max tCK tCK min VIN VREF for DQ DQS and DM IDD2P Note 1 Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor 165 mA Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 166Mhz for DDR333 Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM IDD2F 533 mA Active power down standby current one bank active power down mode CKE lt VIL max tCK tCK min VIN VREF for DQ DQS and DM IDD3P 214 mA Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle IDD3N 765 mA Operating current burst read Burst length 2 reads continguous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK tCK min 50 of data changing at every burst lout 0 mA IDD4R 1 840 mA Transcend Information Inc 6 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuf
7. to 70 C V 3 3 VID is the magnitude of the difference between the input level on CK and the input level on CK Parameter Symbol Min Input crossing point voltage CK and CK inputs VIX DC 1 15 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 4 9 mA Transcend Information Inc 5 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK tCK min DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst IDD4W 1 720 Parameter Symbol Max mA Unit Note Auto refresh current tRC tRFC min IDD5 3 429 Operating current One bank Active Precharge tRC tRCmin tCK tCK min DQ DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle mA Self refresh current CKE lt 0 2V IDD0 1466 mA IDD6 64 mA Operating current One bank Active Read Precharge Burst 2 Operating current Four bank operation
8. valid at every burst length 8 DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 9 This combination is not defined for any function which means No Operation NOP in DDR SDRAM RAS CAS WE BA0 1 H 3 X H 4 X H Exit L A10 AP A0 A9 A11 A12 Note Auto Precharge Disable Write amp Column Address 5 Active Power Down H X H Register Extended H H X L Entry H L X X Mode Register Set H X L X X X H L L V H X X X L L L 3 Bank Active amp Row Addr L Column Address X L OP CODE 1 2 H X L 4 A0 A9 V V V Register Mode Register Set H X L H H V Auto Precharge Enable L V V DM L L L Row Address V H X X L OP CODE 1 2 H 4 6 Burst Stop H Exit L H X X X X 8 H X X No Operation Command H X Auto Refresh Refresh H H L L X L 3 Auto Precharge Disable H X X 7 Entry H Down Mode L Entry Self Refresh L H L H Bank Selection Precharge H X H X L H H H L L V Column L L H X X X 9 L H X Read amp Column Address H H L Precharge Power 3 Auto Precharge Enable X L 4 BA0 BA1 Bank select addresses If both BA0 and BA1 are Low at read write row active and precharge bank A is selected If both
9. 8 DDR SDRAM 64Mx8 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Max Unit Note 1 35 V 5 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Symbol Value Unit Supply voltage VDD 2 4 Input leakage current II 10 Voltage on any pin relative to Vss VIN VOUT 2 6 V 10 uA 0 5 3 6 V Voltage on VDD supply to Vss I O Supply voltage VDDQ 2 4 Output leakage current IOZ 10 VDD VDDQ 1 0 3 6 V 2 6 V 10 uA Storage temperature TSTG I O Reference voltage VREF Output High Current Normal strength driver VOUT 1 95 55 150 C Power dissipation VDDQ 2 50mV VDDQ 2 50mV V 1 IOH 16 8 mA PD 16 W I O Termination voltage VTT Output Low Current Normal strength driver Short circuit current IOS VREF 0 04 VREF 0 04 V VOUT 0 35 IOL 16 8 50 mA Mean time between failure 2 Input logic high
10. BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM5 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM7 A0 A12 BA0 BA1 DQ0 DQ63 RAS CAS WE CS0 CKE0 DQS DQS0 DQS DQS DQS DQS DQS DQS DQS DQS2 DQS4 DQS6 DQS7 DQS5 DQS3 DQS1 CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK0 CK0 CK1 CK1 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE CK CK DM DM0 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM6 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM4 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM2 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM1 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM3 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM5 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM7 CS1 CKE1 DQS DQS0 DQS DQS DQS DQS DQS DQS DQS DQS2 DQS4 DQS6 DQS7 DQS5 DQS3 DQS1 CK CK CK CK CK CK CK CK CK CK CK CK CK CK 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx8 DDR SDRAM 64Mx
11. DQ15 100 177 DQ56 42 119 WE 187 61 DQS3 129 71 CB0 139 13 DQ2 81 CK1 23 A11 168 VDD DQ20 110 A2 DQ58 52 VSS 120 DQ33 197 VDDSPD 62 DQ35 04 VSS 72 VDD 149 VSS 14 DQ9 91 CK2 159 33 VDD 101 178 DQ60 43 CAS 188 DQ62 DM3 130 DQ37 CB4 140 DQ39 DQ6 82 VDD VSS 24 DQ13 A9 169 DQS6 DQ17 111 A1 53 DQ19 198 SA2 05 150 VSS 92 VDD 160 34 VDD 102 179 VDD 44 121 CS0 189 63 VSS 131 VDD DQ0 73 CB1 141 VSS 83 CB3 DQ40 06 DQ4 151 DQ42 DQS1 93 VDD CK0 15 CK1 25 A8 170 DM6 DQ21 112 A0 180 DQ59 54 DQ23 122 199 VDD 64 35 VDD 45 CS1 190 DQ63 VSS 132 VDD 55 200 DU 65 Transcend Information Inc 3 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 Block Diagram SCL SDA SCL SDA Serial EEPROM A0 A1 A2 SA0 SA1 SA2 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE CK CK DM DM0 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM6 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM4 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM2 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM1 A0 A12 BA0 BA1 DQ0 DQ7 RAS CAS WE CS CKE DM DM3 A0 A12
12. For registered DIMMs tCL and tCH are gt 45 of the period including both the half period jitter tJIT HP of the PLL and the half period jitter due to crosstalk tJIT crosstalk on the DIMM ns Power down exit time 5 A write command can be applied with tRCD satisfied after this command tPDEX 6 ns Exit self refresh to bank active command tXSA 7 5 ns 5 Exit self refresh to read command tXSR 200 Cycle Refresh interval time tREF 7 8 us 1 Clock half period tHP tCLmin or tCHmin ns Data hold skew factor tQHS 0 55 ns DQS write post amble time tWPST 0 4 0 6 tck Transcend Information Inc 9 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND Exit L H All Banks H H H If both BA0 is Low and BA1 is High at read write row active and precharge bank C is selected If both BA0 and BA1 are High at read write row active and precharge bank D is selected 5 If A10 AP is High at row precharge BA0 and BA1 are ignored and all banks are selected CKEn 1 CKEn CS L H H 6 During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 7 Burst stop command is
13. TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 Description The TS128MSD64V3A is a 128M x 64bits Double Data Rate SDRAM high density for DDR333 The TS128MSD64V3A consists of 16pcs CMOS 64Mx8 bits Double Data Rate SDRAMs in 60 Ball FBGA packages and a 2048 bits serial EEPROM on a 200 pin printed circuit board The TS128MSD64V3A is a Dual In Line Memory Module and is intended for mounting into 200 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features Power supply VDD VDDQ 2 5V 0 1V Max clock Freq 166MHZ Double data rate architecture two data transfers per clock cycle Differential clock inputs CK and CK DLL aligns DQ and DQS transitions with CLK transition Commands entered on each positive CLK edge Auto and Self Refresh Data I O transactions on both edge of data strobe Serial Presence Detect SPD with serial EEPROM SSTL 2 compatible inputs and outputs MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequent
14. fered SO DIMM 1GB With 64Mx8 CL2 5 AC OPERATING CONDITIONS Parameter Symbol V Input Levels VIH VIL Min Max Unit VREF 0 31 VREF 0 31 V Note Input High Logic 1 Voltage DQ DQS and DM signals Input timing measurement reference level VREF VIH AC VREF 0 31 V V Output timing measurement reference level 3 Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 Output load condition See Load Circuit V 3 Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 Input Output CAPACITANCE VDD 2 5V VDDQ 2 5V TA 25 C f 1MHz Parameter Symbol V 1 Min Max Unit Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 Input capacitance A0 A12 BA0 BA1 RAS CAS WE Input capacitance CKE0 CKE1 Input capacitance CS0 CS1 0 5 VDDQ 0 2 V 2 Input capacitance CK0 CK1 Input capacitance DM0 DM7 Data and DQS input output capacitance DQ0 DQ63 Note 1 VIH max 4 2V The overshoot voltage duration is lt 3ns at VDD CIN1 CIN2 CIN3 2 VIL min 1 5V The undershoot voltage duration is lt 3ns at VSS CIN4 CIN5 COUT1 34 3 VID is the magnitude of the difference between the input level on CK and the input on CK 18 18 18 4 The Value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the DC level of the same 10 10 56 AC OPERATING
15. ial amp Interleave Placement A B E F I J D C K G H PCB 09 1870 Transcend Information Inc 1 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 Dimensions DQS0 DQS7 Data strobe input output Side Millimeters Inches CK0 CK2 CK0 CK2 Clock Input A 67 60 0 20 CKE0 CKE1 Clock Enable Input 2 661 0 008 B 47 40 CS0 CS1 Chip Select Input 1 866 C RAS Row Address Strobe CAS 11 40 0 449 Column Address Strobe WE D 4 20 0 165 Write Enable DM0 DM7 E 2 15 0 085 Data in Mask VDD 2 5 Voltage power supply F 1 80 VREF Power Supply for Reference 0 071 G 4 00 VDDSPD 2 5 Voltage Serial EEPROM Power Supply 0 157 H SA0 SA2 Address in EEPROM 6 00 0 236 SCL Serial PD Clock I 20 00 0 787 SDA Serial PD Add Data input output J 31 75 0 20 1 250 0 008 VSS Ground K 1 00 0 10 NC No Connection 0 039 0 004 Refer Placement Pin Identification Symbol Function A0 A12 BA0 BA1 Address input DQ0 DQ63 Data Input Output Transcend Information Inc 2 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 Pinouts 74 CB5 142 DQ44 16 VSS 84 CB7 161 VSS 26 DM1 103 VSS 171 DQ50 VDD 113 VDD DQ24 Pin No Pin 07 DQ1 152 DQ46
16. to Row active delay Output data access time from CK CK DQS in high level width tRP 18 ns tAC 0 70 0 75 ns tDQSH 0 35 tCK Row active to Row active delay Data strobe edge to output data edge DQS in low level width tRRD 12 tDQSQ 0 45 tDQSL 0 35 ns Write recovery time ns 4 Read Preamble tCK DQS in cycle time tWR 15 tRPRE 0 9 1 1 tDSC 0 9 1 1 tCK tCK tCK Last data in to Read command tCDLR 1 Read Postamble tRPST 0 4 0 6 Address and Control input setup time tIS 0 75 Clock high level width tCH DQS in hold time tWPREH Data out low impedance time from CK CK tLZ 0 70 0 25 0 70 ns Transcend Information Inc 8 TTTSSS111222888M MMSSSD DD666444VVV333A AA 200PIN DDR333 Unbuffered SO DIMM 1GB With 64Mx8 CL2 5 DQ amp DM hold time to DQS 3 Note tDH 0 45 ns 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High_Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS DQ amp DM input pulse width 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly tDIPW 1 75 4
17. voltage VIH DC mA MTBF 50 VREF 0 15 VDDQ 0 3 V Output High Current Half strength driver VOUT VTT 0 45V IOH year Temperature Humidity Burning THB 85 C 85 Static Stress C Input logic low voltage VIL DC 0 3 VREF 0 15 Output High Current Half strength driver Temperature Cycling Test TC 0 C 125 C Cycling C V 4 Input Voltage Level CK and CK inputs VOUT VTT 0 45V IOL 9 Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded VIN DC 0 3 VDDQ 0 3 mA Functional operation should be restricted to recommended operating condition V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH Exposure to higher than recommended voltage for extended periods of time could affect device reliability Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0
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