Transcend 1 GB DDR2 DDR2-533 Unbuffer Non-ECC Memory
Contents
1.2. Placement Ko lt PCB 09 2162 Transcend Information Inc TS128MSQ64V5J 200PIN DDR2 533 SO DIMM 1024MB With 64Mx8 CL4 Pin Identification Symbol Function A0 A13 BAO BA2 Address input DQ0 DQ63 Data Input Output DQS0 DQS7 Data strobe DQS0 DQS7 Differential Data strobe Dimensions Side Millimeters Inches A 67 6 0 15 2 661 0 006 B 63 6 2 503 C 11 4 0 449 D 47 4 1 866 E 4 2 0 165 F 2 15 0 15 0 085 0 006 G 6 0 236 H 18 0 709 4 0 157 J 30 1 181 K 1 040 075 0 039 0 003 Refer Placement Transcend Information Inc CKO CKO Clock Input CK1 CK1 CKEO CKE1 Clock Enable Input ODTO ODT1 On die termination control line CSO CS1 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DM0 DM7 Data in Mask VDD 1 8 Voltage power supply 1 8 Voltage Power Supply for VDDQ DQS VREF Power Supply for Reference Serial EEPROM Positive Power VDDSPD Supply SA0 SA2 Address select for EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection 200PIN DDR2 533 SO DIMM TS1 Z28MSQ64V5J 1024MB With 64Mx8 CL4 Pinouts Pin Pin Pin Pin
3. 125 DQ33 193 VSS 58 DQ23 126 DQ37 194 DQ63 59 VSS 127 VSS 195 SDA 60 VSS 128 VSS 196 VSS 61 DQ24 129 DQS4 197 SCL 62 DQ28 130 DM4 198 SAO 63 DQ25 131 DQS4 199 VDDSPD 64 DQ29 132 VSS 200 SA1 65 VSS 133 VSS 66 VSS 134 DQ38 67 DM3 135 DQ34 68 DQS3 136 DQ39 Please refer Block Diagram Transcend Information Inc 3 TS128MSQ64V5J Block Diagram ICS ICSO DQSO w DQSO DMO A0 A13 BAO BA1 CKEO CKE RAS ICAS IWE ODTO ODT1 Note U5 U13 38 DM CS DQS DQS 100 I 01 1 0 2 103 1 0 4 VO 5 1 06 I 07 wU w 7w U7 W U8 U w ws ws gt U w W U8 U NO NNDWO DM CS DQS DQS U15 CK0 CK0 gt CK1 CK1 _ gt 1 DQ DM DQS amp DQS resistors 22 Ohms 5 2 Bx Ax CKEx ODTx CSx RAS CAS amp WEresistors 3 Ohmst5 Transcend Information Inc 200PIN DDR2 533 SO DIMM 1024MB With 64Mx8 CL4 U6 U14 U1 U2 U5 U6 U9 U10 U13 U14 U3 U4 U7 U8 U11 U12 U15 U16 U8 SCL U16 EEPROM AQ Al A2 SAO SAT SDA VDDSPD j EEPROM gt U1 U16 VDD VDDQ I VSS U1 U16 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and
4. tREFI 3 9 us is required and to enter to self refresh mode at this temperature range an EMRS command is required to change internal refresh rate Transcend Information Inc 5 200PIN DDR2 533 SO DIMM TS1 Z28MSQ64V5J 1024MB With 64Mx8 CL4 IDD Specification parameters Definition IDD values are for full operating range of voltage and Temperature Parameter Symbol Max Unit Note Operating One bank Active Precharge current tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands IDDO 1 360 mA Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating One bank Active read Precharge current IOUT OmA BL 4 CL CL IDD AL 0 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD1 1 440 mA Precharge power down current All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2P 128 mA Precharge quiet standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data bus inputs are pp2Q 400 mA FLOATING Precharge standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING Data bus inputs are IDD2N 480 mA SWI
5. VIH AC on the positive transitions and VIH AC to VIL AC on the negative transitions ViH AC min VI H DC min VREE VIL DC max VIL AC max VSS delta TF delta TR Falling Slew Vre Vi ACO Rising Slew Vis AC nin Veer delta TF delta TR AC Input Test Signal Waveform Input Output Capacitance Vpp 1 8V Voda 1 8V TA 25 C Input capacitance CKO and CKO Input capacitance CK1 and CK1 Input capacitance AO A13 BAO BA2 RAS CAS WE Input capacitance CKE and CS Input capacitance DQ DM DQS DQS Note DM is internally loaded to match DQ and DQS identically Transcend Information Inc 7 200PIN DDR2 533 SO DIMM TS1 Z28MSQ64V5J 1024MB With 64Mx8 CL4 Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Unit Note DQ output access time from CK amp CK tAC 500 500 ps DQS output access time from CK amp CK tDQSCK 450 450 ps CK high level width tCH 0 45 0 55 tCK CK low level width tCL 0 45 0 55 tCK CK half period tHP min tCL tCH X ps Clock cycle time CL x tCK 3750 8000 ps DQ and DM input hold time tDH 225 x ps DQ and DM input setup time tDS 100 X ps Control amp Address input pulse width for each input tIPW 0 6 x tCK DQ and DM input pulse width for each input tDIPW 0 35 X tCK Data out high impedance time from
6. assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice 200PIN DDR2 533 SO DIMM TS1 28MSQ64V5J 1024MB With 64Mx8 CL4 Absolute Maximum DC Ratings Parameter Symbol Value Unit Notes Voltage on VDD relative to Vss VDD 1 0 2 3 V 1 Voltage on VDDQ pin relative to Vss VDDQ 0 5 2 3 V 1 Voltage on VDDL pin relative to Vss VDDL 0 5 2 3 V 1 Voltage on any pin relative to Vss VIN VOUT 0 5 2 3 V 1 Storage temperature TSTG 55 100 C 1 2 Mean time between failure MTBF Reserved year Temperature Humidity Burning THB Reserved C Temperature Cycling Test TC Reserved C Note 1 Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard AC amp DC Operating Conditions Recommended DC operating conditions SSTL 1 8 Rating Parameter Symbol Unit Notes Min Typ Max Supply voltage VDD 1 7 1 8 1
7. input setup time before strobe tDS 0 10ns 10 35 Data input hold time after strobe tDH 0 22ns 22 36 Write recovery time tWR 15ns 3C Transcend Information Inc 10 TS128MSQ64V5J 200PIN DDR2 533 SO DIMM 1024MB With 64Mx8 CL4 37 Internal write to read command delay tWTR 7 5ns 1E 38 Internal read to precharge command delay tRTP 7 5ns 1E 39 Memory analysis probe characteristics 00 40 Reserved 00 41 DDR SDRAM Minimum Active to Active Auto Refresh 55ns 37 Time tRC 42 DDR SDRAM Minimum Auto Refresh to 405ns 69 Active Auto Refresh Command Period tRFC 43 DDR SDRAM Maximum Device Cycle Time tCK max 8ns 80 AA DDR SDRAM DQS DQ Skew for DQS and associated 0 3ns 1E DQ signals tDQSQ max i 45 DDR SDRAM Read Data Hold Skew Factor tQHS 0 4ns 28 46 PLL Relock Time X 00 47 61 Superset Information 00 62 SPD Data Revision Code REV 1 0 10 63 Checksum for Bytes 0 62 33 33 64 71 Manufacturers JEDEC ID Transcend TF 4F 72 Manufacturing Location T 54 54 53 31 32 38 4D 73 90 Manufacturers Part Number TS128MSQ64V5J 53 51 36 34 56 35 4A 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Open for customer use Undefined Transcend Information Inc ll
8. 9 V Supply voltage for DLL VDDL 1 7 1 8 1 9 V 4 Supply voltage for Output VDDQ 1 7 1 8 1 9 V 4 I O Reference voltage VREF 0 49 VDDQ 0 50 VDDQ 0 51 VDDQ V 1 2 I O Termination voltage VTT VREF 0 04 VREF VREF 0 04 V 3 DC Input logic high VIH DC VREF 0 125 VDDQ 0 3 V DC Input logic low VIL DC 0 3 VREF 0 125 V Note There is no specific device VDD supply voltage requirement for SSTL 1 8 compliance However under all conditions VDDQ must be less than or equal to VDD 1 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ 2 Peak to peak AC noise on VREF may not exceed 2 VREF DC 3 VTT of transmitting device must track VREF of receiving device 4 AC parameters are measured with VDD VDDQ and VDDDL tied together Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 95 C 1 2 3 Note 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 2 At 0 85 C operation temperature range are the temperature which all DRAM specification will be supported 3 At 85 95 C operation temperature range doubling refresh commands in frequency to a 32ms period
9. CK CK tHZ X tAC max ps DQS low impedance time from CK CK tLZ DQS tAC min tAC max ps DQ low impedance time from CK CK tLZ DQ 2 tAC min TAC max ps DQS DQ skew for DQS and associated DQ signals tDQSQ X 300 ps DQ hold skew factor tQHS X 400 ps DQ DQS output hold time from DQS tQH tHP tQHS x ps Write command to first DQS latching transition tDQSS WL 0 25 WL 0 25 tCK DQS input high pulse width tDQSH 0 35 X tCK DQS input low pulse width tDQSL 0 35 X tCK DQS falling edge to CK setup time tDSS 0 2 x tCK DQS falling edge hold time from CK tDSH 0 2 X tCK Mode register set command cycle time tMRD 2 X tCK Write postamble tWPST 0 4 0 6 tCK Write preamble tWPRE 0 35 X tCK Address and control input hold time tIH 375 X ps Address and control input setup time tIS 250 X ps Read preamble tRPRE 0 9 1 1 tCK Read postamble tRPST 0 4 0 6 tCK a active command period for 1KB page size IRRD 75 xX a R active command period for 2KB page size tRRD 40 x n Four Activate Window for 1KB page size products tFAW 37 5 ns Four Activate Window for 2KB page size products tFAW 50 ns Transcend Information Inc g TS128MSQ64V5J 200PIN DDR2 533 SO DIMM 1024MB With 64Mx8 CL4 tCCD asynchronously drops LOW CAS to CAS command delay 2 tCK Write recovery time tWR 15 x ns Auto precharge write recovery precharge time tDAL tWR tRP x tCK Internal write to read command del
10. Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 VREF 69 NC 137 DQ35 02 VSS 70 DQS3 138 VSS 03 VSS 71 VSS 139 VSS 04 DQ4 72 VSS 140 DQ44 05 DQO 73 DQ26 141 DQ40 06 DQ5 74 DQ30 142 DQ45 07 DQ1 75 DQ27 143 DQ41 08 VSS 76 DQ31 144 VSS 09 VSS 77 VSS 145 VSS 10 DMO 78 VSS 146 DQS5 11 DQSO 79 CKEO 147 DM5 12 VSS 80 CKE1 148 DQS5 13 DQSO 81 VDD 149 VSS 14 DQ6 82 VDD 150 VSS 15 VSS 83 CS2 151 DQ42 16 DQ7 84 A15 152 DQ46 17 DQ2 85 BA2 153 DQ43 18 VSS 86 A14 154 DQ47 19 DQ3 87 VDD 155 VSS 20 DQ12 88 VDD 156 VSS 21 VSS 89 A12 157 DQ48 22 DQ13 90 A11 158 DQ52 23 DQ8 91 A9 159 DQ49 24 VSS 92 AT 160 DQ53 25 DQ9 93 A8 161 VSS 26 DM1 94 A6 162 VSS 27 VSS 95 VDD 163 NC TEST 28 VSS 96 VDD 164 CK1 29 DQS1 97 AS 165 VSS 30 CKO 98 A4 166 CK1 31 DQS1 99 A3 167 DQS6 32 CKO 100 A2 168 VSS 33 VSS 101 A1 169 DQS6 34 VSS 102 AO 170 DM6 35 DQ10 103 VDD 171 VSS 36 DQ14 104 VDD 172 VSS 37 DQ11 105 A10 AP 173 DQ50 38 DQ15 106 BA1 174 DQ54 39 VSS 107 BAO 175 DQ51 40 VSS 108 RAS 176 DQ55 41 VSS 109 IWE 177 VSS 42 VSS 110 CSO 178 VSS 43 DQ16 111 VDD 179 DQ56 44 DQ20 112 VDD 180 DQ60 45 DQ17 113 ICAS 181 DQ57 46 DQ21 114 ODTO 182 DQ61 47 VSS 115 1CS1 183 VSS 48 VSS 116 A13 184 VSS 49 DQS2 117 VDD 185 DM7 50 NC 118 VDD 186 DQS7 51 DQS2 119 ODT1 187 VSS 52 DM2 120 CS3 188 DQS7 53 VSS 121 VSS 189 DQ58 54 VSS 122 VSS 190 VSS 55 DQ18 123 DQ32 191 DQ59 56 DQ22 124 DQ36 192 DQ62 57 DQ19
11. TCHING Active power down current All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are l FLOATING Slow PDN Exit MRS 12 1mA IDD3P S 240 Fast PDN Exit MRS 12 OmA IDD3P F 480 mA Active standby current All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Other control IDD3N 1 120 mA and address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating burst read current All banks open Continuous burst reads IOUT OmA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD4R 2 160 mA Operating burst write current All banks open Continuous burst writes BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING DD4W 2 000 mA Data bus inputs are SWITCHING IDD4R Burst Auto refresh current tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands Other control and IDD5B 2 120 mA address bus inputs are SWITCHING Data bus inputs are SWITCHING Self refresh current CK and CK at OV CKE 0 2V Other control and address bus inputs are FLOATING Data bu
12. TS128MSQ64V5J 200PIN DDR2 533 SO DIMM 1024MB With 64Mx8 CL4 Description The TS128MSQ64V5J is a 128M x 64bits DDR2 533 SO DIMM The TS128MSQ64V5J consists of 16pcs 64Mx8its DDR2 SDRAMs in 60 ball FBGA packages and a 2048 bits serial EEPROM on a 200 pin printed circuit board The TS128MSQ64V5J is a Dual In Line Memory Module and is intended for mounting into 200 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHS compliant products e JEDEC standard 1 8V 0 1V Power supply e VDDQ 1 8V 0 1V e Max clock Freq 267MHZ 533Mb s Pin e Posted CAS e Programmable CAS Latency 3 4 5 e Programmable Additive Latency 0 1 2 3 and 4 e Write Latency WL Read Latency RL 1 e Burst Length 4 8 Interleave nibble sequential e Programmable sequential Interleave Burst Mode e Bi directional Differential Data Strobe Single ended data strobe is an optional feature e Off Chip Driver OCD Impedance Adjustment e MRS cycle with address key programs e On Die Termination e Refresh and Self Refresh Average Refresh Period 7 8us at lower then TCASE 85 C 3 9us at 85 C lt TCASE lt 95 C e Serial presence detect with EEPROM
13. ay tWTR 7 5 X ns Internal read to precharge command delay tRTP 7 5 ns Exit self refresh to a non read command tXSNR tRFC 10 ns Exit self refresh to a read command tXSRD 200 tCK Exit precharge power down to any non read command tXP 2 x tCK Exit active power down to read command tXARD 2 X tCK Exit active power down to read command Slow exit tXARDS 6 AL tCK Lower power CKE minimum pulse width high and low pulse width tCKE tCK ODT turn on delay tAOND 2 tCK ODT turn on tAON tAC min tAC max 1 ns ODT turn on Power Down mode tAONPD tAC min 2 ena ns ODT turn off delay tAOFD 2 5 2 5 tCK ODT turn off tAOF tAC min tAC max 0 6 ns ODT turn off Power Down mode tAOFPD tAC min 2 A ns ODT to power down entry latency tANPD 3 tCK ODT power down exit latency tAXPD 8 tCK OCD drive mode output delay tOIT 0 12 ns Minimum time clocks remains ON after CKE tDelay tIS tCK tlH ae Transcend Information Inc 200PIN DDR2 533 SO DIMM TS1 28MSQ64V5J 1024MB With 64Mx8 CL4 SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Serial PD Bytes written during module production 128bytes 80 1 Total of Bytes of S P D Memory Device 256bytes 08 2 Fundamental Memory Type DDR2 SDRAM 08 3 of Row Addresses on this Assembly 14 OE 4 of Column Address
14. es on this Assembly 10 OA 5 of Module Rows on this Assembly AROW Planar 61 30 0mm 6 Data Width of this Assembly 64bits 40 7 Reserved 00 8 VDDQ and Interface Standard of this Assembly SSTL 1 8V 05 DDR2 SDRAM cycle time at Max Supported CAS o dieno y di 3 75ns 3D 10 DDR2 SDRAM Access time from clock at CL X 0 5ns 50 11 DIMM configuration type non parity Parity ECC Non ECC 00 12 Refresh Rate 7 8us 02 13 Primary DDR2 SDRAM Width X8 08 14 Error Checking DDR2 SDRAM Width N A 00 15 Reserved 00 DDR2 SDRAM device attributes Burst lengths 16 urpo g 4 8 oc 17 DDR2 SDRAM device attributes of banks on each 4 banks 04 DDR2 SDRAM device 18 DDR2 SDRAM device attributes CAS Latency 5 4 3 38 supported 19 Reserved 00 20 DIMM type information SODIMM 04 Analysis probe not 21 DDR2 SDRAM Module Attributes installed FET switch 00 external not enable 22 DDR2 SDRAM Device Attributes General Supports weak driver 01 23 DDR2 SDRAM Cycle Time CL X 1 3 75ns 3D 24 DDR SDRAM Access from Clock CL X 1 0 5ns 50 25 DDR SDRAM Cycle Time CL X 2 5 0ns 50 26 DDR SDRAM Access from Clock CL X 2 0 6ns 60 27 Minimum Row Precharge Time tRP 15ns 3C 28 Minimum Row Active to Row Activate delay tRRD 10 0ns 28 29 Minimum RAS to CAS Delay tRCD 15ns 3C 30 Minimum active to Precharge time tRAS 40ns 28 31 Module ROW density 512MB 80 32 Command and address setup time before clock tlS 0 25ns 25 33 Command and address hold time after clock tlH 0 37ns 37 34 Data
15. s inputs are FLOATING Eee 93 mA Operating bank interleave read current All bank interleaving reads IOUT OmA BL 4 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD tRC tRC IDD tRRD tRRD IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid IDD7 2 760 mA commands Address bus inputs are STABLE during Deselects Data pattern is same as IDD4R Refer to the following page for detailed timing conditions Note 1 Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor Transcend Information Inc 6 200PIN DDR2 533 SO DIMM TS1 28 MSQ64V5J 1024MB With 64Mx8 CL4 Input AC Logic Level Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 250 V Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 250 V AC Input Test Condition Condition Symbol Vae Unt Note VsWING MAX Input signal minimum slew rate 2 3 Note 1 Input waveform timing is referenced to the input signal crossing through the VIH IL AC level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from VREF to VIH AC min for rising edges and the range from VREF to VIL AC max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from VIL AC to
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