Transcend 256MB SDRAM PC133 Unbuffer Non-ECC Memory
Contents
1. Parameter Symbol Min Max Unit Input capacitance AO A12 BAO BA1 CADD 25 45 pF Input capacitance RAS CAS WE CIN 25 45 pF Input capacitance CKE0 CKE1 CCKE 15 25 pF Input capacitance CLKO CLK3 CCLK 15 21 pF Input capacitance CSO CS3 Ccs 15 25 pF Input capacitance DQM0 DQM 7 CDQM 10 12 pF Data input output capacitance DQ0 DQ63 COUT 13 18 pF DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Transcend information Inc 5 TS32MLS64V6G 168PIN PC133 Unbuffered DIMM 256MB With 16Mx16 CL3 Operating Current Icc1 Burst Length 1 520 mA 1 One Bank Active ae Icc2P CKE lt ViL max tcc 10ns 16 Precharge Standby Current mA in power down mode Icc2PS CKE amp CLK lt ViL max tcc lt 16 Icc2N ICKE gt ViH min CS gt ViH min tcc 10ns 160 Precharge Standby Current Input signals are changed one time during 20ns mA in non power down mode cc2NS_CKE ViH min CLK lt ViL max tcc 80 Input signals are stable Icc3P_ CKE lt ViL max tcc 10ns 48 A Active Standby Current m in power down mode Icc3PS CKE amp CLK lt ViL max tcc lt 48 Penner ie tere loc3N Ee KESvinimin CS gt ViH min tec 10ns 240 L y Input signals are changed one time during 20ns in non power down mode mA One Bank Acti Icc3N pone San ene S eKESvinimin CLK2. tf 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC133 Unbuffered DIMM TS32M LS64V6G 256MB With 1 6Mx16 CL3 SIMPLIFIED TRUTH TABLE oN ele wae Ease See le Eny 2 al re stn oe ee EES esl Read amp Auto Precharge Disable Column H Address Column Address Auto Precharge Enable Ao As Write amp Auto Precharge Disable Column H L L Address Column Address Auto Precharge Enable Ao As est St cAeU CaCI CHET iN a iN a Bank Selection Precharge Both Banks Clock Suspend or Active Power Down Precharge Power Down Mode No Operation Command V aie X aa t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read wr
3. 14 61 NC 103 DQ46 145 NC 20 DQ15 62 Vref 104 DQ47 146 Vref 21 CBO 63 CKE1 105 CB4 147 REGE 22 CB1 64 Vss 106 CB5 148 Vss 23 Vss 65 DQ21 107 Vss 149 DQ53 24 NC 66 DQ22 108 NC 150 DQ54 25 NC 67 DQ23 109 NC 151 DQ55 26 Vcc 68 Vss 110 Vcc 152 Vss 27 IWE 69 DQ24 111 CAS 153 DQ56 28 DQMO 70 DQ25 112 DQM4 154 DQ57 29 DQM1 71 DQ26 113 DQM5 155 DQ58 30 CSO 72 DQ27 114 CS1 156 DQ59 31 NC 73 Vcc 115 RAS 157 Vcc 32 Vss 74 DQ28 116 Vss 158 DQ60 33 AO 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 AG 78 Vss 120 A7 162 Vss 37 A8 79 CLK2 121 AQ 163 CLK3 38 A10 AP 80 NC 122 BAO 164 NC 39 BA1 81 NC 123 A11 165 SAO 40 Vcc 82 SDA 124 Vcc 166 SA1 41 Vcc 83 SCL 125 CLK1 167 SA2 42 CLKO 84 Vcc 126 A12 168 Vcc Please refer Block Diagram Transcend information Inc 3 168PIN PC133 Unbuffered DIMM TS32M LS64V6G 256MB With 16Mx16 CL3 Block Diagram A0 A12 BAO BA1 DQ0 DQ63 DQ0 DQ15 RAS ICAS WE ICSO CLKO CKEO A0 A12 BA0 BA1 ICS2 CLK2 ICS1 CLK1 CKE1 ICS3 CLK3 Serial EEPROM SDA WP SCL This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice T
4. 3 32 4D 4C 73 90 Manufacturers Part Number TS32MLS64V6G 53 36 34 56 36 47 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 3 Clock 0 2 F6 128 Unused Storage Locations Open FF Transcend information Inc 11
5. TS32MLS64V6G Description The TS32MLS64V6G is a 32M bit x 64 Synchronous Dynamic RAM high density memory modules The TS32MLS64V6G consists of 8 piece of CMOS 16Mx16bits Synchronous DRAMs in TFBGA 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS32MLS64V6G is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth applications high performance memory system Features e ROHS compliant products e Performance Range PC133 e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Scramble Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Placement 168PIN PC133 Unbuffered DIMM 256MB With 16Mx16 CL3 PCB 09 2410 Transcend information Inc TS32MLS64V6G Dimensions Side Millimeters Inc
6. ghest CL 5 4ns 54 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec R W OE Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 Transcend information Inc 10 TS32MLS64V6G 168PIN PC133 Unbuffered DIMM 256MB With 16Mx16 CL3 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 AA AA 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 3
7. hes 133 35 0 40 5 250 0 016 B 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 22 225 0 20 0 875 0 008 G 19 80 0 788 H 15 80 0 622 l 1 27 0 10 0 050 0 004 Refer Placement 168PIN PC133 Unbuffered DIMM 256MB With 16Mx16 CL3 Pin Identification Symbol Function A0 A12 Address inputs BAO BA1 Select Bank DQ0 DQ63 __ Data inputs outputs CLKO 3 Clock Input CKEO CKE1 Clock Enable Input CS0 3 Chip Select Input IRAS Row address strobe ICAS Column address strobe IWE Write Enable DQMO 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data I O SA0 2 Address in EEPROM WP Write protection SCL Serial Clock NC No Connection Transcend information Inc 168PIN PC133 Unbuffered DIMM TS32M LS64V6G 256MB With 16Mx16 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 Vss 43 Vss 85 Vss 127 Vss 02 DQO 44 NC 86 DQ32 128 CKEO 03 DQ1 45 ICS2 87 DQ33 129 CS3 04 DQ2 46 DQM2 88 DQ34 130 DQM6 05 DQ3 47 DQM3 89 DQ35 131 DQM7 06 Vcc 48 NC 90 Vcc 132 A13 07 DQ4 49 Vcc 91 DQ36 133 Vcc 08 DQ5 50 NC 92 DQ37 134 NC 09 DQ6 51 NC 93 DQ38 135 NC 10 DQ7 52 CB2 94 DQ39 136 CB6 11 DQ8 53 CB3 95 DQ40 137 CB7 12 Vss 54 Vss 96 Vss 138 Vss 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 Vcc 101 DQ45 143 Vcc 18 Vcc 60 DQ20 102 Vcc 144 DQ52 19 DQ
8. ite row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and all banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 O Transcend information Inc 9 168PIN PC133 Unbuffered DIMM TS32M LS64V6G 256MB With 16Mx16 CL3 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A12 oD 4 of Column Addresses on this Assembly A0 A8 09 5 of Module Banks on this Assembly 2 banks 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock hi
9. lt ViL max toc 200 Input signals are stable Operating Current jca OES Om mA 1 Page Burst 680 Burst Mode teco 2CL Ks mA 2 Refresh current Icc5 tRC lt tRC min 920 A Self Refresh Current Icce CKE lt 0 2V lt a i Note 4 Measured with outputs open 2 Refresh period is 64 ms 3 Unless otherwise noted input swing level is CMOS VIH VIL VDDQ Vssq AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V TA 0 to 70 C Parameter Vawe nits OE AC Input levels VIH VIL 2 4 0 4 Transcend information Inc 168PIN PC133 Unbuffered DIMM TS32M LS64V6G 256MB With 16Mx16 CL3 Input timing measurement reference level nput rise and fall time tr tf 1 1 Output timing measurement reference level Output load condition 3 3V Vtt 1 4V O 1200 Ohm 50 Ohm gt Von DC 2 4V loH 2MA Output z0 60 Ohm Vo DC 0 4V loL 2mA 50pF s0pr 870 Ohm 71177 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time tRAS min 45 ns 1 tRAS max 100 us Row cycle time tRc min 65 ns 1 Last data in to row precharge tRDL min 2 CLK 2 Last data in to new col address delay tCDL min 1 CLK 2 Last data in t
10. o Active delay tDAL 2CLK tRP Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK Number of valid output data CAS latency 3 2 ea Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 168PIN PC133 Unbuffered DIMM TS32MLS64V6G 256MB With 16Mx16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time tcc 7 5 1000 ns 1 CLK to valid tSAC 54 ns 1 2 output delay Output data ton 3 i 2 hold time CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output 54 in Hi Z tSHZ ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr
11. ranscend information Inc 4 168PIN PC133 Unbuffered DIMM TS32M LS64V6G 256MB With 16Mx16 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 8 W Short circuit current Los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symboli _ Min Typ Max Note ae eh E Input low voltage vwe 03 o f 08 Output high voltage von 24 0 1 2 6 Output low voltage vo o4 Input leakage current Iu 10 10 uA Note 1 V H max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt Vin lt SVDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state output CAPACITANCE VDD 3 3V TA 23 C f 1MHz VREF 1 4V 200mV
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