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Intel Desktop Board D910GLDW

1. LGA775 System Bus Diskette Drive Processor Socket 533 MHz Connector LPC Bus y z y TZ v 2 se E S Intel 82801 FB 4 Mbit rapaces an qm eS UO Controller Hub Y gt Firmware Hub Memory Controller 2 Hub GMCH CH6 SE a A A A A A i i Intel 910GL Chipset VGA d el Port a Display Interface 8 e E o Dual Channel 3 5 Channel A Memory Bus l Z DIMM SE 5 10 100 LAN 2 LAN PLC gt Connector Channel B 3 Optional Optional DIMM gt O E aia eras d PCI Bus ei a Serial ATA Serial ATA IDE Optional Ti IDE Interface Connectors 4 PCI Bus T PCI Slot 1 a Mie In Retasking Jack B ZE Spe Line In Retasking Jack C o Ke Ge Line Out Retasking Jack D 4 Retasking Jack E Port 1 gt Hardware Monitoring Retasking Jack F Port 2J gt and Fan Control ASIC connector or socket 14 OM17307 Figure 2 Block Diagram Product Description 1 3 Online Support 1 4 1 5 To find information about Visit this World Wide Web site Intel Desktop Board D910GLDW under http www intel com design motherbd Desktop Board Products or Desktop Board Support http support intel com support motherboards desktop Available configurations for the Desktop http developer intel com design motherbd dw dw_available htm Board D910GLDW
2. The overall system noise reduction will vary based on system configuration and environment 1 11 5 Chassis Intrusion and Detection The board supports a chassis security feature that detects if the chassis cover is removed The security feature uses a mechanical switch on the chassis that attaches to the chassis intrusion connector When the chassis cover is removed the mechanical switch is in the closed position 1 12 Power Management 30 Power management is implemented at several levels including e Software support through Advanced Configuration and Power Interface ACPI e Hardware support Power connector Fan connectors LAN wake capabilities Instantly Available PC technology Resume on Ring Wake from USB Wake from PS 2 devices Power Management Event signal PME wake up support 1 12 1 Product Description ACPI ACPI gives the operating system direct control over the power management and Plug and Play functions of a computer The use of ACPI with this board requires an operating system that provides full ACPI support ACPI features include Plug and Play including bus and device enumeration Power management control of individual devices add in boards some add in boards may require an ACPI aware driver video displays and hard disk drives Methods for achieving less than 15 watt system operation in the power on standby sleeping state A Soft off feature that enables the opera
3. 4 1 BIOS Error Messages E 73 42 PON SOM POs lb COGSS sec a e aaa AAE EER AeA AEE AE Ss TE SI EAA EA EARE EENE 75 4 3 Bus Initialization Checkpoints vecs lina 79 AA Speaker tip dial 80 45 BIOS Beep Godas cti ria ad is 80 4 1 BIOS Error Messages Table 40 lists the error messages and provides a brief description of each Table 40 BIOS Error Messages Error Message GA20 Error Pri Master HDD Error Pri Slave HDD Error Pri Master Drive ATAPI Incompatible Pri Slave Drive ATAPI Incompatible A Drive Error Cache Memory Bad CMOS Battery Low CMOS Display Type Wrong CMOS Checksum Bad CMOS Settings Wrong CMOS Date Time Not Set DMA Error FDC Failure HDC Failure Checking NVRAM Explanation An error occurred with Gate A20 when switching to protected mode during the memory test Could not read sector from corresponding drive Corresponding drive in not an ATAPI device Run Setup to make sure device is selected correctly No response from diskette drive An error occurred when testing L2 cache Cache memory may be bad The battery may be losing power Replace the battery soon The display type is different than what has been stored in CMOS Check Setup to make sure type is correct The CMOS checksum is incorrect CMOS memory may have been corrupted Run Setup to reset values CMOS values are not the same as the last boot These values have either been corrupted or the battery has failed T
4. 76 Table 43 Runtime Code Uncompressed in F000 Shadow RAM Code 03 05 06 07 08 0B OC 0E OF 10 11 12 13 14 19 1A 23 24 25 27 28 2A 2B 2C 2D 2E 2F 30 31 32 34 37 38 39 3A Description of POST Operation NMI is Disabled To check soft reset power on BIOS stack set Going to disable cache if any POST code to be uncompressed CPU init and CPU data area init to be done CMOS checksum calculation to be done next Any initialization before keyboard BAT to be done next KB controller 1 B free To issue the BAT command to keyboard controller Any initialization after KB controller BAT to be done next Keyboard command byte to be written Going to issue Pin 23 24 blocking unblocking command Going to check pressing of lt INS gt lt END gt key during power on To init CMOS if Init CMOS in every boot is set or lt END gt key is pressed Going to disable DMA and Interrupt controllers Video display is disabled and port B is initialized Chipset init about to begin 8254 timer test about to start About to start memory refresh test Memory Refresh line is toggling Going to check 15 us ON OFF time To read 8042 input port and disable Megakey GreenPC feature Make BIOS code segment writeable To do any setup before Int vector init Interrupt vector initialization to begin To clear password if necessary Any initialization before setting video mode to be done Going for monochrome mod
5. Processor data sheets http www intel com design litcentr ICH6 addressing http developer intel com design chipsets datashts Custom splash screens http intel com design motherbd gen_indx htm Audio software and utilities http www intel com design motherbd LAN software and drivers http www intel com design motherbd Processor The board is designed to support an Intel Celeron processor in an LGA775 processor socket with a 533 MHz system bus See the Intel web site listed below for the most up to date list of supported processors For information about Refer to Supported processors for the D910GLDW board http www intel com design motherbd dw dw_proc htm CAUTION Use only the processors listed on web site above Use of unsupported processors can damage the board the processor and the power supply INTEGRATOR S NOTE Use only ATX12V compliant power supplies For information about Refer to Power supply connectors Section 2 8 2 1 page 47 System Memory The board has two DIMM sockets and supports the following memory features e 2 5 V only DDR SDRAM DIMMs with gold plated contacts e Unbuffered single sided or double sided DIMMs with the following restriction Double sided DIMMS with x16 organization are not supported 2 GB maximum total system memory Minimum total system memory 128 MB Non ECC DIMMs Serial Presence Detect DDR 400 MHz and DDR 333 MHz SDRAM DIMMs Intel Desktop Board D910GLDW Technical P
6. D C OM17318 Item Description A Processor voltage regulator area B Processor C Intel 82910GL GMCH D Intel 82801FB ICH6 Figure 20 Localized High Temperature Zones Technical Reference Table 31 provides maximum case temperatures for the Desktop Board D910GLDW components that are sensitive to thermal changes The operating temperature current load or operating frequency could affect case temperatures Maximum case temperatures are important when considering proper airflow to cool the Desktop Board D910GLDW Table 31 Thermal Considerations for Components Component Maximum Case Temperature Intel Celeron processor For processor case temperature see processor datasheets and processor specification updates Intel 82910GL GMCH 99 C under bias Intel 82801FB ICH6 110 C under bias For information about Refer to Intel Celeron processor datasheets and specification updates Section 1 3 page 15 2 13 Reliability The Mean Time Between Failures MTBF prediction is calculated using component and subassembly random failure rates The calculation is based on the Bellcore Reliability Prediction Procedure TR NWT 000332 Issue 4 September 1991 The MTBF prediction is used to estimate repair rates and spare parts requirements The MTBF data is calculated from predicted data at 55 C The MTBF for the D910GLDW board is 102 038 hours 59 Intel Desktop Board D910GLDW Technical Product Specification 2 14 Environmental Ta
7. CPU in real mode Going to disable gate A20 line and disable parity NMI 57 A20 address line parity NMI disable successful Going to adjust memory size depending on relocation shadow 58 Memory size adjusted for relocation shadow Going to clear Hit lt DEL gt message 59 Hit lt DEL gt message cleared lt WAIT gt message displayed About to start DMA and interrupt controller test 60 DMA page register test passed To do DMA 1 base register test 62 DMA 1 base register test passed To do DMA 2 base register test 65 DMA 2 base register test passed To program DMA unit 1 and 2 66 DMA unit 1 and 2 programming over To initialize 8259 interrupt controller 7F Extended NMI sources enabling is in progress 80 Keyboard test started Clearing output buffer checking for stuck key to issue keyboard reset command 81 Keyboard reset error stuck key found To issue keyboard controller interface test command 82 Keyboard controller interface test over To write command byte and init circular buffer 83 Command byte written global data init done To check for lock key continued 77 Intel Desktop Board D910GLDW Technical Product Specification 78 Table 43 Runtime Code Uncompressed in F000 Shadow RAM continued Code 84 85 86 87 88 89 8B 8C 8D 8F 91 95 96 97 98 99 9A 9B 9C 9D 9E A2 A3 A4 A5 A7 A8 A9 AA AB AC AD Description of POST Operation Lock key checking over To check for mem
8. Dependent on the standby power consumption of wake up devices used in the system Product Description 1 12 1 2 Wake up Devices and Events Table 8 lists the devices or specific events that can wake the computer from specific states Table 8 Wake up Devices and Events These devices events can wake up the computer from this state LAN S1 S3 S4 S5 Note Modem back panel Serial Port A S1 S3 PME signal S1 S3 S4 S5 Note Power switch S1 S3 S4 S5 PS 2 devices S1 S3 RTC alarm S1 S3 S4 S5 USB S1 S3 WAKE S1 S3 S4 S5 Note For LAN and PME signal S5 is disabled by default in the BIOS Setup program Setting this option to Power On will enable a wake up event from LAN in the S5 state da NOTE The use of these wake up events from an ACPI state requires an operating system that provides full ACPI support In addition software drivers and peripherals must fully support ACPI wake events 1 12 2 Hardware Support A CAUTION Ensure that the power supply provides adequate 5 V standby current if LAN wake capabilities and Instantly Available PC technology features are used Failure to do so can damage the power supply The total amount of standby current required depends on the wake devices supported and manufacturing options The board provides several power management hardware features including Power connector Fan connectors LAN wake capabilities Instantly Available PC technology Resume on
9. and Warnings da NOTE Notes call attention to important information SK INTEGRATOR S NOTES Integrator s notes are used to call attention to information that may be useful to system integrators A CAUTION Cautions are included to help you avoid damaging hardware or losing data A WARNING Warnings indicate conditions which if not observed can cause personal injury Intel Desktop Board D910GLDW Technical Product Specification Other Common Notation NxnX GB GB sec KB Kbit kbits sec MB MB sec Mbit Mbit sec xxh x x V Used after a signal name to identify an active low signal such as USBPO When used in the description of a component N indicates component type xn are the relative coordinates of its location on the Desktop Board D910GLDW and X is the instance of the particular part at that general location For example J5J1 is a connector located at 5J Itis the first connector in the 5J area Gigabyte 1 073 741 824 bytes Gigabytes per second Kilobyte 1024 bytes Kilobit 1024 bits 1000 bits per second Megabyte 1 048 576 bytes Megabytes per second Megabit 1 048 576 bits Megabits per second An address or data value ending with a lowercase h indicates a hexadecimal value Volts Voltages are DC unless otherwise specified This symbol is used to indicate third party brands and names that are the property of their respective owners Contents 1 Product Description 2 1 1
10. Instantly Available PC technology the 5 V standby line for the power supply must be capable of providing adequate 5 V standby current Failure to provide adequate standby current when implementing Instantly Available PC technology can damage the power supply Instantly Available PC technology enables the board to enter the ACPI S3 Suspend to RAM sleep state While in the S3 sleep state the computer will appear to be off the power supply is off and the front panel LED is amber if dual colored or off if single colored When signaled by a wake up device or event the system quickly returns to its last known wake state Table 8 on page 33 lists the devices and events that can wake the computer from the S3 state The board supports the PCI Bus Power Management Interface Specification Add in boards that also support this specification can participate in power management and can be used to wake the computer The use of Instantly Available PC technology requires operating system support and PCI 2 2 compliant add in cards PCI Express add in cards and drivers 1 12 2 5 Resume on Ring The operation of Resume on Ring can be summarized as follows e Resumes operation from ACPI S1 or S3 states e Detects incoming call similarly for external and internal modems e Requires modem interrupt be unmasked for correct operation 1 12 2 6 Wake from USB USB bus activity wakes the computer from ACPI S1 or S3 states Jal NOTE Wake from USB requires t
11. PCI Bus Terminology CARAS castidad 9 OAE AEE EEN e 10 1 2 1 Feature SUMIMALY aa 10 1 2 2 Manufacturing Options escojas dla aaa 11 1 2 3 ele BE e EE 12 1 2 4 BIO CK Ren E 14 1 3 Online SUpport EE 15 TA PFOCOSSOM EE 15 1 5 System ee EE 15 1 5 1 Memory Configurations ica 17 1 6 Intel 910GL Chipset EE 19 1 6 1 Intel 910GL Graphics Controller cusco 19 1 6 2 UB 20 1 6 3 IDE SUPDO corra ia 20 1 6 4 Real Time Clock CMOS SRAM and DBatten 22 1 7 PGI Express Connector eege stacy ssctects dee 22 ES COINS eae arate ae Ee EE E 23 1 8 1 EB A e 23 1 8 2 Parallel duel dee cuca cdo dde 23 1 8 3 Diskette Drive Correll t eegen e irkgedugerdeeu art dra 23 1 8 4 Keyboard and Mouse Interface eecceccccceeeeeeeeeseeeeeeeeeeeeeeseenseeeeeneeeeees 23 1 9 Audio SUS Siesta adi ei 24 1 9 1 Audio Subsystem Software cenicero EEEAS EE ECENdEE ENNEN 24 1 9 2 Audio eene 24 1 9 3 Intel High Definition Audio Subsystem coococococconononcnnonenencnninonnenrorinonenoso 25 1 10 LAN Subsystem OPIO on id 26 1 10 1 Intel 82562EZ Physical Layer Interface Device 26 1 10 2 Alert Standard Format ASF Support reueg emetic ieee toad 27 1 10 3 EAN Subsystem SOMWaNG asian 27 1 11 Hardware Management Subsystem ENEE 28 1 11 1 Hardware Monitoring and Fan Control AG 28 1 11 2 Thermal MoNItOrINO isosconcoicciiio Dis SES 29 da Fan MORON patada idad 30 1 11 4 Fan Speed Control Intel Precision Cooling Technologie 30 1 11 5 Chassis Intrusio
12. Ring Wake from USB Wake from PS 2 keyboard PME signal wake up support WAKE signal wake up support LAN wake capabilities and Instantly Available PC technology require power from the 5 V standby line 33 Intel Desktop Board D910GLDW Technical Product Specification Resume on Ring enables telephony devices to access the computer when it is in a power managed state The method used depends on the type of telephony device external or internal lt j NOTE The use of Resume on Ring and Wake from USB technologies from an ACPI state requires an operating system that provides full ACPI support 1 1221 Power Connector ATX12V compliant power supplies can turn off the system power through system control When an ACPI enabled system receives the correct command the power supply removes all non standby voltages When resuming from an AC power failure the computer returns to the power state it was in before power was interrupted on or off The computer s response can be set using the Last Power State feature in the BIOS Setup program s Boot menu For information about Refer to The location of the main power connector Figure 12 page 44 The signal names of the main power connector Table 22 page 47 1 12 2 2 Fan Connectors The function operation of the fan connectors is as follows e The fans are on when the board is in the SO or S1 state e The fans are off when the board is off or in the S3 S4 or S5 state e Bach fan co
13. about Refer to The location of the keyboard and mouse connectors Figure 11 page 42 23 Intel Desktop Board D910GLDW Technical Product Specification 1 9 Audio Subsystem The board supports the Intel High Definition audio subsystem based on the Realtek ALC860 codec The audio subsystem supports the following features e Advanced jack sense front and rear panel that enables the audio codec to recognize the device that is connected to an audio port All jacks are capable of retasking according to user s definition or can be automatically switched depending on the recognized device type e Stereo input and output for all jacks e A signal to noise S N ratio of 90 dB SK INTEGRATOR S NOTE For the front panel jack sensing and automatic retasking feature to function a front panel daughter card that is designed for Intel High Definition Audio must be used Otherwise an AC 97 style audio front panel connector will be assumed and the Line Out and Mic In functions will be permanent 1 9 1 Audio Subsystem Software Audio software and drivers are available from Intel s World Wide Web site For information about Refer to Obtaining audio software and drivers Section 1 3 page 15 1 9 2 Audio Connectors The board contains audio connectors on both the back panel and the component side of the board The front panel audio connector located on the component side of the board is a 2 x 5 pin connector that provides mic in and line out sign
14. boot speed e Choose a hard drive with parameters such as power up to data ready less than eight seconds that minimize hard drive startup delays e Select a CD ROM drive with a fast initialization rate This rate can influence POST execution time e Eliminate unnecessary add in adapter features such as logo displays screen repaints or mode changes in POST These features may add time to the boot process e Try different monitors Some monitors initialize and communicate with the BIOS more quickly which enables the system to boot more quickly 3 8 2 Intel Rapid BIOS Boot Use of the following BIOS Setup program settings reduces the POST execution time In the Boot Menu e Set the hard disk drive as the first boot device As a result the POST does not first seek a diskette drive which saves about one second from the POST execution time e Disable Quiet Boot which eliminates display of the logo splash screen This could save several seconds of painting complex graphic images and changing video modes e Enable Intel Rapid BIOS Boot This feature bypasses memory count and the search for a diskette drive In the Peripheral Configuration submenu disable the LAN device if it will not be used This can reduce up to four seconds of option ROM boot time Jal NOTE 70 It is possible to optimize the boot process to the point where the system boots so quickly that the Intel logo screen or a custom logo splash screen will not be
15. component side C US FCC Declaration of Conformity logo mark for Class B equipment includes Intel name and D910GLDW model designation component i Tested To Comply side FC With FCC Standards Trade Name Model Number FOR HOME OR OFFICE USE CE mark Declares compliance to European Union EU EMC directive 89 336 EEC and Low Voltage directive 73 23 EEC component side The CE mark should also be on the shipping container Australian Communications Authority ACA C Tick mark Includes adjacent Intel supplier code number N 232 The C tick mark should also be on the shipping container Printed wiring board manufacturer s recognition mark consists of a V 0 or 94V 0 unique UL recognized manufacturer s logo along with a flammability rating solder side 64 3 Overview of BIOS Features What This Chapter Contains 3 1 a iio e TL y PPP RO oe eee ee ere ree 65 3 2 BIOS Flash Memory Organization ENEE 66 3 3 Resource COMMOUEALON usd o aci 66 3 4 System Management BIOS SMBIOS EEN 67 30 Leg cy y USB leen astra aii iaa 67 3 6 BIOS MATS o sa 68 3 7 BOO OPUON Sarri a a eaaa a E A a ncaa Te aA aa giaid aetoz antag iat 69 3 8 Fast Booting Systems with Intel Rapid BIOS Boot 70 3 9 BIOS Security Features ee eege dee 71 3 1 Introduction The board uses an Intel AMI BIOS that is stored in the Firmware Hub FWH and can be updated using a disk based program The FWH contains the BIOS Setup program POST the PCI a
16. digital apparatus complies with Canadian ICES 003 Cet appereil num rique de la classe B est conforme a la norme NMB 003 du Canada 2 15 3 European Union Declaration of Conformity Statement 62 We Intel Corporation declare under our sole responsibility that the product Intel Desktop Board D910GLDW is in conformity with all applicable essential requirements necessary for CE marking following the provisions of the European Council Directive 89 336 EEC EMC Directive and Council Directive 73 23 EEC Safety Low Voltage Directive The product is properly CE marked demonstrating this conformity and is for distribution within all member states of the EU with no restrictions L This product follows the provisions of the European Directives 89 336 EEC and 73 23 EEC Dansk Dette produkt er i overensstemmelse med det europ iske direktiv 89 336 EEC amp 73 23 EEC Dutch Dit product is in navolging van de bepalingen van Europees Directief 89 336 EEC amp 73 23 EEC Technical Reference Francais Ce produit est conforme aux exigences de la Directive Europ enne 89 336 EEC amp 73 23 EEC Deutsch Dieses Produkt entspricht den Bestimmungen der Europ ischen Richtlinie 89 336 EEC amp 73 23 EEC Icelandic Pessi vara stenst regluger Evr pska Efnahags Bandalagsins n mer 89 336 EEC amp 73 23 EEC Italiano Questo prodotto conforme alla Direttiva Europea 89 336 EEC amp 73 23 EEC Norsk Dette produktet er i henhold til
17. drives The BIOS determines the capabilities of each drive and configures them to optimize capacity and performance To take advantage of the high capacities typically available today hard drives are automatically configured for Logical Block Addressing LBA and 66 Overview of BIOS Features to PIO Mode 3 or 4 depending on the capability of the drive You can override the auto configuration options by specifying manual configuration in the BIOS Setup program To use ATA 66 100 features the following items are required e An ATA 66 100 peripheral device e An ATA 66 100 compatible cable e ATA 66 100 operating system device drivers lt j NOTE Do not connect an ATA device as a slave on the same IDE cable as an ATAPI master device For example do not connect an ATA hard drive as a slave to an ATAPI CD ROM drive 3 4 System Management BIOS SMBIOS SMBIOS is a Desktop Management Interface DMI compliant method for managing computers in a managed network The main component of SMBIOS is the Management Information Format MIF database which contains information about the computing system and its components Using SMBIOS a system administrator can obtain the system types capabilities operational status and installation dates for system components The MIF database defines the data and provides the method for accessing this information The BIOS enables applications such as third party management software to use SMBIOS The BIOS st
18. e Setting the user password restricts who can boot the computer The password prompt will be displayed before the computer is booted If only the supervisor password is set the computer boots without asking for a password If both passwords are set the user can enter either password to boot the computer e For enhanced security use different passwords for the supervisor and user passwords e Valid password characters are A Z a z and 0 9 Passwords may be up to 16 characters in length Table 39 shows the effects of setting the supervisor password and user password This table is for reference only and is not displayed on the screen Table 39 Supervisor and User Password Functions Supervisor Password to Password Password Set Mode User Mode Setup Options Enter Setup During Boot Neither Can change all Can change all None None None options Note options Note Supervisor Can change all Can changea Supervisor Password Supervisor None only options limited number of options User only Can change all Enter Password User User options Clear User Password Supervisor Can change all Can changea Supervisor Password Supervisor or Supervisor or and user set options limited number Enter Password user user of options Note If no password is set any user can change all Setup options 71 Intel Desktop Board D910GLDW Technical Product Specification 72 4 Error Messages and Beep Codes What This Chapter Contains
19. fan Figure 9 Thermal Monitoring 29 Intel Desktop Board D910GLDW Technical Product Specification 1 11 3 Fan Monitoring Fan monitoring can be implemented using Intel Desktop Utilities LANDesk software or third party software The level of monitoring and control is dependent on the hardware monitoring ASIC used with the Desktop Board For information about Refer to The functions of the fan connectors Section 1 12 2 2 page 34 1 11 4 Fan Speed Control Intel Precision Cooling Technology Intel Precision Cooling Technology automatically adjusts the processor fan speed based on the processor thermal diode temperature and adjusts the chassis fan speeds depending on the system temperature System fan noise may be reduced by operating controlled chassis and processor fans at the minimum necessary speeds The processor and chassis fan speed control features can be disabled independently through the desktop board BIOS Disabling the processor fan speed control will result in the fan operating at full speed if it is not a self controlled fan It is recommended that processor fan speed control remain enabled default BIOS setting when using the processor fan heat sink included with Intel boxed processors Disabling the chassis fan speed control results in chassis fans always operating at full speed The chassis fan speed control feature should be disabled if a self controlled chassis fan is attached to any controlled chassis fan header
20. low power state Table 7 lists the power states supported by the board along with the associated system power targets See the ACPI specification for a complete description of the various system and power states Table 7 Power States and Targeted System Power Global States GO working state G1 sleeping state G1 sleeping state G1 sleeping state G2 S5 G3 mechanical off AC power is disconnected from the computer Notes Process Targeted System Sleeping States or States Device States Power Note 1 SO working CH DO working state Full power gt 30 W working S1 Processor C1 stop D1 D2 D3 device 5 W lt power lt 52 5 W stopped grant specification specific S3 Suspend to No power D3 no power except Power lt 5 W Note 2 RAM Context for wake up logic saved to RAM S4 Suspend to No power D3 no power except Power lt 5 W Note 2 disk Context for wake up logic saved to disk S5 Soft off No power D3 no power except Power lt 5 W Note 2 Context not saved for wake up logic Cold boot is required No power to the No power D3 no power for No power to the system wake up logic except system Service can when provided by be performed safely battery or external source 1 Total system power is dependent on the system configuration including add in boards and peripherals powered by the system chassis power supply 2
21. options on the Desktop Board D91OGLDW Not every manufacturing option is available in all marketing channels Please contact your Intel representative to determine which manufacturing options are available to you Table 2 Manufacturing Options IEEE 1394a IEEE 1394a controller and two IEEE 1394a connectors Interface LAN Support 10 100 Mbits sec LAN subsystem using the Intel 82562EZ Platform LAN Connect PLC device For information about Refer to Available configurations for the Desktop Board D910GLDW Section 1 3 page 15 11 Intel Desktop Board D910GLDW Technical Product Specification 1 2 3 Board Layout Figure 1 shows the location of the major components on the Desktop Board D910GLDW AB C D E gt E 8 _ El O p DD 8 RE EE eg ain d SA CC D ESTA E G BB eo EE AA A ie a H 2 3 UY J 8 K YS L cg um 4 O W UIS X V T RQ P O N M OM17306 Figure 1 Board Components Table 3 lists the components identified in Figure 1 Product Description Table 3 Board Components Shown in Figure 1 Item Callout from
22. x 1536 at 75 Hz refresh High performance 3 D setup and render engine High quality performance texture engine Display Integrated 24 bit 400 MHz RAMDAC DDC2B compliant interface Video hardware motion compensation for software MPEG2 decode Dynamic Video Memory Technology DVMT support up to 224 MB e Intel Zoom Utility For information about Refer to DVMT Section 0 page 20 Obtaining graphics software and utilities Section 1 3 page 15 Intel Desktop Board D910GLDW Technical Product Specification 1 6 1 1 Dynamic Video Memory Technology DVMT DVMT enables enhanced graphics and memory performance through Direct AGP and highly efficient memory utilization DVMT ensures the most efficient use of available system memory for maximum 2 D 3 D graphics performance Up to 224 MB of system memory can be allocated to DVMT on systems that have 512 MB or more of total system memory installed Up to 128 MB can be allocated to DVMT on systems that have 256 MB but less than 512 MB of total installed system memory Up to 64 MB can be allocated to DVMT when less than 256 MB of system memory is installed DVMT returns system memory back to the operating system when the additional system memory is no longer required by the graphics subsystem DVMT will always use a minimal fixed portion of system physical memory as set in the BIOS Setup program for compatibility with legacy applications An example of this would be when using VGA graphics under DO
23. 94a connector optional PCI Express x1 bus add in card connector 45 Intel Desktop Board D910GLDW Technical Product Specification 46 Table 17 Front Panel Audio Connector Pin Signal Name i Signal Name 1 Port E Port 1 Left Channel Ground 3 Port E Port 1 Right Channel 4 Presence dongle present 5 Port F Port 2 Right Channel 6 Port E Port 1 Sense return jack detection 7 Port E Port 1 and Port F Port 2 Key Sense send jack detection 9 Port F Port 2 Left Channel 10 Port F Port 2 Sense return jack detection INTEGRATOR S NOTE The front panel audio connector is colored yellow Table 18 Front Chassis Fan and Rear Chassis Fan Connectors Pin Signal Name 1 Control 2 12 V 3 Tach Pin Signal Name 1 Ground 2 12 V 3 FAN_TACH 4 FAN_CONTROL Pin Signal Name 1 Intruder 2 Ground Table 21 Serial ATA Connectors Signal Name Ground TXP TXN Ground RXN RXP Ground 2 8 2 1 Power Supply Connectors The board has two power supply connectors Technical Reference e Main power a 2 x 12 connector This connector is compatible with 2 x 10 connectors previously used on Intel Desktop boards The board supports the use of ATX12V power supplies with either 2 x 10 or 2 x 12 main power cables When using a power supply with a 2 x 10 main power cable attach that cable on the rightmost pins of the main power connector leaving pins 11 12 23 and 24 unconnected e ATX12
24. America 1 800 548 4725 Europe 44 0 1793 431 155 France 44 0 1793 421 777 Germany 44 0 1793 421 333 other Countries 708 296 9333 Intel Pentium and Celeron are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2004 Intel Corporation All rights reserved Preface This Technical Product Specification TPS specifies the board layout components connectors power and environmental requirements and the BIOS for the Intel Desktop Board D910GLDW It describes the standard product and available manufacturing options Intended Audience The TPS is intended to provide detailed technical information about the Desktop Board D910GLDW and their components to the vendors system integrators and other engineers and technicians who need this level of information It is specifically not intended for general audiences What This Document Contains Chapter Description 1 A description of the hardware used on the Desktop Board D910GLDW 2 A map of the resources of the Desktop Board 3 The features supported by the BIOS Setup program 4 A description of the BIOS error messages beep codes and POST codes Typographical Conventions This section contains information about the conventions used in this specification Not all of these symbols and abbreviations appear in all specifications of this type Notes Cautions
25. Board D910GLDW Technical Product Specification 2 8 2 Component side Connectors Figure 12 shows the locations of the component side connectors A CG E F B D OM17315 Figure 12 Component side Connectors Table 16 lists the component side connectors identified in Figure 12 44 Technical Reference Table 16 Component side Connectors Shown in Figure 12 Item Callout from Figure 12 A lt EI A 0 D O TIO Z S m A e I 0 n m Oo oO D Description Front panel audio connector PCI Conventional bus add in card connector 2 Front panel IEEE 1394a connector optional PCI Conventional bus add in card connector 1 Rear chassis fan connector 12V power connector ATX12V Processor fan connector Power connector Diskette drive connector Parallel ATA IDE connector Chassis intrusion connector Front chassis fan connector Serial ATA connector 1 Serial ATA connector 3 Serial ATA connector 2 Serial ATA connector 0 Auxiliary front panel power LED connector Front panel connector Front panel USB connector Front panel USB connector Front panel IEEE 13
26. Definition Audio Subsystem Block Diagram For information about Refer to The back panel audio connectors Figure 11 page 42 25 Intel Desktop Board D910GLDW Technical Product Specification 1 10 LAN Subsystem Optional The 10 100 Mbits sec LAN subsystem consists of the following e The Intel 82801FB ICH6 e An Intel 82562EZ Platform LAN Connect PLC device for 10 100 Mbits sec Ethernet LAN connectivity e AnRJ 45 LAN connector with integrated status LEDs Additional features of the LAN subsystem include e CSMA CD protocol engine e LAN Connect Interface LCI between the 82562EZ and the ICH6 e PCI Conventional bus power management Supports ACPI technology Supports LAN wake capabilities 1 10 1 Intel 82562EZ Physical Layer Interface Device The Intel 82562EZ provides the following functions e Basic 10 100 Ethernet LAN connectivity e Full device driver compatibility e Programmable transit threshold e Configuration EEPROM that contains the MAC address 1 10 1 1 RJ 45 LAN Connector with Integrated LEDs 26 Two LEDs are built into the RJ 45 LAN connector shown in Figure 8 below Green LED Yellow LED OM15076 Figure 8 LAN Connector LED Locations Table 5 describes the LED states when the board is powered up and the 10 100 Mbits sec LAN subsystem is operating Table 5 LAN Connector LED States LED Color Condition Green LAN link is not established On LAN link is established LAN activity i
27. Figure 1 HI Z N lt x S lt c o ao 3 o z z m x z o a m o o w gt u o ele Description Realtek ALC860 audio codec Front panel audio connector Yellow PCI Conventional bus add in card connectors Rear chassis fan connector Back panel connectors 12V power connector ATX12V LGA775 processor socket Hardware monitoring and fan control ASIC Processor fan connector Intel 82910GL GMCH DIMM Channel A socket DIMM Channel B socket I O controller Power connector Diskette drive connector Parallel ATE IDE connector Battery Chassis intrusion connector BIOS Setup configuration jumper block 4 Mbit Firmware Hub FWH Front chassis fan connector Serial ATA connectors Auxiliary front panel power LED connector Front panel connector Front panel USB connectors Intel 82801FB I O Controller Hub ICH6 Front panel IEEE 1394a connectors optional IEEE 1394a controller optional Speaker PCI Express x1 bus add in card connector Intel Desktop Board D910GLDW Technical Product Specification 1 2 4 Block Diagr am Figure 2 is a block diagram of the major functional areas of the board PCI Express x1 Slot 1 4 Parallel ATA IDE Connector a PCI Express x1 Interface Parallel ATA IDE Interface Back Panel Front Panel USB gt USB Ports Serial Ports D wd Parallel Port Controller t PS 2 Mouse PS 2 Keyboard
28. High Byte Functions ion ie ec 80 See 80 1 Product Description What This Chapter Contains a sch o e zech o sch o o sch sch md 1 1 1 PCI Bus Terminology AMI cui oi aa A ere Eege OA a ea a a a a N POCOS ctm di dd ie EE beiei 5 System Memo esa in ad 6 Intel 910GL Chipset EE ft PGI Express Connector nee nnna en teta 2 MO Control aiii io E e 10 LAN Subsystem OPIO as et 11 Hardware Management Subsystem AEN 12 Power Management dd PCI Bus Terminology Change Previous generations of Intel Desktop Boards used an add in card connector referred to as PCI This generation of Intel Desktop Boards adds a new technology for add in cards PCI Express The 32 bit parallel bus previously referred to as PCI is now called PCI Conventional Intel Desktop Board D910GLDW Technical Product Specification 1 2 Overview 1 2 1 Feature Summary Table 1 summarizes the major features of the Desktop Board D910GLDW Table 1 Feature Summary Form Factor Processor Memory Chipset Video Audio UO Control USB Peripheral Interfaces BIOS Instantly Available PC Technology microATX Form Factor 9 60 inches by 9 60 inches 243 84 millimeters by 243 84 millimeters Support for an Intel Celeron processor in an LGA775 socket e Two DDR SDRAM Dual Inline Memory Module DIMM sockets e Support for DDR 400 MHz and DDR 333 MHz DIMMs e Support for up to 2 GB of system memory Intel 910GL Chipset consisting of
29. Intel Desktop Board D910GLDW Technical Product Specification October 2004 Order Number C88966 002 The Intel Desktop Board D910GLDW may contain design defects or errors known as errata that may cause the product to deviate from published specifications Current characterized errata are documented in the Intel Desktop Board D910GLDW Specification Update Revision History Revision Revision History Date 001 First release of the Intel Desktop Board D910GLDW Technical Product September 2004 Specification 002 Second release of the Intel Desktop Board D910GLDW Technical Product October 2004 Specification This product specification applies to only standard Intel Desktop Board D910GLDW with BIOS identifier WB91X10J 86A Changes to this specification will be published in the Intel Desktop Board D910GLDW Specification Update before being incorporated into a revision of this document INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT CO
30. PYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL LIFE SAVING OR LIFE SUSTAINING APPLICATIONS Intel Corporation may have patents or pending patent applications trademarks copyrights or other intellectual property rights that relate to the presented subject matter The furnishing of documents and other materials and information does not provide any license express or implied by estoppel or otherwise to any such patents trademarks copyrights or other intellectual property rights Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Intel desktop boards may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order Copies of documents which have an ordering number and are referenced in this document or other Intel literature may be obtained from Intel Corporation P O Box 5937 Denver CO 80217 9808 or call in North
31. S Once loaded the operating system and graphics drivers allocate additional system memory to the graphics buffer as needed for performing graphics functions Jal NOTE The use of DVMT requires operating system driver support 1 6 2 USB The board supports up to eight USB 2 0 ports supports UHCI and EHCI and uses UHCI and EHCI compatible drivers The ICH6 provides the USB controller for all ports The port arrangement is as follows e Four ports are implemented with dual stacked back panel connectors adjacent to the audio connectors e Four ports are routed to two separate front panel USB connectors NOTE Computer systems that have an unshielded cable attached to a USB port may not meet FCC Class B requirements even if no device is attached to the cable Use shielded cable that meets the requirements for full speed devices For information about Refer to The location of the USB connectors on the back panel Figure 11 page 42 The location of the front panel USB connectors Figure 12 page 44 1 6 3 IDE Support 20 The board provides five IDE interface connectors e One parallel ATA IDE connector that supports two devices e Four serial ATA IDE connectors that support one device per connector Product Description 1 6 3 1 Parallel ATE IDE Interface The ICH6 s Parallel ATA IDE controller has one bus mastering Parallel ATA IDE interface The Parallel ATA IDE interface supports the following modes e Programmed I O PIO pr
32. TA IDE connector Figure 12 page 44 1 6 3 2 Serial ATA Interfaces The ICH6 s Serial ATA controller offers four independent Serial ATA ports with a theoretical maximum transfer rate of 150 MB s per port One device can be installed on each port for a maximum of four Serial ATA devices A point to point interface is used for host to device connections unlike Parallel ATA IDE which supports a master slave configuration and two devices per channel For compatibility the underlying Serial ATA functionality is transparent to the operating system The Serial ATA controller can operate in both legacy and native modes In legacy mode standard IDE I O and IRQ resources are assigned IRQ 14 and 15 In Native mode standard PCI Conventional bus resource steering is used Native mode is the preferred mode for configurations using the Windows XP and Windows 2000 operating systems 21 Intel Desktop Board D910GLDW Technical Product Specification lt j NOTE Many Serial ATA drives use new low voltage power connectors and require adaptors or power supplies equipped with low voltage power connectors For more information see http www serialata org For information about Refer to The location of the Serial ATA IDE connectors Figure 12 page 44 1 6 4 Real Time Clock CMOS SRAM and Battery A coin cell battery CR2032 powers the real time clock and CMOS memory When the computer is not plugged into a wall socket the battery has an estimat
33. V power a 2 x 2 connector This connector provides power directly to the processor voltage regulator and must always be used Failure to do so will prevent the board from booting Table 22 Main Power Connector Signal Name 3 3 V 3 3 V Ground 5 V Ground 5 V Ground PWRGD Power Good 5 V Standby 12 V 12 V Note 2 x 12 connector detect Note Note When using a 2 x 10 power supply cable this pin will be unconnected Table 23 ATX12V Power Connector Pin Signal Name 1 Ground Pin 13 14 15 16 17 18 19 20 21 22 23 24 Signal Name 3 3 V 12 V Ground PS ON power supply remote on off Ground Ground Ground No connect 5 V 5 V 5 V Note Ground Note Signal Name 47 Intel Desktop Board D910GLDW Technical Product Specification 2 8 2 2 Add in Card Connectors The board has the following add in card connectors e One PCI Express x1 connector The x1 interface support simultaneous transfer speeds up to 500 MBytes sec e Two PCI Conventional rev 2 2 compliant local bus slots The SMBus is routed to PCI Conventional bus connector 2 only ATX expansion slot 6 PCI Conventional bus add in cards with SMBus support can access sensor data and other information residing on the Desktop Board Note the following considerations for the PCI Conventional bus connectors e All of the PCI Conventional bus connectors are bus master capable e SMBus signals are rou
34. als for front panel audio connectors For information about Refer to The location of the front panel audio connector Figure 12 page 44 The signal names of the front panel audio connector Table 17 page 46 24 Product Description 1 9 3 Intel High Definition Audio Subsystem The Intel High Definition Audio subsystem includes the following e ntel 82801FB I O Controller Hub ICH6 e Realtek ALC860 audio codec e Microphone input that supports a single dynamic condenser or electret microphone The front and back audio connectors are configurable through the audio device drivers The available configurable audio ports are shown in Figure 6 Front Panel Back Panel Audio Connectors Audio Connectors Line Out Mic In Retasking Jack F Retasking Jack E Line In Port 2 Port 1 Retasking Jack C O Line Out Retasking Jack D Mic In Retasking Jack B OM16989 Figure 6 Front Back Panel Audio Connector Options for High Definition Audio Subsystem Figure 7 is a block diagram of the High Definition audio subsystem Mic In Retasking Jack B _____ 82801FB Intel Line In Retasking Jack C __ UO Controller ae ALC860 a gt Hub a High Definition Audio Codec Line Out Retasking Jack D ICH6 Audio Link a Front Panel Mic In Retasking Jack E Port 1 8 a Front Panel Line Out Retasking Jack F Port 2 OM17311 Figure 7 High
35. apacities of both DIMM channels are equal Technology and device width can vary from one channel to the other but the installed memory capacity for each channel must be equal If different speed DIMMs are used between channels the slowest memory timing will be used e Single channel Asymmetric mode This mode is equivalent to single channel bandwidth operation for real world applications This mode is used when only a single DIMM is installed or the memory capacities are unequal Technology and device width can vary from one channel to the other If different speed DIMMs are used between channels the slowest memory timing will be used Figure 3 illustrates the memory channel and DIMM configuration Channel A DIMM 0 Channel B DIMM 0 OM17308 Figure 3 Memory Channel Configuration Intel Desktop Board D910GLDW Technical Product Specification 1 5 1 1 Dual Channel Interleaved Mode Configuration Figure 4 shows a dual channel configuration using two DIMMs In this example the DIMM sockets of both channels are populated with identical DIMMs Channel A DIMM 0 Channel B DIMM 0 OM17309 Figure 4 Dual Channel Interleaved Mode Configuration with Two DIMMs 1 5 1 2 Single Channel Asymmetric Mode Configuration Jal NOTE Dual channel Interl
36. bestemmelsene i det europeiske direktivet 89 336 EEC amp 73 23 EEC Portuguese Este produto cumpre com as normas da Diretiva Europ ia 89 336 EEC amp 73 23 EEC Espanol Este producto cumple con las normas del Directivo Europeo 89 336 EEC amp 73 23 EEC Svenska Denna produkt har tillverkats i enlighet med EG direktiv 89 336 EEC amp 73 23 EEC 2 15 4 Product Ecology Statements The following information is provided to address worldwide product ecology concerns and regulations 2 15 4 1 Disposal Considerations This product contains the following materials that may be regulated upon disposal lead solder on the printed wiring board assembly 2 15 4 2 Recycling Considerations Intel encourages its customers to recycle its products and their components e g batteries circuit boards plastic enclosures etc whenever possible In the U S a list of recyclers in your area can be found at http www eiae org In the absence of a viable recycling option products and their components must be disposed of in accordance with all applicable local environmental regulations 63 Intel Desktop Board D910GLDW Technical Product Specification 2 15 5 Product Certification Markings Board Level Table 35 lists the board s product certification markings Table 35 Product Certification Markings Description Marking UL joint US Canada Recognized Component mark Includes adjacent 3 UL file number for Intel Desktop Boards E210882
37. ble 32 lists the environmental specifications for the board Table 32 Environmental Specifications Parameter Specification Temperature 40 C to 70 C 0 C to 55 C Non Operating Operating Shock Unpackaged 50 g trapezoidal waveform Velocity change of 170 inches second Half sine 2 millisecond Packaged Product Weight pounds Free Fall inches Velocity Change inches sec Vibration Unpackaged 5 Hz to 20 Hz 0 01 g Hz sloping up to 0 02 g Hz 20 Hz to 500 Hz 0 02 g Hz flat Packaged 5 Hz to 40 Hz 0 015 g Hz flat 40 Hz to 500 Hz 0 015 g Hz sloping down to 0 00015 g Hz 60 Technical Reference 2 15 Regulatory Compliance This section describes the Desktop Board s compliance with U S and international safety and electromagnetic compatibility EMC regulations 2 15 1 Safety Regulations Table 33 lists the safety regulations the Desktop Board D910GLDW complies with when correctly installed in a compatible host system Table 33 Safety Regulations Regulation UL 60950 1 2003 CSA C22 2 No 60950 1 03 EN 60950 1 2002 IEC 60950 1 2001 First Edition 2 15 2 EMC Regulations Title Information Technology Equipment Safety Part 1 General Requirements USA and Canada Information Technology Equipment Safety Part 1 General Requirements European Union Information Technology Equipment Safety Part 1 General R
38. e Intel 82910GL Graphics Memory Controller Hub GMCH e Intel 82801FB I O Controller Hub ICH6 e 4 Mbit Firmware Hub FWH Intel GMA900 onboard graphics subsystem Intel High Definition Audio subsystem using the Realtek ALC860 audio codec LPC Bus I O controller Support for USB 2 0 devices e Eight USB ports e One serial port e One parallel port e Four Serial ATA interfaces e One Parallel ATA IDE interface with UDMA 33 ATA 66 100 support e One diskette drive interface e PS 2 keyboard and mouse ports e 4 Mbit FWH e Intel Rapid BIOS Boot e Support for Advanced Configuration and Power Interface ACPI Plug and Play and SMBIOS e Support for PCI Local Bus Specification Revision 2 2 e Support for PCI Express Revision 1 0a e Suspend to RAM support e Wake on PCI RS 232 front panel PS 2 devices and USB ports continued Product Description Table 1 Feature Summary continued Expansion Capabilities e Two PCI Conventional bus add in card connectors SMBus routed to PCI Conventional bus connector 2 e One PCI Express x1 bus add in card connector Hardware Monitor Subsystem e Hardware monitoring and fan control ASIC e Voltage sense to detect out of range power supply voltages e Thermal sense to detect out of range thermal values e Three fan connectors e Three fan sense inputs used to monitor fan activity e Fan speed control 1 2 2 Manufacturing Options Table 2 describes the manufacturing
39. e and color mode setting Different buses init system static output devices to start if present See Section 4 3 for details of different buses To give control for any setup required before optional video ROM check To look for optional video ROM and give control To give control to do any processing after video ROM returns control If EGA VGA not found then do display memory R W test EGA VGA not found Display memory R W test about to begin Display memory R W test passed About to look for the retrace checking Display memory R W test or retrace checking failed To do alternate Display memory R W test Alternate Display memory R W test passed To look for the alternate display retrace checking Video display checking over Display mode to be set next Display mode set Going to display the power on message Different buses init input IPL general devices to start if present See Section 4 3 for details of different buses Display different buses initialization error messages See Section 4 3 for details of different buses New cursor position read and saved To display the Hit lt DEL gt message continued Error Messages and Beep Codes Table 43 Runtime Code Uncompressed in F000 Shadow RAM continued Code Description of POST Operation 40 To prepare the descriptor tables 42 To enter in virtual mode for memory test 43 To enable interrupts for diagnostics mode 44 To initialize data to check memory wrap ar
40. eaved mode configurations provide the highest memory throughput Figure 5 shows a single channel configuration using one DIMM In this example only the Channel A DIMM socket is populated Channel B is not populated Channel A DIMM O Channel B DIMM 0 2 OM17310 Figure 5 Single Channel Asymmetric Mode Configuration with One DIMM Product Description 1 6 Intel 910GL Chipset The Intel 910GL chipset consists of the following devices Intel 82910GL Graphics Memory Controller Hub GMCH with Direct Media Interface DMI interconnect Intel 82801FB I O Controller Hub ICH6 with DMI interconnect Firmware Hub FWH The GMCH is a centralized controller for the system bus the memory bus the PCI Express bus and the DMI interconnect The ICH6 is a centralized controller for the board s I O paths The FWH provides the nonvolatile storage of the BIOS For information about Refer to The Intel 910GL chipset http developer intel com Resources used by the chipset Chapter 2 1 6 1 Intel 910GL Graphics Controller The Intel GMA900 graphics controller features the following Integrated graphics controller 32 bpp Bits Per Pixel graphics engine 333 MHz core frequency 256 bit 2 D engine 32 bit 3 D engine Motion video acceleration Pixel Shader 2 0 4 pixel pipes DirectX 9 0 Hardware Acceleration Software Vertex Shader Up to 2048
41. ed life of three years When the computer is plugged in the standby current from the power supply extends the life of the battery The clock is accurate to 13 minutes year at 25 C with 3 3 VSB applied Qs NOTE If the battery and AC power fail custom defaults if previously saved will be loaded into CMOS RAM at power on 1 7 PCI Express Connector 22 The board provides one PCI Express x1 connector The x1 interface supports simultaneous transfer speeds up to 500 MBytes sec The PCI Express interface supports the PCI Conventional bus configuration mechanism so that the underlying PCI Express architecture is compatible with PCI Conventional compliant operating systems Additional features of the PCI Express interface includes the following e Support for the PCI Express enhanced configuration mechanism e Automatic discovery link training and initialization e Support for Active State Power Management ASPM e SMBus 2 0 support e Wake signal supporting wake events from ACPI S1 S3 S4 or S5 e Software compatible with the PCI Power Management Event PME mechanism defined in the PCI Power Management Specification Rev 1 1 Product Description 1 8 1 0 Controller The I O controller provides the following features e One serial port e One parallel port with Extended Capabilities Port ECP and Enhanced Parallel Port EPP support e Serial IRQ interface compatible with serialized IRQ support for PCI Conventional bus system
42. equirements International Table 34 lists the EMC regulations the Desktop Board D910GLDW complies with when correctly installed in a compatible host system Table 34 EMC Regulations Regulation FCC Class B ICES 003 Class B EN55022 1998 Class B EN55024 1998 AS NZS 3548 Class B CISPR 22 3 Edition Class B CISPR 24 1997 VCCI Class B Title Title 47 of the Code of Federal Regulations Parts 2 and 15 Subpart B Radio Frequency Devices USA Interference Causing Equipment Standard Digital Apparatus Canada Limits and methods of measurement of Radio Interference Characteristics of Information Technology Equipment European Union Information Technology Equipment Immunity Characteristics Limits and methods of measurement European Union Australian Communications Authority Standard for Electromagnetic Compatibility Australia and New Zealand Limits and methods of measurement of Radio Disturbance Characteristics of Information Technology Equipment International Information Technology Equipment Immunity Characteristics Limits and Methods of Measurements International Voluntary Control for Interference by Information Technology Equipment Japan 61 Intel Desktop Board D910GLDW Technical Product Specification 2 15 2 1 FCC Compliance Statement USA Product Type D910GLDW Desktop Board This device complies with Part 15 of the FCC Rules Operation is subject to the following
43. ery diskette is required Technical Reference 2 10 Mechanical Considerations 2 10 1 Form Factor The board is designed to fit into either a microATX or an ATX form factor chassis Figure 17 illustrates the mechanical form factor of the board Dimensions are given in inches millimeters The outer dimensions are 9 60 inches by 9 60 inches 243 84 millimeters by 243 84 millimeters Location of the I O connectors and mounting holes are in compliance with the ATX specification 1 800 45 72 6 500 la p 165 10 nn e LIL Seer 6 100 A 154 94 5 200 132 08 0 00 2 850 72 39 3 100 78 74 L 6 450 3 150 163 83 2 600 6 200 80 01 esou 157 48 OM17317 Figure 17 Board Dimensions 53 Intel Desktop Board D910GLDW Technical Product Specification 2 10 2 UO Shield The back panel I O shield for the board must meet specific dimension and material requirements Systems based on this board needs the back panel I O shield to pass certification testing Figure 18 shows the I O shield Dimensions are given in inches to a tolerance of 0 02 inches The figure also indicates the
44. es one IEEE 1394a port 51 Intel Desktop Board D910GLDW Technical Product Specification 2 9 Jumper Block A CAUTION 52 Do not move the jumper with the power on Always turn off the power and unplug the power cord from the computer before changing a jumper setting Otherwise the board could be damaged Figure 16 shows the location of the jumper block The 3 pin jumper block determines the BIOS Setup program s mode Table 28 describes the jumper settings for the three modes normal configure and recovery When the jumper is set to configure mode and the computer is powered up the BIOS compares the processor version and the microcode version in the BIOS and reports if the two match OM17316 Figure 16 Location of the Jumper Block Table 28 BIOS Setup Configuration Jumper Settings Function Mode Jumper Setting Jumper Setting Configuration Normal The BIOS uses current configuration information and 1 2 ia of passwords for booting Configure After the POST runs Setup runs automatically The 2 3 DI maintenance menu is displayed Recovery The BIOS attempts to recover the BIOS configuration A None recov
45. ess A parity error occurred in onboard memory at an unknown address NVRAM CMOS and passwords have been cleared The system should be powered down and the jumper removed CMOS is ignored and NVRAM is cleared User must enter Setup Error Messages and Beep Codes 4 2 Port 80h POST Codes During the POST the BIOS generates diagnostic progress codes POST codes to I O port 80h If the POST fails execution stops and the last POST code generated is left at port 80h This code is useful for determining the point where an error occurred Displaying the POST codes requires a PCI bus add in card often called a POST card The POST card can decode the port and display the contents on a medium such as a seven segment display lt a NOTE The POST card must be installed in PCI bus connector 1 The tables below offer descriptions of the POST codes generated by the BIOS Table 41 defines the uncompressed INIT code checkpoints Table 42 describes the boot block recovery code checkpoints and Table 43 lists the runtime code uncompressed in F000 shadow RAM Some codes are repeated in the tables because that code applies to more than one operation Table 41 Uncompressed INIT Code Checkpoints Code Description of POST Operation DO NMI is Disabled Onboard KBC RTC enabled if present Init code Checksum verification starting D1 Keyboard controller BAT test CPU ID saved and going to 4 GB flat mode D3 Do necessary chipset initialization sta
46. for menu screens Table 37 BIOS Setup Program Function Keys BIOS Setup Program Function Key Description lt lt gt OF lt gt gt Selects a different menu screen Moves the cursor left or right lt P gt or lt gt Selects an item Moves the cursor up or down lt Tab gt Selects a field Not implemented lt Enter gt Executes command or selects the submenu lt F9 gt Load the default configuration values for the current menu lt F10 gt Save the current values and exits the BIOS Setup program lt Esc gt Exits the menu 3 2 BIOS Flash Memory Organization The Firmware Hub FWH includes a 4 Mbit 512 KB symmetrical flash memory device 3 3 Resource Configuration 3 3 1 PCI Autoconfiguration The BIOS can automatically configure PCI devices PCI devices may be onboard or add in cards Autoconfiguration lets a user insert or remove PCI cards without having to configure the system When a user turns on the system after adding a PCI card the BIOS automatically configures interrupts the I O space and other system resources Any interrupts set to Available in Setup are considered to be available for use by the add in card 3 3 2 PCIIDE Support If you select Auto in the BIOS Setup program the BIOS automatically sets up the PCI IDE connector with independent I O channel support The IDE interface supports hard drives up to ATA 66 100 and recognizes any ATAPI compliant devices including CD ROM drives tape drives and Ultra DMA
47. g the test point error writes the error to I O port 80h attempts to initialize the video and writes the error in the upper left corner of the screen using both monochrome and color adapters If POST completes normally the BIOS issues one short beep before passing control to the operating system Table 47 Beep Codes Beep Description 1 CPU error 3 Memory error 6 System failure 7 System failure 8 Video error 80
48. ge 15 3 6 1 Language Support The BIOS Setup program and help messages are supported in US English Additional languages are available in the Integrator s Toolkit utility Check the Intel website for details 3 6 2 Custom Splash Screen During POST an Intel splash screen is displayed by default This splash screen can be augmented with a custom splash screen The Integrator s Toolkit that is available from Intel can be used to create a custom splash screen is NOTE If you add a custom splash screen it will share space with the Intel branded logo For information about Refer to The Intel World Wide Web site Section 1 3 page 15 68 Overview of BIOS Features 3 7 Boot Options In the BIOS Setup program the user can choose to boot from a diskette drive hard drives CD ROM or the network The default setting is for the diskette drive to be the first boot device the hard drive second and the ATAPI CD ROM third The fourth device is disabled 3 7 1 CD ROM Boot Booting from CD ROM is supported in compliance to the El Torito bootable CD ROM format specification Under the Boot menu in the BIOS Setup program ATAPI CD ROM is listed as a boot device Boot devices are defined in priority order Accordingly if there is not a bootable CD in the CD ROM drive the system will attempt to boot from the next defined drive 3 7 2 Network Boot The network can be selected as a boot device This selection allows booting from t
49. guage SUP DON E 68 3 6 2 CUSTOM Splash SOMA a 68 Bide BOO OPON ti if aes Re 69 3 7 1 CD MB OON ss ee 69 3 7 2 Network BOO d sen enee EEN lege 69 3 7 3 Booting Without Attached Devices cccccccceeeeeeeeeeseeeeeeeeeeeseseseeneeeeeeeeees 69 3 7 4 Changing the Default Boot Device During POST oooccccccinnccccccnonccccccnnacancncnnns 69 3 8 Fast Booting Systems with Intel Rapid BIOS Boot 70 3 8 1 Peripheral Selection and Configuration oooooccccnnnncccccnnnnocccccnnnnaanccnnnnrncnnnnnnnos 70 3 8 2 intel Rapid BIOS BOO dias 70 3 9 BIOS S c rity ER suis A 71 Contents 4 Error Messages and Beep Codes 4 1 BIOS Error Messages EE 73 4 amp 2 TR POST ee EE 75 4 3 Bus Initialization Checkpoints jose ts sccestedanset cess ccanetsdsacdevesevieoseegedetns tarde Wedsdtahad Weeee 79 44 EES 80 4 5 BIOS Beep COMES eege ao 80 Figures Ts Board Components EE 12 Si Block rem gege ENEE EENS 14 3 Memory Channel Configuration ENEE 17 4 Dual Channel Interleaved Mode Configuration with Two DiMMs 18 5 Single Channel Asymmetric Mode Configuration with One DIMM 18 6 Front Back Panel Audio Connector Options for High Definition Audio Subsystem 25 7 High Definition Audio Subsystem Block Diagram oooococcccnoniccccnnonaccccnnnnnccccncnanancnnnnnns 25 8 LAN Connector LED Locations aiii 26 SH Thermal Monitor cocina as 29 10 Location of the Standby Power Indicator LED oooonnoccccnnnnnccccnnoncccncnonancncnnnnanccn
50. h Dual colored Single colored 4 3 27 Power LED Power LED 2 Hard Drive 5 p N Activity LED 5 H gt 5 j r z A Ku Figure 13 Connection Diagram for Front Panel Connector OM17000 2 8 2 4 1 Hard Drive Activity LED Connector Yellow Pins 1 and 3 Yellow can be connected to an LED to provide a visual indicator that data is being read from or written to a hard drive Proper LED function requires one of the following e A Serial ATA hard drive connected to an onboard Serial ATA connector e An IDE hard drive connected to an onboard IDE connector 2 8 2 4 2 Reset Switch Connector Purple Pins 5 and 7 Purple can be connected to a momentary single pole single throw SPST type switch that is normally open When the switch is closed the board resets and runs the POST 2 8 2 4 3 Power Sleep LED Connector Green Pins 2 and 4 Green can be connected to a one or two color LED Table 26 shows the possible states for a one color LED Table 27 shows the possible states for a two color LED Table 26 States for a One Color Power LED LED State Description Off Power off sleeping Steady Green Running Table 27 States for a Two Color Power LED LED State Description Off Power off Steady Green Running Steady Yellow Sleeping 49 Intel Desktop Board D910GLDW Technical Product Specification lt Q NOTE The colors listed in Table 26 and Table 27 are suggested colors only Actual LED colors are prod
51. he onboard LAN or a network add in card with a remote boot ROM installed Pressing the lt F12 gt key during POST automatically forces booting from the LAN To use this key during POST the User Access Level in the BIOS Setup program s Security menu must be set to Full 3 7 3 Booting Without Attached Devices For use in embedded applications the BIOS has been designed so that after passing the POST the operating system loader is invoked even if the following devices are not present e Video adapter e Keyboard e Mouse 3 7 4 Changing the Default Boot Device During POST Pressing the lt F10 gt key during POST causes a boot device menu to be displayed This menu displays the list of available boot devices as set in the BIOS setup program s Boot Device Priority Submenu Table 38 lists the boot device menu options Table 38 Boot Device Menu Options Boot Device Menu Function Keys Description lt P gt or lt gt Selects a default boot device lt Enter gt Exits the menu saves changes and boots from the selected device lt Esc gt Exits the menu without saving changes 69 Intel Desktop Board D910GLDW Technical Product Specification 3 8 Fast Booting Systems with Intel Rapid BIOS Boot These factors affect system boot speed e Selecting and configuring peripherals properly e Using an optimized BIOS such as the Intel Rapid BIOS 3 8 1 Peripheral Selection and Configuration The following techniques help improve system
52. he time and or date values stored in CMOS are invalid Run Setup to set correct values Error during read write test of DMA controller Error occurred trying to access diskette drive controller Error occurred trying to access hard disk controller NVRAM is being checked to see if it is valid continued 73 Intel Desktop Board D910GLDW Technical Product Specification 74 Table 40 BIOS Error Messages continued Error Message Update OK Updated Failed Keyboard Error KB Interface Error Explanation NVRAM was invalid and has been updated NVRAM was invalid but was unable to be updated Error in the keyboard connection Make sure keyboard is connected properly Keyboard interface test failed Memory Size Decreased Memory Size Increased Memory Size Changed No Boot Device Available Off Board Parity Error On Board Parity Error Parity Error NVRAM CMOS PASSWORD cleared by Jumper lt CTRL_N gt Pressed Memory size has decreased since the last boot If no memory was removed then memory may be bad Memory size has increased since the last boot If no memory was added there may be a problem with the system Memory size has changed since the last boot If no memory was added or removed then memory may be bad System did not find a device to boot A parity error occurred on an off board card This error is followed by an address A parity error occurred in onboard memory This error is followed by an addr
53. he use of a USB peripheral that supports Wake from USB 1 12 2 7 Wake from PS 2 Devices PS 2 device activity wakes the computer from an ACPI S1 or S3 state 35 Intel Desktop Board D910GLDW Technical Product Specification 1 12 2 8 PME Signal Wake up Support When the PME signal on the PCI Conventional bus is asserted the computer wakes from an ACPI S1 S3 S4 or S5 state with Wake on PME enabled in BIOS 1 12 2 9 WAKE Signal Wake up Support When the WAKE signal on the PCI Express bus is asserted the computer wakes from an ACPI S1 S3 S4 or S5 state 1 12 2 10 5 V Standby Power Indicator LED The 5 V standby power indicator LED shows that power is still present even when the computer appears to be off Figure 10 shows the location of the standby power indicator LED A CAUTION If AC power has been switched off and the standby power indicator is still lit disconnect the power cord before installing or removing any devices connected to the board Failure to do so could damage the board and any attached devices OM17313 Figure 10 Location of the Standby Power Indicator LED 36 2 Technical Reference What This Chapter Con
54. ical Product Specification 2 6 Interrupts The interrupts can be routed through either the Programmable Interrupt Controller PIC or the Advanced Programmable Interrupt Controller APIC portion of the ICH6 component The PIC is supported in Windows 98 SE and Windows ME and uses the first 16 interrupts The APIC is supported in Windows 2000 and Windows XP and supports a total of 24 interrupts Table 13 Interrupts IRQ System Resource NMI I O channel check 0 Reserved interval timer 1 Reserved keyboard buffer full 2 Reserved cascade interrupt from slave PIC 3 COM2 Note 1 4 COM1 Note 1 5 LPT2 Plug and Play option User available 6 Diskette drive 7 LPT1 Note 1 8 Real time clock 9 User available 10 User available 11 User available 12 Onboard mouse port if present else user available 13 Reserved math coprocessor 14 Primary IDE Serial ATA if present else user available 15 Secondary IDE Serial ATA if present else user available 16 Note 2 User available through PIRQA 17 Note 2 User available through PIRQB 18 Note 2 User available through PIRQC 19 Note 2 User available through PIRQD 20 Note 2 User available through PIRQE 21 Note 2 User available through PIRQF 22 Note 2 User available through PIRQG 23 Note 2 User available through PIRQH Notes 1 Default but can be changed to another IRQ 2 Available in APIC mode only 40 Technical Reference 2 7 PCI Conventi
55. ices could cause damage to the computer the power cable and the external devices themselves This section describes the board s connectors The connectors can be divided into these groups e Back panel I O connectors e Component side I O connectors see page 44 2 8 1 Back Panel Connectors 42 Figure 11 shows the location of the back panel connectors The back panel connectors are color coded The figure legend Table 15 lists the colors used when applicable C K 0000000000000 SAS EH 000000000000 OM17314 Figure 11 Back Panel Connectors Table 15 lists the back panel connectors identified in Figure 11 lt j NOTE Technical Reference The back panel audio line out connector is designed to power headphones or amplified speakers only Poor audio quality occurs if passive non amplified speakers are connected to this output Table 15 Back Panel Connectors Shown in Figure 11 Item Callout from Figure 11 A Description PS 2 mouse port Green PS 2 keyboard port Purple Parallel port Burgundy Serial port A Teal VGA port Audio line in Retasking Port C Light blue Audio line out Retasking Port D Lime Green m xX ej I oO n mM Oo D Mic in Retasking Port B Pink IEEE 1394a optional USB ports two LAN optional USB ports two 43 Intel Desktop
56. it for all buses 79 Intel Desktop Board D910GLDW Technical Product Specification Table 46 describes the lower nibble of the high byte and indicates the bus on which the routines are being executed Table 46 Lower Nibble High Byte Functions Value Description Generic DIM Device Initialization Manager On board System devices ISA devices EISA devices ISA PnP devices PCI devices Oli N oO 4 4 Speaker A 47 Q inductive speaker is mounted on the board The speaker provides audible error code beep code information during POST For information about Refer to The location of the onboard speaker Figure 1 page 12 4 5 BIOS Beep Codes Whenever a recoverable error occurs during POST the BIOS displays an error message describing the problem see Table 47 The BIOS also issues a beep code one long tone followed by two short tones during POST if the video configuration fails a faulty video card or no card installed or if an external ROM module does not properly checksum to zero An external ROM module for example a video BIOS can also issue audible errors usually consisting of one long tone followed by a series of short tones For more information on the beep codes issued check the documentation for that external device There are several POST routines that issue a POST terminal error and shut down the system if they fail Before shutting down the system the terminal error handler issues a beep code signifyin
57. l through the hardware monitoring and fan control ASIC e Thermal and voltage monitoring e Chassis intrusion detection 1 11 1 Hardware Monitoring and Fan Control ASIC The features of the hardware monitoring and fan control ASIC include e Internal ambient temperature sensor e Two remote thermal diode sensors for direct monitoring of processor temperature and ambient temperature sensing e Power supply monitoring of five voltages 5 V 12 V 3 3 VSB 1 5 V and VCCP to detect levels above or below acceptable values e Thermally monitored closed loop fan control for all three fans that can adjust the fan speed or switch the fans on or off as needed e SMBus interface For information about Refer to The location of the fan connectors and sensors for thermal monitoring Figure 9 page 29 28 Product Description 1 11 2 Thermal Monitoring Figure 9 shows the location of the sensors and fan connectors Hem mmm DO D OM17312 Description Thermal diode located on processor die Remote ambient temperature sensor Ambient temperature sensor internal to hardware monitoring and fan control ASIC Processor fan Rear chassis fan Front chassis
58. m Keyboards and mice are not recognized during this period if Legacy USB support was set to Disabled in the BIOS Setup program After the operating system loads the USB drivers all legacy and non legacy USB devices are recognized by the operating system and Legacy USB support from the BIOS is no longer used To install an operating system that supports USB verify that Legacy USB support in the BIOS Setup program is set to Enabled and follow the operating system s installation instructions 3 6 BIOS Updates The BIOS can be updated using either of the following utilities which are available on the Intel World Wide Web site Intel Express BIOS Update utility which enables automated updating while in the Windows environment Using this utility the BIOS can be updated from a file on a hard disk a 1 44 MB diskette or a CD ROM or from the file location on the Web Intel Flash Memory Update Utility which requires creation of a boot diskette and manual rebooting of the system Using this utility the BIOS can be updated from a file on a 1 44 MB diskette from a legacy diskette drive or an LS 120 diskette drive or a CD ROM Both utilities verify that the updated BIOS matches the target system to prevent accidentally installing an incompatible BIOS lt j NOTE Review the instructions distributed with the upgrade utility before attempting a BIOS update For information about Refer to The Intel World Wide Web site Section 1 3 pa
59. n and Detectan lirio 30 1 12 Power Ate ET 30 A E 31 Dede Hardware Support di 33 Technical Reference A a Tee E 37 2 2 Memory Map tesi it Orale das deca nencaannceents tue 37 DB AINA EE 38 24 DMA Channels tia ee eee ce de oe ae haces er aces ea ia 39 Intel Desktop Board D910GLDW Technical Product Specification vi 2 5 PCI Configuration Space Mapas A cscs add ae ine 39 20 REDER O A0 2 7 PCI Conventional Interrupt Routing Map 41 28 SOMME CLOG sca tees ih ii 42 2 8 1 Back Panel Conmeciors aura 42 2 8 2 Component side COMME CtOIS ku 44 2 9 Jumper eier 52 2 10 Mechanical Considerations seu gugeeska rae geet tetra nnee E 53 2 10 11 Form Facti e ea ee e 53 E RE EE 54 2 11 Electrical Considera OS loo cta 55 211 1 DOLO darla ida 55 2 11 2 Add in Board CONSI ON Sastre tad 55 2 11 3 Fan Connector Current Capability AEN 55 2 11 4 Power Supply Considerations AEN 56 GEN Kann Ee E e 57 PREE A EE 59 P ee 60 2 15 Regulatory null e 61 22151 Sale E HE le EE 61 21927 EMG Regulations EE 61 2 15 3 European Union Declaration of Conformity Gtaiement eects 62 2 15 4 Product Ecology Statements a m 63 2 15 5 Product Certification Markings Board Level 64 Overview of BIOS Features UT MUO CUCU O EE 65 3 2 BIOS Flash Memory Organization aia daa 66 33 Res rc COMNGUrALON ata E 66 3 3 1 PE GEIER Ee 66 3 3 2 PENDE SUPPOR E 66 3 4 System Management BIOS MIO 67 BO Ee Een EE 67 306 BIOS Udala ts A eee eds coe eee hes 68 3 6 1 Lan
60. nnector is wired to a fan tachometer input of the hardware monitoring and fan control ASIC e All fan connectors support closed loop fan control that can adjust the fan speed or switch the fan on or off as needed e All fan connectors have a 12 V DC connection For information about Refer to The location of the fan connectors Figure 12 page 44 The location of the fan connectors and sensors for thermal monitoring Figure 9 page 29 The signal names of the processor fan connector Table 19 page 46 The signal names of the chassis fan connectors Table 18 page 46 1 12 2 3 LAN Wake Capabilities A CAUTION For LAN wake capabilities the 5 V standby line for the power supply must be capable of providing adequate 5 V standby current Failure to provide adequate standby current when implementing LAN wake capabilities can damage the power supply 34 Product Description LAN wake capabilities enable remote wake up of the computer through a network The LAN network adapter monitors network traffic at the Media Independent Interface Upon detecting a Magic Packet frame the LAN subsystem asserts a wake up signal that powers up the computer Depending on the LAN implementation the board supports LAN wake capabilities with ACPI in the following ways e The PCI Express WAKE signal e The PCI Conventional bus PME signal for PCI 2 2 compliant LAN designs e The onboard LAN subsystem 1 12 2 4 Instantly Available PC Technology A CAUTION For
61. nnnancccno 36 11 Back Panel e a ee 42 12 Component side Connectors ceros 44 13 Connection Diagram for Front Panel Connechor 49 14 Connection Diagram for Front Panel USB Connectors oooocccccnnnoccccccccncccnnananccnnnnanncnnns 50 15 Connection Diagram for IEEE 1394a Connector AAA 51 16 Location of the Jumper BOCK essa hen ces oul iuceaenedednidaee 52 17 Board DIMENSIONS a 53 18 I O Shield DIMENSIONS EE 54 19 Processor Heatsink AirfloW tintadas eege ita 57 20 Localized High Temperature ZOneS ccccceeeeeeeeecee teeter eeeeeeeeeeeeeeeeeesessseeeeeeaneeeeneees 58 Tables Le Feat re Summa eco 10 2 Manufacturing Option S seein aae a aeaa a a AAE ARE E ina 11 3 Board Components Shown in Figure 1 13 4 Supported Memory Configurations cooococnnnnccccnnnnoccccncnnncnccnnnnncn cn conan cnn cnn nccn anna 16 5 LAN Connector LED EE 26 6 Effects of Pressing the Power Switch uk 31 7 Power States and Targeted System Power 32 8 Wake up Devices and Events sinici et CHE eege 33 9 gt System Memory Map caia lod 37 10 MOM sei ds 38 1i DMA Chamels cion toaitada ia tai aa tad iia bra cu 39 12 PCI Configuration Space Map nit ti 39 de A A A a eae 40 14 PCI Interrupt Routing Map DEE 41 15 Back Panel Connectors Shown in Figure 171 43 16 Component side Connectors Shown in Figure 12 45 17 Front Panel Audio Connector ici id 46 vii Intel Desktop Board D910GLDW Technical Product Specification viii Fron
62. o one of these PIRQ signals Some PCI Conventional interrupt sources are electrically tied together on the board and therefore share the same interrupt Table 14 shows an example of how the PIRQ signals are routed Table 14 PCI Interrupt Routing Map ICH6 PIRQ Signal Name PCI Interrupt Source PIRQA PIRQB PIRQC PIRQD IEEE1394a controller INTA optional ES PCI bus connector 1 PCI bus connector 2 dal NOTE In PIC mode the ICH6 can connect each PIRO line internally to one of the IRQ signals 3 4 5 6 7 9 10 11 12 14 and 15 Typically a device that does not share a PIRO line will have a unique interrupt However in certain interrupt constrained situations it is possible for two or more of the PIRO lines to be connected to the same IRO signal Refer to Table 13 for the allocation of PIRO lines to IRQ signals in APIC mode PCI interrupt assignments to the USB ports Serial ATA ports and PCI Express ports are dynamic 41 Intel Desktop Board D910GLDW Technical Product Specification 2 8 Connectors A CAUTION Only the following connectors have overcurrent protection back panel USB front panel USB and PS 2 The other internal connectors are not overcurrent protected and should connect only to devices inside the computer s chassis such as fans and internal peripherals Do not use these connectors to power devices external to the computer s chassis A fault in the load presented by the external dev
63. ocessor controls data transfer e 8237 style DMA DMA offloads the processor supporting transfer rates of up to 16 MB sec e Ultra DMA DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 33 MB sec e ATA 66 DMA protocol on IDE bus supporting host and target throttling and transfer rates of up to 66 MB sec ATA 66 protocol is similar to Ultra DMA and is device driver compatible e ATA 100 DMA protocol on IDE bus allows host and target throttling The ICH6 s ATA 100 logic can achieve read transfer rates up to 100 MB sec and write transfer rates up to 88 MB sec Qs NOTE ATA 66 and ATA 100 are faster timings and require a specialized cable to reduce reflections noise and inductive coupling The Parallel ATA IDE interface also supports ATAPI devices such as CD ROM drives and ATA devices using the transfer modes The BIOS supports Logical Block Addressing LBA and Extended Cylinder Head Sector ECHS translation modes The drive reports the transfer rate and translation mode to the BIOS The board supports Laser Servo LS 120 diskette technology through the Parallel ATA IDE interfaces An LS 120 drive can be configured as a boot device by setting the BIOS Setup program s Boot menu to one of the following e ARMD FDD ATAPI removable media device floppy disk drive e ARMD HDD ATAPI removable media device hard disk drive For information about Refer to The location of the Parallel A
64. onal Interrupt Routing Map This section describes interrupt sharing and how the interrupt signals are connected between the PCI Conventional bus connectors and onboard PCI Conventional devices The PCI Conventional specification describes how interrupts can be shared between devices attached to the PCI Conventional bus In most cases the small amount of latency added by interrupt sharing does not affect the operation or throughput of the devices In some special cases where maximum performance is needed from a device a PCI Conventional device should not share an interrupt with other PCI Conventional devices Use the following information to avoid sharing an interrupt with a PCI Conventional add in card PCI Conventional devices are categorized as follows to specify their interrupt grouping e INTA By default all add in cards that require only one interrupt are in this category For almost all cards that require more than one interrupt the first interrupt on the card is also classified as INTA e INTB Generally the second interrupt on add in cards that require two or more interrupts is classified as INTB This is not an absolute requirement e INTC and INTD Generally a third interrupt on add in cards is classified as INTC and a fourth interrupt is classified as INTD The ICH6 has eight Programmable Interrupt Request PIRQ input signals All PCI Conventional interrupt sources either onboard or from a PCI Conventional add in card connect t
65. ore Coprocessor test Required initialization before Coprocessor is over Going to initialize the Coprocessor next Coprocessor initialized Going to do any initialization after Coprocessor test Initialization after Coprocessor test is complete Going to check extended keyboard keyboard ID and num lock Going to display any soft errors Soft error display complete Going to set keyboard typematic rate Keyboard typematic rate set To program memory wait states Going to enable parity NMI NMI and parity enabled Going to do any initialization required before giving control to optional ROM at E000 Initialization before E000 ROM control over E000 ROM to get control next Returned from E000 ROM control Going to do any initialization required after E000 optional ROM control Initialization after E000 optional ROM control is over Going to display the system configuration Put INT13 module runtime image to shadow Generate MP for multiprocessor support if present Put CGA INT10 module if present in Shadow continued Error Messages and Beep Codes Table 43 Runtime Code Uncompressed in F000 Shadow RAM continued Code AE B1 00 Description of POST Operation Uncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in shadow Going to copy any code to specific area Copying of code to specific area done Going to give control to INT 19 boot loader 4 3 Bus Initialization Checkpoints The sy
66. ores and reports the following SMBIOS information e BIOS data such as the BIOS revision level e Fixed system data such as peripherals serial numbers and asset tags e Resource data such as memory size cache size and processor speed e Dynamic data such as event detection and error logging Non Plug and Play operating systems such as Windows NT require an additional interface for obtaining the SMBIOS information The BIOS supports an SMBIOS table interface for such Operating systems Using this support an SMBIOS service level application running on a non Plug and Play operating system can obtain the SMBIOS information 3 5 Legacy USB Support Legacy USB support enables USB devices to be used even when the operating systems USB drivers are not yet available Legacy USB support is used to access the BIOS Setup program and to install an operating system that supports USB By default Legacy USB support is set to Enabled Legacy USB support operates as follows 1 When you apply power to the computer legacy support is disabled 2 POST begins 3 Legacy USB support is enabled by the BIOS allowing you to use a USB keyboard to enter and configure the BIOS Setup program and the maintenance menu 4 POST completes 67 Intel Desktop Board D910GLDW Technical Product Specification The operating system loads While the operating system is loading USB keyboards and mice are recognized and may be used to configure the operating syste
67. ort These calculations are not based on specific processor values or memory configurations but are based on the minimum and maximum current draw possible from the board s power delivery subsystems to the processor memory and USB ports Use the datasheets for add in cards such as PCI to determine the overall system power requirements The selection of a power supply at the system level is dependent on the system s usage model and not necessarily tied to a particular processor speed Table 29 DC Loading Characteristics DC Current at DC Power 5 V 12 V 12 V 2 11 2 Add in Board Considerations The board is designed to provide 2 A average of 5 V current for each add in board The total 5 V current draw for a fully loaded board all three expansion slots filled must not exceed 6 A Mode Minimum loading Maximum loading 1 40A 2 11 3 Fan Connector Current Capability Jh CAUTION The processor fan must be connected to the processor fan connector not to a chassis fan connector Connecting the processor fan to a chassis fan connector may result in onboard component damage that will halt fan operation Table 30 lists the current capability of the fan connectors Table 30 Fan Connector Current Capability Maximum Available Current 1000 mA 600 mA 600 mA Fan Connector Processor fan Front chassis fan Rear chassis fan 55 Intel Desktop Board D910GLDW Technical Product Specification 2 11 4 Powe
68. ory size mismatch with CMOS Memory size check done To display soft error and check for password or bypass setup Password checked About to do programming before setup Programming before setup complete To uncompress SETUP code and execute CMOS setup Returned from CMOS setup program and screen is cleared About to do programming after setup Programming after setup complete Going to display power on screen message First screen message displayed lt WAIT gt message displayed PS 2 Mouse check and extended BIOS data area allocation to be done Setup options programming after CMOS setup about to start Going for hard disk controller reset Hard disk controller reset done Floppy setup to be done next Floppy setup complete Hard disk setup to be done next Init of different buses optional ROMs from C800 to start See Section 4 3 for details of different buses Going to do any init before C800 optional ROM control Any init before C800 optional ROM control is over Optional ROM check and control will be done next Optional ROM control is done About to give control to do any required processing after optional ROM returns control and enable external cache Any initialization required after optional ROM test over Going to setup timer data area and printer base address Return after setting timer and printer base address Going to set the RS 232 base address Returned after RS 232 base address Going to do any initialization bef
69. ound at 0 0 45 Data initialized Going to check for memory wrap around at 0 0 and finding the total system memory size 46 Memory wrap around test done Memory size calculation over About to go for writing patterns to test memory 47 Pattern to be tested written in extended memory Going to write patterns in base 640k memory 48 Patterns written in base memory Going to find out amount of memory below 1M memory 49 Amount of memory below 1M found and verified Going to find out amount of memory above 1M memory 4B Amount of memory above 1M found and verified Check for soft reset and going to clear memory below 1M for soft reset If power on go to check point 4Eh 4C Memory below 1M cleared SOFT RESET Going to clear memory above 1M 4D Memory above 1M cleared SOFT RESET Going to save the memory size Go to check point 52h 4E Memory test started NOT SOFT RESET About to display the first 64k memory size 4F Memory size display started This will be updated during memory test Going for sequential and random memory test 50 Memory testing initialization below 1M complete Going to adjust displayed memory size for relocation shadow 51 Memory size display adjusted due to relocation shadow Memory test above 1M to follow 52 Memory testing initialization above 1M complete Going to save memory size information 53 Memory size information is saved CPU registers are saved Going to enter in real mode 54 Shutdown successful
70. position of each cutout Additional design considerations for I O shields relative to chassis requirements are described in the ATX specification da NOTE The I O shield drawing in this document is for reference only An I O shield compliant with the ATX chassis specification 2 03 is available from Intel 162 3 REF 6 390 nae D U 0 063 0 005 E S mg eg _ a O d a a a E a aa 20 0 254 TYP T 0 787 0 10 1 55 REF 159 2 0 12 0 061 6 268 0 005 22 45 0 884 8x R 0 5 MIN 7 012 AT EROS 0 276 1 00 0 039 A A ooo Le I d LI 0 00 11 811 C 11 81 i 0 465 ee ME 144 1200 A 0 567 0 472 e ea Yo Pictorial View OM17166 Figure 18 I O Shield Dimensions 54 Technical Reference 2 11 Electrical Considerations 2 11 1 DC Loading Table 29 lists the DC loading characteristics of the board This data is based on a DC analysis of all active components within the board that impact its power delivery subsystems The analysis does not include PCI add in cards Minimum values assume a light load placed on the board that is similar to an environment with no applications running and no USB current draw Maximum values assume a load placed on the board that is similar to a heavy gaming environment with a 500 mA current draw per USB p
71. r Supply Considerations A 56 CAUTION The 5 V standby line for the power supply must be capable of providing adequate 5 V standby current Failure to do so can damage the power supply The total amount of standby current required depends on the wake devices supported and manufacturing options System integrators should refer to the power usage values listed in Table 29 when selecting a power supply for use with the board Additional power required will depend on configurations chosen by the integrator The power supply must comply with the following recommendations found in the indicated sections of the ATX form factor specification The potential relation between 3 3 VDC and 5 VDC power rails Section 4 2 The current capability of the 5 VSB line Section 4 2 1 2 All timing parameters Section 4 2 1 3 All voltage tolerances Section 4 2 2 Technical Reference 2 12 Thermal Considerations A CAUTION A chassis with a maximum internal ambient temperature of 38 C at the processor fan inlet is a requirement Use a processor heatsink that provides omni directional airflow as shown in Figure 19 to maintain required airflow across the processor voltage regulator area il OM16996 Figure 19 Processor Heatsink Airflow A CAUTION Failure to ensure appropriate airflow may result in reduced performance of both the processor and or voltage regulator or in some instances damage to the board For a list of chassis
72. roduct Specification lt j NOTE To be fully compliant with all applicable DDR SDRAM memory specifications the board should be populated with DIMMs that support the Serial Presence Detect SPD data structure This allows the BIOS to read the SPD data and program the chipset to accurately configure memory settings for optimum performance If non SPD memory is installed the BIOS will attempt to correctly configure the memory settings but performance and reliability may be impacted or the DIMMs may not function under the determined frequency Table 4 lists the supported DIMM configurations Table 4 DIMM Capacity 128 MB 256 MB 256 MB 512 MB 512 MB 512 MB 1024 MB 1024 MB 2048 MB Supported Memory Configurations extort ety SDRAM Organization Number of SDRAM Configuration Boniy Front side Back side Devices E EEE ss bizmi s2Mx16empy Ds aeni S2Mx802Mxb 16 Ss ew Lousen ss em TACA E pe mum ugoen 76 Site anes Je 1 Gbit 128 M x 8 128 M x 8 16 Note In the second column DS refers to double sided memory modules containing two rows of SDRAM and SS refers to single sided memory modules containing one row of SDRAM Product Description 1 5 1 Memory Configurations The Intel 82910GL GMCH supports two types of memory organization e Dual channel Interleaved mode This mode offers the highest throughput for real world applications Dual channel mode is enabled when the installed memory c
73. rt memory refresh and do memory sizing D4 Verify base memory D5 Init code to be copied to segment 0 and control to be transferred to segment 0 D6 Control is in segment 0 To check recovery mode and verify main BIOS checksum If either it is recovery mode or main BIOS checksum is bad go to check point EO for recovery else go to check point D7 for giving control to main BIOS D7 Find Main BIOS module in ROM image D8 Uncompress the main BIOS module D9 Copy main BIOS image to F000 shadow RAM and give control to main BIOS in F000 shadow RAM Table 42 Boot Block Recovery Code Checkpoints Code Description of POST Operation EO Onboard Floppy Controller if any is initialized Compressed recovery code is uncompressed in F000 0000 in Shadow RAM and give control to recovery code in F000 Shadow RAM Initialize interrupt vector tables initialize system timer initialize DMA controller and interrupt controller E8 Initialize extra Intel Recovery Module E9 Initialize floppy drive EA Try to boot from floppy If reading of boot sector is successful give control to boot sector code EB Booting from floppy failed look for ATAPI LS 120 Zip devices EC Try to boot from ATAPI If reading of boot sector is successful give control to boot sector code EF Booting from floppy and ATAPI device failed Give two beeps Retry the booting procedure again go to check point E9 75 Intel Desktop Board D910GLDW Technical Product Specification
74. s e PS 2 style mouse and keyboard interfaces e Interface for one 1 44 MB or 2 88 MB diskette drive e Intelligent power management including a programmable wake up event interface e PCI Conventional bus power management support The BIOS Setup program provides configuration options for the I O controller 1 8 1 Serial Port The board supports one serial port connector Serial port A located on the back panel The serial port supports data transfers at speeds up to 115 2 kbits sec with BIOS support For information about Refer to The location of the serial port A connector Figure 11 page 42 1 8 2 Parallel Port The 25 pin D Sub parallel port connector is located on the back panel Use the BIOS Setup program to set the parallel port mode For information about Refer to The location of the parallel port connector Figure 11 page 42 1 8 3 Diskette Drive Controller The I O controller supports one diskette drive Use the BIOS Setup program to configure the diskette drive interface For information about Refer to The location of the diskette drive connector Figure 12 page 44 1 8 4 Keyboard and Mouse Interface PS 2 keyboard and mouse connectors are located on the back panel da NOTE The keyboard is supported in the bottom PS 2 connector and the mouse is supported in the top PS 2 connector Power to the computer should be turned off before a keyboard or mouse is connected or disconnected For information
75. s occurring Yellow Off 10 Mbits sec data rate is selected 100 Mbits sec data rate is selected Product Description 1 10 2 Alert Standard Format ASF Support The boards provide the following ASF support for PCI Express x1 bus add in LAN cards and PCI Conventional bus add in LAN cards installed in PCI Conventional bus slot 2 e Monitoring of system firmware progress events including BIOS present Primary processor initialization Memory initialization Video initialization PCI resource configuration Hard disk initialization User authentication Starting operating system boot process e Monitoring of system firmware error events including Memory missing Memory failure No video device Keyboard failure Hard disk failure No boot media e Boot options to boot from different types of boot devices e Reset shutdown power cycle and power up options 1 10 3 LAN Subsystem Software LAN software and drivers are available from Intel s World Wide Web site For information about Refer to Obtaining LAN software and drivers Section 1 3 page 15 27 Intel Desktop Board D910GLDW Technical Product Specification 1 11 Hardware Management Subsystem The hardware management features enable the board to be compatible with the Wired for Management WfM specification The Desktop Board has several hardware management features including the following e Fan monitoring and contro
76. seen Monitors and hard disk drives with minimum initialization times can also contribute to a boot time that might be so fast that necessary logo screens and POST messages cannot be seen This boot time may be so fast that some drives might be not be initialized at all If this condition should occur it is possible to introduce a programmable delay ranging from three to 30 seconds using the Hard Disk Pre Delay feature of the Advanced Menu in the Drive Configuration Submenu of the BIOS Setup program Overview of BIOS Features 3 9 BIOS Security Features The BIOS includes security features that restrict access to the BIOS Setup program and who can boot the computer A supervisor password and a user password can be set for the BIOS Setup program and for booting the computer with the following restrictions e The supervisor password gives unrestricted access to view and change all the Setup options in the BIOS Setup program This is the supervisor mode e The user password gives restricted access to view and change Setup options in the BIOS Setup program This is the user mode e If only the supervisor password is set pressing the lt Enter gt key at the password prompt of the BIOS Setup program allows the user restricted access to Setup e If both the supervisor and user passwords are set users can enter either the supervisor password or the user password to access Setup Users have access to Setup respective to which password is entered
77. stem BIOS gives control to the different buses at several checkpoints to do various tasks Table 44 describes the bus initialization checkpoints Table 44 Bus Initialization Checkpoints Checkpoint Description 2A 38 39 95 Different buses init system static and output devices to start if present Different buses init input IPL and general devices to start if present Display different buses initialization error messages Init of different buses optional ROMs from C800 to start While control is inside the different bus routines additional checkpoints are output to port 80h as WORD to identify the routines under execution In these WORD checkpoints the low byte of the checkpoint is the system BIOS checkpoint from which the control is passed to the different bus routines The high byte of the checkpoint is the indication of which routine is being executed in the different buses Table 45 describes the upper nibble of the high byte and indicates the function that is being executed Table 45 Upper Nibble High Byte Functions Value N Oli or A o P CH Description func 0 disable all devices on the bus concerned func 1 static devices init on the bus concerned func 2 output device init on the bus concerned func 3 input device init on the bus concerned func 4 IPL device init on the bus concerned func 5 general device init on the bus concerned func 6 error reporting for the bus concerned func 7 add on ROM in
78. sters Notes 1 Default but can be changed to another address range 2 Dword access only 3 Byte access only lt Q NOTE Some additional I O addresses are not available due to ICH6 address aliassing The ICH6 data sheet provides more information on address aliassing For information about Refer to Obtaining the ICH6 data sheet Section 1 3 page 15 38 Technical Reference 2 4 DMA Channels Table 11 DMA Channels DMA Channel Number Data Width System Resource o EE 1 8 or 16 bits Parallel port 2 Diskette drive 3 Parallel port for ECP or EPP 4 DMA controller 7 16 bits Open 2 5 PCI Configuration Space Map Table 12 PCI Configuration Space Map Bus Device Function Number hex Number hex Number hex Description 00 oo ee Memory controller of Intel 82910GL component 00 o2 fo Integrated graphics controller 00 Integrated graphics controller 00 Intel High Definition Audio Controller 1C C 00 ae 00 PCI Express port 1 PCI Express x1 bus connector 1 00 PCI Express port 2 03 PCI Express port 4 not used 00 Oe USB UHCI controller 1 00 USB UHCI controller 2 1D 02 USB UHCI controller 3 1D 03 USB UHCI controller 4 00 1D EHCI controller 1E PCI bridge o o PCI controller 1F oO 00 Parallel ATA IDE controller 1F 03 SMBus controller o o Note PCI Conventional bus connector 1 Note Bus number is dynamic and can change based on add in cards used 39 Intel Desktop Board D910GLDW Techn
79. t Chassis Fan and Rear Chassis Fan Connechors 46 Processor Fan COMO CON aid deta 46 Chassis Intrusion EHS eieengaugtouegedegedE ed Serge EA geed neteet 46 Serial ATA COME Sii eege Se 46 Main Power e le 47 ATX12V Power Conpertor oe ZeirdeleeCA RENE GEESS 47 Auxiliary Front Panel Power Sleep LED Connector occoccccococccccononcccnonancnnnonancccnnnnnncnnnos 48 Front Panel Connector miocarditis 48 States for a One Color Power LEI 49 States Tor a Two Color Power D RE 49 BIOS Setup Configuration Jumper Getttngs AE 52 DC Loading er Eet 55 Erres EES 55 Thermal Considerations for Components cccoooocccccconoccccconononcncnnnnncnncnnnnncnn nana ncccnnnnnaccn 59 Environmental Specifications uge cicatrices 60 MER E 61 Lee IEN 61 Product Certification Markings a cc csicenecneieceetedandasecnes ede sbteesnceenaudentnatenteccegavessdeensennense 64 BIOS Setup Program ET taaesitieataadeenneiaa otto eaten ge 66 BIOS Setup Program Function Me 66 Boot Device Menu OPUONS ck tyes wes o ai 69 Supervisor and User Password Functions EEN 71 BIOS Error Messages ss 73 Uncompressed INIT Code Checkpooimts cnn cnonnn ana ncnnnnes 75 Boot Block Recovery Code Checkpoint oooccoocooccccnonoccccononncnccnnnnncnccnonannncnnnnnnn aca ncnnnnos 15 Runtime Code Uncompressed in F000 Shadow DAME 76 Bus Initialization Checkpoints a eiii ares 79 Upper Nibble High Byte Functions ccccc csszcesed ot cece sesaasuasoetanenuevecsgy ude sdeeedenenueiesstedaetaeatee 79 Lower Nibble
80. tains Zt e ee et Te EE 37 2 2 Memory MADD sario sidad AE Ee 37 2 3 Fixed re E EE 38 24 HMA GA AMS ci 39 2 5 PCI Configuration Space Map 39 Sr EES eege Ee eegener A0 2 7 PCI Conventional Interrupt Routing Map ANEN 41 28 GONMOCIOIS cccvssccesiecciteststacte Aa theta stasaatecte aaa a secsteassteadotsgs tay 42 2 9 UMPC leie 52 2 10 Mechanical Considerations ccccccccceccseseeceeceeeececeeeseuceeeeeeeeeeaeeeeeeeeeeeeaeaeaeseeeeeeseeea 53 2 11 Electrical Considerations canon nan cnnno nan cnn nn nana nana naninns 55 2 12 Thermal Considerations conc nnnn naar nn anna caca nanans 57 E E er EEN 59 2 14 NN 60 2 15 Regulatory GOmpllanee ies lt scecsascesceeetvet feds nia sra 61 2 1 Introduction Sections 2 2 2 6 contain several standalone tables Table 9 describes the system memory map Table 10 shows the I O map Table 11 lists the DMA channels Table 12 defines the PCI Conventional bus configuration space map and Table 13 describes the interrupts The remaining sections in this chapter are introduced by text found with their respective section headings 2 2 Memory Map Table 9 lists the system memory map Table 9 System Memory Map Address Range decimal Address Range hex Size Description 1024 K 4194304 K 100000 FFFFFFFF 4095 MB Extended memory 960 K 1024 K Runtime BIOS 896 K 960 K Reserved 800 K 896 K C8000 DFFFF 96 KB Potential available high DOS memory open to the PCI Conventional b
81. ted to PCI Conventional bus connector 2 This enables PCI Conventional bus add in boards with SMBus support to access sensor data on the board The specific SMBus signals are as follows The SMBus clock line is connected to pin A40 The SMBus data line is connected to pin A41 2 8 2 3 Auxiliary Front Panel Power Sleep LED Connector Pins 1 and 3 of this connector duplicate the signals on pins 2 and 4 of the front panel connector Table 24 Auxiliary Front Panel Power Sleep LED Connector Pin In Out Description 2 8 2 4 Front Panel Connector This section describes the functions of the front panel connector Table 25 lists the signal names of the front panel connector Figure 13 is a connection diagram for the front panel connector 48 Table 25 Front Panel Connector Pin Signal In Qut Description Hard Drive Activity LED Yellow Hard disk LED pull up 750 Q to 5 V E Front panel green LED Front panel yellow LED Pin Signal In Out Description Power LED Green N Front panel green LED HDR_BLNK_ Out GRN 3 Hard disk active LED 4 HDR_BLNK_ Out Front panel yellow YEL LED Reset Switch On Off Switch Purple Red 5 Ground Ground 6 FPBUT_IN In Power switch 7 FP_RESET In Reset switch 8 Ground Ground Power Not Connected 9 5 V Power 10 N C Not connected Technical Reference Nc 9 45 VDC Power E 2 Reset Switch e O E Switc
82. that have been tested with Intel desktop boards please refer to the following website http developer intel com design motherbd cooling htm All responsibility for determining the adequacy of any thermal or system design remains solely with the reader Intel makes no warranties or representations that merely following the instructions presented in this document will result in a system with adequate thermal performance A CAUTION Ensure that the ambient temperature does not exceed the board s maximum operating temperature Failure to do so could cause components to exceed their maximum case temperature and malfunction For information about the maximum operating temperature see the environmental specifications in Section 2 14 57 Intel Desktop Board D910GLDW Technical Product Specification A CAUTION 58 Ensure that proper airflow is maintained in the processor voltage regulator circuit Failure to do so may result in damage to the voltage regulator circuit The processor voltage regulator area item A in Figure 20 can reach a temperature of up to 85 C in an open chassis Figure 20 shows the locations of the localized high temperature zones
83. ting system to power off the computer Support for multiple wake up events see Table 8 on page 33 Support for a front panel power and sleep mode switch Table 6 lists the system states based on how long the power switch is pressed depending on how ACPI is configured with an ACPI aware operating system Table 6 Effects of Pressing the Power Switch and the power switch is If the system is in this state pressed for the system enters this state Off Less than four seconds Power on ACPI G2 G5 Soft off ACPI GO working state On Less than four seconds Soft off Standby ACPI GO working state ACPI G1 sleeping state On More than four seconds Fail safe power off ACPI GO working state ACPI G2 G5 Soft off Sleep Less than four seconds Wake up ACPI G1 sleeping state ACPI GO working state Sleep More than four seconds Power off ACPI G1 sleeping state ACPI G2 G5 Soft off 31 Intel Desktop Board D910GLDW Technical Product Specification 1 12 1 1 32 System States and Power States Under ACPI the operating system directs all system and device power state transitions The operating system puts devices in and out of low power states based on user preferences and knowledge of how devices are being used by applications Devices that are not being used can be turned off The operating system uses information from applications and user settings to put the system as a whole into a
84. two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna e Increase the separation between the equipment and the receiver e Connect the equipment to a different electrical branch circuit from that to which the receiver is connected e Consult the dealer or an experienced radio TV technician for help Any changes or modifications to the equipment not expressly approved by Intel Corporation could void the user s authority to operate the equipment 2 15 2 2 Canadian Compliance Statement This Class B
85. uct or customer specific 2 8 2 4 4 Power Switch Connector Red Pins 6 and 8 Red can be connected to a front panel momentary contact power switch The switch must pull the SW_ON pin to ground for at least 50 ms to signal the power supply to switch on or off The time requirement is due to internal debounce circuitry on the board At least two seconds must pass before the power supply will recognize another on off signal 2 8 2 5 Front Panel USB Connectors Figure 14 is a connection diagram for the front panel USB connectors SK INTEGRATOR S NOTES 50 The 5 V DC power on the USB connector is fused Pins 1 3 5 and 7 comprise one USB port Pins 2 4 6 and 8 comprise one USB port Use only a front panel USB connector that conforms to the USB 2 0 specification for high speed USB devices eevee i eee 2 POON e Port p 1G O o Fon Ground Ground Key no pin No Connect OM15963 Figure 14 Connection Diagram for Front Panel USB Connectors Technical Reference 2 8 2 6 Front Panel IEEE 1394a Connectors Optional Figure 15 is a connection diagram for the optional IEEE 1394a connector TPA Ground TPB 12 VDC Key no pin Al HOJA MOZO O TPA Ground TPB 12 VDC Ground OM16107 Figure 15 Connection Diagram for IEEE 1394a Connector SK INTEGRATOR S NOTES e The 12 V DC power on the IEEE 1394a connectors is fused e The IEEE 1394a connector provid
86. us Dependent on video adapter used 640 K 800 K A0000 C7FFF 160 KB Video memory and BIOS 639 K 640 K 9FCOO 9FFFF 1 KB Extended BIOS data movable by memory manager software 512 K 639 K 80000 9FBFF 127 KB Extended conventional memory OK 512K 00000 7FFFF 512 KB Conventional memory 37 Intel Desktop Board D910GLDW Technical Product Specification 2 3 Fixed I O Map Table 10 I O Map Address hex Sie Description 0000 OOFF 256 bytes Used by the Desktop Board D910GLDW Refer to the ICH6 data sheet for dynamic addressing information 0170 0177 Secondary Parallel ATA IDE channel command block 01FO 01F7 Primary Parallel ATA IDE channel command block 0228 022F Note 1 8 bytes LPT3 0278 027F Note 1 8 bytes LPT2 02E8 02EF Note 1 COM4 02F8 02FF Note 1 8 bytes COM2 0374 0377 Secondary Parallel ATA IDE channel control block 0377 bits 6 0 Secondary IDE channel status port 0378 037F 8 bytes LPT1 03E8 O3EF 8 bytes COM3 O3FO 03F5 Diskette channel 03F4 03F7 Primary Parallel ATA IDE channel control block 03F8 03FF COM1 04D0 04D1 Edge level triggered PIC LPTn 400 ECP port LPTn base address 400h OCF8 OCFB Note 2 PCI Conventional bus configuration address register OCF9 Note 3 Reset control register OCFC OCFF PCI Conventional bus configuration data register FFAO FFA7 Primary Parallel ATA IDE bus master registers FFA8 FFAF Secondary Parallel ATA IDE bus master regi
87. uto configuration utility and Plug and Play support The BIOS displays a message during POST identifying the type of BIOS and a revision code The initial production BIOSs are identified as WB91X10J 86A When the BIOS Setup configuration jumper is set to configure mode and the computer is powered up the BIOS compares the CPU version and the microcode version in the BIOS and reports if the two match The BIOS Setup program can be used to view and change the BIOS settings for the computer The BIOS Setup program is accessed by pressing the lt F2 gt key after the Power On Self Test POST memory test begins and before the operating system boot begins The menu bar is shown below Maintenance Main Advanced Security Power Boot Exit da NOTE The maintenance menu is displayed only when the Desktop Board is in configure mode Section 2 9 on page 52 shows how to put the Desktop Board in configure mode 65 Intel Desktop Board D910GLDW Technical Product Specification Table 36 lists the BIOS Setup program menu features Table 36 BIOS Setup Program Menu Bar Clears Displays Configures Sets Configures Selects boot Saves or passwords and processor advanced passwords power options discards displays and memory features and security management changes to processor configuration available features features and Setup information through the power supply program chipset controls options Table 37 lists the function keys available

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