Transcend 256MB SDRAM 144Pin SO-DIMM PC100 Unbuffer Non-ECC Memory
Contents
1. UII pe Ee C OR Read amp Auto Precharge Disable Column Address Auto Precharge Enable Write amp Auto Precharge Disable N Column Address Auto Precharge Enable ACA Burst Stop x X ee Precharae Bank Selection X V Both Banks Xx Clock Suspend or Active Power Down Column Address aay Ao A9 L Address X L Precharge Power Down Mode V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatic precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BAt1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BAt1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 is ignored and all banks are selected 5 During burst read or write with auto precharge new read wr2. CAS ANE 16Mx8 SDRAM SCL A0 A11 BAO 1 DQO 7 RAS CAS 16Mx8 SDRAM A0 A11 BAO 1 DQO 7 RAS ICAS 16Mx8 SDRAM 16Mx8 SDRAM This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc TS32MSS64V8L2 ABSOLUTE MAXIMUM RATINGS 144PIN PC100 Unbuffered SO DIMM 256MB With 16M X 8 CL2 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 C Power dissipation PD 16 W Short circuit current IOS 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Recommended operating conditions Voltage referenced to Vss 0V TA 0
3. 70 Ohm OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter RAS to CAS delay Row precharge time Row active time Row cycle time ast data in to new col address dela ast data in to row precharge ast data in to burst stop Col address to col address delay tccD min Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8L2 256MB With 16M X 8 CL2 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8L2 256MB With 16M X 8 CL2 SIMPLIFIED TRUTH TABLE ares exen es ms voe me uam ve Te
4. B With 16M X 8 CL2 Pin Identification Dimensions Side Millimeters Inches A 67 60 0 200 2 661 0 008 B 32 80 1 291 C 23 20 0 913 D 4 60 0 181 E 3 30 0 130 F 2 50 0 098 G 4 00 0 157 H 6 00 0 236 20 00 0 787 J 31 75 0 200 1 250 0 008 K 1 00 0 100 0 039 0 004 Transcend information Inc Symbol Function AO A11 Address inputs BAO BA1 Select Bank DQ0 DQ63 Data inputs outputs CLKO CLK1 Clock Input CKEO CKE1 Clock Enable Input CSO CS1 Chip Select Input RAS Row address strobe ICAS Column address strobe ANE Write Enable DQMO 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data I O SCL Serial Clock NC No Connection 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8L2 256MB With 16M X 8 CL2 Pinouts Pin i Pin i Pin Pin Pin Name No No Name No Name Please refer Block Diagram Transcend information Inc 3 TS32MSS64V8L2 144PIN PC100 Unbuffered SO DIMM 256MB With 16M X 8 CL2 Block Diagram AO A11 BAO BA1 DQ0 DQ63 RAS ICAS ANE CSO CKEO CLKO f A0 A11 BA0 1 DQO 7 RAS CAS 16Mx8 SDRAM CS CKI 16Mx8 SDRAM A0 A11 BA0 1 DQO 7 RAS CAS ANE ICS CKE CLK 16Mx8 SDRAM SDA A0 A11 BA0 1 DQO 7 RAS ICAS ANE ICS CKE CLK 16Mx8 SDRAM 16Mx8 SDRAM A0 A11 BA0 1 DQO 7 RAS ICAS 16Mx8 SDRAM 16Mx8 SDRAM A0 A11 BA0 1 DQO 7 RAS
5. Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec R W Burst OE 23 SDRAM Cycle Time ow highest CL 10ns 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 20ns 14 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 50ns 32 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 2ns 20 33 Command Address Hold Time 1ns 10 34 Data Signal Setup Time 2ns 20 35 Data Signal Hold Time 1ns 10 36 61 Superset Information 00 62 SPD Data Revision Code Intel SPD SPEC V1 2 12 63 Checksum for Bytes 0 62 17 17 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 33 32 4D 53 73 90 Manufacturers Part Number TS32MSS64V8L2 53 36 34 56 38 4C 32 20 20 20 20 20 91 92 Revision Code 0 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable Transcend information Inc 10 TS32MSS64V8L2 144PIN PC100 U
6. TS32MSS64V8L2 Description The TS32MSS64V8L2 is a 32M bit x 64 Synchronous Dynamic high density memory module The TS32MSS64V8L2 consists of 16 pcs of CMOS 16Mx8bits Synchronous DRAMs in 54pins sTSOP packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS32MSS64V8L2 is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC100 CL2 e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Transcend information Inc 144PIN PC100 Unbuffered SO DIMM 256MB With 16M X 8 CL2 Placement oc l LL LL E eua IL fr ik gt x pe lt s gt PCB 09 1100 TS32MSS64V8L2 144PIN PC100 Unbuffered SO DIMM 256M
7. ite command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 TS32MSS64V8L2 Serial Presence Detect Specification 144PIN PC100 Unbuffered SO DIMM 256MB With 16M X 8 CL2 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A11 0C 4 of Column Addresses on this Assembly A0 A9 5 of Module Banks on this Assembly 2 banks 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X8 08 14
8. nbuffered SO DIMM 256MB With 16M X 8 CL2 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 amp 3 Clock 0 1 C6 128 255 Unused Storage Locations Open FF Transcend information Inc 11
9. tandby Current lcc P CKEs Viu max 51908 power down mode lcczPS amp CLKxViL max tcc lt Icc2N CKE SViH min CS ViH min tcc 15ns at Precharge Standby Current Input signals are changed one time during 30ns mA in non power down mode ccoNS CKE ViH min CLK lt ViL max tcc lt 112 Input signals are stable Active Standby Current lccsP lt por tons 80 mA in power down mode lccaPS CKE amp CLK lt ViL max tcc ICC3N CKE ViH min CS2ViH min tcc 10ns Active Standby Current 4 Input signals are changed one time during 30ns in non power down mode SORS Bani ACIVE lec3NS o KE Vinmin CLK lt ViL max Input signals are stable Operating Current Icc4 Burst Mode Refresh current Icc5 tRC 2 tRC min Self Refresh Current loce 0 2V R WE Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend information Inc 6 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8L2 256MB With 16M X 8 CL2 AC OPERATING TEST CONDITIONS vo 3 3V 0 3V TA 0 to 70 C Parameter nit AC Input levels VIH VIL 2 4 0 4 tr tf 1 1 See Fig 2 1200 Ohm 50 Ohm Output gt Von DC 2 4V 2 Output Z0 50 Ohm Vo DC 0 4V lo 22mA 50pF ZZ AT WIN UM 2 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit 8
10. to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage 2 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current ILI 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 min 2 0V AC The undershoot voltage duration is lt 3 Any input OV lt Vin lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state output CAPACITANCE von 3 3V 23 f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance A0 A11 BAO BA1 CIN1 60 90 pF Input capacitance RAS CAS WE CIN2 60 90 pF Input capacitance CKEO CKE1 CIN3 35 55 pF Input capacitance CLKO CLK1 CIN4 25 35 pF Input capacitance CS0 CS1 CIN5 25 35 pF Input capacitance DQM0 DQM7 CIN6 15 25 pF Data input output capacitance DQ0 DQ63 10 25 pF Transcend information Inc 5 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8L2 256MB With 16M X 8 CL2 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter _ Symbol Test Condition Value Unit Note Operating Current Burst Length 1 Icc1 1 12 A 1 One Bank Active tRC tRC min 269 m loL OmA Precharge S
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