Transcend 128MB SDRAM 144Pin SO-DIMM PC66 Unbuffer Non-ECC Memory
Contents
1. Undefined Transcend Information Inc 112. down mode CKE VIH min CLK lt VIL max tCC lt ICC2NS 56 Input signals are stable Active Standby Current ICC3P CKE lt VIL max tCC 15ns 40 X m in power down mode ICC3PS CKE amp CLK lt VIL max tCC lt 40 ICC3N CKESvIEKmIn IOSA HOr One 240 Active Standby Current Input signals are changed one time during 20ns in non power down mode mA CKE gt VIH min CLK lt VIL max tCC lt One Bank Active ICC3NS 160 Input signals are stable IOL 0 mA O ting C t P Burst perating Curren ICCA age Burs 1 000 t 4 Burst Mode 4Banks actived tccD 2CLKs Refresh Current ICC5 tRC tRC min 1 680 mA 2 Self Refresh Current ICC6 CKES lt 0 2V 6 4 mA Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend Information Inc 6 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1ED 128MB With 16Mx8 CL3 AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels ViH ViL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 o ow 1200 Ohm 50 Ohm Vou DC 2 4V lon 2mA Output _Z0 50 Ohm Vor DC 0 4V lo 2mA 50pF __50pF 870 Ohm e THT Fig 1 DC Output Load Ci
3. length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend Information Inc 9 TS16MSS64V1ED Serial Presence Detect Specification 144PIN PC66 Unbuffered SO DIMM 128MB With 16Mx8 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly AO A11 oC 4 of Column Addresses on this Assembly A0 A9 0A 5 of Module Banks on this Assembly 1 banks 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns AO 10 SDRAM Access from Clock highest CL Tns 70 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 cloc
4. 3 Input hold time tSH 1 5 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 7 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 8 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1ED 128MB With 16Mx8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A10 AP A11 Ao Ag Note Register Mode Register Set H x L L L L X OP CODE 1 2 Auto Refresh H 3 Hio peres H L L L H x x Entry L 3 Refresh Self i L H H H 3 Refresh Exit L H X X H X X X 3 Bank Active amp Row Addr H x L L H H x V Row Address Auto Precharge Disable L Column 4 Read amp H X L H L H X V Address Column Address Auto Precharge Enable H ao Ag 45 Auto Precharge Disable L Column 4 Write amp i H x L H L L x v Address Column Address Auto Precharge Enable H A0 A9 4 5 Burst Stop H X L H H L X X 6 Bank Selection V L Precharge H x L L H L x x Both Banks X H d H X X X Clock Suspen or Entry H L x Active Power
5. 4 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current IIL 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs Input Output CAPACITANCE VDD 3 3V TA 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance AO A11 BAO BA1 CIN1 25 45 pF Input capacitance RAS CAS WE CIN2 25 45 pF Input capacitance CKEO CIN3 25 45 pF Input capacitance CLKO 1 CIN4 15 21 pF Input capacitance CSO CIN5 15 25 pF Input capacitance DQM0 DQM 7 CIN6 8 12 pF Data input output capacitance DQ0 DQ63 COUT 9 12 pF Transcend Information Inc 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1ED 128MB With 16Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Burst Length 1 Operating Current i ICC1 tRC gt tRC min 880 mA 1 One Bank Active IOL OmA Precharge Standby Current ICC2P CKE lt VIL max tCC 15ns 8 Aik in power down mode ICC2PS CKE amp CLKsVIL max tCC lt 8 ICCON ORES Ia peeve ns 160 Precharge Standby Current Input signals are changed one time during 20ns k m in non power
6. L V V V xX Down Exit L H X X X X X Ent H X X X y H L x Precharge Power L H H H x Down Mode Exit H X X X s L H x L V V V DQM H X V X 7 i H X X X No Operation Command H x x x L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA are ignored and all banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst
7. Q35 58 CB4 106 BAO 11 Vcc 59 CB1 107 Vss 12 Vcc 60 CB5 108 Vss 13 DQ4 61 CLKO 109 AQ 14 DQ36 62 CKEO 110 BA1 15 DQ5 63 Vcc 111 A10 16 DQ37 64 Vcc 112 A11 17 DQ6 65 RAS 4133 Vcc 18 DQ38 6 CAS 414 Vcc 19 DQ7 67 IWE 115 DQM2 20 DQ39 68 CKE1 116 DQM6 21 Vss 69 CSO 117 DQM3 22 Vss 70 A12 118 DQM7 23 DQMO 71 CS1 119 Vss 24 DQM4 72 A13 120 Vss 25 DQM1 73 NC 121 DQ24 26 DQM5 74 CLK1 122 DQ56 27 Vcc 75 Vss 123 DQ25 28 Vcc 76 Vss 124 DQ57 29 AO 77 CB2 125 DQ26 30 A3 78 CB6 126 DQ58 31 A1 79 CB3 127 DQ27 32 A4 80 CB7 128 DQ59 33 A2 81 Vcc 129 Vcc 34 A5 82 Vcc 130 Vcc 35 Vss 83 DQ16 131 DQ28 36 Vss 84 DQ48 132 DQ60 37 DQ8 85 DQ17 133 DQ29 38 DQ40 86 DQ49 134 DQ61 39 DQ9 87 DQ18 135 DQ30 40 DQ41 88 DQ50 136 DQ62 41 DQ10 89 DQ19 137 DQ31 42 DQ42 90 DQ51 138 DQ63 43 DQ11 91 Vss 139 Vss 44 DQ43 92 Vss 140 Vss 45 Vcc 93 DQ20 141 SDA 46 Vcc 94 DQ52 142 SCL 47 DQ12 95 DQ21 143 Vec 48 DQ44 96 DQ53 144 Vcc Please refer Block Diagram Transcend Information Inc 3 TS1 6MSS64V1 ED 144PIN PC66 Unbuffered SO DIMM 128MB With 16Mx8 CL3 Block Diagram AO A11 BAOZBAI A0 A11 BA0 1 A0 A11 BA0 1 A0 A11 BA0 1 POO DRGS DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 IRAS ICAS WE ICS0 CLKO CKEO amp A0 A11 BA0 1b AO A11 BA0 1 bf A0 A11 BA0 1 be AO A11 BAO 1 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 RAS ICAS 16Mx8 CLK1 be CLK CKE SCL SCL AO A1 a SDA This technical information is based on industry standard data a
8. TS16MSS64V1ED Description The TS16MSS64V1ED is a 16M bit x 64 Synchronous Dynamic RAM high density memory modules The TS16MSS64V1ED consists of 8 piece of CMOS 4Mx8bitsx4banks Synchronous DRAMs_ in TSOP lII 400mil packages and a 2048 bits serial EEPROM on a 144 pin printed circuit board The TS16MSS64V1ED is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range Speed 66MHz e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock 144PIN PC66 Unbuffered SO DIMM 128MB With 16Mx8 CL3 Pin Identification Symbol Function AO A11 Address inputs BAO BA1 Select Bank DQ0 DQ63 Data inputs outputs CLKO CLK1 Clock Input CKEO Clock Enable Input CSO Chip Select Input IRAS Row add
9. k 01 21 SDRAM Module Attributes Non Buffer 00 Prec All Auto Prec R W 22 SDRAM Device Attributes General OE Burst 23 SDRAM Cycle Time 2 highest CL 13ns DO 24 SDRAM Access from Clock 2 highest CL Tns 70 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 24ns 18 28 Minimum Row Active to Row Activate 20ns 14 29 Minimum RAS to CAS Delay 24ns 18 30 Minimum RAS Pulse Width 50ns 32 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 2 5ns 25 33 Command Address Hold Time 1 5ns 15 34 Data Signal Setup Time 2 5ns 25 35 Data Signal Hold Time 1 5ns 15 Transcend Information Inc 10 TS16MSS64V1ED 144PIN PC66 Unbuffered SO DIMM 128MB With 16Mx8 CL3 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC 12 63 Checksum for Bytes 0 62 82 64 71 Manufacturers JEDEC ID Transcend TF 4F 72 Manufacturing Location T 54 54 53 31 36 4D 53 73 90 Manufacturers Part Number TS16MSS64V1ED 53 36 34 56 31 45 44 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 _ Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 126 Intel Specification Frequency 66MHz 66 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 1 C7 128 255 Unused Storage Locations
10. nd tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 144PIN PC66 Unbuffered SO DIMM 128MB With 16Mx8 CL3 TS16MSS64V1ED ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 8 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2
11. rcuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 20 ns 1 RAS to CAS delay tRCD min 24 ns 1 Row precharge time tRP min 24 ns 1 f tRAS min 50 ns 1 Row active time tRAS max 100 us Row cycle time tRC min 80 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 Number of valid output data 2 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 7 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1ED 128MB With 16Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Value Unit Note Min Max CLK cycle time tCC 10 1000 ns 1 CLK to valid output delay tSAC 7 ns 1 2 Output data hold time tOH 3 ns 2 CLK high pulse width tCH 3 5 ns 3 CLK low pulse width tCL 3 5 ns 3 Input setup time tSS 2 5 ns
12. ress strobe ICAS Column address strobe IWE Write Enable DQM0 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data I O SCL Serial Clock NC No Connection Transcend Information Inc TS16MSS64V1ED Placement Dimensions MOODNNOI OOOOH OOO NO NON ONO O 144PIN PC66 Unbuffered SO DIMM TOUT TUTTO ROROA LAERA AOR IAN MUON OOOO NANANA NIN LONLA R NORIA LAURIA ROR ORA RUROINI AAIR panonnnnonnnnnnnnnnnnnnnnnn O O TOUT TOOT MUO OOOO Oooo TUTTO TOOT To ooo O TUTTO TT TTT oo DOMONO OOOO NANANA NN NNN O Side PCB 09 6855 Millimeters Inches A 67 60 0 20 2 661 0 008 32 80 1 291 23 20 0 913 4 60 0 181 3 30 0 130 2 50 0 098 2 55 0 100 I Jn m jo O w 4 00 0 157 I 20 00 0 787 J 26 67 0 20 1 050 0 008 K 1 00 0 10 0 039 0 004 Refer Placement 128MB With 16Mx8 CL3 Transcend Information Inc 144PIN PC66 Unbuffered SO DIMM TS16MSS64V1ED 128MB With 16Mx8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 49 DQ13 97 DQ22 02 Vss 50 DQ45 98 DQ54 03 DQO 51 DQ14 99 DQ23 04 DQ32 52 DQ46 100 DQ55 05 DQ1 53 DQ15 401 Vcc 06 DQ33 54 DQ47 102 Vcc 07 DQ2 55 Vss 103 A6 08 DQ34 56 Vss 104 A7 09 DQ3 57 CBO 105 A8 10 D
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