Transcend 256MB SDRAM PC133 ECC Unbuffer Memory
Contents
1. 9 PCB 09 7149 Y n E gt r A 4 n anu I gt lt Transcend Information Inc TS32MLS72V6D Dimensions Side Millimeters A 133 35 0 40 65 67 23 49 8 89 3 00 31 75 0 20 19 80 15 80 1 27 0 10 Refer Placement Transcend Information Inc Inches 5 250 0 016 2 585 0 925 0 350 0 118 1 250 0 008 0 780 0 622 0 050 0 004 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 Pin Identification Symbol Function A0 A11 BA0 BA1 Address input DQ0 DQ63 C0 C7 CLKO CLK3 CKEO CKE1 CS0 CS3 RAS ICAS IWE DQM0 DQM7 SA0 SA2 SCL SDA Data Input Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data DQ Mask Address in EEPROM Serial PD Clock Serial PD Add Data input output 5 0 Voltage Power Supply Ground No Connection 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 Pinouts Please refer Block Diagram Transcend Information Inc 3 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 Block Diagram2. 11 11 11 11 11 11 BAO BA1 a BAO BA1 BAO BA1 A BAO BA1 BAO BA1 BAO BA1 DQ0 DQ63 T DQ0 DQ7 ig DQ0 DQ7 ES DQ0 DQ7 m DQ0 DQ7 mas RAS lems IRAS m Da NETTE 8 RAS 6 ICAS SDRAM peas SDRAM m SDRAM cas SDRAM WE CSO FEE Py x eee P P A p CLKO elie TTT T o To T C Jj y a oe HH RAS z RAS IRAS 7 RAS 16Mx8 16Mx8 16Mx8 16Mx8 SDRAM I SS SDRAM il ers SDRAM Mees SDRAM TT WE m WE i WE ial WE FERRERS ES gt Yes m E Q CKE g 1 beams DQM6 DQM7 AO A11 AO A11 a BAO BA1 BAO BA1 8 BAO BA1 am DQ0 DQ7 RAS SB 16Mx8 ICAS 16Mx8 SDRAM SDRAM G ss H LUT qapi ER ss ort y AT Y A0 A11 L 11 X AO0 A11 X ET m I 1 O D BAO BA1 O BA1 O BAO BA1 O DQ0 DQ7 mee DQ7 T DQ0 DQ7 DQ0 DQ7 RAS RAS RAS RAS ICAS SDRAM licas spram HH CAS spram CAS SDRAM WE WE WE WE ICS gt ICS gt gt ICS E ckE 9 En 8 CkE g g DQM5 pav Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in c
3. 128 Unused Storage Locations Transcend Information Inc 11
4. AT Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted imo min tocp min Number of valid output data case _ clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 7 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Max Unit CAS latency 3 7 5 CLK cycle time tcc CAS latency 2 CLK to valid CAS latency 3 t output delay SAC CAS latency 2 Output data CAS latency 3 t hold time OH CAS latency 2 tcH tcL Input setup time tss Input hold time tsH CLK to output in Low Z CAS latency 3 tSHZ CAS latency 2 Ca ss Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter Transcend Information Inc 8 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 SIMPLIFIED TRUTH TABLE com ES ET TENE Ja aaa Auto Refresh ESSERE Eny i Self Refresh Bank Active amp Row Add Ac
5. TS32MLS72V6D 168PIN PC133 Unbuffered DIMM 256MB With 16Mx8 CL3 Description The TS32MLS72V6D is a 32M x 72bits Synchronous Dynamic RAM high density for PC 133 The TS32MLS72V6D consists of 18pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS32MLS72V6D is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 CL3 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e Power Down Mode e DQM Byte Masking Read Write Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock
6. e Standby Current lcczP CKE Viumax Io Tons 36 power down mode Icc2PS CKE amp CLK lt VIL max tcc lt ICC2N CKE ViH min CS 2ViH min tcc 10ns 360 Input signals are changed one time during 20ns Precharge Standby Current mA in non power down mode CKE2VIH min CLKxVIL max tcc ICC2NS 180 nput signals are stable Il Active Standby Current lccaP CKEsViumax tcc 10ns w in power down mode Icc3PS_ CKE amp CLK lt ViL max tcc Active Standby Current Icc3N s ICS gt ViH min tcc 10s e nput signals are changed one time during 30ns in non power down mode Bank Acti ne ICC3NS CKE ViH min CLK lt VIL max tcc Input signals are stable loL 0 mA Page Burst Operating Current Bust Mode 4 Banks activated 1 620 mA 1 tccp 2CLKs Refresh Current lccs mc gt tac min 2 070 Self Refresh Current Icos ckE o2v 3 m 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noted input swing level is CMOS ViH ViL VDDQ VSSQ AC OPERATING TEST CONDITIONS vpp 3 3V 0 3V TA 0 to 70 C Transcend Information Inc 6 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 AC Input levels VIH VIL 2 4 0 4 unit 0 Output load condition Ser2 3 3V Vtt 1 4V 1200 Ohm 50 Ohm gt Vor DC 2 4V lou 2mA Output O Z0 50 Ohm Vo DC 0 4V lo 2mA B0pF B5OpF 870 Ohm
7. erial Presence Detect Number of Row Addresses on this Assembly 2 0 Number of Module Rows on this Assembly 7 Data Width of this Assembly U SDRAM Cycle Time CAS latency of 3 10 11 C 13 Primary SDRAM Width 8 8 3 14 15 16 17 Non buffered SDRAM Module Attributes non registered amp redundant addressing 10 voltage tolerance Burst Read SDRAM Device Attributes General Single bit Write precharge all auto precharge g 23 SDRAM Cycle Time CAS Latency of 2 AO 24 SDRAM Access Time from Clock CAS Latency of 2 DRAM Cycle Time CAS Latency of 1 3 Byte No ee zas 28 REC 10 pH 44 gc 16 zs RELI 19 04 0 0 02 48 01 75 54 02 8F 04 01 18 19 20 N N N 20ns m 2 2 2 2 2 36 61 Superset Information R ae Transcend Information Inc 10 OF 2D 20 15 5 6 7 8 9 30 31 32 33 34 35 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 62 SPD Data Revision Code JEDEC2 63 Checksum for Bytes 0 62 ca On cess e 64 71 Manufacturers JEDEC ID Code per JEP 108E 7F 4F T 72 Manufacturing Location 54 33 32 73 90 Manufacturers Part Number TS32MLS72V6D 32 56 20 20 91 92 Revision Code 0 99 125 Manufacturer SpecificData 0 126 lintel Specification Frequency x L ___ 6
8. onnection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 ABSOLUTE MAXIMUM RATINGS Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE Vpp 3 3V 23 C f 1MHz VREF 1 4V 200mV Address Ao A11 BAO BA1 IRAS CAS WE CKEO CKE1 Clock CLKO CLK3 ICS CSO CS3 DQM DQMO DQM7 DQ DQ0 DQ63 CB CBO CB7 DC CHARACTERISTICS Transcend Information Inc 5 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 Recommended operating condition unless otherwise noted TA 0 to 70 C Operating Current Purr ha 1 080 A 1 m One Bank Active ee ey lo 0mA Precharg
9. tive amp Row Addr Read amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable Ao As Auto Precharge Disable Column Address Auto Precharge Enable Ao As Bank Selection Both Banks Clock Suspend or Active Power Down No Operation Command H x V Valid X Don t Care H Logic High L Logic Low 1 OP Code Operand Code 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA4 is High at read write row active and precharge bank B is selected If both BAo is High and BA4 is Low at read write row active and precharge bank C is selected Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DOM latency is 2 Transcend Information Inc 9 168PIN PC133 Unbuffered DIMM TS32MLS72V6D 256MB With 16Mx8 CL3 Serial Presence Detect Specification S
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