Transcend 128MB DDR266 Unbuffer Non-ECC Memory
Contents
1. Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Information Inc j TS16MLD64V6D5 184PIN DDR266 Unbuffered DIMM 128MB With 16Mx8 CL2 5 Dimensions Side Millimeters 133 35 0 20 I Q TI m O JO W 72 39 6 35 2 20 31 75 0 20 19 80 4 00 12 00 1 27 0 10 Refer Placement Transcend Information Inc Inches 5 250 0 008 2 850 0 250 0 087 1 250 0 008 0 779 0 157 0 472 0 050 0 004 Pin Identification Symbol Function A0 A11 BAO BA1 Address input DQ0 DQ63 DQS0 DQS7 CKO CKO CK1 CK1 CK2 CK2 CKEO CS0 IRAS ICAS ANE DMO DM7 VDD VDDQ VREF VDDSPD SA0 SA2 SCL SDA VSS NC Data Input Output Data strobe input output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data in Mask 2 5 Voltage power supply 2 5 Voltage Power Supply for DQS Power Supply for Reference 2 5 Voltage Serial EEPROM Power Supply Address in EEPROM Serial PD Clock Serial PD Add Data input output Ground No Connection 184PIN DDR266 Unbuffered DIMM TS1 6M LD64V6D5 128MB With 16Mx8 CL2 5 Pinouts Please refer Block Diagram Transcend Information Inc 3 184PIN DDR266 Unbuffered DIMM TS1 6M LD64V6D5 128MB With 16Mx8 CL2 5 Block Diagram A0 A11 BAO BA1 DQ0 DQ63 RAS ICAS IWE CSO CKEO A0 A11 N BAO BA1 DQ2. 0 DQ7 A0 A11 B BAO BA1 DQ0 DQ7 CK1 CK1 CKO CKO ck2 ck2 M BAO BA1 DQ0 DQ7 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184PIN DDR266 Unbuffered DIMM TS1 6M LD64V6D5 128MB With 16Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Umt Voltage on any pin relative to Vss Voltage on VDD supply to Vss 1 0 3 6 torage temperature 55 150 hort circuit current los o0 Mean time between failure MTBF 50 year emperature Humidity Burning THB C emperature Cycling Test TC C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability Power dissipation DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C upply voltage O Supply voltage O Reference voltage O Termination voltage nput logic high voltage nput logic low vo
3. 184PIN DDR266 Unbuffered DIMM TS1 6M LD64V6D5 128MB With 16Mx8 CL2 5 Description V E The TS16MLD64V6D5 is a 16M x 64bits Double Data o V Rate SDRAM high density for DDR266 The TS16MLD64V6D5 consists of 8pcs CMOS 16Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS16MLD64V6D5 is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the NM MN NM NI Lone MN use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply VDD 2 5V 0 2V VDDQ 2 5V x 0 2V e Max clock Freq 133MHZ m am e Double data rate architecture two data transfers per n clock cycle mH e Differential clock inputs CK and CK x gt c e DLL aligns DQ and DOS transition with CK transition e Auto and Self Refresh 15 6us refresh interval esp e Data l O transactions on both edge of data strobe e Edge aligned data output center aligned data input e Serial Presence Detect SPD with serial EEPROM e SSIL 2 compatible inputs and outputs e MRS cycle with address key programs PCB 09 1395 CAS Latency
4. AM Cycle Time at CAS Latency 2 5 75ns 75 11 DIMM configuration type non parity Parity ECC NON ECC 00 12 RefreshRateType 15 6 25us SelfRefresh 8 13 PrimaryDDRSDRAMWidth Y X Y 08 14 Error Checking DDR SDRAM Width o Z O OT o o 15 Min Clock Delay for Back to jese rencom lu dereso eek 18 0C 19 20 0 Registered address amp DDR SDRAM Module Attributes control inputs and N L 18 OC O 19 IN ONE on card DLL o aem NM tolerance 25 DDRSDRAMCycleTimeCL 1 5 O 00 26 DDR SDRAM Access from Clock CL 1 5 o 00 32 Command Address Input Setup fme 0O9n 90 O 33 Command Address Input Hold Ime SCs 90 36 61 Superset Information o com X4 dE 4 62 SPD Data Revision Code CT 00 JJ 63 Checksum for Bytes062 1 1 1 9C O Transcend Information Inc 10 TS1 eM LD64V6D5 184PIN DDR266 Unbuffered DIMM 128MB With 16Mx8 CL2 5 64 71 Manufacturers JEDEC ID 7F 4F 72 Manufacturing Location 54 54 ss 31 3e 40 40 73 90 Manufacturers Part Number TS16MLD64V6D5 35 20 20 20 20 20 Variable Variable 99 127 Manufacturer Specific Data o 91 92 Transcend Information Inc 1
5. SO Input capacitance CKO CK2 Input capacitance DMO DM7 Data and DQS input output capacitance DQ0 DQ63 Transcend Information Inc 7 184PIN DDR266 Unbuffered DIMM TS1 6M LD64V6D5 128MB With 16Mx8 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol Min Max Row cycle time RC 65 Jd ms Refresh row cycle time REC 75 y ms Row active time ns RAS to CAS delay tRCD 20 JJ ns Row active to Row active delay RP oO 20 ns Row active to Row active delay RRD 15 ns Write recovery time WWR 415 dX 4A ms ast data in to Read command WTR 1 tCK Col Address to Col Address delay CCD Wo 4 T ol tCK Clock cycle time CK 75 S ms Clock high level width tCK Clock low level width tCK DQS out access time from CK CK S Output data access time from CK CK S Data strobe edge to output data edge IDOSO 05 ns Read Preamble tRPRE 09 2311 JJ tK Read Postamble tRPST 04 06 tCK CK to valid DOS in 1 25 CK DOS in setup time tWPRES 0 ms Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High Z to logic Low applies when no writes were previously in progress on the bus Ifa previous write was in progress DQS could be High at this t
6. e bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and BAT is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected 5 If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are selected 6 During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is O This combination is not defined for any function which means No Operation NOP in DDR SDRAM Coco Transcend Information Inc 0 184PIN DDR266 Unbuffered DIMM TS1 6M LD64V6D5 128MB With 16Mx8 CL2 5 Serial Presence Detect Specification Serial Presence Detect 0 of Bytes Written into Serial Memory 128byes BO 1 TetalfofBytesof S P D Memory 256byes 008 6 jDataWidthofthisAssemby amp 4bts 40 Data Width of this Assembly Eom 00 Data Width of this Assembly 8 VDDQ and Interface Standard of this Assembly SSTL25V A 9 JDDR SDR
7. ic 0 Voltage DO DOS and DM signals VIL AC VREF 031 V 3 Input Differential Voltage CK and CK inputs VID AC VDDQ 06 IV 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 02 0 5 VDDQ 02 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Value Unt Note Input reference voltage for Clock O5VDDQ V Input signal maximum peak swing o o 15 V input Levels VIH VIL VREFXO3INREFO3T1 V J o o Input timing measurement reference level VREE V Output timing measurement reference level vir v Output load condition S See toad Circuit o o VTT 0 5 VDDQ 0 5 VDDQ NE Output Load circuit Input Output CAPACITANCE Voo 2 5V Vppo 2 5V TA 25 C f 1MHz Input capacitance A0 A11 BAO BA1 RAS CAS ANE Input capacitance CKEO Input capacitance C
8. ime depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly Transcend Information Inc g 184PIN DDR266 Unbuffered DIMM TS16MLD64V6D5 128MB With 16Mx8 CL2 5 SIMPLIFIED TRUTH TABLE VzValid X lt Don t Care H Logic High L Logic Low Extended Reaster de Register sor MEHER pen Hof X pepe pe ft OP CODE mE EH ja ja e Enty m Refresh Self m Em a E CREET o ae Bank Active amp Row Addr Row Address Read amp Auto Precharge Disable Auto Precharge Disable nam Column o Column Address Auto Precharge Enable Ao Ao Write amp Auto Precharge Disable Column Address Column Address Auto Precharge Enable Auto Precharge Enable NM sne Burst Stop Burst Stop Precharaa Bank Selection g All Banks Active Power Down Precharge Power Down Mode Note 1 OP Code Operand Code A0 A11 amp BAO BA1 Program keys EMRS MRS 2 EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS 3 Auto refresh functions are same as the CBR refresh of DRAM The automatic precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAO BAT Bank select addresses If both BAO and BA1 are Low at read write row active and precharg
9. in the dc level of the same Transcend Information Inc 5 184PIN DDR266 Unbuffered DIMM TS1 6M LD64V6D5 128MB With 16Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Operating current One bank Active Precharge tRC tRCmin tCK 133MHZ for DDR266 DQ DM and DGS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle Operating current One bank operation One bank open Burst 4 Reads mpi 90 m Refer to the following page for detailed test condition Percharge power down standby current All banks idle power down mode ope 2 m CKE lt VIL max tCK 133MHZ for DDR266 VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 133MHZ for DDR266 Address and other control inputs IDD2F 176 mA changing once per clock cycle VIN VREF for DQ DQS and DM Precharge Quiet Standby current CS gt VIH min All banks idle CKE gt VIH min tCK 133MHZ for DDR266 Address and other control inputs IDD2Q 120 stable with keeping gt VIH min or lt VIL max VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode IDD3P 280 CKE lt VIL max tCK 133MHZ for DDR266 VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC
10. ltage nput Voltage Level CK and CK inputs nput Differential Voltage CK and CK inputs nput crossing point voltage CK and CK inputs VIX DC nput leakage current uA Output leakage current loz uA Output High Current Normal strength driver lOH a UH mA VOUT VTT 0 84V Output Low Current Normal strength driver IOL 16 8 mA VOUT VTT 0 84V NEN Output High Current Half strength driver OH mA VOUT VIT s 048V NI Output High Current Half strength driver IOL Z NMR ai Note 1 Includes 25mV margin for DC offset on VREF and a combined total of x 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations
11. tRASmax tCK 133MHZ for DDR266 IDD3N 440 ne DQ DQS and DM inputs changing twice per clock cycle Address and other control inputs changing once per clock cycle Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle IDD4R 1136 mA 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuous burst One bank active address and control inputs changing once per clock cycle IDDAW 1040 mE CL 2 5 at tCK 133MHZ for DDR266 DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst Auto refresh current tRC tRFC min 10 tCK for DDR266at 133Mhz distributed refresh IDs 1480 ma Self refresh current CKE 0 2V External clock should be on mp6 16 maf tCK 133MHZ for DDR266 Operating current Four bank operation Four bank interleaving with BL 4 Refer to the following page for detailed test condition m7 240 m Note 1 Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor 760 mA Transcend Information Inc 6 184PIN DDR266 Unbuffered DIMM TS16MLD64V6D5 128MB With 16Mx8 CL2 5 AC OPERATING CONDITIONS Symbol Min Max Unit Note nput High Logic 1 Voltage DO DOS and DM signals VIH AC VREF 0 31 NM K Z ME nput Low Log
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