Transcend 512MB SDRAM PC133 ECC Unbuffer Memory
Contents
1. Serial Number By Manufactory Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 3 F6 128 Unused Storage Locations Open FF Transcend information Inc 112. Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 Prec All Auto Prec 22 SDRAM Device Attributes General R W Burst 23 SDRAM Cycle Time 273 highest CL 00 24 SDRAM Access from Clock om highest CL 10ns AO 25 SDRAM Cycle Time Cy highest CL 6ns 60 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 1row of 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 D5 Transcend information Inc 10 168PIN PC133 Unbuffered DIMM TS64MLS72V6F 512MB With 32Mx8 CL3 64 71 Manufacturers ID Code per JEP 108E Transcend TF 4 72 Manufacturing Location T 54 54 53 36 34 4D 4C 73 90 Manufacturers Part Number TS64MLS72V6F 53 37 32 56 36 46 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufactory Variable 95 98
3. Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time 28 ns 1 tRAS max 100 us Row cycle time tRC min 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccp min 1 CLK 3 Number of valid output data CAS latency 3 2 4 CAS latency 2 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 7 168PIN PC133 Unbuffered DIMM TS64MLS72V6F 512MB With 32Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Min Max Unit Note CAS latency 3 7 5 CLK cycle time us tcc 1000 ns 1 CAS latency 2 10 CLK to valid 24 ns 1
4. 168PIN PC133 Unbuffered DIMM TS64MLS72V6F 512MB With 32Mx8 CL3 Description Placement The TS64MLS72VGF is a 64M bit x 64 Synchronous Dynamic RAM high density for 133 The TS64MLS72V6F consists of 18pcs CMOS 32 8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS64MLS72VGF is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 B e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e Power Down Mode e DQM Byte Masking Read Write Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MR
5. 2 output delay CAS latency 2 6 Output data tOH 3 i ns 2 hold time CAS latency 2 3 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z CAS latency 3 tSHZ 5 4 is CAS latency 2 6 Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC133 Unbuffered DIMM TS64MLS72V6F 512MB With 32Mx8 CL3 SIMPLIFIED TRUTH TABLE COMMAND 1 CS RAS ICAS DQM BAo Ato AP gies Note Register Mode Register Set H X L L L L X OP CODE 12 Auto Refresh H H L L L H 3 Entry L 3 Refresh Self L H H H 3 Refresh i Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Address Auto Precharge Disable L Column 4 Read amp 9 H X L H L H X V Address Column Address Auto Precharge Enable H 4 5 i Auto Precharge Disable L Column 4 Write 3 H x L H L L X v Address Column Address Au
6. 2 Vss 33 AO 34 A2 35 A4 36 A6 37 A8 38 A10 AP 39 BA1 40 Vcc 41 Vcc 42 CLKO Pin No 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Please refer Block Diagram Transcend information Inc TS64MLS72V6F 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Block Diagram A0 A12 A0 A12 12 A0 A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ63 DQ0 DQ7 DQ0 DQ7 090 007 IRAS IRAS IRAS 32Mx8 32Mx8 ICAS ICAS SDRAM ICAS SDRAM ICS x 0 12 BAO BA1 DQ0 DQ7 A0 A12 v BAO BA1 090 007 E IRAS IRAS IRAS 32Mx8 32Mx8 mu 32Mx8 ICAS SDRAM Alpe SDRAM ICAS SDRAM i a ICS CKE g DQM5 J 12 A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 BAO BA1 290 007 090 007 290 007 090 007 IRAS IRAS IRAS 32Mx8 32Mx8 32Mx8 ICAS SDRAM ICAS SDRAM ICS gt x A0 A12 BAO BA1 BAO BA1 o BAO BA1 DQ0 DQ7 DQ0 DQ7 000 007 IRAS IRAS IRAS 32Mx8 32Mx8 32Mx8 ICAS SDRAM ICAS SDRAM SDRAM ICS ICS 8 CKE 8 DQM4 DQM5 J Serial EEPROM SCL SCL SDA SDA AO A1 A2 SA0 SA1 SA2 32Mx8 SDRAM This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties eit
7. S cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave PCB 09 7147 e All inputs are sampled at the positive going edge of the system clock Transcend information Inc 1 TS64MLS72V6F 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Dimensions Pin Identification Side Millimeters Inches yn 133 35 0 40 5 250 0 016 12 Address input B 65 67 2 585 23 49 0 925 DQ0 DQ63 Data Input Output D 8 89 0 350 CLKO CLK3 Clock Input E 3 00 0 118 F 31 7520 20 1 250 0 008 CKEO CKE1 Clock Enable Input G 19 80 0 788 H 15 80 0 622 CS0 CS3 Chip Select Input 1 27 0 10 0 050 0 004 RAS Row Address Strobe Refer Placement ICAS Column Address Strobe IWE Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend information Inc TS64MLS72V6F 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Pinouts Pin Pin No Name 01 Vss 02 DQO 03 DQ1 04 DQ2 05 DQ3 06 Vcc 07 DQ4 08 DQ5 09 DQ6 10 DQ7 11 DQ8 12 Vss 13 DQ9 14 DQ10 15 DQ11 16 DQ12 17 DQ13 18 Vcc 19 DQ14 20 DQ15 21 CBO 22 CB1 23 Vss 24 NC 25 NC 26 Vcc 27 ANE 28 DQMO 29 DQM1 30 CSO 31 NC 3
8. current Inputs liL 10 10 uA 3 Input leakage current I O pins liL uA Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 Dout is disabled OV lt VouT lt VDDQ Transcend information Inc 168PIN PC133 Unbuffered DIMM TS64MLS72V6F 512MB With 32Mx8 CL3 CAPACITANCE VDD 3 3V TA 20 C f 1MHz VREF 1 4V 200 mV Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA1 CIN1 85 105 pF Input capacitance RAS CAS WE CIN2 85 105 pF Input capacitance CKEO CIN3 50 65 pF Input capacitance CLKO CLK3 CINA 40 45 pF Input capacitance 50 CS2 CIN5 30 40 pF Input capacitance DQM0 DQM 7 CIN6 25 30 pF Data input output capacitance 000 0063 10 15 pF Data input output capacitance CBO CB7 2 10 15 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition CAS Latency Value Typ Unit Note Operating Current Burst Length 1 Taso One Bank Active loL 0mA Precharge Standby Current 2 __ CKExViL max tcc 10ns 36 mA in power down mod
9. e Icc2PS amp CLKxViL max tcc e 36 CKE ViH min CS ViH min tcc 10ns Precharge Standby Current Icc2N Input signals are changed one time during 20ns 360 in non power down mode ICC2NS CKE2VIH min CLK lt VIL max tcc 180 Input signals are stable Active Standby Current Icc3P CKE lt ViL max tcc 10ns 108 mA in power down mode IccaPS CKE amp CLK lt ViL max tcc 108 Active Standby Current Icc3N CKE2VIH min CS2Vin min tcc 10ns 540 Input signals are changed one time during 20ns in non power down mode TA ONE BARK ARIVE Icc3NS gt CLK lt ViL max tec 450 Input signals are stable loL 0 mA eee Icc4 Page Burst s 1260 1 tccp 2CLKs 2 z Refresh Current ICC5 tRC2tRC min 2 070 mA 2 Self Refresh Current cce CKE lt 0 2V 54 mA Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 6 168PIN PC133 Unbuffered DIMM TS64MLS72V6F 512MB With 32Mx8 CL3 AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 o om Vou DC 2 4V 2 Output Z0 50 0hm 9 Vo DC 0 4V lo 2mA 50 LL 870 Ohm TIT Fig 1 DC Output Load
10. her expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc TS64MLS72V6F ABSOLUTE MAXIMUM RATINGS 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TsTG 55 150 C Power dissipation PD 16 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Hr Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 24 V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage
11. ssued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 TS64MLS72V6F Serial Presence Detect Specification 168PIN PC133 Unbuffered DIMM 512MB With 32Mx8 CL3 Serial Presence Detect Byte No Function Described S cun E ae Vendor Part pecification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 13 00 4 of Column Addresses this Assembly 10 0A 5 of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 72bits 48 7 Data Width Continuation 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC ECC 02 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width X8 08 15 Min Clock Delay Back to Back Random
12. to Precharge Enable H amp A 4 5 Burst Stop H X L H H L X X 6 Bank Selection V L Precharge Both Banks H X L L H L X X H X H X X X Entry H L X Clock Suspend or L V V V X Active Power Down Exit L H X X X X X H X X X Entry H L X Precharge Power H H X Down Mode Exit H X X X m L H x L V V V DOM H X V X 7 H X X X No Operation Command H X X X L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BAt1 are Low at read write row active and precharge bank A is selected If both BAo is Low and 1 is High at read write row active and precharge bank is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BAt1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be i
Download Pdf Manuals
Related Search