Transcend 128MB SDRAM PC133 ECC Unbuffer Memory
Contents
1. currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE TA 25 C f 1MHz Parameter Input capacitance Ao A11 BAo BA1 Input capacitance RAS CAS WE Input capacitance CKEO Input capacitance CLKO CLK2 Input capacitance CS0 CS2 Input capacitance DQMO DQWM7 Data input output capacitance DQ0 DQ63 CBO CB7 Transcend Information Inc 5 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2V6D 128MB With 16Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Symbol Test Condition Value Unit Note Operating Current Burst Length 1 tRC2tRC min One Bank Active TEE s Precharge Standby Current lccaP ckEs Vi max tcc 10ns in power down mode Icc2PS CKE amp CLK lt ViL max tcc CKE ViH min CS ViH min tcc 10ns Input signals are changed one time during 30ns ICC2N Precharge Standby Current in non power down mode CKE ViH min CLKxViL max tcc Input signals are stable Active Standby Current IccsP CKEsVi max tcc 10ns o 45 ICC2NS Icc3N CKE ViH min CS2ViH min tcc 10ns Active Standby Current Input signals are changed one time during 30ns in non power down mode Bank Acti SERES Icc3NS_ CKE gt Vin min CLK lt ViL max tcc Input signals are stable Operating Current a 2 Bust Mode age wae tccp 2CLKs Refresh Current tRC2tRC min 1800 Note2. 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS VIH VIL VDDQ VSsqQ Transcend Information Inc 6 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2V6D 128MB With 16Mx8 CL3 AC OPERATING TEST CONDITIONS vop 3 3V 0 3V TA 0 to 70 C Parameter vau Unt AC Input levels VIH VIL 2 4 0 4 Input timing measurement reference level Input rise and fall time tr tf 1 1 Output timing measurement reference level Output load condition See Fig 2 1200 Ohm VoH DC 2 4V lou 2mA Output Vo DC 0 4V lo 2mA 5 OpF 870 Ohm DAMM M 1 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Row active to row active delay RAS to CAS delay Row precharge time Row active time i Row cycle time Last data in to new col address delay Last data in to row precharge Last data in to burst stop iccotmin Number of valid CAS latency 3 output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend Information Inc 2 168Pin PC133 ECC Unb
3. 128MB With 16Mx8 CL3 33 Command Address Hold Time Oss 08 35 Data Signal Hold Time Oss 08 36 61 Superset Information 82 _ SPD Data Revision Code JEDEC2 O2 EM A for Bytes 0 62 Len 71 Manufacturers JEDEC ID Code Manufacturers JEDFC D Goge per JEP 108E _ JEP 108E IHE 4F 72 Mandfactuinglocaion ring Location 73 90 Part Number TS16MLS72V6D 32 56 93 904 94 Manufacturing Date Date 99 125 Manufacturer Speciie bala 9 126 intel Specification Frequency o y a 0 127 line Specfeaton GAS Lstonoyok Signal Suppor LES GiokO 3 ag 128 _ Unused Storage Locations Opn FF O Transcend Information Inc 1
4. Dimensions Side Millimeters Inches A 133 35 0 40 5 250 0 016 B 65 67 2 585 C 23 49 0 925 D 8 89 0 350 E 3 00 0 118 F 31 77 0 20 1 250 0 008 G 19 80 0 788 H 15 80 0 622 1 27 0 10 0 050 0 004 Refer Placement Pin Identification Symbol AO0 A11 BAO BA1 DQ0 DQ63 CBO CB7 CLKO CLK2 CKEO CS0 CS2 RAS ICAS WE DQM0 DQM 7 SA0 SA2 SCL SDA Vcc Vss NC Function Address input Data Input Output Check Bit Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data DQ Mask Address in EEPROM serial PD Clock Serial PD Add Data input output 3 3 Volt Power Supply Ground No Connection Transcend Information Inc 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2V6D 128MB With 16Mx8 CL3 Pinouts Pin Name No Name Please refer Block Diagram Transcend Information Inc 3 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2V6D 128MB With 16Mx8 CL3 Block Diagram CBO CB7 A0 A11 BAO BA1 BAO BA1 DQ0 DQ63 DQ0 DQ7 RAS ET H RAS ICAS ICAS SDRAM i ANEN eS ieee Ed B TT ae mina ss a6 LEELEEE BAO BA1 DQO0 DQ7 RAS 16Mx8 ICAS SDRAM ICAS SDRAM IWE IWE ICS Serial EEPROM SCL SCL SDA SDA A0 A1 A2 SA0 SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assu
5. TS16MLS72V6D Description The TS16MLS72V6D is a 16M x 72bits Synchronous Dynamic RAM high density for PC 133 The TS16MLS72V6D consists of 9pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS16MLS72V6D is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 133 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Transcend Information Inc 168Pin PC133 ECC Unbuffered DIMM Placement 128MB With 16Mx8 CL3 M Lo F PCB 09 7149 TS16MLS 2V6D 168Pin PC133 ECC Unbuffered DIMM 128MB With 16Mx8 CL3
6. V6D 128MB With 16Mx8 CL3 Serial Presence Detect Specification Serial Presence Detect Standard Byte No Function Described DU Vendor Part Specification 0 jfofBytesWrttenintoSeral Memory 128byes 04 EN GNE 0C 0A of Module Banks on this Assembly 01 48 0 __ dk j 01 9 SDRAM Cycle Time highest CAS latency 75ns 75 10 SDRAM Access from Clock highest CL 11 DIMM configuration type non parity ECC 12 Refresh Rate Type 15 625us Self d Refresh 18 PPrmaySDRAMWidh S X8 08 14 EmorChecingSDRAMWidh x 18 cAS Latency o 1 2883 06 21 SDRAMModule Attributes NonBufer 00 22 l Prec All Auto Prec OE SDRAM Device Attributes General R W Burst 23 SDRAM Cycle Time 2 highest CL 24 SDRAM Access from Clock 2 highest CL es 60 25 SDRAM Cycle Time 3 highest CL EE NEM NNNM MEM 26 SDRAM Access from Clock 37 highest CL 0 0 Transcend Information Inc 10 1 2 3 D lo 3 3 3k m Ig O o o lo IS Q Q se ME o o 3 J 2 c Q D D 3 5 S S gt 23 o D 2 Q bk JO a z 2 o Q D 3n m 2 IB oO Z D D Y D IH o TE 2 0 o iO U Q IO jO o 3 4 oO 3 3 o x U Q O 3 m gt V 0 i gt o io gt 2 9 7 o 8 lt gt o 2 N Oo O U 3 lt S O e lt Ke 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2V6D
7. mes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2V6D 128MB With 16Mx8 CL3 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Vaue Unt Voltage on any pin relative to Vss Voltage on VDD supply to Vss Storage temperature aan I N 1 4 1 j Shortcircuitourent lo a mA 0 C 125 C Cycling Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Type Max Unt Note Supply voltage vo 30 33 36 v 3 Ipuwvotge w o3 o o8 v 2 Output high voltage vo 24 v IoH 2m Oupulowvotae va 04 v ioma Input leakage current Inputs m o 10 vA 3 Note 1 ViH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is x 3ns 3 Any input OV x VIN lt VDDQ Input leakage
8. uffered DIMM TS1 6M LS 2V6D 128MB With 16Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol value Min Valure Max Unt Note CLK cycle time icc CLK to valid output delay tsa 54 S Output data hold time tOH ns i i toh ns tou ns Input setup time tSS ns Input hold time tSH ns CLK to output in Low Z ns tSHZ Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 8 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2V6D 128MB With 16Mx8 CL3 SIMPLIFIED TRUTH TABLE Auto Refresh omen te Refresh Self Entry EN i few o Bank Active amp Row Addr DESE Read amp Auto Precharge Disable cu Column Address Auto Precharge Enable less Ao Ag Write amp Auto Precharge Disable nn 7 Column Address Column Address Auto Precharge Enable Ao Ag ara C2 A C1 A C1 Bank Selection Both Banks Clock Suspend or Entry pe Active Power Down ext Entry Precharge Power Down Mode No Operation Command V Valid X Don t Care H Logic High L Logic Lo
9. w Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BAt1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BAi are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend Information Inc 9 168Pin PC133 ECC Unbuffered DIMM TS1 6M LS 2
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