Transcend 256MB DDR333 Unbuffer Non-ECC Memory
Contents
1. Address to Col Address delay tCCD 1 tCK Clock cycle time tCK 6 ns 4 Clock high level width tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time from CK CK tDQSCK 0 6 0 6 ns Output data access time from CK CK tAC 0 7 0 7 ns Data strobe edge to output data edge tDQSQ 0 45 ns 4 Read Preamble tRPRE 0 9 1 1 tCK Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 75 1 25 tCK DQS in setup time tWPRES 0 ns 2 DQS in hold time tWPREH 0 25 tCK DQS falling edge to CK rising setup time tDSS 0 2 tCK DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK DQS in cycle time tDSC 0 9 1 1 tCK Address and Control input setup time tIS 0 75 ns Address and Control input hold time tlH 0 75 ns Data out high impedance time from CK CK tHZ 0 7 0 7 ns Data out low impedance time from CK CK tLZ 0 7 0 7 ns Mode register set cycle time tMRD 12 ns DQ amp DM setup time to DQS tDS 0 45 ns DQ amp DM hold time to DQS tDH 0 45 ns DQ amp DM input pulse width tDIPW 1 75 ns Exit self refresh to non read command tXSNR 75 ns 4 Exit self refresh to read command tXSRD 200 tCK Refresh interval time tREF 7 8 us 1 tCLmin or Clock half period tHP tCHmin ns DQS write postamble time DRSI ieni tCK 3 Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case s2. 04 18 CAS Latency supported 2 2 5 0C 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 Registered address amp 21 DDR SDRAM Module Attributes control inputs and 20 on card DLL 22 DDR SDRAM Device Attributes General trey Slade 00 tolerance 23 DDR SDRAM Cycle Time CL 2 0 7 5ns 75 24 DDR SDRAM Access from Clock CL 2 0 0 7ns 70 25 DDR SDRAM Cycle Time CL 1 5 00 26 DDR SDRAM Access from Clock CL 1 5 00 27 Minimum Row Precharge Time tRP 18ns 48 28 Minimum Row Active to Row Activate delay tRRD 12ns 30 29 Minimum RAS to CAS Delay tRCD 18ns 48 30 Minimum active to Precharge time tRAS 42ns 2A 31 Module ROW density 256MB 40 32 Command Address Input Setup Time 0 8ns 80 33 Command Address Input Hold Time 0 8ns 80 34 Data Signal Input Setup Time 0 45ns 45 35 Data Signal Input Hold Time 0 45ns 45 36 61 Superset Information 00 Transcend Information Inc 10 184PIN DDR333 Unbuffered DIMM TS32M LD64V3 F5 256MB With 32Mx8 CL2 5 62 SPD Data Revision Code 00 63 Checksum for Bytes 0 62 20 64 71 Manufacturers JEDEC ID Transcend TF 4F 72 Manufacturing Location T 54 54 53 33 32 4D 4C 73 90 Manufacturers Part Number TS32MLD64V3F5 44 36 34 56 33 46 35 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific D
3. DQ1 50 VSS 96 VDDQ 142 CB6 05 DQSO 51 CB3 97 DMO 143 VDDQ 06 DQ2 52 BA1 98 DQ6 144 CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ33 101 NC 147 DQ37 10 NC 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4 12 DQ8 58 VSS 104 VDDQ 150 DQ38 13 DQ9 59 BAO 105 DQ12 151 DQ39 14 DQS1 60 DQ35 106 DQ13 152 VSS 15 VDDQ 61 DQ40 107 DM1 153 DQ44 16 CK1 62 VDDQ 108 VDD 154 RAS 17 CK1 63 IWE 109 DQ14 155 DQ45 18 VSS 64 DQ41 110 DQ15 156 VDDQ 19 DQ10 65 ICAS 111 CKE1 157 CS0 20 DQ11 66 VSS 112 VDDQ 158 CS1 21 CKEO 67 DQS5 113 NC 159 DM5 22 VDDQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 DQ48 118 A11 164 VDDQ 27 A9 73 DQ49 119 DM2 165 DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 ICK2 121 DQ22 167 NC 30 VDDQ 76 CK2 122 A8 168 VDD 31 DQ19 77 VDDQ 123 DQ23 169 DM6 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 A6 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDDQ 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 82 NC 128 VDDQ 174 DQ60 37 A4 83 DQ56 129 DM3 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 A1 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDDQ 182 SA1 45 CB1 91 SDA 137 CKO 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Please refer Block Diagram Transcend Information Inc 184PIN DDR33
4. MA Output High Current Half strength driver VOUT VTT 0 45V oR nA Output High Current Half strength driver iat 9 mA VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 20MHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF VID is the magnitude of the difference between the input level on CK and the input level on CK These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same Po Transcend Information Inc 5 184PIN DDR333 Unbuffered DIMM TS32MLD64V3F5 256MB With 32Mx8 CL2 5 DC CHARACTERISTICS 2 3 4 Recommended operating condition unless otherwise noted TA 0 to 70 C Operating current One bank Active Precharge tRC tRCmin tCK tCK
5. V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 C Power dissipation PD 12 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 3 2 7 V I O Supply voltage VDDQ 2 3 2 7 V I O Reference voltage VREF VDDQ 2 50mV VDDQ 2 50mV V 1 I O Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 36 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current lI 2 2 uA Output leakage current OZ 5 5 uA Output High Current Normal strength driver VOUT VTT 0 84V ee me Output Low Current Normal strength driver VOUT VTT 0 84V we 199
6. 3 Unbuffered DIMM TS32M LD64V3 F5 256MB With 32Mx8 CL2 5 Block Diagram Jy ZO NIS bia UWUR WOODARD a ROOOQRACO ISIRO SEE DOOD S9259 QQQQQQQO esms lt Q Q lt lt lt lt ESO ADTAL A FIFI ISS 4B BLISS BSS Sahay BESS DQS 6 Bay xe DOIG 1 Bai x 5020 3 Boo 31 DQ 23 55 pow g ROH Q36 ee AB pO DOS BR Be D 3 D 24 30 Serial PD A0 A12 BA0 amp 1 gt SDRAM U1 U8 ilies ee IRAS SDRAM U1 U8 oe ICAS o gt SDRAM U1 U8 AD A1 A2 WE o gt SDRAM U1 U8 sho ski sha CKE00o SDRAM U1 U8 CKOo gt ICS00 SDRAM U1 U8 F 1200 U4US DQn DQSn DMno 4i3 Connect to SDRAM ree zong L One 0 1uF Capacitors per b i bn ULU2 U3 Vss o each SDRAM QKL gt Vreto L One 0 1uF Capacitors per ICK2 0 i acs U6 U7 U8 gt Vss o each SDRAM N This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184PIN DDR333 Unbuffered DIMM TS32MLD64V3F5 256MB With 32Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6
7. EAAAAnoOMOeeeeeL CACCOCAC COCO o ive oun Transcend Information Inc TS32MLD64V3F5 184PIN DDR333 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Pin Identification Symbol Function A0 A12 BA0 BA1 Address input Dimensions Side Millimeters Inches 133 35 0 20 5 250 0 008 B 72 39 2 850 C 6 35 0 250 D 2 20 0 087 E 30 48 0 20 1 200 0 008 F 19 80 0 800 G 4 00 0 157 H 12 00 0 472 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output DQS0 DQS7 Data strobe input output CKO CKO CK1 CK1 Clock Input CK2 CK2 CKEO Clock Enable Input CSO Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DMO DM7 Data in Mask VDD 2 5 Voltage power supply VDDQ 2 5 Voltage Power Supply for DQS VREF Power Supply for Reference 2 5 Voltage Serial EEPROM VDDSPD Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection TS32MLD64V3F5 184PIN DDR333 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 VREF 47 DQS8 93 VSS 139 VSS 02 DQO 48 AO 94 DQ4 140 DM8 03 VSS 49 CB2 95 DQ5 141 A10 04
8. L V Address Column Address Auto Precharge Enable H A0 A9 4 5 Burst Stop H x L H H L X 6 Bank Selection V L Precharge H x L L H L X All Banks X H X X X Entry H L Active Power Down V V V X Exit L H X X X X H X X X Entry H L Precharge Power L H H H x Down Mode H x x x Exit L H L V V V DM H X X 7 H X X X No Operation Command H X X L H H H Note 1 OP Code Operand Code AO A12 amp BAO BA1 Program keys EMRS MRS 2 EMRS MRS can be issued only at all banks precharge state 3 Auto refresh functions are same as the CBR refresh of DRAM The automatic precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAO BA1 Bank select addresses If both BAO and BA are Low at read write row active and precharge bank A is selected If both SIEIS EREN BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAO and BA are ignored and all banks are selected During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst sto
9. TS32MLD64V3F5 184PIN DDR333 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Description The TS32MLD64V3F5 is a 32M x 64bits Double Data Rate SDRAM high density for DDR333 The TS32MLD64V3F5 consists of 8pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS32MLD64V3F5 is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply VDD 2 5V 0 2V VDDQ 2 5V 0 2V e Max clock Freq 166MHZ Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and CK e Burst Mode Operation e Auto and Self Refresh e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data input e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Placement o H gt F 4 E gt PCB 09 1862 OTIC CTO COO OAAARAAAAAAAAA
10. ata 128 255 Unused Storage Locations Undefined Transcend Information Inc 11
11. hown DQS going from High_Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly 4 For registered DIMMs tCL and tCH are gt 45 of the period including both the half period jitter tJIT HP of the PLL and the half period jitter due to crosstalk tUIT crosstalk on the DIMM Transcend Information Inc 8 184PIN DDR333 Unbuffered DIMM TS32MLD64V3F5 256MB With 32Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND CKEn 1 CKEn CS RAS CAS WE BAo 1 A1o AP Ao Ag A11 A12 Note Extended Register H X L L L L OP CODE 1 2 Mode Register Set Register Mode Register Set H x L E L L OP CODE 1 2 Auto Refresh H 3 H L L L H X Entry L 3 Refresh Self p L H H H 3 Refresh Exit L H X H X X X 3 Bank Active amp Row Addr H X L L H H V Row Address Auto Precharge Disable L Column 4 Read amp H x L H L H V Address Column Address Auto Precharge Enable H 4 5 A0 A9 i L Column 4 Write amp Auto Precharge Disable H x L H L
12. min 2 DQ DM and DQS inputs changing twice per clock cycle Address and control inputs changing once per clock cycle Operating current One bank Active Read Precharge Burst 2 IDD1 1120 tRC tRC min CL 2 5 tCK tCK min VIN VREF fro DQ DQS and DM Percharge power down standby current All banks idle 24 4 2 8 power down mode CKE lt VIL max tCK tCK min VIN VREF for DQ DQS and DM Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min tCK 166MHz for DDR333 Address and other control inputs changing once per clock cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max tCK tCK min VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax tCK tCK min DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle 0 0 0 0 0 4 Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK tCK min 50 of data changing at every burst lout 0 mA 1 480 1 400 Operating current Four bank operation Four bank interleaving with BL 4 IDD7 2 800 Refer to the following page for detailed test condition Operating current burst write Burst length 2 writes conti
13. nuous burst One bank active address and control inputs changing once per clock cycle CL 2 5 at tCK tCK min DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst Auto refresh current tRC tRFC min Self refresh current CKE lt 0 2V Note 1 Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor Transcend Information Inc 6 184PIN DDR333 Unbuffered DIMM TS32MLD64V3F5 256MB With 32Mx8 CL2 5 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Input High Logic 1 Voltage DQ DQS and DM signals VIH AC VREF 0 31 V Input Low Logic 0 Voltage DQ DQS and DM signals VIL AC VREF 0 31 V Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5 VDDQ 0 2 V Note 1 VIH max 4 2V The overshoot voltage duration is lt 3ns at VDD 2 ViL min 1 5V The undershoot voltage duration is lt 3ns at VSS 3 VID is the magnitude of the difference between the input level on CK and the input on CK 4 The Value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the DC level of the same AC OPERATING TEST CONDITIONS Vpp 2 5 Vopa 2 5 Ta 0 to 70 C Parameter Value Unit Note Input reference voltage for Cl
14. ock 0 5 VDDQ V Input signal maximum peak swing 1 5 V Input Levels VIH VIL VREF 0 31 VREF 0 31 V Input timing measurement reference level VREF V Output timing measurement reference level Vtt V Output load condition See Load Circuit VTT 0 5 VDDQ meio lt Output ZO 500hm pE VREF V 0 5 VDDQ CLoap 30pF Vi Output Load circuit INPUT OUTPUT CAPACITANCE voo 2 5V Vona 2 5V TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance AO A12 BAO BA1 RAS CAS WE CIN1 49 57 pF Input capacitance CKEO CIN2 42 50 pF Input capacitance CSO CIN3 42 50 pF Input capacitance CLKO CLK1 CLK2 CIN4 22 25 pF Data and DQS input output capacitance DQ0 DQ63 COUT 6 8 pF Input capacitance DMO DM7 CIN5 6 8 pF Transcend Information Inc 7 TS32MLD64V3F5 AC TIMING PARAMETERS amp SPECIFICATIONS These AC characteristics were tested on the Component 184PIN DDR333 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Parameter Symbol Min Max Unit Note Row cycle time tRC 60 ns Refresh row cycle time tRFC 72 ns Row active time tRAS 42 70K ns RAS to CAS delay tRCD 18 ns Row active to Row active delay tRP 18 ns Row active to Row active delay tRRD 12 ns Write recovery time tWR 15 ns Last data in to Read command tWTR 1 tCK Col
15. p command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Transcend Information Inc 9 TS32MLD64V3F5 184PIN DDR333 Unbuffered DIMM 256MB With 32Mx8 CL2 5 SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Byte No Function Described oe S aie Vendor Part Specification 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 0D 4 of Column Addresses on this Assembly 10 OA 5 of Module Rows on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 5V 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 6ns 60 10 DDR SDRAM Access Time from Clock at CL 2 5 0 7ns 70 11 DIMM configuration type non parity Parity ECC Non ECC 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width 00 Min Clock Delay for Back to x B Back Random Column Address RORE IER 9 16 Burst Lengths Supported 2 4 8 0E 17 of banks on each DDR SDRAM device 4 bank
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