Transcend 512MB SDRAM 144Pin SO-DIMM PC133 Unbuffer Non-ECC Memory
Contents
1. 12 BAO0 BA1 A0 A12 BA0 1H A0 A12 BA0 1H A0 A12 BA0 1H AO A12 BAO 1 20 063 H DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 ae IRAS IRAS IRAS CAS 32Mx8 H CAS 32Mx8 H CAS 32Mx8 H CAS 32Mx8 WE PL Tt we SDRAML we SDRAML we SDRam Uwe SDRAM CS0 HHHH cs ICS ICS CLKO eae CKEO e TI CLK1 A0 A12 BA0 1H A0 A12 BAO 1H AO A12 BA0 1 a DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 RAS RAS aul CAS 32Mx8 CAS 32Mx8 ICAS 32Mx8 ICAS 32Mx8 M we SDRAM we SDRAM Ive SDRAML ye SDRAM BEEN GS 0 12 A0 A12 BAO 1H AO A12 AO A12 BA0 1 5 0 7 7 L Tiras RAS RAS LT RAS cas 2 icas 2 Ll cAs 32Mx8 Ll cAs 32Mx8 hwe SDRAML wE SDRam 1 51 i s e EN f CKE1 bowl pavz 12 1 AO A12 BA0 1 AO A12 BA0 1 AO A12 BA0 1 DQ0 DQ7 200 007 DQ0 DQ7 DQ0 DQ7 RAS RAS i RAS CAS 32Mx8 H CAS 32Mx8 H CAS 32Mx8 H CAS 32 8 ANE SDRAM l yyg SDRAM SDRAM ICS ICS CLK gt O we SDRAM SDA This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at2. tRP min 20 ns 1 wee tRAS min 45 ns 1 R tive t PURUS SUR tRAS max 100 us Row cycle time Operation tRC min 65 ns 1 Last data in to new col address delay tCDL min 2 CLK 2 Last data in to Active delay tDAL min 2CLK 20ns Last data in to row precharge tRDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 Number of valid output data 2 ea 4 Note 1 cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 n case of row precharge interrupt auto precharge and read burst stop Transcend information Inc The minimum number of clock cycles is determined by dividing the minimum time required with clock TS64MSS64V6F 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 AC Characteristics 0 to 65 C 3 3V 0 3V Vss 0V Parameter Symbol Value Unit Note System clock cycle time 7 5 ns 1 CK high pulse width 2 5 ns 1 CK low pulse width 2 5 ns 1 Access time from CK tac 5 4 ns 1 2 Data out hold time 3 0 ns 1 2 CK to Data out low impedance Lz 0 0 ns 1 2 CK to Data out high impedance tHz 3 0 ns 1 Input setup time tas tcs tps tcEs 1 5 ns 1 CKE setup time for power down exit tcEsP 2 0 ns 1 Input hold time t H
3. H L X X Precharge Both Banks H X L L X H H X X X Clock Suspend or Entry E L X x Active Power Down L V V V Exit L H X X X X X H X X X Entry H L X Precharge Power L H X Down Mode H X X X Exit L H X L V V V DQM H X V X 7 H X X X No Operation Command H X X X L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatic precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 Bank select address If both BAo and BAt1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo and BAt1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA is ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the asso
4. M TS64MSS64V6F 512MB With 32Mx8 CL3 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name 01 Vss 49 DQ13 97 0922 02 Vss 50 DQ45 98 DQ54 03 DQO 51 DQ14 99 DQ23 04 DQ32 52 DQ46 100 0055 05 001 53 0015 101 Vcc 06 0033 54 0047 102 Vcc 07 002 55 Vss 103 08 0034 56 Vss 104 A7 09 003 57 CBO 105 A8 10 DQ35 58 CB4 106 11 Vcc 59 CB1 107 Vss 12 Vcc 60 CB5 108 Vss 13 DQ4 61 CLKO 109 AQ 14 DQ36 62 CKEO 110 BA1 15 DQ5 63 Vcc 111 10 16 DQ37 64 Vcc 112 A11 17 DQ6 65 RAS 113 Vcc 18 DQ38 66 CAS 114 Vcc 19 DQ7 67 115 DQM2 20 0039 68 CKE1 116 DQM6 21 Vss 69 CSO 117 DQM3 22 Vss 70 A12 118 DQM7 23 DQMO 71 CS1 119 Vss 24 DQM4 72 A13 120 Vss 25 73 NC 121 DQ24 26 DQM5 74 CLK1 122 09056 27 Vcc 75 Vss 123 DQ25 28 Vcc 76 Vss 124 DQ57 29 AO 77 CB2 125 DQ26 30 A3 78 CB6 126 0058 31 A1 79 CB3 127 0027 32 4 80 CB7 128 0059 33 2 81 Vcc 129 Vcc 34 5 82 Vcc 130 Vcc 35 Vss 83 DQ16 131 DQ28 36 Vss 84 DQ48 132 09060 37 008 85 0017 133 00929 38 0040 86 0049 134 0961 39 009 87 0018 135 0030 40 0041 88 0050 136 0962 41 0010 89 0019 137 0031 42 0042 90 0051 138 09063 43 0011 91 Vss 139 Vss 44 DQ43 92 Vss 140 Vss 45 Vcc 93 0020 141 SDA 46 Vcc 94 DQ52 142 SCL 47 0012 95 0021 143 Vcc 48 0044 96 0053 144 Vcc Please refer Block Diagram Transcend information Inc TS64MSS64V6F Block Diagram 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3
5. TS64MSS64V6F 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 Description Module S O DIMM mounted 16 pieces of 256 Mbit SDRAM sealed in TSOP package and 1 piece of serial EEPROM 2 kbit for Presence Detect PD An outline of the products is 144 pin Zig Zag Dual tabs socket type compact and thin package Therefore they make high density mounting possible without surface mount technology They provide common data inputs and outputs Decoupling capacitors are mounted beside TSOP on the module board Note Do not push the cover or drop the modules in order to protect from mechanical defects which would be electrical defects Features e Performance Range PC 133 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Pin Identification Symbol Function A0 A12 BAO BA1 Address input DQ0 DQ63 Data Input Output CLKO CLK1 Clock Input CKEO CKE1 Clock Enable Input CS0 CS3 Chip Select Input RAS Row Address Strobe ICAS Column Address Strob
6. any time without prior notice Transcend information Inc TS64MSS64V6F ABSOLUTE MAXIMUM RATINGS 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 to 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 to 4 6 V Storage temperature TsTG 55 to 150 C Power dissipation PD 16 W Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V 2 Output low voltage VOL 0 4 V IOL 2mA Input leakage current liL 10 10 uA 3 output leakage current loL 10 10 uA Note 1 2 0V AC The overshoot voltage duration is lt 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Inp
7. ax tcc 96 Active Standby Current IccaN CKESViH min CS ViH min tcc 10ns 480 mA in non power down mode Input singals are changed one time during 20ns One Bank Active IccaNS CKE ViH min CLKxViL max tcc 400 Input signals are stable Operating Current Icc4 loL 0 mA mA 1 Bust Mode Page Burst 1 360 4Banks activated tccp 2CLKs Refresh Current Icc5 tRC2tRC min 1 920 mA 1 Self Refresh Current cce CKExO0 2V 80 mA Note DQ loading cap Module IDD was calculated on the basis of component IDD and can be differently measured according to Transcend information Inc TS64MSS64V6F AC OPERATING TEST CONDITIONS Vbo 3 3V 0 3V 0 to 65 C 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 3 3V Vttz1 4V Output gt Von DC 2 4V 2 Output Z0 50 Ohm Vor DC 0 4V lo 2mA THT TT TIT d Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 Ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time
8. ciated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc TS64MSS64V6F 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Singer Vendor Part Specification 0 Number of Bytes Written into Serial Memory 128bytes 80 1 Total Number of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on this Assembly 13 00 4 Number of Column Addresses this Assembly 10 5 Number of Module Banks on this Assembly 2 bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC Non parity 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width None 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 full 8F 17 Number of banks on
9. e Write Enable DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend information Inc TS64MSS64V6F 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 Dimension QODO00000100000 000000000000 DODO 00000000 0000 0 0 0 0 0 0 0 UU 0 0 1 11000000000000000001000001 0 0 1000000000000000000000000 0 TUTUTUTUUT TTUTUTUUTUUUUUT GOOD CO 0 TOTO 0 O_o ETE TET T T PCB 09 7265 Side Millimeters TOTO F gt lt 6 H Inches A d B 4 4 5 4 Y gt lt 67 60 2 661 32 80 1 291 23 20 0 913 4 60 0 181 3 30 0 130 4 00 0 157 20 00 0 787 50 50 1 988 1 00 0 100 0 039 0 004 Transcend information Inc 144PIN PC133 Unbuffered SO DIM
10. each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General PPE O ARIRE 0E R W Burst 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 1row of 256MB 40 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 Transcend information Inc 10 TS64MSS64V6F 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDCE2 02 63 Checksum for Bytes 0 62 C3 64 71 Manufacturers ID Code per JEP 108E Transcend TF AF 72 Manufacturing Location T 54 54 53 36 34 4D 53 73 90 Manufacturers Part Number TS64MSS64V 6F 53 36 34 56 36 46 20 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specif
11. ication Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 1 F6 128 Unused Storage Locations Open FF Transcend information Inc 11
12. tcH 0 8 ns 1 Ref Active to Ref Active command period tRC 70 0 ns 1 Active to precharge command period tRas min 45 0 ns 1 Active command to column command same bank tRCD 20 0 ns 1 Precharge to active command period tRP 20 0 ns 1 Write recovery or data in to precharge lead time tDPL 15 0 ns 1 Active a to Active b command period tRRD 15 0 ns 1 Transition time rise and fall tr min 1 0 ns Refresh period REF max 64 0 ms Note 1 AC measurement assumes tT 1ns Reference level for timing of input signals is 1 5V 2 Access time is measured at 1 5V Load condition is CL 50 pF Transcend information Inc 144PIN PC133 Unbuffered SO DIMM TS64MSS64V6F 512MB With 32Mx8 CL3 SIMPLIFIED TRUTH TABLE COMMAND 1 CS RAS CAS DQM BAo 1 eura Note Register Mode Register Set H X L L L L X OP CODE 1 2 Auto Refresh H H L L L H x 3 Entry L 3 Refresh Self L H H H 3 Refresh i efres Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Address Read amp Auto Precharge Disable L Column 4 H X L H L H X V Address Column Address Auto Precharge Enable H 4 5 Auto Precharge Disable L Column 4 Write amp H X L H L L X V Address Column Address Auto Precharge Enable H c 4 5 Burst Stop H X L H H L X 6 Bank Selection V L
13. ut leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 Dout is disabled OV lt VouT lt VDDQ CAPACITANCE Vpp 3 3V 0 3V TA 0 C 70 C Parameter Symbol Min Max Unit Input capacitance Ao A12 BAo BA1 CIN1 80 100 pF Input capacitance RAS CAS WE CIN2 80 100 pF Input capacitance CKEO CKE1 CIN3 50 60 pF Input capacitance CLKO CLK1 CIN4 40 45 Input capacitance CSO CS1 CIN5 25 35 pF Input capacitance DQM0 DQM 7 CIN6 15 20 pF Data input output capacitance DQ0 DQ63 COUT1 10 15 pF Transcend information Inc TS64MSS64V6F 144PIN PC133 Unbuffered SO DIMM 512MB With 32Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Typ Unit Note Operating Current Icc1 Burst Length 1 1 200 mA 1 One Bank Active tRC2tRC min loL OmA Precharge Standby Current cc2P CKEsViL max tcc 10ns 32 mA M power gown mede lccaPS CKE amp CLK lt VIL max 32 Precharge Standby Current cc2N CKE ViH min CS ViH min tcc 10ns 256 mA in non power down mode Input signals are changed one time during 20ns Icc2NS gt CLKxViL max tcc lt 224 Input signals are stable Active Standby Current IccaP lt tcc 10ns 96 mA TOO IccaPS CKE amp CLKsViLm
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