Transcend 128MB SDRAM PC133 Unbuffer Non-ECC Memory
Contents
1. V IOH 2mA Output low voltage VOL 0 4 V IOL 2mA Input leakage current ILI 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt Vin lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri state output CAPACITANCE Voo 3 3V Ta 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance AO A12 BAO BA1 CADD 15 25 pF Input capacitance RAS CAS WE CIN 15 25 pF Input capacitance CKE CCKE 15 25 pF Input capacitance CLK CCLK 10 13 pF Input capacitance CS Ccs 10 15 pF Input capacitance DQM0 DQM7 CDQM 8 10 pF Data input output capacitance DQ0 DQ63 COUT 9 12 pF DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Transcend information Inc 168PIN PC133 Unbuffered DIMM TS1 6M LS64V6G 128MB with 16Mx16 CL3 Parameter Symbol Test Condition Value Unit Note Operating Current Burst Length 1 Icc1 One Bank Active tRC gt tRC min OO i ae 1 IOL 0MA Precharge Standby Current IGA PRES HAME EINS 8 mA in power down mode Icc2PS CKE amp CLK lt ViL max tcc lt 8 Icc2N CKE ViH min CS gt VIH min tcc 10ns 80 Precharge Standby Current Input signals are changed one time during 20ns mA in non power2. 20 19 80 15 80 l 1 27 0 10 I O n m o O w Transcend information Inc Inches 5 250 0 016 2 585 0 925 0 350 0 118 0 875 0 008 0 788 0 622 0 050 0 004 168PIN PC133 Unbuffered DIMM 128MB with 16Mx16 CL3 Pin Identification Symbol Function A0 A12 Address inputs BAO BA1 Select Bank DQ0 DQ63 Data inputs outputs CLKO CLK2 Clock Input CKEO Clock Enable Input CSO CS2 Chip Select Input IRAS Row address strobe ICAS Column address strobe IWE Write Enable DQM0 7 DQM Vcc Power Supply Vss Ground SDA Serial Address Data I O SA0 2 Address in EEPROM WP Write protection SCL Serial Clock NC No Connection TS1 6M LS64V6G 168PIN PC133 Unbuffered DIMM 128MB with 16Mx16 CL3 Block Diagram A0 A12 BA0 BA1 DQ0 DQ63 RAS ICAS IWE CSO CLEO CKEO ICS2 CLE2 Serial SCL SDA WP This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 168PIN PC133 Unbuffered DIMM TS1 6M LS64V6G 128MB with 16Mx16 CL3 Pinouts Pin Name No No Name No Name Vss 43 85 Vss 127 Vss DQO 44 86 DQ32 128 CKEO DQ1 DQ33 129 CS3
3. DQ2 DQ34 130 DQM6 DQ3 DQ35 131 DQM7 Vcc 132 A13 DQ4 DQ36 133 DQ37 134 DQ38 135 DQ39 136 DQ40 137 Vss 138 DQ41 139 DQ42 140 DQ43 141 DQ44 142 DQ45 143 Vcc 144 DQ46 145 DQ47 146 CB4 147 CB5 148 Vss 149 NC 150 NC 151 Vcc 152 ICAS 153 DQM4 154 DQM5 155 CS1 156 157 158 159 160 161 162 163 A10 AP 80 164 BA 165 Vcc 166 Vcc 167 CLKO 168 Please refer Block Diagram Transcend information Inc TS16MLS64V6G ABSOLUTE MAXIMUM RATINGS 168PIN PC133 Unbuffered DIMM 128MB with 16Mx16 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 4 W Short circuit current Los 50 mA Operating Temperature TA 0 70 C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4
4. down mode licc2NS CKE ViH min CLK lt ViL max tcc 40 Input signals are stable Active Standby Current Icc3P CKE lt ViL max tcc 10ns 24 TA in power down mode Icc3PS CKE amp CLK lt ViL max tcc lt 24 Icc3N a Active Standby Current ec eam ae 120 in non power down mode nput signals are changea one time quring ns mA Rene PANE AGHVS lcc3NS OkE gt ViHmin CLK lt ViL max tcc 100 Input signals are stable Operating Current Icc4 oe SIM mA 1 Bari iode Page Burst 560 tccp 2CLKs mA 2 Refresh current Icc5 tRC lt tRc min 800 Self Refresh Current Icc6 CKE lt 0 2V 12 mA Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap Transcend information Inc 6 TS16MLS64V6G 168PIN PC133 Unbuffered DIMM 128MB with 16Mx16 CL3 AC OPERATING TEST CONDITIONS Vpp 3 3V 0 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 1200 Ohm Vox DC 2 4V loH 2MA Vor DC 0 4V loL 2mMA 50PF 870 Ohm 71117 Fig 1 DC Output Load Circuit 50 Ohm Output _Z0 50 Ohm 50pPF Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwi
5. M Device Attributes General Prec All Auto Prec R W Burst OE 23 SDRAM Cycle Time 2 highest CL 10ns AO 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 Transcend information Inc 1 TS16MLS64V6G 168PIN PC133 Unbuffered DIMM 128MB with 16Mx16 CL3 62 SPD Data Revision Code JEDEC Ver 2 02 63 Checksum for Bytes 0 62 AB AB 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend TF 4F 72 Manufacturing Location T 54 54 53 31 36 4D 4C 73 90 Manufacturers Part Number TS16MLS64V6G 53 36 34 56 36 47 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 28 amp 3 Clock 0 2 A6 128 Unused Storage Locations Open FF Transcend infor
6. Power Down Mode Exit i F H x x x x xX L V V V DQM H X V X 7 bie H xX xX X No Operation Comman H x x x L H H H V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A12 BA0 BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and all banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going ed
7. TS16MLS64V6G 168PIN PC133 Unbuffered DIMM 128MB with 16Mx16 CL3 Description The TS16MLS64V6G is a 16M bit x 64 Synchronous Dynamic RAM high density memory module The TS16MLS64V6G consists of 4 piece of CMOS 16Mx16bits Synchronous DRAMs in TFBGA 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS16MLS64V6G is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth applications high performance memory system Features e ROHS compliant products e Performance Range PC133 e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Scramble Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Placement O PCB 09 2410 Transcend information Inc TS16MLS64V6G Dimensions Side Millimeters 133 35 0 40 65 67 23 49 8 89 3 00 22 225 0
8. ged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 TS16MLS64V6G Serial Presence Detect Specification 168PIN PC133 Unbuffered DIMM 128MB with 16Mx16 CL3 Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly A0 A12 oD 4 of Column Addresses on this Assembly A0 A8 09 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary SDRAM Width X16 10 14 Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 amp 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRA
9. mation Inc 1
10. s 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output in Hi Z tSHZ 5 4 ns Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC133 Unbuffered DIMM TS1 6M LS64V6G 128MB with 16Mx16 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn cs RAS CAS WE DQM BAo1 Aiw AP ANAD Note Register Mode Register Set H x L L L L x OP CODE 1 2 Auto Refresh H 3 Entry H L L L H xX xX 3 Refresh Self ese Exit L fie oes e E x x 3 H 3 Bank Active amp Row Addr H X L L H H X V Row Address Read amp Auto Precharge Disable L Column 4 Address Column Address Auto Precharge Enable H X L x H x y H Ao As 4 5 Write amp Auto Precharge Disable L Column 4 Address Column Address Auto Precharge Enable H X E H a x y H Ao As 4 5 Burst Stop H xX L H H L xX xX 6 Bank Selection V L Precharge Bothi Banke H X L L H L x x H X Clock Suspend or 5 x x X Entr H L X Active Power y L V V V y Down Exit L H x x x x X H xX xX xX Entry H L xX L H H H Precharge
11. se noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time iS ania 1 1 tRAS max 100 us Row cycle time Operation tRC min 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tccD min 1 CLK 3 Number of valid output data CAS lately es 5 CAS latency 2 ca 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 168PIN PC133 Unbuffered DIMM TS1 6M LS64V6G 128MB with 16Mx16 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Unit Note Min Max CLK cycle time tcc 7 5 1000 ns 1 GEK to valid tsac 5 4 ns 1 2 output delay Output data hold time oH i ne e CLK high pulse width tCH 2 5 ns 3 CLK low pulse width tCL 2 5 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 n
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