Transcend 256MB SDRAM 144Pin SO-DIMM PC100 Unbuffer Non-ECC Memory
Contents
1. Parameter Symbol Min Typ Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 2 Input low voltage VIL 0 3 0 0 8 V 1 2 Output high voltage VOH 24 V 2mA Output low voltage VOL 0 4 V IOL 2mA Notez 1 All voltages are referenced to Vss 2 VIH may overshoot to VDD 2 0V for pulse width of 4ns with 3 3V VIL may undershoot to 2 0V for pulse width 4 O0ns with 3 3V Pulse width measured at 50 points with amplitude measured peak to DC reference CAPACITANCE VDD 3 3V TA 23 C f 1MHz VREF 1 4V 200mV Parameter Symbol Min Max Unit Input capacitance 0 11 BAO BA1 CIN1 45 85 pF Input capacitance RAS CAS WE CIN2 45 85 pF Input capacitance CKEO CKE1 CIN3 25 45 pF Input capacitance CLKO CINA 25 21 pF Input capacitance CS0 CS1 CIN5 25 25 pF Input capacitance DOMO DOM7 CIN6 10 15 pF Data input output capacitance 000 0063 COUT 13 18 pF Transcend information Inc 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8D2 256MB With 16Mx8 CL2 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current Burst Length 1 tRC2tRC min One Bank Active IOL OmA in power down mode ICC2PS CKE amp CKE2VIH min CS2VIH min tCC 10ns Input signals are changed one time during 20ns ICC2N Precharge Stan2. TS32MSS64V8D2 256MB With 16Mx8 CL2 Block Diagram 0 11 BAO BAT MAO A11 80 1 MA0 A11 8A0 1 HA0 A11 8A0 1 HAO A11 BAO il DQ0 DQ7 i DQ0 DQ7 DQ0 DQ7 i DQ0 DQ7 IRAS IRAS IRAS IRAS ICAS 1 6 Ll cas temxs Llicas 16Mx8 Licas 16Mx8 WE we SDRAM SDRAM SDRAM WWE SDRAM 50 LLL Iles ics ics cik 2 Uee S8 Hee 2 8 DQMO DOM2 gt AO ATT BAO 1 MA0 A11 AO 1 HAO A11 BA0 1 HAO A11 BA0 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 I ras Ras Hras Hras ot ICAS 16Mx8 ICAS 16Mx8 ICAS 16Mx8 ICAS 16Mx8 SDRAM We SDRAM We SDRAM We SDRAM CLKO2 ICS ICS ICS ICS 3 cke g 2 DQM4 DQM5 DQM6 7 AO A11 BA0 1 HAO AT1 BA0 1 MA0 A11 8A0 1 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 DQ0 DQ7 LT ras L RAS Hras Hras cas 1emxs Ll cas temxs Llicas 16Mx8 Licas 16Mx8 SDRAM SDRAM SDRAM SDRAM T 1 i WE WE i cuo ICS ICS ICS ck Lick s CKE1 ce 98 Uee 2 2 2 DQMO DOM2 A0 A11 BA0 1 MAO A11 BA0 1 M A0 A11 BA0 1 M A0 A11 BAO 1 DQo bQ7 HDqo Da 7 IRAS L RAS Hras Hras ICAS 16Mx8 U NE SDRAM ICS ICS ICS Lak 9 DQM4 DQM5 DQM6 7 PLL EEP
3. 3 Assumed input rise and fall time tr amp tf 1ns if tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend information Inc 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8D2 256MB With 16Mx8 CL2 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn IRAS CAS DQ BAo 1 A10 AP 1 Ao A9 Note _ s Auto Precharge Disable NEL L H L X V Auto Precharge Enable H Address H 40 A8 Eme am TTC c TR L Precharge Benk Selection _____ Precharge Auto Precharge Disable L Column EE et s Auto Precharge Enable 0 8 X V L Both Banks Suspend or Active Power Down Mode V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 Bank select address If both BAo and are Low at read write row active and precharge bank A is selected If both BAo is Low and is High at read
4. 0 Ohm OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 2 RAS to CAS delay tRCD min Lp Row precharge time tRP min Row active time tRAS min Row cycle time tRC min EXEC Last data in to new col address delay tCDL min a lc Last data in to Active dela tDAL min 2CLK tRP Last data in to row precharge tRDL min CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 Number of valid output data 1 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8D2 256MB With 16Mx8 CL2 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module E 1 EA CLK cycle time tCC CLK to valid output delay Output data hold time 10H ns ICH ic iss CLK to output in Hi Z Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter
5. 108E Transcend 72 Manufacturing Location T 54 54 53 33 32 40 53 73 90 Manufacturers Part Number TS32MSS64V8D2 53 36 34 56 38 44 32 20 20 20 20 20 Transcend information Inc 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8D2 256MB With 16Mx8 CL2 91 92 Revision Code 0 93 94 Manufacturing Date By Manufactory Variable 95 98 Assembly Serial Number By Manufactory Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 64 127 Intel Specification CAS Latency Clock Signal Support CL 2 3 Clock 0 C6 128 Unused Storage Locations Open FF Transcend information Inc 10
6. Enable DQMO DOM7 DOM Vcc Power Supply Vss Ground SDA Serial Address Data SCL Serial Clock NC No Connection Dimensions Side Millimeters Inches A 67 60 0 20 2 661 0 008 B 32 80 1 291 C 23 20 0 913 D 4 60 0 181 E 3 30 0 130 F 4 00 0 157 G 20 00 0 787 H 50 50 0 20 1 988 0 008 1 00 0 10 0 040 0 004 Transcend information Inc TS32MSS64V8D2 TUTTTTUUUUUTUTTTUTUUUTUTUUU DIODDD0 0000000090000 0000000 Dimension TUUTUTUTUUUUTUUUUUUUUUUUUUUUU TOUT TOTO nnnnnnannnnnnn nnnnnnnnnnni TITTTTTTUTTUT TT TUUT TIT TTUU Pinouts Pin Name Please refer Block Diagram Name 144PIN PC100 Unbuffered SO DIMM 256MB With 16Mx8 CL2 pnnnnnannnnnonnnnnonnnnnn Dn nnnnnnnnnnnnnnnnnnmnnnan rn TUUTTUUUUUUUUTUTUUUUUUUUUT TTTUUTUTUUUTIUUUUUUUUTIUUUU ninnnn nnnnnnnnnnnnnnnnnnn nnnnnnnnnnnnnnnnnnnnnnnnnnn o TIUTETTTTTTTTTTTTETITUTUTU TITUUTTTTUTTTEUTTTUTTUTUTTT TUUTUUUUTUUUUUTUTUUUUUUUTUUUUT TUUTTUUTUUTTTUUUUUUUTUUUU i i TUUUTIUUUUUUUUTUTUUUUUUUUUU T Pin Name Pin Name Transcend information Inc 144PIN PC100 Unbuffered SO DIMM
7. ROM CLKO scL JscL sDA SDA CLKO01 CLKO3 CLK04 0 1 A2 ft This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8D2 256MB With 16Mx8 CL2 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 16 Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 859 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note 1 Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded 2 Functional operation should be restricted to recommended operating condition 3 Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV 0 to 70 C
8. TS32MSS64V8D2 144PIN PC100 Unbuffered SO DIMM 256MB With 16Mx8 CL2 Description The TS32MSS64V8D2 is a 32M bit x 64 Synchronous Dynamic high density memory modules The TS32MSS64V8D2 consists of 16 pieces of CMOS 4Mx8bitsx4banks Synchronous DRAMs in TSOP II 400mil packages a 2048 bits serial EEPROM and a PLL on 144 pin printed circuit board The TS32MSS64V8D2 is a Dual In Line Memory Module and is intended for mounting into 144 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Burst Mode Operation e Auto and Self Refresh e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Scramble Sequential amp Interleave e All inputs are sampled at the positive going edge of the system clock Pin Identification Symbol Function 0 11 Address inputs BAO BA1 Banks Select D0 D63 Data inputs outputs CLKO Clock Input CKEO CKE1 Clock Enable Input CS0 CS1 Chip Select Input RAS Row address strobe ICAS Column address strobe Write
9. dby Current in non power down mode gt CLK lt VIL max ICC2NS Input signals stable Active Standby Current ICC3P CKExVIL max tCC 10ns 8 in power down mode ICC3PS amp CLK lt VIL max tCC ICC3N gt CS VIH min tCC 10ns neve Input signals are changed one time during 20ns in non power down mode One Bank Active 480 ICC3NS CKE VIH min CLKxVIL max Input signals are stable Operating Current ee H dd Burst Mode age Burs ib tccD 2CLKs Refresh current eas e Self Refresh Current 6 CKE lt 0 2V 2 ma Note 1 Measured with outputs open 2 Refresh period is 64ms 3 Unless otherwise noticed input swing level is CMOS VIH VIL VDDQ VSSQ 400 Transcend information Inc 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8D2 256MB With 16Mx8 CL2 AC OPERATING TEST CONDITIONS VDD 3 350 3V TA 0 to 70 C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 o om 1200 Ohm 50 Ohm gt Vox DC 2 4V 2 Output 4 20 50 Ohm Vo DC 0 4V lo 22mA 50 ZZ 7T 7 7 UT 2 Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit 87
10. e Banks on this Assembly 2 banks 02 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM Cycle Time highest CAS latency 10ns 0 10 SDRAM Access from Clock highest CL 6ns 60 11 DIMM configuration type non parity ECC DIMM 00 12 Refresh Rate Type 15 625us Self Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width 0 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 2 3 06 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 6 Prec All Auto Prec 22 SDRAM Device Attributes General R W Burst 23 SDRAM Time 2 highest CL 10ns 0 24 SDRAM Access from Clock 2 highest CL 6ns 60 25 SDRAM Cycle Time 3 highest CL 00 26 SDRAM Access from Clock 3 highest CL 00 27 Minimum Row Time 20ns 14 28 Minimum Row Active to Row Activate 20ns 14 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 50ns 32 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 20ns 20 33 Command Address Hold Time 10ns 10 34 Data Signal Setup Time 20ns 20 35 Data Signal Hold Time 10ns 10 36 61 Superset Information 00 62 SPD Data Revision Code INTEL 12 63 Checksum for Bytes 0 62 17 17 64 71 Manufacturers JEDEC ID code per JEP
11. write row active and precharge bank B is selected If both BAo is High and is Low at read write row active and precharge bank C is selected If both BAo and are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and are ignored and all banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 144PIN PC100 Unbuffered SO DIMM TS32MSS64V8D2 256MB With 16Mx8 CL2 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Vendor Part Specification 0 Number of Bytes Written into Serial Memory 128bytes 80 1 Total Number of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on this Assembly 12 0C 4 Number of Column Addresses on this Assembly 10 OA 5 Number of Modul
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