Transcend 512MB SDRAM PC100 Unbuffer Non-ECC Memory
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1. 50pF 870 Ohm e 7 11 VIMI T T Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Symbol Value Row active to row active delay romm 2 ns IRAS to CAS delay tRCD min Row precharge time tRP min tRAS min Row active time tRAS max Row cycle time tRC min Last data in to row precharge tRDL min Last data in to burst stop tBDL min Col address to col address delay tCCD min Number of valid output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Transcend information Inc 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module 0 NS Ns NS NS NS NS sz eo n Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf2. Input capacitance CKEO CKE1 Input capacitance CLKO CLK3 Input capacitance CSO CS3 Input capacitance DQM0 DQM 7 Data input output capacitance DQ0 DQ63 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Symbol Test Condition Value Typ Unit Note Operating Current Roa One Bank Active F 1 120 hk loL OmA in power down mode Icc2PS CKE 8 CLK lt VIL max tcc lt oon srez poe HMI ene 256 Input signals are changed one time during 20ns CKE gt VIH min CLK lt VIL max tcC lt Input signals are stable Precharge Standby Current in non power down mode p cc2NS Active Standby Current Icc3P CKE lt VIL max tcc 10ns in power down mode IccaPS CKE amp CLK lt ViL max tec icca SKEZVIH MIN CS2ViH min tec 10ns Active Standby Current Input signals are changed one time during 20ns in non power down mode One Bank Active pome prevri CLK lt VIL max tCC lt ZNE Input signals are stable lOL 0 mA Operating Current eca Page Burst 1 160 mA 1 Bust Mode tccp 2CLKs Refresh Current tRC gt tRC min 1 840 Note 1 Measured with outputs open 2 Refresh period is 64ms Transcend information Inc 6 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 AC OPERATING TEST CONDITIONS vpo 3 3V 0 3V Ta 0 to 70 C 3 3V Vtt 1 4V 1200 Ohm 50 Ohm Vou DC 2 4V lon 2mA Output Vor DC 0 4V lo 2mA
3. 2 1 ns should be added to the parameter Transcend information Inc 8 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 SIMPLIFIED TRUTH TABLE V Valid X lt Don t Care H Logic High L lt Logic Low comano orent oren rs mas as me pom sma mone A A nore poose teers ES ovce RU zaj ena a apa k re ae om tt Refresh ze NE K a m am am m A NA m L Address Column Address Auto Precharge Enable oH Ao As 5 ie Precharge Disable L Column Write amp T a Column Address auto Auto Precharge Enable Enable Ao A9 4 5 Burst Stop Read amp Auto Precharge Disable Auto Precharge Disable Disable SOE e Column Burst Step aeei Pp Bracharae Bank Selection ss Selection g Both Banks Clock Suspend or Precharge Power Down Mode Note 1 OP Code Operand Code Ao A12 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA are Low at read write row active and precharge bank A is selected If both BAo is Low and BA is High at read write row active and precharge bank B is selected If both BAo is High and BA
4. CL 60ns of QS SDRAM Cycle Time 3 highest CL a ee SDRAM Access from Clock 3 highest CL pf V Vendor Part O NO NM NM BD Transcend information Inc 10 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 5661 Superset nomatlan 7 T2 1 7 o 63 Checksum for Bytes0 62 A 73 90 Manufacturers Part Number TS64MLS64V8F2 91 92 RevisionCode S o S 0 99 125 Manufacturer Specific Data o o ooo doo 0 126 __ Intel Specification Frequency Transcend information Inc 11
5. is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA1 are ignored and both banks are selected 5 During burst read or write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend information Inc 9 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 SERIAL PRESENCE DETECT SPECIFICATION Serial Presence Detect Saas 3 it of Row Addresses on this 13 s ovo ere ons osna ben fp 6 pala Wan ot nis Assemoly IS r par wis contusion go e Notage ierace StendardoftisAssomby wmo o 9 SDRAM Cyele Te highest CAS atero wos m 10 DRAM access fom Ciok oreste eos 6o DIMM configuration type non parity ECC Nonpariy go o Primay SDRAM Web x o 14 EworChecking SDRAM Wii Nene ooo Ce easttaeney SiS 21 SORAM moau anres Non Butler O O9 23 SDRAM Cycle Time 2 highest CL SDRAM Access from Clock 2 highest
6. technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend information Inc 4 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 ABSOLUTE MAXIMUM RATINGS Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 Dout is disabled OV lt VOUT lt VDDQ Transcend information Inc 5 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 CAPACITANCE VDD 3 3V TA 20 C f 1MHz VREF 1 4V 200 mV Parameter Input capacitance Ao A12 BAo BA1 Input capacitance RAS CAS WE
7. 5 0 40 65 67 23 49 8 89 3 00 29 21 0 20 19 80 15 80 1 27 0 10 I O T M JU JO O Refer Placement Transcend information Inc Inches 5 250 0 016 2 585 0 925 0 350 0 118 1 150 0 008 0 788 0 622 0 050 0 004 Pin Identification Symbol A0 A12 BAO BA1 DQ0 DQ63 CLKO CLK3 CKEO CKE1 CS0 CS3 RAS ICAS ANE DOMO DOM 7 SA0 SA2 SCL SDA Vcc Vss NC Function Address input Data Input Output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data DQ Mask Address in EEPROM serial PD Clock Serial PD Add Data input output 3 3 Voltage Power Supply Ground No Connection 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 Pinouts Pin Pin i Pin Pin Name No Name No Name No Name Please refer Block Diagram Transcend information Inc 3 168PIN PC100 Unbuffered DIMM TS64M LS64V8 F2 512MB With 32MX8 CL2 Block Diagram A0 A12 A0 A12 A0 A12 BAO BA1 BAO BA1 BAO BA1 DQ0 DQ63 ri W l DQ0 DQ7 DQ0 DQ7 RAS a E A IRAS gova IRAS eee ICAS ICAS SDRAM ICAS SDRAM ICAS SDRAM k HUJE ae ITI SIT CS2 It di m Le ae a CLK2 AO A12 i i BAO BA1 BAO BA1 a Et DQ0 DQ7 DQ0 DQ7 aul IRAS vx IRAS 30ux8 ICAS SDRAM ICAS SDRAM ce a na ICS1 Pit NM ICS s a A Z A ww LEE ICAS SDRAM IWE ICS CKE CLK1 CLK3 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This
8. TS64MLS64V8F2 168PIN PC100 Unbuffered DIMM 512MB With 32MX8 CL2 Description The TS64MLS64V8F2 is a 64M bit x 64 Synchronous Dynamic RAM high density for PC 100 The TS64MLS64V8F2 consists of 16pcs CMOS 32Mx8 bits synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS64MLS64V8F2 is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Performance Range PC 100 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Placement PCB 09 7308 Transcend information Inc TS64MLS64V8F2 168PIN PC100 Unbuffered DIMM 512MB With 32MX8 CL2 Dimensions Side Millimeters A 133 3
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