Transcend 1GB DDR333 Unbuffer Non-ECC Memory
Contents
1. Parameter Symbol Min Max Unit Note Row cycle time tRC 60 ns Refresh row cycle time tRFC 72 ns Row active time tRAS 42 70K ns RAS to CAS delay tRCD 18 ns Row active to Row active delay tRP 18 ns Row active to Row active delay tRRD 12 ns Write recovery time tWR 15 ns Last data in to Read command tWTR 1 tCK Col Address to Col Address delay tCCD 1 tCK Clock cycle time tCK 6 12 ns Clock high level width tCH 0 45 0 55 tCK Clock low level width tCL 0 45 0 55 tCK DQS out access time from CK CK tDQSCK 0 6 0 6 ns Output data access time from CK CK tAC 0 7 0 7 ns Data strobe edge to output data edge tDQSQ 0 45 ns Read Preamble tRPRE 0 9 1 1 tCK Read Postamble tRPST 0 4 0 6 tCK CK to valid DQS in tDQSS 0 75 1 25 tCK DQS in setup time tWPRES 0 ns 2 DQS in hold time tWPREH 0 25 tCK DQS falling edge to CK rising setup time tDSS 0 2 tCK DQS falling edge from CK rising hold time tDSH 0 2 tCK DQS in high level width tDQSH 0 35 tCK DQS in low level width tDQSL 0 35 tCK DQS in cycle time tDSC 0 9 1 1 tCK Address and Control input setup time tIS 0 75 ns Address and Control input hold time tlH 0 75 ns Data out high impedance time from CK CK tHZ 0 7 0 75 ns Data out low impedance time from CK CK tLZ 0 7 0 75 ns Mode register set cycle time tMRD 12 ns DQ amp DM setup time to DQS tDS 0 45 ns DQ amp DM hold time to DQS tDH 0 45 ns DQ amp DM input pulse width tDIPW 2 2 ns Pow2. ive lt gt PCB 09 1675 Transcend Information Inc TS7128MLD64V3E 184 PIN DDR333 Unbuffered DIMM 1GB With 64Mx4 CL2 5 Pin Identification Symbol Function AO A12 BAO BA1 Address input Dimensions Side Millimeters Inches 133 35 0 20 5 250 0 008 B 72 39 2 850 C 6 35 0 250000 D 2 20 0 0870 E 30 48 0 20 1 200 0 008 F 19 80 0 779 G 4 00 0 157 H 12 00 0 472 1 27 0 10 0 050 0 004 Refer Placement Transcend Information Inc DQ0 DQ63 Data Input Output DQS0 DQS8 Data strobe input output CKO CKO CK1 CK1 Clock Input CK2 CK2 CKEO CKE1 Clock Enable Input CSO CS1 Chip Select Input RAS Row Address Strobe ICAS Column Address Strobe IWE Write Enable DM0 DM8 Data in Mask VDD 2 5 Voltage power supply VDDQ 2 5 Voltage Power Supply for DQS VREF Power Supply for Reference 2 5 Voltage Serial EEPROM VDDSPD Power Supply SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output VSS Ground NC No Connection TS7128MLD64V3E 184 PIN DDR333 Unbuffered DIMM 1GB With 64Mx4 CL2 5 Pinouts Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name 01 VREF 47 DQS8 93 VSS 139 VSS 02 DQO 48 AO 94 DQ4 140 DM8 03 VSS 49 CB2 95 DQ5 141 A10 04 pal 50 VSS 96 VDDQ 142 CB6 05 paso 51 CB3 97 DMO 143
3. 12 Refresh Rate Type 7 8us Self Refresh 82 13 Primary DDR SDRAM Width X8 08 14 Error Checking DDR SDRAM Width 00 15 Min Clock Delay for Back to Back Random Cain Address KURNA os 16 Burst Lengths Supported 2 4 8 OE 17 of banks on each DDR SDRAM device 4 bank 04 18 CAS Latency supported 2 2 5 oC 19 CS Latency 0 CLK 01 20 WE Latency 1 CLK 02 Registered address amp 21 DDR SDRAM Module Attributes control inputs and 20 on card DLL i 0 2V voltage 22 DDR SDRAM Device Attributes General 00 tolerance 23 DDR SDRAM Cycle Time CL 2 0 7 5ns 75 24 DDR SDRAM Access from Clock CL 2 0 0 7ns 70 25 DDR SDRAM Cycle Time CL 1 5 00 26 DDR SDRAM Access from Clock CL 1 5 00 27 Minimum Row Precharge Time tRP 18ns 48 28 Minimum Row Active to Row Activate delay tRRD 12ns 30 29 Minimum RAS to CAS Delay tRCD 18ns 48 30 Minimum active to Precharge time tRAS 42ns 2A 31 Module ROW density 512MB 80 32 Command Address Input Setup Time 0 8ns 80 Transcend Information Inc 10 TS7128MLD64V3E 184 PIN DDR333 Unbuffered DIMM 1GB With 64Mx4 CL2 5 33 Command Address Input Hold Time 0 8ns 80 34 Data Signal Input Setup Time 0 45ns 45 35 Data Signal Input Hold Time 0 45ns 45 36 61 Superset Information 00 62 SPD Data Revision Code 00 63 Checksum for Bytes 0 62 62 64 71 Manufacturers JEDEC ID Transcend 7F 4F 72 Manufacturing Location T 54 54 53 31
4. 2 2 uA Output leakage current lOZ 5 5 uA Output High Current Normal strength driver VOUT VTT 0 84V loH R mA Output Low Current Normal strength driver VOUT VTT 0 84V Dp ki ma Output High Current Half strength driver VOUT VTT 0 45V om ie Output High Current Half strength driver tap 9 mA VOUT VTT 0 45V Note 1 Includes 25mV margin for DC offset on VREF and a combined total of 50mV margin for all AC noise and DC offset on VREF bandwidth limited to 2OMHz The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF both of which may result in VREF noise VREF should be de coupled with an inductance of lt 3nH 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF VID is the magnitude of the difference between the input level on CK and the input level on CK 4 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ 5 The value of Vix is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same a Transcend Information Inc 5 184 PIN DDR333 Unbuffered DIMM TS7128MLD64V3E 1GB With 64Mx
5. 32 38 4D 73 90 Manufacturers Part Number TS128MLD64V3E 4C 44 36 34 56 33 45 20 20 20 20 20 91 92 Revision Code 93 94 Manufacturing Date By Manufacturer Variable 95 98 _ Assembly Serial Number By Manufacturer Variable 99 127 Manufacturer Specific Data 128 255 Unused Storage Locations Undefined Transcend Information Inc 11
6. are ignored and all banks are selected During burst write with auto precharge new read write command cannot be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in is masked at the both edges Write DM latency is 0 This combination is not defined for any function which means No Operation NOP in DDR SDRAM Transcend Information Inc 9 TS7128MLD64V3E 184 PIN DDR333 Unbuffered DIMM 1GB With 64Mx4 CL2 5 Serial Presence Detect Specification Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type DDR SDRAM 07 3 of Row Addresses on this Assembly 13 oD 4 of Column Addresses on this Assembly 11 0B 5 of Module Rows on this Assembly 2 bank 02 6 Data Width of this Assembly 64bits 40 7 Data Width of this Assembly 0 00 8 VDDQ and Interface Standard of this Assembly SSTL 2 5V 04 9 DDR SDRAM Cycle Time at CAS Latency 2 5 6 0ns 60 10 DDR SDRAM Access Time from Clock at CL 2 5 0 7ns 70 11 DIMM configuration type non parity Parity ECC Non ECC 00
7. level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST CONDITIONS VDD 2 5 VDDQ 2 5 TA 0 to 70 C Parameter Value Unit Note Input reference voltage for Clock 0 5 VDDQ V Input signal maximum peak swing 1 5 V Input Levels VIH VIL VREF 0 31 VREF 0 31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V Output load condition See Load Circuit VIT 0 5 VDDQ erin Output O ZO 500hm CLoap 30pF Output Load circuit Input Output CAPACITANCE Vpn 2 5V VDDQ 2 5V TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance AO A12 BAO BA1 RAS CAS WE CIN1 69 81 pF Input capacitance CKEO CKE1 CIN2 42 50 pF Input capacitance CSO CS1 CIN3 42 50 pF Input capacitance CKO CK2 CKO CK2 CIN4 27 34 pF Input capacitance DMO DM8 CIN5 10 13 pF Data and DQS input output capacitance DQ0 DQ63 CouT1 10 13 pF Transcend Information Inc 184 PIN DDR333 Unbuffered DIMM TS7128MLD64V3E 1GB With 64Mx4 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component
8. 3E 1GB With 64Mx4 CL2 5 Block Diagram AO A12 BAO BA1 DQ0 DQ63 RAS AO A12 BAO BA1 DQO0 DQ7 RAS 64mx4 DDR CAS_ SDRAM IWE AO A12 AO A12 BAO BA1 BAO BA1 DQO0 DQ7 DQO0 DQ7 RAS 64Mx4 RAS_ 64Mx4 DDR CAS_ SDRAM DDR M CAS_ SDRAM gu Oz Vo e CK CK CK1 CK1 CKO CKO CK2 CK2 A0 A12 y A0 A12 BA0 BA1 BAO BA1_ DQ0 Da7 g m pao Da7 S IRAS o 64MX4 ICAS DDR A0 A12 BAO BA1 DQO0 DQ7 RAS 64MX4 CAS DDR SDRAM ICS1 CKE1 CK1 CK1 CKO CKO CK2 CK2 A0 A12 AO A12 A0 A12 BAO BA1 a BAO BA1 BAO BA1 O DQ0 DQ7 DQ0 DQ7 DQO0 DQ7 RAS O RAS RAS O 64MX4 CAS DDA WE SDRAM ICS gt A CKE 4 amp CAS Saa ICAS as WE SDRAM IWE ICS CKE 64MX4 CAS DDR WE SDRAM SDRAM DQS4 DQS5 DQS7 Serial EEPROM SCL SCL SDA SDA AO A1 A2 SAO SA1 SA2 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184 PIN DDR333 Unbuffered DIMM T
9. 4 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Parameter Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin DQ DM and DQS inputs changing twice per clock cycle IDDO 2880 mA Address and control inputs changing once per clock cycle Operating current One bank operation One bank open Burst 4 Reads Refer to the following page for detailed test condition ee PA mA Percharge power down standby current All banks idle power down mode CKE lt VIL max VIN VREF for DQ DQS and DM eee i ua Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min Address and other control inputs changing once per clock IDD2F 800 mA cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode CKE lt VIL max VIN VREF for DQ DQS and DM Active standby current CS gt VIH min CKE gt VIH min One bank active active precharge tRC tRASmax DQ DQS and DM inputs changing twice per clock cycle address and other control inputs changing once per clock cycle Operating current burst read Burst length 2 reads contiguous burst One bank active address and control inputs changing once per clock cycle IDD4R 4800 mA 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes continuou
10. S7128MLD64V3E 1GB With 64Mx4 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 0 5 3 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 3 6 V Storage temperature TSTG 55 150 C Power dissipation PD 48 W Short circuit current los 50 mA Mean time between failure MTBF 50 year Temperature Humidity Burning THB 85 C 85 Static Stress C Temperature Cycling Test TC 0 C 125 C Cycling C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C Parameter Symbol Min Max Unit Note Supply voltage VDD 2 3 2 7 V I O Supply voltage VDDQ 2 3 2 7 V I O Reference voltage VREF VDDQ 2 50mV Vpba 2 50mV V 1 I O Termination voltage VTT VREF 0 04 VREF 0 04 V 2 Input logic high voltage VIH DC VREF 0 15 VDDQ 0 3 V 4 Input logic low voltage VIL DC 0 3 VREF 0 15 V 4 Input Voltage Level CK and CK inputs VIN DC 0 3 VDDQ 0 3 V Input Differential Voltage CK and CK inputs VID DC 0 3 VDDQ 0 6 V 3 Input crossing point voltage CK and CK inputs VIX DC 1 15 1 35 V 5 Input leakage current lI
11. TS7128MLD64V3E 184 PIN DDR333 Unbuffered DIMM 1GB With 64Mx4 CL2 5 Description The TS128MLD64V3E is a 128Mx64bits Double Data Rate SDRAM high DDR333 The TS128MLD64V3E consists of 32cs CMOS 64Mx4 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS128MLD64V3E is a Dual In Line Memory Module and is intended for mounting into density for 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply VDD 2 5V 0 2V VDDQ 2 5V 0 2V e Max clock Freq 166MHZ e Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and CK e DLL aligns DQ and DQS transition with CK transition e Auto and Self Refresh 7 8us refresh interval e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data e Serial Presence Detect SPD with serial EEPROM e SSTL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Placement
12. VDDQ 06 DQ2 52 BAI 98 DQ6 144 CB7 07 VDD 53 DQ32 99 DQ7 145 VSS 08 DQ3 54 VDDQ 100 VSS 146 DQ36 09 NC 55 DQ33 101 NC 147 DQ37 10 NC 56 DQS4 102 NC 148 VDD 11 VSS 57 DQ34 103 NC 149 DM4 12 DQ8 58 VSS 104 VDDQ 150 DQ38 13 pag 59 BAO 105 DQ12 151 DQ39 14 DQst 60 DQ35 106 DQ13 152 VSS 15 VDDQ 61 Dado 107 DM1 153 DQ44 16 CK1 62 VDDQ 108 VDD 154 RAS 17 CK1 63 WE 109 DQ14 155 DQ45 18 VSS 64 Dadi 110 DQ15 156 VDDQ 19 DQ10 65 CAS 111 CKE1 157 CS0 20 DQ11 66 VSS 112 VDDQ 158 CS1 21 CKEO 67 DQS5 113 NC 159 DM5 22 VDDQ 68 DQ42 114 DQ20 160 VSS 23 DQ16 69 DQ43 115 A12 161 DQ46 24 DQ17 70 VDD 116 VSS 162 DQ47 25 DQS2 71 NC 117 DQ21 163 NC 26 VSS 72 Dads 118 A11 164 VDDQ 277 A9 73 DQ49 119 DM2 165 DQ52 28 DQ18 74 VSS 120 VDD 166 DQ53 29 A7 75 CK2 121 DQ22 167 NC 30 VDDQ 76 CK2 122 A8 168 VDD 31 DQ19 77 VDDQ 123 DQ23 169 DM6 32 A5 78 DQS6 124 VSS 170 DQ54 33 DQ24 79 DQ50 125 AG 171 DQ55 34 VSS 80 DQ51 126 DQ28 172 VDDQ 35 DQ25 81 VSS 127 DQ29 173 NC 36 DQS3 822 NC 128 VDDQ 174 DQ60 37 A4 83 DQ56 129 DM3 175 DQ61 38 VDD 84 DQ57 130 A3 176 VSS 39 DQ26 85 VDD 131 DQ30 177 DM7 40 DQ27 86 DQS7 132 VSS 178 DQ62 41 A2 87 DQ58 133 DQ31 179 DQ63 42 VSS 88 DQ59 134 CB4 180 VDDQ 43 AT 89 VSS 135 CB5 181 SAO 44 CBO 90 NC 136 VDDQ 182 SA1 45 CB1 91 SDA 137 CKO 183 SA2 46 VDD 92 SCL 138 CKO 184 VDDSPD Please refer Block Diagram Transcend Information Inc 184 PIN DDR333 Unbuffered DIMM TS7128MLD64V
13. er down exit time tPDEX 6 Ns Exit self refresh to non Read command tXSNR 75 ns Exit self refresh to read command tXSRD 200 tCK Refresh interval time tREF 7 8 us 1 Clock half period tHP tCLmin or tCHmin ns Data hold skew factor tQHS 0 55 ns DQS write postamble time tWPST 0 4 0 6 tCK 3 Note 1 Maximum burst refresh of 8 2 The specific requirement is that DQS be valid High or Low on or before this CK edge The case shown DQS going from High_Z to logic Low applies when no writes were previously in progress on the bus If a previous write was in progress DQS could be High at this time depending on tDQSS 3 The Maximum limit for this parameter is not a device limit The device will operate with a great value for this parameter but system performance bus turnaround will degrade accordingly Transcend Information Inc g 184 PIN DDR333 Unbuffered DIMM TS7128MLD64V3E 1GB With 64Mx4 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND CKEn 1 CKEn CS RAS CAS WE BAo 1 A1o AP Ao Ag A11 A12 Note Extended Register i H X L L L L OP CODE 1 2 Mode Register Set Register Mode Register Set H X L L L L OP CODE 1 2 Auto Refresh H 3 H L L L H X Entry L 3 Refresh Self L H H H 3 Refresh Exit L H X H X X X 3 Bank Active amp Row Addr H X L L H H V R
14. ow Address Auto Precharge Disable L Column 4 Read amp H x L H L H V Address Column Address Auto Precharge Enable H 4 Ao A9 A11 Write amp Auto Precharge Disable L Column 4 H X L H L L V Address Column Address Auto Precharge Enable H 4 6 Ao A9 A11 Burst Stop H X L H H L X 7 Bank Selection V L Precharge H X L L H L X All Banks X H 5 H X X X Entry H L Active Power Down L Vv V V X Exit L H xX xX X X Ent H X X X 7 H L Precharge Power L H H H x Down Mode Exit H x x x L H L V V V DM H X X 8 No Operation Command H X X x 9 H X xX L H H H 9 Note OP Code Operand Code AO A12 amp BAO BA1 Program keys EMRS MRS EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state BAO BA1 Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA is Low at read write row active and precharge bank B is selected If both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BA1 are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAO and BA
15. s burst One bank active address and control inputs changing once per clock cycle DQ DM and DQS inputs changing twice per clock cycle 50 of input data changing at every burst Auto refresh current tRC tRFC min 10 tCK for DDR266at 133Mhz distributed refresh Self refresh current CKE lt 0 2V External clock should be on IDD6 96 mA Operating current Four bank operation Four bank interleaving with BL 4 Refer to the following page for detailed test condition Note Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap IDD3P 1120 mA IDD3N 1760 mA IDD4W 5120 mA IDD5 5760 mA IDD7 9280 mA Transcend Information Inc 6 TS1 28MLD64V3E 184 PIN DDR333 Unbuffered DIMM 1GB With 64Mx4 CL2 5 AC OPERATING CONDITIONS Parameter Symbol Min Max Unit Note Input High Logic 1 Voltage DQ DQS and DM signal VIH AC VREF 0 31 V 3 Input Low Logic 0 Voltage DQ DQS and DM signal VIL AC VREF 0 31 V 3 Input Differential Voltage CK and CK inputs VID AC 0 7 VDDQ 0 6 V 1 Input Crossing Point Voltage CK and CK inputs VIX AC 0 5 VDDQ 0 2 0 5VDDQ 0 2 V 2 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC
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