Transcend 256MB DDR DDR400 ECC Unbuffer Memory
Contents
1. continuous burst One bank active address and control inputs changing once per clock cycle DQ DM and DGS inputs changing twice per clock cycle IDD4W 1 980 mA 50 of input data changing at every burst Auto refresh current tRC tRFC min wos 1800 m 10 tCK for DDR400 at 200Mhz distributed refresh oe mA Operating current Four bank operation Four bank interleaving with BL 4 DD 3450 m Refer to the following page for detailed test condition Note 1 Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading capacitor Transcend Information Inc 6 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 AC OPERATING CONDITIONS Symbol Min Max Unit Note nput High Logic 1 Voltage DQ DOS and DM signals VIHAC VREF 0 31 Vv 3 nput Low Logic 0 Voltage DQ DQS and DM signals VILLAC VREF 0 31 Note 1 VID is the magnitude of the difference between the input level on CK and the input on CK 2 The value of VIX is expected to equal 0 5 V DDQ of the transmitting device and must track variations in the DC level of the same 3 These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation The AC and DC input specifications are relative to a VREF envelope that has been bandwidth limited 20MHz AC OPERATING TEST C2. i PCB 09 1675 TS32MLD 2V4F 184PIN DDR400 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Dimensions Side Millimeters A 133 35 0 20 12 39 6 35 2 20 30 48 0 20 19 80 4 00 12 00 1 27 0 10 I O m im J IO W Refer Placement Transcend Information Inc Inches 5 250 0 008 2 850 0 250 0 087 1 200 0 008 0 779 0 157 0 472 0 050 0 004 Pin Identification Symbol Function A0 A12 BAO BA1 DQ0 DQ63 CBO CB7 DQS0 DQS8 CKO CKO CK1 CK1 CK2 CK2 CKEO CS0 RAS ICAS IWE DMO DM8 VDD VDDQ VREF VDDSPD SA0 SA2 SCL SDA VSS NC Address input Data Input Output Data strobe input output Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data in Mask 2 5 Voltage power supply 2 5 Voltage Power Supply for DQS Power Supply for Reference 2 5 Voltage Serial EEPROM Power Supply Address in EEPROM serial PD Clock Serial PD Add Data input output Ground No Connection 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 Pinouts Pin Name No Name Please refer Block Diagram Transcend Information Inc 3 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 Block Diagram A0 A12 BAO BA DQ0 DQ63 RAS ICAS ANE CS0 CKEO CK1 CK1 CKO CKO CK2 CK2 A0 A1 A2 SA0 SA1 SA2 This technical information is based on industry s
3. selected 6 During burst write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst Burst stop command is valid at every burst length DM sampled at the rising and falling edges of the DQS and Data in are masked at the both edges Write DM latency is O This combination is not defined for any function which means No Operation NOP in DDR SDRAM Com Transcend Information Inc 10 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 Serial Presence Detect Specification Serial Presence Detect 0 jofBytsWrtteninoSeralMemory 128bytes BO 1 JTotalfofBytesofS P D Memory 256byts 08 3 of Row Addresses on this Assembly 103 0D 4 ofColumn Addresses on this Assemby 10 A 72bits a ee 2 A 7 Data Width of this Assembly 8 VDDQ and Interface Standard of this Assembly SSTL 2 04 DDR SDRAM Cycle Time at CAS Latency 2 5 n 10 DDR SDRAM Access Time from Clock at CL 2 5 T Refresh Rate Type 7 8us Self Refresh 5 43 Primary DDR SDRAM Width X 1 8 04 0 0 02 2 44 Error Checking DDR SDRAM Width 1 Min Clock Delay for Back 5 in Clock Delay for Back to ICCD 4CLK Back Random Column Address 16 BurstLengths Supported 2 4 8 17 __ of banks on each DDR SDRAM device 18 CAS La
4. 12 Ext pede L OP CODE Mode Register Set Register Mode Register Set H L L L L OP CODE 1 2 Auto Refresh E X Write amp Column Address Auto Precharge Enable mre Burst Stop on Eel Ent Self y Refresh Exit I Bank Active amp Row Addr Auto Precharge Disable Column Read amp Add Column Address Auto Precharge Enable id Auto Precharge Disable Column Address X Bank Selection Precharge All Banks Entry Active Power Down x m lt Precharge Power Down Mode No Operation Command ELEE Note 1 OP Code Operand Code A0 A12 amp BAO BA1 keys TGEWRSIMUS 2 EMRS MRS can be issued only at all banks precharge state A new command can be issued 2 clock cycles after EMRS or MRS 3 Auto refresh functions are same as the CBR refresh of DRAM The automatically precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAO BAT Bank select addresses If both BAO and BA1 are Low at read write row active and precharge bank A is selected If both BAO is High and BA1 is Low at read write row active and precharge bank B is selected If both BAO is Low and BA1 is High at read write row active and precharge bank C is selected If both BAO and BAT are High at read write row active and precharge bank D is selected 5 If A10 AP is High at row precharge BAO and BA1 are ignored and all banks are
5. DQS out access time from CK CK ibQscK 05 05 Output data access time from CK CK AC 07 07 Data strobe edge to output data edge tasa 035 Read Preamble IRPRE 09 11 Read Postamble trest 04 06 CK to valid DQS in tass 072 Write preamble setup time IWPRES oo Write preamble IWPRE 025 Write postamble twest 04 DQS falling edge to CK rising setup time iss 02 DQS falling edge from CK rising hold time sH 02 DQS in high level width tDQSH 035 DQS in low level width tase 035 Address and Control input setup time tIS 358 1 Address and Control input hold time tlH oe Data out high impedance time from CK CK tHZ 46 Data out low impedance time from CK CK tLZ a EN Mode register set cycle time DQ amp DM setup time to DQS tDS DQ amp DM hold time to DOS tDH DQ amp DM input pulse width Control amp Address input pulse width for each input EN tHP 0 55 tCLmin tCHmin Refresh interval time tREF 7 8 Output DQS valid window TQH tHP 0 55 HP tCLmin tCHmin Clock half period Transcend Information Inc g 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 Data hold skew factor Auto Precharge write recovery precharge time tDAL LX d o aa d A Exit self refresh to non READ command tXSNR 75 ee Exit self refresh to READ command tXSRD Do a LLL tCK Note 1 VID is the magnitude of the difference between the input lev
6. ONDITIONS Vpp 2 6 Vppa 2 6 Ta 0 to 70 C po Parameter Vale Umit Note Input reference voltage for Clock O5 VDQ VT Input signal maximum peak swing Input Levels VIKIL JVREFSOSIVREF 031 V Input timing measurementreferencelevel VREF V Output timing measurementreferencelevel TT Output load condition S See toad Circuit 0 VTT 0 5 VDDQ 0 5 VDDQ al CLoAD 30pF Output Load circuit Input Output CAPACITANCE Voo 2 6V Vopa 2 6V TA 25 C f 1MHz Parameter Input capacitance A0 A12 BAO BA1 RAS CAS ANE Input capacitance CKEO Input capacitance CSO Input capacitance CKO CK2 Input capacitance DMO DMB8 Data and DQS input output capacitance DQ0 DQ63 Data input output capacitance CBO CB7 Transcend Information Inc 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 AC Timing Parameters amp Specifications These AC characteristics were tested on the Component Parameter Symbol RC nm Refresh row cycle time ns Row active time 40 70K Row cycle time RAS to CAS delay tRCD 15 Row active to Row active delay RP 15 Row active to Row active delay tRRD 10 et o v Lou o Lom p NN NEM NN Write recovery time WR 40 Internal write to read command delay WIR 2 j Clock cycle time tCK Clock high level width tCH tCK Clock low level width tCL L O45 i 559
7. TS32MLD 2V4F 184PIN DDR400 Unbuffered DIMM 256MB With 32Mx8 CL2 5 Description The TS382MLD72V4F is a 32M x 64bits Double Data Rate SDRAM high density for DDR400 The TS32MLD72V4F consists of 9pcs CMOS 32Mx8 bits Double Data Rate SDRAMs in 66 pin TSOP II 400mil packages and a 2048 bits serial EEPROM on a 184 pin printed circuit board The TS32MLD72V4F is a Dual In Line Memory Module and is intended for mounting into 184 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock Data I O transactions are possible on both edges of DQS Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e Power supply VDD 2 6V 0 1V VDDQ 2 6V 0 1V e Max clock Freq 200MHZ Double data rate architecture two data transfers per clock cycle e Differential clock inputs CK and CK e DLL aligns DQ and DQS transition with CK transition e Auto and Self Refresh 7 8us refresh interval e Data I O transactions on both edge of data strobe e Edge aligned data output center aligned data e Serial Presence Detect SPD with serial EEPROM e SSIL 2 compatible inputs and outputs e MRS cycle with address key programs CAS Latency Access from column address 2 5 Burst Length 2 4 8 Data Sequence Sequential amp Interleave Transcend Information Inc Placement oO
8. ac 11 Min tCL tCH refers to the smaller of the actual clock low time and the actual clock high time as provided to the device i e this value can be greater than the minimum specification limits for tCL and tCH For example tCL and tCH are 50 of the period less the half period jitter tJIT HP of the clock source and less the half period jitter due to crosstalk tUIT crosstalk into 12 tQH tHP tQHS where tHP minimum half clock period for any given cycle and is defined by clock high or clock low tCH tCL tQHS accounts for 1 The pulse duration distortion of on chip clock circuits and 2 The worst case push out of DQS on one transition followed by the worst case pull in of DQ on the next transition both of which are separately due to data pin skew and output pattern effects and p channel to n channel variation of the output drivers 13 tDQSQ Consists of data pin skew and output pattern effects and p channel to n channel variation of the output drivers for any given cycle 14 tDAL tWR tCK tRP tCK 15 In all circumstances tXSNR can be satisfied using tXSNR tRFCmin 1 tCK 16 The only time that the clock frequency is allowed to change is during self refresh mode O ON 9 Transcend Information Inc Q 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 SIMPLIFIED TRUTH TABLE V Valid X Don t Care H Logic High L Logic Low COMMAND CKEn 1 ICS JRAS CAS A10 AP Ao Ag A11 A
9. el on CK and the input level on CK 2 The value of VIX is expected to equal 0 5 VDDQ of the transmitting device and must track variations in the dc level of the same 09 tHZ and tLZ transitions occur in the same access time windows as valid data transitions These parameters are not referenced to a specific voltage level but specify when the device output in no longer driving HZ or begins driving LZ 4 The maximum limit for this parameter is not a device limit The device will operate with a greater value for this parameter but sys tem performance bus turnaround will degrade accordingly 5 The specific requirement is that DQS be valid HIGH LOW or at some point on a valid transition on or before this CK edge A valid transition is defined as monotonic and meeting the input slew rate specifications of the device When no writes were previously in progress on the bus DQS will be transitioning from High Z to logic LOW If a previous write was in progress DQS could be HIGH LOW or transitioning from HIGH to LOW at this time depending on tDQSS A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device For command address input slew rate gt 0 5 V ns For CK amp CK slew rate 0 5 V ns These parameters guarantee device timing but they are not necessarily tested on each device They may be guaranteed by device design or tester correlation 10 Slew Rate is measured between VOH ac and VOL
10. h driver lOH lw 1 mA VOUT VTT 0 84V Output Low Current Normal strength driver NEN mA VOUT VTT 0 84V Output High Current Half strength driver lOH L1 mA VOUT VTT 0 45V Output High Current Half strength driver IOL NEN EE LA VOUT VTT 0 45V Note 1 VREF is expected to be equal to 0 5 VDDQ of the transmitting device and to track variations in the dc level of same Peak to peak noise on VREF may not exceed 2 of the dc value 2 VTT is not applied directly to the device VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF 3 VID is the magnitude of the difference between the input level on CK and the input level on CK 4 The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage over the entire temperature and voltage range for device drain to source voltages from 0 25V to 1 0V For a given output it represents the maximum difference between pullup and pulldown drivers due to process variation The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1 7 for device drain to source voltages from 0 1 to 1 0 5 This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz Any noise above OMHz at the DRAM generated from any source other than the DRAM itself may not exceed the DC voltage range of 2 6V 100mV Tra
11. nscend Information Inc 5 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 DC CHARACTERISTICS Recommended operating condition unless otherwise noted VDD 2 7V TA 10 C Symbol Max Unit Note Operating current One bank Active Precharge tRC tRCmin DQ DM and DQS inputs changing twice per clock cycle 950 mA Address and control inputs changing once per clock cycle Operating current One bank operation One bank open Burst 4 Reads IDD1 1170 M Refer to the following page for detailed test condition i Percharge power down standby current All banks idle power down mode CKE VIL max VIN VREF for DQ DQS and DM IDD2P 40 mA Precharge Floating standby current CS gt VIH min All banks idle CKE gt VIH min Address and other control inputs changing once per clock IDD2F 270 mA cycle VIN VREF for DQ DQS and DM Active power down standby current one bank active power down mode Active standby current CS gt VIH min CKE gt VIH min one bank active active precharge tRC tRASmax DQ DQS and DM inputs changing twice per clock cycle IDDSN 680 mA address and other control inputs changing once per clock cycle Operating current burst read Burst length 2 reads continuous burst One bank active address and control inputs changing once per clock cycle IDDAR 1 670 mA 50 of data changing at every burst lout 0 mA Operating current burst write Burst length 2 writes
12. tandard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 ABSOLUTE MAXIMUM RATINGS Parameter Symb Value Umit Voltage on any pin relative to Vss Voltage on VDD supply to Vss torage temperature C Power dissipation hort circuit current lOS mA Mean time between failure MTBF year emperature Humidity Burning C emperature Cycling Test C Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss 0V TA 0 to 70 C upply voltage VDD O Supply voltage VDDQ O Reference voltage VREF O Termination voltage VIT nput logic high voltage nput logic low voltage VIL DC nput Voltage Level CK and CK inputs nput Differential Voltage CK and CK inputs V I Matching Pullup to Pulldown Current Ratio VI Ratio nput leakage current uA Output leakage current loz uA Output High Current Normal strengt
13. tency supported 2 582 01 02 0 0 C 28 C 8 0 S 8 0 11 DIMM configuration type non parity Party ECC ECC 02 0 19 CS Latency ock 01 20 WE Latency tock 002 00 21 Differential DDR SDRAM Module Attributes Clock Input 0 2V voltage DDR SDRAM Device Attributes General tolerance 22 25 DDRSDRAMCydeTmeCL t 5 0 26 _ DDR SDRAM Access from Clock CL 1 5 29 3 32 Command AddressImutSetup Time O6n s 60 33 Commend Address Input Hold Time oes 680 5 8 0 7 3 Transcend Information Inc 1 184PIN DDR400 Unbuffered DIMM TS32MLD 2V4F 256MB With 32Mx8 CL2 5 36 61 Superset Information oOo 0 62 SPD Data Revision Code o yY 00 64 71 Manufacturers JEDEC ID 73 90 Manufacturers Part Number 91 92 93 94 Manufacturing Date By Manufacturer 95 98 Assembly Serial Number By Manufacturer 128 255 Unused Storage Locations Undefined 99 127 Manufacturer Specific Data ee ee Transcend Information Inc 12
Download Pdf Manuals
Related Search