Transcend 128MB SDRAM PC133 Unbuffer Non-ECC Memory
Contents
1. TOU OCARINA AA PCB 09 7149 I gt lt 168Pin PC133 Unbuffered DIMM TS1 6M LS64V6D 128MB with 16Mx8 CL3 Dimensions Pin Identification Side Millimeters Inches Symbol Function A 133 35 0 40 5 250 0 016 AO A11 BAO BA1 Address input B 65 67 2 585 DQ0 DQ63 Data Input Output C 23 49 0 925 CLKO CLK2 Clock Input 2 ee 2 230 CKEO Clock Enable Input E 3 00 0 118 CSO CS2 Chip Select Input F 31 75 0 20 1 250 0 008 RAS Row Address Strobe G 19 80 0 788 H 15 80 0 622 CAS Column Address Strobe 1 27 0 10 0 050 0 004 PNE Wie Enable Refer Placement DQM0 DQM7 Data DQ Mask SA0 SA2 Address in EEPROM SCL Serial PD Clock SDA Serial PD Add Data input output Vcc 3 3 Voltage Power Supply Vss Ground NC No Connection Transcend Information Inc 2 168Pin PC133 Unbuffered DIMM TS1 6M LS64V6D 128MB with 16Mx8 CL3 Pinouts Pin Pin Pin Name No Name No Name No Name Vss 43 85 Vss 127 Vss DQO 44 86 DQ32 128 CKEO DQ1 DQ33 129 CS3 DQ2 DQ34 130 DQM6 DQ3 DQ35 131 DQM7 Vcc Vcc 132 A13 DQ4 DQ36 133 DQ5 DQ37 134 DQ6 DQ38 135 DQ7 DQ39 136 DQ8 DQ40 137 Vss Vss 138 DQ9 DQ41 139 DQ10 DQ42 140 DQ11 DQ43 141 DQ12 DQ44 142 DQ13 DQ45 143 Vcc Vcc 144 DQ14 DQ46 145 DQ15 DQ47 146 CBO CB4 147 148 149 NC 150 151 152 153 154 A10 AP 80 BA1 Vcc Vcc CLKO Please refer Block Diagram Transcend Information Inc 3 168Pin PC133 Unbuffere2. 128MB with 16Mx8 CL3 DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C Parameter Symbol Test Condition Value Unit Note Operating Current Burst Length 1 Icc1 960 mA 1 One Bank Active tRC tRC min loL OmA Precharge Standby Current CAE a Ce Moet Ons mA in power down mode Icc2PS CKE amp CLK lt ViL max tcc lt 8 Icc2N CKE ViH min CS gt VIH min tcc 10ns 160 Precharge Standby Current Input signals are changed one time during 30ns mA in non power down mode Icc2NS CKE gt ViH min CLK lt ViL max tcc 56 Input signals are stable Active Standby Current Icc3P CKE lt VIL max tcc 10ns 40 are in power down mode Icc3PS CKE amp CLK lt ViL max tcc lt 40 Icc3N Active Standby Current ae ae fa on eae ane in non power down mode nput signals are changed one time during 30ns mA ONG Bam ACIve lec3NS KE gt Vvinimin CLK lt ViL max tec 160 Input signals are stable Operating Current Icc4 Oem mA 1 Bust Mode Page Burst 4200 tccp 2CLKs Refresh Current ICC5 tRC gt tRC min 1760 mA 2 Self Refresh Current Icce CKE lt 0 2V 12 mA Note DQ loading cap Module IDD was calculated on the basis of component IDD and can be differently measured according to Transcend Information Inc 168Pin PC133 Unbuffered DIMM TS1 6M LS64V6D 128MB with 16Mx8 CL3 AC OPERATING TEST CONDITIONS vo 3 3V 0 3V TA 0 to 70
3. C Parameter Value Unit AC Input levels VIH VIL 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 3 3V O Vtt 1 4V gt VoH DC 2 4V loH 2MA Output O E2050 Ohm Vor DC 0 4V loL 2MA 50pF Z 50F 870 Ohm 77T Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit OPERATING AC PARAMETER AC operating conditions unless otherwise noted Parameter Symbol Value Unit Note Row active to row active delay tRRD min 15 ns 1 RAS to CAS delay tRCD min 20 ns 1 Row precharge time tRP min 20 ns 1 Row active time IRAS min A9 ns 1 tRAs max 100 us Row cycle time tRC min 65 ns 1 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to row precharge tRDL min 2 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 Number of valid CASTEN S ea 4 output data Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop Trans
4. Cycle Time highest CAS latency 7 5ns 75 10 SDRAM Access from Clock highest CL 5 4ns 54 11 DIMM configuration type non parity ECC None 00 15 625us Self 12 Refresh Rate Type Refresh 80 13 Primary SDRAM Width X8 08 14 Error Checking SDRAM Width none 00 15 Min Clock Delay Back to Back Random Address 1 clock 01 16 Burst Lengths Supported 1 2 4 8 amp Full page 8F 17 Number of banks on each SDRAM device 4 bank 04 18 CAS Latency 3 04 19 CS Latency 0 clock 01 20 Write Latency 0 clock 01 21 SDRAM Module Attributes Non Buffer 00 22 SDRAM Device Attributes General Prec All Auto Prec OE R W Burst 23 SDRAM Cycle Time 2 highest CL 0 00 24 SDRAM Access from Clock 2 highest CL 0 00 25 SDRAM Cycle Time 3 highest CL 0 00 26 SDRAM Access from Clock 3 highest CL 0 00 27 Minimum Row Precharge Time 20ns 14 28 Minimum Row Active to Row Activate 15ns OF 29 Minimum RAS to CAS Delay 20ns 14 30 Minimum RAS Pulse Width 45ns 2D 31 Density of Each Bank on Module 128MB 20 32 Command Address Setup Time 1 5ns 15 33 Command Address Hold Time 0 8ns 08 34 Data Signal Setup Time 1 5ns 15 35 Data Signal Hold Time 0 8ns 08 36 61 Superset Information 00 62 SPD Data Revision Code JEDEC2 02 63 Checksum for Bytes 0 62 9D 64 71 Manufacturers JEDEC ID Code per JEP 108E Transcend 7F 4F 72 Man Manufacturers Manufacturing Location T 54 73 90 Part Number 54 53 31 36 4D 4C TS16MLS64V6D 53 36 34 56 36 44 Transcend Info
5. TS16MLS64V6D Description The TS16MLS64VED is a 16M bit x 64 Synchronous Dynamic RAM high density for PC 133 The TS16MLS64VED consists of 8pcs CMOS 16Mx8 bits Synchronous DRAMs in TSOP II 400mil packages and a 2048 bits serial EEPROM on a 168 pin printed circuit board The TS16MLS64V6D is a Dual In Line Memory Module and is intended for mounting into 168 pin edge connector sockets Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operation frequencies programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system applications Features e RoHs Compliant Product e Performance Range PC 133 e Conformed to JEDEC Standard Spec e Burst Mode Operation e Auto and Self Refresh e CKE Power Down Mode e DQM Byte Masking Read Write e Serial Presence Detect SPD with serial EEPROM e LVTTL compatible inputs and outputs e Single 3 3V 0 3V power supply e MRS cycle with address key programs Latency Access from column address Burst Length 1 2 4 8 amp Full Page Data Sequence Sequential amp Interleave e Allinputs are sampled at the positive going edge of the system clock Transcend Information Inc Placement 168Pin PC133 Unbuffered DIMM 128MB with 16Mx8 CL3 TOUT COCO OOOO TOO JOUNE DOE DA OA DOEDE nnmnnn
6. cend Information Inc 7 TS16MLS64V6D 168Pin PC133 Unbuffered DIMM 128MB with 16Mx8 CL3 AC CHARACTERISTICS AC operating conditions unless otherwise noted Refer to the individual component not the whole module Parameter Symbol Value Min Value Max Unit Note CLK cycle time tcc 7 5 1000 ns 1 CLK to valid output delay tSAC 5 4 ns 1 2 Output data hold time tOH 3 0 ns 2 CLK high pulse width tCH 2 5 ns 3 CLK low pulse width teL 25 ns 3 Input setup time tss 1 5 ns 3 Input hold time tSH 0 8 ns 3 CLK to output in Low Z tSLZ 1 ns 2 CLK to output tSHZ A A 5 4 in Hi Z Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf Ins If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter Transcend Information Inc 168Pin PC133 Unbuffered DIMM TS1 6M LS64V6D 128MB with 16Mx8 CL3 SIMPLIFIED TRUTH TABLE COMMAND CKEn 1 CKEn CS RAS CAS WE DQM BAo 1 A1o AP A11 Ao A9 Note Register Mode Register Set H X L L L L X OP CODE 1 2 Auto Refresh H H L L L H x x 3 Entry L 3 Refresh Self L H H H 3 Refresh i ef
7. d BA1 are High at read write row active and precharge bank D is selected If A1o AP is High at row precharge BAo and BA is ignored and both banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edged of a CLK masks the data in at the very CLK Write DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Transcend Information Inc 9 TS16MLS64V6D Serial Presence Detect Specification 168Pin PC133 Unbuffered DIMM 128MB with 16Mx8 CL3 Serial Presence Detect Standard Byte No Function Described Specification Vendor Part 0 of Bytes Written into Serial Memory 128bytes 80 1 Total of Bytes of S P D Memory 256bytes 08 2 Fundamental Memory Type SDRAM 04 3 of Row Addresses on this Assembly 12 0C 4 of Column Addresses on this Assembly 10 OA 5 of Module Banks on this Assembly 1 bank 01 6 Data Width of this Assembly 64bits 40 7 Data Width Continuation 0 00 8 Voltage Interface Standard of this Assembly LVTTL3 3V 01 9 SDRAM
8. d DIMM TS1 6M LS64V6D 128MB with 16Mx8 CL3 Block Diagram CSO CKEO ICS CKE ICS CKE W Ul 2 US ICS CKE ICS CKE Bol 3 U2 3 3 U6 ICS CKE ICS CKE U3 5 U7 556565656 DQM ICS CKE ICS CKE U4 Dose U8 BAO VV U1 U8 VDD gt gt BAL w __ U1 U8 U1 U8 RAS Ww U1 U8 VSS 2 F _ 7 CAS U1 U8 WE U1 U8 CLKO NAN t U1 U2 U5 U6 EEPROM CLK2 ne ee mel U3 U4 U7 U8 as SAO SA1 SA2 Note 1 U1 U8 are 16Mx8 SDRAM 2 DQ to I O wiring may be changed per nibble 3 Unless otherwise noted resister values are 10 Ohms 5 This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assumes no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice Transcend Information Inc 4 TS16MLS64V6D ABSOLUTE MAXIMUM RATINGS 168Pin PC133 Unbuffered DIMM 128MB with 16Mx8 CL3 Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on VDD supply to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation PD 8 W Short circuit current los 50 mA Operating temperature TA 0 70 C Note Permanent device da
9. mage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS AND CHARACTERISTICS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Symbol Min Type Max Unit Note Supply voltage VDD 3 0 3 3 3 6 V Input high voltage VIH 2 0 3 0 VDD 0 3 V 1 Input low voltage VIL 0 3 0 0 8 V 2 Output high voltage VOH 2 4 V IOH 2mA Output low voltage VOL gt 0 4 V IOL 2mA Input leakage current Inputs lL 10 10 uA 3 Note 1 VIH max 5 6V AC The overshoot voltage duration is lt 3ns 2 VIL min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs CAPACITANCE TA 25 C f 1MHz Parameter Symbol Min Max Unit Input capacitance Ao A11 BAo BA1 CIN1 30 45 pF Input capacitance RAS CAS WE CIN2 30 45 pF Input capacitance CKEO CIN3 30 45 pF Input capacitance CLKO CLK2 CIN4 22 30 pF Input capacitance CS0 CS2 CIN5 15 25 pF Input capacitance DQM0 DQM7 CIN6 6 8 pF Data input output capacitance DQ0 DQ63 COUT 6 8 pF Transcend Information Inc 5 TS16MLS64V6D 168Pin PC133 Unbuffered DIMM
10. res Exit L H H X X X X X 3 Bank Active amp Row Addr H X L L H H X V Row Address Read amp Auto Precharge Disable L Column 4 H xX L H L H X V Address Column Address Auto Precharge Enable H ia 4 5 i Auto Precharge Disable L Column 4 Write amp H x L H L L X V Address Column Address Auto Precharge Enable H AoAo 4 5 Burst Stop L H H L X 6 Bank Selection V L L L H L X Precharge Both Banks X H Clock Suspend or H X X X E H L X Active Power L V V V x Down Exit L H X X x x x Entry 4 L H X X X x Precharge Power L H H H x Down Mode Exit H X X X L H X L V V V DQM H X V X 7 No Operation Command H x H x X x x V Valid X Don t Care H Logic High L Logic Low Note 1 OP Code Operand Code Ao A11 BAo BA1 Program keys MRS 2 MRS can be issued only at both banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at both banks precharge state 4 BAo BA1 Bank select address If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA1 is High at read write row active and precharge bank B is selected If both BAo is High and BA1 is Low at read write row active and precharge bank C is selected If both BAo an
11. rmation Inc 10 168Pin PC133 Unbuffered DIMM TS1 6M LS64V6D 128MB with 16Mx8 CL3 20 20 20 20 20 20 91 92 Revision Code 0 93 94 Manufacturing Date By Manufacturer Variable 95 98 Assembly Serial Number By Manufacturer Variable 99 125 Manufacturer Specific Data 0 126 Intel Specification Frequency 100MHz 64 127 Intel Specification CAS Latency Clock Signal Support CL 3 Clock 0 3 F4 128 Unused Storage Locations Open FF Transcend Information Inc 11
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