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Intel S1400FP2

1. Error Code Error Message Response 852D DIMM_E2 failed test initialization Major 852E DIMM_E38 failed test initialization Major 852F DIMM_F1 failed test initialization Major 8530 DIMM_F2 failed test initialization Major 8531 DIMM_FS failed test initialization Major 8532 DIMM_G1 failed test initialization Major 8533 DIMM_G2 failed test initialization Major 8534 DIMM_G3 failed test initialization Major 8535 DIMM_H1 failed test initialization Major 8536 DIMM_H2 failed test initialization Major 8537 DIMM_H3 failed test initialization Major 8538 DIMM_11 failed test initialization Major 8539 DIMM_l2 failed test initialization Major 853A DIMM_I3 failed test initialization Major 853B DIMM_J1 failed test initialization Major 853C DIMM_J2 failed test initialization Major 853D DIMM_J3 failed test initialization Major 853E DIMM_K 1 failed test initialization Major 853F DIMM_K2 failed test initialization Major Go to 85C0 8540 DIMM_A1 disabled Major 8541 DIMM_A2 disabled Major 8542 DIMM A3 disabled Major 8543 DIMM_B1 disabled Major 8544 DIMM_B2 disabled Major 8545 DIMM_B3 disabled Major 8546 DIMM_C1 disabled Major 8547 DIMM_C2 disabled Major 8548 DIMM_C3 disabled Major 8549 DIMM_D1 disabled Major 854A DIMM_D2 disabled Major 854B DIMM_D3 disabled Major 854C DIMM_E1 disabled
2. lt a Os S565 SS Kl E clen e e l Ala i AK AH AE AC AB DIMM_C1 DIMM_B1 EREEFEE Overview AF005202 Figure 2 Intel Server Board S1400FP Layout Table 2 Intel Server Board S1400FP Component Layout Description Description A Serial B header Y TPM header B RMM4 header Z Storage Upgrade Key C Slot 2 32bit 33MHz PCI AA BIOS Recovery jumper D eUSB SSD Header AB Password Clear jumper E Slot 3 PCI Express Gen2 x4 electrical AC LCP header with x8 physical connector F Slot 4 PCI Express Gen3 x4 electrical AD System Fan 1 header with x8 physical connector G RMM4 Lite header AE HSBP DC header Slot 5 PCI Express Gens x8 electrical AF Chassis intrusion haader with x8 physical connector Slot 6 PCI Express Gens x8 electrical AG IPMB header with x16 physical connector J Status LED AH HDD LED header Revision 2 0 Intel order number G64246 003 5 Overview Intel Server Board S1400FP TPS Description Description K Identify LED Al BMC Force Update jumper L Diagnostic LED AJ BIOS Default jumper M NIC 3 4 connectors for S1400FP4 only AK ME force update jumper N NIC 1 2 and USB 0 1 2 3 connectors AL Internal USB header O VGA connector AM Internal USB header P Serial B connector AN SATA SGPIO header Q Auxil
3. 118 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets PCI Riser 1 nc Temperature Temperature Threshold Degraded e 27h Seely p u l c nc J Ge and analog R T A Xx PCI Riser 1 Specitic Oth O1h c Non e Temp fatal nc IO Riser Temperature Threshold Degraded Temperature 28h Ge p u l c nc g Gi and analog 187 A D IO Riser Temp specific Oth Oth c Non e fatal Hot swap nc Backplane 1 is Temperature Threshold Degraded Se 29h ee u l c nc Gs and analog R T A D perature specific oih Oth c Non e HSBP 1 Temp fatal Hot swap nc Backplane 2 is Temperature Threshold Degraded De 2Ah GE M u l c nc 3 Ge and analog R T A D perature specific Oth Oih c Non e HSBP 2 Temp fatal Hot swap nc Backplane 3 is Temperature Threshold Degraded at 2Bh ies p u 1 c nc E and Analog R T a x perature specific Oth Oih c Non e HSBP 3 Temp fatal PCI Riser 2 nc Temperature Temperature Threshold Degraded pS 2Ch Elation g u l c nc g Asand Analog R T A X PCI Riser 2 specific Oth Oth c Non
4. nnsssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 78 7 1 Keyboard Video and Mouse KVM Redirection ceeeceeeeeeeeeeeeeeeeeeeeteeeeeeees 79 7 1 1 Rem te Console EE 80 7 1 2 Steg Te EE 80 Paro SOCUMIY steno a en cede a ek aan an ache aan waa ke meee eae 81 PA EL EE 81 7 1 5 E EE 81 7 1 6 Force enter BIOS Setup icici cock ege ceed a ace eege EEN 81 7 2 Media RgdirectiON zectantectcecrescsenaesccenctioteaueanconctbee retin hatenellderuscGnectidettgerascnnetidonus 81 7 2 1 E e 82 7 2 2 Network Port Usage i ci ssrin e A R oon pede 82 8 On board Connector Header Overview cccccccssseeeeeeeneeeeeeeeeeeeeeneeeeeeeeeeeeeeaeeeeeeeeeeeeeeees 83 8 1 Board Connector Information EE 83 8 2 Power GOMMECIONS oesie ra eai e a aeea EE E E KEE Ea a Ei 84 8 3 System Management Headers sssesssnnneneesseernerrrrrrestrrrrrrnnrreseresertrnnrnnnneserrenne 85 8 3 1 Intel Remote Management Module 4 Connechor 85 8 3 2 TPM EIDEN ee ee EE 86 8 3 3 Intel RAID C600 Upgrade Key Connechor 86 8 3 4 Local Control Panel Header snc hc acs tec centeetiviect Ztet genee 86 8 3 5 HSBP FG EE EE 86 8 3 6 HDD LED TEEN 86 8 3 7 Chassis Intrusion Header 87 vi Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Table of Contents 8 3 8 SATA SGPIO E TEE 87 8 3 9 lt SAS SGPIO e TEE 87 SIE LEM eet See ENEE Ehe e ENEE SES Ee 87 8 4 Front Panel Connector EE 87 8 4 1 Power Sleep Button and LED Support ke
5. ses PCI E GENS x8 SLOT 6 x16 CONN Riser Board Support SLOT 5 X8 CONN PCI E GEN3 x8 x N39 310d px ZN39 IWG PCI E GENS x4 SLOT 4 X8 CONN PCI E GEN2 x4 SLOT 3 X8 CONN SLOT 2 PCI32 SS Dees Gbit LAN x2 Intel 1350 Intel C600 PPM Gigabit Chipset ether Gbit LAN x2 bi Ne eech AF005561 Figure 15 Functional Block Diagram of Processor IIO Sub system The following sub sections will describe the server board features that are directly supported by the processor IIO module Features and functions of the Intel C600 Series chipset will be described in its own dedicated section Revision 2 0 Intel order number G64246 003 27 Functional Architecture Intel Server Board S1400FP TPS 3 2 3 1 Network Interface Network connectivity is provided by means of one onboard Intel Ethernet Controller 1350 providing up to four 10 100 1000 Mb Ethernet ports The NIC chip is supported by implementing x2 PCle Gen2 signals from the Intel C600 PCH On the Intel Server Board S1400FP two for S1400FP2 and four for S1400FP4 external 10 100 1000 Mb RJ45 Ethernet ports are provided Each Ethernet port drives two LEDs located on each network interface connector The LED at the right of the connector is the link activity LED and indicates network connection when on and transmit receive activity when blinking The LED at the left of the connector indicates link speed as defined in the following table Table 6
6. DXE Core started DXE NVRAM Init SB RUN Init Dxe CPU Init DXE PCI Host Bridge Init DXE NB Init DXE NB SMM Init DXE SB Init DXE SB SMM Init DXE SB devices Init 136 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Appendix C POST Code Diagnostic LED Decoder Checkpoint Diagnostic LED Decoder 1 LED On O LED Off MSB Upper Nibble Lower Nibble LSB 8h 4h 2h lh 8h 4h ch 1h LED 78h 79h 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh Ath A2h A3h A4h A5h A6h A7h A8h A9h ABh ACh ADh AEh AFh BOh Bih B2h B3h B4h B5h B6h B7h 00h S3 Resume 7 6 5 4 3 2 1 0 Description DXE ACPI Init DXE CSM Init DXE BDS Started DXE BDS connect drivers DXE PCI Bus begin DXE PCI Bus HPC Init DXE PCI Bus enumeration DXE PCI Bus resource requested DXE PCI Bus assign resource DXE CON_OUT connect DXE CON_IN connect DXE SIO Init DXE USB start DXE USB reset DXE USB detect DXE USB enable DXE IDE begin DXE IDE reset DXE IDE detect DXE IDE enable DXE SCSI begin DXE SCSI reset DXE SCSI detect DXE SCSI enable DXE verifying SETUP password DXE SETUP start DXE SETUP input wait DXE R
7. Glossary This appendix contains important terms used in the preceding chapters For ease of use numeric entries are listed first for example 82460GX with alpha entries following for example AGP 4x Acronyms are then entered in their respective place with non acronyms following ne A AR ns B S S F Bridge Circuitry connecting one computer bus to another allowing an agent on one to access the other P Bootstrap Processor B U Chassis Bridge Controller A microcontroller connected to one or more other CBCs Together they bridge the IPMB buses of multiple chassis Command Line Interface CLTT Closed Loop Thermal Throttling memory throttling mode B C C CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory on the server board B P C C CSR Control and Status Register C P L C M rs Lcache Instruction cache Processor local cache dedicated for memory locations retrieved through instruction fetch operations P D cache Data cache Processor local cache dedicated for memory locations explicitly loaded and stored by running code M M B LI P S B M D E E FM FN FR FR FS FT Revision 2 0 Intel order number G64246 003 147 Glossary Intel Server Board S1400FP TPS Term EE use ed an SNMP agent hen decoding SEL entries Reliability Availability and Serviceability Rivest Cipher A A stream ciph
8. Major Connector Pin 1 Locations 2 of 2 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Overview HEATSINK ASSEMBLY ARI NO COMPONENT ALLOWED IEATSINK INSTALLATION AREA MAX COMP HEIGHT 0 047 AL OMPONENT HEIGHT RESTRICTION GROUND PADS S PLACES errors T205 OSMM MAX g MAX COMP HEIGHT 0 047 16 SOMPONENT HEIGHT RESTRICTION NO PIN THROUGHHOLE COMPONENT ZONE 0 24716 10MM MAX psy EET 7 7 OMPONENT HEIGHT RESTRICTION NO COMPONENT TRACES OR VIAS ALLOWED S d Ke a 0 28 7 10MM MAX PLACES e PU HEATSINK AREA O 283 7 2MM MAX COMPONENT HEIGHT RESTRICTION MAX HEIGHT FOR VR FET IS 0 043 See JOCKET ILM AND FINGER ACCESS KEEPOUT ZONE NO COMPONENT La SOMM MAX COMPONENT HEIGHT RESTRICTION JOCKET CAVITY 0 059 11 50MM MAX COMPONENT HEIGHT RESTRICTION COMPONENT HEIGHT RESTRICTION 0 205 08MMMAX COMPONENT HEIGHT RESTRICTION 0 10 2 54mi WM SLBA VV f NO COMPONENT ALLOWED HEF COMPONENT HEIGHT RESTRICTI 0 120 3 05MM MAX EE DETAIL A TSINK RETENTION MODULE TOUCH AREA NO COMPONENT ZONE 4 PLACES COMPONENT HEIGHT RESTRICTION 0 056 1 70MM MAX caer Ai BT BARE DIE HEATSINK ANCHOR SOLDERING AREA NO COMPONENT ALLOWED 2 PLACES 0 08 2MM MAX 2 PLACES COMPONENT HEIGHT RESTRICTION _ 0 036 PONENT HEIGHT RESTRICTION 0 54 13 72MM MAX 2 PLACES SOMPONENT HEIGHT RESTRICTION 0 24 6 10MM
9. The following table provides the pin out for this connector Table 36 Front Panel 30 pin Connector Pin out Pin Signal Pin Signal 1 SB3 3V 2 SB3 3V 3 Key 4 SB5V 5 Power LED Cathode 6 System ID LED Cathode 7 3 3V 8 System Fault LED Anode 9 HDD Activity LED Cathode 10 System Fault LED Cathode 11 Power Switch 12 NIC 1 1 2 Activity LED 13 GND Power Switch 14 NIC 1 1 2 Link LED 15 Reset Switch 16 12C SDA 17 GND Reset ID NMI Switch 18 12C SCL 19 System ID Switch 20 Chassis Intrusion 21 Pull Down 22 NIC 2 Activity LED 23 NMI to CPU Switch 24 NIC 2 Link LED 25 26 27 NIC 3 Activity LED 28 NIC 4 Activity LED 29 NIC 3 Link LED 30 NIC 4 Link LED 8 4 1 Power Sleep Button and LED Support Pressing the Power button will toggle the system power on and off This button also functions as a sleep button if enabled by an ACPI compliant operating system Pressing this button will send a signal to the integrated BMC which will power on or power off the system The power LED is a single color and is capable of supporting different indicator states as defined in the following table Table 37 Power Sleep LED Functional States Non ACPI Off System power is off and the BIOS has not initialized the chipset Non ACPI On System power ig on EEE System power is on es ACPI Mechanical is off and the operating system has not saved any context to the hard disk S4 ACPI WER Mechanica
10. Open Source Compliance Binary Driver includes Partial Source files or Open Source using MDRAID layer in Linux Revision 2 0 Intel order number G64246 003 35 Functional Architecture Intel Server Board S1400FP TPS OS Support Microsoft Windows 7 Microsoft Windows 2008 Microsoft Windows 2003 RHEL SLES other Linux variants using partial source builds Utilities Microsoft Windows GUI and CLI Linux GUI and CLI DOS CLI and EFI CLI 3 3 23 2 Intel Rapid Storage Technology RSTe Features of the embedded software RAID option Intel Rapid Storage Technology RSTe include the following Software RAID with system providing memory and CPU utilization Supported RAID Levels 0 1 5 10 o 4 Port SATA RAID 5 available standard no option key required o 8 Port SATA RAID 5 support provided with appropriate Intel RAID C600 Upgrade Key o No SAS RAID 5 support Maximum drive support 32 in arrays with 8 port SAS 16 in arrays with 4 port SAS 128 JBOD Open Source Compliance Yes uses MDRAID OS Support Microsoft Windows 7 Microsoft Windows 2008 Microsoft Windows 2003 RHEL 6 2 and later SLES 11 w SP2 and later VMware 5 x Utilities Microsoft Windows GUI and CLI Linux CLI DOS CLI and EFI CLI Uses Matrix Storage Manager for Microsoft Windows MDRAID supported in Linux Does not require a driver Note No boot drive support to targets attached through SAS expander car
11. 8 3 2 TPM connector Table 27 TPM connector Pin out 5 IRQ SERIAL Te LPC_FRAMEN 7 P3v3 GND 9 RST_IBMC_NICN 10 _ CLK_33M_TPM_CONN _ 8 3 3 Intel RAID C600 Upgrade Key Connector The server board provides one connector to support Intel RAID C600 Upgrade Key The Intel RAID C600 Upgrade Key is a small PCB board that enables different versions of RAID 5 software stack and or upgrade from SATA to SAS storage functionality The pin configuration of connector is identical and defined in the following table Table 28 Intel RAID C600 Upgrade Key Connector Pin out Pin Signal Name 1 GND 2 FM_PBG_DYN_SKU_KEY 3 GND 4 FM_SSB_SAS_SATA_RAID_ KEY 8 3 4 Local Control Panel Header Table 29 LCP Header Pin out E 6 FM_LCP_LEFTN 8 3 5 HSBP_ C Header Table 30 HSBP_I C Header Pin out Signal Name SMB_HSBP_3V3STBY_DATA SMB_HSBP_3V3STBY_CLK 8 3 6 HDD LED Header The server board includes a 2 pin hard drive activity LED header used with some SAS SATA controller add in cards The header has the following pin out Table 31 HDD LED Header Pin out Pin Signal Name Pin Signal Name 1 LED HDD ACTN 2 NA 86 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS On board Connector Header Overview 8 3 7 Chassis Intrusion Header The server board includes a 2 pin chassis intrusion header which can be used when the
12. 8181 Processor 02 microcode update not found Minor 8182 Processor 03 microcode update not found Minor 8183 Processor 04 microcode update not found Minor 8190 Watchdog timer failed on last boot Major 8198 OS boot watchdog timer failure Major 8300 Baseboard management controller failed self test Major 8305 Hot Swap Controller failure Major 83A0 Management Engine ME failed Self Test Major 83A1 Management Engine ME Failed to respond Major 84F2 Baseboard management controller failed to respond Major 84F3 Baseboard management controller in update mode Major 84F4 Sensor data record empty Major 84FF System event log full Minor 8500 Memory component could not be configured in the selected RAS mode Major 8501 DIMM Population Error Major 8520 DIMM_A1 failed test initialization Major 8521 DIMM_A2 failed test initialization Major 8522 DIMM_AS failed test initialization Major 8523 DIMM_B1 failed test initialization Major 8524 DIMM_B2 failed test initialization Major 8525 DIMM_B3 failed test initialization Major 8526 DIMM_C1 failed test initialization Major 8527 DIMM_C2 failed test initialization Major 8528 DIMM_C3 failed test initialization Major 8529 DIMM_D1 failed test initialization Major 852A DIMM_D2 failed test initialization Major 852B DIMM_D8 failed test initialization Major 852C DIMM_E1 failed test initialization Major Revision 2 0 Intel order number G64246 003 14 Appendix D POST Code Errors Intel Server Board S1400FP TPS
13. Server Board S1400FP TPS Table 61 Integrated BMC Core Sensors Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor name in SDR Power Unit Status Pwr Unit Status Sensor Oih Platform Applicability All Sensor Type Power Unit 09h Event Reading Type Sensor Specific 6Fh Event Offset Triggers 00 Power down Contrib To System Status OK 02 240 VA power down Fatal 04 A C lost 05 Soft power control failure 06 Power unit failure OK Fatal Assert De assert As and De Readable Value Offsets Event Data Trig Offset Rearm Standby Power Unit Redundancy1 Pwr Unit Redund Chassis specific Power Unit 09h Generic OBh 00 Fully Redundant OK 01 Redundancy lost Degraded 02 Redundancy degraded Degraded 03 Non redundant sufficient resources Transition from full redundant state 04 Non redundant sufficient resources Transition from insufficient state Degraded Degraded 05 Non redundant insufficient resources Fatal As and De Trig Offset Revision 2 0 Intel order number G64246 003 113 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Even
14. sensor that detects fan failure and may also be associated with a fan presence sensor for hot swap support For redundant fan configurations the fan failure and presence status determines the fan redundancy sensor state The system fans are divided into fan domains each of which has a separate fan speed control signal and a separate configurable fan control policy A fan domain can have a set of temperature and fan sensors associated with it These are used to determine the current fan domain state A fan domain has three states sleep nominal and boost The sleep and boost states have fixed but configurable through OEM SDRs fan speeds associated with them The nominal state has a variable speed determined by the fan domain policy An OEM SDR record is used to configure the fan domain policy System fan speeds are controlled through pulse width modulation PWM signals which are driven separately for each domain by integrated PWM hardware Fan speed is changed by adjusting the duty cycle which is the percentage of time the signal is driven high in each pulse 6 11 1 Thermal and Acoustic Management The S1400FP offers multiple thermal and acoustic management features to maintain comprehensive thermal protection as well as intelligent fan speed control The features can be adjusted in BIOS interface with path BIOS gt Advanced gt System Acoustic and Performance Configuration This feature refers to enhanced fan management to keep the
15. 0 Intel order number G64246 003 99 Intel Light Guided Diagnostics Intel Server Board S1400FP TPS Criticality 3 Minimum number of fans to cool the system not present or failed 4 Hard drive fault 5 Power Unit Redundancy sensor Insufficient resources offset indicates not enough power supplies present 6 In non sparing and non mirroring mode if the threshold of correctable errors is crossed within the window1 Amber Solid on Critical non Fatal alarm system has failed or shutdown recoverable 1 CPU CATERR signal asserted 2 MSID mismatch detected CATERR also asserts for this case 3 CPU 1 is missing 4 CPU ThermalTrip 5 No power good power fault 6 DIMM failure when there is only 1 DIMM present and hence no good memory presenti 7 Runtime memory uncorrectable error in non redundant mode1 8 DIMM Thermal Trip or equivalent 9 SSB Thermal Trip or equivalent 10 CPU ERR2 signal asserted 11 BMC Video memory test failed Chassis ID shows blue solid on for this condition 12 Both uBoot BMC FW images are bad Chassis ID shows blue solid on for this condition 13 240VA fault Not ready AC power off 10 3 BMC Boot Reset Status LED Indicators During the BMC boot or BMC reset process the System Status LED and System ID LED are used to indicate BMC boot process transitions and states A BMC boot will occur when AC power is first applied to the system A BMC reset will occur after a BMC FW update upon receiv
16. 1 Optional hardware supported by the server system 2 Refers to the actual channel used to send the request 6 12 1 User Model The BMC supports the IPMI 2 0 user model 15 user IDs are supported These 15 users can be assigned to any channel The following restrictions are placed on user related operations 1 User names for User IDs 1 and 2 cannot be changed These are always Null blank and root respectively 2 User 2 root always has the administrator privilege level 3 All user passwords including passwords for 1 and 2 may be modified User IDs 3 15 may be used freely with the condition that user names are unique Therefore no other users can be named Null root or any other existing user name 6 12 2 IPMB Communication Interface The IPMB communication interface uses the 100 KB s version of an 1 C bus as its physical medium For more information on 1 C specifications see The FC Bus and How to Use It The IPMB implementation in the BMC is compliant with the PMB v1 0 revision 1 0 The BMC IPMB slave address is 20h The BMC both sends and receives IPMB messages over the IPMB interface Non IPMB messages received by means of the IPMB interface are discarded Messages sent by the BMC can either be originated by the BMC such as initialization agent operation or by another source One example is KCS IPMB bridging 6 12 3 LAN Interface The BMC implements both the IPMI 1 5 and IPMI 2 0 messagin
17. 14 31818 MHz oscillator input provides the clock source for these three counters The C600 chipset provides an ISA Compatible Programmable Interrupt Controller PIC that incorporates the functionality of two 82C59 interrupt controllers The two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible In addition the C600 chipset supports a serial interrupt scheme 3 3 10 Advanced Programmable Interrupt Controller APIC In addition to the standard ISA compatible Programmable Interrupt controller PIC described in the previous section the C600 incorporates the Advanced Programmable Interrupt Controller APIC 3 3 11 Universal Serial Bus USB Controller The C600 chipset has up to two Enhanced Host Controller Interface EHCI host controllers that support USB high speed signaling High speed USB 2 0 allows data transfers up to 480 Mb s which is 40 times faster than full soeed USB The C600 chipset supports up to fourteen USB 2 0 ports All fourteen ports are high speed full speed and low speed capable 3 3 12 Gigabit Ethernet Controller The Gigabit Ethernet Controller provides a system interface using a PCI function The controller provides a full memory mapped or IO mapped interface along with a 64 bit address master support for systems using more than 4 GB of physical memory and DMA Direct Memory Addressing mechanisms for high performance data transfers Its bus master capabilities enable t
18. 7Ah Platform p u c nc SE As and Analog Trig A e specific Oth Oth De Offset P3 Therm Ctrl fatal Processor 4 nc Thermal Degraded Temperature Threshold i Control 7Bh a kane KN u e ne c Non Pont Janalog Ra A P4 Therm Ctrl fatal Processor 1 Processor Digital ERR2 Timeout 7Ch All Discrete 01 State fatal Ae and _ Trig A E 07h Asserted De Offset P1 ERR2 03h Processor 2 BEN Digital ERR2 Timeout 7Dh All Discrete 01 State fatal Asand _ Trig A S 07h Asserted De Offset P2 ERR2 03h Processor 3 Pri c ssor Digital ERR2 Timeout 7Eh SE Discrete 01 State ai Ae and _ Trig me te specific 07h Asserted De Offset P3 ERR2 03h Processor 4 Proc se i Digital A ERR2 Timeout 7Fh latons Discrete 01 State fatal Ae and _ Trig eis specific O7h Asserted De Offset P4 ERR2 03h Revision 2 0 Intel order number G64246 003 123 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Catastrophic Eege Digital f Error 80h All Discrete 01 State fatal As and Trig M Z 07h Asserted De Offset CATERR 03h Processor1 Digital MSID Mismatch Sit All Processor Discrete 01 State pe As and 8 Trig M 8
19. 87 Table 34 SATA SGPIO Header Pin out 87 Table 35 IPMB Connector Pin out 87 Table 36 Front Panel 30 pin Connector Pin out cccccccccccceceeceeeeeeeeeeeceeeeeeceeeeeeeeeeeeeseseeseeeeess 88 Table 37 Power Sleep LED Functional Gtates eneee eneee nee re errre rreren r rrnrrrnnnn nrnna 88 Table 38 NMI Signal Generation and Event Loggmg 89 Fable 39 VGA Connector BP Oe e a a a e aa ea 90 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS List of Tables Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Revision 2 0 SATA Connector Gel EE 90 SAS Connector dn DE 90 External DB9 Serial A Port Bike EEN NASA 91 Internal 9 pin Serial B Header Pin Out ENEE 91 Internal JEE Dette ee Ee eE de 91 Pin out of Internal Low Profile USB Connector for Solid State Drive ee 92 Internal Type A USB Port Pin OUt 2 ccciesseckiveesgcetees sasbuenstdderccaes dete ftaereeneerttaetueasnontes 92 SSI 4 pin Fan Header Pin Out AANEREN 92 Server Board SUMPGES eegen eset awh Eege ee 95 System Status LED State Detnmtons AEN 99 BMC Boot Reset Status LED Indicators 0 eeeeeeeeeeeeee eter eee eeeeeeeeeeeeeeeeteeeeeeeeaaees 100 Server Board De
20. 91 3 430 87 12 3 979 101 07 4 674 118 72 5 524 140 31 6 064 154 03 176 671 7 681 195 09 8 406 213 50 8 576 217 83 op Get AY wa as an US oF ne 22 Sin BR ou Hi 1 uM E a s 1811 46 00 2 611 66 32 3411 86 641 8 975 227 97 II IN ZE Hf LU Overview D ee er AR sa 0 340 ID 8 641 a 0 260 6 60 0 062 1 57 8 420 2 3 195 81 15 3 48 088 44 3 645 92 58 5 605 7 835 199 01 142 37 213 87 Figure 5 Intel Server Boards S1400FP Major Connector Pin 1 Locations 1 of 2 Revision 2 0 Intel order number G64246 003 Overview 2 381 60 48 2 955 75 06 3721 94 52 4126 104 801 4 821 122 451 6 956 176 671 7681 195 09 8 406 213 50 8 580 217 93 8 875 225 43 8 972 227 89 10 12 04 0 370 9 40 0 00 0 131 0 000 0 00 0 474 0 635 16 13 6 399 162 531 Intel Server Board S1400FP TPS FOE rss SL WE B A aama E es so II 227 33 162 05 0 013 0 331 1 007 25 571 6 465 164 21 6 659 169 14 8 921 226 60 oT om SS S S33 SR RU RG eR SE Sm Sa a a a As 2 RR Ki e o ot oa e u u 6 E D 2 E Figure 6 Intel Server Boards S1400FP
21. Code Diagnostic LED Decoder Appendix C POST Code Diagnostic LED Decoder As an aid to assist in trouble shooting a system hang that occurs during a system s Power On Self Test POST process the server board includes a bank of eight POST Code Diagnostic LEDs on the back edge of the server board During the system boot process Memory Reference Code MRC and System BIOS execute a number of memory initialization and platform configuration processes each of which is assigned a specific hex POST code number As each routine is started the given POST code number is displayed to the POST Code Diagnostic LEDs on the back edge of the server board During a POST system hang the displayed post code can be used to identify the last POST routine that was run prior to the error occurring helping to isolate the possible cause of the hang condition Each POST code is represented by eight LEDs four Green and four Amber The POST codes are divided into two nibbles an upper nibble and a lower nibble The upper nibble bits are represented by Amber Diagnostic LEDs 4 5 6 7 The lower nibble bits are represented by Green Diagnostics LEDs 0 1 2 and 3 If the bit is set in the upper and lower nibbles the corresponding LED is lit If the bit is clear the corresponding LED is off AF005568 In the following example the BIOS sends a value of ACh to the diagnostic LED decoder The LEDs are decoded as follows Note Diagnostic LEDs
22. De Temp fatal SAS Module nc Temperature Temperature Threshold Degraded P 2Dh Ge S u l c nc g Asand Analog R T A X SAS Mod specific Oth Oth c Non De Temp fatal Exit Air Chassis Ge T and Temperature Threshold Degraded As and emperature 2Eh Plat u l c nc D Analog R T A X Exit Air Temp atform Oth O1h c Non e Exi p Specific fatal Revision 2 0 Intel order number G64246 003 119 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Network Interface T Threshold De i ded emperature resho egrade Controller 2Fh All P u l c nc 7 Asand analog R T X Temperature Oth Oth c Non De LAN NIC Temp ital Fan Tachometer Chassis nc Sensors Fan Threshold Degraded S gon aFh 1 amp 9 mine S Asand analog R T Chassis specific Platform 04h Oth c Non De sensor names Specific fatal2 Fan Present SCC Fan Soch e et e a e Sensors SS an eneric Device san riggere g AONAN Platform 04h 08h inserted OK De Offset Auto Fan x Present Specific 00 Presence OK 01 Failure Degraded Power Supply 1 Sensor 02 Predictive Status 50h Chassis Power Supply Specific Failure Degraded As and _
23. External RJ45 NIC Port LED Definition Link Activity Speed LED LED LED Color LED State NIC State Green Amber Right Off 10 Mbps Amber 100 Mbps Green 1000 Mbps Green Left 7 On Active Connection Blinking 7 Transmit Receive activity 3 3 Intel C602 A Chipset Functional Overview The following sub sections will provide an overview of the key features and functions of the Intel C602 A chipset used on the server board For more comprehensive chipset specific information refer to the Intel C600 Series chipset documents ea PCI E GEN2 x2 Intel 1350 Gigabit Ethernet n EoLA E aech SR 8 SAS 3Gbps ei ae 2 gt PCI E GEN1 x1 ech SER ORT 1 EE Tey SMBUS PORTS AS D SERIAL PORT Chipset ISB a B 1 1 ye e p 2x5 HDA 4 SATA 3Gdps 2 2x5 HDR use 20 l Q SB Nr al RMM4 Lit eUSB SSD RE Vertical USB P TypeA Figure 16 Functional Block Diagram Chipset Supported Features and Functions NC SI PORT RGMII 28 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture On the Intel Server Boards 1400FP the chipset provides support for the following on board functions Digital Media Interface DMI PCI Express Interface Serial ATA SATA Controller Serial Attached SCSI SAS SATA Controller AHCI Rapid Storage Technology PCI Interface Low P
24. Filesystem List Info BMC Network Info BMC Syslog BMC Configuration Data External BMC Data Hex SEL listing Human readable sensor listing External BIOS Data BIOS configuration settings Human readable SEL listing POST codes for the two most recent boots System Data SMBIOS table for the current boot 256 bytes of PCI config data for each PCI device 76 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview Category Data Memory Map EFI and Legacy for current boot Table 19 Additional Diagnostics on Error Categor Data System Data First 256 bytes of PCI config data for each PCI device PCI error registers MSR registers MCH registers 6 12 16 Data Center Management Interface DCMI The DCMI Specification is an emerging standard that is targeted to provide a simplified management interface for Internet Portal Data Center IPDC customers It is expected to become a requirement for server platforms which are targeted for IPDCs DCMI is an IPMI based standard that builds upon a set of required PM standard commands by adding a set of DCMI specific PMI OEM commands Intel S1400 S1600 S2400 S2600 Server Platforms will be implementing the mandatory DCMI features in the BMC firmware DCMI 1 1 Errata 1 compliance Please refer to DCMI 1 1 errata 1 specification for details Only mandatory com
25. Internal 9 pin Serial B Header Pin out 6 SPB_CTS_ CTS clear to send 8 SPBRI Ri Ringindicatey 9 GND Ground 8 5 4 USB Connector Two 2x5 connectors J2J1 J2J2 on the server board provides support for two additional USB ports respectively which are recommended for front panel USB ports Table 44 Internal USB Connector Pin out Pin 6 USB_PP_CONN USB port positive signal 7 Ground a7 f 8 Ground Il 9 Key Nopin y Revision 2 0 Intel order number G64246 003 9 On board Connector Header Overview Intel Server Board S1 400FP TPS One low profile 2x5 connector J2E1 on the server boards provides an option to support a low profile USB Solid State Drive Table 45 Pin out of Internal Low Profile USB Connector for Solid State Drive Pin Signal Pin Signal 1 5V 6 NC 2 USB_N 7 NC 3 USB_P 8 NC 4 GND 9 NC 5 Key Pin 10 LED The server board provides one additional Type A USB port J1B1 to support the installation of a USB device inside the server chassis Table 46 Internal Type A USB Port Pin out Signal Name USB_PWR7_5V USB_PWR USB_PN USB port negative signal USB PP USB port positive signal 8 6 Fan Headers The server board provides five SSl compliant 4 pin fans to use as CPU and I O cooling fans 3 pin fans are supported on all fan headers The pin configuration for each of the 4 pin fan headers is identical and defined in t
26. MOUNTING HOLE AREA NO COMPONENT NO ROUTING AREA PLACES Overview UNG END NO COMPONENT ALLOWED en BETWEEN 2 LINES D 045 ROUTING AT THE BOTTOM LAYER BETWEEN Ze e RO COMPONENT ALLOWED THE NO ROUTING AREA ABOVE INCLUDED DETAL 8 SCALE 3 000 Figure 10 Intel Server Boards S1400FP Second Side Keepout Zone 13 Overview Intel Server Board S1400FP TPS 2 2 3 Server Board Rear I O Layout The following drawing shows the layout of the rear I O components for the server board AF005208 A Serial Port A E NIC Port 3 top NIC Port 4 bottom for S1400FP4 only B Video Port F Diagnostic LEDs C NIC Port 1 USB 0 1 G ID LED D NIC Port 2 USB 2 3 H System Status LED Figure 11 Intel Server Boards 1400FP Rear I O Layout 14 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Functional Architecture 3 Functional Architecture The architecture and design of the Intel Server Board S1400FP is based on the Intel C600 chipset The chipset is designed for systems based on the Intel Xeon processor in an FC LGA 1356 Socket B2 package with Intel QuickPath Interconnect Intel QPI This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards DDR II MEMORY Intel Xeon CHANNEL gt Ko Processor 5 2400 ED Family lt
27. Major 854D DIMM_E2 disabled Major 854E DIMM_E3 disabled Major 854F DIMM_F1 disabled Major 8550 DIMM_F2 disabled Major 8551 DIMM_F3 disabled Major 8552 DIMM_G1 disabled Major 8553 DIMM_G2 disabled Major 8554 DIMM_G3 disabled Major 8555 DIMM_H1 disabled Major 8556 DIMM_Ha2 disabled Major 8557 DIMM_H3 disabled Major 8558 DIMM_I1 disabled Major 8559 DIMM_12 disabled Major 855A DIMM_1I3 disabled Major 855B DIMM_J1 disabled Major 855C DIMM_J2 disabled Major 855D DIMM_J3 disabled Major 855E DIMM_K1 disabled Major 855F DIMM_K2 disabled Major Go to 85D0 8560 DIMM_A1 encountered a Serial Presence Detection SPD failure Major 8561 DIMM_A2 encountered a Serial Presence Detection SPD failure Major 8562 DIMM_A3 encountered a Serial Presence Detection SPD failure Major 142 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix D POST Code Errors Error Code Error Message Response 8563 DIMM_B1 encountered a Serial Presence Detection SPD failure Major 8564 DIMM_B2 encountered a Serial Presence Detection SPD failure Major 8565 DIMM_B3 encountered a Serial Presence Detection SPD failure Major 8566 DIMM_C1 encountered a Serial Presence Detection SPD failure Major 8567 DIMM_C2 encountered a Serial Presence D
28. Margin 6 Agg Therm Mrgn 6 CDh Platform Specific Temperature Oth Threshold O1h Analog R T Global Aggregate Temperature Margin 7 Agg Therm Mron 7 CEh Platform Specific Temperature Oth Threshold O1h Analog R T 130 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Global Aggregate Temperature Platform Temperature Threshold Margin 8 CFh Specific Oth Oth Analog R T A Agg Therm Mrgn 8 nc Baseboard 12V Degraded Doh All Voltage Threshold u l e ne g As and Analog R T A A BB 12 0V 02h Oth c Non De fatal nc Baseboard 5V Degraded Dih All Ke GE u l fend q Ge and analog 187 A BB 5 0V c Non e fatal P Poad Volt Threshold Gene lasaia 3 3V D2h All GE E 9 u l c nc Ge an Analog R T A BB 3 3V C Non fatal Baseboard 5V nc Stand by Voltage Threshold Degraded As and D3h All u l c nc Analo R T A x BB 5 0V 02h Oth u l fe ne c Non De S STBY fatal ere Volt Threshold Degraded As and 3 3V Auxiliary D4h All Rr HS GE u 1 c nc Ge Se
29. Messages Error Code Error Message Response 0012 System RTC date time not set Major 0048 Password check failed Major 0140 PCI component encountered a PERR error Major 0141 PCI resource conflict Major 0146 PCI out of resources error Major 0191 Processor core thread count mismatch detected Fatal 0192 Processor cache size mismatch detected Fatal 0194 Processor family mismatch detected Fatal 0195 Processor Intel R QPI link frequencies unable to synchronize Fatal 0196 Processor model mismatch detected Fatal 0197 Processor frequencies unable to synchronize Fatal 5220 BIOS Settings reset to default settings Major 5221 Passwords cleared by jumper Major 5224 Password clear jumper is Set Major 8130 Processor 01 disabled Major 8131 Processor 02 disabled Major 8132 Processor 03 disabled Major 8133 Processor 04 disabled Major 8160 Processor 01 unable to apply microcode update Major 8161 Processor 02 unable to apply microcode update Major 8162 Processor 03 unable to apply microcode update Major 8163 Processor 04 unable to apply microcode update Major 8170 Processor 01 failed Self Test BIST Major 8171 Processor 02 failed Self Test BIST Major 8172 Processor 03 failed Self Test BIST Major 8173 Processor 04 failed Self Test BIST Major 8180 Processor 01 microcode update not found Minor
30. NIC 1 MAC address for OS usage NIC 2 MAC address NIC 1 MAC address 1 for OS usage BMC LAN channel 1 MAC address NIC1 MAC address 2 BMC LAN channel 2 MAC address NIC1 MAC address 3 BMC LAN channel 3 RMM MAC address NIC MAC address 4 The printed MAC address on the server board and or server system is assigned to NIC1 on the server board For security reasons embedded LAN channels have the following default settings P Address Static All users disabled IPMl enabled network interfaces may not be placed on the same subnet This includes the Intel Dedicated Server Management NIC and either of the BMC s embedded network interfaces Host BMC communication over the same physical LAN connection also known as loopback is not supported This includes ping operations On server boards with more than two onboard NIC ports only the first two ports can be used as BMC LAN channels The remaining ports have no BMC connectivity Maximum bandwidth supported by BMC LAN channels are as follows BMC LAN1 Baseboard NIC port 100Mb 10Mb in DC off state BMC LAN 2 Baseboard NIC port 100Mb 10Mb in DC off state BMC LAN 3 Dedicated NIC 1000Mb 6 12 3 3 IPv6 Support In addition to IPv4 the server board has support for IPv6 for manageability channels Configuration of IPv6 is provided by extensions to the PMI Set and Get LAN Configuration Parameters commands as well as through a Web Co
31. Oth a exceeded EES ee Offset M P2 VRD Hot Processor 3 E VRD Temperature Je 01 Limit As and Trig iscrete 8 Temperature ed AN Oth DE exceeded Fall De Offset NM P3 VRD Hot Processor 4 wo VRD Temperature Jo 01 Limit As and Trig iscrete Temperature 33h gei Oth O5h exceeded SES De Offset M P4 VRD Hot Processor 1 Memory VRD Digital ae Temperature Hot 0 1 94h All p Discrete 01 Limit Non fatal As and Trig A E oih exceeded De Offset P1 Mem01 VRD 05h Hot Processor 1 Memory VRD Temperature Digital 01 Limit A d Tri Hot 2 3 95h All Discrete Ph Non fatal San z ng A z oih exceeded De Offset P1 Mem23 VRD 05h Hot Processor 2 Memory VRD Temperature Digital 01 Limit A d Tri Hot 0 1 96h All Discrete AM Non fatal Sa ng A oih exceeded De Offset P2 Mem01 VRD 05h Hot Revision 2 0 Intel order number G64246 003 125 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Processor 2 Memory VRD Temperature Digital 01 Limit A d Tri Hot 2 3 97h All Discrete gent Non fatal SANG a ng A z Oth exceeded De Offset P2 Mem23 VRD 05h Hot Processor 3 Memory VRD Temperature Digital 01 Limit A d Tri Hot 0 1 98h A
32. OxCC Invalid Data Field in Request completion code and the subnet mask is not set If no valid mask has been previously set default subnet mask is 0 0 0 0 Revision 2 0 Intel order number G64246 003 67 Platform Management Functional Overview Intel Server Board S1400FP TPS 2 The user may only set a default gateway address that can potentially exist within the subnet specified above Default gateway addresses outside the BMC s subnet are technically unreachable and the BMC will not set the default gateway address to an unreachable value The BMC returns a OxCC Invalid Data Field in Request completion code for default gateway addresses outside its subnet 3 If acommand is issued to set the default gateway IP address before the BMC s IP address and subnet mask are set the default gateway IP address is not updated and the BMC returns OxCC If the BMC s IP address on a LAN channel changes while a LAN session is in progress over that channel the BMC does not take action to close the session except through a normal session timeout The remote client must re sync with the new IP address The BMC s new IP address is only available in band through the Get LAN Configuration Parameters command 6 12 3 5 3 Enabling Disabling Dynamic Host Configuration DHCP Protocol The BMC DHCP feature is activated by using the Set LAN Configuration Parameter command to set LAN configuration parameter 4 P Address Source to 2h address obtained b
33. P1 MSID 07h Asserted De Offset 03h Mismatch Processor GE Digital Population Fault 82h All Discrete 01 State Fatal As and 2 Trig M 8 GEN 07h Asserted De Offset CPU Missing 03h Processor 1 DTS Thermal Margin Temperature Threshold 83h All Analog R T A P1 DTS Therm Oih Oth Mgn Processor 2 DTS Thermal Margin Temperature Threshold 84h All Analog R T A P2 DTS Therm Oih Oth Mgn Processor 3 DTS Thermal Margin Temperature Threshold 85h All Analog R T A P3 DTS Therm Oih Oth Mgn Processor 4 DTS Thermal Margin Temperature Threshold In 86h All P e Analog R T a l P4 DTS Therm Oih Oth Mgn Processor2 Digital MSID Mismatch 87h All Processor Discrete 01 State fatal As and Trig M 8 P2 MSID 07h Asserted De Offset 03h Mismatch 124 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Processor 1 Digital VRD Temperature Ode 01 Limit As and Trig iscrete 2 Temperature 90h al Oth fe exceeded Non fatal De Offset M P1 VRD Hot Processor 2 Ze VRD Temperature OC 01 Limit As and Trig iscrete d Temperature a Al
34. PC Client Specification Revision 1 2 When available Intel Trusted Execution Technology can be enabled or disabled in the processor from a BIOS Setup option For general information about Intel TXT visit the Intel Trusted Execution Technology website http www intel com technology security 46 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Technology Support 5 Technology Support 5 1 me Trusted Execution Technology The Intel Xeon Processor E5 4600 2600 2400 1600 Product Families support Intel Trusted Execution Technology Intel TXT which is a robust security environment designed to help protect against software based attacks Intel Trusted Execution Technology integrates new security features and capabilities into the processor chipset and other platform components When used in conjunction with Intel Virtualization Technology and Intel VT for Directed IO with an active TPM Intel Trusted Execution Technology provides hardware rooted trust for your virtual applications 5 2 Intel Virtualization Technology Intel VT x VT d VT c Intel Virtualization Technology consists of three components which are integrated and interrelated but which address different areas of Virtualization Intel Virtualization Technology VT x is processor related and provides capabilities needed to provide hardware assist to a Virtual Machine Monitor VMM Intel Virtualization Technolog
35. POST Reclaim of non critical NVRAM variables Minor 8605 BIOS Settings are corrupted Major 8606 NVRAM variable space was corrupted and has been reinitialized Major 92A3 Serial port component was not detected Major 92A9 Serial port component encountered a resource conflict error Major A000 TPM device not detected Minor A001 TPM device missing or not responding Minor A002 TPM device failure Minor A003 TPM device failed self test Minor A100 BIOS ACM Error Major A421 PCI component encountered a SERR error Fatal A5A0 PCI Express component encountered a PERR error Minor A5A1 PCI Express component encountered an SERR error Fatal AGAO DXE Boot Service driver Not enough memory available to shadow a Legacy Minor Option ROM POST Error Beep Codes The following table lists the POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users on error conditions The beep code is followed by a USEer VI isible code on the POST Progress LEDs Table 67 POST Error Beep Codes POST Progress Code El device action Short beep sounded whenever a USB device is discovered in POST or inserted or removed during runtime a long violation Intel TXT security eee error OxAE OxAF System halted because Intel Trusted Execution pe Technology detected a potential violation of system security was detected E Recovery NA Recovery boot has been initiated started 144 Intel orde
36. Pilot III Emulex Pilot Ill Baseboard Management Controller Functionality The Integrated BMC is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMl based server management Firmware usage of these hardware features is platform dependent The following is a summary of the Integrated BMC management hardware features that comprise the BMC 54 400MHz 32 bit ARM9 processor with memory management unit MMU Two independent10 100 1000 Ethernet Controllers with Reduced Media Independent Interface RMII Reduced Gigabit Media Independent Interface RGMII support DDR2 3 16 bit interface with up to 800 MHz operation 16 10 bit ADCs Sixteen fan tachometers Eight Pulse Width Modulators PWM Chassis intrusion logic JTAG Master Eight I C interfaces with master slave and SMBus timeout support All interfaces are SMBus 2 0 compliant Parallel general purpose I O Ports 16 direct 32 shared Serial general purpose I O Ports 80 in and 80 out Three UARTs Platform Environmental Control Interface PECI Six general purpose timers Interrupt controller Multiple Serial Peripheral Interface SPI flash interfaces NAND Memory interface Sixteen mailbox registers for communication between the BMC and host LPC ROM interface BMC watchdog timer capability SD MMC card controller with DMA support LED support with programmable blink rate controls on GPIOs Port 80h snooping capability
37. Product Description Kit Contents Benefits Code AXXRMMALITE Intel Remote Management Module 4 RMM4 Lite Activation Key Enables KVM and media Lite redirection from onboard NIC AXXRMM4 Intel Remote Management Module 4 RMM4 Lite Activation Key Dedicated NIC for Dedicated NIC Port Module management traffic Higher bandwidth connectivity for KVM and media Redirection with 100Mbe NIC On the server board each Intel RMM4 component is installed at the following locations AF005290 Figure 21 Intel RMM4 Lite Activation Key Installation 78 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Advanced Management Feature Support RMM4 AF005435 Figure 22 Intel RMM4 Dedicated Management NIC Installation If the optional Dedicated Server Management NIC is not used then the traffic can only go through the onboard Integrated BMC shared NIC and will share network bandwidth with the host system Advanced manageability features are supported over all NIC ports enabled for server manageability 7 1 Keyboard Video and Mouse KVM Redirection The BMC firmware supports keyboard video and mouse redirection KVM over LAN This feature is available remotely from the embedded web server as a Java applet This feature is only enabled when the Intel RMM4 lite is present The client system must have a Java Runtime Environment JRE version 6 0 or later to run the KVM
38. SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES SUBCONTRACTORS AND AFFILIATES AND THE DIRECTORS OFFICERS AND EMPLOYEES OF EACH HARMLESS AGAINST ALL CLAIMS COSTS DAMAGES AND EXPENSES AND REASONABLE ATTORNEYS FEES ARISING OUT OF DIRECTLY OR INDIRECTLY ANY CLAIM OF PRODUCT LIABILITY PERSONAL INJURY OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN MANUFACTURE OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literature may be o
39. Server Board S1400FP provides TPM settings through the security screen To access this screen from the Main screen select the Security option Advanced Server Management Boot Options Boot Manager Figure 19 Setup Utility TPM Configuration Screen 44 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS System Security Table 10 TPM Setup Utility Security Configuration Screen Fields Setup Item Options Help Text Comments TPM State Enabled and Information only Activated Shows the current TPM device Enabled and state Deactivated Disabled and A disabled TPM device will not Activated execute commands that use TPM Disabled and functions and TPM security Deactivated operations will not be available An enabled and deactivated TPM is in the same state as a disabled TPM except setting of TPM ownership is allowed if not present already An enabled and activated TPM executes all commands that use TPM functions and TPM security operations will be available TPM No Operation No Operation No changes to Administrative Turn On current state Control Turn Off Turn On Enables and activates Clear Ownership TPM Turn Off Disables and deactivates TPM Clear Ownership Removes the TPM ownership authentication and returns the TPM to a factory default state Note The BIOS setting returns to No Operation on every boot cycle by default 4 3 Intel Trusted Execu
40. The output connector ground pins are connected to the safety ground power supply enclosure This grounding is well designed to ensure passing the max allowed Common Mode Noise levels The power supply is provided with a reliable protective earth ground All secondary circuits are connected to protective earth ground Resistance of the ground returns to chassis does not exceed 1 0 mQ This path may be used to carry DC current 12 1 8 Residual Volatge Immunity in Standy mode The power supply is immune to any residual voltage placed on its outputs Typically a leakage voltage through the system from standby output up to 500mV There is neither additional heat generated nor stressing of any internal components with this voltage applied to any individual or all outputs simultaneously It also does not trip the protection circuits during turn on The residual voltage at the power supply outputs for no load condition does not exceed 100mV when AC voltage is applied and the PSON signal is de asserted 106 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Server Board Power Distribution 12 1 9 Common Mode Noise The Common Mode noise on any output does not exceed 350mV pk pk over the frequency band of 10Hz to 20MHz The measurement is made across a 1000 resistor between each of DC outputs including ground at the DC power connector and chassis ground power subsystem enclosure The test set up shall use a FET probe s
41. The BMC provides an embedded lite version of SM CLP that is syntax compatible but not considered fully compliant with the DMTF standards The SM CLP utilized by a remote user by connecting a remote system through one of the system NICs It is possible for third party management applications to create scripts using this CLP and execute them on server to retrieve information or perform management tasks such as reboot the server configure events and so on The BMC embedded SM CLP feature includes the following capabilities Power on off reset the server Get the system power state Clear the System Event Log SEL Get the interpreted SEL in a readable format Initiate terminate an Serial Over LAN session Support help to provide helpful information Get set the system ID LED Get the system GUID Get set configuration of user accounts Get set configuration of LAN parameters Embedded CLP communication should support SSH connection Provide current status of platform sensors including current values Sensors include voltage temperature fans power supplies and redundancy power unit and fan redundancy The embedded web server is supported over any system NIC port that is enabled for server management capabilities 72 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview 6 12 13 Embedded Web Server BMC Base manageability provides an embedded web ser
42. The Intel QuickPath Interconnect is a high speed packetized point to point interconnect used in the processor The narrow high speed links stitch together processors in distributed shared memory and integrated I O platform architecture It offers much higher bandwidth with low latency The Intel QuickPath Interconnect has an efficient architecture allowing more interconnect performance to be achieved in real systems It has a snoop protocol optimized for low latency and high scalability as well as packet and lane structures enabling quick completions of transactions Reliability availability and serviceability features RAS are built into the architecture The physical connectivity of each interconnect link is made up of twenty differential signal pairs plus a differential forwarded clock Each port supports a link pair consisting of two uni directional links to complete the connection between two components This supports traffic in both directions simultaneously To facilitate flexibility and longevity the interconnect is defined as having five layers Physical Link Routing Transport and Protocol The Intel QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation It supports both low latency source snooping and a scalable home snoop behavior The coherency protocol provides for direct cache to cache transfers for optimal latency 3 2 2 Integrat
43. Trig x specific O8h De Offset PS1 Status 6Fh 03 A C lost Degraded 06 Configuration OK error 00 Presence OK 01 Failure Degraded Power Supply 2 Sensor 02 Predictive Status 5th Chassis Power Supply Specific Failure Degraded Asand _ Trig x specific 08h De Offset PS2 Status 6Fh 03 A C lost Degraded 06 Configuration OK error Power Supply 1 ee is Other Units Threshold Degraded AC Power Input 54h Chassis u c nc Asang Analog R T X specific OBh Oth c Non De PS1 Power In fatal 120 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Power Supply 2 Chassis Other Units Threshold Ge As and AC Power Input 55h ge u c nc Analog R T A xX specific OBh Oth c Non De PS2 Power In fatal Power Supply 1 12V of nc Maximum Chassis Current Threshold Degraded As and Current Output 58h specific O3h Oth u c nc ebe De Analog R T A X PS1 Curr Out fatal Power Supply 2 12V of nc Maximum Chassis Current Threshold Degraded As and Current Output 59h specific He Ser u cnc GE Analog R T A x PS2 Curr Out fatal Power
44. a CLTT table structure error Revision 2 0 Intel order number G64246 003 139 Appendix D POST Code Errors Intel Server Board S1400FP TPS Appendix D POST Code Errors Most error conditions encountered during POST are reported using POST Error Codes These codes represent specific failures warnings or are informational POST Error Codes may be displayed in the Error Manager display screen and are always logged to the System Event Log SEL Logged events are available to System Management applications including Remote and Out of Band OOB management There are exception cases in early initialization where system resources are not adequately initialized for handling POST Error Code reporting These cases are primarily Fatal Error conditions resulting from initialization of processors and memory and they are handed by a Diagnostic LED display with a system halt The following table lists the supported POST Error Codes Each error code is assigned an error type which determines the action the BIOS will take when the error is encountered Error types include Minor Major and Fatal The BIOS action for each is defined as follows Minor The error message is displayed on the screen or on the Error Manager screen and an error is logged to the SEL The system continues booting in a degraded state The user may want to replace the erroneous unit The POST Error Pause option setting in the BIOS setup does not ha
45. and Analog R T A Xx BB 3 3V AUX ae ON fatal Baseboard ies Se Volt Threshold Degraded As and Processor Vecp Det All Sa K e S u l c nc a Ge and Analog R T A z BB 1 05Vccp ea P1 fatal Revision 2 0 Intel order number G64246 003 131 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Baseboard nc SE Vol Threshold Degraded As and Processor2 Vecp D7h All EE resno ng S sand analog R T a l 02h Oth c Non De BB 1 05Vccp fatal P2 Baseboard 1 5V P1 nc Memory AB Voltage Threshold Degraded As and VDDQ D8h All 02h Oth u 1 c nc See De Analog R T A BB 1 5 fatal P1MEM AB Baseboard 1 5V P1 nc Memory CD Voltage Threshold Degraded As and VDDQ D9h All 02h Oth u l c nc SE No De Analog R T A E BB 1 5 fatal P1MEM CD Baseboard 1 5V P2 nc Memory AB Voltage Threshold Degraded As and VDDQ DAh All 02h Oth u 1 c nc Dee E De Analog R T A BB 1 5 fatal P2MEM AB Baseboard 1 5V P2 nc Memory CD Voltage Threshold Degraded As and VDDQ DBh All 02h Oth u 1 c nc SE e De Analog R T A 8 BB 1 5 fatal P2MEM CD nc Baseboard Degraded 1 8V Aux DCh All Voltage Thr
46. are best read and decoded when viewing the LEDs from the back of the system Revision 2 0 Intel order number G64246 003 135 Appendix C POST Code Diagnostic LED Decoder Intel Server Board S1400FP TPS Table 62 POST Progress Code LED Example gwe E E dea Posh an n Th rus kleene DO ee Upper nibble bits 1010b Ah Lower nibble bits 1100b Ch the two are concatenated as ACh 1h The following table provides a list of all POST progress codes Table 63 POST Progress Codes Diagnostic LED Decoder 1 LED On 0 LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h dh 1h LED 7 6 5 4 3 2 1 0 Description SEC Phase First POST code after CPU reset Microcode load begin CRAM initialization begin Pei Cache When Disabled SEC Core At Power On Begin Early CPU initialization during Sec Phase Early SB initialization during Sec Phase Early NB initialization during Sec Phase End Of Sec Phase Microcode Not Found Microcode Not Loaded PEI Core CPU PEIM NB PEIM SB PEIM MRC Process Codes MRC Progress Code Sequence is executed See Table 65 PEI Phase continued Memory Installed CPU PEIM Cpu Init CPU PEIM Cache Init CPU PEIM BSP Select CPU PEIM AP Init CPU PEIM CPU SMM Init Dxe IPL started
47. be 2 or more single rank or dual rank DIMMs or at least one quad rank DIMM installed on each memory channel Rank Sparing Mode is enabled or disabled in the Memory RAS and Performance Configuration screen in the lt F2 gt Bios Setup Utility When Sparing Mode is operational for each channel the largest size memory rank is reserved as a spare and is not used during normal operations The impact on Effective Memory Size is to subtract the sum of the reserved ranks from the total amount of installed memory Hardware registers count the number of Correctable ECC Errors for each rank of memory on each channel during operations and compare the count against a Correctable Error Threshold When the correctable error count for a given rank hits the threshold value that rank is deemed to be failing and it triggers a Sparing Fail Over SFO event for the channel in which that rank resides The data in the failing rank is copied to the Spare Rank for that channel and the Spare Rank replaces the failing rank in the IMC s address translation registers An SFO Event is logged to the BMC SEL The failing rank is then disabled and any further Correctable Errors on that now non redundant channel will be disregarded Revision 2 0 Intel order number G64246 003 23 Functional Architecture Intel Server Board S1400FP TPS The correctable error that triggered the SFO may be logged to the BMC SEL if it was the first one to occur in the system Th
48. correctable error threshold Correctable error counts accumulate by rank and the first event is logged What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error occurring with critical data in process Without Mirroring the system would be expected to Blue Screen and halt possibly with serious impact to operations But with Mirroring Mode in operation an Uncorrectable ECC Error from one channel becomes a Mirroring Fail Over MFO event instead in which the IMC retrieves the correct data from the mirror image channel and disables the failed channel Since the ECC Error was corrected in the process of the MFO Event the ECC Error is demoted to a Correctable ECC Error The channel pair becomes a single non redundant channel but without impacting operations and the Mirroring Fail Over Event is logged to SEL to alert the user that there is memory hardware that has failed and needs to be replaced In Mirrored Channel Mode the memory contents are mirrored between Channel B and Channel C As a result of the mirroring the total physical memory available to the system is half of what is populated Mirrored Channel Mode requires that Channel B and Channel C must be populated identically with regards to size and organization DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel B and Channel C must be populated the same 3 2 2 4 4 Lockstep Cha
49. during the boot sequence the system is placed into a halt state A system reset is required to exit out of the halt state This feature makes it more difficult to guess or break a password In addition on the next successful reboot the Error Manager displays a Major Error code 0048 which also logs a SEL event to alert the authorized user or administrator that a password access failure has occurred 4 2 Trusted Platform Module TPM Support Trusted Platform Module TPM option is a hardware based security device that addresses the growing concern on boot process integrity and offers better data protection TPM protects the system start up process by ensuring it is tamper free before releasing system control to the operating system A TPM device provides secured storage to store data such as security keys and passwords In addition a TPM device has encryption and hash functions The server board implements TPM as per TPM PC Client Specifications Revision 1 2 by the Trusted Computing Group TCG A TPM device is optionally installed onto a high density 14 pin connector labeled TPM and is secured from external software attacks and physical theft A pre boot environment such as the BIOS and operating system loader uses the TPM to collect and store unique measurements from multiple factors within the boot process to create a system fingerprint This unique fingerprint remains the same unless the pre boot environment is tampered with There
50. have to be configured accordingly 7 1 2 Performance The remote display accurately represents the local display The feature adapts to changes to the video resolution of the local display and continues to work smoothly when the system transitions from graphics to text or vice versa The responsiveness may be slightly delayed depending on the bandwidth and latency of the network Enabling KVM and or media encryption will degrade performance Enabling video compression provides the fastest response while disabling compression provides better video quality For the best possible KVM performance a 2Mb sec link or higher is recommended 80 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Advanced Management Feature Support RMM4 The redirection of KVM over IP is performed in parallel with the local KVM without affecting the local KVM operation 7 1 3 Security The KVM redirection feature supports multiple encryption algorithms including RC4 and AES The actual algorithm that is used is negotiated with the client based on the client s capabilities 7 14 Availability The remote KVM session is available even when the server is powered off in stand by mode No re start of the remote KVM session shall be required during a server reset or power on off An BMC reset for example due to an BMC Watchdog initiated reset or BMC reset after BMC FW update will require the session to be re established KVM sessio
51. intel Intel Server Board 1400FP Technical Product Specification Intel order number G64246 003 SERVER Revision 2 0 BOARD inside December 2013 Platform Collaboration and Systems Division Marketing Revision History Intel Server Board S1 400FP TPS Revision History Modifications July 2012 2012 Initial release an 2012 1 1 e Updated Table 1 e Correct errors in Table 2 e Updated Appendix E December 2013 Added support for Intel Xeon processor E5 2400 v2 product family ii Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT A Mission Critical Application is any application in which failure of the Intel Product could result directly or indirectly in personal injury or death SHOULD YOU PURCHASE OR USE INTEL S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION YOU
52. made to the throttling during runtime based on changes in system cooling fan speed Dynamic Closed Loop Thermal Throttling Dynamic CLTT CLTT control registers are configured by BIOS MRC during POST The memory throttling is run as a closed loop system with the DIMM temperature sensors as the control input Adjustments are made to the throttling during runtime based on changes in system cooling fan speed Both Static and Dynamic CLTT modes implement a Hybrid Closed Loop Thermal Throttling mechanism where the Integrated Memory Controller estimates the DRAM temperature in between actual reads of the memory thermal sensors 6 12 Messaging Interfaces The BMC supports the following communications interfaces Host SMS interface by means of low pin count LPC keyboard controller style KCS interface Host SMM interface by means of low pin count LPC keyboard controller style KCS interface Intelligent Platform Management Bus IPMB DC interface LAN interface using the IPMl over LAN protocols Every messaging interface is assigned an IPMI channel ID by IPMI 2 0 Table 16 Messaging Interfaces Channel ID Interface Supports one 0 Primary IPMB EC 3 LAN 3 Yes Provided by the Intel Dedicated Server Management NIC E E 62 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview ea amp 00h EE SMS Receive Message Queue Notes
53. management and members of the VLAN will be isolated from any other network traffic Please note that VLAN does not change the behavior of the host network setting it only affects the BMC LAN communication LAN configuration options are now supported by means of the Set LAN Config Parameters command parameters 20 and 21 that allow support for 802 1Q VLAN Layer 2 This allows VLAN headers packets to be used for IPMI LAN sessions VLAN IDs are entered and enabled Revision 2 0 Intel order number G64246 003 69 Platform Management Functional Overview Intel Server Board S1400FP TPS by means of parameter 20 of the Set LAN Config Parameters PMI command When a VLAN ID is configured and enabled the BMC only accepts packets with that VLAN tag ID Conversely all BMC generated LAN packets on the channel include the given VLAN tag ID Valid VLAN IDs are 1 through 4094 VLAN IDs of 0 and 4095 are reserved per the 802 1Q VLAN Specification Only one VLAN can be enabled at any point in time on a LAN channel If an existing VLAN is enabled it must first be disabled prior to configuring a new VLAN on the same LAN channel Parameter 21 VLAN Priority of the Set LAN Config Parameters PMI command is now implemented and a range from 0 7 will be allowed for VLAN Priorities Please note that bits 3 and 4 of Parameter 21 are considered Reserved bits Parameter 25 VLAN Destination Address of the Set LAN Config Parameters IPMI command is not supported and re
54. or media redirection applets The BMC supports an embedded KVM application Remote Console that can be launched from the embedded web server from a remote console USB1 1 or USB 2 0 based mouse and keyboard redirection are supported It is also possible to use the KVM redirection KVM r session concurrently with media redirection media r This feature allows a user to interactively use the keyboard video and mouse KVM functions of the remote server as if the user were physically at the managed server KVM redirection console support the following keyboard layouts English Dutch French German Italian Russian and Spanish Revision 2 0 Intel order number G64246 003 79 Advanced Management Feature Support RMM4 Intel Server Board S1400FP TPS KVM redirection includes a soft keyboard function The soft keyboard is used to simulate an entire keyboard that is connected to the remote system The soft keyboard functionality supports the following layouts English Dutch French German Italian Russian and Spanish The KVM redirection feature automatically senses video resolution for best possible screen capture and provides high performance mouse tracking and synchronization It allows remote viewing and configuration in pre boot POST and BIOS setup once BIOS has initialized video Other attributes of this feature include Encryption of the redirected screen keyboard and mouse Compression of the redirected scr
55. sensors that are readable with the Get Sensor Reading command Unless indicated all event triggers are readable Readable Offsets consist of the reading type offsets that do not generate events Event Data Event data is the data included in an event message generated by the sensor For threshold based sensors the following abbreviations are used R Reading value IT Threshold value Revision 2 0 Intel order number G64246 003 111 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS 112 Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states You can rearm the sensors manually or automatically This column indicates the type supported by the sensor The following abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm Default Hysteresis The hysteresis setting applies to all thresholds of the sensor This column provides the count of hysteresis for the sensor which is 1 or 2 positive or negative hysteresis Criticality Criticality is a classification of the severity and nature of the condition It also controls the behavior of the Control Panel Status LED Standby Some sensors operate on standby power You can access these sensors and or generate events when the main system power is off but AC power is present Intel order number G64246 003 Revision 2 0 Intel
56. the following system degradations that will require a system reset or power cycle to correct 1 Timeout value for the rotation period can be set using this parameter Potentially there will be incorrect ACPI Power State reported by the BMC 2 Reversion of temporary test modes for the BMC back to normal operational modes 3 FP status LED and DIMM fault LEDs may not reflect BIOS detected errors 6 7 Fault Resilient Booting FRB Fault resilient booting FRB is a set of BIOS and BMC algorithms and hardware support that allow a multiprocessor system to boot even if the bootstrap processor BSP fails Only FRB2 is supported using watchdog timer commands FRB2 refers to the FRB algorithm that detects system failures during POST The BIOS uses the BMC watchdog timer to back up its operation during POST The BIOS configures the watchdog timer to indicate that the BIOS is using the timer for the FRB2 phase of the boot operation 56 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview After the BIOS has identified and saved the BSP information it sets the FRB2 timer use bit and loads the watchdog timer with the new timeout interval If the watchdog timer expires while the watchdog use bit is set to FRB2 the BMC if so configured logs a watchdog expiration event showing the FRB2 timeout in the event data bytes The BMC then hard resets the system assuming the BIOS selected rese
57. to change the BIOS boot order to boot from this remote device Itis possible to install an operating system on a bare metal server no OS present using the remotely mounted device This may also require the use of KVM r to configure the OS during install USB storage devices will appear as floppy disks over media redirection This allows for the installation of device drivers during OS installation If either a virtual IDE or virtual floppy device is remotely attached during system boot both the virtual IDE and virtual floppy are presented as bootable devices It is not possible to present only a single mounted device type to the system BIOS 7 2 1 Availability The default inactivity timeout is 30 minutes and is not user configurable Media redirection sessions persist across system reset but not across an AC power loss or BMC reset 7 2 2 Network Port Usage The KVM and media redirection features use the following ports 5120 CD Redirection 5123 FD Redirection 5124 CD Redirection Secure 5127 FD Redirection Secure 7578 Video Redirection 7582 Video Redirection Secure 82 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS On board Connector Header Overview 8 On board Connector Header Overview The following section provides detailed information regarding all connectors headers and jumpers on the server boards 8 1 Board Connector Information The following table l
58. two parts the upper network portion comes from the router and the lower unique portion comes from the BMC s channel MAC address The 6 byte MAC address is converted into an 8 byte value per the EUI 64 standard For example a MAC value of 00 15 17 FE 2F 62 converts into a EUI 64 value of 215 17ff fefe 2f62 If the BMC receives a Router Advertisement from a router at IP 1 2 3 4 1 with a prefix of 64 it would then generate for itself an IP of 1 2 3 4 215 1 7ff fefe 2f62 The IP Prefix and Gateway are read only parameters to the BMC user in this mode IPv6 can be used with the BMC s Web Console JViewer remote KVM and Media and Systems Management Architecture for Server Hardware Command Line Protocol SMASH CLP interface ssh There is no standard yet on how IPMI RMCP or RMCP should operate over IPv6 so that is not currently supported 6 12 3 4 LAN Failover The BMC FW provides a LAN failover capability such that the failure of the system HW associated with one LAN link will result in traffic being rerouted to an alternate link This functionality is configurable using IPMI methods as well as the BMC s Embedded UI allowing the user to specify whether the physical LAN links constitute the redundant network paths or the physical LAN links constitute different network paths BMC will support only all or nothing approach that is all interfaces bonded together or none are bonded together The LAN Failover feature applies
59. 2 0 for sensor and event reading type table information Sensor Type The Sensor Type is the value enumerated in the Sensor Type Codes table in the IPMI Specification The Sensor Type provides the context in which to interpret the sensor such as the physical entity or characteristic represented by this sensor Event Reading Type The Event Reading Type values are from the Event Reading Type Code Ranges and Generic Event Reading Type Codes tables in the IPMI Specification Digital sensors are a specific type of discrete sensor with only two states Event Offset Triggers Event Thresholds are event generating thresholds for threshold type sensors u l nr c nc upper nonrecoverable upper critical upper noncritical lower nonrecoverable lower critical lower noncritical uC Ic upper critical lower critical Event Triggers are supported event generating offsets for discrete type sensors You can find the offsets in the Generic Event Reading Type Codes or Sensor Type Codes tables in the IPMI Specification depending on whether the sensor event reading type is generic or a sensor specific response Assertion De assertion Enables Assertion and de assertion indicators reveal the type of events the sensor generates As Assertions De De assertion Readable Value Offsets Readable Values indicate the type of value returned for threshold and other non discrete type sensors Readable Offsets indicate the offsets for discrete
60. 20 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Functional Architecture DIMM C2 C1 B2 B1 A2 A1 a vn M LW Dae Adi o T 4 a e m ce vn Lol we KH SS EH GE AF005206 Figure 14 Intel Server Board S1400FP DIMM Slot Layout The following are generic DIMM population requirements that generally apply to the Intel Server Board S1400FP All DIMMs must be DDR3 DIMMs Registered DIMMs must be ECC only unbuffered DIMMs can be ECC or non ECC However Intel only validates and supports ECC memory for its server products Mixing of Registered and Unbuffered DIMMs is not allowed per platform Mixing of DDR3 voltages is not validated within a socket or across sockets by Intel If 1 35V DDR3L and 1 50V DDR3 DIMMs are mixed the DIMMs will run at 1 50V Mixing of DDR3 operating frequencies is not validated within a socket or across sockets by Intel If DIMMs with different frequencies are mixed all DIMMs will run at the common lowest frequency Quad rank DIMMs are NOT supported LR Load Reduced DIMMs are NOT supported A maximum of 4 logical ranks ranks seen by the host per channel is allowed Mixing of ECC and non ECC DIMMs is not allowed per platform DIMMs with different timing parameters can be installed on different slots within the same channel but only timings that support the slowest D
61. 46 003 39 Functional Architecture Intel Server Board S1400FP TPS Hardware based Video Compression and Redirection Logic Supports both text and Graphics redirection Hardware assisted Video redirection using the Frame Processing Engine Direct interface to the Integrated Graphics Controller registers and Frame buffer Hardware based encryption engine 3 4 3 2 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10 100 network interfaces These interfaces are not shared with the host system At any time only one dedicated interface may be enabled for management traffic The default active interface is the NIC 1 port For these channels support can be enabled for IPMl over LAN and DHCP For security reasons embedded LAN channels have the following default settings P Address Static All users disabled 40 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS System Security 4 System Security 4 1 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup Passwords can restrict entry to the BIOS Setup restrict use of the Boot Popup menu and suppress automatic USB device reordering There is also an option to require a Power On password entry to boot the system If the Power On Password function is enabled in Setup the BIOS will halt early in POST to request a password before continuing POST Both Administra
62. 6 003 93 Jumper Blocks Intel Server Board S1400FP TPS 9 Jumper Blocks The server board has several 3 pin jumper blocks that can be used to configure protect or recover specific features of the server boards The following symbol identifies Pin 1 on each jumper block on the silkscreen Y nn J CH om I Ea I EEH 7 t D E I mettle BIOS Default Default 2 l Ian Clear oy Zi amc do Force Default Update H Enabled J3J2 3 og oD oD Do Do oD oD Do Do oD oD Do Chassis Intrusion Header EB LE E ME ot le O Force F Default BIOS Default Password Default Update 2 3 Recovery 2 Clear 5 F Enabled H Recover D Password Jam do ER 43 2 3335 do Clear AF005203 Figure 23 Jumper Blocks Note 1 For safety purposes the power cord should be disconnected from a system before removing any system components or moving any of the on board jumper blocks 2 System Update and Recovery files are includ
63. 74 Virtual Front Panel is the module present as Virtual Front Panel on the left side in the embedded web server when remote Control tab is clicked Main Purpose of the Virtual Front Panel is to provide the front panel functionality virtually Virutal Front Panel VFP will mimic the status LED and Power LED status and Chassis ID alone It is automatically in sync with BMC every 40 seconds For any abnormal status LED state Virtual Front Panel will get the reason behind the abnormal or status LED changes and displayed in VFP side As Virtual Front Panel uses the chassis control command for power actions It will not log the Front button press event since Logging the front panel press event for Virtual Front Panel press will mislead the administrator For Reset from Virtual Front Panel the reset will be done by a Chassis contro command For Reset from Virtual Front Panel the restart cause will be because of Chassis control command During Power action Power button Reset button should not accept the next action until current Power action is complete and the acknowledgment from BMC is received EWS will provide a valid message during Power action until it completes the current Power action The VFP does not have any effect on whether the front panel is locked by Set Front Panel Enables command The chassis ID LED provides a visual indication of a system being serviced The state of the chassis ID LED is affected by the following actions o To
64. Applicability Type System assert Value Data SDR Status Offsets 06 Non Redundant degraded from fully Degraded redundant 07 Redundant degraded from Degraded non redundant Se Ee Temperature pale 01 Stat As and Tri rip Discrete State san 8 rig SSB Therm SH All Oth Asserted kata De Offset H 2 03h Trip IO Module Digital Presence OEh Platform Module Board Discrete 01 OK As and 8 Trig M i IO Mod specific 15h O8h Inserted Present De Offset Presence SAS Module Digital Presence OFh Platform Module Board Discrete 01 OK As and Trig M x SAS Mod specific 15h Osh Inserted Present De Offset Presence BMC Firmware Health Mgmt Health Sensor 04 Sensor Degraded Tri 10h All Specific Ae E g A x BMC FW 28h 6Fh Failure Offset Health System Airflow Other Units Threshold 11h All E 8 Analog System Airflow OBh Oth FW Update 12h All Version OEM defined 00h gt Update OK As Trig A Status Change 2Bh x70h started Offset 01h gt Update completed successfully 02h gt Update failure 116 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets IO Module Digital
65. C600 Upgrade Keys Upgrade keys install onto a 4 pin connector on the server board labeled STOR_UPG_KEY The following table identifies available upgrade key options and their supported features Table 7 Intel RAID C600 Upgrade Key Options Product Code Color On Server Board SATA SAS Capable Controller On Server Board AHCI Capable SATA Controller No Key N A Intel RSTE 4 ports SATA RO 1 10 5 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 4 ports SATA RO 1 10 or Intel ESRT2 SATA RO 1 10 RKSATA4R5 Black Intel RSTE A ports SATA RO 1 10 5 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 4 ports SATA RO 1 10 5 or Intel ESRT2 SATA RO 1 10 5 34 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Functional Architecture Product Code Color On Server Board SATA SAS Capable Controller On Server Board AHCI Capable SATA Controller RKSATA8 Blue Intel RSTE 8 ports SATA RO 1 10 5 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 8 ports SATA RO 1 10 or Intel ESRT2 SATA RO 1 10 RKSATA8R5 White Intel RSTE 8 ports SATA RO 1 10 5 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 8 ports SATA RO 1 10 5 or Intel ESRT2 SATA RO 1 10 5 RKSAS4 Green Intel RSTE 4 ports SAS RO 1 10 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 4 ports SAS RO 1 10 or Intel ESRT2 SATA RO 1 10 RKSAS4R5 Yellow Intel RSTE 4 ports SAS RO 1 10 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 4 ports SAS RO 1 10 5 or Int
66. Degraded Thermal Margin Temperature Threshold z 3 In Leer Platiorm p u l c nc c Non Asand analog R T A Specific 01h Oth fatal De P3 DIMM Thrm Mrgn2 Processor 4 nc DIMM Aggregate Degraded Thermal Margin Temperature Threshold 2 In Beh SE p u l c nc c Non Asand analog R T A Specific Oth Oth fatal De P4 DIMM Thrm Mrgn1 Processor 4 nc DIMM Aggregate Degraded Thermal Margin Temperature Threshold gt an en plattor p u l c nc c Non Asand analog R T A Specific Oth Oth fatal De P4 DIMM Thrm Mrgn2 Fan Tachometer Chassis nc Sensors Fan Threshold Degraded Ee BER 24 l e nc g Asand Analog R T M Chassis specific Platform 04h Oth c Non De sensor names Specific fatal2 128 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Processor 1 DIMM Memor Digital as i Thermal Trip COh All J Discrete 0A Critical Fatal EE d Trig M l OCh overtemperature De Offset P1 Mem Thrm 03h Trip Processor 2 DIMM hierar Digital e Thermal Trip Cth All y Discrete OA Critical over Fatal As and 8 Trig M DCH temperature De Offs
67. Device Data Correction SDDC for any single x4 or x8 DRAM device Independent channel mode supports x4 SDDC x8 SDDC requires lockstep mode o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in lockstep mode o Data scrambling with address to ease detection of write errors to an incorrect address o Error reporting through Machine Check Architecture o Read Retry during CRC error handling checks by iMC o Channel mirroring within a socket CPU Channel Mirror Pairs B and C o Error Containment Recovery Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling CLTT Memory thermal monitoring support for DIMM temperature 3 2 2 1 Supported Memory Table 3 UDIMM Support Guidelines E Speed MT s and Voltage Validated by e Slot per Channel SPQ and DIMM Per Channel DPQ 2 3 DIMM and Memory Capacity Per DIMM1 Data 1 Slot per Channel 2 Slots per Channel Width 1DPC 1DPC 2DPC 1 35V 1 5V 1 35V 1 5V 1 35V 1 5V n a 1066 1333 n a 1066 1333 n a 1066 n a 1066 1333 n a 1066 1333 n a 1066 n a 1066 1333 n a 1066 1333 n a 1066 1066 1066 1333 1066 1333 1333 1066 1333 1066 1066 DRx8 sep 1066 1066 ECC 2GE 1333 1066 1333 1333 1066 1333 1066 1066 Notes 1 Supported DRAM Densities are 1Gb 2Gb and 4Gb Only 2Gb and 4Gb are validated by Intel 2 Command Address Timing is 1N for 1DPC and 2N for 2DPC Supported and Validated Supp
68. EEN 58 6 11 1 Thermal and Acoustic Management 58 6 11 2 Setting Throttling Mode EE 59 6 11 37 leegen 59 6 11 4 Sel Fan e ENEE 59 611 5 Fat PWM OSSD geed aaelin canal eed ds 59 Bib Q etFanldle MEss enee Ma eege a a o e 59 GR SE ne 60 6 11 8 Thermal Sensor Input to Fan Speed Control 60 Revision 2 0 Intel order number G64246 003 Vv Table of Contents Intel Server Board S1400FP TPS 6 11 9 Memory Thermal Throttling sde tee deed EE Eege Eege 61 6 12 Messaging Interfaces EE 62 Bt User Mod e e 63 6 12 2 IPMB Communication Intertace cceccccccceeeeeeeeeeeeeeeecnneeeeeeeeeeeteeeeeeseieeeeeeeees 63 O23 CLAN ANS aCe EE 63 6 12 4 Address Resolution Protocol AP uk 69 6 12 5 Internet Control Message Protocol CMD 69 6 12 6 Virtual Local Area Network VLAN teeter ee eeeeeaeeeeeeeeeeeteseeaaaaaaeeeeeeees 69 642 7 SCCUPS GE EE 70 6 12 8 Serial over LAN SOL 2 0 eege Dessen Eege SEENEN EEN 70 6 12 9 Platform Event Filter EE 71 6 12 10 LAN ACMI DEE 71 6 12 11 Alert Policy Tabl n TE 72 6 12 12 SM CLP SM CLP Lite E 72 6 12 13 Embedded Web Genver uk 73 6 12 14 Virtual Front Panel ssteissi rnein eia a Oe EEE SEE ESES r Se a 74 6 12 15 Embedded Platform D DUG sc ccccsinticnciceesienits aig a Oa wars Gan ea eae 75 6 12 16 Data Center Management Interface DCMI ssssssssssrnsesssserenrrrnnrsssrrnrrrnnresserrnne 77 6 12 17 Lightweight Directory Authentication Protocol DAP 77 7 Advanced Management Feature Support RMM45
69. EN 88 8 4 2 System ID Button and LED Support eet Eege enee 88 8 4 3 System Reset Button Support eee ENNEN 88 8 4 4 NMI Button Support E 89 8 4 5 NIC Activity LED SUPPO EE 89 8 4 6 Hard Drive Activity LED Support eieskteedd Seege NEEN EEN 89 8 4 7 System Status LED Support 2 4c44u6adaacaGenidnaiedaeeawonee 89 8 5 VO COMING CHONG es crete adie EE 90 8 5 1 VE eene 90 8 5 2 SATA and SAS CGonnechors ENNEN 90 8 5 3 Serial Port Connectors E 91 8 5 4 USB CONNECto asserenar a a e a eee eee S 91 8 6 EE an aa e ies aa ON em ani 92 9 J mpe r EE 94 9 1 BIOS R c very JUMPE een egen Dee ebe 95 9 2 Management Engine ME Firmware Force Update Jumper Block 96 9 3 Password Clear Jumper Block AAA 96 9 4 BIOS Default JUmperiBloCk EE 97 9 5 BMC Force Update Jumper BlOCK esis scs ice Reha eeas dees kees d vide Seege gege ee 97 10 Intel Light Guided Diagnostics scscssssessssssssssssssseseseseseseeranaeatensteseseeesnananananaeaesess 98 10 1 System ID LED weiss steve tect ees ege Ee EE dee 98 10 2 System Stat s LED EE 99 10 3 BMC Boot Reset Status LED Indicators ccceeeceeeeeeeeeeeeeneeeeeeeeeeteeeenaeeeaees 100 10 4 Post Code Diagnostic RE 101 10 5 5 Volt Stand By Present LED a escescccdivcanecanrsecraneeaatenspiamne te set ae Renveuetaeetneaceres 101 10 6 Fan Fault LEDS eege sect thetsin a e a ER EA ER 101 10 7 Memory Fault EE 101 11 Environmental Limits Specification cccccccceeeeeeeeeeeeeeeeeee
70. IMM will be applied to all As a consequence faster DIMMs will be operated at timings supported by the slowest DIMM populated Revision 2 0 Intel order number G64246 003 21 Functional Architecture Intel Server Board S1400FP TPS When one DIMM is used it must be populated in the BLUE DIMM slot farthest away from the CPU of a given channel When single and dual rank DIMMs are populated for 2DPC always populate the higher number rank DIMM first starting from the farthest slot for example first dual rank and then single rank DIMM DIMM population rules require that DIMMs within a channel be populated starting with the BLUE DIMM slot or DIMM farthest from the processor in a fill farthest approach Intel MRC will check for correct DIMM placement 3 2 2 3 Publishing System Memory The BIOS displays the Total Memory of the system during POST if Display Logo is disabled in the BIOS setup This is the total size of memory discovered by the BIOS during POST and is the sum of the individual sizes of installed DDR3 DIMMs in the system The BIOS displays the Effective Memory of the system in the BIOS setup The term Effective Memory refers to the total size of all DDR3 DIMMs that are active not disabled and not used as redundant units The BIOS provides the total memory of the system in the main page of the BIOS setup This total is the same as the amount described by the first bullet above H Display Logo is disable
71. Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits Disclaimer Note Intel ensures the unpackaged server board and system meet the shock requirement mentioned above through its own chassis development and system configuration It is the responsibility of the system integrator to determine the proper shock level of the board and system if the system integrator chooses different system configuration or different chassis Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits 11 1 Processor Thermal Design Power TDP Support To allow optimal operation and long term reliability of Intel processor based systems the processor must remain within the defined minimum and maximum case temperature Tcase specifications Thermal solutions not designed to provide sufficient thermal capability
72. Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Platform Support for Serial over LAN SOL TMode and Terminal Mode External Architecture Specification Version 1 1 02 01 02 Intel Corporation Inte Remote Management Module User s Guide Intel Corporation Alert Standard Format ASF Specification Version 2 0 23 April 2003 2000 2003 Distributed Management Task Force Inc http www dmit org BIOS for PCSD Platforms Based on Inte Xeon Processor E5 4600 2600 2400 1600 Product Families External Product Specification PCSD Platforms Based On Intel Xeon Processor E5 4600 2600 2400 1600 Product Families BMC Core Firmware External Product Specification Intel order number G64246 003 Revision 2 0
73. Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview Secondary Service Processor SSP which provides the HW capability of offloading time critical processing tasks from the main ARM core Emulex Pilot Ill contains an integrated SIO KVMS subsystem and graphics controller with the following features 6 4 Advanced Configuration and Power Interface ACPI The server board has support for the following ACPI states Table 13 ACPI Power States Supported SO Yes Working The front panel power LED is on not controlled by the BMC The fans spin at the normal speed as determined by sensor inputs Front panel buttons work normally Sleeping Hardware context is maintained equates to processor and chipset clocks being stopped The front panel power LED blinks at a rate of 1 Hz with a 50 duty cycle not controlled by the BMC The watchdog timer is stopped The power reset front panel NMI and ID buttons are unprotected Fan speed control is determined by available SDRs Fans may be set to a fixed state or basic fan management can be applied The BMC detects that the system has exited the ACPI S1 sleep state when the BIOS SMI handler notifies it a E No Net Not supported e S D OEN e only on Workstation platforms See appropriate Platform Specific Information for more information Not supported Soft off The front panel buttons are not locke
74. Low Pin Count LPC Interface ects cen cu iuceee eet baat cues Me ncte cee cake ada tec 30 3 3 8 serial Peripheral Interface SP nccnceeneein tne tein nine hao st et 31 3 3 9 Compatibility Modules DMA Controller Timer Counters and Interrupt Controller 31 3 3 10 Advanced Programmable Interrupt Controller APIC cceeeeeeeeeeeeteeeeeeeeeeeeeee 31 3 3 11 Universal Serial Bus USB CGontroller AAA 31 3 3 12 Gigabit Ethernet Controller coscccctietscccedeceeendd stad pede es shee AE et ENNER 31 CRCP AEN n i E OEE AE AE e Ee ee ee ek Ae 32 33AF Ee ee eege e ed ee 32 3 3 15 Enhanced Power Management ANEN ENEE 32 3 3 16 Ee GE ER 3 3 17 System Management Bus SMBus 201 33 3 3 18 Intel Active Management Technology Intel AMT 33 3 3 19 Integrated NVSRAM Controller AAA 33 3 3 20 Intel Virtualization Technology for Direct I O Intel VT 33 33 20 RE Reie Ee EE 33 3 3 22 KVM Serial Over LAN SOL Functon 34 Intel Server Board S1400FP TPS Table of Contents 3 3 23 On board Serial Attached SCSI SAS Serial ATA SATA Support and Options 34 3 4 Integrated Baseboard Management Controller BMC Overview 36 3 4 1 super V O Controlle rreri e e a a E RE R eee 37 3 4 2 Graphics Controller and Video Support ss ssssssseeesnrrnreesseerenrrrnnrsserrrnnrnnnnnnnneeeet 38 3 4 3 Baseboard Management Controller uk 39 4 gt System d EE 41 4 1 BIOS Password Protection ugktgdeaeguengcNeSdde REENEN EEER SEENEN 41 4 2 Trusted Plat
75. MAX 2 PLACES COMPONENT HEIGHT RESTRICTION O 05 1 27MM MAX APLACES COMPONENT HEIGHT RESTRICTION 0 08 12 OMMIMAX 2 PLACES COMPONENT HEIGHT RESTRIC GZ a 1481 THROUGH ALL ROUTE KEEPOUT A PLA DETAIL A SCALE 2 000 ROUNTING AT TOP LAYER 0 025 OUTSIDE AROUND THE HOLE ROUNTION ALL LAYER NO COMPONENT ALLOWED 0 015 OUTSIDE AROUND ROUTING ALL LAYER THE SLOT HOLE EDGE 0 015 OUTSIDE AROUND THE HOLE IB CIRCULAR HOLE ROUTING ALL LAYER 0 025 OUTSIDE iO ROUNTING AT THE TOP LAYER AROUND THE SLOT HOLE EDGE DETAIL 6 DETAIL D sea to E De Figure 7 Intel Server Boards S1400FP Primary Side Keepout Zone Revision 2 0 Intel order number G64246 003 11 Overview Intel Server Board S1 400FP TPS COMPONENT HEIGHT RESTRICTIO O 25 MAK4 PLACES j COMPONENT HEIGHT RESTRICTION awa COMPONENT HEIGHT RESTRICTION QETMAX OMPONENT HEIGHT RESTRICTION O20 MAX 12 PLACES MPONENT HEIGHT RESTRICTION OTMAX Figure 9 Intel Server Boards S1400FP Primary Side Air Duct Keepout Zone 12 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS BASEBOARD MOUNTING KEEFOUT AREA NO COMPONENT ZONES PLACES k goso Ro GROUND PADS S PLACES RUSSER PAD LOCATON NO COMPONENT ZONE PLACES K ES N PLACE WEAR PAD oN SECONDARY SDE NO COMPONENT ALLOWD HERE Revision 2 0 SEE DETAL amp Intel order number G64246 003 Ze
76. MC boot blocks to avoid possibility of a corrupted boot block resulting in a scenario that prevents a user from updating the BMC o BMC System Management Health Monitoring Fault resilient booting FRB FRB2 is supported by the watchdog timer functionality Enable Disable of System Reset Due to CPU Errors Chassis intrusion detection Fan speed control Fan redundancy monitoring and support Hot swap fan support Power Supply Fan Sensors System Airflow Monitoring Exit Air Temperature Monitoring Acoustic management Support for multiple fan profiles Ethernet Controller Thermal Monitoring Global Aggregate Temperature Margin Sensor Platform environment control interface PECI thermal management support Memory Thermal Management DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings Power supply redundancy monitoring and support Power unit management Support for power unit sensor The BMC handles power good dropout conditions Intel Intelligent Power Node Manager support Signal testing support The BMC provides test commands for setting and getting platform signal states The BMC generates diagnostic beep codes for fault conditions System GUID storage and retrieval Front panel management The BMC controls the system status LED and chassis ID LED It supports secure lockout of certain front panel functionality and monitors button pr
77. OST code sequence for the two most recent boots This is a best effort data collection by the BMC as the BMC real time response cannot guarantee that all POST codes are captured Support for multiple debug files The platform debug feature provides the ability to save data to 2 separate files that are encrypted with different passwords O 6 12 15 1 File 1 is strictly for viewing by Intel engineering and may contain BMC log messages that is syslog and other debug data that Intel FW developers deem useful in addition to the data specified in this document File 2 can be viewed by Intel partners who have signed an NDA with Intel and its contents are restricted to specific data items specified in this with the exception of the BMC syslog messages and power supply black box data Output Data Format The diagnostic feature shall output a password protected compressed HTML file containing specific BMC and system information This file is not intended for end customer usage this file is for customer support and engineering only 6 12 15 2 Output Data Availability The diagnostic data shall be available on demand from the embedded web server KCS or IPMI over LAN commands 6 12 15 3 Output Data Categories The following tables list the data to be provided in the diagnostic output Table 18 Diagnostic Data Category Data Internal BMC Data BMC uptime load Process list Free Memory Detailed Memory List
78. Output Power Currents The following table defines the minimum power and current ratings The power supply meets both static and dynamic voltage regulation requirements for all conditions 104 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Server Board Power Distribution Table 53 Over Voltage Protection Limits Parameter Min Max Peak Unit 5V 0 3 10 0 A 12V1 0 7 16 0 18 0 A 12V2 1 5 16 0 18 0 A 3 3V 0 5 18 0 A 12V 0 0 0 5 A 5Vstby 0 0 2 5 3 0 A Notes Max combined power for all output shall not exceed 365W Peak combined power for all outputs shall not exceed 385W Max combined power of 12V1 and 12V2 shall not exceed 318W Max combined power on 3 3V and 5V shall not exceed 80W Peak power and current loading shall be supported for a minimum of 12 seconds OU 00 Non 12 1 2 Cross Loading The power supply maintains voltage regulation limit when operated over the following cross loading conditions Power Power Power os fes as fe feo ES a Table 54 Loading Conditions CSS EE fo CSS Load4 13 6 3 6 e o5 SECHER EES 12 1 3 Standby Output The 5VSB output is present when an AC input greater than the power supply turn on voltage is applied 365 12 1 4 Voltage Regulation The power supply output voltages stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include t
79. PS 3 3 3 Serial ATA SATA Controller The C600 chipset has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 6 0 Gb s 600 MB s on up to two ports Port 0 and 1 Only while all ports support rates up to 3 0 Gb s 800 MB s and up to 1 5 Gb s 150 MB s The SATA controller contains two modes of operation a legacy mode using I O space and an AHCI mode using memory space Software that uses legacy mode will not have AHCI capabilities The C600 chipset supports the Serial ATA Specification Revision 3 0 The C600 also supports several optional sections of the Serial ATA II Extensions to Serial ATA 1 0 Specification Revision 1 0 AHCI support is required for some elements 3 3 4 AHCI The C600 chipset provides hardware support for Advanced Host Controller Interface AHCI a standardized programming interface for SATA host controllers Platforms supporting AHCI may take advantage of performance features such as no master slave designation for SATA devices each device is treated as a master and hardware assisted native command queuing AHCI also provides usability enhancements such as Hot Plug AHCI requires appropriate software support for example an AHCI driver and for some features hardware support in the SATA device or additional platform hardware 3 3 5 Rapid Storage Technology The C600 chipset provides support for Intel Rapid Storage Technol
80. Presence 13h Platform Module Board Discrete 01 OK As and Trig M IO Mod specific 15h osh Inserted Present De Offset Presence Baseboard nc Temperature 5 Platform Temperature Threshold Degraded As and 14h te u l c nc Analo R T A x Platform specific Oth Oth u1 enc c Non De S Specific fatal Baseboard nc Temperature 6 Platform Temperature Threshold Degraded As and 15h ae u l c nc Analo R T A x Platform specific Oth Oth ust fesne c Non De Specific fatal nc IO Module Temperature Threshold Degraded Temperature 16h ee P u l c nc Ge and analog R T A D I O Mod2 Temp SESSE joii Oth c Non e fatal PCI Riser 3 nc Temperature Platform Temperature Threshold Degraded As and 17h Gr u l c nc Analo R T A x PCI Riser 5 specific Oth Oth u1 enc c Non De S Temp fatal PCI Riser 4 nc Temperature Platform Temperature Threshold Degraded As and 18h a u l c ne Analo R T A X PCI Riser 4 specific Oth Oth ust fesne c Non De S Temp fatal Baseboard E GE Platf Vol Threshold Degraded As and Processor3 Veep 19h el eg ee u l c nc ng anc Analog R T A l BB 1 05Vecp SE jig 0 c Non e P3 fatal Revision 2 0 Intel order number G64246 003 117 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Re
81. S provides a setup option to allow one of these baseboard ports to be dedicated to the BMC for manageability purposes When this is enabled that port is hidden from the OS 6 12 3 2 3 Concurrent Server Management Use of Multiple Ethernet Controllers The BMC FW supports concurrent OOB LAN management sessions for the following combination Two on board NIC ports One on board NIC and an optional dedicated RMM4 add in management NIC Two on board NICs and an optional dedicated RMM4 add in management NIC All NIC ports must be on different subnets for the above concurrent usage models 64 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview MAC addresses are assigned for management NICs from a pool of up to 3 MAC addresses allocated specifically for manageability The Intel Server Board S1400FP4 has seven MAC addresses programmed at the factory MAC addresses are assigned as follows NIC 1 MAC address for OS usage NIC 2 MAC address NIC 1 MAC address 1 for OS usage NIC 3 MAC address NIC 1 MAC address 2 for OS usage NIC 4 MAC address NIC 1 MAC address 3 for OS usage BMC LAN channel 1 MAC address NIC1 MAC address 4 BMC LAN channel 2 MAC address NIC1 MAC address 5 BMC LAN channel 3 RMM MAC address NIC1 MAC address 6 The Intel Server Board S1400FP2 has five MAC addresses programmed at the factory MAC addresses are assigned as follows
82. Supply 1 nc Temperature is Temperature Threshold Degraded T 5Ch Chassis S ul e nc 4 Asand Analog RT A x PS1 specific Oth Oth c Non De Temperature fatal Power Supply 2 nc Temperature is Threshold Degraded p 5Dh Gees Temperature u c nc I Asang Analog R T A X PS2 specific Oth c Non De Temperature fatal 00 Drive OK Presence Hard Disk Drive 01 Drive Fault Degraded 60h f j Sensor f 16 24 Status S Chassis Drive Slot Specific 07 As and 8 Trig A x HDD 16 24 ogh specific om 6Fh Rebuild Remap in pe Si Status progress Degraded Revision 2 0 Intel order number G64246 003 121 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets iil Ch M Il 04 Off T A assis icrocontroller n transition to z rig specific 16h Discrete 0AN Tihe Degraded Offset x 6Bh Processor 1 Sensor 01 Thermal tri Fatal i Status 70h All SE Specific d SS SE Se u S P1 Status Orh 6Fh 07 Presence OK Processor 2 Piocessor Sensor 01 Thermal trip Fatal Status 71h All Specific Ge E oe t m T e se P2 Status 07h ett 07 Presence OK Processor 3 Sensor 01 Thermal tri Fatal i Status 72h e e Specific i i and j G
83. adable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Baseboard ae SE Platf Vol Threshold Degraded As and Processor4 Veep 1Ah SE TESO u 1 c nc S sand analog R T A l specific 02h Oth c Non De BB 1 05Vccp P4 fatal Baseboard nc Temperature 1 Temperature Threshold Degraded R 20h satio p u l c nc Asand Analog RT A x Platform specific Oth Oth c Non De Specific fatal Front Panel nc Temperature Temperature Threshold Degraded E g Ee 21h All SE j an u l c nc e a and analog R T A D ront Pane c Non Temp fatal nc SSB Temperature Threshold Degraded As and Temperature 22h All u 1 c nc De Analog R T A X SSB Temp Oth Oth S CH ata Baseboard nc Temperature 2 Temperature Threshold Degraded P 23h manera P u l c nc E Asand Analog R T A x Platform specific Oth Oth c Non De Specific fatal Baseboard nc T ture 3 Temperature Threshold D ded emperature 24h Platform p u l c nc SE SE Analog R T A X Platform specific Oth Oth c Non De Specific fatal Baseboard nc Temperature 4 Temperature Threshold Degraded R 25h SEN S u l c nc g Asand Analog R T A x Platform specific Oth Oth c Non De Specific fatal nc IO Module Temperature 26h Platform Temperature Threshold iwi eb Degraded As and aen RT A x specific Oth Oth de N De g b I O Mod Temp p e Non fatal
84. al monitor video mode is supported ont 16 MB DDR3 Memory AN Two Gigabit Ethernet Ports through the Intel Ethernet Controller 1350 for S1400FP2 Four Gigabit Ethernet Ports through the Intel Ethernet Controller 1350 for S1400FP4 Intel TPM module AXXTPMES5 Accessory Option L Server Management Onboard ServerEngines LLC Pilot III Controller Support for Intel Remote Management Module 4 solutions optional Support for Intel Remote Management Module 4 Lite solutions optional Intel Light Guided Diagnostics on field replaceable units Support for Intel System Management Software Support for Intel Intelligent Power Node Manager Need PMBus compliant power supply ATX 12 x9 6 compliant form factor Compatible Intel Intel Server Chassis P4000S for S1400FP Server Chassis Note 1 Internal 2x5 pin serial port B header does not function if power supply cannot support 12V output Revision 2 0 Intel order number G64246 003 3 Overview Intel Server Board S1400FP TPS 2 2 Server Board Layout Figure 1 Intel Server Board S1400FP Layout S1400FP4 as shown 4 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS 2 2 1 Server Board Connector and Component Layout The following figure shows the layout of the server board Each connector and major component is identified by a number or letter and a description is given in the figure below A BC DE FG UH
85. altitude selection can lead to potential thermal risk And higher altitude selection provides better cooling but with undesired acoustic and fan power consumption If the altitude is known higher altitude is recommended in order to provide sufficient cooling The default setting is 301m 900m 6 11 4 Set Fan Profile The Performance and Acoustic fan profiles in BIOS must be selected in BIOS gt Advanced gt System Acoustic and Performance Configuration gt Set Fan Profile The Acoustic mode offers the best acoustic experience and appropriate cooling capability covering mainstream and majority of the add in cards with 100LFM thermal requirements For any add in card requiring more than 100LFM performance mode must be selected to provide sufficient cooling capability 6 11 5 Fan PWM Offset This feature is reserved for manual adjustment to the minimum fan speed curves The valid range is from 0 to 100 which stands for 0 to 100 PWM adding to the minimum fan speed This feature is valid when Quiet Fan Idle Mode is at Enabled state The default setting is 0 6 11 6 Quiet Fan Idle Mode This feature can be Enabled or Disabled If enabled the fan will either stopped or shift to a lower speed when the aggregate sensor temperatures are satisfied indicating the system is at ideal thermal light loading conditions When the aggregate sensor temperatures not satisfied the fan will shift back to normal control curves If disabled the fan
86. ard S1400FP TPS 9 2 Management Engine ME Firmware Force Update Jumper Block When the ME Firmware Force Update jumper is moved from its default position the ME is forced to operate in a reduced minimal operating capacity This jumper should only be used if the ME firmware has gotten corrupted and requires re installation The following procedure should be followed Note System Update and Recovery files are included in the System Update Packages SUP posted in the Intel website 1 Turn off the system and remove power cords 2 Move the ME FRC UPD Jumper from the default pins 1 and 2 operating position to the Force Update position pins 2 and 3 3 Re attach system power cords 4 Power on the system Note System Fans will boost and the BIOS Error Manager should report an 83A0 error code ME in recovery mode 5 Boot to the EFI shell and update the ME firmware using the MEComplete cap file where ME revision number using the following command iflash32 u ni MEComplete cap When update has successfully completed power off system Remove AC power cords Move ME FRC UPD jumper back to the default position Note If the ME FRC UPD jumper is moved with AC power applied the ME will not operate properly The system will need have the AC power cords removed wait for at least 10 seconds and then reinstalled to ensure proper operation 9 Install AC power cords 10 Power on system OR 9 3 Passwo
87. at first correctable error event will be the only one logged for the system However since each channel is a Sparing Domain the correctable error counting continues for other channels which are still in a redundant state There can be as many SFO Events as there are memory channels with DIMMs installed 3 2 2 4 3 Mirrored Channel Mode Channel Mirroring Mode gives the best memory RAS capability by maintaining two copies of the data in main memory If there is an Uncorrectable ECC Error the channel with the error is disabled and the system continues with the good channel but in a non redundant configuration For Mirroring mode to be to be available as a RAS option the DIMM population must be identical between each pair of memory channels that participate Not all channel pairs need to have memory installed but for each pair the configuration must match If the configuration is not matched up properly the memory operating mode falls back to Independent Channel Mode Mirroring Mode is enabled disabled in the Memory RAS and Performance Configuration screen in the lt F2 gt BIOS Setup Utility When Mirroring Mode is operational each channel in a pair is mirrored by the other channel The impact on Effective Memory size is to reduce by half the total amount of installed memory available for use When Mirroring Mode is operational the system treats Correctable Errors the same way as it would in Independent channel mode There is a
88. board Management Controller BMC Overview sssesssseseeeeeeesn 37 Integrated BMC Hardware cc32 iets geseet Meder ert 37 Setup Utility TPM Configuration Sereen ENNEN rnn 44 Fan Speed Control ee E 61 Intel RMM4 Lite Activation Key Installation cccccccccccccsssssssesssesesesesesestssssstetetenenens 78 Intel RMM4 Dedicated Management NIC Installetlon 79 On Board LED PlIaGement ciccenuitenieaatenta tue ido Ghe eaeuatasiaaae 98 Power Distribution Block Det ss eege eect eh teat EE 104 Differential Noise test setup AAA 107 Output Voltage Timing a ee E EE 108 Turn On Off Timing Power Supply Signals eceeeeeeeeeeee eee eeeeenneeeeeeeeeeeeeeeeee 109 Processor Heatsink Jett eneen Seege Zeg Ee EE 146 Revision 2 0 Intel order number G64246 003 ix List of Tables Intel Server Board S1400FP TPS List of Tables Table 1 Intel Server Board S1400FP Feature Set 2 Table 2 Intel Server Board S1400FP Component Layout 5 Table 3 UDIMM Support Guidelines en 19 Table 4 RDIMM Support Guidelines eege eeh rees 20 Table 5 Intel Server Board S1400FP DIMM Nomenclature 20 Table 6 External RJ45 NIC Port LED Dettntton 28 Table 7 Intel RAID C600 Upgrade Key Options ccccccsecesccssesescsessesesceeseesesessseeecseeeeseeeseens 34 Table 8 Video MAES iiini ieia aE EEN Eeer 38 ikable 9 Video FOE ebe eeh ee 39 Table 10 TPM Setup Utility Security Configuration Screen Fields cccccc
89. btained by calling 1 800 548 4725 or go to http Awww intel com design literature Revision 2 0 Intel order number G64246 003 jii Table of Contents Intel Server Board S1400FP TPS Table of Contents E Introductlony ee ees 1 1 1 Chapter Outline E 1 1 2 Server Board Use Disclaimer 1 Ze EENS 2 2 1 Intel Server Boards S1400FP Feature Set 2 2 2 Server Board Layout E 4 2 2 1 Server Board Connector and Component Layout 5 2 2 2 Server Board Mechanical Drawings AEN 7 2 2 3 Server Board Rear W O Layout EE 14 Sa F nctional Architecturen EE 15 3 1 Processor SUPPOM nenn Saker n ee es 16 3 1 1 Processor Socket ASSOMDIY inicciiaretestscckivnstteegeesseakseattdseteedssauenedamereaeapekteaeteeaanteees 16 3 2 Processor Function Cerview geed cols Aenea hs ed ee eden ce 17 3 2 1 Intel QuickPath Interconnect 18 3 2 2 Integrated Memory Controller IMC and Memory Subsystem sssssseeeeeeeseeenne 18 3 2 3 Processor Integrated I O Module IO 26 3 3 Intel C602 A Chipset Functional Overview ccccccccesesesssesesesesesereseetesstseeeeeees 28 3 3 1 Digital Media Interface DMI c ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeaaaaeaaaaeeeeeeeeeeeeenaaaaes 29 3 3 2 PCI Express Interface giiia ee Ae seed rede ees EEE ede EEN 29 3 3 3 Serial ATA SATA CGontroller cece eececneee teeter eeeececeeeeeeeeeeeeeeeeteennaaeeeeeeees 30 3 34 AIG EE 30 3 3 5 Rapid Re ER ele VE 30 3 3 6 PCI INCH OCG oct ee Ee Maa ean aaa 30 3 3 7
90. captured from the last boot PCI configuration data for on board devices and add in cards The first 256 bytes of PCI configuration data is captured for each device for each boot System memory map The system memory map is provided by BIOS on the current boot This includes the EFl memory map and the Legacy E820 memory map depending on the current boot Power supplies debug capability o Capture of power supply black box data and power supply asset information Power supply vendors are adding the capability to store debug data within the power supply itself The platform debug feature provides a means to capture this data for each installed power supply The data can be analyzed by Intel for failure analysis and possibly provided to the power supply vendor as well The BMC Revision 2 0 Intel order number G64246 003 75 Platform Management Functional Overview Intel Server Board S1400FP TPS gets this data from the power supplies from the PMBus manufacturer specific commands Storage of system identification in power supply The BMC copies board and system serial numbers and part numbers into the power supply whenever a new power supply is installed in the system or when the system is first powered on This information is included as part of the power supply black box data for each installed power supply Accessibility from IPMI interfaces The platform debug file can be accessed from an external IPMI interface KCS or LAN P
91. chassis is configured with a chassis intrusion switch The header has the following pin out Table 32 Chassis Intrusion Header Pin out Header State Description Pins 1 and 2 closed FM_INTRUDER_HDR_N is pulled HIGH Chassis cover is closed Pins 1 and 2 open FM_INTRUDER_HDR_N is pulled LOW Chassis cover is removed 8 3 8 SATA SGPIO Header Table 33 SATA SGPIO Header Pin out Pin Signal Name 1 SCLK 2 SLOAD 3 GND 4 SDATAOUTO 5 SDATAOUT1 8 3 9 SAS SGPIO Header Table 34 SATA SGPIO Header Pin out Pin Signal Name 1 SCLK 2 SLOAD 3 GND 4 DATAOUT 5 DATAIN 8 3 10 IPMB Connector Table 35 IPMB Connector Pin out Pin Signal Name 1 SMB_IPMB_5VSTBY_ DATA 2 GND 3 SMB_IPMB_5VSTBY_CLK 4 P5V_STBY 8 4 Front Panel Connector The server board provides a 30 pin front panel connector J1C3 for use with Intel and third party chassis The 30 pin connector consists of a 24 pin SSI compatible front panel connector and a 4 pin connector to support optional NIC 3 4 LEDs The 24 pin SSI front panel connector provides various front panel features including Power Sleep Button System ID Button NMI Button NIC Activity LEDs Hard Drive Activity LEDs System Status LED System ID LED Revision 2 0 Intel order number G64246 003 87 On board Connector Header Overview Intel Server Board S1400FP TPS
92. d The fans are stopped The power up process goes through the normal boot process The power reset front panel NMI and ID buttons are unlocked 6 5 Power Control Sources The server board supports several power control sources which can initiate a power up or power down activity Table 14 Power Control Initiators Sage External Signal Name or Capabilities Internal Subsystem Power button Front panel power button Turns power on or off BMC watchdog timer Internal BMC timer Turns power off or power cycle Command Routed through command processor Turns power on or off or power cycle Power state retention Implemented by means of BMC Turns power on when AC power returns internal logic Revision 2 0 Intel order number G64246 003 55 Platform Management Functional Overview Intel Server Board S1400FP TPS External Signal Name or ef Source Capabilities Internal Subsystem Chipset Sleep S4 S5 signal same as Turns power on or off POWER_ON CPU Thermal CPU Thermtrip Turns power off WOL Wake On TAN 6 6 BMC Watchdog The BMC FW is increasingly called upon to perform system functions that are time critical failure to provide these functions in a timely manner can result in system or component damage Intel S1400 S1600 S2400 S2600 S4600 Server Platforms introduce a BMC watchdog feature to provide a safe guard against this scenario by providing an automatic recovery mechanism It also can provide automatic recovery
93. d 3 4 Integrated Baseboard Management Controller BMC Overview The server board utilizes the I O controller Graphics Controller and Baseboard Management features of the Server Engines Pilot Il Server Management Controller The following is an overview of the features as implemented on the server board from each embedded controller kd Intel 1350 Gigabit PCI E GEN2 x2 NC SI PORT EMU 50Mbps Ethernet Controller VIDEO RGB X PCI EGENI ai _ K SERIAL PORT 1 wb Intel C600 SMBUS PORTS Integrated eege 2x5 HOR Chipset mem BMC SERIAL PORT 0 USB 1 1 NC SI PORT RGMII DOR 3 S A RMM4 Lite TPM CONN 16 MB IBMC SPI FLASH LPC 33MHz RMM4 DNM CONN AF005563 36 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture Figure 17 Integrated Baseboard Management Controller BMC Overview USB External Bus SPI Interface interface to amp NAND r Host Interface ARM code Fan Tach Veciored 16 ExtBus amp JTAG Interrupt PWM PECI NAND amp Controller 8 Interface SPI Flash ADC 16 Eihemet 10 ARM926EJ S 16KD amp 16K Cache 400MHz RTC Timers 6 3 Watchdog Virtual UART 2 GPIO KCS BT System SE amp amp Wakeup SGPIO Mailboxes Control LPC to SPI Flash Bridge Watchdog Timer System BIOS SPI Memory Interface Accelarator Subsystem DDR II 16 bit Memory Controller 800MH2 Super VO Subsystem Figu
94. d the BIOS displays the total system memory on the diagnostic screen at the end of POST This total is the same as the amount described by the first bullet above Note Some server operating systems do not display the total physical memory installed What is displayed is the amount of physical memory minus the approximate memory space used by system BIOS components These BIOS components include but are not limited to 1 ACPI may vary depending on the number of PCI devices detected in the system ACPI NVS table Processor microcode Memory Mapped I O MMIO Manageability Engine ME BIOS flash OF O ew Fei 3 2 2 4 RAS Features The server board supports the following memory RAS modes e Independent Channel Mode Rank Sparing Mode Mirrored Channel Mode Lockstep Channel Mode Single Device Data Correction SDDC Error Correction Code ECC Memory Demand Scrubbing for ECC Memory Patrol Scrubbing for ECC Memory 22 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture Regardless of RAS mode the requirements for populating within a channel given in the section 3 2 2 2 must be met at all times Note that support of RAS modes that require matching DIMM population between channels Mirrored and Lockstep require that ECC DIMMs be populated Independent Channel Mode is the only mode that supports non ECC DIMMs in addition to ECC DIMMs For RAS modes that require matching popu
95. d S1400FP TPS Error Code Error Message Response 85DB DIMM_O2 disabled Major 85DC DIMM_O8 disabled Major 85DD DIMM_P1 disabled Major 85DE DIMM_P2 disabled Major 85DF DIMM_P3 disabled Major 85E0 DIMM_K3 encountered a Serial Presence Detection SPD failure Major 85E1 DIMM_L1 encountered a Serial Presence Detection SPD failure Major 85E2 DIMM_L2 encountered a Serial Presence Detection SPD failure Major 85E3 DIMM_L3 encountered a Serial Presence Detection SPD failure Major 85E4 DIMM_M1 encountered a Serial Presence Detection SPD failure Major 85E5 DIMM_M2 encountered a Serial Presence Detection SPD failure Major 85E6 DIMM _M3 encountered a Serial Presence Detection SPD failure Major 85E7 DIMM_N1 encountered a Serial Presence Detection SPD failure Major 85E8 DIMM_N2 encountered a Serial Presence Detection SPD failure Major 85E9 DIMM_N3 encountered a Serial Presence Detection SPD failure Major 85EA DIMM_O1 encountered a Serial Presence Detection SPD failure Major 85EB DIMM_O2 encountered a Serial Presence Detection SPD failure Major 85EC DIMM_O3 encountered a Serial Presence Detection SPD failure Major 85ED DIMM_P1 encountered a Serial Presence Detection SPD failure Major 85EE DIMM_P2 encountered a Serial Presence Detection SPD failure Major 85EF DIMM_P3 encountered a Serial Presence Detection SPD failure Major 8604
96. des BOh Detect DIMM population Bih Set DDR3 frequency Bhn Ju b by ju RE Gather remaining SPD data B3h Program registers on the memory controller level B4h Evaluate RAS modes and save rank information B5h Program registers on the channel level B6h Perform the JEDEC defined initialization sequence B7h Train DDR3 ranks B8h Initialize CLTT OLTT B9h Hardware memory test and init BAh Execute software memory init BBh Program memory map and interleaving BCh Program RAS configuration BFh MRC is done Memory Initialization at the beginning of POST includes multiple functions including discovery channel training validation that the DIMM population is acceptable and functional initialization of the IMC and other hardware settings and initialization of applicable RAS configurations When a major memory initialization error occurs and prevents the system from booting with data integrity a beep code is generated the MRC will display a fatal error code on the diagnostic LEDs and a system halt command is executed Fatal MRC error halts do NOT change the state of the System Status LED and they do NOT get logged as SEL events The following table lists all MRC fatal errors that are displayed to the Diagnostic LEDs 138 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix C POST Code Diagnostic LED Decoder Table 65 POST Progress LED C
97. dge of the server next to the stacked USB connectors During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the given POST code to the POST code diagnostic LEDs The purpose of these LEDs is to assist in troubleshooting a system hang condition during the POST process The diagnostic LEDs can be used to identify the last POST process to be executed See Appendix C and D for a complete description of how these LEDs are read and for a list of all supported POST codes 10 5 5 Volt Stand By Present LED This LED is illuminated when a power cord AC or DC is connected to the server and the power supply is supplying 5 Volt Stand by power to the server board This LED is intended as a service caution indicator to anyone accessing the inside of the server system 10 6 Fan Fault LEDs The server board includes a Fan Fault LED next to each of the system fans and CPU fan The LED has two states On and Off The BMC lights a fan fault LED if the associated fan tach sensor has a lower critical threshold event status asserted Fan tach sensors are manual re arm sensors Once the lower critical threshold is crossed the LED remains lit until the sensor is rearmed These sensors are rearmed at system DC power on and system reset 10 7 Memory Fault LEDs The server board includes a Memory Fault LED for eac
98. dvance rather than just 24 hours in advance 3 3 14 GPIO Various general purpose inputs and outputs are provided for custom system design The number of inputs and outputs varies depending on the C600 chipset configuration 3 3 15 Enhanced Power Management The C600 chipset s power management functions include enhanced clock control and various low power Suspend states for example Suspend to RAM and Suspend to Disk A hardware based thermal management circuit permits software independent entrance to low power states The C600 chipset contains full support for the Advanced Configuration and Power Interface ACPI 3 3 16 Manageability The chipset integrates several functions designed to manage the system and lower the total cost of ownership TCO of the system These system management functions are designed to report errors diagnose the system and recover from system lockups without the aid of an external microcontroller TCO Timer The chipset s integrated programmable TCO timer is used to detect system locks The first expiration of the timer generates an SMI that the system can use to recover from a software lock The second expiration of the timer causes a system reset to recover from a hardware lock Processor Present Indicator The chipset looks for the processor to fetch the first instruction after reset If the processor does not fetch the first instruction the chipset will reboot the system ECC Error Repo
99. e 300M altitude CLTT 2 Acoustic 900M altitude CLTT 3 Performance 900M altitude CLTT 4 Acoustic 1500M altitude CLTT 5 Performance 1500M altitude CLTT 6 Acoustic 3000M altitude CLTT 7 Performance 3000M altitude Each group of profiles allows for varying fan control policies based on the altitude For a given altitude the Tcontrol SDRs associated with an acoustics optimized profile generate less noise than the equivalent performance optimized profile by driving lower fan speeds and the BIOS reduces thermal management requirements by configuring more aggressive memory throttling The BMC only supports enabling a fan profile through the command if that profile is supported on all fan domains defined for the given system It is important to configure platform Sensor Data Records SDRs so that all desired fan profiles are supported on each fan domain If no single profile is supported across all domains the BMC by default uses profile 0 and does not allow it to be changed 6 11 8 Thermal Sensor Input to Fan Speed Control The BMC uses various IPMI sensors as input to the fan speed control Some of the sensors are IPMI models of actual physical sensors whereas some are virtual sensors whose values are derived from physical sensors using calculations and or tabular information The following IPMI thermal sensors are used as input to the fan speed control Front Panel Temperature Sensor Baseboard Temperature Sensor CPU Marg
100. e GE P3 Status SC 6Fh 07 Presence OK Processor 4 Sensor 01 Thermal tri Fatal i Status 73h Foma Pe Specific i Be Sie e SP e P4 Status S Och 6Fh 07 Presence OK Processor 1 Thermal Margin Temperature Threshold 74h All Analog R T A P1 Therm Oth 01h Margin Processor 2 Thermal Margin Temperature Threshold an 75h All p Analog R T a l P2 Therm O1h O1h Margin Processor 3 Thermal Margin Temperature Threshold 76h Panom j Analog R T Aa l P3 Therm specific Oth Oth Margin Processor 4 Thermal Margin Temperature Threshold a 77h panor S e Analog R T A l P4 Therm specific Oth Oth Margin 122 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Processor 1 nc Thermal Degraded Temperature Threshold i Control 78h All p fu enc on As and Analog Trig A 8 Oth Oth De Offset P1 Therm Ctrl fatal Processor 2 nc Thermal Degraded Temperature Threshold i Control 79h All H u e nc bt As and Analog Trig A 8 Oth Oih De Offset P2 Therm Ctrl fatal Processor 3 nc Thermal Degraded Temperature Threshold i Control
101. eady to Boot DXE Legacy Boot DXE Exit Boot Services RT Set Virtual Address Map Begin RT Set Virtual Address Map End DXE Legacy Option ROM init DXE Reset system DXE USB Hot plug DXE PCI BUS Hot plug DXE NVRAM cleanup DXE Configuration Reset INT19 E0h Eth E2h E3h BIOS Recovery S3 Resume PEIM S3 started S3 Resume PEIM S3 boot script S3 Resume PEIM S3 Video Repost S3 Resume BEIM S3 OS wake FOh Revision 2 0 PEIM which detected forced Recovery condition PEIM which detected User Recovery condition Recovery PEIM Recovery started Recovery PEIM Capsule found Recovery PEIM Capsule loaded Intel order number G64246 003 137 Appendix C POST Code Diagnostic LED Decoder Intel Server Board S1400FP TPS POST Memory Initialization MRC Diagnostic Codes There are two types of POST Diagnostic Codes displayed by the MRC during memory initialization Progress Codes and Fatal Error Codes The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step Table 64 MRC Progress Codes Diagnostic LED Decoder 1 LED On O LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h Ih 8h 4h 2h 1h LED 7 6 5 4 3 2 1 0 Description MRC Progress Co
102. eatures such as KVM and media redirection These features are grayed out in the GUI unless the system has been updated to support these advanced features Additional features supported by the web GUI includes Presents all the Basic features to the users Power on off reset the server and view current power state Displays BIOS BMC ME and SDR version information Display overall system health Configuration of various IPMI over LAN parameters for both IPv4 and IPv6 Configuration of alerting SNMP and SMTP Display system asset information for the product board and chassis Display of BMC owned sensors name status current reading enabled thresholds including color code status of sensors Provides ability to filter sensors based on sensor type Voltage Temperature Fan and Power supply related Automatic refresh of sensor data with a configurable refresh rate On line help Display clear SEL display is in easily understandable human readable format Supports major industry standard browsers Microsoft Internet Explorer and Mozilla Firefox Automatically logs out after user configurable inactivity period The GUI session automatically times out after a user configurable inactivity period By default this inactivity period is 30 minutes Revision 2 0 Intel order number G64246 003 73 Platform Management Functional Overview Intel Server Board S1400FP TPS Embedded Platform Debug feature Allow the user to i
103. ecoverable Voltage sensor out of range 3 Non critical critical and non recoverable Fan failure 4 General chassis intrusion Chassis intrusion security violation 5 Failure and predictive failure Power supply failure 6 Uncorrectable ECC BIOS 7 POST error BIOS POST code error 8 FRB2 Watchdog Timer expiration for FRB2 9 Policy Correction Time Node Manager 10 Power down power cycle and reset Watchdog timer 11 OEM system boot event System restart reboot 12 Drive Failure Predicted Failure Hot Swap Controller Additionally the BMC supports the following PEF actions Power off Power cycle Reset OEM action Alerts The Diagnostic interrupt action is not supported 6 12 10 LAN Alerting The BMC supports sending embedded LAN alerts called SNMP PET Platform Event traps and SMTP email alerts The BMC supports a minimum of four LAN alert destinations 6 12 10 1 SNMP Platform Event Traps PETs This feature enables a target system to send SNMP traps to a designated IP address by means of LAN These alerts are formatted per the Intelligent Platform Management Interface Specification Second Generation v2 0 A Modular Information Block MIB file associated with the traps is provided with the BMC firmware to facilitate interpretation of the traps by external software The format of the MIB file is covered under RFC 2578 Revision 2 0 Intel order number G64246 003 71 Platform Management Functional Overview Inte
104. ed Memory Controller IMC and Memory Subsystem Integrated into the processor is a memory controller Each processor provides three DDR3 channels that support the following Unbuffered DDR3 and registered DDR3 DIMMs Independent channel mode or lockstep mode Data burst length of eight cycles for all memory organization modes Memory DDR3 data transfer rates of 800 1066 1333 and 1600 MT s 64 bit wide channels plus 8 bits of ECC support for each channel DDR3 standard I O Voltage of 1 5 V and DDR3 Low Voltage of 1 35 V 1 Gb 2 Gb and 4 Gb DDR3 DRAM technologies supported for these devices o UDIMM DDR3 SR x8 and x16 data widths DR x8 data width o RDIMM DDR3 SR and DR x4 and x8 data widths Up to 4 ranks supported per memory channel 1 2 ranks per DIMM Open with adaptive idle page close timer or closed page policy Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC with or without data scrambler or a predefined test pattern lIsochronous access support for Quality of Service QoS Minimum memory configuration independent channel support with 1 DIMM populated Integrated dual SMBus master controllers Command launch modes of 1n 2n RAS Support o Rank Level Sparing and Device Tagging o Demand and Patrol Scrubbing 18 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture o DRAM Single
105. ed in the System Update Packages SUP posted to Intel s website 94 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Jumper Blocks Table 48 Server Board Jumpers Jumper Name Pins System Results J3J2 BMC 1 2 BMC Firmware Force Update Mode Disabled Default Force Update 5 3 BMC Firmware Force Update Mode Enabled J3J4 BIOS 1 2 Pins 1 2 should be jumpered for normal system operation Default Recovery 2 3 The main system BIOS does not boot with pins 2 3 jumpered The system only boots from EFI bootable recovery media with a recovery BIOS image present J3J1 BIOS 1 2 These pins should have a jumper in place for normal system operation Default Default 2 3 If pins 2 3 are jumpered with AC power plugged in the CMOS settings clear in 5 seconds Pins 2 3 should not be jumpered for normal system operation J3J3 ME 1 2 ME Firmware Force Update Mode Disabled Default Force Update 2 3 ME Firmware Force Update Mode Enabled J3J5 1 2 These pins should have a jumper in place for normal system operation Password 2 3 To clear administrator and user passwords power on the system with pins 2 3 connected Clear The administrator and user passwords clear in 5 10 seconds after power on Pins 2 3 should not be connected for normal system operation 9 1 BIOS Recovery Jumper When the BIOS Recovery jumper block is moved from its default pin positi
106. edge of the server board viewable from the back of the system Both LEDs are tied together and will show the same state The System Status LED states are driven by the on board platform management sub system Revision 2 0 Intel order number G64246 003 89 On board Connector Header Overview Intel Server Board S1400FP TPS 8 5 1 0 Connectors 8 5 1 VGA Connector The following table details the pin out definition of the VGA connector Table 39 VGA Connector Pin out JOB E GND 8 5 2 SATA and SAS Connectors The server board provides up to 6 SATA connectors SATA 0 SATA 1 SATA 2 SATA 3 SATA 4 SATA 5 and 8 SAS connectors SATA SAS 0 SATA SAS 1 SATA SAS 2 SATA SAS 3 SATA SAS 4 SATA SAS 5 SATA SAS 6 and SATA SAS 7 The pin configuration for each connector is identical and defined in the following table Table 40 SATA Connector Pin out Pin 1 2 3 4 5 6 7 4 1 SAS Connector Pin out Table H 3 NIJA AVN 90 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS On board Connector Header Overview 8 5 3 Serial Port Connectors The server board provides one external DB9 Serial A port and one internal 9 pin Serial B header The following tables define the pin outs Table 42 External DB9 Serial A Port Pin out Ground _ _ O Ground 6 SPA DSR____ DSR data set ready 8 SPA CTS CTS clearto send 9 SPARI RI Ring Indicate Table 43
107. eeeeeeeeeeeeeeeeeeeees 45 Table 11 Intel Intelligent Power Node Manager 48 Table 12 Basic and Advanced Features 53 Table 13 ACPI Power Giaies 55 Table 14 Power Control Initiators ccccccccseeesecccceeeeceeeeeeeeeceeeeeseeeausceeeeesessaseeaeeceeesessesaanagees 55 Table 15 Fan Profile Sirion n r ea ere a iar E E TEE P AE EA 60 Table 16 Messaging Interfaces ANNE 62 Table 17 Factory Configured PEF Table Entries ccccccccccceccceceeceececeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeess 71 Table 18 Diagnosti NEE 76 Table 19 Additional Diagnostics on Error s ssssssssssseernnessseerrrrrrntesssrrtrrrrnnnesrnrssertrnrrnnnnsserrenne 77 Table 20 RMM4 Option BT 78 Table 21 Board Connector Mats 83 Table 22 Main Power Connector Pin out 84 Table 23 CPU Power Connector Pin out 84 Table 24 Power Supply Auxiliary Signal Connector Pim out eneen 85 Table 25 Intel KEISER ed Eelere Eeer comes 85 Table 26 Intel RMM4 Lite Connector Pin OUt 0 cccceccccessesessesessecessecesseceeseceevaceevacsaservanereas 85 Table 27 TPM Connector Pin out 86 Table 28 Intel RAID C600 Upgrade Key Connector Bin out 86 Lable 29 LCP Header PiN OUT e e a a 86 Table 30 HSBP_I C Header Pin obite gees dees e 86 Table 31 HDD LED Header Pin out onae ideata EAn S 86 Table 32 Chassis Intrusion Header Pin OUut cccccccccccccccceceeeeeeeeeeeeeeeeeceeeeeeeeeeseeseeseseseeeseseeeess 87 Table 33 SATA SGPIO Header Pm out
108. eeeeeeeeeeeeeeeseseeeeseeeeeeeeeeeenneees 102 11 1 Processor Thermal Design Power TDP Support c c ceeeeeeeeeeeeeeeeteeeeeeees 102 11 2 EEN 103 12 Server Board Power Distribution cccccccssseeeseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeesaeeeeeeeeeeeeeeeenneees 104 12 1 DG CUPS SPS CMC AMON cesia e a er eiae or Ena E AEU hereon Des 104 12 1 1 Output e Ti EEN 104 12 e2 NGPOSS OA ee EE 105 121 3 Standby COUT eene eet ed eg 105 12 1 4 Ee II e EE 105 12 1 5 Dynamic Loading WEE 106 Revision 2 0 Intel order number G64246 003 vii Table of Contents Intel Server Board S1400FP TPS 12 1 6 Capacitive Te EE 106 EE Ge ein el WEE 106 12 1 8 Residual Volatge Immunity in Standy mode cece eeeeeeeeeeeeeeeeeeeeeenteeeeeeees 106 12 1 9 Common Mode Noise AAA 107 Eat ek ID DIB e 107 See ON Urs Une Be Mt EE 107 Appendix A Integration and Usage TIps ccccceesssssssscceeeeeeeesneeesneeeeeeeeeseeeesnneesseeeeeeeees 110 Appendix B Integrated BMC Sensor Tables cccccccseeseeeeeeeeeeeseeeeeeeeeeeeeeeeeeseeeseeseseeesaeeneaes 111 Appendix C POST Code Diagnostic LED Decoder ccccseeeceeseseeeeeeeeeeeeeeeseeneeeeesenneeeeeeeneeaes 135 Appendix D POST Egeter 140 Appendix E Supported Intel Server Chassis ccsseeccceseseeeeeeseeeeeeeeseeeeeseeseeeeeeeseeseeeeeeeeneenes 146 et Ge EE 147 Reference Documents agebett EE 150 viii Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Lis
109. een Ability to select a mouse configuration based on the OS type supports user definable keyboard macros KVM redirection feature supports the following resolutions and refresh rates 640x480 at 60Hz 72Hz 75Hz 85Hz 100Hz 800x600 at 60Hz 72Hz 75Hz 85Hz 1024x768 at 60Hx 72Hz 75Hz 85Hz 1280x960 at 60Hz 1280x1024 at 60Hz 1600x1200 at 60Hz 1920x1080 1080p 1920x1200 WUXGA 1650x1080 WSXGA 7 1 1 Remote Console The Remote Console is the redirected screen keyboard and mouse of the remote host system To use the Remote Console window of your managed host system the browser must include a Java Runtime Environment plug in If the browser has no Java support such as with a small handheld device the user can maintain the remote host system using the administration forms displayed by the browser The Remote Console window is a Java Applet that establishes TCP connections to the BMC The protocol that is run over these connections is a unique KVM protocol and not HTTP or HTTPS This protocol uses ports 7578 for KVM 5120 for CDROM media redirection and 5123 for Floppy USB media redirection When encryption is enabled the protocol uses ports 7582 for KVM 5124 for CDROM media redirection and 5127 for Floppy USB media redirection The local network environment must permit these connections to be made that is the firewall and in case of a private internal network the NAT Network Address Translation settings
110. el ESRT2 SATA RO 1 10 5 RKSAS8 Orange Intel RSTE 8 ports SAS RO 1 10 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 8 ports SAS RO 1 10 or Intel ESRT2 SATA RO 1 10 RKSAS8R5 Purple Intel RSTE 8 ports SAS RO 1 10 Intel RSTE SATA RO 1 10 5 or Intel ESRT2 8 ports SAS RO 1 10 5 or Intel ESRT2 SATA RO 1 10 5 Additional information for the on board RAID features and functionality can be found in the InteP RAID Software Users Guide Intel Document Number D29305 018 The system includes support for two embedded software RAID options e Intel Embedded Server RAID Technology 2 ESRT2 based on LSI MegaRAID SW RAID technology Intel Rapid Storage Technology RSTe Using the lt F2 gt BIOS Setup Utility accessed during system POST options are available to enable disable SW RAID and select which embedded software RAID option to use 3 3 23 1 Intel Embedded Server RAID Technology 2 ESRT2 Features of the embedded software RAID option Intel Embedded Server RAID Technology 2 ESRT2 include the following Based on LSI MegaRAID Software Stack Software RAID with system providing memory and CPU utilization Supported RAID Levels 0 1 5 10 o 4and 8 Port SATA RAID 5 support provided with appropriate Intel RAID C600 Upgrade Key o 4and8 Port SAS RAID 5 support provided with appropriate Intel RAID C600 Upgrade Key Maximum drive support Eight with or without SAS expander option installed
111. el Server Board S1400FP TPS Functional Architecture 3 3 8 Serial Peripheral Interface SPI The C600 chipset implements an SPI Interface as an alternative interface for the BIOS flash device An SPI flash device can be used as a replacement for the FWH and is required to support Gigabit Ethernet and Intel Active Management Technology The C600 chipset supports up to two SPI flash devices with speeds up to 50 MHz utilizing two chip select pins 3 3 9 Compatibility Modules DMA Controller Timer Counters and Interrupt Controller The DMA controller incorporates the logic of two 82C37 DMA controllers with seven independently programmable channels Channels 0 3 are hardwired to 8 bit count by byte transfers and channels 5 7 are hardwired to 16 bit count by word transfers Any two of the seven DMA channels can be programmed to support fast Type F transfers Channel 4 is reserved as a generic bus master request The C600 chipset supports LPC DMA which is similar to ISA DMA through the C600 chipset s DMA controller LPC DMA is handled through the use of the LDRQ lines from peripherals and special encoding on LAD 3 0 from the host Single Demand Verify and Increment modes are supported on the LPC interface The timer counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer These three counters are combined to provide the system timer function and speaker tone The
112. eliability Prediction Procedure Method 1 Parts Count Prediction Case Ill Generic Value Quality Stress Temperature Confidence Level 90 Quality Level II Temperature Customer Specified default 40 C Duty Cycle Continuous 100 Operating Environment Ground Benign Fixed Controlled Table 52 MTBF Estimate Assembly Name Temperature Degree C MTBF hours Intel Server Board Revision 2 0 Intel order number G64246 003 103 Server Board Power Distribution Intel Server Board S1400FP TPS 12 Server Board Power Distribution This section provides power supply design guidelines for a system using the Intel Server Board S1400FP The following diagram shows the power distribution implemented on this server board Di Ereement Pass VR Block Sonn 1216 2011 Note All currents are PEAK TOC or just TOC 1 SNB EN VCCP estimates are value A Peak valua A TOC 2 IVB EN estimates are value A Peak value A TOC EU SE Figure 24 Power Distribution Block Diagram The power supply data provided in this section is for reference purposes only It reflects Intel s own DC power out requirements for a 365W power supply as used in an Intel designed 4U server platform The intent of this section is to provide customers with a guide to assist in defining and or selecting a power supply for custom server platform designs that utilize the server boards detailed in this document 12 1 DC Output Specification 12 1 1
113. em Management Bus SMBus Specification Version 2 0 Quick Command Send Byte Receive Byte Write Byte Word Read Byte Word Process Call Block Read Write and Host Notify The C600 chipset s SMBus also implements hardware based Packet Error Checking for data robustness and the Address Resolution Protocol ARP to dynamically provide address to all SMBus devices 3 3 18 Intel Active Management Technology Intel AMT Intel Active Management Technology Intel AMT is the next generation of client manageability using the wired network Intel AMT is a set of advanced manageability features developed as a direct result of IT customer feedback gained through Intel market research With the new implementation of System Defense in C600 chipset the advanced manageability feature set of Intel AMT is further enhanced 3 3 19 Integrated NVSRAM Controller The C600 chipset has an integrated NVSRAM controller that supports up to 32KB external device The host processor can read and write data to the NVSRAM component 3 3 20 Intel Virtualization Technology for Direct UO Intel VT d The C600 chipset provides hardware support for implementation of Intel Virtualization Technology with Directed UO Intel VT d Intel VT d consists of technology components that support the virtualization of platforms based on Intel Architecture Processors Intel VT d Technology enables multiple operating systems and applications to run in independ
114. ensors 4 Power supply predictive failure occurred while redundant power supply configuration was present 5 Unable to use all of the installed memory more than 1 DIMM installed 6 Correctable Errors over a threshold and migrating to a spare DIMM memory sparing This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition Corresponding DIMM LED lit 7 In mirrored configuration when memory mirroring takes place and system loses memory redundancy 8 Battery failure 9 BMC executing in uBoot Indicated by Chassis ID blinking at Blinking at 3Hz System in degraded state no manageability BMC uBoot is running but has not transferred control to BMC Linus Server will be in this state 6 8 seconds after BMC reset while it pulls the Linus image into flash 10 BMC booting Linux Indicated by Chassis ID solid ON System in degraded state no manageability Control has been passed from BMC uBoot to BMC Linux itself It will be in this state for 10 20 seconds 11 BMC Watchdog has reset the BMC 12 Power Unit sensor offset for configuration error is asserted 13 HDD HSC is off line or degraded Amber 1 Hz blink Non critical Non fatal alarm system is likely to fail 1 Critical threshold crossed Voltage temperature including HSBP temp input power to power supply output current for main power rail from power supply and PROCHOT Therm Ctrl sensors 2 VRD Hot asserted Revision 2
115. ent partitions A partition behaves like a virtual machine VM and provides isolation and protection across partitions Each partition is allocated its own subset of host physical memory 3 3 21 JTAG Boundary Scan The C600 chipset adds the industry standard JTAG interface and enables Boundary Scan in place of the XOR chains used in previous generations of chipsets Boundary Scan can be used to ensure device connectivity during the board manufacturing process The JTAG interface Revision 2 0 Intel order number G64246 003 33 Functional Architecture Intel Server Board S1400FP TPS allows system manufacturers to improve efficiency by using industry available tools to test the C600 chipset on an assembled board Since JTAG is a serial interface it eliminates the need to create probe points for every pin in an XOR chain This eases pin breakout and trace routing and simplifies the interface between the system and a bed of nails tester 3 3 22 KVM Serial Over LAN SOL Function These functions support redirection of keyboard mouse and text screen to a terminal window on a remote console The keyboard mouse and text redirection enables the control of the client machine through the network without the need to be physically near that machine Text mouse and keyboard redirection allows the remote machine to control and configure the client by entering BIOS setup The KVM SOL function emulates a standard PCI serial port and redirects the data f
116. eo controller supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD Table 8 Video Modes 2D Mode 2D Video Mode Support 8bpp 16bpp 24bpp 32 bpp 640x480 A A X X 800x600 X X X D 1024x768 X X X X 1152x864 X X X X 1280x1024 X X X X 1600x1200 X X Video resolutions at 1600x1200 and higher are only supported through the external video connector located on the rear I O section of the server board Utilizing the optional front panel video connector may result in lower video resolutions The BIOS supports dual video mode when an add in video card is installed In the single mode dual monitor video disabled the on board video controller is disabled when an add in video card is detected In the dual mode on board video enabled dual monitor video enabled the on board video controller is enabled and is the primary video device The add in video card is allocated resources and is considered the secondary video device The BIOS Setup utility provides options to configure the feature as follows 38 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture Table 9 Video mode On board Video Enabled Disabled Dual Monitor Video Enabled Shaded if on board video is set to Disabled Disabled 3 4 3 Baseboard Management Controller The server board utilizes the following features
117. er designed by Rivest for RSA Data Security now RSA Security It is a variable key size stream cipher with byte oriented operations The algorithm is based ona random permutation RMCP Remote Management Control Protocol 148 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Glossary Read Only Memory Real Time Clock ESCH System Control Interrupt A system interrupt used by hardware to notify the operating system of ACPI events RTC SCI O Server Input Output SMBus A two wire interface based on the I C protocol The SMBus is a low speed bus that provides positive addressing for devices and bus arbitration SM O Server Management Interrupt SMI is the highest priority non maskable interrupt SMM Server Management Mode sa Seavert eer StaightPass Trough SSCS mr UserDatagramProoeol SSCS SMI SMM Server Management Software SOL SPT UDP Revision 2 0 Intel order number G64246 003 149 Reference Documents Intel Server Board S1400FP TPS Reference Documents See the following documents for additional information 150 Advanced Configuration and Power Interface Specification Revision 3 0 http www acpi info Intelligent Platform Management Bus Communications Protocol Specification Version 1 0 1998 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Intelligent Platform Management Interface Specification Version 2 0 2004
118. er to the Intel Xeon processor E5 2400 product family documents listed in the Reference Document list Processor Feature Details Up to 8 execution cores Intel Xeon processor E5 2400 product family Up to 10 execution cores Intel Xeon processor E5 2400 v2 product family Each core supports two threads Intel Hyper Threading Technology 46 bit physical addressing and 48 bit virtual addressing 1 GB large page support for server applications A 32 KB instruction and 32 KB data first level cache L1 for each core A 256 KB shared instruction data mid level L2 cache for each core Up to 20 MB last level cache LLC up to 2 5 MB per core instruction data last level cache LLC shared among all cores Supported Technologies Intel Virtualization Technology Intel VT e Intel Virtualization Technology for Directed HO Intel VT d Intel Trusted Execution Technology Intel TXT Intel 64 Architecture Intel Streaming SIMD Extensions 4 1 Intel SSE4 1 Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 Intel Advanced Vector Extensions Intel AVX Intel Hyper Threading Technology Execute Disable Bit Intel Turbo Boost Technology Intel Intelligent Power Technology Enhanced Intel SpeedStep Technology Revision 2 0 Intel order number G64246 003 17 Functional Architecture Intel Server Board S1400FP TPS 3 2 1 Intel QuickPath Interconnect
119. eshold u1 c nc g As and Analog R T A 8 02h Oth c Non De BB 1 8V AUX fatal 132 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Baseboard nc 1 1V Stand by Voltage Threshold Degraded As and DDh All u l c nc Analo R T A BB 1 1V 02h Oth u l ene c Non De q STBY fatal Geen Vol Threshold Degraded As and CMOS Battery DEh All oltage ii u 1 c nc sand Analog R T A 02h Oth c Non De BB 3 3V Vbat fatal Baseboard 1 35V P1 Low nc Voltage Memory Voltage Threshold Degraded As and AB VDDQ E4h All 02h Oth u 1 c nc a De Analog R T A BB 1 35 P1LV fatal AB Baseboard 1 35V P1 Low nc Voltage Memory Voltage Threshold Degraded As and CD VDDQ E5h All 02h Oth u 1 c nc Be Noa De Analog R T A BB 1 35 P1LV fatal CD Baseboard 1 35V P2 Low nc Voltage Memory Voltage Threshold Degraded As and AB VDDQ E6h All 02h Oth u l c nc B Nak De Analog R T A BB 1 35 P2LV fatal AB Baseboard 1 35V P2 Low nc Voltage Memory Voltage Threshold Degraded As and CD VDDQ E7h All 02h Oth u 1 c nc Nom De Analog R T A BB 1 35 P2LV
120. essed encrypted and password protected The file is not meant to be viewable by the end user but rather to provide additional debugging capability to an Intel support engineer A list of data that may be captured using this feature includes but is not limited to Platform sensor readings This includes all readable sensors that can be accessed by the BMC FW and have associated SDRs populated in the SDR repository This does not include any event only sensors All BIOS sensors and some BMC and ME sensors are event only meaning that they are not readable using an IPMI Get Sensor Reading command but rather are used just for event logging purposes SEL The current SEL contents are saved in both hexadecimal and text format CPU memory register data useful for diagnosing the cause of the following system errors CATERR ERR 2 SMI timeout PERR and SERR The debug data is saved and timestamped for the last 3 occurrences of the error conditions o PCI error registers o MSR registers o MCH registers BMC configuration data o BMC FW debug log that is SysLog Captures FW debug messages o Non volatile storage of captured data Some of the captured data will be stored persistently in the BMC s non volatile flash memory and preserved across AC power cycles Due to size limitations of the BMC s flash memory it is not feasible to store all of the data persistently SMBIOS table data The entire SMBIOS table is
121. esses The chassis ID LED is turned on using a front panel button or a command Local Control Display Panel support Power state retention Power fault analysis Intel Light Guided Diagnostics Revision 2 0 Intel order number G64246 003 5 Platform Management Functional Overview Intel Server Board S1400FP TPS 6 1 3 Address Resolution Protocol ARP The BMC sends and responds to ARPs supported on embedded NICs Dynamic Host Configuration Protocol DHCP The BMC performs DHCP supported on embedded NICs E mail alerting Embedded web server o Support for embedded web server UI in Basic Manageability feature set o Human readable SEL o Additional system configurability o Additional system monitoring capability o Enhanced on line help Integrated KVM Integrated Remote Media Redirection Local Directory Access Protocol LDAP support Sensor and SEL logging additions enhancements for example additional thermal monitoring capability SEL Severity Tracking and the Extended SEL Embedded platform debug feature which allows capture of detailed data for later analysis Provisioning and inventory enhancements o Inventory data system information export partial SMBIOS table DCMI 1 1 compliance product specific Management support for PMBus rev1 2 compliant power supplies Energy Star Server Support Smart Ride Through SmaRT Closed Loop System Throttling CLST Power Supply Cold Redundancy Power Supply FW Update Power Supply C
122. et P2 Mem Thrm 03h Trip Processor 3 DIMM smor Digital 8 Thermal Trip C2h All A Discrete ae Fatal SE ee g M x OCh overtemperature De Offset P3 Mem Thrm 03h Trip Processor 4 DIMM Riginer Digital RA e Thermal Trip C3h All S Discrete cans We Fatal ene anig M x DCH overtemperature De Offset P4 Mem Thrm 03h Trip Global Aggregate Temperature Platform Temperature Threshold Margin 1 C8h Specific Oth oth Analog R T A Agg Therm Mrgn 1 Global Aggregate Temperature Platform Temperature Threshold Margin 2 C9h Specific EI oth Analog R T A Agg Therm Mron 2 Revision 2 0 Intel order number G64246 003 129 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor name in SDR Global Aggregate Temperature Margin 3 Agg Therm Mrgn 3 Sensor CAh Platform Applicability Platform Specific Sensor Type Temperature Oth Event Reading Type Threshold O1h Event Offset Triggers Contrib To System Status Assert De assert Readable Value Offsets Analog Event Data R T Rearm Standby Global Aggregate Temperature Margin 4 Agg Therm Mrgn 4 CBh Platform Specific Temperature Oth Threshold O1h Analog R T Global Aggregate Temperature Margin 5 Agg Therm Mrgn 5 CCh Platform Specific Temperature Oth Threshold O1h Analog R T Global Aggregate Temperature
123. etection SPD failure Major 8568 DIMM_C3 encountered a Serial Presence Detection SPD failure Major 8569 DIMM_D1 encountered a Serial Presence Detection SPD failure Major 856A DIMM_D2 encountered a Serial Presence Detection SPD failure Major 856B DIMM_D3 encountered a Serial Presence Detection SPD failure Major 856C DIMM_E1 encountered a Serial Presence Detection SPD failure Major 856D DIMM_E2 encountered a Serial Presence Detection SPD failure Major 856E DIMM_ES encountered a Serial Presence Detection SPD failure Major 856F DIMM_F1 encountered a Serial Presence Detection SPD failure Major 8570 DIMM_F2 encountered a Serial Presence Detection SPD failure Major 8571 DIMM_F3 encountered a Serial Presence Detection SPD failure Major 8572 DIMM_G1 encountered a Serial Presence Detection SPD failure Major 8573 DIMM_G2 encountered a Serial Presence Detection SPD failure Major 8574 DIMM_G3 encountered a Serial Presence Detection SPD failure Major 8575 DIMM_H 1 encountered a Serial Presence Detection SPD failure Major 8576 DIMM_H2 encountered a Serial Presence Detection SPD failure Major 8577 DIMM_H3 encountered a Serial Presence Detection SPD failure Major 8578 DIMM_I1 encountered a Serial Presence Detection SPD failure Major 8579 DIMM_1I2 encountered a Serial Presence Detection SPD failure Major 857A DIMM_I3 encountered a Serial Presence Detection SPD failure Major 857B DIMM_J1 encountered a Serial Presence Detection SPD fai
124. fatal CD Revision 2 0 Intel order number G64246 003 133 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Baseboard GE 3 3V Riser 1 al Power Good EAh Platform Voltage Threshold tu 1 fonc Degraded Asand Analog IRT A 8 Specific 02h Oth E c Non De g 5 BB 3 3 RSR1 f PGD atal Baseboard Age 3 3V Riser 2 Platf Volt Threshold Degraded A d Power Good atform oltage resho san 8 Sch Specific 02h Oth u 1 e ne c Non De Analog R T 2 BB 3 3 RSR2 PGD fatal 00 Drive OK Presence oe a Drive FOh Drive Slot Sensor 01 Drive Fault Degraded s atus g Chassis opt Specific 07 l l As and 8 Trig A x HDD 1 15 specific D Rebuild Remap in De Offset Status FEN progress Degraded Notes 1 Redundancy sensors will be only present on systems with appropriate hardware to support redundancy for instance fan or power supply 2 This is only applicable when the system does not support redundant fans When fan redundancy is supported then the contribution to system state is driven by the fan redundancy sensor 134 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix C POST
125. fied in the Intelligent Platform Management Interface Specification Version 2 0 This functionality provides commands used for accessing and managing the FRU inventory information These commands can be delivered through all interfaces The BMC provides FRU device command access to its own FRU device and to the FRU devices throughout the server The FRU device ID mapping is defined in the Platform Specific Information The BMC controls the mapping of the FRU device ID to the physical device Revision 2 0 Intel order number G64246 003 57 Platform Management Functional Overview Intel Server Board S1400FP TPS 6 10 System Event Log SEL The BMC implements the system event log as specified in the ntelligent Platform Management Interface Specification Version 2 0 The SEL is accessible regardless of the system power state through the BMC s in band and out of band interfaces The BMC allocates 65 502 bytes approximately 64 KB of non volatile storage space to store system events The SEL timestamps may not be in order Up to 3 639 SEL records can be stored at a time Any command that results in an overflow of the SEL beyond the allocated space is rejected with an Out of Space IPMI completion code C4h Events logged to the SEL can be viewed using Intel s SELVIEW utility Embedded Web Server and Active System Console 6 11 System Fan Management The BMC controls and monitors the system fans Each fan is associated with a fan speed
126. fore it is used to compare to future measurements to verify the integrity of the boot process After the system BIOS completes the measurement of its boot process it hands over control to the operating system loader and in turn to the operating system If the operating system is TPM enabled it compares the BIOS TPM measurements to those of previous boots to make sure the system was not tampered with before continuing the operating system boot process Once the operating system is in operation it optionally uses TPM to provide additional system and data security for example Microsoft Vista supports Bitlocker drive encryption 4 2 1 TPM security BIOS The BIOS TPM support conforms to the TPM PC Client Specific Implementation Specification for Conventional BIOS Version 1 2 and to the TPM Interface Specification Version 1 2 The BIOS adheres to the Microsoft Vista BitLocker requirement The role of the BIOS for TPM security includes the following Measures and stores the boot process in the TPM microcontroller to allow a TPM enabled operating system to verify system boot integrity 42 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS System Security Produces EFI and legacy interfaces to a TPM enabled operating system for using TPM Produces ACPI TPM device and methods to allow a TPM enabled operating system to send TPM administrative command requests to the BIOS Verifies operator physical pre
127. form Module TPM Support ssessseesssnrrnnsssesererrnnressrrrnnrrnnrrnneeeee 42 4 2 1 d SE ie BIOS aranes nanon neat Dente at dee teres ea 42 4 2 2 Physical EE 43 4 2 3 TPM Security Setup Options ENNEN 43 4 3 Intel Trusted Execution Technology 45 5 Technology SU e es a r a het a raa etc tea ee en edie eee eee 47 5 1 Intel Trusted Execution Technology 47 5 2 Intel Virtualization Technology Intel VT x VT A VT C n se 47 5 3 Intel Intelligent Power Node Manager 48 5 3 1 Hardware Requirements EE 49 6 Platform Management Functional OvervieW ssssssnnnssennnunnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nanna 50 6 1 Baseboard Management Controller BMC Firmware Feature Suppott 50 6 1 1 IM 2 0 F Atures yo eech ege ee EZE ENEE EEE GAEE EEE RE GEETE 50 6 1 2 Non IPMI GE 51 6 1 3 New Manageability Features cic c tress dia ctee Rehwntansanegdont beni deavaterastneedeacbertelenest 52 6 2 Basic and Advanced EE 53 6 3 Integrated BMC Hardware Emulex Pilot II 54 6 3 1 Emulex Pilot Ill Baseboard Management Controller Functionality 8 54 6 4 Advanced Configuration and Power Interface AC 55 6 5 Power Control SOUrCeS E 55 6 6 BMC Ee ee EE 56 6 7 Fault Resilient Booting FRB E 56 6 8 Sensor Monitorning EE 57 6 9 Field Replaceable Unit FRU Inventory Device sssssseeessseseenerrnressserrrerrnneessee 57 6 10 System Event Be EE 58 6 11 System Fan Management i euugECZKEEEAdENEEEREN EELER NENNEN
128. g Power Supply Signals Revision 2 0 Intel order number G64246 003 109 Appendix A Integration and Usage Tips Intel Server Board S1400FP TPS Appendix A Integration and Usage Tips When adding or removing components or peripherals from the server board you must remove AC power cord With AC power plugged into the server board 5 V standby is still present even though the server board is powered off This server board supports Intel Xeon Processor E5 2400 product family or Intel Xeon Processor E5 2400 v2 product family with a Thermal Design Power TDP of up to and including 95 Watts Previous generation Intel Xeon processors are not supported The onboard SATA connectors 0 and 1 are designed to support the ODD or SSD do NOT connect SATA connector 0 and 1 to the backplane The onboard SATA connectors 2 5 are designed to support the backplane On the back edge of the server board are EIGHT diagnostic LEDs that display a sequence of amber POST codes during the boot process If the server board hangs during POST the LEDs display the last POST event run before the hang Only Registered DDR3 DIMMs RDIMMs and Unbuffered DDR3 DIMMs UDIMMs are supported on this server board Mixing of RDIMMs and UDIMMs is not supported The Intel RMM4 RMM4 Lite connectors are not compatible with the previous Intel Remote Management Modules Clear CMOS with the AC power cord plugged in Removing AC power before performing t
129. g models These provide out of band local area network LAN communication between the BMC and the network See the ntelligent Platform Management Interface Specification Second Generation v2 0 for details about the IPMl over LAN protocol Run time determination of LAN channel capabilities can be determined by both standard IPMI defined mechanisms 6 12 3 1 RMCP ASF Messaging The BMC supports RMCP ping discovery in which the BMC responds with a pong message to an RMCP ASF ping request This is implemented according to the ntelligent Platform Management Interface Specification Second Generation v2 0 Revision 2 0 Intel order number G64246 003 63 Platform Management Functional Overview Intel Server Board S1400FP TPS 6 12 3 2 BMC LAN Channels The BMC supports three RMII RGMII ports that can be used for communicating with Ethernet devices Two ports are used for communication with the on board NICs and one is used for communication with an Ethernet PHY located on an optional RMM4 add in module 6 12 3 2 1 Baseboard NICs The on board Ethernet controller provides support for a Network Controller Sideband Interface NC SI manageability interface This provides a sideband high speed connection for manageability traffic to the BMC while still allowing for a simultaneous host access to the OS if desired The NC SI is a DMTF industry standard protocol for the side band management LAN interface This protocol provides a fast multi drop in
130. g occurred 3 2 2 6 2_Uncorrectable Memory ECC Error Handling All multi bit detectable but not correctable memory errors are classified as Uncorrectable Memory ECC Errors This is generally a fatal error However before returning control to the OS drivers through the Machine Check Exception MCE or Non Maskable Interrupt NMI the Uncorrectable Memory ECC Error is logged to the SEL the appropriate memory slot fault LED is lit and the System Status LED state is changed to solid Amber 3 2 2 7 Demand Scrubbing for ECC Memory Demand scrubbing is the ability to write corrected data back to the memory once a correctable error is detected on a read transaction This allows for correction of data in memory at detect and decrease the chances of a second error on the same address accumulating to cause a multi bit error MBE condition Demand Scrubbing is enabled disabled default is enabled in the Memory Configuration screen in Setup 3 2 2 8 Patrol Scrubbing for ECC Memory Patrol scrubs are intended to ensure that data with a correctable error does not remain in DRAM long enough to stand a significant chance of further corruption to an uncorrectable stage 3 2 3 Processor Integrated I O Module OO The processor s integrated I O module provides features traditionally supported through chipset components The integrated I O module provides the following features PCI Express Interfaces The integrated I O module incorpora
131. ggled by turning the chassis ID button on or off There is no precedence or lock out mechanism for the control sources When a new request arrives previous requests are terminated For example if the chassis ID button is pressed then the chassis ID LED changes to solid on If the button is pressed again then the chassis ID LED turns off Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Platform Management Functional Overview Note that the chassis ID will turn on because of the original chassis ID button press and will reflect in the Virtual Front Panel after VFP sync with BMC Virtual Front Panel will not reflect the chassis LED software blinking from the software command as there is no mechanism to get the chassis ID Led status Only Infinite chassis ID ON OFF from the software command will reflect in EWS during automatic manual EWS sync up with BMC Virtual Front Panel help should available for virtual panel module At present NMI button in VFP is disabled It can be used in future 6 12 15 Embedded Platform Debug The Embedded Platform Debug feature supports capturing low level diagnostic data applicable MSRs PCI config space registers and so on This feature allows a user to export this data into a file that is retrievable from the embedded web GUI as well as through host and remote IPMI methods for the purpose of sending to an Intel engineer for an enhanced debugging capability The files are compr
132. gs support Event receiver device The BMC receives and processes events from other platform subsystems Field Replaceable Unit FRU inventory device functionality The BMC supports access to system FRU devices using PM FRU commands System Event Log SEL device functionality The BMC supports and provides access to a SEL Sensor Data Record SDR repository device functionality The BMC supports storage and access of system SDRs Sensor device and sensor scanning monitoring The BMC provides IPMI management of sensors It polls sensors to monitor and report system health ev PMI interfaces o Host interfaces include system management software SMS with receive message queue support and server management mode SMM o IPMB interface o LAN interface that supports the IPMl over LAN protocol RMCP RMCP Serial over LAN SOL ACPI state synchronization The BMC tracks ACPI state changes that are provided by the BIOS BMC self test The BMC performs initialization and run time self tests and makes results available to external entities 50 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview See also the ntelligent Platform Management Interface Specification Second Generation v2 0 6 1 2 Non IPMI Features The BMC supports the following non IPMI features In circuit BMC firmware update BMC FW reliability enhancements o Redundant B
133. h DIMM slot When the BIOS detects a memory fault condition it sends an IPMI OEM command Set Fault Indication to the BMC to instruct the BMC to turn on the associated Memory Slot Fault LED These LEDs are only active when the system is in the on state The BMC will not activate or change the state of the LEDs unless instructed by the BIOS Revision 2 0 Intel order number G64246 003 101 Environmental Limits Specification Intel Server Board S1400FP TPS 11 Environmental Limits Specification The following table defines the Intel Server Board S1400FP operating and non operating environmental limits Operation of the Intel Server Board S1400FP at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 51 Server Board Design Specifications 0 C to 55 C 32 F to 131 F DiC 10 TO HOF o 18H 5 of all nominal voltages Shock Packaged lt 20 pounds 36 inches 20 to lt 40 pounds 30 inches 40 to lt 80 pounds 24 inches 80 to lt 100 pounds 18 inches 100 to lt 120 pounds 12 inches 120 pounds 9 inches Vibration Unpackaged 5 Hz to 500 Hz 3 13 g RMS random Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when
134. he CMOS Clear operation causes the system to automatically power up and immediately power down after the CMOS Clear procedure is followed and AC power is re applied If this happens remove the AC power cord wait 30 seconds and then re connect the AC power cord Power up the system and proceed to the lt F2 gt BIOS Setup Utility to reset the desired settings Normal BMC functionality is disabled with the Force BMC Update jumper set to the enabled position pins 2 3 You should never run the server with the Force BMC Update jumper set in this position and should only use the jumper in this position when the standard firmware update process fails This jumper must remain in the default disabled position pins 1 2 when the server is running normally This server board no longer supports the Rolling BIOS two BIOS banks It implements the BIOS Recovery mechanism instead When performing a normal BIOS update procedure you must set the BIOS Recovery jumper to its default position pins 1 2 110 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Appendix B Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose See the ntelligent Platform Management Interface Specification Version
135. he component to process high level commands and perform multiple operations this lowers processor utilization by off loading communication tasks from the processor Two large Revision 2 0 Intel order number G64246 003 31 Functional Architecture Intel Server Board S1400FP TPS configurable transmit and receive FIFOs up to 20 KB each help prevent data underruns and overruns while waiting for bus accesses This enables the integrated LAN controller to transmit data with minimum interframe spacing IFS The LAN controller can operate at multiple speeds 10 100 1000 MB s and in either full duplex or half duplex mode In full duplex mode the LAN controller adheres with the IEEE 802 3x Flow Control Specification Half duplex performance is enhanced by a proprietary collision reduction mechanism 3 3 13 RTC The C600 chipset contains a Motorola MC146818B compatible real time clock with 256 bytes of battery backed RAM The real time clock performs two key functions keeping track of the time of day and storing system data even when the system is powered down The RTC operates on a 32 768 KHz crystal and a 3 V battery The RTC also supports two lockable memory ranges By setting bits in the configuration space two 8 byte ranges can be locked to read and write accesses This prevents unauthorized reading of passwords or other system security information The RTC also supports a date alarm that allows for scheduling a wake up event up to 30 days in a
136. he following tables One 4 pin fan header is designated as processor cooling fan o CPU fan J7G1 Three 4 pin fan headers are designated as system fans o System fan 1 J3J7 o System fan 2 J6J1 o System fan 3 J7J1 One 4 pin fan header is designated as a rear system fan o System fan 4 J6B1 Table 47 SSI 4 pin Fan Header Pin out Ground is the power supply ground Power supply 12 V FAN_TACH signal is connected to the BMC to monitor the fan speed Fan PWM FAN_PWM signal to control fan speed Note Intel Corporation server boards support peripheral components and can contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for 92 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS On board Connector Header Overview their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits Revision 2 0 Intel order number G6424
137. he peak peak ripple noise These shall be measured at the output connectors Table 55 Voltage Regulation Limits 5 5 5 5 Revision 2 0 Intel order number G64246 003 105 Server Board Power Distribution Intel Server Board S1400FP TPS 12 1 5 Dynamic Loading The output voltages remain within limits specified for the step loading and capacitive loading specified in the table below The load transient repetition rate is tested between 50Hz and 5kHz at duty cycles ranging from 10 90 The load transient repetition rate is only a test specification The A step load may occur anywhere within the MIN load to the MAX load conditions Table 56 Transient Load Requirements A Step Load Size Load Slew Rate Test capacitive Load See note 2 970 uF 400 pF 12V14 12V2 18 0A 2200 uF 5VSB Notes 1 Step loads on each 12V output may happen simultaneously 2 The 12V should be tested with 2200uF evenly split between the four 12V rails 3 This will be tested over the range of load conditions in section 12 1 2 12 1 6 Capacitive Loading The power supply is stable and meets all requirements with the following capacitive loading ranges Table 57 Capacitive Loading Conditions Output MIN MAX Units 3 3V 250 5000 uF 5V 400 5000 uF 12V 500 8000 uF 12V 1 350 uF 5VSB 20 350 uF 12 1 7 Grounding The output ground of the pins of the power supply provides the output power return path
138. hierarchies handled by the particular DMA Remapping Engine Similarly there are reserved memory regions typically allocated by the BIOS at boot time The BIOS marks these regions as either reserved or unavailable in the system address memory map reported to the OS Some of these regions can be a target of DMA requests from one or more devices in the system while the OS or executive is active The BIOS reports each such memory region using exactly one RMRR Reserved Memory Region Reporting structure in the DMAR Each RMRR has a Device Scope listing the devices in the system that can cause a DMA request to the region Revision 2 0 Intel order number G64246 003 47 Technology Support Intel Server Board S1400FP TPS For more information on the DMAR table and the DRHD entry format refer to the Inte Virtualization Technology for Directed I O Architecture Specification For more general information about VT x VT d and VT c a good reference is Enabling Inte Virtualization Technology Features and Benefits White Paper 5 3 Intel Intelligent Power Node Manager Data centers are faced with power and cooling challenges that are driven by increasing numbers of servers deployed and server density in the face of several data center power and cooling constraints In this type of environment Information Technology IT needs the ability to monitor actual platform power consumption and control power allocation to servers and racks in order to solve spec
139. hometer A5h Chassis Fan Se 8 01 State Non fatal As and E Trig M PS2 Fan Tach specific 04h dree Asserted De Offset 2 Processor 1 nc DIMM Aggregate Degraded Thermal Margin Temperature Threshold S i In Boh All Ge j Ee uf c nc SE Ge and analog R T A P1 DIMM Thrm Mrgn1 Processor 1 nc DIMM Aggregate Degraded Thermal Margin Temperature Threshold an en All or P E u l c nc EES BE and analog R T A P1 DIMM Thrm Mrgn2 Processor 2 nc DIMM Aggregate Degraded Thermal Margin Temperature Threshold i an Boh All ak p Sr u l c nc ae a and analog R T A P2 DIMM Thrm Mrgn1 Revision 2 0 Intel order number G64246 003 127 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Processor 2 nc DIMM Aggregate Degraded Thermal Margin Temperature Threshold x 2 an B3h All p u l c nc c Non Asand Analog R T A Oih Oth fatal De P2 DIMM Thrm Mrgn2 Processor 3 nc DIMM Aggregate Degraded Thermal Margin Temperature Threshold _ 3 IT Bah Flatiorm S ul c nc c Non Asand analog R T A a Specific 01h Oth fatal De P3 DIMM Thrm Mrgn1 Processor 3 nc DIMM Aggregate
140. iary Signal Power connector AO SATA Port 0 1 R System Fan 4 header AP SATA Port 2 3 4 5 S DIMM slots AQ SAS SGPIO 2 header T Main Power connector AR SAS SATA Port 4 5 6 7 U CPU Power connector AS SAS SATA Port 0 1 2 3 V System Fan 3 header AT SAS SGPIO 1 header W System Fan 2 header AU Front Panel header X CPU Fan header AV USB header Intel order number G64246 003 Revision 2 0 Overview Intel Server Board S1400FP TPS 2 2 2 Server Board Mechanical Drawings 0 900 22 86 282 37 1110 2412 61 27 2 487 2783 607 70 68 3 915 99 44 6 100 154 94 Revision 2 0 E FT Geet Se Li o gt 5 aS ss oS 33 23 om BS ER gg Sr Sn S vo dt su os Figure 3 Intel Server Board S1400FP Mounting Hole Locations 1 of 2 Intel order number G64246 003 Overview Intel Server Board S1400FP TPS 0 059 1 50 HOLE FOR FIX SPRING Go 156 gegen BASEBOARD MOUNTING HOLE 11 19 S FXS erences OVAL HOLE FOR FIX SPRING 0 125 2 PLACES B 18 HOLE FOR CPU VR HEATSINK J 0 125 B 18 HOLE FOR ZEPHER GE CPU SOCKETILM MOUNTING HOLE 4 PLACES e hoe ee TRUSTED PLATFORM MODULE STANDOFF HOLE Figure 4 Intel Server Board S1400FP Mounting Hole Locations 2 of 2 8 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS 0 518 13 16 0 000 0 00 1225 31 12 1 389 3528 1 886 47
141. ific data center problems including the following issues Table 11 Intel Intelligent Power Node Manager IT Challenge Requirement Over allocation of power Ability to monitor actual power consumption Control capability that can maintain a power budget to enable dynamic power allocation to each server Under population of rack space Control capability that can maintain a power budget to enable increased rack population High energy costs Control capability that can maintain a power budget to ensure that a set energy cost can be achieved Capacity planning Ability to monitor actual power consumption to enable power usage modeling over time and a given planning period Ability to understand cooling demand from a temperature and airflow perspective Detection and correction of hot spots Control capability that reduces platform power consumption to protect a server in a hot spot Ability to monitor server inlet temperatures to enable greater rack utilization in areas with adequate cooling The requirements listed above are those that are addressed by the C600 chipset Management Engine ME and Intel Intelligent Power Node Manager NM technology The ME NM combination is a power and thermal control capability on the platform which exposes external interfaces that allow IT through external management software to query the ME about platform power capability and consumption thermal characteristics a
142. ify only the System Time and System Date in the Setup Main screen Other setup fields can be modified only if the Administrator password has been entered If any password is set a password is required to enter the BIOS setup The Administrator has control over all fields in the BIOS setup including the ability to clear the User password and the Administrator password It is strongly recommended that at least an Administrator Password be set since not having set a password gives everyone who boots the system the equivalent of Administrative access Unless an Administrator password is installed any User can go into Setup and change BIOS settings at will Revision 2 0 Intel order number G64246 003 41 System Security Intel Server Board S1400FP TPS In addition to restricting access to most Setup fields to viewing only when a User password is entered defining a User password imposes restrictions on booting the system To simply boot in the defined boot order no password is required However the F6 Boot popup prompts for a password and can only be used with the Administrator password Also when a User password is defined it suppresses the USB Reordering that occurs if enabled when a new USB boot device is attached to the system A User is restricted from booting in anything other than the Boot Order defined in the Setup by an Administrator As a security measure if a User or Administrator enters an incorrect password three times in a row
143. in Count LPC interface Serial Peripheral Interface SPI Compatibility Modules DMA Controller Timer Counters Interrupt Controller Advanced Programmable Interrupt Controller APIC Universal Serial Bus USB Controller Gigabit Ethernet Controller RTC GPIO Enhanced Power Management Manageability System Management Bus SMBus 2 0 Intel Active Management Technology Intel AMT Integrated NVSRAM controller Virtualization Technology for Direct I O Intel VT d JTAG Boundary Scan KVM Serial Over LAN SOL Function 3 3 1 Digital Media Interface DMI Digital Media Interface DMI is the chip to chip connection between the processor and C600 chipset This high speed interface integrates advanced priority based servicing allowing for concurrent traffic and true isochronous transfer capabilities Base functionality is completely software transparent permitting current and legacy software to operate normally 3 3 2 PCI Express Interface The C600 chipset provides up to eight PCI Express Root Ports supporting the PC Express Base Specification Revision 2 0 Each Root Port x1 lane supports up to 5 Gb s bandwidth in each direction 10 Gb s concurrent PCI Express Root Ports 1 4 or Ports 5 8 can independently be configured to support four vis two x2s one x2 and two x1s or one x4 port widths Revision 2 0 Intel order number G64246 003 29 Functional Architecture Intel Server Board S1 400FP T
144. in Sensors DIMM Thermal Margin Sensors Exit Air Temperature Sensor PCH Temperature Sensor 60 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview On board Ethernet Controller Temperature Sensors Add In Intel SAS IO Module Temperature Sensors P PSU Thermal Sensor CPU VR Temperature Sensors 7 DIMM VR Temperature Sensors Integrated BMC Temperature Sensor 7 Global Aggregate Thermal Margin Sensors e OD a a a LU a LU a OONDOAURONA For fan speed control in Intel chassis For fan speed control in third party chassis Temperature margin from throttling threshold Absolute temperature PECI value On die sensor On board sensor Virtual sensor Available only when PSU has PMBus The following illustration provides a simple model showing the fan speed control structure that implements the resulting fan speeds High Level FSC Structure RDIMM UDIMM Throttle Settings System Behavior Policy CLTT OLTT Acoustic Performance Altitude Resulting Fan Speed Figure 20 Fan Speed Control Process 6 11 9 Memory Thermal Throttling The server board provides support for system thermal management through open loop throttling OLTT and closed loop throttling CLTT of system memory Normal system operation uses closed loop thermal throttling CLTT and DIMM temperature monitoring as major factors in
145. ing a BMC cold reset command and upon a BMC watchdog initiated reset The following table defines the LED states during the BMC Boot Reset process Table 50 BMC Boot Reset Status LED Indicators Chassis BMC Boot Reset State ID LED Comment Nonrecoverable condition Contact your Intel representative for information on replacing this motherboard Nonrecoverable condition Contact your Intel representative for information on replacing this motherboard Blinking green indicates degraded state no manageability blinking blue indicates u Boot is running but has not transferred control to BMC Linux Server will be in this state 6 8 seconds after BMC reset while it pulls the Linux image into flash Solid green with solid blue after an AC cycle BMC reset indicates that the control has been passed from u Boot to BMC Linux itself It will be in this state for 10 20 seconds Indicates BMC Linux has booted and manageability functionality is up and running Fault Status LEDs operate as per usual BMC Video memory test failed Both Universal Bootloader u Boot images bad BMC in u Boot BMC Booting Linux End of BMC boot reset process Normal system operation 100 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Intel Light Guided Diagnostics 10 4 Post Code Diagnostic LEDs A bank of eight POST code diagnostic LEDs are located on the back e
146. ists all connector types available on the board and the corresponding preference designators printed on the silkscreen Table 21 Board Connector Matrix Quantity Reference Designators Connector Type Power supply 3 J9J1 CPU power J9A1 PS AUX 5 U6E1 EE J3C1 J3C2 J2C1 J4D1 enn D a 124 inte RMA D Wun 30 nie RMM4 Lite fu Storage Upgrade Key J3G1 J3J7 J6J1 J7J1 J6B1 J7G1 Dual USB LAN U7A1 U6A1 RJ45 Combo Connector T A LI ch System fans CPU fan N Stacked RJ45 2xUSB Stacked RJ45 NIC For S1400FP4 ASAI J8A1 J9A2 J1C2 J1C3 J2J1 J2J2 J2E1 J1B1 J3J9 J1J1 J1J2 J1H1 J1H2 J1G1 J1G2 J1D1 J1D3 J1E2 J1E3 J1E4 J1F2 J1F3 J1F5 J3J6 J1H3 J1E1 J1F4 Serial port A Serial port B CH Front panel Internal Dual USB eUSB SSD Internal USB ae 3 C JE 3 E m el Wel AS SEC SATA SGPIO SAS SGPIO a ra ao 2 PS Ee 7 L Wa D U Revision 2 0 Intel order number G64246 003 83 On board Connector Header Overview Intel Server Board S1400FP TPS Connector Quantity Reference Designators Connector Type IPMB J3J2 Force Integrated BMC update E EN 5 J3J5 Password Clear sar Jumpers J3J4 BIOS Recovery J3J1 Reset BIOS Configuration J3J3 ME Firmware Update 1 Chassis Intrusion noo 8 2 Power Connectors The main power supply connection uses an SSl compliant 2x12 pin connector Two additional power related connectors also exis
147. l Server Board S1400FP TPS 6 12 11 Alert Policy Table Associated with each PEF entry is an alert policy that determines which IPMI channel the alert is to be sent There is a maximum of 20 alert policy entries There are no pre configured entries in the alert policy table because the destination types and alerts may vary by user Each entry in the alert policy table contains four bytes for a maximum table size of 80 bytes 6 12 11 1 E mail Alerting The Embedded Email Alerting feature allows the user to receive e mails alerts indicating issues with the server This allows e mail alerting in an OS absent for example Pre OS and OS Hung situation This feature provides support for sending e mail by means of SMTP the Simple Mail Transport Protocol as defined in Internet RC 821 The e mail alert provides a text string that describes a simple description of the event SMTP alerting is configured using the embedded web server 6 12 12 SM CLP SM CLP Lite SMASH refers to Systems Management Architecture for Server Hardware SMASH is defined by a Suite of specifications managed by the DMTF that standardize the manageability interfaces for server hardware CLP refers to Command Line Protocol SM CLP is defined by the Server Management Command Line Protocol Specification SM CLP ver1 0 which is part of the SMASH suite of specifications The specifications and further information on SMASH can be found at the DMTF website http www dmitf org
148. l is off The operating system has saved context to the hard disk 3 S1 ACPI Slow blink DC power is still on The operating system has saved context and gone into a level of low power state ACPI Steady on System and the operating system are up and running 8 4 2 System ID Button and LED Support Pressing the System ID Button will toggle both the ID LED on the front panel and the Blue ID LED on the server board on and off The System ID LED is used to identify the system for maintenance when installed in a rack of similar server systems The System ID LED can also be toggled on and off remotely using the PMI Chassis Identify command which will cause the LED to blink for 15 seconds 8 4 3 System Reset Button Support When pressed this button will reboot and re initialize the system 88 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS On board Connector Header Overview 8 4 4 NMI Button Support When the NMI button is pressed it puts the server in a halt state and causes the BMC to issue a non maskable interrupt NMI This can be useful when performing diagnostics for a given issue where a memory download is necessary to help determine the cause of the problem Once an NMI has been generated by the BMC the BMC does not generate another NMI until the system has been reset or powered down The following actions cause the BMC to generate an NMI pulse Receiving a Chassis Control command to pulse the diag
149. lations the same slot positions across channels must hold the same DIMM type with regards to size and organization DIMM timings do not have to match but timings will be set to support all DIMMs populated that is DIMMs with slower timings will force faster DIMMs to the slower common timing modes 3 2 2 4 1 Independent Channel Mode In non ECC and x4 SDDC configurations each channel is running independently nonlock step that is each cache line from memory is provided by a channel To deliver the 64 byte cache line of data each channel is bursting eight 8 byte chunks Back to back data transfer in the same direction and within the same rank can be sent back to back without any dead cycle The independent channel mode is the recommended method to deliver most efficient power and bandwidth as long as the x8 SDDC is not required 3 2 2 4 2 Rank Sparing Mode In Rank Sparing Mode one rank is a spare of the other ranks on the same channel The spare rank is held in reserve and is not available as system memory The spare rank must have identical or larger memory capacity than all the other ranks sparing source ranks on the same channel After sparing the sparing source rank will be lost Rank Sparing Mode enhances the system s RAS capability by swapping out failing ranks of DIMMs Rank Sparing is strictly channel and rank oriented Each memory channel is a Sparing Domain For Rank Sparing to be available as a RAS option there must
150. ll record the hostname as NULL because the first block contains NULL data This scheme effectively does not allow a user to make a partial Hostname change Any Hostname change needs to start from Block 1 Byte 64 Block Selector 04h byte 16 is always ignored and set to NULL by BMC which effectively means we can set only 63 bytes User is responsible for keeping track of the Set series of commands and Local Memory contents While BMC firmware is in Set Hostname in Progress Update not complete the firmware continues using the Previous Hostname for DHCP purposes 6 12 4 Address Resolution Protocol ARP The BMC can receive and respond to ARP requests on BMC NICs Gratuitous ARPs are supported and disabled by default 6 12 5 Internet Control Message Protocol ICMP The BMC supports the following ICMP message types targeting the BMC over integrated NICs Echo request ping The BMC sends an Echo Reply Destination unreachable If message is associated with an active socket connection within the BMC the BMC closes the socket 6 12 6 Virtual Local Area Network VLAN The BMC supports VLAN as defined by IPMI 2 0 specifications VLAN is supported internally by the BMC not through switches VLAN provides a way of grouping a set of systems together so that they form a logical network This feature can be used to set up a management VLAN where only devices which are members of the VLAN will receive packets related to
151. ll Discrete Sech Non fatal 120 _ G A z Oth exceeded De Offset P3 Mem01 VRD 05h Hot Processor 3 Memory VRD Temperature Digital 01 Limi A d Tri Hot 2 3 99h All Discrete Sais Non fatal Zenn _ rig A l Oth exceeded De Offset P4 Mem23 VRD 05h Hot Processor 4 Memory VRD Temperature Digital 01 Limit A d Tri Hot 0 1 9Ah All an Discrete See d Non fatal Ze an SE Se A P4 Mem01 VRD 05h Hot Processor 4 Memory VRD Temperature Digital 01 Limit A d Tri Hot 2 3 9Bh All Discrete eat Non fatal ree des rg A Oth exceeded De Offset P4 Mem23 VRD 05h Hot Power Supply 1 NEE Chassis Fan Generic 01 State As and Trig i eon specific digital Asserted Non fatal vs Offset Mi PS1 Fan Tach P 04h discrete 1 126 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Tables Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Power Supply 1 SC Tachometer Ath Chassis Fan cial 01 State Non fatal As and S Trig M 7 PS1 Fan Tach specific 04h Gre Asserted De Offset 2 Power Supply 2 ST Tacnometer A4h Chassis Fan a E 01 State Non fatal As and S Trig M g PS2 Fan Tach specific 04h discrete Asserted De Offset 1 Power Supply 2 m Tac
152. lure Major 857C DIMM_J2 encountered a Serial Presence Detection SPD failure Major 857D DIMM_J3 encountered a Serial Presence Detection SPD failure Major 857E DIMM_K1 encountered a Serial Presence Detection SPD failure Major 857F DIMM_K2 encountered a Serial Presence Detection SPD failure Major Go to 85E0 85C0 DIMM_K3 failed test initialization Major 85C1 DIMM_L1 failed test initialization Major 85C2 DIMM_L2 failed test initialization Major 8503 DIMM_L3 failed test initialization Major 8504 DIMM_M1 failed test initialization Major 85C5 DIMM_M2 failed test initialization Major 85C6 DIMM_MsS failed test initialization Major 85C7 DIMM_N1 failed test initialization Major 85C8 DIMM_N2 failed test initialization Major 85C9 DIMM_N3 failed test initialization Major 85CA DIMM_O1 failed test initialization Major 85CB DIMM_O2 failed test initialization Major 85CC DIMM_O failed test initialization Major 85CD DIMM_P1 failed test initialization Major 85CE DIMM_P2 failed test initialization Major 85CF DIMM_P3 failed test initialization Major 85D0 DIMM_K8 disabled Major 85D1 DIMM_L1 disabled Major 85D2 DIMM_L2 disabled Major 85D3 DIMM_L3 disabled Major 85D4 DIMM_M1 disabled Major 85D5 DIMM_M2 disabled Major 85D6 DIMM M disabled Major 85D7 DIMM_N1 disabled Major 85D8 DIMM_N2 disabled Major 85D9 DIMM_N3 disabled Major 85DA DIMM_O1 disabled Major Revision 2 0 Intel order number G64246 003 143 Appendix D POST Code Errors Intel Server Boar
153. m Status LED The System Status LED on the server board is tied directly to the System Status LED on the front panel if present This LED indicates the current health of the server Possible LED states include solid green blinking green blinking amber and solid amber When the server is powered down transitions to the DC off state or S5 the BMC is still on standby power and retains the sensor and front panel status LED state established before the power down event When AC power is first applied to the system the status LED turns solid amber and then immediately changes to blinking green to indicate that the BMC is booting If the BMC boot process completes with no errors the status LED will change to solid green Table 49 System Status LED State Definitions Criticality on Lex that the System Status is healthy The system is not tn any errors AC power is present and BMC has booted and manageability functionality is up and running Www ei Hz blink Degraded System degraded 1 Redundancy loss such as power supply or fan Applies only if the associated platform sub system has redundancy capabilities 2 Fan warning or failure when the number of fully operational fans is more than minimum number needed to cool the system 3 Non critical threshold crossed Temperature including HSBP temp voltage input power to power supply output current for main power rail from power supply and Processor Thermal Control Therm Ctrl s
154. mands will be supported No support for optional DCM commands Optional power management and SEL roll over feature is not supported DCMI Asset tag will be independent of baseboard FRU asset Tag 6 12 17 Lightweight Directory Authentication Protocol LDAP The Lightweight Directory Access Protocol LDAP is an application protocol supported by the BMC for the purpose of authentication and authorization The BMC user connects with an LDAP server for login authentication This is only supported for non IPMI logins including the embedded web UI and SM CLP IPMI users passwords and sessions are not supported over LDAP LDAP can be configured IP address of LDAP server port and so on from the BMC s Embedded Web UI LDAP authentication and authorization is supported over the any NIC configured for system management The BMC uses a standard Open LDAP implementation for Linux Only open LDAP is supported by BMC Windows and Novell LDAP are not supported Revision 2 0 Intel order number G64246 003 77 Advanced Management Feature Support RMM4 Intel Server Board S1400FP TPS 7 Advanced Management Feature Support RMM4 The integrated baseboard management controller has support for advanced management features which are enabled when an optional Intel Remote Management Module 4 RMM4 is installed RMM4 is comprised of two boards RMM4 lite and the optional Dedicated Server Management NIC DMN Table 20 RMM4 Option Kits Intel
155. may affect the long term reliability of the processor and system The server board is designed to support the Intel Xeon Processor E5 2400 product family TDP guidelines up to and including 95W Disclaimer Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server 102 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Environmental Limits Specification building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits 11 2 MTBF The following is the calculated Mean Time Between Failures MTBF These values are derived using a historical failure rate and multiplied by factors for application electrical and or thermal stress and for device maturity You should view MTBF estimates as reference numbers only Telcordia SR_332 Issue II R
156. mber of the FRUSDR package Reboot the system 13 Configure desired BMC configuration settings Revision 2 0 Intel order number G64246 003 97 Intel Light Guided Diagnostics Intel Server Board S1400FP TPS 10 Intel Light Guided Diagnostics The server board includes several on board LED indicators to aid troubleshooting various board level faults The following diagram shows the location for each System ID LED co System Status DC D FA Diagnostic LED HY LED g Memory Fault System Fan 4 LEDs Fault LED CPU Fan Fault E OH E H 5 volt Standy by Leo OH SS System Fan 1 System Fan 2 System Fan 3 Fault LED Fault LED Fault LED AF005604 Figure 23 On Board LED Placement 10 1 System ID LED The server board includes a blue system ID LED which is used to visually identify a specific server installed among many other similar servers There are two options available for illuminating the System ID LED 1 The front panel ID LED Button is pushed which causes the LED to illuminate to a solid on state until the button is pushed again 2 An IPMI Chassis Identify command is remotely entered which causes the LED to blink The System ID LED on the server board is tied directly to the System ID LED on system front panel if present 98 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Intel Light Guided Diagnostics 10 2 System Status LED The server board includes a bi color Syste
157. nd specify policy directives for example set a platform power budget Node Manager NM is a platform resident technology that enforces power capping and thermal triggered power capping policies for the platform These policies are applied by exploiting subsystem knobs such as processor P and T states that can be used to control power consumption NM enables data center power management by exposing an external interface to management software through which platform policies can be specified It also implements specific data center power management usage models such as power limiting and thermal monitoring The NM feature is implemented by a complementary architecture utilizing the ME BMC BIOS and an ACPI compliant OS The ME provides the NM policy engine and power control limiting functions referred to as Node Manager or NM while the BMC provides the external LAN link by which external management software can interact with the feature The BIOS provides system power information utilized by the NM algorithms and also exports ACPI Source Language ASL 48 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Technology Support code used by OS Directed Power Management OSPM for negotiating processor P and T state changes for power limiting PMBus compliant power supplies provide the capability to monitoring input power consumption which is necessary to support NM Below are the some of the applications of In
158. nit PSU is 1 5 4 4 Power control fault power good assertion Power good assertion timeout Power unit present that is an incompatible model with one or more other PSUs in the system Revision 2 0 Intel order number G64246 003 145 Appendix E Supported Intel Server Chassis Intel Server Board S1400FP TPS Appendix E Supported Intel Server Chassis The Intel Server Board S1400FP requires a passive processor heatsink solution when integrated in the Intel pedestal server chassis listed below The Intel Server Board S1400FP supports up to 95W TDP Intel Xeon Processor Table 69 Compatible Intel Server Chassis P4000S family Intel Server Chassis SKU System Fans Storage Drives Power Supply s P4304XXSHDR Two Fixed Fans Four 3 5 Hotswap Drive Bay Two 460W CRPS P4304XXSFDR Two Fixed Fans Four 3 5 Fixed Drive Trays Two 460W CRPS If an active processor heatsink is used when the Intel Server Board S1400FP is integrated in the third party chassis the airflow direction should be followed as shown in the figure below CH z E Sr CPU Heat Sink D l y D B 8888 ii ei gi H AF005207 Figure 28 Processor Heatsink Installation 146 Intel order number 64246 003 Revision 2 0 Intel Server Board S1400FP TPS Glossary
159. nitiate a diagnostic dump to a file that can be sent to Intel for debug purposes Virtual Front Panel The Virtual Front Panel provides the same functionality as the local front panel The displayed LEDs match the current state of the local panel LEDs The displayed buttons for example power button can be used in the same manner as the local buttons Severity level indication of SEL events The web server UI displays the severity level associated with each event in the SEL The severity level correlates with the front panel system status LED OK Degraded Non Fatal or Fatal Display of ME sensor data Only sensors that have associated SDRs loaded will be displayed Ability to save the SEL to a file Ability to force HTTPS connectivity for greater security This is provided through a configuration option in the UI Display of processor and memory information as is available over IPMI over LAN Ability to get and set Node Manager NM power policies Display of power consumed by the server Ability to view and configure VLAN settings Warn user the reconfiguration of IP address will cause disconnect Capability to block logins for a period of time after several consecutive failed login attempts The lock out period and the number of failed logins that initiates the lock out period are configurable by the user Server Power Control Ability to force into Setup on a reset 6 12 14 Virtual Front Panel
160. nnel Mode In lockstep channel mode the cache line is split across channels This is done to support Single Device Data Correction SDDC for DRAM devices with 8 bit wide data ports Also the same address is used on both channels such that an address error on any channel is detectable by bad ECC The iMC module always accumulates 32 bytes before forwarding data so there is no latency benefit for disabling ECC 24 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture Lockstep channels must be populated identically That is each DIMM in one channel must have a corresponding DIMM of identical organization number ranks number banks number rows number columns DIMMs may be of different speed grades but the iMC module will be configured to operate all DIMMs according to the slowest parameters present by the Memory Reference Code MRC Performance in lockstep mode cannot be as high as with independent channels The burst length for DDR3 DIMMs is eight which is shared between two channels that are in lockstep mode Each channel of the pair provides 32 bytes to produce the 64 byte cache line DRAMs on independent channels are configured to deliver a burst length of eight The maximum read bandwidth for a given Rank is half of peak There is another drawback in using lockstep mode that is higher power consumption since the total activation power is about twice of the independent channel operation if c
161. nostic interrupt This command does not cause an event to be logged in the SEL Watchdog timer pre timeout expiration with NMI diagnostic interrupt pre timeout action enabled The following table describes behavior regarding NMI signal generation and event logging by the BMC Table 38 NMI Signal Generation and Event Logging NMI Causal Event Signal Front Panel Diag Interrupt Sensor Event Logging Generation Support Chassis control command pulse diagnostic X interrupt Front panel diagnostic interrupt button pressed Watchdog Timer pre timeout expiration with X X NMI diagnostic interrupt action 8 4 5 NIC Activity LED Support The Front Control Panel includes an activity LED indicator for each on board Network Interface Controller NIC When a network link is detected the LED will turn on solid The LED will blink once network activity occurs at a rate that is consistent with the amount of network activity that is occurring 8 4 6 Hard Drive Activity LED Support The drive activity LED on the front panel indicates drive activity from the on board hard disk controllers The server board also provides a header giving access to this LED for add in controllers 8 4 7 System Status LED Support The System Status LED is a bi color Green Amber indicator that shows the current health of the server system The system provides two locations for this feature one is located on the Front Control Panel the other is located on the back
162. ns persist across system reset but not across an AC power loss 7 1 5 Usage As the server is powered up the remote KVM session displays the complete BIOS boot process The user is able interact with BIOS setup change and save settings as well as enter and interact with option ROM configuration screens At least two concurrent remote KVM sessions are supported It is possible for at least two different users to connect to same server and start remote KVM sessions 7 1 6 Force enter BIOS Setup KVM redirection can present an option to force enter BIOS Setup This enables the system to enter F2 setup while booting which is often missed by the time the remote console redirects the video 7 2 Media Redirection The embedded web server provides a Java applet to enable remote media redirection This may be used in conjunction with the remote KVM feature or as a standalone applet The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD ROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears just like a local device to the server allowing system administrators or users to install software including operating systems copy files update BIOS and so on or boot the server from this device The following capabilities are supported The operation of remotely mounted devices is independent of the local devices on the server Both rem
163. nsole IPv6 configuration web page Revision 2 0 Intel order number G64246 003 65 Platform Management Functional Overview Intel Server Board S1400FP TPS The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and completely independently For example Pv4 can be DHCP configured while IPv6 is statically configured or vice versa The parameters for IPv6 are similar to the parameters for IPv4 with the following differences An IPv6 address is 16 bytes versus 4 bytes for IPv4 An IPv6 prefix is 0 to 128 bits whereas IPv4 has a 4 byte subnet mask The IPv6 Enable parameter must be set before any IPv6 packets will be sent or received on that channel There are two variants of automatic IP Address Source configuration versus just DHCP for IPv4 The three possible IPv6 IP Address Sources for configuring the BMC are Static Manual The IP Prefix and Gateway parameters are manually configured by the user The BMC ignores any Router Advertisement messages received over the network DHCPv 6 The IP comes from running a DHCPv 6 client on the BMC and receiving the IP from a DHCPv6 server somewhere on the network The Prefix and Gateway are configured by Router Advertisements from the local router The IP Prefix and Gateway are read only parameters to the BMC user in this mode Stateless auto config The Prefix and Gateway are configured by the router through Router Advertisements The BMC derives its IP in
164. odes Diagnostic LED Decoder 1 LED On O LED Off Checkpoint Upper Nibble Lower Nibble Description MSB LSB 8h 4h 2h 1h 8h 4h dh 1h ITT a aT LED 7 6 5 4 3 2 1 0 __ E MRC Fatal Error Codes No usable memory error 01h No memory was detected from SPD read or invalid config that causes no operable memory 02h Memory DIMMs on all channels of all sockets are disabled due to hardware memtest error 3h No memory installed All channels are disabled Memory is locked by Intel Trusted Execution Technology and is inaccessible DDR3 channel training error 01h Error on read DQ DQS Data Data Strobe init 02h Error on Receive Enable 3h Error on Write Leveling 04h Error on write DQ DQS Data Data Strobe Memory test failure 01h Software memtest failure 02h Hardware memtest failed 03h Hardware Memtest failure in Lockstep Channel mode requiring a channel to be disabled This is a fatal error which requires a reset and calling MRC with a different RAS mode to retry DIMM configuration population error Oth Different DIMM types UDIMM RDIMM LRDIMM are detected installed in the system 02h Violation of DIMM population rules 03h The 3rd DIMM slot cannot be populated when QR DIMMs are installed 04h UDIMMs are not supported in the 3rd DIMM slot 05h Unsupported DIMM Voltage Indicates
165. of functionality that has failed due to a fatal FW defect triggered by a rare sequence of events or a BMC hang due to some type of HW glitch for example power This feature is comprised of a set of capabilities whose purpose is to detect misbehaving subsections of BMC firmware the BMC CPU itself or HW subsystems of the BMC component and to take appropriate action to restore proper operation The action taken is dependent on the nature of the detected failure and may result in a restart of the BMC CPU one or more BMC HW subsystems or a restart of malfunctioning FW subsystems The BMC watchdog feature will only allow up to three resets of the BMC CPU such as HW reset or entire FW stack such as a SW reset before giving up and remaining in the UBOOT code This count is cleared upon cycling of power to the BMC or upon continuous operation of the BMC without a watchdog generated reset occurring for a period of gt 30 minutes The BMC FW logs a SEL event indicating that a watchdog generated BMC reset either soft or hard reset has occurred This event may be logged after the actual reset has occurred Refer sensor section for details for the related sensor definition The BMC will also indicate a degraded system status on the Front Panel Status LED after an BMC HW reset or FW stack reset This state which follows the state of the associated sensor will be cleared upon system reset or AC or DC power cycle Note A reset of the BMC may result in
166. of the embedded baseboard management controller e PMI 2 0 Compliant 400MHz 32 bit ARM9 processor with memory management unit MMU Two independent 10 100 1000 Ethernet Controllers with RMII RGMII support DDR2 3 16 bit interface with up to 800 MHz operation 12 10 bit ADCs Fourteen fan tachometers Eight Pulse Width Modulators PWM Chassis intrusion logic JTAG Master Eight DC interfaces with master slave and SMBus timeout support All interfaces are SMBus 2 0 compliant Parallel general purpose I O Ports 16 direct 32 shared Serial general purpose I O Ports 80 in and 80 out Three UARTs Platform Environmental Control Interface PECI Six general purpose timers Interrupt controller Multiple SPI flash interfaces NAND Memory interface Sixteen mailbox registers for communication between the BMC and host LPC ROM interface BMC watchdog timer capability SD MMC card controller with DMA support LED support with programmable blink rate controls on GPIOs Port 80h snooping capability Secondary Service Processor SSP which provides the HW capability of offloading time critical processing tasks from the main ARM core 3 4 3 1 Remote Keyboard Video Mouse and Storage KVMS Support USB 2 0 interface for Keyboard Mouse and Remote storage such as CD DVD ROM and floppy USB 1 1 USB 2 0 interface for PS2 to USB bridging remote keyboard and mouse Revision 2 0 Intel order number G642
167. ogy providing both AHCI see above for details on AHCI and integrated RAID functionality The industry leading RAID capability provides high performance RAID 0 1 5 and 10 functionality on up to 6 SATA ports of the C600 chipset Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives such as RAID 0 and RAID 1 on two disks Other RAID features include hot spare support SMART alerting and RAID 0 auto replace Software components include an Option ROM for pre boot configuration and boot functionality a Microsoft Windows compatible driver and a user interface for configuration and management of the RAID capability of the C600 chipset 3 3 6 PCI Interface The C600 chipset PCI interface provides a 33 MHz Revision 2 3 implementation The C600 chipset integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal C600 chipset requests This allows for combinations of up to four PCI down devices and PCI slots 3 3 7 Low Pin Count LPC Interface The C600 chipset implements an LPC Interface as described in the LPC 1 1 Specification The Low Pin Count LPC bridge function of the C600 resides in PCI Device 31 Function 0 In addition to the LPC bridge interface function D31 FO contains other functional units including DMA interrupt controllers timers power management system management GPIO and RTC 30 Intel order number G64246 003 Revision 2 0 Int
168. omparing to same type of DIMMs In Lockstep Channel Mode each memory access is a 128 bit data access that spans Channel B and Channel C Lockstep Channel mode is the only RAS mode that allows SDDC for x8 devices Lockstep Channel Mode requires that Channel B and Channel C must be populated identically with regards to size and organization DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel B and Channel C must be populated the same 3 2 2 5 Single Device Data Correction SDDC SDDC Single Device Data Correction is a technique by which data can be replaced by the IMC from an entire x4 DRAM device which is failing using a combination of CRC plus parity This is an automatic IMC driven hardware It can be extended to x8 DRAM technology by placing the system in Channel Lockstep Mode 3 2 2 6 Error Correction Code ECC Memory ECC uses extra bits 64 bit data in a 72 bit DRAM array to add an 8 bit calculated Hamming Code to each 64 bits of data This additional encoding enables the memory controller to detect and report single or multiple bit errors when data is read and to correct single bit errors 3 2 2 6 1 Correctable Memory ECC Error Handling A Correctable ECC Error is one in which a single bit error in memory contents is detected and corrected by use of the ECC Hamming Code included in the memory data For a correctable error data integrity is prese
169. ompatibility Check New Manageability Features Intel S1400 S1600 S2400 S2600 Server Platforms offer a number of changes and additions to the manageability features that are supported on the previous generation of servers The following is a list of the more significant changes that are common to this generation Integrated BMC based Intel Server boards 52 Sensor and SEL logging additions enhancements for example additional thermal monitoring capability SEL Severity Tracking and the Extended SEL Embedded platform debug feature which allows capture of detailed data for future analysis Provisioning and inventory enhancements o Inventory data system information export partial SMBIOS table Enhancements to fan speed control Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview DCMI 1 1 compliance product specific Support for embedded web server UI in Basic Manageability feature set Enhancements to embedded web server o Human readable SEL o Additional system configurability o Additional system monitoring capability o Enhanced on line help Enhancements to KVM redirection o Support for higher resolution Support for EU Lot6 compliance Management support for PMBus rev1 2 compliant power supplies BMC Data Repository Managed Data Region Feature Local Control Display Panel e System Airflow Monitoring Exit Air Temperature Monitoring Ethernet C
170. ompatible with all fan headers Add in Card Slots Five expansion slots Slot 6 PCI Express Gen3 x8 electrical with x16 physical connector from processor Slot 5 PCI Express Gen3 x8 electrical with x8 physical connector from processor Slot A PCI Express Gen3 x4 electrical with x8 physical connector from processor Slot 3 PCI Express Gen2 x4 electrical with x8 physical connector from PCH Slot 2 32 bit 33 MHz PCI slot from PCH Hard Drive and Optical Optical devices are supported Drive Support Two SATA connectors at 6Gbps Four SATA connectors at 3Gbps Up to eight SAS connectors at 3Gbps with optional Intel C600 RAID Upgrade Keys RAID Support Intel RSTe SW RAID 0 1 10 5 LSI SW RAID 0 1 10 5 I O control support External connections One DB39 serial port A connector One DB 15 video connector Two RJ 45 10 100 1000 Mb NIC connectors for S1400FP2 Four RJ 45 10 100 1000 Mb NIC connectors for S1400FP4 Four USB 2 0 ports at the back of the board Internal connections Two 2x5 pin USB headers each providing front panel support for two USB ports One DH10 serial port B header 2 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Overview One internal Type A USB 2 0 port One 9 pin USB header for eUSB SSD One 1x7 pin header for optional Intel Local Control Panel support One 30 pin front panel connector Video Support Integrated 2D video controller Du
171. on the system will boot into a BIOS Recovery Mode It is used when the system BIOS has become corrupted and is non functional requiring a new BIOS image to be loaded on to the server board Note The BIOS Recovery jumper is ONLY used to re install a BIOS image in the event the BIOS has become corrupted This jumper is NOT used when the BIOS is operating normally and you need to update the BIOS from one version to another The following steps demonstrate the BIOS recovery process 1 After downloading the latest System Update Package SUP from the Intel website copy the following files to the root directory of a USB media device e PMI EFI e Flash32 EFI e RML ROM REC CAP where BIOS revision number STARTUP NSH Power OFF the system Locate the BIOS Recovery Jumper on the server board and move the jumper block from pins 1 2 default to pins 2 3 recovery setting Insert the recovery media into a USB port Power ON the system The system will automatically boot into the embedded EFI Shell The STARTUP NSH file automatically executes and initiates the flash update When complete the IFlash utility will display a message 8 Power OFF the system and return the BIOS Recovery jumper to its default position 9 Power ON the system 10 Do NOT interrupt the BIOS POST during the first boot 11 Configure desired BIOS settings ST E Revision 2 0 Intel order number G64246 003 95 Jumper Blocks Intel Server Bo
172. only to BMC LAN traffic It bonds all available Ethernet devices but only one is active at a time When enabled if the active connection s leash is lost one of the secondary connections is automatically configured so that it has the same IP address Traffic immediately resumes on the new active connection 66 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview The LAN Failover enable disable command may be sent at any time After it has been enabled standard PM commands for setting channel configuration that specify a LAN channel other than the first will return an error code 6 12 3 5 BMC IP Address Configuration Enabling the BMC s network interfaces requires using the Set LAN Configuration Parameter command to configure LAN configuration parameter 4 IP Address Source The BMC supports this parameter as follows 1h static address manually configured Supported on all management NICs This is the BMC s default value 2h address obtained by BMC running DHCP Supported only on embedded management NICs IP Address Source value 4h address obtained by BMC running other address assignment protocol is not supported on any management NIC Attempting to set an unsupported IP address source value has no effect and the BMC returns error code OxCC Invalid data field in request Note that values Oh and 3h are no longer supported and will return a OxCC error comple
173. ontroller Thermal Monitoring Global Aggregate Temperature Margin Sensor Memory Thermal Management Power Supply Fan Sensors Energy Star Server Support Smart Ride Through SmaRT Closed Loop System Throttling CLST Power Supply Cold Redundancy Power Supply FW Update Power Supply Compatibility Check BMC FW reliability enhancements o Redundant BMC boot blocks to avoid possibility of a corrupted boot block resulting in a scenario that prevents a user from updating the BMC o BMC System Management Health Monitoring 6 2 Basic and Advanced Features The following table lists basic and advanced feature support Individual features may vary by platform See the appropriate Platform Specific EPS addendum for more information Table 12 Basic and Advanced Features IPMI 2 0 Feature Support xX XY In circuit BMC Firmware Update FRB 2 2 JS EE E Fan Redundancy Woro XX fRotSwapFanSuppot Xd Acoustic Management dd Revision 2 0 Intel order number G64246 003 53 Platform Management Functional Overview Intel Server Board S1400FP TPS 6 3 6 3 1 Feature Diagnostic Beep Code Support Power State Retention ARP DHCP Support PECI Thermal Management Support E mail Alerting Embedded Web Server SSH Support Integrated KVM Integrated Remote Media Redirection Ee Lightweight Directory Access Protocol LDAP Intel Intelligent Power Node Manager Support SMASH CLP x lt Integrated BMC Hardware Emulex
174. orted but not Validated Revision 2 0 Intel order number G64246 003 19 Functional Architecture Intel Server Board S1400FP TPS Table 4 RDIMM Support Guidelines Ranks Speed MT s and Voltage Validated by Per Slot per Channel SPC and DIMM Per Channel DPQ2 3 Memory Capacity Per DIMM DIMMI and Data 1 Slot per Channel 2 Slots per Channel Width 1DPC 1DPC 2DPC T35V 15V T35V 15V T35V E 1066 1066 1066 1066 1333 1066 1333 SRx8 1333 ie 1333 1600 Tee eee 1600 1066 1066 1333 1066 1333 DRx8 ee 1333 ne 1600 1066 1333 1600 1333 ie 1333 1066 1066 1333 1066 1333 SRx4 1088 1333 E 1600 1066 1333 1600 1333 1333 1600 1066 1066 1333 1066 1333 DRx4 ee 1333 eae 1600 1066 1333 1600 1333 1333 1600 Notes 1 Supported DRAM Densities are 1Gb 2Gb and 4Gb Only 2Gb and 4Gb are validated by Intel 2 Command Address Timing is 1N Supported and Validated Supported but not Validated 3 2 2 2 Memory population rules Note Although mixed DIMM configurations may be functional Intel only performs platform validation on systems that are configured with identical DIMMs installed On the Intel Server Board S1400FP a total of 6 DIMM slots is provided The nomenclature for DIMM sockets is detailed in the following table Table 5 Intel Server Board S1400FP DIMM Nomenclature Processor Socket 1 Channel B 0 Channel A 2 Channel C
175. ote and local devices are useable in parallel Either IDE CD ROM floppy or USB devices can be mounted as a remote device to the server Itis possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE IMG and CD ROM or DVD ROM ISO files See the Tested supported Operating System List for more information Media redirection supports redirection for both a virtual CD device and a virtual Floppy USB device concurrently The CD device may be either a local CD drive or else an ISO image file the Floppy USB device may be either a local Floppy drive a local USB device or else a disk image file Revision 2 0 Intel order number G64246 003 8 Advanced Management Feature Support RMM4 Intel Server Board S1400FP TPS The media redirection feature supports multiple encryption algorithms including RC4 and AES The actual algorithm that is used is negotiated with the client based on the client s capabilities A remote media session is maintained even when the server is powered off in standby mode No restart of the remote media session is required during a server reset or power on off An BMC reset for example due to an BMC reset after BMC FW update will require the session to be re established The mounted device is visible to and useable by managed system s OS and BIOS in both pre boot and post boot states The mounted device shows up in the BIOS boot order and it is possible
176. overall thermal and acoustics management In the event that BIOS is unable to configure the system for CLTT it defaults to open loop thermal throttling OLTT In the OLTT mode it is assumed that the DIMM temperature sensors are not available for fan speed control Throttling Revision 2 0 Intel order number G64246 003 61 Platform Management Functional Overview Intel Server Board S1400FP TPS levels are changed dynamically to cap throttling based on memory and system thermal conditions as determined by the system and DIMM power and thermal parameters The BMC s fan speed control functionality is linked to the memory throttling mechanism used The following terminology is used for the various memory throttling options Static Open Loop Thermal Throttling Static OLTT OLTT control registers that are configured by BIOS MRC remain fixed after post The system does not change any of the throttling control registers in the embedded memory controller during runtime Static Closed Loop Thermal Throttling Static CLTT CLTT control registers are configured by BIOS MRC during POST The memory throttling is run as a closed loop system with the DIMM temperature sensors as the control input Otherwise the system does not change any of the throttling control registers in the embedded memory controller during runtime Dynamic Open Loop Thermal Throttling Dynamic OLTT OLTT control registers are configured by BIOS MRC during POST Adjustments are
177. owes gt SE CPU mmer gt ma PCKE GENS x8 SLOT 6 x16 CONN Riser Board Support as S 8 PCI E GEN3 x8 SLOT 5 X8 CONN E 7 PCI E GENS x4 SLOT 4 X8 CONN a as PCI E GEN2 x4 SLOT 3 X8 CONN Se SLOT 2 PCI32 Legacy PC132 st Lol E PCI E GEN2 x2 Intel 1350 Gigabit NC SI PORT RMI 50Mbps Ethernet Gbit LAN 2 REI fe VIDEO RGB Gbit LAN x2 AE e e EH q PCI E GENI x1 Kee 8 SERIAL PORT 1 2 SATA 6Gops Intel C600 SMBUS PORTS Integrated ET Bes EH Chipset Se BMC SERIAL PORT 0 4 SATA 3Gbps 5 oe a ert USB 1 1 2 2x5 amp USB 2 0 Gr USB eUSB SSD Vertical USB TypeA Figure 12 Intel Server Board 1400FP Functional Block Diagram NC SI PORT RGMII Qe 7 t Comp DOR 3 RMM4 Lite LPC 33MHz RMM4 DNM CONN TPM CONN AFUCESEO Revision 2 0 Intel order number G64246 003 15 Functional Architecture Intel Server Board S1400FP TPS 3 1 Processor Support The Intel Server Board S1400FP includes one Socket B2 LGA 1356 processor socket and can support the following processor Intel Xeon processor E5 2400 product family with a Thermal Design Power TDP of up to 95W Intel Xeon processor E5 2400 v2 product family with a Thermal Design Power TDP of up to 95W Note Previous generation Intel Xeon processors are not supported on the Intel server board described in this documen
178. r number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix D POST Code Errors POST Progress Code 4 BIOS Recovery NA BIOS recovery has failed This typically happens so quickly failure after recovery us initiated that it sounds like a 2 4 beep code The Integrated BMC may generate beep codes upon detection of failure conditions Beep codes are sounded each time the problem is discovered such as on each power up attempt but are not sounded continuously Codes that are common across all Intel server boards and systems that use same generation chipset are listed in the following table Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 68 Integrated BMC Beep Codes Reason for Beep 1 5 2 1 No CPUs installed or first CPU socket is CPU1 socket is empty or sockets are populated empty incorrectly CPU1 must be populated before CPU2 1 5 2 4 MSID Mismatch MSID mismatch occurs if a processor is installed into a system board that has incompatible power capabilities 1 5 4 2 Power fault DC power unexpectedly lost power good dropout pe Power unit sensors report power unit failure offset timeout sensors report soft power control failure offset 1 5 1 2 VR Watchdog Timer sensor assertion VR controller DC power on sequence was not completed in time 1 5 1 4 Power Supply Status The system does not power on or unexpectedly powers off and a Power Supply U
179. rameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of the published operating or non operating limits Revision 2 0 Intel order number G64246 003 Overview Intel Server Board S1400FP TPS 2 Overview The Intel Server Board S1400FP is monolithic printed circuit boards PCBs with features designed to support the pedestal and rack server markets 2 1 Intel Server Boards S1400FP Feature Set Table 1 Intel Server Board S1400FP Feature Set Processor Support for one Intel Xeon E5 2400 processor or one Intel Xeon E5 2400 v2 processor in an FC LGA 1356 Socket B2 package with Thermal Design Power of up to 95W Memory Three memory channels six memory DIMMs Two memory DIMMs per channel Support for 1066 1333 MT s Unbuffered UDIMM LVDDR3 or DDR3 memory Support for 1066 1333 1600 MT s ECC Registered RDIMM DDR3 memory Support for 1066 1333 MT s ECC Registered RDIMM LVDDR3 memory No support for mixing of RDIMMs and UDIMMs No support for LRDIMMs No support for Quad Rank DIMMs Chipset Intel C602 A chipset with support for storage option upgrade keys Cooling Fan Support Support for One processor fan 4 pin header Three front system fans 4 pin headers One rear system fan 4 pin header 3 pin fans are c
180. rd Clear Jumper Block This jumper causes both the User password and the Administrator password to be cleared if they were set The operator should be aware that this creates a security gap until passwords have been installed again through the BIOS Setup utility This is the only method by which the Administrator and User passwords can be cleared unconditionally Other than this jumper passwords can only be set or cleared by changing them explicitly in BIOS Setup or by similar means No method of resetting BIOS configuration settings to default values will affect either the Administrator or User passwords 1 Power down the server and unplug the power cords 2 Move jumper from the default pins 1 and 2 operating position to the password clear position pins 2 and 3 Close the server chassis and reattach the power cords Power up the server and wait until POST completes Note BIOS Error Manager should report a 5224 and 5221 error codes Password clear jumper is set and Passwords cleared by jumper Power down the server and unplug the power cords Move the jumper back to the default position covering pins 1 and 2 Close the server chassis and reattach the power cords Power up the server TEO o NoD Or 96 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Jumper Blocks 9 4 BIOS Default Jumper Block This jumper resets BIOS Setup options to their default factory settings 1 2 3 4 5 Po
181. re 18 Integrated BMC Hardware 3 4 1 Super 1 0 Controller The integrated super I O controller provides support for the following features as implemented on the server board Two Fully Functional Serial Ports compatible with the 16C550 Serial IRQ Support Up to 16 Shared direct GPIOs Serial GPIO support for 80 general purpose inputs and 80 general purpose outputs available for host processor Programmable Wake up Event Support Plug and Play Register Set Power Supply Control Host SPI bridge for system BIOS support Revision 2 0 Intel order number G64246 003 37 Functional Architecture Intel Server Board S1400FP TPS 3 4 1 1 Keyboard and Mouse Support The server board does not support PS 2 interface keyboard and mouse However the system BIOS recognizes the USB specification compliant keyboard and mouse 3 4 1 2 Wake up Control The super I O contains functionality that allows various events to power on and power off the system 3 4 2 Graphics Controller and Video Support The integrated graphics controller provides support for the following features as implemented on the server board Integrated Graphics Core with 2D Hardware accelerator DDR 3 memory interface supporting up to 128MB of memory 16MB allocated to graphic Supports display resolutions up to 1600 x 1200 16bpp 60Hz High speed Integrated 24 bit RAMDAC Single lane PCI Express host interface running at Gen 1 speed The integrated vid
182. rom the serial port to the management console using LAN KVM has additional requirements of internal graphics and SOL may be used when KVM is not supported 3 3 23 On board Serial Attached SCSI SAS Serial ATA SATA Support and Options The Intel C602 A chipset provides storage support from two integrated controllers AHCI and SCU By default the server board will support two single 6Gb sec SATA ports routed from the AHCI controller to the two white SATA connectors labeled SATA_0 and SATA_1 four 3Gb sec SATA ports routed from the AHCI controller to the four black SATA connectors labeled SATA_2 to SATA_5 and four 3Gb sec SATA ports routed from the SCU to the four SATA SAS connectors labeled SATA SAS_ 0 to SATA SAS_3 Note The SATA SAS connector labeled SATA SAS_ 4 to SATA SAS_7 is NOT functional by default and is only enabled with the addition of an Intel RAID C600 Upgrade Key option supporting eight SAS SATA ports Standard are two embedded software RAID options using the storage ports configured from the SCU only Intel Embedded Server RAID Technology 2 ESRT2 based on LSI MegaRAID SW RAID technology supporting SATA RAID levels 0 1 10 Intel Rapid Storage Technology RSTe supporting SATA RAID levels 0 1 5 10 The server board is capable of supporting additional chipset embedded SAS and RAID options from the SCU controller when configured with one of several available Intel RAID
183. ror code 0xD5 Cannot Execute command Command or request parameter s are not supported in present state 6 12 3 6 DHCP BMC Hostname The BMC allows setting a DHCP Hostname using the Set Get LAN Configuration Parameters command 68 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview DHCP Hostname can be set regardless of the IP Address source configured on the BMC But this parameter is only used if the IP Address source is set to DHCP When Byte 2 is set to Update in progress all the 16 Block Data Bytes Bytes 3 18 must be present in the request When Block Size lt 16 it must be the last Block request in this series In other words Byte 2 is equal to Update is complete on that request Whenever Block Size lt 16 the Block data bytes must end with a NULL Character or Byte 0 All Block write requests are updated into a local Memory byte array When Byte 2 is set to Update is Complete the Local Memory is committed to the NV Storage Local Memory is reset to NULL after changes are committed When Byte 1 Block Selector 1 firmware resets all the 64 bytes local memory This can be used to undo any changes after the last Update in Progress User should always set the hostname starting from block selector 1 after the last Update is complete If the user skips block selector 1 while setting the hostname the BMC wi
184. rting When detecting an ECC error the host controller has the ability to send one of several messages to the chipset The host controller can instruct the chipset to generate GMIS NMI SERR or TCO interrupt 32 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture Function Disable The chipset provides the ability to disable the following integrated functions LAN USB LPC SATA PCI Express or SMBus Once disabled these functions no longer decode UC memory or PCI configuration space Also no interrupts or power management events are generated from the disabled functions Intruder Detect The chipset provides an input signal INTRUDER that can be attached to a switch that is activated by the system case being opened The chipset can be programmed to generate an SMI or TCO interrupt due to an active INTRUDERz signal 3 3 17 System Management Bus SMBus 2 0 The C600 chipset contains a SMBus Host interface that allows the processor to communicate with SMBus slaves This interface is compatible with most IC devices Special C commands are implemented The C600 chipset s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals slaves Also the C600 chipset supports slave functionality including the Host Notify protocol Hence the host controller supports eight command protocols of the SMBus interface see Syst
185. rved but it may be a warning sign of a true failure to come Note that some correctable errors are expected to occur The system BIOS has logic to cope with the random factor in correctable ECC errors Rather than reporting every correctable error that occurs the BIOS has a threshold and only logs a correctable error when a threshold value is reached Additional correctable errors that occur after the threshold has been reached are disregarded In addition on the expectation the server system may have extremely long operational runs without being rebooted there is a Leaky Bucket algorithm incorporated into the correctable error counting and comparing mechanism The Leaky Bucket algorithm reduces the correctable error count as a function of time as the system remains running for a certain amount of time the correctable error count will leak out Revision 2 0 Intel order number G64246 003 25 Functional Architecture Intel Server Board S1400FP TPS of the counting registers This prevents correctable error counts from building up over an extended runtime The correctable memory error threshold value is a configurable option in the lt F2 gt BIOS Setup Utility where you can configure it for 20 10 5 ALL None Once a correctable memory error threshold is reached the event is logged to the System Event Log SEL and the appropriate memory slot fault LED is lit to indicate on which DIMM the correctable error threshold crossin
186. s Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets Button S Button Switch Ge 00 Power Button Tri utton Sensor 09h All utton Switc Specific OK AS E rig A x Button 14h 6Fh 02 Reset Button Offset Mgmt System Digital BMC Watchdog OAh All Health Discrete 01 State Degraded As 8 Trig A Asserted Offset 28h 03h GE Volt pale 01 Stat As and Tri oltage Discrete State san 2 rig Watchdog SEI A 02h ah Asserted Fatal De offset M IX VR Watchdog 00 Fully redundant of 01 Redundancy Degraded lost 02 Redundancy degraded Degraded 03 Non redundant Sufficient Fan resources Degraded Redundancy1 Chassis Fan Generic Transition from As and Trig OCh as A Fan specific 04h OBh redundant De Offset Redundancy 04 Non redundant Sufficient Degraded resources Transition from insufficient 05 Non de Non Fatal insufficient resources Revision 2 0 Intel order number G64246 003 115 Appendix B Integrated BMC Sensor Tables Intel Server Board S1400FP TPS Full Sensor Name Sensor Platform Sensor Type Event Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in
187. s TPM physical presence verification Using BIOS TPM Setup the operator can turn ON or OFF TPM functionality and clear the TPM ownership contents After the requested TPM BIOS Setup operation is carried out the option reverts to No Operation The BIOS TPM Setup also displays the current state of the TPM whether TPM is enabled or disabled and activated or deactivated Note that while using TPM a TPM enabled operating system or application may change the TPM state independent of the BIOS setup When an operating system modifies the TPM state the BIOS Setup displays the updated TPM state The BIOS Setup TPM Clear option allows you to clear the TPM ownership key and to take control of the system with TPM You use this option to clear security settings for a newly initialized system or to clear a system for which the TPM ownership security key was lost Revision 2 0 Intel order number G64246 003 43 System Security Intel Server Board S1400FP TPS 4 2 3 1 Security Screen To enter the BIOS Setup press the F2 function key during boot time when the OEM or Intel logo displays The following message displays on the diagnostics screen and under the Quiet Boot logo screen Press lt F2 gt to enter setup When the Setup is entered the Main screen is displayed The BIOS Setup utility provides the Security screen to enable and set the user and administrative passwords and to lock out the front panel buttons so they cannot be used The Intel
188. se approximately at the same time All outputs must rise monotonically Each output voltage reach regulation within 50Ms Tyout on of each other during turn on the power supply Each output voltage fall out of regulation within 400ms Tyout ol Of each other during turn off Table 21 shows the timing requirements for the power supply being turned on and off from the AC input with PSON held low and the PSON signal with the AC input applied Revision 2 0 Intel order number G64246 003 107 Server Board Power Distribution Intel Server Board S1400FP TPS Table 59 Output Voltage Timing Item Description MIN MAX UNITS Tvout_tise Output voltage rise time from each main output 2 50 ms Output rise time for the 5Vstby output 1 25 ms Tvout_on All main outputs must be within regulation of each 50 ms other within this time T vout_off All main outputs must leave regulation within this 400 ms time i i A O SH d VA i i l l KEE ie lt Tyout rise lt gt Tvout_off i Tvout_on Figure 26 Output Voltage Timing Table 60 Turn On Off Timing Item Description Min Max Units Tsb_on_delay Delay from AC being applied to 5VSB being within 1500 ms regulation T ac_on_delay Delay from AC being applied to all output voltages 2500 ms being within regulation Tyout_holdup Time all output voltages stay within regulation 13 ms after loss of AC Tested at 75 of ma
189. sence Confirms and executes operating system TPM administrative command requests Provides BIOS Setup options to change TPM security states and to clear TPM ownership For additional details refer to the TCG PC Client Specific Implementation Specification the TCG PC Client Specific Physical Presence Interface Specification and the Microsoft BitLocker Requirement documents 4 2 2 Physical Presence Administrative operations to the TPM require TPM ownership or physical presence indication by the operator to confirm the execution of administrative operations The BIOS implements the operator presence indication by verifying the setup Administrator password A TPM administrative sequence invoked from the operating system proceeds as follows 1 User makes a TPM administrative request through the operating system s security software 2 The operating system requests the BIOS to execute the TPM administrative command through TPM ACPI methods and then resets the system 3 The BIOS verifies the physical presence and confirms the command with the operator 4 The BIOS executes TPM administrative command s inhibits BIOS Setup entry and boots directly to the operating system which requested the TPM command s 4 2 3 TPM Security Setup Options The BIOS TPM Setup allows the operator to view the current TPM state and to carry out rudimentary TPM administrative operations Performing TPM administrative options through the BIOS setup require
190. sign Specifications AEN 102 MTBF EStimate serce nae strat See a EEGENEN EE eeh 103 Over Voltage Protection Limits ENNEN 105 Loading COMMONS E 105 Voltage Regulation Rn 105 Transient Load Requirement Au 106 Capacitive Loading Conditions css siccici ees cere iat edeiit cotendn eaten gil ae teats eoeeeede are 106 Edel ie BEE 107 Output Voltage Tin EE 108 Turn laf neal Ml le 108 Integrated BMC ee EE 113 POST Progress Code LED Example ease ien Ze ag degen geseet deet eke 136 POST Progress Coes 24a fs dicate team see ean ean heen es Os 136 MRG Progress EE 138 POST Progress EE 139 POST Error Codes and Messages ENNEN 141 POST rei RE 144 Integrated BMC Beep e 145 Compatible Intel Server Chassis P4000S family cccccccccscscscssssesssesesesseesererenens 146 Intel order number G64246 003 xi List of Tables Intel Server Board S1400FP TPS lt This page is intentionally left blank gt xii Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Introduction 1 Introduction This Technical Product Specification TPS provides board specific information detailing the features functionality and high level architecture of the Intel Server Board S1400FP In addition you can obtain design level information for specific subsystems by ordering the External Product Specifications EPS or External Design Specifications EDS for a given subsystem EPS and EDS documents are not publicly available and you must order
191. system optimally cooled while reducing the amount of noise generated by the system fans Aggressive acoustics standards might require a trade off between fan speed and system performance parameters that contribute to the cooling requirements primarily memory bandwidth The BIOS BMC and SDRs work together to provide control over how this trade off is determined This capability requires the BMC to access temperature sensors on the individual memory DIMMs Additionally closed loop thermal throttling is only supported with buffered DIMMs 58 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview 6 11 2 Setting Throttling Mode Select the most appropriate memory thermal throttling mechanism for memory sub system from Auto DCLTT SCLTT and SOLTT Auto BIOS automatically detect and identify the appropriate thermal throttling mechanism based on DIMM type airflow input DIMM sensor availability DCLTT Dynamic Closed Loop Thermal Throttling for the SOD DIMM with system airflow input SCLTT Static Close Loop Thermal Throttling for the SOD DIMM without system airflow input SOLTT Static Open Loop Thermal Throttling for the DIMMs without sensor on DIMM SOD The default setting is Auto 6 11 3 Altitude Select the proper altitude that the system is distributed from 300m or less 301m 900m 901m 1500m Above 1500m options Lower
192. t One SSI compliant 2x4 pin power connector to provide 12 V power to the CPU voltage regulators and memory One SSI compliant 1x5 pin connector to provide DC monitoring of the power supply The following tables define these connector pin outs Table 22 Main Power Connector Pin out PS Yellow Yellow Pin 1 5 7 12 Vdc Yellow black DDR3_CPU1 Pin a 5 e 84 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS On board Connector Header Overview 12 Vdc Yellow black DDR3_CPU1 Table 24 Power Supply Auxiliary Signal Connector Pin out SMB_CLK_FP_PWR_R SMB_DAT_FP_PWR_R SMB_ALRT_3_ESB_R 3 3 V SENSE 3 3 V SENSE 8 3 System Management Headers 8 3 1 Intel Remote Management Module 4 Connector A 30 pin Intel RMM4 connector and a 7 pin Intel RMM4 Lite connector are included on the server board to support the optional Intel Remote Management Module 4 or Intel Remote Management Module 4 Lite This server board does not support third party management cards Note This connector is not compatible with the previous generation Intel Remote Management Modules Intel RMM RMM2 RMM3 Table 25 Intel RMM4 Connector Pin out i 3V3_AUX GND GND s Gno GND GND GND GND GND GND 3V3_AUX N A SPI_RMM4_LITE_DO SPI_RMM4_LITE_CS_N 8 Revision 2 0 Intel order number G64246 003 85 On board Connector Header Overview Intel Server Board S1400FP TPS
193. t Visit the Intel website for a complete list of supported processors 3 1 1 Processor Socket Assembly Each processor socket of the server board is pre assembled with an Independent Latching Mechanism ILM and Back Plate which allow for secure placement of the processor and processor heat to the server board The illustration below identifies each sub assembly component Heat Sink Server Board Independent Latching Mechanism ILM Figure 13 Processor Socket Assembly 16 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Functional Architecture 3 2 Processor Function Overview With the release of the Intel Xeon processor E5 2400 product family several key system components including the CPU Integrated Memory Controller IMC and Integrated IO Module IIO have been combined into a single processor package and feature per socket One Intel QuickPath Interconnect point to point links capable of up to 8 0 GT s up to 24 lanes of Gen 3 PCI Express links capable of 8 0 GT s and 4 lanes of DMI2 PCI Express Gen 1 interface with a peak transfer rate of 5 0 GT s The processor supports up to 46 bits of physical address space and 48 bit of virtual address space The following sections will provide an overview of the key processor features and functions that help to define the performance and architecture of the server board For more comprehensive processor specific information ref
194. t Reading Event Offset Triggers Contrib To Assert De Readable Event Rearm Standby Sensor name in Applicability Type System assert Value Data SDR Status Offsets 06 Redundant Degraded degraded from fully redundant state 07 Redundant Degraded Transition from non redundant state 00 Timer expired status only Sensor lo1 Hardreser Trig 01 Hard reset IPMI Watchdog oh All Watchdog 2 Specific OK As Offset A xX IPMI Watchdog 23h 6Fh 02 Power down 03 Power cycle 08 Timer interrupt Chassis 00 Chassis e Physical Sensor Physical Security 04h Intrusion GC Specific intrusion Degraded As and Trig A x Physical Scrty i chassis oep SFR 04 LAN leash lost OK De Offset specific FP Interrupt Ghas Critical Sensor 00 Front panel Trig i Interrupt Specific NMl diagnostic FP NMI Diag osh specific p H eee a OK As Offset S Int 13h 6Fh errup e Digital 01 State asserted SMI Timeout D All SMI Timeout Discrete Fatal As and 8 Trig A 8 SMI Timeout F3h De Offset 03h ae Event Event Logging Sensor 9 07h All Disabled Specific 02 Log area OK As Trig A x System Event reset cleared Offset 10h 6Fh Log System Event Sensor 02 Undetermined System Event y Specific system H W failure Fatal and Trig System Event osh Al den 6Fh 04 PEF action OK aw j Offset e S 114 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix B Integrated BMC Sensor Table
195. t SOL 2 0 Configuration Parameter and Set SOL 2 0 Configuration Parameters These commands are used to get and set the values of the SOL configuration parameters The parameters are implemented on a per channel basis Activating SOL This command is not accepted by the BMC It is sent by the BMC when SOL is activated to notify a remote client of the switch to SOL Activating a SOL session requires an existing IPMl over LAN session If encryption is used it should be negotiated when the IPMl over LAN session is established 70 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Platform Management Functional Overview 6 12 9 Platform Event Filter PEF The BMC includes the ability to generate a selectable action such as a system power off or reset when a match occurs to one of a configurable set of events This capability is called Platform Event Filtering or PEF One of the available PEF actions is to trigger the BMC to send a LAN alert to one or more destinations The BMC supports 20 PEF filters The first twelve entries in the PEF filter table are pre configured but may be changed by the user The remaining entries are left blank and may be configured by the user Table 17 Factory Configured PEF Table Entries Event Filter Offset Mask Events Number 1 Non critical critical and non recoverable Temperature sensor out of range 2 Non critical critical and non r
196. t as the watchdog timeout action The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan and before displaying a request for a boot password If the processor fails and causes an FRB2 timeout the BMC resets the system The BIOS gets the watchdog expiration status from the BMC If the status shows an expired FRB2 timer the BIOS enters the failure in the system event log SEL In the OEM bytes entry in the SEL the last POST code generated during the previous boot attempt is written FRB2 failure is not reflected in the processor status sensor value The FRB2 failure does not affect the front panel LEDs 6 8 Sensor Monitoring The BMC monitors system hardware and reports system health Some of the sensors include those for monitoring Component board and platform temperatures Board and platform voltages System fan presence and tach Chassis intrusion Front Panel NMI Front Panel Power and System Reset Buttons SMI timeout Processor errors The information gathered from physical sensors is translated into IPMI sensors as part of the IPMI Sensor Model The BMC also reports various system state changes by maintaining virtual sensors that are not specifically tied to physical hardware See Appendix B Integrated BMC Sensor Tables for additional sensor information 6 9 Field Replaceable Unit FRU Inventory Device The BMC implements the interface for logical FRU inventory devices as speci
197. t of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Intel Server Board S1400FP Layout S1400FP4 as SHOWN ccccccceescsseseeeeeeeteens 4 Intel Server Board S1400FP Layout 5 Intel Server Board S1400FP Mounting Hole Locations 1 Of 3 7 Intel Server Board S1400FP Mounting Hole Locations 2 Of 2 8 Intel Server Boards S1400FP Major Connector Pin 1 Locations 1 Of 2 9 Intel Server Boards S1400FP Major Connector Pin 1 Locations 2 of 2 10 Intel Server Boards S1400FP Primary Side Keepout Zone 11 Intel Server Boards S1400FP Primary Side Card Side Keepout Zone s 0 21 12 Intel Server Boards S1400FP Primary Side Air Duct Keepout Zone ssiseieeeeieeie 12 Intel Server Boards S1400FP Second Side Keepout Zone n 13 Intel Server Boards S1400FP Rear I O Layout 14 Intel Server Board S1400FP Functional Block Dlagram 15 Breet El EE 16 Intel Server Board S1400FP DIMM Slot Layout 21 Functional Block Diagram of Processor IIO Sub system eeceeeeeeeeeeeeeeeeeeenaeees 27 Functional Block Diagram Chipset Supported Features and Functions 28 Integrated Base
198. tel Intelligent Power Node Manager technology Platform Power Monitoring and Limiting The ME NM monitors platform power consumption and hold average power over duration It can be queried to return actual power at any given instance The power limiting capability is to allow external management software to address key IT issues by setting a power budget for each server For example if there is a physical limit on the power available in a room then IT can decide to allocate power to different servers based on their usage servers running critical systems can be allowed more power than servers that are running less critical workload Inlet Air Temperature Monitoring The ME NM monitors server inlet air temperatures periodically If there is an alert threshold in effect then ME NM issues an alert when the inlet room temperature exceeds the specified value The threshold value can be set by policy Memory Subsystem Power Limiting The ME NM monitors memory power consumption Memory power consumption is estimated using average bandwidth utilization information Processor Power monitoring and limiting The ME NM monitors processor or socket power consumption and holds average power over duration It can be queried to return actual power at any given instant The monitoring process of the ME will be used to limit the processor power consumption through processor P states and dynamic core allocation Core allocation at boot time Res
199. terface for management traffic The baseboard NIC s are connected to a single BMC RMII RGMII port that is configured for RMII operation The NC SI protocol is used for this connection and provides a 100 Mb s full duplex multi drop interface which allows multiple NICs to be connected to the BMC The physical layer is based upon RMII however RMII is a point to point bus whereas NC SI allows 1 master and up to 4 slaves The logical layer configuration commands is incompatible with RMI The server board will provide support for a dedicated management channel that can be configured to be hidden from the host and only used by the BMC This mode of operation is configured from a BIOS setup option 6 12 3 2 2 Dedicated Management Channel An additional LAN channel dedicated to BMC usage and not available to host SW is supported from an optional RMM4 add in card There is only a PHY device present on the RMM4 add in card The BMC has a built in MAC module that uses the RGMII interface to link with the card s PHY Therefore for this dedicated management interface the PHY and MAC are located in different devices The PHY on the RMM4 connects to the BMC s other RMII RGMII interface that is the one that is not connected to the baseboard NICs This BMC port is configured for RGMII usage In addition to the use of an RMM4 add in card for a dedicated management channel on systems that support multiple Ethernet ports on the baseboard the system BIO
200. tes the PCI Express interface and supports up to 24 lanes of PCI Express Following is the key attribute of the PCI Express interface o Gen3 speeds at 8 GT s no 8b 10b encoding DMI2 Interface to the PCH The platform requires an interface to the legacy Southbridge PCH which provides basic legacy functions required for the server platform and operating systems Since only one PCH is required and allowed for the system any sockets which do not connect to PCH would use this port as a standard x4 PCI Express 2 0 interface Integrated IOAPIC Provides support for PCI Express devices implementing legacy interrupt messages without interrupt sharing 26 Intel order number G64246 003 Revision 2 0 Intel Server Board S1 400FP TPS Functional Architecture Non Transparent Bridge PCI Express non transparent bridge NTB acts as a gateway that enables high performance low overhead communication between two intelligent subsystems the local and the remote subsystems The NTB allows a local processor to independently configure and control the local subsystem provides isolation of the local host memory domain from the remote host memory domain while enabling status and data exchange between the two domains Intel QuickData Technology Used for efficient high bandwidth data movement between two locations in memory or from memory to I O DDR IIl MEMORY Intel Xeon CHANNEL gt ne Processor E5 2400 a nur zs CPU CHANNEL
201. them through your Intel representative 1 1 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Overview Chapter 3 Functional Architecture Chapter 4 System Security Chapter 5 Technology Support Chapter 6 Platform Management Functional Overview Chapter 7 Advanced Management Feature Support RMM4 Chapter 8 On board Connector Header Overview Chapter 9 Jumper Blocks Chapter 10 Intel Light Guided Diagnostics Chapter 11 Environmental Limits Specifications Chapter 12 Server Board Power Distribution Appendix A Integration and Usage Tips Appendix B Integrated BMC Sensor Tables Appendix C POST Code Diagnostic LED Decoder Appendix D POST Code Errors Appendix E Supported Intel Server Chassis Glossary Reference Documents 1 2 Server Board Use Disclaimer Intel Server Boards contain a number of high density VLSI Very Large Scale Integration and power delivery components that require adequate airflow for cooling Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system meets the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating pa
202. tion Technology The Intel Xeon Processor E5 4600 2600 2400 1600 Product Families support Intel Trusted Execution Technology Intel TXT which is a robust security environment Designed to help protect against software based attacks Intel Trusted Execution Technology integrates new security features and capabilities into the processor chipset and other platform components When used in conjunction with Intel Virtualization Technology Intel Trusted Execution Technology provides hardware rooted trust for your virtual applications This hardware rooted security provides a general purpose safer computing environment capable of running a wide variety of operating systems and applications to increase the confidentiality and integrity of sensitive information without compromising the usability of the platform Intel Trusted Execution Technology requires a computer system with Intel Virtualization Technology enabled both VT x and VT d an Intel Trusted Execution Technology enabled processor chipset and BIOS Authenticated Code Modules and an Intel Trusted Execution Revision 2 0 Intel order number G64246 003 45 System Security Intel Server Board S1400FP TPS Technology compatible measured launched environment MLE The MLE consists of a virtual machine monitor an OS or an application In addition Intel Trusted Execution Technology requires the system to include a TPM v1 2 as defined by the Trusted Computing Group TPM
203. tion code 6 12 3 5 1_ Static IP Address IP Address Source Values Oh 1h and 3h The BMC supports static IP address assignment on all of its management NICs The IP address source parameter must be set to static before the IP address the subnet mask or gateway address can be manually set The BMC takes no special action when the following IP address source is specified as the IP address source for any management NIC 1h Static address manually configured The Set LAN Configuration Parameter command must be used to configure LAN configuration parameter 3 P Address with an appropriate value The BIOS does not monitor the value of this parameter and it does not execute DHCP for the BMC under any circumstances regardless of the BMC configuration 6 12 3 5 2 Static LAN Configuration Parameters When the IP Address Configuration parameter is set to 01h static the following parameters may be changed by the user LAN configuration parameter 3 IP Address LAN configuration parameter 6 Subnet Mask LAN configuration parameter 12 Default Gateway Address When changing from DHCP to Static configuration the initial values of these three parameters will be equivalent to the existing DHCP set parameters Additionally the BMC observes the following network safety precautions 1 The user may only set a subnet mask that is valid per IPv4 and RFC 950 Internet Standard Subnetting Procedure Invalid subnet values return a
204. tor and User passwords are supported by the BIOS An Administrator password must be installed to set the User password The maximum length of a password is 14 characters A password can have alphanumeric a z A Z 0 9 characters and it is case sensitive Certain special characters are also allowed from the following set 1 GE amp _ 2 The Administrator and User passwords must be different from each other An error message will be displayed if there is an attempt to enter the same password for one as for the other The use of Strong Passwords is encouraged but not required In order to meet the criteria for a Strong Password the password entered must be at least 8 characters in length and must include at least one each of alphabetic numeric and special characters If a weak password is entered a popup warning message will be displayed although the weak password will be accepted Once set a password can be cleared by changing it to a null string This requires the Administrator password and must be done through BIOS Setup or other explicit means of changing the passwords Clearing the Administrator password will also clear the User password Alternatively the passwords can be cleared by using the Password Clear jumper if necessary Resetting the BIOS configuration settings to default values by any method has no effect on the Administrator and User passwords Entering the User password allows the user to mod
205. trict the number of cores for OS VMM use by limiting how many cores are active at boot time After the cores are turned off the CPU will limit how many working cores are visible to BIOS and OS VMM The cores that are turned off cannot be turned on dynamically after the OS has started It can be changed only at the next system reboot Core allocation at run time This particular use case provides a higher level processor power control mechanism to a user at run time after booting An external agent can dynamically use or not use cores in the processor subsystem by requesting ME NM to control them specifying the number of cores to use or not use 5 3 1 Hardware Requirements NM is supported only on platforms that have the NM FW functionality loaded and enabled on the Management Engine ME in the SSB and that have a BMC present to support the external LAN interface to the ME NM power limiting features requires a means for the ME to monitor input power consumption for the platform This capability is generally provided by means of PMBus compliant power supplies although an alternative model using a simpler SMBus power monitoring device is possible there is potential loss in accuracy and responsiveness using non PMBus devices The NM SmaRT CLST feature does specifically require PMBus compliant power supplies as well as additional hardware on the baseboard Revision 2 0 Intel order number G64246 003 49 Platform Management Functional Overvie
206. turns a completion code of 0x80 parameter not supported for any read write of parameter 25 If the BMC IP address source is DHCP then the following behavior is seen If the BMC is first configured for DHCP prior to enabling VLAN when VLAN is enabled the BMC performs a discovery on the new VLAN in order to obtain a new BMC IP address If the BMC is configured for DHCP before disabling VLAN when VLAN is disabled the BMC performs a discovery on the LAN in order to obtain a new BMC IP address If the BMC IP address source is Static then the following behavior is seen If the BMC is first configured for static prior to enabling VLAN when VLAN is enabled the BMC has the same IP address that was configured before It is left to the management application to configure a different IP address if that is not suitable for VLAN If the BMC is configure for static prior to disabling VLAN when VLAN is disabled the BMC has the same IP address that was configured before It is left to the management application to configure a different IP address if that is not suitable for LAN 6 12 7 Secure Shell SSH Secure Shell SSH connections are supported for SMASH CLP sessions to the BMC 6 12 8 Serial over LAN SOL 2 0 The BMC supports IPMI 2 0 SOL IPMI 2 0 introduced a standard serial over LAN feature This is implemented as a standard payload type 01h over RMCP Three commands are implemented for SOL 2 0 configuration Ge
207. uch as Tektronix model P6046 or equivalent 12 1 10 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in below Table 19 This is measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors A 10uF tantalum capacitor in parallel with a 0 1uF ceramic capacitor is placed at the point of measurement Table 58 Ripples and Noise 12V1 12V2 5VSB Sieten SomVpp Zo0mVvp p SomVp p The test set up shall be as shown below MV OUT LOAD MUST BE O ac HOT i Loap ISOLATED FROM POWER SUPPLY ape SIS R A THE GROUND OF O AC NEUTRAL RETURN THE POWER 10uF up SUPPLY AC GROUND GENERAL NOTES Ww Le AD THE OUTPUT WITH ITS MINIMUM LOAD CURRENT 2 CONNECT THE PROBES AS SHOWN ANN 3 REPEAT THE MEASUREMENTS WITH THE MAXIMUM LOAD ON THE OUTPUT vort s SCOPE NOTE USE A TEKTRONIX 7834 OSCILLOSCOPE WITH 7A13 AND DIFFERENTIAL PROBE P6055 OR EQUIVALENT Figure 25 Differential Noise test setup Note When performing this test the probe clips and capacitors should be located close to the load 12 1 11 Timing Requirements These are the timing requirements for the power supply operation The output voltages rise from 10 to within regulation limits Tyout rise Within 2 to 50ms except for 5VSB it is allowed to rise from 1 to 25ms The 3 3V 5V and 12V1 12V2 output voltages should start to ri
208. ve any effect on this error Major The error message is displayed on the Error Manager screen and an error is logged to the SEL The POST Error Pause option setting in the BIOS setup determines whether the system pauses to the Error Manager for this type of error so the user can take immediate corrective action or the system continues booting Note that for 0048 Password check failed the system halts and then after the next reset reboot will displays the error code on the Error Manager screen Fatal The system halts during post at a blank screen with the text Unrecoverable fatal error found System will not boot until the error is resolved and Press lt F2 gt to enter setup The POST Error Pause option setting in the BIOS setup does not have any effect with this class of error When the operator presses the F2 key on the keyboard the error message is displayed on the Error Manager screen and an error is logged to the SEL with the error code The system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system Note The POST error codes in the following table are common to all current generation Intel server platforms Features present on a given server board system will determine which of the listed error codes are supported 140 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Appendix D POST Code Errors Table 66 POST Error Codes and
209. ver and an OEM customizable web GUI which exposes the manageability features of the BMC base feature set It is supported over all on board NICs that have management connectivity to the BMC as well as an optional RMM4 dedicated add in management NIC At least two concurrent web sessions from up to two different users is supported The embedded web user interface shall support the following client web browsers Microsoft Internet Explorer 7 0 Microsoft Internet Explorer 8 0 Microsoft Internet Explorer 9 0 Mozilla Firefox 3 0 Mozilla Firefox 3 5 Mozilla Firefox 3 6 The embedded web user interface supports strong security authentication encryption and firewall support since it enables remote server configuration and control Embedded web server uses ports 80 and 443 The user interface presented by the embedded web user interface shall authenticate the user before allowing a web session to be initiated Encryption using 128 bit SSL is supported User authentication is based on user id and password The GUI presented by the embedded web server authenticates the user before allowing a web session to be initiated It presents all functions to all users but grays out those functions that the user does not have privilege to execute For example if a user does not have privilege to power control then the item shall be displayed in grey out font in that user s UI display The web GUI also provides a launch point for some of the advanced f
210. w Intel Server Board S1400FP TPS 6 Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions monitor and report system health and control various thermal and performance features to maintain when possible server functionality in the event of component failure and or environmentally stressed conditions This chapter provides a high level overview of the platform management features and functionality implemented on the server board For more in depth and design level Platform Management information please reference the BMC Core Firmware External Product Specification EPS and BIOS Core External Product Specification EPS for Intel Server products based on the Intel Xeon processor E5 2400 product families 6 1 Baseboard Management Controller BMC Firmware Feature Support The following sections outline features that the integrated BMC firmware can support Support and utilization for some features is dependent on the server platform in which the server board is integrated and any additional system level components and options that may be installed 6 1 1 IPMI 2 0 Features Baseboard management controller BMC e PMI Watchdog timer Messaging support including command bridging and user session support Chassis device functionality including power reset control and BIOS boot fla
211. wer down the server and unplug the power cords Move BIOS DFLT jumper from the default pins 1 and 2 position to the Set BIOS Defaults position pins 2 and 3 Wait 5 seconds then move the jumper back to the default position of pins 1 and 2 Install Power Cords Power on system i Note BIOS Error Manager should report a 5220 error code BIOS Settings reset to 9 5 default settings BMC Force Update Jumper Block The BMC Force Update jumper is used to put the BMC in Boot Recovery mode for a low level update It is used when the BMC has become corrupted and is non functional requiring a new BMC image to be loaded on to the server board 1 2 3 4 g CR KEE Turn off the system and remove power cords Move the BMC FRC UPDT Jumper from the default pins 1 and 2 operating position to the Force Update position pins 2 and 3 Re attach system power cords Power on the system Note System Fans will boost and the BIOS Error Manager should report an 84F3 error code Baseboard Management Controller in update mode Boot to the EFI shell and update the BMC firmware using BMC NSH where is the version number of the BMC When update has successfully completed power off system Remove AC power cords Move BMC FRC UPDT jumper back to the default position Install AC power cords Power on system Boot to the EFI shell and update the FRU and SDR data using FRUSDR nsh where is the version nu
212. will never stopped or shift into lower fan speed whatever the aggregate sensor temperatures are satisfied or not The default setting is Disabled Note 1 The efficiency of the features listed above may or may not be in effective depends on the actual thermal characters of a specific system 2 Refer to the Inte server system TPS for the board in Intel chassis thermal and acoustic management 3 Refer to Fan Control Whitepaper for the board in 3rd party chassis fan speed control customization Revision 2 0 Intel order number G64246 003 59 Platform Management Functional Overview Intel Server Board S1400FP TPS 6 11 7 Fan Profiles The server system supports multiple fan control profiles to support acoustic targets and American Society of Heating Refrigerating and Air Conditioning Engineers ASHRAE compliance The BIOS Setup utility can be used to choose between meeting the target acoustic level or enhanced system performance This is accomplished through fan profiles The BMC supports eight fan profiles numbered from 0 to 7 Table 15 Fan Profiles Type Profile Details OLTT 0 Acoustic 300M altitude OLTT 1 Performance 300M altitude OLTT 2 Acoustic 900M altitude OLTT 3 Performance 900M altitude OLTT 4 Acoustic 1500M altitude OLTT 5 Performance 1500M altitude OLTT 6 Acoustic 3000M altitude OLTT 7 Performance 3000M altitude CLTT 0 Acoustic 300M altitude CLTT 1 Performanc
213. ximum load Tpwok_holdup Delay from loss of AC to de assertion of PWOK 12 ms Tested at 75 of maximum load Tpson_on_delay Delay from PSON active to output voltages within 5 400 ms regulation limits T pson_pwok Delay from PSON deactivate to PWOK being de 50 ms asserted Tpwok_on Delay from output voltages within regulation limits 100 500 ms to PWOK asserted at turn on T pwok_off Delay from PWOK de asserted to output voltages ms 3 3V 5V 12V 12V dropping out of regulation 1 limits 108 Intel order number G64246 003 Revision 2 0 Intel Server Board S1400FP TPS Server Board Power Distribution Item Description Min Max Units Tpwok_low Duration of PWOK being in the de asserted state ms during an off on cycle using AC or the PSON 100 signal Tsb_vout Delay from 5VSB being in regulation to O Ps ms see 10 1000 being in regulation at AC turn on TS5VSB_holdup Time the 5VSB output voltage stays within 70 ms regulation after loss of AC AC Input Tyout_holdup i i Tac_on_delay l j l Tpwok low Tssb_on_delay k Twoi k Tpwok ott i Ta on deier i TS Tpwok off PWOK i i aT wane i ij E Tron pot i i i H l i e lt x i l 5VSB 7 tr i I j Tvou 5VSB_holdup i foe JI j Tpson_on_delay PSON l i i i i i lt AC turn on off cycle gt t lt PSON turn on off cycle I Figure 27 Turn On Off Timin
214. y BMC running DHCP Once this parameter is set the BMC initiates the DHCP process within approximately 100 ms If the BMC has previously been assigned an IP address through DHCP or the Set LAN Configuration Parameter command it requests that same IP address to be reassigned If the BMC does not receive the same IP address system management software must be reconfigured to use the new IP address The new address is only available in band through the IPMI Get LAN Configuration Parameters command Changing the P Address Source parameter from 2h to any other supported value will cause the BMC to stop the DHCP process The BMC uses the most recently obtained IP address until it is reconfigured If the physical LAN connection is lost that is the cable is unplugged the BMC will not re initiate the DHCP process when the connection is re established 6 12 3 5 4 DHCP related LAN Configuration Parameters Users may not change the following LAN parameters while the DHCP is enabled LAN configuration parameter 3 IP Address LAN configuration parameter 6 Subnet Mask LAN configuration parameter 12 Default Gateway Address To prevent users from disrupting the BMC s LAN configuration the BMC treats these parameters as read only while DHCP is enabled for the associated LAN channel Using the Set LAN Configuration Parameter command to attempt to change one of these parameters under such circumstances has no effect and the BMC returns er
215. y for Directed I O VT d is primarily concerned with virtualizing I O efficiently in a VMM environment This would generally be a chipset I O feature but in the Second Generation Intel Core Processor Family there is an Integrated I O unit embedded in the processor and the IIO is also enabled for VT d Intel Virtualization Technology for Connectivity VT c is primarily concerned I O hardware assist features complementary to but independent of VT d Intel VT x is designed to support multiple software environments sharing same hardware resources Each software environment may consist of OS and applications The Intel Virtualization Technology features can be enabled or disabled in the BIOS setup The default behavior is disabled Intel VT d is supported jointly by the Intel Xeon Processor E5 4600 2600 2400 1600 Product Families and the C600 chipset Both support DMA remapping from inbound PCI Express memory Guest Physical Address GPA to Host Physical Address HPA PCI devices are directly assigned to a virtual machine leading to a robust and efficient virtualization The Intel S 4600 S2600 S2400 S1600 S1400 Server Board Family BIOS publishes the DMAR table in the ACPI Tables For each DMA Remapping Engine in the platform one exact entry of DRHD DMA Remapping Hardware Unit Definition structure is added to the DMAR The DRHD structure in turn contains a Device Scope structure that describes the PCI endpoints and or sub

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