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Intel Xeon E3-1220L

1. ccccceccee eee eee nnn e tee 20 2 4 PCI Memory Address Range lt cicccsiesdcicivoie aaae nnen ic ee nen be apis eterna ene 24 2 5 Case 1 Less than 4 GB of Physical Memory no remap ecee cece eee eee eee eee ee ee 29 2 6 Case 2 Greater than 4 GB of Physical MEMOry cceeeeeee eee e tent eee teeta teat ee eae 30 2 7 Example DMI Upstream VCO Memory Mab ceeeeseee nent eee eee teeta eee eae eeeaes 39 2 8 PEG Upstream VCO Memory Map ccceccece cette rere nena 41 Tables 2 1 Register Attributes and Terminology ssssssssrsssssrrsssrrrsssesrnrnnrrrrnnrrrrrrasennnnrrrrseere 13 2 2 Register Attribute Modifiers sssssssssssrrsssrrrrrssnnrurrrrrrsesrrnunrrrnunnrrrraneeenurerrrrnane 14 273 SMM regi M Sirene a unun Gas aa aan a rE TEE M Ae UER EEEE E REEE SEENA 35 2 4 IGD Frame Buffer ACCESSES cc cece eee nett eee 42 2 5 LGD VGA O MAPPING iine nei atin eds ena iaae a o ra en dad EAA yaa ERa 42 2 6 VGA and MDA I O Transaction Mapping sssssssssssrrrssrrrrrrsssrirnntrirrnnrrrnnarirrnrrrrrnan 43 2 7 PCI Device 0 Function 0 Register Address Map sssssssisssssrsssrrrrssrrirenrsrrrrrrrrrrrser 46 2 8 PCI Device 1 Function 0 2 Configuration Register Address Map sssssesesreecsrrrssee 85 2 9 PCI Device 1 Function 0 2 Extended Configuration Register Address Map 127 2 10 PCI Device 2 Configuration Register Address Map sssssssssssrrrsssrirreerrrrrrnnerrrerrrens 132 2
2. 0 6 0 PCI 4 5h 0000h Access RW RO Size 16 bits BIOS Optimal Default 00h Reset RST Description Value PWR P safe o pema ooo INTA Assertion Disable INTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt messages Any INTA emulation interrupts already asserted must be de 10 RW Uncore asserted when this bit is set This bit only affects interrupts generated by the device PCI INTA from a PME or Hot Plug event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and deassert messages neers Fast Back to Back Enable FB2B Not Applicable or Implemented Hardwired to 0 SERR Message Enable SERRE Controls the root port SERR messaging The processor communicates the SERR condition by sending an SERR message to the PCH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control register In addition for Type 1 configuration space header devices this bit when set enables transmission by the primary interface of RW Uncore ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface This bit does not affect the transmission of forwarded ERR_COR messages 0 The SERR message is ge
3. MCTP messages can occur These are routed in a peer fashion e VCp Optionally enabled Supports priority snoop traffic only This VC is given higher priority at the snoop VC arbiter Routed as an independent virtual channel and treated independently within the Cache module VCp snoops are indicated as high priority in the snoop priority field USB classic and USB2 traffic are expected to use this channel Note on prior chipsets this was termed snoop isochronous traffic Snoop isochronous is now termed priority snoop traffic SNR bit is ignored MSI on VCP is supported Peer read and write requests are not supported Writes will route to address 000C_0000h with byte enables deasserted while reads will route to address 000C_0000h and an unsupported request completion Internal Graphics GMADR writes are NOT supported These will route to address 000C_0000h with byte enables de asserted Internal Graphics GMADR reads are not supported See DMI2 TC mapping for expected TC to VCp mapping This has changed from DMI to DMI2 e VC1 Optionally enabled Supports non snoop transactions only Used for isochronous traffic Note that the PCI Express Egress port PXPEPBAR must also be programmed appropriately The snoop not required SNR bit must be set Any transaction with the SNR bit not set will be treated as an unsupported request MSI and peer transactions will be treat
4. Datasheet Volume 2 Processor Configuration Registers intel 2 19 6 GT_PERF_STATUS GT Performance Status Register P state encoding for the Secondary Power Plane s current PLL frequency and the current VID B D F Type 0 0 0 MCHBAR PCU Address Offset 5948 594Bh Default Value 0000_0000h Access RO V Size 32 bits BIOS Optimal Default 0000h Reset oe i RP State Ratio RP_STATE_RATIO 1 8 ROSY ooh Ratio of the current RP state 7 0 RO V 00h Uncore RP State VID RP_STATE_VID VID of the current RP state 2 19 7 RP_STATE_CAP RP State Capability Register This register contains the maximum base frequency capability for the Integrated Graphics Engine GT B D F Type 0 0 0 MCHBAR PCU Address Offset 5998 599Bh Default Value 0000_0000h Access RO FW Size 32 bits BIOS Optimal Default 00h Reset font pare mo sere oO RPN Capability RPN_CAP S This field indicates the maximum RPN base frequency capability 23 16 RO FW h 3 o 99 ee for the Integrated GFX Engine GT Values are in units of 100 MHz RP1 Capability RP1_ CAP This field indicates the maximum RP1 base frequency capability for the Integrated GFX Engine GT Values are in units of 100 MHz RPO Capability RPO_ CAP This field indicates the maximum RPO base frequency capability for the Integrated GFX Engine GT Values are in units of 100 MHz Uncore Uncore Datasheet Volume 2 265 Processor Configu
5. Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified through the Root entry Table Address RTA_REG register Hardware reports the status of the Set Root Table Pointer operation through the RTPS field in the Global Status register The Set Root Table Pointer operation must be performed before enabling or re enabling after disabling DMA remapping through the TE field After a Set Root Table Pointer operation software must globally 30 wo Uncore invalidate the context cache and then globally invalidate of IOTLB This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer and not stale cached entries While DMA remapping hardware is active software may update the root table pointer through this field However to ensure valid in flight DMA requests are deterministically remapped software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer Clearing this bit has no effect The value returned on read of this field is undefined 232 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 GFXVTBAR Address Offset 18 1Bh Reset Value 0000_0000h Access RO WO Size 32 bits BIOS Optimal Default 000000h Reset RST Desc
6. core ra ecg devices or Root Ports that do not support peer The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource This field does not affect the root port behavior e o emas ooo TC High VCO Map TCHVCOM 15 8 RW 00h Uncore Allow usage of high order TCs BIOS should keep this field zeroed to allow usage of the reserved TC 3 for other purposes TC VCO Map TCVCOM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this VC 7 1 RW 7Fh Uncore resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource To remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link 1b U core TCO VCO Map TCOVCOM Traffic Class 0 is always routed to VCO Datasheet Volume 2 Processor Configuration Registers oy 2 7 6 VCORSTS VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 1 0 2 MMR Address Offset 11A 11Bh Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P safe w pee o VCO Negotiation Pending VCONP 0
7. 0 6 0 PCI 19h 00h Access RW Size 8 bits Reset RST Tr GORJE Secondary Bus Number BUSN 7 0 RW 00h Uncore This field is programmed by configuration software with the bus number assigned to PCI Express G 2 10 11 SUBUSN6 Subordinate Bus Number Register This register identifies the subordinate bus if any that resides at the level below PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type 0 6 0 PCI Address Offset 1Ah Reset Value 00h Access RW Size 8 bits Reset RST ae jo fae Ses Sie esermton Subordinate Bus Number BUSN This register is programmed by configuration software with the number of the highest subordinate bus that lies behind the 10 RW voh oncore processor root port bridge When only a single PCI device resides on the PCI Express G segment this register will contain the same value as the SBUSN1 register Datasheet Volume 2 153 ntel 2 10 12 2 10 13 154 Processor Configuration Registers IOBASE6 I O Base Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt 10_LIMIT Only the upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined I O address range will be aligned to a 4 KB boundary B D
8. 00 Disabled 01 LOs Entry Supported 10 Reserved 11 LOs and L1 Entry Supported 202 Datasheet Volume 2 Processor Configuration Registers 2 12 21 LSTS DMI Link Status Register This register indicates DMI status B D F Type 0 0 0 DMI BAR Address Offset 8A 8Bh Reset Value 0001h Access RO V Size 16 bits BIOS Optimal Default 00h Reset RST Description Value PWR P SS eee Training TXTRN When set this bit indicates that the Physical Layer TXTSSM is in 11 RO V neore the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the TXTSSM exits the Configuration Recovery state once Link training is complete o f e o eea o Negotiated Width NWI D This field indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed RO V 00h Uncore 00h Reserved Olh X1 02h X2 04h X4 All other encodings are reserved Negotiated Speed NSPD This field indicates negotiated link speed 1h 2 5 Gb s 3 0 RO V 1h Uncore 2h 5 0 Gb s All other encodings are reserved The value in this field is undefined when the Link is not up Datasheet Volume 2 203 t i Processor Configuration Registers 2 12 22 LCTL2 Link Control 2 Register B D F Type 0 0 0 DMI BAR Address Offset 98 99h Reset Value
9. 100 Hardware supports 14 bit domain ids with support for up to 16K domains 110 Hardware supports 16 bit domain ids with support for up to 64K domains 111 Reserved Datasheet Volume 2 273 Uncore Processor Configuration Registers intel 2 21 3 ECAP_REG Extended Capability Register This register reports remapping hardware extended capabilities B D F Type 0 0 0 VCOPREMAP Address Offset 10 17h Reset Value 0000_0000_O0FO_10DAh Access RO V RO Size 64 bits BIOS Optimal Default 000_0000_0000h Reset RST Value PWR a pena o Maximum Handle Mask Value MHMV The value in this field indicates the maximum supported value for the Handle Mask HM field in the interrupt entry cache invalidation descriptor iec_inv_dsc This field is valid only when the IR field in Extended Capability register is reported as set Description IOTLB Register Offset IRO This field specifies the offset to the IOTLB registers relative to the register base address of this remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first IOTLB invalidation register is calculated as X 16 Y Uncore Snoop Control SC 0 Hardware does not support 1 setting of the SNP field in the page table entries 1 Hardware supports the 1 setting of the SNP field in the page table entries Pass Through PT 0 Hardware does not support pass through tr
10. 128 MB buses 0 127 Bits 38 27 are decoded in the PCI Express Base Address field 10 64 MB buses 0 63 Bits 38 26 are decoded in the PCI Express Base Address field 11 Reserved This register is locked by Intel TXT PCIEXBAR Enable PCI EXBAREN 0 The PCIEXBAR register is disabled Memory read and write transactions proceed as if there were no PCIEXBAR register PCIEXBAR bits 38 26 are RW with no functionality behind them RW Uncore The PCIEXBAR register is enabled Memory read and write transactions whose address bits 38 26 match PCIEXBAR will be translated to configuration reads and writes within the Uncore These translated cycles are routed as shown in the above table This register is locked by Intel TXT Datasheet Volume 2 61 62 Processor Configuration Registers DMI BAR Root Complex Register Range Base Address Register This is the base address for the Root Complex configuration space This window of addresses contains the Root Complex Register set for the PCI Express Hierarchy associated with the Host Bridge There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the Root Complex configuration space is disabled and must be enabled by writing a 1 to DMI BAREN Device 0 offset 68h bit 0 All the bits in this register are locked in Intel TXT mode B D F Type 0 0 0 PCI Ad
11. 14 12 core PEG10 VCO Minimum Completion Credits PEG1OVCO Minimum number of credits for PEG1O VCO completions 17 15 RW L Uncore DMI VC1 Minimum Completion Credits DMI VC1 RW L U sas Minimum number of credits for DMI VC1 completions DMI VCm Minimum Completion Credits DMI VCM RW L U seas Minimum number of credits for DMI VCm completions DMI VCp Minimum Completion Credits DMI VCP U ge Minimum number of credits for DMI VCp completions DMI VCO Minimum Completion Credits DMI VCO U cia Minimum number of credits for DMI VCO completions Datasheet Volume 2 217 Table 2 18 2 16 1 218 Processor Configuration Registers MCHBAR Registers in Memory Controller Common Table 2 18 lists the registers arranged by address offset Register bit descriptions are in the sections following the table MCHBAR Registers in Memory Controller Common Register Address Map Address Register Ranickar Nanie Reset Offset Symbol g Value 5000 5003h MAD_CHNL Address decoder Channel Configuration 0000_0024h 5004 5007h MAD_DIMM_chO Address Decode Channel 0 0060_0000h osos o feed ooo o ees o eea o MAD_CHNL Address Decoder Channel Configuration Register This register defines which channel is assigned to be channel A channel B and channel C according to the rule size A gt size B gt size C Since the processor implements only two channels channel C is always channel 2 and its size is al
12. Address Register Capability Register 00C9_0080 7 Extended Capability Register 0000_0000 3 10 17h ECAP_REG 00FO 10DAR RO V RO 18 1Bh GCMD_REG Global Command Register 0000_0000h WO RO 1C 1Fh GSTS_REG Global Status Register 0000_0000h RO RO V Root Entry Table Address Register 0000 0000 Context Command Register 0000_0000 RW V RW Fault Status Register Oh 38 3Bh FECTL_REG Fault Event Control Register 8000_0000h RW RO V 3C 3Fh FEDATA_REG Fault Event Data Register 0000_0000h RW 40 43h FEADDR_REG Fault Event Address Register 0000_0000h RW 44 47h FEUADDR_REG Fault Event Upper Address Register 0000_0000h RW Oh p Advanced Fault Log Register 0000_0000 64 67h PMEN_REG Protected Memory Enable Register 0000_0000h RW RO V 68 6Bh PLMBASE_REG Protected Low Memory Base Register 0000_0000h 6C 6Fh PLMLIMIT_REG Protected Low Memory Limit Register 0000_0000h imi i RW Protected High Memory Base Register 0000 0000 _ Protected High Memory Limit Register 0000_0000 Invalidation Queue Head Register 0000_0000 Invalidation Queue Tail Register 0000 0000 88 8Fh IQT_REG 00007 0000h 90 97h Invalidation Queue Address Register R A4 A7h Invalidation Event Data Register RW L nD ie wn RW RW RO RW W V L L Datasheet Volume 2 269 Processor Configuration Registers intel Table 2 23 Default PEG DMI VT d Remapping Engine Register Address Map Sheet 2 of 2 Address Register r aiki seat
13. DI MM A DDR Width DAW DIMM A width of DDR chips X8 chips X16 chips DI MM B number of Ranks DBNOR Single rank Dual rank DIMM A number of Ranks DANOR Uncore Single rank Dual rank DI MM A select DAS Selects which of the DIMMs is DIMM A should be the larger Uncore DIMM 0 DIMM O 1 DIMM1 a Size of DIMM B DIMM_B_ Size Size of DIMM B in 256 MB multiples Size of DIMM A DIMM_A Size Size of DIMM A in 256 MB multiples 23 22 21 20 19 18 17 16 15 8 7 0 Datasheet Volume 2 219 intel 2 16 3 220 Processor Configuration Registers MAD_DIMM_ch1 Address Decode Channel 1 Register This register defines channel characteristics number of DIMMs number of ranks size ECC interleave options and ECC options B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5008 500Bh Reset Value 0060_0000h Access RW L Size 32 bits BIOS Optimal Default 00h Reset RST Description Value PWR ECC is active in the channel ECC 25 24 00 No ECC active in the channel 01 ECC is active in I O ECC logic is not active In this case on write accesses the data driven on ECC byte is copied from DQ 7 0 to be used in training or lOSAV 10 ECC is disabled in I O but ECC logic is enabled to be used in ECC4ANA mode 11 ECC active in both I O and ECC logic freee Enhanced Interleave mode Enh_Interleave 0 Off Uncore Rank Interleave RI Off On DIMM B DDR width
14. Global Status Register This register reports general remapping hardware status B D F Type 0 0 0 GFXVTBAR Address Offset 1C 1Fh Reset Value 0000_0000h Access RO RO V Size 32 bits BIOS Optimal Default 000000h Translation Enable Status TES This field indicates the status of DMA remapping hardware 0 DMA remapping hardware is Not enabled 1 DMA remapping hardware is enabled Root Table Pointer Status RTPS This field indicates the status of the root table pointer in hardware This field is cleared by hardware when software sets the SRTP field in the Global Command register This field is set by hardware when hardware completes the Set Root Table Pointer operation using the value provided in the Root Entry Table Address register Fault Log Status FLS 0 Cleared by hardware when software Sets the SFL field in the Global Command register 1 Set by hardware when hardware completes the Set Fault Log Pointer operation using the value provided in the Advanced Fault Log register Advanced Fault Logging Status AFLS This field is valid only for implementations supporting advanced fault logging It indicates the advanced fault logging status 0 Advanced Fault Logging is Not enabled 1 Advanced Fault Logging is enabled Write Buffer Flush Status WBFS This field is valid only for implementations requiring write buffer flushing This field indicates the status of the write buffer flush comma
15. Powers Reserved for Future Use RWSVD2 MDLL Shutdown Latency Time WM2 Number of microseconds to access memory if the MDLL is shutdown requires memory in Self Refresh The value is programmed in 0 5 us granularity 00h O us Olh 0 5 us 21 16 RWS 000000b Powerg 02h 1 us 3Fh 31 5 us NOTE The value in this field corresponds to the memory latency requested to the Display Engine when MDLL shutdown is enabled The Display LP2 latency and watermark values GTTMMADR offset 4511Ch should be programmed to match the latency in this register 15 14 Rs oo PoS Reserved for Future Use RWSVD1 266 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 MCHBAR PCU Address Offset 5D10 5D17h Reset Value 0000_0000_0000_0000h Access RWS Size 64 bits Reset RST Description Value PWR p Self Refresh Latency Time WM1 Number of microseconds to access memory if memory is in Self Refresh 0 5 us granularity 00h 0 us Olh 0 5 us 02h 1 us 13 8 Rws o00000b Powerg ood ae 3Fh 31 5 us NOTE The value in this field corresponds to the memory latency requested to the Display Engine when Memory is in Self Refresh The Display LP1 latency and watermark values GTTMMADR offset 45118h should be programmed to match the latency in this register ore ews ooo Pag aie jiii Normal Latency Time WMO Number of microseconds to access memory for normal memory operat
16. Revision dentification Register This register contains the revision number of Device 0 These bits are read only and writes to this register have no effect This register contains the revision number of the processor The Revision ID RID is a traditional 8 bit Read Only RO register located at offset 08h in the standard PCI header of every PCI PCI Express compatible device and function Following reset the SRID is returned when the RID is read at offset 08h The SRID value reflects the actual product stepping To select the CRID value BIOS configuration software writes a key value of 69h to Bus 0 Device 0 Function 0 DMI device of the processor RID register at offset 08h This causes the CRID to be returned when the RID is read at offset 08h Stepping Revision ID SRID This register contains the revision number of the processor The SRID is a 8 bit hardwired value assigned by Intel based on product stepping The SRID is not a directly addressable PCI register The SRID value is reflected through the RID register when appropriately addressed Compatible Revision ID CRID The CRID is an 8 bit hardwired value assigned by Intel during manufacturing process Normally the value assigned as the CRID will be identical to the SRID value of a previous stepping of the product with which the new product is deemed compatible The CRID is not a directly addressable PCI register The CRID value is reflected through the RID register when
17. Site esermton Physical Slot Number PSN This field indicates the physical slot number attached to this Port 31 19 RW O 0000h Uncore BIOS Requirement This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis No Command Completed Support NCCS When set to 1 this bit indicates that this slot does not generate 18 1b Uncore software notification when an issued command is completed by the Hot Plug Controller This bit is only permitted to be set to 1b if the hotplug capable port is able to accept writes to all fields of the Slot Control register without delay between successive writes Reserved for Electromechanical I nterlock Present EIP 17 Uncore When set to 1 this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot 118 Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size intel 0 1 0 2 PCI B4 B7h 0004_0000h RW O RO 32 bits Reset RST Description Value PWR p Datasheet Volume 2 Slot Power Limit Scale SPLS This field specifies the scale used for the Slot Power Limit Value 00 1 0x 01 0 1x 10 0 01x 11 0 001x If this field is written the link sends a Set_Slot_Power_Limit message Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value specifies the upper limit on power su
18. ace Sats Btn eon O O Device I dentification Number MSB DID_MSB 15 4 RO FW 010h Uncore This is the upper part of a 16 bit value assigned to the Graphics device Device I dentification Number SKU DID_ SKU 3 2 RO V Uncore These are bits 3 2 of the 16 bit value assigned to processor graphics device Device Identification Number LSB DI D_LSB 1 0 RO V 10b Uncore This is the lower part of a 16 bit value assigned to the processor graphics device Datasheet Volume 2 133 t i Processor Configuration Registers 2 8 3 PCI CMD2 PCI Command Register This 16 bit register provides basic control over the IGD s ability to respond to PCI cycles The PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory B D F Type 0 2 0 PCI Address Offset 4 5h Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 00h Reset RST jee ew fie pik ee pm we a irene o Interrupt Disable INTDIS FLR This bit disables the device from asserting INTx 10 RW Uncore 0 Enable the assertion of this device s INTx signal 1 Disable the assertion of this device s INTx signal DO_INTx messages will not be sent to DMI Unesre Fast Back to Back FB2B Not Implemented Hardwired to 0 Urcare SERR Enable SERRE Not Implemented Hardwired to 0 Address Data Stepping Enable ADSTEP 7 Uncore Not Implemented Hardwired to 0 Parity Error Enable PERRE Not Impl
19. 0 0 GFXVTBAR Address Offset 10 17h Reset Value 0000_0000_O0FO_101Ah Access RO RO V Size 64 bits BIOS Optimal Default 00000000000h Reset RST Description Value PWR p saj o w pe o Maximum Handle Mask Value MHMV The value in this field indicates the maximum supported value for 23 20 1111b ricore ae ay Nae in the interrupt entry cache invalidation This field is valid only when the IR field in Extended Capability register is reported as set pase me mame o 1OTLB Register Offset I RO This field specifies the offset to the OTLB registers relative to the register base address of this remapping hardware unit If the register base address is X and the value reported in this field is Y the address for the first OTLB invalidation register is calculated as X 16 Y Uncore Snoop Control SC 0 Hardware does not support 1 setting of the SNP field in the Uncore page table entries 1 Hardware supports the 1 setting of the SNP field in the page table entries Pass Through PT 0 Hardware does Not support pass through translation type in Uncore context entries 1 Hardware supports pass through translation type in context entries Caching Hints CH 0 Hardware does Not support OTLB caching hints ALH and EH Uncore fields in context entries are treated as reserved 1 Hardware supports OTXTB caching hints through the ALH and EH fields in context entries Extended Interrupt Mode EI M 0 O
20. 0002h Access RWS RWS V Size ae bits BIOS Optimal Default Reset RST Description Value PWR p pas Ro ef penae oo oS Compliance De emphasis ComplianceDeemphasis This bit sets the de emphasis level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1b 1 3 5 dB 0 6 dB When the Link is operating at 2 5 GT s the setting of this bit has Powerg nO effect Components that support only 2 5 GT s speed are 12 RWS ood permitted to hardwire this bit to Ob For a Multi Function device associated with an Upstream Port the bit in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is RsvdP This bit is intended for debug compliance testing purposes System firmware and software is allowed to modify this bit only during debug or compliance testing Compliance SOS compsos When set to 1 the TXTSSM is required to send SKP Ordered Sets periodically in between the modified compliance patterns For a 11 RWS Powerg Multi Function device associated with an Upstream Port the bit in ood Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is RsvdP Components that support only the 2 5 GT s speed are permitted to hardwire this field to Ob Enter Modified Compliance entermodcompliance Powerg When this bit is set to 1 the device tra
21. F Type Address Offset Reset Value 0 6 0 PCI 1Ch FOh Access RW Size 8 bits BIOS Optimal Default Oh neser nel Description Value PWR I O Address Base I OBASE 7 4 RW Fh Uncore This field corresponds to A 15 12 of the I O addresses passed by the root port to PCI Express G ope o peen LOLI MI T6 I O Limit Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt 10_LIMIT Only the upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type Address Offset Reset Value 0 6 0 PCI 1Dh 00h Access RW Size A s BIOS Optimal Default Reset RST Description Value PWR p 1 O Address Limit I OLI MIT This field corresponds to A 15 12 of the I O address limit of the a RW 9h pears root port Devices between this upper limit and OBASE1 will be passed to the PCI Express hierarchy associated with this device ofe o eea Datasheet Volume 2 Processor Configuration Registers intel 2 10 14 SSTS6 Secondary Status Register SSTS is a 16 bit status register that reports the occurrence of error conditions associated with secondary side that is PCI Express G side of the virtual PCI PCI bridge embedded within the processor B D F T
22. Hardware implementations not supporting device Device IOTLBs implement this bit as RsvdZ Invalidation Completion Error ICE Hardware received an unexpected or invalid Device OTLB invalidation completion This could be due to either an invalid ITag or invalid source id in an invalidation completion response At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device OTLBs implement this bit as RsvdZ Invalidation Queue Error I QE Hardware detected an error associated with the invalidation queue This could be due to either a hardware error while fetching a descriptor from the invalidation queue or hardware detecting an erroneous or invalid descriptor in the invalidation queue At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting queued invalidations implement this bit as RsvdZ Advanced Pending Fault APF When this bit is 0 hardware sets this bit when the first fault record at index 0 is written to a fault log At this time a fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ Advanced Fault Overflow AFO Hardware sets this bit to indicate advanced fault log ove
23. Max Payload Size MPS 000 128B maximum payload for Transaction Layer Packets TLP RW 000b Uncore All other encodings are reserved As a receiver the device must handle TLPs as larger as the value set in this field As a transmitter the device must not generate TLPs exceeding the value set in this field Ro o Uncore Reserved for Enable Relaxed Ordering ROE Unsupported Request Reporting Enable URRE When set this bit allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an RW Uncore Unmasked Unsupported Request UR An ERR_CORR is signaled when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register Fatal Error Reporting Enable FERE When set this bit enables signaling of ERR_FATAL to the Root RW Uncore Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Non Fatal Error Reporting Enable NERE When set this bit enables signaling of ERR_NONFATAL to the Rool RW Uncore Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Correctable Error Reporting Enable CERE When set this bit ena
24. PME Status PMESTS This bit indicates that this device does not support PME generation from D3cold Data Scale DSCALE This field indicates that this device does not support the power management data register Data Select DSEL This field indicates that this device does not support the power management data register PME Enable PMEE This bit indicates that this device does not generate PME assertion from any D state 0 Disable PME generation not possible from any D State 1 Enable PME generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 PO No Soft Reset NSR 1 Device is transitioning from D3hot to DO because the power state commands do not perform an internal reset Configuration context is preserved Upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits Uncore 0 Devices do not perform an internal reset upon transitioning from D3hot to DO using software control of the power state bits Regardless of this bit the devices that transition from a D3hot to DO by a system or bus segment reset will return to the device state DO uninitialized with only PME context preserved if PME is supported and enabled a a 166 Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Defau
25. Processor Configuration Registers DSTS Device Status Register Reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link B D F Type 0 1 0 2 PCI Address Offset AA ABh Reset Value 0000h Access RWI1C RO Size 16 bits BIOS Optimal Default 000h Reset RST PWR Description Transactions Pending TP 0 All pending transactions including completions for any outstanding non posted requests on any used virtual channel have been completed 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes Not Applicable or Implemented Hardwired to 0 Unsupported Request Detected URD This bit indicates that the Function received an Unsupported Request Errors are logged in this register regardless of whether Uncore error reporting is enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Not Applicable or Implemented Hardwired to 0 Fatal Error Detected FED This bit indicates status of Fatal errors detected Errors are logged in this register regardless of whether error reporting is enabled or Uncore not in the Device Control register For a multi Function device each Function
26. Reset Value 0000_ 0000h Access RW Size 32 bits BIOS Optimal Default 00000h Protected Low Memory Limit PLML 000h Uncore This register specifies the last host physical address of the DMA protected low memory region in system memory oo o e eena o Reset RST Description Value PWR p 290 Datasheet Volume 2 Processor Configuration Registers n t 2 21 17 PHMBASE_ REG Protected High Memory Base Register This register sets up the base address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software may setup the protected high memory region either above or below 4 GB Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 70 77h Reset Value 0000_0000_0000_000
27. Type 0 6 0 PCI Address Offset 3Ch Reset Value 00h Access RW Size 8 bits Reset RST er jose ace tates te tesermton O Interrupt Connection INTCON This field is used to communicate interrupt line routing information 7 0 RW 00h Uncore BIOS Requirement POST software writes the routing information into this register as it initializes and configures the system The value indicates to which input of the system interrupt controller this device s interrupt pin is connected 2 10 23 INTRPIN6 I nterrupt Pin Register 162 This register specifies which interrupt pin this device uses B D F Type Address Offset Reset Value 0 6 0 PCI 3Dh Olh Access RW O RO Size 8 bits Reset RST o e ee Interrupt Pin I NTPI N As a multifunction device the PCI Express device may specify any INTx x A B C D as its interrupt pin The Interrupt Pin register indicates which interrupt pin the device or device function uses 1h Corresponds to INTA Default 2h Corresponds to INTB oe RWO th pears 3h Corresponds to INTC 4h Corresponds to INTD Devices or device functions that do not use an interrupt pin must put a 0 in this register The values 05h through FFh are reserved This register is write once BIOS must set this register to select the INTx to be used by this root port Datasheet Volume 2 Processor Configuration Registers intel 2 10 24 BCTRL6 Bridge Control Register This regi
28. the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 83h Reset Value 00h Access RW Size a are BIOS Optimal Default Reset RST Description Value PWR p mje o pe o 0D4000 0D7FFF Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D4000h to OD7FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT afe o pee o 0D0000 OD3FFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D0000h to OD3FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are 1 0 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers intel 2 5 20 PAM
29. 0 Accesses to I O address range x3BCh x3BFh are treated just like any other I O accesses That is the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and ISA enable bit is not set otherwise they are forwarded to the DMI Interface VGA compatible memory and I O range accesses are not forwarded to PCI Express but rather they are mapped to DMI Interface unless they are mapped to PCI Express using I O and memory range registers defined above IOBASE OLIMIT Table 2 6 shows the behavior for all combinations of MDA and VGA VGA and MDA I O Transaction Mapping ven ee poar tose oetten e o ree won oer OO a a MDA DMI Interface Note x3BCh x3BEh will also go to DMI Interface The same registers control mapping of VGA I O address ranges VGA I O range is defined as addresses where A 9 0 are in the ranges 3BOh to 3BBh and 3COh to 3DFh inclusive of ISA address aliases A 15 10 are not decoded The function and interaction of these two bits is described below MDA Present MDAP This bit works with the VGA Enable bit in the BCTRL register of device 1 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set when the VGA Datasheet Volume 2 43 Processor Configuration Registers Enable bit is not set If the VGA enable bit is set then accesses to I O address range x3BCh x3BFh are forwarded to DMI Interface I
30. 085 252 2 18 26 IRTA_REG Interrupt Remapping Table Address Register eeeeee 253 2 18 27 IVA_REG Invalidate Address Register sssssrsrrrrerrerrrrnrrrrrrrrrrrererre 254 2 18 28 IOTLB_REG IOTLB Invalidate Register eee 255 2 18 29 FRCDL_REG Fault Recording Low Register cceceeeee teens teeta tee teeta ees 257 2 18 30 FRCDH_REG Fault Recording High RegiSter cceceeeeeee eee ee teeta teeta ees 258 2 18 31 VTPOLICY DMA Remap Engine Policy Control Register cseeeee eee 259 PCU MCHBAR R QIStGMSiiniciicciseticatiaiceraiiee rie aieaieeniie tenes p a Eene aE ekin 260 2 19 1 MEM_TRML_ESTIMATION_CONFIG Memory Thermal Estimation Configuration Register c cect nett erent entre eee e eres 261 2 19 2 MEM_TRML_THRESHOLDS_CONFIG Memory Thermal Thresholds Configuration REGIStEr cece eect ee en ee eer 262 2 19 3 MEM_TRML_STATUS_ REPORT Memory Thermal Status Report Register 263 2 19 4 MEM_TRML_TEMPERATURE_REPORT Memory Thermal Temperature Report Register ccc cece eee eee eee rene nee eee teen ne eee teen E 264 2 19 5 MEM_TRML_INTERRUPT Memory Thermal Interrupt Register 264 2 19 6 GT_ PERF_ STATUS GT Performance Status Register ccce 265 2 19 7 RP_ STATE_ CAP RP State Capability Register ccc ceeeeee eee eee 265 2 19 8 SSKPD Sticky Scratchpad Data ReGiSter cece cece cette ete ee eee e teen eae 266 PXPEPBAR
31. 0B4h Uncore Time of refresh from beginning of refresh until next ACT or refresh is allowed in DCLK cycles default is 180 tREFI period in DCLK cycles tREFI 1004h Uncore Defines the average period between refreshes and the rate that tREFI counter is incremented in DCLK cycles default is 4100 Datasheet Volume 2 211 Processor Configuration Registers intel 2 14 MCHBAR Registers in Memory Controller Channel 1 Table 2 16 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 16 MCHBAR Registers in Memory Controller Channel 1 Register Address Map i ee e ee E Reseed a Timing of DDR Regular Access Parameters oam sw fena CSS C Reeves Refresh Parameters 4698 469Bh TC_RFTP_C1 Refresh Timing Parameters 46B4_1004h RW L 2 14 1 TC_DBP_C1 Timing of DDR Bin Parameters Register This register defines the BIN timing parameters for safe logic tRCD tRP and tCL B D F Type 0 0 0 MCHBAR MC1 Address Offset 4400 4403h Reset Value 0000_0666h Access RW L 32 bits Reset RST Description Value PWR p Oh Co p pena o PRE to ACT Same Bank Delay tRP Range is 4 15 DCLK cycles ACT to CAS RD or WR Same Bank Delay tRCD Range is 4 15 CAS Command Delay to Data Out of DDR Pins tCL This field provides the delay from CAS command to data out of DDR pins Range is 5 15 This does not define the sample point in the I
32. 2 10 29 MSI_CAPID Message Signaled Interrupts Capability I D Register When a device supports MSI it can generate an interrupt request to the processor by writing a predefined data item a message to a predefined memory address The reporting of the existence of this capability can be disabled by setting MSICH CAPL O 7Fh In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability B D F Type Address Offset Reset Value Access Size 0 6 0 PCI 90 91h A005h RO 16 bits Reset RST Description Value PWR p Pointer to Next Capability PNC 15 8 AOh Uncore This field contains a pointer to the next item in the capabilities list that is the PCI Express capability Capability ID CID 7 0 O5h Uncore The value of 05h identifies this linked list item capability structure as being for MSI registers 168 Datasheet Volume 2 Processor Configuration Registers intel 2 10 30 MC Message Control Register System software can modify bits in this register but the device is prohibited from doing so If the device writes the same message multiple times only one of those messages is assured to be serviced If all of th the same message again until the em must be serviced the device must not generate driver services the earlier one B D F Type 0 6 0 PCI Address Offset 92 93h Reset Value 0000h Acces
33. 2 12 5 DMIVCORCAP DMI VCO Resource Capability Register cece eee 191 2 12 6 DMIVCORCTL DMI VCO Resource Control ReGiSter cceeeeee sete e cnet ees 192 2 12 7 DMIVCORSTS DMI VCO Resource Status Register usce 193 2 12 8 DMIVC1RCAP DMI VC1 Resource Capability Register eee 193 Datasheet Volume 2 2 12 9 DMIVC1RCTL DMI VC1 Resource Control Register eceeeeee eee ee eee 194 2 12 10 DMIVC1RSTS DMI VC1 Resource Status Register ceceeeee cece eee eee 195 2 12 11 DMIVCPRCAP DMI VCp Resource Capability Register ceceeeeee eee 195 2 12 12 DMIVCPRCTL DMI VCp Resource Control Register cceeeeee eee ene eaten 196 2 12 13 DMIVCPRSTS DMI VCp Resource Status Register cceeeeeee eee ee eee eee 197 2 12 14 DMIESD DMI Element Self Description Register ceceeece eee ee ee eee eee 198 2 12 15 DMILE1D DMI Link Entry 1 Description Register c cece eeee ee ee eee 199 2 12 16 DMILE1A DMI Link Entry 1 Address RegiSter cccecseene ene ee teeta tent ees 199 2 12 17 DMILE2D DMI Link Entry 2 Description Register cceeeeeee eee ee eee ees 200 2 12 18 DMILE2A DMI Link Entry 2 Address ReGiSter ccceceeene ene ee eee en seat ees 200 2 12 19 LCAP Link Capabilities RegiSter ccc ccec ence eee teen e ee eee teen e nett ees 201 2 12 20 LCTL Link Control Register ccecee cece eee eee eee ee teeta
34. 2 18 9 FECTL_REG Fault Event Control Register This register specifies the fault event interrupt message control bits B D F Type 0 0 0 GEXVTBAR Address Offset 38 3Bh Reset Value 8000_0000h Access RW RO V Size 32 bits BIOS Optimal Default 00000000h Reset RST Description Value PWR P ofe o ee Datasheet Volume 2 Interrupt Mask IM 0 No masking of interrupt When an interrupt condition is detected hardware issues an interrupt message using the Fault Event Data and Fault Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this bit Hardware is prohibited from sending the interrupt message when this bit is set Interrupt Pending IP Hardware sets the IP bit when it detects an interrupt condition which is defined as e When primary fault logging is active an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF bit in Fault Status register When advanced fault logging is active an interrupt condition occurs when hardware records a fault in the first fault record at index 0 of the current fault log and sets the APF bit in the Fault Status register Hardware detected error associated with the Invalidation Queue setting the IQE bit in the Fault Status register Hardware detected invalid Device OTLB invalidation completion setting the ICE bit in the Fault Status
35. 3 10 System Management Mode SMM Unlike FSB platforms the Core handles all SMM mode transaction routing Also the platform no longer supports HSEG The processor will never allow I O devices access to CSEG TSEG HSEG ranges DMI Interface and PCI Express masters are not allowed to access the SMM space SMM regions SMM Space Enabled Transaction Address Space DRAM Space DRAM Compatible C 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh TSEG T TOLUD STOLEN TSEG to TOLUD TOLUD STOLEN TSEG to TOLUD STOLEN STOLEN SMM and VGA Access through GTT TLB Accesses through the Graphics Translation Table GTT Translation Lookaside Buffer TLB address translation SMM DRAM space are not allowed Writes will be routed to Memory address 000C_0000h with byte enables de asserted and reads will be routed to Memory address 000C_0000h If a GTT TLB translated address hits SMM DRAM space an error is recorded in the PGTBL_ER register PCI Express and DMI Interface originated accesses are never allowed to access SMM space directly or through the GTT TLB address translation If a GTT TLB translated address hits enabled SMM DRAM space an error is recorded in the PGTBL_ER register PCI Express and DMI Interface write accesses through GMADR range will not be snooped Only PCI Express and DMI assesses to GMADR linear range defined using fence registers are supported PCI Express and DMI Interface tileY and tileX writes to GMADR are not sup
36. 4 RO V 0000h Uncore queue for the command that will be fetched next by hardware Hardware resets this field to 0 whenever the queued invalidation is disabled QIES field Clear in the Global Status register oe o E eena o 2 21 20 EG Invalidation Queue Tail Register Register indicating the invalidation tail head This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 88 8Fh Reset Value 0000_0000_0000_0000h Access RW L Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RST Description Value PWR p snf e o j ena ooo Queue Tail QT 18 4 RW L 0000h Uncore This field specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software see nese o Datasheet Volume 2 293 t i Processor Configuration Registers 2 21 21 1IQA_REG Invalidation Queue Address Register This register configures the base address and size of the invalidation queue This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 90 97h Reset Value 0000_0000_0000_0000h Access RW L Size 64 bits BIOS Optimal Default 0_0000_0000h Reset RST jee ew fic pk ee ere no om pema ooo Invalidation Queue
37. 6 0 PCI 94 97h 0000_0000h RW RO 32 bits Reset RST Description Value PWR p Message Address MA 0000_000 This field is used by system software to assign an MSI address to 1 2 RW oh MENT the device The device handles an MSI by writing the padded contents of the MD register to this address Force DWord Align FDWA 1 0 Uncore Hardwired to 00 so that addresses assigned by system software are always aligned on a dword address boundary 2 10 32 MD Message Data Register B D F Type Address Offset Reset Value Access Size 0 6 0 PCI 98 99h 0000h RW 16 bits Reset RST Description Value PWR p Message Data MD Base message data pattern assigned by system software and used to handle an MSI from the device 15 0 RW 0000h Uncore When the device must generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register 2 10 33 PEG_CAPL PCI Express G Capability List Register This register enumerates the PCI Express capability structure B D F Type Address Offset Reset Value Access Size 0 6 0 PCI A0 A1h 0010h RO 16 bits Reset RST Description Value PWR p Pointer to Next Capability PNC This value terminates the capabilities list The Virtual Channel 15 8 00h Uncore capability and any other PCI Express specific capabilities that are r
38. Address PMBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 64 bit Address Support AS64 This field indicates that the upper 32 bits of the prefetchable 3 0 1h Uncore memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h Datasheet Volume 2 99 m t 1 Processor Configuration Registers Note 100 PMLI MI T1 Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is
39. Base Address IQA This field points to the base of 4 KB aligned invalidation request 38 12 RW L 0000000h Uncore queue Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Reads of this field return the value that was last programmed to it FE o oa eena o Queue Size QS This field specifies the size of the invalidation request queue A 2 0 RW L Oh Uncore value of X in this field indicates an invalidation request queue of 2 X 4 KB pages The number of entries in the invalidation queue is 2 X 8 2 21 22 1I1CS_REG Invalidation Completion Status Register Register to report completion status of invalidation wait descriptor with Interrupt Flag IF Set This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 9C 9Fh Reset Value 0000_ 0000h Access RWICS Size 32 bits BIOS Optimal Default 0000_ 0000h Reset RST eA me fa f Bite eon O O me w e Invalidation Wait Descriptor Complete IWC This bit indicates completion of Invalidation Wait Descriptor with Interrupt Flag IF field Set Hardware implementations not supporting queued invalidations implement this field as RsvdZ 294 Datasheet Volume 2 Processor Configuration Registers intel 2 21 23 IECTL_REG Invalidation Event Control Register This register specifies the
40. Bus Number Register This register identifies the subordinate bus if any that resides at the level below PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type Address Offset Reset Value 0 1 0 2 PCI 1Ah 00h Access RW Size 8 bits Reset RST or js awe ss Site esermton Subordinate Bus Number BUSN This register is programmed by configuration software with the number of the highest subordinate bus that lies behind the ae RW ogh Uncore processor root port bridge When only a single PCI device resides on the PCI Express G segment this register will contain the same value as the SBUSN1 register 94 Datasheet Volume 2 Processor Configuration Registers 2 6 12 2 6 13 ntel IOBASE1 I O Base Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt IO_LIMIT Only the upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are treated as 0 Thus the bottom of the defined I O address range will be aligned to a 4 KB boundary B D F Type 0 1 0 2 PCI Address Offset 1Ch Reset Value FOh Access RW Size 8 bits BIOS Optimal Default Oh neser RST Description Value PWR 1 O Address Base I OBASE 7 4 RW Fh Uncore This field corresponds to A 15 12 of the I O address
41. Capabilities Register when set to 1b this bit enables software notification when a hot plug command is completed by the Hot Plug Controller If Command Completed notification is not supported this bit must be hardwired to Ob Presence Detect Changed Enable PDCE When set to 1b this bit enables software notification on a presence detect changed event Reserved for MRL Sensor Changed Enable MSCE When set to 1b this bit enables software notification on a MRL sensor changed event If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Reserved for Power Fault Detected Enable PFDE When set to 1b this bit enables software notification on a power fault event If Power Fault detection is not supported this bit is permitted to be read only with a value of Ob Reserved for Attention Button Pressed Enable ABPE When set to 1b this bit enables software notification on an attention button pressed event 180 Datasheet Volume 2 Processor Configuration Registers 2 10 42 SLOTSTS Slot Status Register This is for PCI Express Slot related registers Note Hot Plug is not supported on Intel Xeon processor E3 1200 family platforms B D F Type 0 6 0 PCI Address Offset BA BBh Reset Value 0000h Access RO RO V RW1C Size 16 bits BIOS Optimal Default 00h Reset RST a js fae Ses Sie esermon ee ee a R
42. Graphics Stolen Memory Size set to 2 MB e BIOS knows the OS requires 1G of PCI space e BIOS also knows the range from 0_FECO_0000h to O_FFFF_FFFFh is not usable by the system This 20 MB range at the very top of addressable memory space is lost to APIC and Intel TXT e According to the above equation TOLUD is originally calculated to 4 GB 1_0000_0000h e The system memory requirements are 4 GB max addressable space 1 GB pci space 0_C000_0000h Since 0_C000_0000h PCI and other system requirements is less than 1_0000_0000h TOLUD should be programmed to COOh These bits are Intel TXT lockable Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 PCI Address Offset BC BFh Reset Value 0010_0000h Access RW KL RW L Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR F Top of Low Usable DRAM TOLUD This register contains bits 31 20 of an address one byte above the maximum DRAM memory below 4 GB that is usable by the operating system Address bits 31 20 programmed to 01h implies a minimum memory size of 1 MB Configuration software must set this value to the smaller of the following 2 choices maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory Address bits 19 0 are assumed to be 0_0000h for the purposes of address 31 20 RW L OO1h Uncore comparison The Host interface positively deco
43. O This is defined by training in round trip register and other registers because this is also affected by board delays 212 Datasheet Volume 2 Processor Configuration Registers 2 14 2 2 14 3 intel TC_RAP_C1 Timing of DDR Regular Access Parameters Register This register provides the regular timing parameters in DCLK cycles B D F Type 0 0 0 MCHBAR MC1 Address Offset 4404 4407h Reset Value 0010_4044h Access RW L Size 32 bits Reset RST Description Value PWR p EEA Four Activate Window 23 16 RW L 10h This field provides the timeframe in which maximum of 4 ACT commands to the same rank are allowed The miniumum value is 4 tRRD the maximum value is 63 DCLK cycles Delay Internal WR to RD Transaction 15 12 RW L 4h This field provides the delay from internal WR transaction to internal RD transaction The minimum delay is 4 DCLK cycles whereas the maximum delay is 8 DCLK cycles mef f o eena o Minimum Delay From CAS RD to PRE 7 4 RW L 4h The minimum delay is 4 DCLK cycles the maximum delay is 8 DCLK cycles Delay Between Two Act Commands tRRD 3 0 RW L 4h tRRD is the minimum delay between two ACT commands targeted f to different banks in the same rank The minimum delay is 4 DCLK cycles the maximum delay is 7 cycles SC_IO_LATENCY_ C1 10 O Latency Configuration Register This register identifies the I O latency per rank and I O compensation global B D F Type 0 0 0 MCH
44. Palette Snoop Enable VGASNOOP The processor does not implement this bit and it is hardwired to a 0 Writes to this bit position have no effect Memory Write and Invalidate Enable MWIE The processor will never issue memory write and invalidate commands This bit is therefore hardwired to 0 Writes to this bit position will have no effect Datasheet Volume 2 49 2 5 4 50 B D F Type Address Offset Reset Value Access Size BIOS Optimal Default Processor Configuration Registers 0 0 0 PCI 4 5h 0006h RO RW 16 bits 00h Reset RST ae jw awe ss Site esermton Bus Master Enable BME 2 1b Uncore The processor is always enabled as a master on the backbone This bit is hardwired to a 1 Writes to this bit position have no effect Memory Access Enable MAE The processor always allows access to main memory except when 1 1b Uncore such access would violate security principles Such exceptions are outside the scope of PCI control This bit is not implemented and is hardwired to 1 Writes to this bit position have no effect I O Access Enable 1 OAE Uncore This bit is not implemented in the processor and is hardwired to a 0 Writes to this bit position have no effect PCI STS PCI Status Register This status register reports the occurrence of error events on Device O s PCI interface Since Device 0 does not physically reside on PCI_A many of the bits are not implemented B D
45. Poisoned TLP is received by its Primary Side This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned Peer to peer posted forwarded will not set this bit They are reported at the receiving port Signaled System Error SSE This bit is set when this Device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is 1 Both received if enabled by BCTRL1 1 and internally detected error messages do not affect this field Received Master Abort Status RMAS This bit is Set when a Requester receives a Completion with Unsupported Request Completion Status On a Function with a Type 1 Configuration header the bit is Set when the Unsupported Request is received by its Primary Side Not applicable UR is not on primary interface Received Target Abort Status RTAS This bit is Set when a Requester receives a Completion with Completer Abort Completion Status On a Function with a Type 1 Configuration header the bit is Set when the Completer Abort is received by its Primary Side Not Applicable or Implemented Hardwired to 0 The concept of a Completer abort does not exist on primary side of this device Signaled Target Abort Status STAS This bit is Set when a Function completes a Posted or Non Posted Request as a Completer Abort error This applies to a Function with a Type 1 Configuration header when the Completer Abort was generated
46. Reset RST Description Value PWR P Detected Parity Error DPE This bit is set by a Function when it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register On a Function with a Type 1 Configuration header the bit is set when the Poisoned TLP is received by its Primary Side This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned Peer to peer posted forwarded will not set this bit They are reported at the receiving port Signaled System Error SSE This bit is set when this Device sends an SERR due to detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the Command register is 1 Both received if enabled by BCTRL1 1 and internally detected error messages do not affect this field Received Master Abort Status RMAS This bit is set when a Requester receives a Completion with Unsupported Request Completion Status On a Function with a Type 1 Configuration header the bit is set when the Unsupported Request is received by its Primary Side Not applicable There is not a UR on the primary interface Received Target Abort Status RTAS This bit is set when a Requester receives a Completion with Completer Abort Completion Status On a Function with a Type 1 Configuration header the bit is set when the Completer Abort is received by its Primary Side Not Applicable or Implemented Hardwired to 0 The concept of a Completer
47. The value returned on a read of this field is undefined Interrupt Remapping Enable I RE This field is valid only for implementations supporting interrupt remapping 0 Disable interrupt remapping hardware 1 Enable interrupt remapping hardware Hardware reports the status of the interrupt remapping enable operation through the IRES field in the Global Status register There may be active interrupt requests in the platform when 25 wo Uncore software updates this field Hardware must enable or disable interrupt remapping logic only at deterministic transaction boundaries so that any in flight interrupts are either subject to remapping or not at all Hardware implementations must drain any in flight interrupts requests queued in the Root Complex before completing the interrupt remapping enable command and reflecting the status of the command through the IRES field in the Global Status register The value returned on a read of this field is undefined Datasheet Volume 2 277 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 18 1Bh Reset Value 0000_ 0000h Access WO RO Size 32 bits BIOS Optimal Default 00_0000h Reset RST Description Value PWR p Set Interrupt Remap Table Pointer SI RTP This field is valid only for implementations supporting interrupt remapping Software sets this field to set update the interrupt remapping table pointer used by hardware The interrupt remapping tab
48. This field is relevant only when the F bit is set pare eo reseed o Datasheet Volume 2 257 Processor Configuration Registers intel 2 18 30 FRCDH_REG Fault Recording High Register This register records fault information when primary fault logging is active Hardware reports the number and location of fault recording registers through the Capability register This register is relevant only for primary fault logging This register is sticky and can be cleared only through power good reset or by software clearing the RWIC fields by writing a 1 B D F Type 0 0 0 GFXVTBAR Address Offset 208 20Fh Reset Value 0000_0000_0000_0000h Access RO RW1CS ROS V Size 64 bits BIOS Optimal Default 0000_0000_0000_0000h Reset RST GRUG Fault F Hardware sets this bit to indicate a fault is logged in this Fault Recording register The F field is set by hardware after the details 63 RW1CS Powerg of the fault is recorded in other fields When this bit is set hardware may collapse additional faults from the same source id SID Software writes the value read from this field to clear it Type T Type of the faulted request Powerg 0 Write request 62 ROS V ood 1 Read request or AtomicOp request This field is relevant only when the F field is Set and when the fault reason FR indicates one of the DMA remapping fault conditions Address Type AT This field captures the AT field from the faulted DMA re
49. Type 1 Configuration 15 Uncore Space header device whenever it receives a Poisoned TLP regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register Received System Error RSE 14 Uncore This bit is set when the Secondary Side for a Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL Received Master Abort RMA This bit is set when the Secondary Side for Type 1 Configuration 13 Uncore Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status Received Target Abort RTA This bit is set when the Secondary Side for Type 1 Configuration Uncore Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 The processor Uincore does not generate Target Aborts The root port will never complete a request using the Completer Abort Completion status UR detected inside the processor such as in MC will be reported in primary side status DEVSELB Timing DEVT aos Ro oop unore Not Applicable or Implemented Hardwired to 0 Master Data Parity Error SMDPE When set this bit indicates that the processor received across the RW1C Uncore link upstream a Read Data Completion Poisoned TLP EP 1 This bit can only be set when th
50. Virtual Channel are cleared in both Components on a Link ope o e een Datasheet Volume 2 197 Processor Configuration Registers intel 2 12 14 DMIESD DMI Element Self Description Register This register provides information about the root complex element containing this Link Declaration Capability B D F Type 0 0 0 DMIBAR Address Offset 44 47h Reset Value 0100_0202h Access RO RW O Size bits BIOS Optimal Default Reset RST Description Value PWR P Port Number PORTNUM This field specifies the port number associated with this element 31 24 Olh Uncore with respect to the component that contains this element This port number value is utilized by the egress port of the component to provide arbitration to this Root Complex Element Component ID CID This field identifies the physical component that contains this Root 23 16 RW O 00h Uncore Complex Element a a BIOS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS Number of Link Entries NLE This field indicates the number of link entries following the Element 15 8 02h Uncore Self Description This field reports 2 one for MCH egress port to main memory and one to egress port belonging to ICH on other side of internal link a o j o eea o Element Type ETYP 3 0 2h Uncore This field indicates the type of the Root Complex Element A va
51. above or 3 RW Uncore their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 0 All References to MDA and VGA space are not claimed by Device 6 Function 0 0 1 Illegal combination 0 All VGA and MDA references are routed to PCI Express Graphics Attach Device 6 Function 0 1 All VGA references are routed to PCI Express Graphics Attach Device 6 Function 0 MDA references are not claimed by Device 6 Function 0 VGA and MDA memory cycles can only be routed across PEG60 when MAE PCICMD60 1 is set VGA and MDA I O cycles can only be routed across PEG60 if OAE PCICMD60 0 is set Encoding 0 No MDA 1 MDA Present Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 0 0 PCI Address Offset 87h Reset Value 00h Access RW Size S aad BIOS Optimal Default Reset RST ORES PEG12 MDA Present MDAP12 This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 2 to control the routing of processor initiated transactions targeting MDA compatible 1 O and memory address ranges This bit should not be set if Device 1 Function 2 VGA Enable bit is not set If Device 1 Function 2 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not presen
52. an uncorrectable multiple bit error When this bit is set the column row bank and rank that caused the error and the error syndrome are logged in the ECC Error Log register in the channel where the error occurred Once this bit is set the ECCERRLOGx fields are locked until the processor clears this bit by writing a 1 Software uses bits 1 0 to detect whether the logged error address is for a Single bit or a Multiple bit error This bit is reset on PWROK Single bit DRAM ECC Error Flag DSERR If this bit is set to 1 a memory read data transfer had a single bit correctable error and the corrected data was returned to the requesting agent When this bit is set the column row bank and rank where the error occurred and the syndrome of the error are logged in the ECC Error Log register in the channel where the error occurred Once this bit is set the ECCERRLOGx fields are locked to further single bit error updates until the processor clears this bit by writing a 1 A multiple bit error that occurs after this bit is set will overwrite the ECCERRLOGx fields with the multiple bit error signature and the DMERR bit will also be set A single bit error that occurs after a multi bit error will set this bit but will not overwrite the other fields This bit is reset on PWROK Datasheet Volume 2 Processor Configuration Registers intel 2 5 33 ERRCMD Error Command Register This register controls the Host Bridge responses to vario
53. and invalidation queue are always coherent Datasheet Volume 2 231 Processor Configuration Registers intel 2 18 4 GCMD_REG Global Command Register This register controls remapping hardware If multiple control fields in this register need to be modified software must serialize the modifications through multiple writes to this register B D F Type 0 0 0 GFXVTBAR Address Offset 18 1Bh Reset Value 0000_0000h Access RO WO Size 32 bits BIOS Optimal Default 000000h Reset RST Description Value PWR p Translation Enable TE Software writes to this field to request hardware to enable disable DMA remapping 0 Disable DMA remapping 1 Enable DMA remapping Hardware reports the status of the translation enable operation through the TES field in the Global Status register There may be active DMA requests in the platform when software 31 wo Uncore updates this field Hardware must enable or disable remapping logic only at deterministic transaction boundaries so that any in flight transaction is either subject to remapping or not at all Hardware implementations supporting DMA draining must drain any in flight DMA read write requests queued within the Root Complex before completing the translation enable command and reflecting the status of the command through the TES field in the Global Status register The value returned on a read of this field is undefined Set Root Table Pointer SRTP
54. applicable only when interrupt 23 RO V Uncore remapping is enabled and Extended Interrupt Mode x2APIC mode is not enabled 0 Compatibility format interrupts are blocked 1 Compatibility format interrupts are processed as pass through bypassing interrupt remapping je o eea 2 18 6 RTADDR_REG Root Entry Table Address Register This register provides the base address of root entry table B D F Type 0 0 0 GFXVTBAR Address Offset 20 27h Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 0000000000h Reset RST Description Value PWR P ssf o o peen o Root Table Address RTA This register points to base of page aligned 4 KB sized root entry table in system memory Hardware ignores and does not 38 12 RW 0000000h Uncore implement bits 63 HAW where HAW is the host address width Software specifies the base address of the root entry table through this register and programs it in hardware through the SRTP field in the Global Command register Reads of this register returns value that was last programmed to it moo a eena 236 Datasheet Volume 2 Processor Configuration Registers intel 2 18 7 CCMD_REG Context Command Register This register manages context cache The act of writing the upper most byte of the CCMD_REG with the ICC field set causes the hardware to perform the context cache invalidation B D F Type 0 0 0 GFXVTBAR Address Offset 28 2Fh R
55. appropriately addressed B D F Type 0 0 0 PCI Address Offset 8h Reset Value 00h Access RO FW Size 8 bits Reset RST Description Value PWR j Revision Identification Number RID This is an 8 bit value that indicates the revision identification 7 0 RO FW 00h Uncore number for the Processor Device 0 Refer to the Intel Xeon Processor E3 1200 Family Specification Update for the value of the RID register Datasheet Volume 2 Processor Configuration Registers 2 5 6 2 5 7 intel CC Class Code Register This register identifies the basic function of the device a more specific sub class and a register specific programming interface B D F Type 0 0 0 PCI Address Offset 9 Bh Reset Value 06_0000h Access Size Reset RST Description Value PWR P Base Class Code BCC This is an 8 bit value that indicates the base class code for the Host 23 16 06h U nee Bridge device This code has the value 06h indicating a Bridge device Sub Class Code SUBCC This is an 8 bit value that indicates the category of Bridge into T98 oon Ungore which the Host Bridge device falls The code is 00h indicating a Host Bridge Programming I nterface PI 7 0 00h Uncore This is an 8 bit value that indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device HDR Header Type Register This register
56. as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within the processor such as VGA compatible address ranges mapping B D F Type 0 1 0 2 PCI Address Offset 3E 3Fh Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default Oh Reset RST Value PWR Description Timer SERR Enable DTSERRE Not Applicable or Implemented Hardwired to 0 Discard Timer Status DTSTS Not Applicable or Implemented Hardwired to 0 Secondary Discard Timer SDT Not Applicable or Implemented Hardwired to 0 Primary Discard Timer PDT fe icable or Implemented Hardwired to 0 Fast Back to Back Enable FB2BEN Not Applicable or Implemented Hardwired to 0 Secondary Bus Reset SRESET Uncore Setting this bit triggers a hot reset on the corresponding PCI Express Port This will force the TXTSSM to transition to the Hot Reset state using Recovery from LO LOs or L1 states 5 wAcere Master Abort Mode MAMODE Does not apply to PCI Express Hardwired to 0 VGA 16 bit Decode VGA16D This bit enables the PCI to PCI bridge to provide 16 bit decoding of VGA I O address precluding the decoding of alias addresses every RW Uncore 1 KB This bit only has meaning if bit 3 VGA Enable of this register is also set to 1 enabling VGA I O decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA I O accesses 1 Execute 16 bit address decodes on VGA I O
57. by its Primary Side Not Applicable or Implemented Hardwired to 0 The concept of a target abort does not exist on primary side of this device DEVSELB Timing DEVT This device is not the subtractive decoded device on bus 0 This bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode Does not apply to PCI Express and must be hardwired to 00b 90 Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 1 0 2 PCI Address Offset 6 7h Reset Value 0010h Access RW1C RO RO V Size oe bits BIOS Optimal Default Reset RST OREI Master Data Parity Error PMDPE This bit is Set by a Requester Primary Side for Type 1 Configuration Space header Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs e Requester receives a Completion marked poisoned RWIC Uncore e Requester poisons a write Request If the Parity Error Response bit is Ob this bit is never Set This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned Peer to peer posted forwarded will not set this bit They are reported at the receiving port ncare Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 ep o o j pema ooo ore 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 Capabilities List CAPL uncore Fane that a capabi
58. default on Reset as well as when the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link E 2 12 11 DMIVCPRCAP DMI VCp Resource Capability Register B D F Type 0 0 0 DMI BAR Address Offset 28 2Bh Reset Value 0000_0001h Access Size BIOS Optimal Default Reset RST eee joe ace Goes Bin eon O O 31 24 Ro oon Uncore Reserved for Port Arbitration Table Offset PATO eo a 22 16 RO ooh Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the 15 Uncore TLP header are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request me o j o O eena ooo zo Rro omm Uncore Reserved for Port Arbitration Capability PAC Datasheet Volume 2 195 Processor Configuration Registers intel 2 12 12 DMIVCPRCTL DMI VCp Resource Control Register This register controls the resources associated with the DMI Private Channel VCp B D F Type 0 0 0 DMIBAR Address Offset 2C 2Fh Reset Value 0200_0000h Access RO RW Size 32 bits B
59. ease teeta een enataes 202 2 12 21 LSTS DMI Link Status Register cece eee e eee ee eee teeter eee e ee tena e ee eas 203 2 12 22 LCTL2 Link Control 2 RegiSter cccceccce cece eee ee eens teen eae eee teen nantes 204 2 12 23 LSTS2 Link Status 2 ReGiSter cece cette eee eee eee eee teenie ees 206 2 12 24 AFE_BMUFO AFE BMU Configuration Function 0 Register eee 206 2 12 25 AFE_BMUTO AFE BMU Configuration Test 0 Register ceeeeeee eee 206 2 13 MCHBAR Registers in Memory Controller Channel 0 cceceeeee eee ee eee ee teeta een ees 207 2 13 1 TC_DBP_CO Timing of DDR Bin Parameters Register cccceeeee eee 207 2 13 2 TC_RAP_CO Timing of DDR Regular Access Parameters Register 208 2 13 3 SC_1O_LATENCY_CO IO Latency Configuration Register e 208 2 13 4 TC_SRFTP_CO Self Refresh Timing Parameters Register eee 209 2 13 5 PM_PDWN_config_CO Power down Configuration Register 00 209 2 13 6 ECCERRLOGO_CO ECC Error Log 0 Register cecceceee cette eee e ee eee eeee 210 2 13 7 ECCERRLOG1_CO ECC Error Log 1 Register cececeee eect eee ne eee ee aes 210 2 13 8 TC_RFP_CO Refresh Parameters Register cece eee ee eens 211 2 13 9 TC_RFTP_CO Refresh Timing Parameters Register cceeeeeee eee ees 211 2 14 MCHBAR Registers in Memory Controller Channel 1 ccceeeeeseee
60. eee tenet ene ee eee ee eee ee teeta 163 2 10 25 PM_CAPID6 Power Management Capabilities Register cee 165 2 10 26 PM _CS6 Power Management Control Status Register eeeeeee ees 166 2 10 27 SS CAPID Subsystem ID and Vendor ID Capabilities Register 167 2 10 28 SS Subsystem ID and Subsystem Vendor ID Register c cece eee eee 168 2 10 29 MSI_CAPID Message Signaled Interrupts Capability ID Register 168 2 10 30 MC Message Control ReGiSter ccece cece eect eee teens tee ee ee eet ee teeta tae 169 2 10 31 MA Message Address ReQISter c ccceceeteee teen eee ee eee e nent eee tee na eet teeta 170 2 10 32 MD Message Data Register ceececee cette eect tere ee ee teeta e eee ee tena eee tetas 170 2 10 33 PEG _CAPL PCI Express G Capability List Register ccce 170 2 10 34 PEG CAP PCI Express G Capabilities Register cece eee cece eee eee ees 171 2 10 35 DCAP Device Capabilities Register icc eter cece e nett teen eee teeta ees 171 2 10 36 DCTL Device Control Register ccc eet c eee ee eee eee eee teeta tae ee teeta 172 2 10 37 DSTS Device Status Register cece cece eect eee eee e eee ee tee e eee e tae 173 2 10 38 LCTL Link Control Register ccc cecte cece erent eee ee eee teeta eee ee eet te ees 174 2 10 39 LSTS Link Status Register ccc en eee ee eee eee eee rene eee ea es 176 2 10 40 S
61. exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is currently disabled 31 RW Uncore BIOS Requirement To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link Software must ensure that no traffic is using a Virtual Channel at the time it is disabled Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel pare me aes CS Virtual Channel 1 ID VC1ID Assigns a VC ID to the VC resource Assigned value must be non 26 24 om uo es zero This field can not be modified when the VC is already enabled saf o f o peen o Port Arbitration Select PAS Configures the VC resource to provide a particular Port Arbitration 19 17 RW 000b Uncore service Valid value for this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource e o oe eera CS 7 Ro ob Uncore Traffic Class m Virtual Channel 1 TCMVC1M Traffic Class
62. identifies the header layout of the configuration space No physical register exists at this location B D F Type 0 0 0 PCI Address Offset Eh Reset Value 00h Access RO Size 8 bits Reset RST cache js fae Ses Sim sermon PCI Header HDR 7 0 00h Uncore This field always returns 0 to indicate that the Host Bridge is a single function device with standard header layout Reads and writes to this location have no effect Datasheet Volume 2 53 Processor Configuration Registers 2 5 8 SVID Subsystem Vendor Identification Register This value is used to identify the vendor of the subsystem B D F Type 0 0 0 PCI Address Offset 2C 2Dh Reset Value 0000h Access RW O Size 16 bits Reset RST ae jose ace e Bite eon O O Subsystem Vendor ID SUBVID i A This field should be programmed during boot up to indicate the 13 0 RWO on Un org vendor of the system board After it has been written once it becomes read only 2 5 9 SI D Subsystem Identification Register This value is used to identify a particular subsystem B D F Type 0 0 0 PCI Address Offset 2E 2Fh Reset Value 0000h Access RW O Size 16 bits Reset RST roar jose acer Seiad Sha T Subsystem ID SUBI D 15 0 RW O 0000h Uncore This field should be programmed during BIOS initialization After it has been written once it becomes read only 54 Datasheet Volume 2 Processor Configuration Registers 2
63. indicates status of errors as perceived by the Uncore respective Function Not Applicable or Implemented Hardwired to 0 Non Fatal Error Detected NFED This bit indicates status of Nonfatal errors detected Errors are logged in this register regardless of whether error reporting is Uncore enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Not Applicable or Implemented Hardwired to 0 Correctable Error Detected CED This bit indicates status of correctable errors detected Errors are logged in this register regardless of whether error reporting is Uncore enabled or not in the Device Control register For a multi Function device each Function indicates status of errors as perceived by the respective Function Not Applicable or Implemented Hardwired to 0 os Eo Eara T GS Datasheet Volume 2 Processor Configuration Registers 2 6 38 LCTL Link Control Register This register allows control of PCI Express link B D F Type 0 1 0 2 PCI Address Offset BO Bih Reset Value 0000h Access RW RO RW V Size 16 bits BIOS Optimal Default 00h Reset RST Description Value PWR P 15 12 Ro on f Reseved o C sCizC Link Autonomous Bandwidth Interrupt Enable LABI E When Set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bi
64. memory base is calculated by subtracting the amount of memory stolen by the Manageability Engine from TOM Only ME can access this space it is not accessible by or coherent with any processor side accesses PCI Memory Address Range TOLUD 4 GB This address range from the top of low usable DRAM TOLUD to 4 GB is normally mapped to the DMI Interface Device 0 exceptions are 1 Addresses decoded to the egress port registers PXPEPBAR 2 Addresses decoded to the memory mapped range for internal MCH registers MCHBAR 3 Addresses decoded to the registers associated with the MCH ICH Serial Interconnect DMI register memory range DMIBAR For each PCI Express port there are two exceptions to this rule 1 Addresses decoded to the PCI Express Memory Window defined by the MBASE MLIMIT registers are mapped to PCI Express 2 Addresses decoded to the PCI Express prefetchable Memory Window defined by the PMBASE PMLIMIT registers are mapped to PCI Express In integrated graphics configurations there are exceptions to this rule 1 Addresses decode to the internal graphics translation window GMADR 2 Addresses decode to the Internal graphics translation table or IGD registers GTTMMADR In a VT enable configuration there are exceptions to this rule 1 Addresses decoded to the memory mapped window to PEG DMI VCO VT remap engine registers VTDPVCOBAR 2 Addresses decoded to the memory mapped window to Graphics VT r
65. messages Any INTA emulation interrupts already asserted must be de 10 RW Uncore asserted when this bit is set Only affects interrupts generated by the device PCI INTA from a PME or Hot Plug event controlled by this command register It does not affect upstream MSIs upstream PCI INTA INTD assert and deassert messages Uincore Fast Back to Back Enable FB2B Not Applicable or Implemented Hardwired to 0 SERR Message Enable SERRE This bit controls the root port SERR messaging The processor communicates the SERR condition by sending an SERR message to the PCH This bit when set enables reporting of non fatal and fatal errors detected by the device to the Root Complex Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control Register In addition for Type 1 configuration space header devices this bit when set enables transmission by the primary interface of RW Uncore ERR_NONFATAL and ERR_FATAL error messages forwarded from the secondary interface This bit does not affect the transmission of forwarded ERR_COR messages 0 The SERR message is generated by the root port only under conditions enabled individually through the Device Control Register 1 The root port is enabled to generate SERR messages that will be sent to the PCH for specific root port error conditions generated detected or received on the secondary side of the virtual PCI to PC
66. of CAS Read command PWR_CAS_R Power contribution of RAS command and PRE command PWR_RAS_ PRE Power contribution of RAS command and PRE command The value 7 0 RW LV 00h U rs should be the sum of the two commands assuming that each RAS command for a given page is followed by a PRE command to the same page in the near future 2 17 5 PM_BW_LIMIT_config BW Limit Configuration Register This register defines the BW throttling at temperature Note that the field BW_limit_tf may not be changed in run time Other fields may be changed in run time B D F Type 0 0 0 MCHBAR_ MCBCAST Address Offset 4F88 4F8Bh Reset Value FFFF_O3FFh Access RW L Size 32 bits BIOS Optimal Default 00h Reset RST ue joe ace e Bite eon O O BW limit when rank is hot BW_limit_ hot 31 24 RW L FFh Uncore poe number of transactions allowed per rank when status of rank is Range 0 255h BW limit when rank is warm BW_limit_warm 23 16 RW L FFh Uncore Tne namber of transactions allowed per rank when status of rank is Range 0 255h sof e o pema ooo BW limit time frame BW_limit_tf RW L 3FFh Uncore Lime frame in which the BW limit is enforced in DCLK cycles Range 1 1023h Note that the field BW_limit_tf may not be changed in run time 224 Datasheet Volume 2 Processor Configuration Registers intel 2 18 Integrated Graphics VT d Remapping Engine Registers Table 2 20 lists the registers arranged by a
67. of up to 82 us Datasheet Volume 2 221 intel 2 17 Processor Configuration Registers Memory Controller MMIO Registers Broadcast Group Table 2 19 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 19 Memory Controller MMIO Registers Broadcast Group Register Address Map ais wwe ween SE oe Or FS A A 2 17 1 222 C A PM_PDWN_ Config Power down Configuration Register This register defines the power down CKE off operation power down mode idle timer and global per rank decision B D F Type 0 0 0 MCHBAR_MCBCAST Address Offset 4CB0 4CB3h Default Value 0000_ 0000h Access RW L Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR p 31 13 Ro on Reseved S O Global power down GLPDN Uncore 1 Power down decision is global for channel 0 A separate decision is taken for each rank Power down mode PDWN_ mode Selects the mode of power down All encodings not in table are reserved Note When selecting DLL off or APD DLL off DIMM MRO register bit 12 PPD must equal 0 Note When selecting APD PPD or APD PPD DIMM MRO register bit 12 PPD must equal 1 Uncore The value Oh no power down is a don t care Oh No Power Down 1h APD 2h PPD 3h APD PPD 6h DLL Off 7h APD DLL Off Power down idle timer PDWN_idle_ counter Uncore This defines the
68. register attributes that are used in this document Attribute modifiers are listed in Table 2 2 Table 2 1 Register Attributes and Terminology Read Only These bits can only be read by software writes have no effect The value of the bits is determined by the hardware only RW Read Write These bits can be read and written by software Read Write 1 to Clear These bits can be read and cleared by software Writing a 1 to a bit will clear it while writing a O to a bit has no effect Hardware sets these bits Read Write 0 to Clear These bits can be read and cleared by software Writing a 0 to a bit will clear it while writing a 1 to a bit has no effect Hardware sets these bits Read Write 1 to Set These bits can be read and set by software Writing a 1 to a bit will set it while writing a 0 to a bit has no effect Hardware clears these bits Reserved and Preserved These bits are reserved for future RW implementations and their value must not be modified by software When writing to these bits software must preserve the value read When SW updates a register that has RsvdP fields it must read the register value first so that the appropriate merge between the RsvdP and updated fields will occur Reserved and Zero These bits are reserved for future RW1C implementations SW must use 0 for writes Write Only These bits can only be written by software reads return zero Note Use of this attribut
69. requests queued within the Root Complex before completing the translation enable command and reflecting the status of the command through the TES field in the Global Status register The value returned on a read of this field is undefined Datasheet Volume 2 275 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 18 1Bh Reset Value 0000_ 0000h Access WO RO Size 32 bits BI OS Optimal Default 00_0000h perce RST Description Value PWR P Set Root Table Pointer SRTP Software sets this field to set update the root entry table pointer used by hardware The root entry table pointer is specified through the Root entry Table Address RTA_REG register Hardware reports the status of the Set Root Table Pointer operation through the RTPS field in the Global Status register The Set Root Table Pointer operation must be performed before enabling or re enabling after disabling DMA remapping through the TE field After a Set Root Table Pointer operation software must globally 30 wo Uncore invalidate the context cache and then globally invalidate of IOTLB This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer and not stale cached entries While DMA remapping hardware is active software may update the root table pointer through this field However to ensure valid in flight DMA requests are deterministically remapped software must en
70. reser o SS Datasheet Volume 2
71. result in SERR message when individually enabled by the Root Control register Parity Error Response Enable PEREN This bit controls whether or not the Master Data Parity Error bit in the Secondary Status register is set when the root port receives RW ncore across the link upstream a Read Data Completion Poisoned TLP 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set 164 Datasheet Volume 2 Processor Configuration Registers intel 2 10 25 PM_CAPID6 Power Management Capabilities Register B D F Type 0 6 0 PCI Address Offset 80 83h Reset Value C803_9001h Access RO RO V Size 32 bits Reset RST Description Value PWR p PME Support PMES This field indicates the power states in which this device may indicate PME wake using PCI Express messaging DO D3hot and 31 27 19h Uncore D3cold This device is not required to do anything to support D3hot and D3cold it simply must report that those states are supported Refer to the PCI Power Management 1 1 Specification for encoding explanation and other power management details D2 Power State Support D2PSS 26 Uncore Hardwired to 0 to indicate that the D2 power management state is NOT supported D1 Power State Support D1PSS 25 Uncore Hardwired to 0 to indicate that the D1 power management state is NOT supported Auxiliary Current AUXC 24 22 000b Uncore H
72. set to 1 if Device 2 is disabled using a register DEVEN 3 0 This register is locked by Intel TXT lock RW KL Gace GGC Lock GGCLCK When set to 1b this bit will lock all bits in this register 58 Datasheet Volume 2 Processor Configuration Registers intel 2 5 13 DEVEN Device Enable Register This register allows for enabling disabling of PCI devices and functions that are within the processor package In the following table the bit definitions describe the behavior of all combinations of transactions to devices controlled by this register All the bits in this register are Intel TXT Lockable B D F Type 0 0 0 PCI Address Offset 54 57h Reset Value 0000_209Fh Access Size RW L RO RW 32 bits BIOS Optimal Default 00_0000h Datasheet Volume 2 Reset RST Description Value PWR 4 Reseved S O Reserved S PEG60 Enable D6FOEN 0 Disabled Bus 0 Device 6 Function 0 is disabled and hidden Uncore 1 Enabled Bus 0 Device 6 Function 0 is enabled and visible This bit will be set to Ob and remain Ob if PEG60 capability is disabled O eena OO O O ema oo O pema SCS Internal Graphics Engine D2EN 0 Disabled Bus 0 Device 2 is disabled and hidden Uncore 1 Enabled Bus 0 Device 2 is enabled and visible This bit will be set to Ob and remain Ob if Device 2 capability is disabled e PEG11 is disabled by strap PEGOCFGSEL PEG12 Enable D1F2EN 0 Disabled Bus 0 Dev
73. software must perform domain selective or global invalidation of IOTLB after the context cache invalidation has completed Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flush before invalidating the context cache Context I nvalidation Request Granularity CI RG Software provides the requested invalidation granularity through this field when setting the ICC field 00 Reserved 01 Global Invalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field 11 Device selective invalidation request The target source 62 61 RW Oh Uncore id s must be specified through the SID and FM fields and the domain id that was programmed in the context entry for these device s must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field Datasheet Volume 2 281 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 28 2Fh Reset Value 0000_0000_0000_0000h Access RW V RW RO V Size 64 bits BIOS Optimal Default 0_0000_0000h Reset RST re js awe
74. specified by ADDR and AM fields Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware may preserve the cached non leaf page table entries corresponding to mappings specified by ADDR and AM fields Address Mask AM The value in this field specifies the number of low order bits of the ADDR field that must be masked for the invalidation operation This field enables software to request invalidation of contiguous mappings for size aligned regions For example Mask ADDR bits Pages Value masked invalidated None 1 12 2 5 0 RW 00h Uncore 13 12 4 14 12 8 15 12 16 When invalidating mappings for super pages software must specify the appropriate mask value For example when invalidating mapping for a 2 MB page software must specify an address mask value of at least 9 Hardware implementations report the maximum supported mask value through the Capability register 254 Datasheet Volume 2 Processor Configuration Registers intel 2 18 28 OTLB_REG I OTLB I nvalidate Register This register invalidates the OTLB The act of writing the upper byte of the OTLB_REG with IVT bit set causes the hardware to perform the OTLB invalidation B D F Type 0 0 0 GFXVTBAR Address Offset 108 10Fh Reset Value 0200_0000_0000_0000h Access RW V RW RO V Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RS
75. sss Sie esermton Context Actual Invalidation Granularity CAI G Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion by clearing the ICC field The following are the encodings for this field 00 Reserved 01 Global Invalidation performed This could be in response to a global domain selective or device selective invalidation 60 59 RO V Oh Uncore request 10 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or device selective invalidation request Device selective invalidation performed using the source id and domain id specified by software in the SID and FM fields This can only be in response to a device selective invalidation request wa o o eea o Function Mask FM Software may use the Function Mask to perform device selective invalidations on behalf of devices supporting PCI Express Phantom Functions This field specifies which bits of the function number portion least significant three bits of the SID field to mask when performing device selective invalidations The following encodings are defined for this field 33 32 RW Oh Uncore 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of function number in the SID fie
76. supported by the component as reported in the Supported Link Speeds field of the Link Capabilities Register unless the corresponding platform form factor requires a different Reset Value For both Upstream and Downstream ports this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode Datasheet Volume 2 205 t i Processor Configuration Registers 2 12 23 LSTS2 Link Status 2 Register B D F Type 0 0 0 DMI BAR Address Offset 9A 9Bh Reset Value 0000h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR p o o j perae SS SEA Current De emphasis Level CURDELVL When the Link is operating at 5 GT s speed this reflects the level of de emphasis Uncore 1 3 5 dB 0 6 dB When the Link is operating at 2 5 GT s speed this bit is Ob 2 12 24 AFE_BMUFO AFE BMU Configuration Function 0 Register B D F Type 0 0 0 DMIBAR Address Offset BCO BC3h Reset Value E978873Ch Access RO RW Size 32 bits Reset RST D ipti Value PWR escription 1110100 Reserved Must be 1 110100 101111 00 010b when writing this 31 14 101111 Uncore register 00 010b PEG Half Swing Enable DETPNSEL 13 RW Uncore This bit is for PEG half swing de emphasis enable 0 No De emphasis at Half Swing for 16 PEG lanes 1 De emphasis 3 5 db at Half Swing 16 PEG lanes 12 0 Ro 90111010 Reserved Must
77. teen eee 78 ERRSTS Error Status ReQiSter ccceceece eee e reece eee eee eee 80 ERRCMD Error Command ReGiSter cceceeee cent eee e ee ee eee e eee ee tena eee ees 81 SMI Command ReGIStel si ciinacccceectscisctecwcsneteed eaan kinak EnA EEEa ia 81 SCICMD SCI Command Register ss ssssrrsssrnusrrrrrrnnssrrnnnrrrnuunrrrrnnnennn 82 SKPD Scratchpad Data Register sssssssrrrrrssssnrrrrrrrrnnsrrrrtrrrnnnnerrrrnnrnnn 82 CAPIDO_A Capabilities A Register sssssssssrrrssrrrrrrrrrnsrrrrrrrrrrrnnnrrrrrrnnnn 83 evice 1 Function 0 2 Configuration Registers ssssssssssssrrrrssrrrrerrirrrererrrrseen 85 VID1 Vendor Identification Register cece eee e ete ee ene eet eee eea teeta 87 DID1 Device Identification Register cece eee ce ee ee teeta neta eeaeaes 87 PCICMD1 PCI Command Register cceeeceee ete ee cnet e eee teeta teeta ene e neta 88 PCISTS1 PCI Status Register ccce cette cece e eee eee eee eee et eee tennant eee 90 RID1 Revision Identification Register ccccece cece eter ete e nett tee eee nies 92 CC1 Class Code ReGiSter cece cece eee eee ee teeter teeta eater teen 92 CL1 Cache Line Size ReGiSter cece teeter ener eee 93 HDR1 Header Type Register ccceccece eee e cece e eee eee ee eee e teens eet eee teen enat ees 93 PBUSN1 Primary Bus Number ReGiSter cceeeeeeee eee ee eee ee eee eee eae ee eee ees 93 SBUSN
78. that supports power fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note that depending on hardware capability it is possible that a power fault can be detected at any time independent of the Power Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Reserved for Attention Button Pressed ABP If an Attention Button is implemented this bit is set when the attention button is pressed If an Attention Button is not supported this bit must not be set 123 Processor Configuration Registers intel 2 6 43 RCTL Root Control Register This register allows control of PCI Express Root Complex specific parameters The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register B D F Type 0 1 0 2 PCI Address Offset BC BDh Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 000h Reset RST Description Value PWR p PME Interrupt Enable PMEIE 0 Disable No interrupts are generated as a result of receiving PME messages 1 Enable interrupt generation upon receipt of a PME message as refle
79. that the error is due to poisoning safe o eea Uncorrectable Error Status MERRSTS This bit is set when an uncorrectable multiple bit error occurs on a P memory read data transfer When this bit is set the address that 1 ROS V ei caused the error and the error syndrome are also logged and they are locked until this bit is cleared This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared Correctable Error Status CERRSTS This bit is set when a correctable single bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they ROS V Powerg are locked to further single bit errors until this bit is cleared A multiple bit error that occurs after this bit is set will override the address error syndrome information This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared 2 13 7 B D F Type Address Offset Reset Value Access Size ECCERRLOG1 CO ECC Error Log 1 Register 0 0 0 MCHBAR MCO 40CC 40CFh 0000_0000h ROS V 32 bits Reset RST T js awe ss Sie esermton Error Column ERRCOL This field holds the DRAM column address of the read transaction that had the ECC error Error Row ERRROW This field holds the DRAM row page address of the read transaction that had the ECC error 210 Datasheet Volume 2 Processor Configuration Registers 5 P e 2 13 8 TC
80. the Command register is a 0 and this Interrupt Status bit is a 1 will the devices INTx signal be asserted Oe o ee Datasheet Volume 2 135 Processor Configuration Registers 2 8 5 RI D2 Revision Identification Register This register contains the revision number for Device 2 Functions 0 These bits are read only and writes to this register have no effect B D F Type Address Offset Reset Value 0 2 0 PCI 8h 00h Access RO FW Size 8 bits Reset RST Description Value PWR p Revision Identification Number MSB RI D_MSB 7 4 RO FW Oh Uncore Four MSB of RID Refer to the Intel Xeon Processor E3 1200 Family Specification Update for the value of the RID register Revision Identification Number RID 3 0 RO FW Oh Uncore Four LSB of RID Refer to the Intel Xeon Processor E3 1200 Family Specification Update for the value of the RID register 2 8 6 CC Class Code Register This register contains the device programming interface information related to the Sub Class Code and Base Class Code definition for the IGD This register also contains the Base Class Code and the function sub class in relation to the Base Class Code B D F Type Address Offset Reset Value 0 2 0 PCI 9 Bh 03_0000h Access RO V RO Size 24 bits Reset RST Description Value PWR p Base Class Code BCC 23 16 RO V 03h Uncore This is an 8 bit value that indicates the base class code 03h indicates a Displ
81. the limit address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region limit depends on the number of reserved bits N 0 of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The protected high memory base amp limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits HAW N 1 specifies a protected low memory region of size 2 N 1 bytes e Programming the protected high memory limit register with a value less than the protected high memory base register disables the protected high memory region Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 78 7Fh Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 0000_0000_0000h Reset RST Description Value PWR P rere o m pe
82. the value programmed in this field Datasheet Volume 2 253 t i Processor Configuration Registers 2 18 27 IVA_REG Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding OTLB Invalidate register This register is a write only register B D F Type 0 0 0 GFXVTBAR Address Offset 100 107h Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 0000_ 0000h Reset RST n jee ew fic pk ee rere no om pema OOO Address ADDR Software provides the DMA address that needs to be page selectively invalidated To make a page selective invalidation 38 12 0000000h Uncore request to hardware software must first write the appropriate fields in this register and then issue the appropriate page selective invalidate command through the OTLB_REG Hardware ignores bits 63 N where N is the maximum guest address width MGAW supported a o eea o I nvalidation Hint 1H This bit provides hint to hardware about preserving or flushing the non leaf page directory entries that may be cached in hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request RW Oh Uncore hardware must flush both the cached leaf and non leaf page table entries corresponding to the mappings
83. this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1 1 specification BS o o eera ooo ncore Extended Tag Field Supported ETFS Hardwired to indicate support for 5 bit Tags as a Requestor Phantom Functions Supported PFS 4 3 U GEA Not Applicable or Implemented Hardwired to 0 Max Payload Size MPS 2 0 RW O 000b Uncore Default indicates 128B maximum supported payload for Transaction Layer Packets TLP Datasheet Volume 2 Processor Configuration Registers 2 6 36 intel DCTL Device Control Register This register provides control for PCI Express device specific capabilities The error reporting enable bits are in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR_CORR ERR_NONFATAL ERR_FATAL received by Root Port is controlled exclusively by Root Port Command Register B D F Type 0 1 0 2 PCI Address Offset A8 A9h Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh Reset RST ae E fo o eena o 14 12 000b Reserved for Max Read Request Size MRRS pu o Uncore Reserved for Enable No Snoop NSE of feeen CS Max Payload Size MPS 000 128B maximum payload for Transaction Layer Packets TLP RW 000b Uncore All other encodings are reserved As a receiver the device must handle TLPs as larger as the value set in this field As a transmitte
84. this field for VCp traffic that will be translated by a virtualization engine and TC2 00000010b is 6 1 RW 00h Uncore the only value that should be programmed into this field for VCp traffic that will not be translated by a virtualization engine This strategy can simplify debug and limit validation permutations BIOS Requirement Program this field with the value 100010b which maps TC2 and TC6 to VCp ios reo vee map reaver CS 196 Datasheet Volume 2 Processor Configuration Registers intel 2 12 13 DMIVCPRSTS DMI VCp Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMIBAR Address Offset 32 33h Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P safe o j pee o Virtual Channel private Negotiation Pending VCPNP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This 1 RO V 1b Uncore bit indicates the status of the process of Flow Control initialization It is set by default on Reset as well as when the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that
85. to enforce prevention of overlap and operations of the system in the case of overlap are not ensured B D F Type 0 1 0 2 PCI Address Offset 22 23h Reset Value 0000h Access RW Size a bits BIOS Optimal Default Memory Address Limit MLI MIT 000h Uncore This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G se we reser o Reset RST Description Value PWR p Datasheet Volume 2 Processor Configuration Registers E t 2 6 17 PMBASE1 Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 2 PCI Address Offset 24 25h Reset Value FFF1h Access RW RO Size 16 bits Reset RST Description Value PWR P Prefetchable Memory Base
86. when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write even if the corresponding hotplug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined Depending on the form factor the power is turned on off either to Uncore the slot or within the adapter Note that in some cases the power controller may autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the Power Controller Control setting 0 Power On 1 Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob writes to this field have no effect and the read value of this field is undefined Reserved Power Indicator Control PIC If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Uncore Datasheet Volume
87. 00 RO RW1CS DMA Remap Engine Policy Control RO RO KFW 2 18 1 VER_REG Version Register This register reports the architecture version supported Backward compatibility for the architecture is maintained with new revision numbers allowing software to load remapping hardware drivers written for prior architecture versions B D F Type 0 0 0 GFXVTBAR Address Offset 0 3h Reset Value 0000_0010h Access RO Size 32 bits BIOS Optimal Default 000000h Reset RST Description Value PWR p Major Version number MAX 7 4 0001b Uncore panie es This field indicates supported architecture version 3 0 0000b fincas Minor Version number MIN l l l This field indicates supported architecture minor version 226 Datasheet Volume 2 Processor Configuration Registers 2 18 2 CAP_REG Capability Register This register reports general remapping hardware capabilities B D F Type 0 0 0 GFXVTBAR Address Offset 8 Fh Reset Value 00CO_0000_20E6_0262h Access RO Size 64 bits BIOS Optimal Default 000h Bie O Oos OO O Co f pena oo DMA Read Draining DRD 1b Hardware does not support draining of DMA read requests Hardware supports draining of DMA read requests DMA Write Draining DWD Uncore 0 Hardware does not support draining of DMA write requests 1 Hardware supports draining of DMA write requests Maximum Address Mask Value MAMV The value in this field indicates the maximum supported v
88. 0000h Access RW Size 32 bits Reset RST ree joe ace Sates Bite eon O O Extended Interrupt Message Data EI MD This field is valid only for implementations supporting 32 bit 31 16 RW 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data may treat this field as RsvdZ Data value in the interrupt request 2 18 11 FEADDR_REG Fault Event Address Register This register specifies the interrupt message address B D F Type 0 0 0 GFXVTBAR Address Offset 40 43h Reset Value 0000_ 0000h Access Size BIOS Optimal Default Reset RST aeea Message Address MA 31 2 RW 00000000h Uncore When fault events are enabled the contents of this register specify the DWORD aligned address bits 31 2 for the interrupt request pee fa awe SSCSC S 2 18 12 FEUADDR_REG Fault Event Upper Address Register This register specifies the interrupt message upper address B D F Type 0 0 0 GFXVTBAR Address Offset 44 47h Reset Value 0000_ 0000h Access RW Size 32 bits Reset RST Description Value PWR P Message upper address MUA Hardware implementations supporting Extended Interrupt Mode 31 0 RW 00000000h Uncore are required to implement this register Hardware implementations not supporting Extended Interrupt Mode may treat this field as RsvdZ 242 Datasheet Volume 2 Processor Configuration Registers intel 2 18 13 AFLOG_REG Adva
89. 00_0000_0000_0000h Access RW L Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RST Description Value PWR p n o o ena oo Queue Tail QT 18 4 RW L 0000h Uncore This field specifies the offset 128 bit aligned to the invalidation queue for the command that will be written next by software see nese o Datasheet Volume 2 249 Processor Configuration Registers intel 2 18 21 1I1QA_REG Invalidation Queue Address Register This register configures the base address and size of the invalidation queue This register is treated as RsvdZ by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 90 97h Reset Value 0000_0000_0000_0000h Access RW L Size 64 bits BIOS Optimal Default 0_0000_0000h Reset RST jee ew fic pk ee ee no on irene o Invalidation Queue Base Address IQA This field points to the base of 4 KB aligned invalidation request 38 12 RW L 0000000h Uncore queue Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Reads of this field return the value that was last programmed to it Fs o eea o Queue Size QS This field specifies the size of the invalidation request queue A 2 0 RW L Oh Uncore value of X in this field indicates an invalidation request queue of 2 X 4KB pages The number of entries in the invalidation queue i
90. 02h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P safe o pee o VCO Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control 1 RO V 1b U initialization It is set by default on Reset as well as whenever the oe corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link ope o e een Datasheet Volume 2 187 Processor Configuration Registers 2 12 DMI BAR Registers Table 2 14 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 14 DMIBAR Register Address Map Sheet 1 of 2 ae sat nee om on omver BN vraa anna Erana Capang ooon RO een omevccara BM Pon Ve capbiiyResiter o0oo oo0on f mo a A oran omvconca o veo resource Caoa 0000 000 mo OS A Liem omvanea BHT ve Resource capai 000 son mo Cam w fenas ooo f o zezan omvceRcae Dn vep Resource Copan 0000 000 mo om ow fen ooo f a e aam omvemRcAe BW Vem Resource copay 0000 son mo EE A Com ew fena i o e OS OC Peca
91. 0_7FFO_0000h 2 GB e ME base 00_7FFO_0000h 1 MB e ME Mask 00_7FFO_0000h e TOUUD 00_0000_0000h Disable Avoid access above 4 GB e TOLUD 00_7FEO_0000h 2 GB minus 1 MB e REMAPBASE 7F_FFFF_0000h default e REMAPLIMIT 00_0000_0000h 0 GB boundary default Datasheet Volume 2 29 m t 1 Processor Configuration Registers Case 2 Greater than 4 GB of Physical Memory Figure 2 6 Case 2 Greater than 4 GB of Physical Memory PHYSICAL MEMORY HOST SYSTEM VIEW DRAM CONTROLLER VIEW 512 GB High PCI Memory Add Range subtractively decoded to DMI i TOUUD BASE 1 MB aligned Reclaim Limit Reclaim Base x Main 1 MB aligned Memory Reclaim Reclaim BASE Add Range MESEG BASE 1 MB aligned 1 MB aligned Main memory OS visible Address gt 4GB Range Flash APIC Intel TXT PE FEC0_0000 20 MB oS inte TOLUD BASE PCI 1 MB aligned 1 MB aligned for reclaim Memory GFX Stolen Add Range 0 256 MB Subtractively GFX Stolen BASE RARE SRSM GFX GTT STOLEN GFX GTT Stolen BASE S 0 2 MB 1 MB aligned TSEG 0 8 MB TSEG BASE 1 MB aligned Main Memory os Add Range VISIBLE lt 4GB Legacy Add Range In this case the amount of memory remapped is the range between TOLUD and 4 GB This physical memory will be mapped to the logical address range defined between the REMAPBASE and the REMAPLIMIT registers Example 5 GB of P
92. 0h Access RW Size 64 bits BIOS Optimal Default 0000_0000_0000h Reset RST Description Value PWR P esf o o j pee o Protected High Memory Base PHMB This register specifies the base of protected high memory region 38 20 RW 00000h Uncore in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width pase wooed o Datasheet Volume 2 291 m t 1 Processor Configuration Registers 2 21 18 PHMLIMIT_REG Protected High Memory Limit Register This register sets up the limit address of DMA protected high memory region This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region limit depends on the number of reserved bits N 0 of this register Software may determine the value of N by writing all 1s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of the limit register are decoded by hardware as all 1s The protected high memory Base and Limit registers function as follows e Programming the protected low memory base and limit registers with the same value in bits HAW N 1 specifie
93. 1 O R R R R R R R Cow CAPPTR6 Capabilities Pointer 0 0 0 0 0 0 8 0 x h h h h h h h h h h h 00h Olh h Datasheet Volume 2 145 Processor Configuration Registers intel Table 2 12 PCI Device 6 Register Address Map Sheet 2 of 2 E oe BO B1h LCTL Link Control 0000h RO RW RW B4 B7h SLOTCAP Slot Capabilities 0004_0000h RW O RO B8 B9h SLOTCTL Slot Control 0000h Slot Status RO RO V 2 10 1 viD6 Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device B D F Type 0 6 0 PCI Address Offset 0 1h Reset Value Access Size Reset RST Description Value PWR p Vendor Identification VID uncore E standard identification for Intel sosen ucore 146 Datasheet Volume 2 Processor Configuration Registers 2 10 2 2 10 3 intel DI D6 Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type Address Offset Reset Value Access Size 0 6 0 PCI 2 3h 010Dh RO FW 16 bits nocet RaT Description Value PWR P Device Identification Number MSB DI D_ MSB 15 0 RO FW 010Dh Uncore Identifier assigned to the processor root port virtual PCI to PCI bridge PCI Express Graphics port PCI CMD6 PCI Command Register B D F Type Address Offset Reset Value
94. 1 Enable interrupt remapping hardware Hardware reports the status of the interrupt remapping enable operation through the IRES field in the Global Status register There may be active interrupt requests in the platform when software updates this field Hardware must enable or disable interrupt remapping logic only at deterministic transaction boundaries so that any in flight interrupts are either subject to remapping or not at all Hardware implementations must drain any in flight interrupt requests queued in the Root Complex before completing the interrupt remapping enable command and reflecting the status of the command through the IRES field in the Global Status register The value returned on a read of this field is undefined Set Interrupt Remap Table Pointer SIRTP This field is valid only for implementations supporting interrupt remapping Software sets this field to set update the interrupt remapping table pointer used by hardware The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address IRTA_REG register Hardware reports the status of the Set Interrupt Remap Table Pointer operation through the IRTPS field in the Global Status register The Set Interrupt Remap Table Pointer operation must be performed before enabling or re enabling after disabling interrupt remapping hardware through the IRE field After a Set Interrupt Remap Table Pointer operation software must globally in
95. 1 Secondary Bus Number ReGISter ccceceeeee eee eeeee eens eae ea teens 94 SUBUSN1 Subordinate Bus Number Register cseeee ener teeta eeaeeee aes 94 IOBASE1 I O Base Address Register csceeteeee cere eee ee teeta eee e eee e ta ene eas 95 IOLIMITI I O Limit Address Register cccecece cence eect eee eee ee eee teeta enna 95 SSTS1 Secondary Status Register cee ceeeee eee eee teeta teeta eee eaten 96 MBASE1 Memory Base Address ReGiStelr ecceeese ene eeeee ene ea tent eee ne enna 97 MLIMIT1 Memory Limit Address ReQiSter cceceseeee eee ee teeta teeta eee eee ees 98 PMBASE1 Prefetchable Memory Base Address RegiSter cceeeee eee ea ee 99 PMLIMIT1 Prefetchable Memory Limit Address Register seeene ee 100 PMBASEU1 Prefetchable Memory Base Address Upper REGISUGR iicctecintiiebintadieiaciasetataniasiatandina Pe nanle nies enkatadsnneitend tan eeesneeebaebe 101 PMLI MI TU1 Prefetchable Memory Limit Address Upper REGISUCM sciscecitsttadiniesnninn sans ietininkai Ei ER bias ta cabana KE Eii irinin iniaa Kia 102 CAPPTR1 Capabilities Pointer Register ssssssssrrirrrrrrrrssrrrrrrrrrrrrrrrrssn 102 INTRLINE1 Interrupt Line Register sssssssssssrisrrrerrrrrerrrrrsssrrrrrrrrrnns 103 INTRPIN1 Interrupt Pin Register ssssssssrrrsssrnrrrrrrrrsssrrrrrrrrrrnrrrrrrssee 103 BCTRL1 Bridge Control Register ssssssssrrssserrrrrrr
96. 11 Device 2 I O Register Address Map sssssssssrrrrssrrrrsserrnnnrrrrnsssrrrnarrrnnusuerrererrennn 144 2 12 PCI Device 6 Register Address Map sssssssssssssssrrrrssrrrnunrrrrusesrrrnnrrrrnnserrrrnerennn 145 2 13 PCI Device 6 Extended Configuration Register Address Map esscssscirrererreerrrrss 183 2 14 DMIBAR Register Address Map ssssssssssssrrsrrrrrrrstrrrtt nner ea 188 2 15 MCHBAR Registers in Memory Controller Channel 0 Register Address Map 207 2 16 MCHBAR Registers in Memory Controller Channel 1 Register Address Map 212 2 17 MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub 217 2 18 MCHBAR Registers in Memory Controller Common Register Address Map 218 2 19 Memory Controller MMIO Registers Broadcast Group Register Address Map 222 2 20 Integrated Graphics VT d Remapping Engine Register Address Map e0eeeeees 225 2 21 PCU MCHBAR Register Address Map cccecceee ete e eter e eee ne ee eee ene et eet ee tee ne ent e ne ne ented 260 2 22 PXPEPBAR Register Address Map cceecece ete etter ened 268 2 23 Default PEG DMI VT d Remapping Engine Register Address Map ceeseeeee eens 269 Datasheet Volume 2 9 intel Revision History Revision Daesctintion Revision Number P Date Updated DSTS Device Status Register B D F Type 0 1 0 PCI Added four registers to Section 2 13 MCHBAR Registers in Memory 002 Cont
97. 2 179 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset B8 B9h Reset Value 0000h Access RO Size a bits BIOS Optimal Default Reset RST js awe Gs Sie esermton Reserved for Attention Indicator Control AIC If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled directly by the 7 6 Uncore downstream port through implementation specific mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Reserved for Hot plug Interrupt Enable HPIE When set to 1b this bit enables generation of an interrupt on enabled hot plug events The Reset Value of this field is Ob If the Hot Plug Capable field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Reserved for Command Completed I nterrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot
98. 2 Configuration Registers Table 2 8 lists the registers arranged by address offset Register bit descriptions are in the sections following the table PCI Device 1 Function 0 2 Configuration Register Address Map Sheet 1 of 2 Address Register Reaistar Nana Reset Offset Symbol g Value VID1 Vendor Identification 8086h Ro Device Identification See PCICMD1 PCI Command 0000h RW RO 7h Pcistsi PC Status 0010h RWI RO h RID1 Revision Identification RO FW 8 2 3h 4 5h I 1 le 3 a SO a 1 oo oor Fon m 0 00h RW 0 F 0 p Oh h 1h Oh Oh Oh Oh Oh h 8h h Oh 1h h WwW RW RW 1Dh IOLIMIT1 I O Limit Address RW 1E 1Fh SSTSL Secondary Status 0000h RW1C RO 20 21h MBASE1 Memory Base Address FFFOh Ww Ww Ww Ww Ww 22 23h MLIMIT1 Memory Limit Address 0000h R R 24 25h PMBASE1 Prefetchable Memory Base Address FFF Ih RW RO 26 27h PMLIMIT1 Prefetchable Memory Limit Address 0001h RW RO 28 2Bh PMBASEU1 Prefetchable Memory Base Address Upper 0000_0000h R 34h Capabilities Pointer h Lee 0 0 Datasheet Volume 2 85 Processor Configuration Registers intel Table 2 8 PCI Device 1 Function 0 2 Configuration Register Address Map Sheet 2 of 2 Reset Value Address Register Offset Symbol BO Blh LCTL Link Control 0000h RW RO Link Status V B4 B7h SLOTCAP Slot Capabilities 0004_0000h RW O RO B8 B9h SLOTCTL Slot Control 0000h Sl
99. 2 GB is not supported Memory Base Address MBA FLR Set by the OS these bits correspond to address signals 38 22 gi Rw oooooh Uncore 4 MB combined for MMIO and Global GTT table aperture 2 MB for MMIO and 2 MB for GTT Address Mask ADM ana ro gence Hardwired to Os to indicate at least 4 MB address range Prefetchable Memory PREFMEM 3 Uncore fj Hardwired to 0 to prevent prefetching Memory Type MEMTYP 00 To indicate 32 bit base address 2 1 10b 01 Reserved 10 To indicate 64 bit base address 11 Reserved Memory 10 Space MI OS Uncore tag Hardwired to 0 to indicate memory space Datasheet Volume 2 Processor Configuration Registers 2 8 11 intel GMADR Graphics Memory Range Address Register GMADR is the PCI aperture used by software to access tiled GFX surfaces in a linear fashion B D F Type 0 2 0 PCI Address Offset 18 1Fh Reset Value 0000_0000_0000_000Ch Access RO RW L RW Size 64 bits peser RST Description Value PWR P FLR Reserved for Memory Base Address RSVDRW 63 39 RW 0000000h 4 62 39 Aw o0000000 Fee Must be set to 0 since addressing above 512 GB is not supported 00000000 FLR Memory Base Address MBA 38 29 RW 00b Uncore Memory Base Address MBA Set by the OS these bits correspond to address signals 38 29 512 MB Address Mask ADMSK512 28 RW L This Bit is either part of the Memory Base Address RW or part of the Address Mask RO dependin
100. 4 Programmable Attribute Map 4 Register This register controls the read write and shadowing attributes of the BIOS range from D8000h to DFFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0O the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 84h Reset Value 00h Access RW Size a w BIOS Optimal Default Reset RST Description Value PWR p mefe j o j pee o ODC000 ODFFFF Attribute HI ENABLE This field controls the steering of read and write cycles t
101. 5 10 intel PXPEPBAR PCI Express Egress Port Base Address Register This is the base address for the PCI Express Egress Port MMIO Configuration space There is no physical memory within this 4 KB window that can be addressed The 4 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the EGRESS port MMIO configuration space is disabled and must be enabled by writing a 1 to PXPEPBAREN Device 0 offset 40h bit 0 All the bits in this register are locked in Intel TXT mode B D F Type 0 0 0 PCI Address Offset 40 47h Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 0_0000_0000h Reset RST Description Value PWR B s o o pena oO PCI Express Egress Port MMI O Base Address PXPEPBAR This field corresponds to bits 38 12 of the base address PCI Express Egress Port MMIO configuration space BIOS will program this register resulting in a base address for a 4 KB block of 38 12 0000000h Uncore contiguous memory address space This register ensures that a naturally aligned 4 KB space is allocated within the first 512 GB of addressable memory space System Software uses this base address to program the PCI Express Egress Port MMIO register set All the bits in this register are locked in Intel TXT mode mafe oa ema ooo PXPEPBAR Enable PXPEPBAREN 0 Disabled PXPEPBAR is disabled and does not claim any RW Uncore Kemo 1 Enabled PXPEPBAR
102. 6 RW O 00h Uncore targeted by this link entry ee l o l BIOS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS pase oo oe Reeves CS Link Type TXTYP This bit indicates that the link points to memory mapped space for 1 Uncore RCRB The link address specifies the 64 bit base address of the target RCRB Link Valid LV RW O Uncore 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 2 12 18 DMILE2A DMI Link Entry 2 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 68 6Bh Reset Value 0000_0000h Access RW O Size 32 bits BIOS Optimal Default 000h Reset RST Description Value PWR P Link Address LA 31 12 RW O 00000h Uncore Memory mapped base address of the RCRB that is the target element Egress Port for this link entry mofe o eea 200 Datasheet Volume 2 Processor Configuration Registers 2 12 19 LCAP Link Capabilities Register This register indicates DMI specific capabilities B D F Type 0 0 0 DMIBAR Address Offset 84 87h Reset Value 0001_2C41h Access RW O RO RW OV Size 32 bits BIOS Optimal Default 00002h Reset RST Description Value PWR P aafe o j pee o L1 Exit Latency LISELAT This field in
103. 8 18 The Integrated Graphics Device has no requirement for the settings of Latency Timers B D F Type Address Offset Reset Value 0 2 0 PCI 3Fh 00h Access RO Size 8 bits Reset RST Poa GRCEJEIT Maximum Latency Value MLV 7 0 00h Uncore The IGD has no specific requirements for how often it needs to access the PCI bus 142 Datasheet Volume 2 Processor Configuration Registers intel 2 8 19 MSAC Multi Size Aperture Control Register This register determines the size of the graphics memory aperture in function 0 and in the trusted space Only the system BIOS will write this register based on pre boot address allocation efforts however the graphics may read this register to determine the correct aperture size System BIOS needs to save this value on boot so that it can reset it correctly during S3 resume Note This register is Intel TXT locked and becomes read only when the trusted environment is launched B D F Type 0 2 0 PCI Address Offset 62h Reset Value 02h Access RW RW K Size 4 pe BIOS Optimal Default Reset RST a O e e oa pea Untrusted Aperture Size High LHSASH This field is used in conjunction with LHSASL The description below is for both fields LHSASH and LHSASL 2 RW K Uncors 11b Bits 28 27 of BMPR are RO allowing 512 MB of GMADR 10b Illegal Programming 01b Bit 28 of GMADR is RW but bit 27 of GMADR is RO allowing 256 MB of GMADR 00b Bits 28 27
104. 9 PBUSN6 Primary Bus Number RegiSter cceceeeecee entree eee ee eae nett eae 152 2 10 10 SBUSN6 Secondary Bus Number ReGiSter ccc cece cece nett nett eee e eens 153 2 10 11 SUBUSN6 Subordinate Bus Number Register cceeeeseeeee eee ener a ees 153 2 10 12 IOBASE6 I O Base Address Register ceccececeee erent eee ne ee tee tae eaeeaeaes 154 2 10 13 IOLIMIT6 I O Limit Address Register cece ete ee eee ee eee ee eee ee eee eee ne es 154 2 10 14 SSTS6 Secondary Status Register cece cece teen ee eee eee e eee ee eae 155 2 10 15 MBASE6 Memory Base Address ReGiSter ccee tect eee ee ene ee teeta ena eeee eae 156 2 10 16 MLIMIT6 Memory Limit Address ReQiSter c cect cece tent eee neta teat eee eee 157 2 10 17 PMBASE6 Prefetchable Memory Base Address Register eeeee eens 158 2 10 18 PMLIMIT6 Prefetchable Memory Limit Address Register ccce 159 2 10 19 PMBASEU6 Prefetchable Memory Base Address Upper Register 160 2 10 20 PMLIMITU6 Prefetchable Memory Limit Address Upper Register 161 2 10 21 CAPPTR6 Capabilities Pointer Register ccc eeeeete nett teen teeta eats 161 2 10 22 INTRLINE6 Interrupt Line Register cece ete eee eee ee eee ee eae ee teeta 162 2 10 23 INTRPIN6 Interrupt Pin ReGiSter ccc eee ee ete ee eee eet ee ener e eee ee eae 162 2 10 24 BCTRL6 Bridge Control Register cece
105. ADDR_REG Fault Event Upper Address Register This register specifies the interrupt message upper address B D F Type 0 0 0 VCOPREMAP Address Offset 44 47h Reset Value 0000_0000h Access RW Size 32 bits qe e Message upper address MUA Hardware implementations supporting Extended Interrupt Mode 31 0 RW 0000_0000h Uncore are required to implement this register Hardware implementations not supporting Extended Interrupt Mode may treat this field as RsvdZ 286 Datasheet Volume 2 Processor Configuration Registers 2 21 13 AFLOG_REG Advanced intel Fault Log Register This register specifies the base address of the memory resident fault log region This register is treated as RsvdZ for implementations not supporting advanced translation fault logging AFL field reported as 0 in the Capability register B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 58 5Fh RO 64 bits 000h 0 0 0 VCOPREMAP 0000_0000_0000_0000h Reset RST ORQJ 0_0000_00 60 0000h Uncore E D eefe f ofe o e eea Datasheet Volume 2 Fault Log Address FLA This field specifies the base of 4 KB aligned fault log region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Software specifies the base address and size of the fault log region through this register and programs it in hardware through the SFL field in th
106. BAR MC1 Address Offset 4428 442Bh Reset Value 0000_ 0000h Access RW L Size 32 bits Reset RST Description Value PWR p aofo o ee o sa w o fro eneon iaa awe o fro atene nan ops Cra owe o f frontene Rank eprom o ee o E froenn UUE Datasheet Volume 2 213 t i Processor Configuration Registers 2 14 4 TC_SRFTP_C1 Self Refresh Timing Parameters Register This register provides Self refresh timing parameters B D F Type 0 0 0 MCHBAR MC1 Address Offset 46A4 46A7h Reset Value 0000_BO00h Access RW L Size 32 bits Reset RST jee ew fic pk ee sme xe ese Delay From SR Exit to First DDR Command 15 12 RW L Bh tXS tRFC 10ns Setup of tXS_offset is of cycles for 10 ns Range is between 3 and 11 DCLK cycles pare eo eee 2 14 5 PM_PDWN_Config_C1 Power down Configuration Register This register defines the power down CKE off operation power down mode idle timer and global per rank decision B D F Type 0 0 0 MCHBAR MC1 Address Offset 44B0 44B3h Default Value 0000_ 0000h Access RW L Size 32 bits BI OS Optimal Default 00000h Reset RST Description Value PWR aaf e a resent o Global power down GLPDN 12 RW L Uncore 1 Power down decision is global for channel 0 A separate decision is taken for each rank Power down mode PDWN_ mode Selects the mode of power down All encodings not in table are reserved Note When selecting DL
107. CTL_REG Fault Event Control Register 0 00 241 2 18 10 FEDATA_REG Fault Event Data Register eerie eee ee 242 2 18 11 FEADDR_REG Fault Event Address Register es ssssrererrrrrrrrrerrrsrrrerre 242 2 18 12 FEUADDR_REG Fault Event Upper Address Register c cceeeeee eee ees 242 2 18 13 AFLOG_REG Advanced Fault Log ReQiSter cccceeeeee nent eens eee ee ee ee es 243 2 18 14 PMEN_REG Protected Memory Enable Register cceeeeeeee eee e eee ene 244 2 18 15 PLMBASE_ REG Protected Low Memory Base Register eeeee eee 245 2 18 16 PLMLIMIT_REG Protected Low Memory Limit Register cece ee 246 2 18 17 PHMBASE_REG Protected High Memory Base Register eeeeeeees 247 2 18 18 PHMLIMIT_REG Protected High Memory Limit Register cc eeeeee 248 2 18 19 IQH_REG Invalidation Queue Head Register cccece cece teen eee eee eens 249 2 18 20 IQT_REG Invalidation Queue Tail Register cc cececeee eset eee e eae ee eae 249 2 18 21 IQA REG Invalidation Queue Address ReGiSter ccs ceeeeeeee eee e ee ee ea ees 250 2 18 22 ICS REG Invalidation Completion Status Register ccceceeeee entree ees 250 2 18 23 ECTL_REG Invalidation Event Control Register eee 251 2 18 24 EDATA_REG Invalidation Event Data Register cece 252 2 18 25 EUADDR_REG Invalidation Event Upper Address Register 0
108. DBW DIMM B width of DDR chips 0 X8 chips 1 X16 chips DIMM A DDR width DAW DIMM A width of DDR chips 0 X8 chips 1 X16 chips DIMM B number of ranks DBNOR 0 Single rank 1 Dual rank DIMM A number of ranks DANOR Single rank Dual rank DIMM A select DAS Selects which of the DIMMs is DIMM A should be the larger Uncore DIMM 0 DIMMO 1 DIMM1 ncore Size of DIMM B DIMM_B_ Size Size of DIMM B in 256 MB multiples ncore Size of DIMM A DIMM_A_ Size Size of DIMM A in 256 MB multiples 23 22 21 20 19 18 17 16 15 8 7 0 Datasheet Volume 2 Processor Configuration Registers intel 2 16 4 PM_SREF_config Self Refresh Configuration Register This self refresh mode control register defines if and when DDR can go into SR B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5060 5063h Reset Value 0001_O0FFh Access RW L Size 32 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P gis Ro on f Reserved CC Self refresh Enable This control bit is an INTEL RESERVED register It is for test and debug purposes only This bit enables or disables self refresh mechanism Uncore Idle timer init value Idle_timer This value is used when the SREF_enable field is set It defines 15 0 RW L OOFFh Uncore the of cycles that there should not be any transaction to enter self refresh It is programmable 1 to 64K 1 In DCLK 800 it determines time
109. E Controls the Root Complex s response to fatal errors 0 No SERR generated on receipt of fatal error 1 Indicates that an SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated 2 RW Uncore with this Root Port or by the Root Port itself OE o eea Datasheet Volume 2 Processor Configuration Registers n t 2 11 PCI Device 6 Extended Configuration Registers Table 2 13 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 13 PCI Device 6 Extended Configuration Register Address Map Address Register 5 a i seit Peostername Restate access 0 104 107h PVCCAP1 Port VC Capability Register 1 0000_0000h 0 2 11 1 e PVCCAP1 Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 6 0 MMR Address Offset 104 107h Reset Value 0000_ 0000h Access RO Size 32 bits BIOS Optimal Default 0000000h Reset RST boos ORES afe o ea Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in 000b Uncore addition to the default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other VC resources in a Strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration a Exte
110. Enable bits in the BCTRL register of Device 1 Function 1 to control the routing of processor initiated transactions targeting MDA compatible O and memory address ranges This bit should not be set if Device 1 Function 1 VGA Enable bit is not set If Device 1 Function 1 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 1 Function 1 if the address is within the corresponding OBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h 0B7FFFh 1 0 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode 1 RW Uncore Any I O reference that includes the I O locations listed above or their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 All References to MDA and VGA space are not claimed by Device 1 Function 1 Illegal combination All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 1 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 1 MDA references are not claimed by Device 1 Function 1 VGA and MDA memory cycles can only be route
111. F Type Address Offset Reset Value Access Size BIOS Optimal Default Datasheet Volume 2 RWS V 000b 0 1 0 2 PCI D0 D1h 0002h RWS RWS V T bits Reserved Compliance De emphasis ComplianceDeemphasis This bit sets the de emphasis level in Polling Compliance state if the entry occurred due to the Enter Compliance bit being 1b 1 3 5 dB 0 6 dB When the Link is operating at 2 5 GT s the setting of this bit has no effect Components that support only 2 5 GT s speed are permitted to hardwire this bit to Ob For a Multi Function device associated with an Upstream Port the bit in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is of type RsvdP This bit is intended for debug compliance testing purposes System firmware and software is allowed to modify this bit only during debug or compliance testing Powerg Compliance SOS compsos When set to 1b the TXTSSM is required to send SKP Ordered Sets periodically in between the modified compliance patterns For a Multi Function device associated with an Upstream Port the bit in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this bit is of type RsvdP The Reset Value of this bit is Ob Components that support only the 2 5 GT s speed are permitted to hardwire this field to Ob Enter Mod
112. F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 0 0 PCI 6 7h 0090h RO RW1C 16 bits 00h Reset RST ead OQUE 15 RW1C Detected Parity Error DPE l This bit is set when this Device receives a Poisoned TLP Signaled System Error SSE This bit is set to 1 when Device 0 generates an SERR message over DMI for any enabled Device 0 error condition Device 0 error Uncore conditions are enabled in the PCICMD ERRCMD and DMIUEMSK registers Device 0 error flags are read reset from the PCISTS ERRSTS or DMIUEST registers Software clears this bit by writing altoit Received Master Abort Status RMAS This bit is set when the processor generates a DMI request that receives an Unsupported Request completion packet Software clears this bit by writing a 1 to it Uncore Received Target Abort Status RTAS This bit is set when the processor generates a DMI request that receives a Completer Abort completion packet Software clears this bit by writing a 1 to it Uncore Signaled Target Abort Status STAS The processor will not generate a Target Abort DMI completion packet or Special Cycle This bit is not implemented and is hardwired to a 0 Writes to this bit position have no effect Uncore Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 0 0 PCI Address Offset 6 7h Reset Value 0090h Access RO RW1C Size 16 bits BIOS Optimal Default 00
113. FFFh in size and is always mapped to the main memory controlled by the MCH 18 Datasheet Volume 2 Processor Configuration Registers Py t 2 3 1 2 Legacy Video Area A_0000h B_ FFFFh The legacy 128 KB VGA memory range frame buffer 000A_0000h 000B_FFFFh can be mapped to IGD Device 2 to PCI Express Device 1 or Device 6 and or to the DMI Interface The appropriate mapping depends on which devices are enabled and the programming of the VGA steering bits Based on the VGA steering bits priority for VGA mapping is constant The processor always decodes internally mapped devices first Non SMM mode processor accesses to this range are considered to be to the Video Buffer Area as described above The processor always positively decodes internally mapped devices namely the IGD and PCI Express Subsequent decoding of regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA configuration bits VGA Enable and MDAP This region is also the default for SMM space Compatible SMRAM Address Range A_0000h B_ FFFFh When compatible SMM space is enabled SMM mode processor accesses to this range route to physical system DRAM at 000A_0000h 000B_FFFFh PCI Express and DMI originated cycles to enable SMM space are not allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the VGA device DMI initiated write cycles are attempted as peer write cycles to a VGA enabled PCle port Monoch
114. I bridge The status of SERRs generated is reported in the PCISTS register o e o pee Parity Error Response Enable PERRE This bit controls whether or not the Master Data Parity Error bit in RW core the PCI Status register can bet set l 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set 5 Uncore VGA Palette Snoop VGAPS Not Applicable or Implemented Hardwired to 0 Rcore Memory Write and Invalidate Enable MWI E Not Applicable or Implemented Hardwired to 0 Special Cycle Enable SCE pa re f o foe Not Applicable or Implemented Hardwired to 0 88 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 1 0 2 PCI Address Offset 4 5h Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 00h Reset RST ane js fae Ss Se esermon Bus Master Enable BME This bit controls the ability of the PEG port to forward Memory Read Write Requests in the upstream direction 0 This device is prevented from making memory requests to its primary bus Note that according to PCI Specification as MSI interrupt messages are in band memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary 2 RW Uncore bus to its primary bus Upstream memory writes reads peer writes reads and MSIs will all be treated
115. INTCON Used to communicate interrupt line routing information 7 0 RW 00h Uncore BIOS Requirement POST software writes the routing information into this register as it initializes and configures the system The value indicates to which input of the system interrupt controller this device s interrupt pin is connected 2 6 23 INTRPIN1 I nterrupt Pin Register This register specifies which interrupt pin this device uses B D F Type Address Offset Reset Value 0 1 0 2 PCI 3Dh olh Access RW O RO Size 8 bits Reset RST Description Value PWR P Interrupt Pin I NTPI N As a multifunction device the PCI Express device may specify any INTx x A B C D as its interrupt pin The Interrupt Pin register tells which interrupt pin the device or device function uses 1h Corresponds to INTA Default 2h Corresponds to INTB a0 oe thi oncore 3h Corresponds to INTC 4h Corresponds to INTD 05h FFh Reserved Devices or device functions that do not use an interrupt pin must put a 0 in this register This register is write once BIOS must set this register to select the INTx to be used by this root port Datasheet Volume 2 103 Processor Configuration Registers intel 2 6 24 BCTRL1 Bridge Control Register This register provides extensions to the PCICMD register that are specific to PCI to PCl bridges BCTRL1 provides additional control for the secondary interface that is PCI Express G as well
116. IOS Optimal Default 00000h Reset RST Description Value PWR P Virtual Channel private Enable VCPE 0 Virtual Channel is disabled 1 Virtual Channel is enabled See exceptions below Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete When VC Negotiation Pending bit is cleared a 1 read from this VC Enable bit indicates that the VC is enabled Flow Control Initialization is completed for the PCI Express port A 0 read from this bit indicates that the Virtual Channel is currently disabled 31 RW Uncore BIOS Requirement To enable a Virtual Channel the VC Enable bits for that Virtual Channel must be set in both Components on a Link To disable a Virtual Channel the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link Software must ensure that no traffic is using a Virtual Channel at the time it is disabled Software must fully disable a Virtual Channel in both Components on a Link before re enabling the Virtual Channel pare eae SS Virtual Channel private ID VCPI D 26 24 RW 010b Uncore Assigns a VC ID to the VC resource This field can not be modified when the VC is already enabled pase no om Reeves CS 7 Ro Uncore Traffic Class m Virtual Channel private Map TCMVCPM Traffic Class Virtual Channel private Map TCVCPM It is recommended that private TC6 01000000b is the only value that should be programmed into
117. Intel Xeon Processor E3 1200 Family Datasheet Volume 2 This is Volume 2 of 2 June 2011 Document Number 324971 002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining critical control or safety systems or in nuclear facility applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on requ
118. Invalidate Address register and the domain id must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the IVT field At this time the granularity at which actual invalidation was performed is reported through the IAIG field me nese Datasheet Volume 2 255 256 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 108 10Fh Reset Value 0200_0000_0000_0000h Access RW V RW RO V Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RST ae js awe Gs Sie esermton IOTLB Actual I nvalidation Granularity 1 Al G Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion by clearing the IVT field The following are the encodings for this field 00 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page selective invalidation requests 58 57 RO V 1h Uncore Global Invalidation performed This could be in response to a global domain selective or page selective invalidation request Domain selective invalidation performed using the domain
119. L This field will allow the double self refresh enable disable 00b Double refresh rate when DRAM is WARM HOT 01b Force double self refresh regardless of temperature 10b Disable double self refresh regardless of temperature 11b Reserved Refresh panic WM Refresh_panic_wm 9h Uncore tREFI count level in which the refresh priority is panic default is 9 It is recommended to set the panic WM at least to 9 in order to use the maximum no refresh period possible Refresh high priority WM Refresh_HP_W M 8h Uncore tREFI count level that turns the refresh priority to high default is 8 Rank idle timer for opportunistic refresh OREF_RI OFh Uncore Rank idle period that defines an opportunity for refresh in DCLK cycles Uncore 2 14 9 TC_RFTP_C1 Refresh Timing Parameters Register B D F Type 0 0 0 MCHBAR MC1 Address Offset 4698 469Bh Default Value 46B4_1004h Access RW L Size 32 bits Reset RST Description Value PWR p 9 tREFI tREFIx9 Uncore Period of minimum between 9 tREFI and tRAS maximum normally 70 us in 1024 DCLK cycles default is 35 need to reduce 100 DCLK cycles uncertainty on timing of panic refresh Refresh execution time tRFC OB4h Uncore Time of refresh from beginning of refresh until next ACT or refresh is allowed in DCLK cycles default is 180 tREFI period in DCLK cycles tREFI This field defines the average period between refreshes and the 1004h U meors ra
120. L off or APD DLL off DIMM MRO register bit 12 PPD must equal 0 Note When selecting APD PPD or APD PPD DIMM MRO register bit 12 PPD must equal 1 11 8 RW L Oh Uncore The value Oh no power down is a don t care Oh No Power Down 1h APD 2h PPD 3h APD PPD 6h DLL Off 7h APD DLL Off Power down idle timer PDWN_idle_ counter 7 0 RW L 00h Uncore This defines the rank idle period in DCLK cycles that causes power down entrance 214 Datasheet Volume 2 Processor Configuration Registers intel 2 14 6 ECCERRLOGO_C1 ECC Error Log 0 Register B D F Type 0 0 0 MCHBAR MC1 Address Offset 44C8 44CBh Reset Value 0000_0000h Access ROS V Size 32 bits BIOS Optimal Default 0000h Reset RST D ipti Value PWR escription p Error Bank ERRBANK 31 29 ROS V 000b aa This field holds the Bank Address of the read transaction that had the ECC error p Error Rank ERRRANK 28 27 ROS V LAF This field holds the Rank ID of the read transaction that had the ECC error 2 Powerg Error Chunk ERRCHUNK 26 24 ROS 0005 Holds the chunk number of the error stored in the register p Error Syndrome ERRSYND 23 16 ROS V 00h prt This field contains the error syndrome A value of FFh indicates that the error is due to poisoning safe o j pee o Uncorrectable Error Status MERRSTS This bit is set when an uncorrectable multiple bit error occurs on a P memory read data transfer When this bit is set the
121. LOTCAP Slot Capabilities Register cece cette rete eee ee teeta eae 177 2 10 41 SLOTCTL Slot Control Register cccceete eee ee eset eee nents teeta e ee eee tae 179 2 10 42 SLOTSTS Slot Status ReGiSter ccccceeee te eee eee ee eee eee eens teen neta te 181 2 10 43 RCTL Root Control Register cceceeee eee te eee eee eee eee teers 182 PCI Device 6 Extended Configuration Registers ccececeete eee ee eee ee ee eee e eae ee teens 183 2 11 1 PVCCAP1 Port VC Capability Register 1 0 0 eect eee eerie 183 2 11 2 PVCCAP2 Port VC Capability Register 2 cece eee e eter eee eee eee eee 184 2 11 3 PVCCTL Port VC Control ReQiSter cccceceee eee eee ee eee ee eee teen eee e eas 184 2 11 4 VCORCAP VCO Resource Capability Register cc ceeeeee teeter nee 185 2 11 5 VCORCTL VCO Resource Control Register ceceeee cent eee eee teen teen eee 186 2 11 6 VCORSTS VCO Resource Status ReGISter cect eee ee teen e teeta eee ee eae 187 DMIBAR Registers inserieren a a A NEES tio amen ie PIEUSE NENEN dates 188 2 12 1 DMIVCECH DMI Virtual Channel Enhanced Capability Register 189 2 12 2 DMIPVCCAP1 DMI Port VC Capability Register 1 eee ee eee ee eee 190 2 12 3 DMIPVCCAP2 DMI Port VC Capability Register 2 cece e eee ee eee eee 190 2 12 4 DMIPVCCTL DMI Port VC Control Register ccecceee eee ee eee ee eee e ee eae ees 191
122. Logical Address Memory Remap range e When TOM is equal to TOLUD remap is not needed and must be disabled by programming REMAPBASE to a value greater than the value in the REMAPLI MIT register Interaction with other Overlapping Address Space The following Memory Mapped IO address spaces are all logically addressed below 4 GB where they do not overlap the logical address of the re mapped memory region GFXGTTstolen At TOLUD GFXstolensize to TOLUD GFXstolen At TOLUD GFXstolensize GFXGTTstolensize to TOLUD GF Xstolensize TSEG At TOLUD GFXstolensize GFXGTTstolensize TSEGSIZE to TOLUD GFXGTTstolensize GFXstolensize High BIOS Reset vector just under 4GB boundary Positive decode to DMI occurs XAPIC At fixed address below 4 GB Local APIC At fixed address below 4 GB MSI Interrupts At fixed address below 4 GB GMADR 64 bit BARs GTTMMADR 64 bit BARS MBASE MLI MIT PXPEPBAR 39 bit BAR DMIBAR 39 bit BAR MCHBAR 39 bit BAR TMBAR 64 bit BAR PMBASE PMLIMIT 64 bit BAR using Upper PMBASE PMLI MIT CHAPADR 64 bit BAR GFXVTBAR 39 bit BARs VTDPVCOBAR 39 bit BARs Datasheet Volume 2 31 m t 1 Processor Configuration Registers Note Note 2 3 5 32 Implementation Notes e Remap applies to transactions from all interfaces All upstream PEG DMI transactions that are snooped get remapped e Upstream PEG DMI transactions that are not snooped Snoop not required attribute set get remapp
123. MRL sensor if it is Uncore implemented 0 MRL Closed 1 MRL Open Reserved for Command Completed CC If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register this bit is set when a hot plug command has completed and the Hot Plug Controller is ready to accept a subsequent command The Command Completed status bit is set as an indication to host software that the Hot Plug Controller has processed the previous command and is ready to receive the next command it provides no guarantee that the action corresponding to the command is complete If Command Completed notification is not supported this bit must be hardwired to Ob Uncore 122 Datasheet Volume 2 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default intel 0 1 0 2 PCI BA BBh 0000h RO RO V RW1C 16 bits 00h Reset RST ane je fae Ses She sermon Datasheet Volume 2 Presence Detect Changed PDC A pulse indication that the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is changed Reserved for MRL Sensor Changed MSC If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Reserved for Power Fault Detected PFD If a Power Controller
124. PCI Express link B D F Type 0 0 0 DMI BAR Address Offset 88 89h Reset Value 0000h Access RW RW V Size 16 bits BIOS Optimal Default 000h Reset RST Description Value PWR Cc res Autonomous Width Disable HAWD When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link RW Uncore operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob o e o eea o Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state 7 RW Uncore This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns ope o pee o Retrain Link RL 0 Normal operation 23 1 Full Link retraining is initiated by directing the Physical Layer 3 RWV Uncore TXTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no need to write a 0 a o o peen o Active State PM ASPM This field controls the level of active state power management supported on the given link 1 0 RW Uncore
125. PE 15 Uncore Since the IGD does not detect parity this bit is always hardwired to 0 14 Uncore Signaled System Error SSE eer l The IGD never asserts SERR therefore this bit is hardwired to 0 Received Master Abort Status RMAS 13 Uncore The IGD never gets a Master Abort therefore this bit is hardwired to 0 Received Target Abort Status RTAS 12 Uncore The IGD never gets a Target Abort therefore this bit is hardwired to 0 11 ncore Signaled Target Abort Status STAS Hardwired to 0 The IGD does not use target abort semantics i DEVSEL Timing DEVT aos ro oop f unore Not applicable These bits are hardwired to 00 Master Data Parity Error Detected DPD Uncore Since Parity Error Response is hardwired to disabled and the IGD does not do any parity detection this bit is hardwired to 0 Fast Back to Back FB2B 7 1b Uncore Hardwired to 1 The IGD accepts fast back to back when the transactions are not to the same agent ijncore User Defined Format UDF Hardwired to 0 5 ncare 66 MHz PCI Capable C66 Not applicable Hardwired to 0 Capability List CLI ST 4 1b Uncore This bit is set to 1 to indicate that the register at 34h provides an offset into the function s PCI Configuration Space containing a pointer to the location of the first item in the list Interrupt Status INTSTS This bit reflects the state of the interrupt in the device Only when 3 RO V Uncore the Interrupt Disable bit in
126. PF field is Set Powerg The FRI field indicates the index from base of the fault recording 15 8 ROS V 00h ood register to which the first pending fault was recorded when the PPF field was Set by hardware The value read from this field is undefined when the PPF field is clear o e oa ea Invalidation Time out Error ITE Hardware detected a Device IOTLB invalidation completion time core out At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting device Device IOTLBs implement this bit as RsvdZ Invalidation Completion Error ICE Hardware received an unexpected or invalid Device OTLB invalidation completion This could be due to either an invalid ITag 5 Uncore 2 invalid source id in an invalidation completion response At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not supporting Device OTLBs implement this bit as reserved Invalidation Queue Error I QE Hardware detected an error associated with the invalidation queue This could be due to either a hardware error while fetching a P descriptor from the invalidation queue or hardware detecting an RWICS a erroneous or invalid descriptor in the invalidation queue At this time a fault event may be generated based on the programming of the Fault Event Control register Hardware implementations not support
127. Parameters 0000_B000h faoeewocm sve Rmeved TY faaoo esarn A Reeves Fa E 2 13 1 TC_DBP_CO Timing of DDR Bin Parameters Register This register defines the BIN timing parameters for safe logic tRCD tRP and tCL B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 4000 4003h Reset Value 0000_0666h Access RW L Size 32 bits Reset RST Description Value PWR j 31 12 Ro on f Reserved Cis CAS Command Delay to Data Out of DDR Pins tCL This field provides the delay from CAS command to data out of DDR pins Range is 5 12 Notes 1 This does not define the sample point in the I O This is defined by training in round trip register and other registers because this is also affected by board delays PRE to ACT Same Bank Delay tRP 7 4 RW L 6h a pom Range SF dees cycles 3 0 RW L 6h ACT to CAS RD or WR Same Bank Delay tRCD Range is 4 15 Datasheet Volume 2 207 Processor Configuration Registers intel 2 13 2 TC_RAP_CO Timing of DDR Regular Access Parameters Register This register provides the regular timing parameters in DCLK cycles B D F Type 0 0 0 MCHBAR MCO Address Offset 4004 4007h Reset Value 0010_4044h Access RW L Size 32 bits Reset RST sjsj ee saf e m pema ooo Four Activate Window 23 16 RW L 10h This field provides the timeframe in which maximum of 4 ACT commands to the same rank are allowed The miniumum value is 4 tRRD the maximum va
128. RAM below TOLUD BIOS will calculate and program this register so the system agent has knowledge of where TOLUD Gfx stolen Gfx GTT stolen TSEG is located I O blocks use this minus DPR for upstream DRAM decode Datasheet Volume 2 Processor Configuration Registers 2 3 4 1 Memory Re claim Background The following are examples of Memory Mapped IO devices that are typically located below 4 GB e High BIOS TSEG e GFX stolen e GTT stolen e XAPIC e Local APIC e MSI Interrupts e Mbase Mlimit e Pmbase PMlimit e Memory Mapped IO space that supports only 32B addressing The processor provides the capability to re claim the physical memory overlapped by the Memory Mapped IO logical address space The processor re maps physical memory from the Top of Low Memory TOLUD boundary up to the 4 GB boundary to an equivalent sized logical address range located just below the Manageability Engine s stolen memory 2 3 4 2 Indirect Accesses to MCHBAR Registers This access is similar to prior chipsets MCHBAR registers can be indirectly accessed using e Direct MCHBAR access decode 1 Cycle to memory from processor 2 Hits MCHBAR base AND 3 MCHBAR is enabled AND 4 Within MMIO space above and below 4 GB e GTTMMADR 10000h 13FFFh range gt MCHBAR decode 1 Cycle to memory from processor AND Device 2 IGD is enabled AND Memory accesses for device 2 is enabled AND Targets GFX MMIO Function 0 AND MCHBAR is enable
129. Registers siia uson r bend aa E EE EEEE E OSEE am neues 268 2 20 1 EPVCORCTL EP VC O Resource Control Register cceeeeeee eects teeta eee 268 Default PEG DMI VT d Remapping Engine RegisterS sssssssssssssrrrsrrrrrrrrrrrrrrrrrrrsns 269 2 21 1 VER_REG Version Register sarserrrerrrierrrrinirrsrinsrineeririnnsiusrindsnrieenss 270 2 21 2 CAP_REG Capability Register ccccecee cece eee eee ee eee eee ee eee nena teenie 271 2 21 3 ECAP_REG Extended Capability Register cccceeeeee eee ne eee e teen eens 274 2 21 4 GCMD_REG Global Command ReGister eee 275 2 21 5 GSTS REG Global Status Register teenie 279 2 21 6 RTADDR_REG Root Entry Table Address Register c eceeeeeeneee eee ee es 280 2 21 7 CCMD_REG Context Command Register ccc eee e eee eee eee eae 281 2 21 8 FSTS_REG Fault Status Register cccceccccscerercesesseeetenenenteeceseneeaears 283 2 21 9 FECTL_REG Fault Event Control Register 0 0 0 eee eee 285 2 21 10 FEDATA_REG Fault Event Data Register eterna 286 2 21 11 FEADDR_REG Fault Event Address Register c ccc eee eee enna 286 2 21 12 FEUADDR_REG Fault Event Upper Address Register c cceeeeee ee en ees 286 2 21 13 AFLOG_REG Advanced Fault Log ReQiSter cciceeeee cent eens eee eee ee tees 287 2 21 14 PMEN_REG Protected Memory Enable Register cceeeeeee enter eee ea eee 288 2 21 15 PLMBASE_REG P
130. Reset Value 0000_0000_0000_0000h Access RW L Size 64 bits BIOS Optimal Default 0000_ 0000h Reset RST Description Value PWR p ssf o o peen o Interrupt Remapping Table Address IRTA This field points to the base of 4KB aligned interrupt remapping table 38 12 RWL 0900090 Uncang Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Reads of this field returns value that was last programmed to it Extended Interrupt Mode Enable EI ME This field is used by hardware on Intel 64 platforms as follows 0 xAPIC mode is active Hardware interprets only low 8 bits of Destination D field in the IRTEs The high 24 bits of the Destination D field are treated as reserved 11 RW L Un ore 1 x2APIC mode is active Hardware interprets all 32 bits of Destination ID field in the IRTEs This field is implemented as RsvdZ on implementations reporting Extended Interrupt Mode EIM field as Clear in Extended Capability register moa mo aero Size S J This field specifies the size of the interrupt remapping table The ae ae oh Uncore number of entries in the interrupt remapping table is 2 X 1 where X is the value programmed in this field Datasheet Volume 2 297 Processor Configuration Registers intel 2 21 28 IWVA_REG Invalidate Address Register This register provides the DMA address whose corresponding IOTLB entry needs to be invalidated through the corresponding O
131. S RO V oh Wacore This field indicates the status of protected memory region s 0 Protected memory region s disabled L Protected memory region s enabled Datasheet Volume 2 Processor Configuration Registers E t 2 21 15 PLMBASE_REG Protected Low Memory Base Register This register sets up the base address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant zero bit position with 0 in the value read back from the register Bits N 0 of this register is decoded by hardware as all Os Software must setup the protected low memory region below 4 GB Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 68 6Bh Reset Value 0000_0000h Access RW Size 32 bits BIOS Optimal Default 00000h Reset RST ie GCEIST Protected Low Memory Base PLMB 31 20 RW 000h Uncore This field specifies the base of protected low me
132. SRTP field in the Global Command register Reads of this register returns value that was last programmed to it mojeo ones o 280 Datasheet Volume 2 Processor Configuration Registers intel 2 21 7 CCMD_REG Context Command Register This register manages context cache The act of writing the upper most byte of the CCMD_REG with the ICC field set causes the hardware to perform the context cache invalidation B D F Type 0 0 0 VCOPREMAP Address Offset 28 2Fh Reset Value 0000_0000_0000_0000h Access RW V RW RO V Size 64 bits BIOS Optimal Default 0_0000_0000h Reset RST bos joe ace Sats Btn eon O O Invalidate Context Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field is Clear to confirm the invalidation is complete Software must not update this register when this field is set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field 63 RW V Oh Uncore Software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this remapping hardware unit Since information from the context cache may be used by hardware to tag IOTLB entries
133. T Description Value PWR p I nvalidate IOTLB IVT Software requests IOTLB invalidation by setting this bit Software must also set the requested invalidation granularity by programming the IIRG field Hardware clears the IVT bit to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field Software must not submit another invalidation request through 63 RAN Oh Ungorg this register while the IVT field is Set nor update the associated Invalidate Address register Software must not submit OTLB invalidation requests when there is a context cache invalidation request pending at this remapping hardware unit Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flushing before invalidating the OTLB pee eo oe meee IOTLB Invalidation Request Granularity 11 RG When requesting hardware to invalidate the OTLB by setting the IVT bit software writes the requested invalidation granularity through this field The following are the encodings for the field 00 Reserved 01 Global invalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field 61 60 RW Oh Uncore 11 Page selective invalidation request The target address mask and invalidation hint must be specified in the
134. TLB Invalidate register This register is a write only register B D F Type 0 0 0 VCOPREMAP Address Offset 100 107h Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 0000_ 0000h Reset RST n pve ew fic pk ee rere no om pema oOo Address ADDR Software provides the DMA address that needs to be page selectively invalidated To make a page selective invalidation 38 12 0000000h Uncore request to hardware software must first write the appropriate fields in this register and then issue the appropriate page selective invalidate command through the OTLB_REG Hardware ignores bits 63 N where N is the maximum guest address width MGAW supported FS o eea o I nvalidation Hint 1H The field provides hint to hardware about preserving or flushing the non leaf page directory entries that may be cached in hardware 0 Software may have modified both leaf and non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request RW Oh Uncore hardware must flush both the cached leaf and non leaf page table entries corresponding to the mappings specified by ADDR and AM fields Software has not modified any non leaf page table entries corresponding to mappings specified in the ADDR and AM fields On a page selective invalidation request hardware may preserve the cached non leaf page table entries corresponding to m
135. The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control 1 RO V 1b U initialization It is set by default on Reset as well as whenever the oe corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state Before using a Virtual Channel software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link a 2 7 7 PEG TC PCI Express Completion Time out Register This register reports PCI Express configuration control of PCI Express Completion Time out related parameters that are not required by the PCI Express specification B D F Type 0 1 0 2 MMR Address Offset a 20Bhh Access Reset RST P Ra Sil ee 00000000 31 15 00000000 Reserved PCI Express Completion Time out PEG_TC This register determines the number of milliseconds the Transaction Layer will wait to receive an expected completion To avoid hang conditions the Transaction Layer will generate a dummy completion to the requestor if it does not receive the completion within this time period 14 12 RW 111b 900 Disable 001 Reserved 010 Reserved 100 Reserved 101 Reserved 110 Reserved x11 48 ms for normal operation pepe pee Datasheet Volume 2 131 Processor Con
136. VGAEN MDAP Description 0 All References to MDA and VGA space are not claimed by Device 1 Function 0 Illegal combination All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 0 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 0 MDA references are not claimed by Device 1 Function 0 VGA and MDA memory cycles can only be routed across PEG10 when MAE PCICMD10 1 is set VGA and MDA I O cycles can only be routed across PEG1O if OAE PCICMD10 0 is set Datasheet Volume 2 73 Processor Configuration Registers 2 5 24 REMAPBASE Remap Base Address Register B D F Type 0 0 0 PCI Address Offset 90 97h Reset Value 0000_O00F_FFFO_0000h Access RW KL RW L Size 64 bits BIOS Optimal Default 0000_0000_0000h Reset RST pm ew fas ik teem ese no om irene oooO Remap Base Address REMAPBASE The value in this register defines the lower boundary of the Remap window The Remap window is inclusive of this address In the decoder A 19 0 of the Remap Base Address are assumed to be Os Thus the bottom of the defined memory range will be aligned to a 35 20 RW L FFFFh Uncore 1 MB boundary When the value in this register is greater than the value programmed into the Remap Limit register the Remap window is disabled These bits are Intel TXT lockable ma e o eea o Lock LOCK RW KL Uncore This bit will lock all writeable settings in this re
137. Virtual Channel 1 Map TCVC1M This field indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 6 is set in this field TC6 is mapped to this VC resource When more than one bit in this field is set it indicates 6 1 RW 00h Uncore that multiple TCs are mapped to the VC resource To remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link BIOS Requirement Program this field with the value 010001b which maps TC1 and TC5 to VC1 Wacore Traffic Class 0 Virtual Channel 1 Map TCOVC1M Traffic Class 0 is always routed to VCO Datasheet Volume 2 Processor Configuration Registers intel 2 12 10 DMIVC1RSTS DMI VC1 Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMIBAR Address Offset 26 27h Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P safe j w j pee o Virtual Channel 1 Negotiation Pending VC1NP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling Software may use this bit when enabling or disabling the VC This 1 RO V 1b Uncore bit indicates the status of the process of Flow Control initialization It is set by
138. Word 16 bit or DWord 32 bit quantities with the exception of CONFIG_ADDRESS which can only be accessed as a DWord All multi byte numeric fields use little endian ordering that is lower addresses contain the least significant parts of the field Registers that reside in bytes 256 through 4095 of each device may only be accessed using memory mapped transactions in DWord 32 bit quantities Some of the processor registers described in this section contain reserved bits These bits are labeled Reserved Software must deal correctly with fields that are reserved On reads software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value On writes software must ensure that the values of reserved bit positions are preserved That is the values of reserved bit positions must first be read merged with the new values for other bit positions and then written back Note the software does not need to perform read merge and write operation for the Configuration Address Register In addition to reserved bits within a register the processor contains address locations in the configuration space of the Host Bridge entity that are marked either Reserved or Intel Reserved The processor responds to accesses to Reserved address locations by completing the host cycle When a Reserved register location is read a zero value is returned Reserved registers can be 8 16 or 32 bits in siz
139. _RFP_CO Refresh Parameters Register B D F Type 0 0 0 MCHBAR MCO Address Offset 4294 4297h Default Value 0000_980Fh Access RW L Size 32 bits BIOS Optimal Default 0000h Reserved Double Refresh Control DOUBLE_REFRESH_CONTROL This field will allow the double self refresh enable disable 00b Double refresh rate when DRAM is WARM HOT 01b Force double self refresh regardless of temperature 10b Disable double self refresh regardless of temperature 11b Reserved Refresh panic WM Refresh_panic_wm 9h Uncore tREFI count level in which the refresh priority is panic default is 9 It is recommended to set the panic WM at least to 9 in order to use the maximum no refresh period possible Refresh high priority WM Refresh_HP_WM 8h Uncore tREFI count level that turns the refresh priority to high default is 8 Rank idle timer for opportunistic refresh OREF_RI OFh Uncore Rank idle period that defines an opportunity for refresh in DCLK cycles Uncore 2 13 9 TC_RFTP_CO Refresh Timing Parameters Register B D F Type 0 0 0 MCHBAR MCO Address Offset 4298 429Bh Default Value 46B4_1004h Access RW L Size 32 bits Reset RST Description Value PWR P 9 tREFI tREFIx9 Uncore Period of minimum between 9 tREFI and tRAS maximum normally 70 us in 1024 DCLK cycles default is 35 need to reduce 100 DCLK cycles uncertainty on timing of panic refresh Refresh execution time tRFC
140. __Reatstername esetvalue cess A8 ABh IEADDR_REG Invalidation Event Address Register 0000_0000h AC AFh IEUADDR_REG Invalidation Event Upper Address Register 0000_0000h 2 Interrupt Remapping Table Address Register 0000_0000 2 Invalidate Address Register 0000 _ 0000 IOTLB Invalidate Register 0000 0000 RW RO V Reserved 0000_0000 Reserved 0000 0000 ROS V RO Reserved RO KFW FFO FF3h RSVD 0000_0000h RW KL RW L RO 2 21 1 VER_REG Version Register This register reports the architecture version supported Backward compatibility for the architecture is maintained with new revision numbers allowing software to load remapping hardware drivers written for prior architecture versions B D F Type 0 0 0 VCOPREMAP Address Offset 0 3h Reset Value 0000_0010h Access Size BIOS Optimal Default 7 4 0001b Uncore Major Version number MAX i i This field indicates supported architecture version 3 0 0000b ingore Minor Version number MIN l l l This field indicates supported architecture minor version 270 Datasheet Volume 2 Processor Configuration Registers 2 21 2 CAP_REG Capability Register This register reports general remapping hardware capabilities B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9_0080_2066_0262h Access RO Size 64 bits BIOS Optimal Default 000h Reset RST Description Value PWR p h Reseved S DMA Read Draining DRD Hardware does N
141. a size granularity of 1 MB The processor positively decodes memory accesses to PCI Express memory address space as defined by the following equations Memory_Base_Address lt Address lt Memory_Limit_Address Prefetchable_Memory_Base_ Address lt Address lt Prefetchable_Memory_Limit_Address The window size is programmed by the plug and play configuration software The window size depends on the size of memory claimed by the PCI Express device Normally these ranges will reside above the Top of Low Usable DRAM and below High BIOS and APIC address ranges They MUST reside above the top of low memory TOLUD if they reside below 4 GB and MUST reside above top of upper memory TOUUD if they reside above 4 GB or they will steal physical DRAM memory space It is essential to support a separate Pre fetchable range in order to apply USWC attribute from the processor point of view to that range The USWC attribute is used by the processor for write combining Note that the processor memory range registers described above are used to allocate memory address space for any PCI Express devices sitting on PCI Express that require such a window The PCICMD register can override the routing of memory accesses to PCI Express In other words the memory access enable bit must be set to enable the memory base limit and pre fetchable base limit windows The upper PMUBASE PMULIMIT registers are implemented for PCI Express Specification compliance Th
142. able ccir 21 2 3 2 4 DRAM Protected Range DPR cccceceeeee eee eect neta eee eea nents nae ene 22 2 3 2 5 Pre allocated Memory 0 cece eee nee eee een ee eee neat erates 22 2 3 2 6 GFX Stolen Spaces reeeo inane tienen ss Akagi iene AEE NE TETI EERENS 23 23 21 ME UMA drenere E A RA A 23 2 3 3 PCI Memory Address Range TOLUD 4 GB ccececee eee eee eee et ee teens 23 2 3 3 1 APIC Configuration Space FECO_OOOOh FECF_FFFFh 08 25 2 3 3 2 HSEG FEDA_OOOOh FEDB_FFFF cceeeeeeee tent eee ee ea ea eee eaes 25 2 3 3 3 MSI Interrupt Memory Space FEEO_OOOOh FEEF_FFFFh 25 2 3 3 4 High BIOS Area ii ceicetaitescved see sede ease echaieds de AEREA E aa EENS 25 2 3 4 Main Memory Address Space 4 GB to TOUUD cc cece cece eee ee eee teeta 26 2 3 4 1 Memory Re claim Background cece cette eee eaten ees 27 2 3 4 2 Indirect Accesses to MCHBAR Registers uccse 27 2 3 4 3 Memory Remapping c cecceeee eee erence ee nee ene nent nee e eae 28 2 3 4 4 Hardware Remap AIQOrith cece eect eee eee ete ents 28 2 3 4 5 Programming Model cce ecient 28 2 3 5 PCI Express Configuration Address Space cccceecenee cnet eee eee eneeeaeeenaes 32 2 3 6 PCI Express Graphics Attach PEG cccceccceeeece eee ee tenner eee eee tnae tne en aes 33 2 3 7 Graphics Memory Address Ranges eceetecene ene e nee e ene tena teeta nae eaten eae 34 2 3 7 1
143. abort does not exist on primary side of this device Signaled Target Abort Status STAS This bit is set when a Function completes a Posted or Non Posted Request as a Completer Abort error This applies to a Function with a Type 1 Configuration header when the Completer Abort was generated by its Primary Side Not Applicable or Implemented Hardwired to 0 The concept of a target abort does not exist on primary side of this device DEVSELB Timing DEVT This device is not the subtractive decoded device on bus 0 This bit field is therefore hardwired to 00 to indicate that the device uses the fastest possible decode Does not apply to PCI Express and must be hardwired to 00b Datasheet Volume 2 149 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset 6 7h Reset Value 0010h Access RW1C RO RO V Size an bits BIOS Optimal Default Reset RST jw awe ss Sie esermton Master Data Parity Error PMDPE This bit is set by a Requester Primary Side for Type 1 Configuration Space header Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs e Requester receives a Completion marked poisoned RWIC Uncore e Requester poisons a write Request If the Parity Error Response bit is Ob this bit is never set This bit will be set only for completions of requests encountering ECC error in DRAM Poisoned Peer to peer posted forwarded w
144. accesses VGA Enable VGAEN 3 RW Uncore This bit controls the routing of processor initiated transactions targeting VGA compatible O and memory address ranges See the VGAEN MDAP table in Device 0 offset 97h 0 104 Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 1 0 2 PCI Address Offset 3E 3Fh Reset Value 0000h Access RW RO Size F bits BIOS Optimal Default Reset RST jw awe Sst Sie esermon ISA Enable ISAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the root port to an I O access issued by the processor that target ISA I O addresses This applies only to I O addresses that are enabled by the OBASE 2 RW ncore and IOLIMIT registers 0 All addresses defined by the IOBASE and IOLIMIT for processor 1 0 transactions will be mapped to PCI Express G 1 The root port will not forward to PCI Express G any O transactions addressing the last 768 bytes in each 1KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers SERR Enable SERREN 0 No forwarding of error messages from secondary side to 1 RW Uncore primary side that could result in an SERR 1 ERR_COR ERR_NONFATAL and ERR_FATAL messages result in SERR message when individually enabled by the Root Control register Parity Error Response Enable PEREN This bit controls whether or n
145. address offset Register bit descriptions are in the sections following the table PCI Device 0 Function 0 Register Address Map Sheet 1 of 2 Address Register Offset Symbol Register Name Reset Value 0 1h Vendor Identification 8086h Device Identification 0100h RO FW RO V 4 5h PCICMD PCI Command 0006h RO RW 6 7h PCISTS PCI Status 0090h RO RW1C 8h Revision Identification 00h RO FW 9 Bh Class Code 06_0000h HDR Dy Eh Header Type 00h Oh Oh ro a 5 ps 3 PCI Express Egress Port Base Address 0000 _ 0000 0 Host Memory Mapped Register Range Base 0000 _0000 0 m ee 80h PAMO Programmable Attribute Map 0 RW RW RW 2C 2Dh SVID Subsystem Vendor Identification 0000h_ Datasheet Volume 2 Processor Configuration Registers Table 2 7 5 P e PCI Device 0 Function 0 Register Address Map Sheet 2 of 2 83h Programmable Attribute Map 3 84h Programmable Attribute Map 4 86h PAM6 Programmable Attribute Map 6 LAC Legacy Access Control RW RW RW RW RW RW RW Remap Base Address Register 0000 OOOF F so ait aeae T a ea Remap Limit Address Register 0000_0000 0 98 9Fh REMAPLI MIT 000 0000h RW KL RW L Top of Memory 0000 007F _F eps Tom MPI parton RL ne E4 E7h CAPIDO_A Capabilities A 0000_0000h RO FW RO Datasheet Volume 2 47 2 5 2 48 Processor Configuration Registers VI D Vendor Identification Register This register
146. address that 1 ROS V AF caused the error and the error syndrome are also logged and they are locked until this bit is cleared This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared Correctable Error Status CERRSTS This bit is set when a correctable single bit error occurs on a memory read data transfer When this bit is set the address that caused the error and the error syndrome are also logged and they ROS V Powerg are locked to further single bit errors until this bit is cleared A multiple bit error that occurs after this bit is set will override the address error syndrome information This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared 2 14 7 ECCERRLOG1 C1 ECC Error Log 1 Register B D F Type 0 0 0 MCHBAR MC1 Address Offset 44CC 44CFh Reset Value 0000_0000h Access ROS V Size 32 bits Reset RST ces ORE Error Column ERRCOL This field holds the DRAM column address of the read transaction that had the ECC error Error Row ERRROW This field holds the DRAM row page address of the read transaction that had the ECC error Datasheet Volume 2 215 Processor Configuration Registers intel 2 14 8 TC_RFP_C1 Refresh Parameters Register B D F Type 0 0 0 MCHBAR MC1 Address Offset 4694 4697h Default Value 0000_980Fh Access RW L Size 32 bits BI OS Optimal Default 0000h Description Double Refresh Control DOUBLE_REFRESH_CONTRO
147. al memory This is NOT necessarily the highest main memory address 38 20 7FFFFh Uncore holes may exist in main memory address map due to addresses allocated for memory mapped 10 These bits correspond to address bits 38 20 1 MB granularity Bits 19 0 are assumed to be 0 All the bits in this register are locked in Intel TXT mode pasa me ened ooo Lock LOCK RW KL Uncore This bit will lock all writeable settings in this register including itself Datasheet Volume 2 75 76 intel Processor Configuration Registers TOUUD Top of Upper Usable DRAM Register This 64 bit register defines the Top of Upper Usable DRAM Configuration software must set this value to TOM minus all ME stolen memory if reclaim is disabled If reclaim is enabled this value must be set to reclaim limit 1 byte 1 MB aligned since reclaim limit is 1 MB aligned Address bits 19 0 are assumed to be 000_0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than or equal to 4 GB BIOS Restriction Minimum value for TOUUD is 4 GB These bits are Intel TXT lockable B D F Type 0 0 0 PCI Address Offset A8 AFh Reset Value 0000_0000_0000_0000h Access RW KL RW L Size 64 bits BIOS Optimal Default 000_0000_ 0000h Reset RST Description Value PWR p ssj o o pee o TOUUD TOUUD This r
148. ale DSCALE This field indicates that this device does not support the power management data register Data Select DSEL This field indicates that this device does not support the power management data register PME Enable PMEE This bit indicates that this device does not generate PME assertion from any D state 0 PME generation not possible from any D State 1 PME generation enabled from any D State The setting of this bit has no effect on hardware See PM_CAP 15 11 No Soft Reset NSR 1 Device is transitioning from D3hot to DO because the power state commands do not perform an internal reset Configuration context is preserved Upon transition no additional operating system intervention is required to preserve configuration context beyond writing the power state bits 0 Devices do not perform an internal reset upon transitioning from D3hot to DO using software control of the power state bits Regardless of this bit the devices that transition from a D3hot to DO by a system or bus segment reset will return to the device state DO uninitialized with only PME context preserved if PME is supported and enabled 107 2 6 27 108 B D F Type Address Offset Reset Value Access Size BIOS Optimal Default Processor Configuration Registers 0 1 0 2 PCI 84 87h 0000_0008h RO RW 32 bits 000000h Reset RST ORQ Power State PS This field indicates the current power state
149. alue for the Address Mask AM field in the Invalidation Address register 53 48 000000b Uncore IVA_REG and ovis Herre Descriptor iotlbs ini dec This field is valid only when the PSI field in Capability register is reported as set Number of Fault recording Registers NFR Number of fault recording registers is computed as N 1 where N is the value reported in this field 00000099 Uncore Implementations must support at least one fault recording register b p pp g reg NFR 0 for each remapping hardware unit in the platform The maximum number of fault recording registers per remapping hardware unit is 256 Page Selective Invalidation PSI 0 Hardware supports only domain and global invalidates for IOTLB 39 1 Hardware supports page selective domain and global invalidates for IOTLB Hardware implementations reporting this field as set are recommended to support a Maximum Address Mask Value MAMV value of at least 9 saf o o een o Super Page Support SPS This field indicates the super page sizes supported by hardware A value of 1 in any of these bits indicates the corresponding super page size is supported The super page sizes corresponding to various bit positions within this field are 21 bit offset to page frame 2 MB alan aoouP Ungare 30 bit offset to page frame 1 GB 39 bit offset to page frame 512 GB 3 48 bit offset to page frame 1 TB Hardware implementations supporting a specific super page size mus
150. and loaded by BIOS e Top of Logical Address Remap Window defined by the REMAPLIMIT register which is calculated and loaded by BIOS e Bottom of Physical Remap Memory defined by the existing TOLUD register e Top of Physical Remap Memory which is implicitly defined by either 4 GB or TOM minus Manageability Engine stolen size Mapping steps Determine TOM Determine TOM minus ME stolen size Determine MMIO allocation Determine TOLUD Determine GFX stolen base Determine GFX GTT stolen base Determine TSEG base Determine remap base limit Determine TOUUD ONANAWNE Figure 2 5 and Figure 2 6 show the two possible general cases of remapping Datasheet Volume 2 Processor Configuration Registers Case 1 Less than 4 GB of Physical Memory no remap Figure 2 5 Case 1 Less than 4 GB of Physical Memory no remap PHYSICAL MEMORY DRAM CONTROLLER VIEW HOST SYSTEM VIEW 1 MB aligned 1 MB aligned TOUUD BASE ME BASE 1 MB aligned Wasted Only if 4 GB minus PCI PCI MMIO MMIO space is greater than 4 GB minus ME stolen base TOLUD BASE 1 MB aligned 1 MB aligned GFX Stolen GFX Stolen BASE 1 MB aligned GFX GTT TOLEN GFX GTT Stolen BASE STO 1 MB aligned TSEG TSEG BASE 1 MB aligned OS VISIBLE lt 4GB e Populated Physical Memory 2 GB e Address Space allocated to memory mapped IO 1 GB e Remapped Physical Memory 0 GB e TOM 0
151. anslation type in context entries 1 Hardware supports pass through translation type in context entries Caching Hints CH 0 Hardware does not support IOTLB caching hints ALH and EH fields in context entries are treated as reserved 1 Hardware supports OTXTB caching hints through the ALH and EH fields in context entries Extended Interrupt Mode EI M 0 On Intel 64 platforms hardware supports only 8 bit APIC IDs xAPIC mode 1 On Intel 64 platforms hardware supports 32 bit APIC IDs x2APIC mode This field is valid only on Intel 64 platforms reporting Interrupt Remapping support IR field Set Interrupt Remapping Support IR 0 Hardware does not support interrupt remapping 1 Hardware supports interrupt remapping Implementations reporting this field as set must also support Queued Invalidation QI Device I OTLB Support DI 0 Hardware does not support device OTLBs 2 Uncore 1 Hardware supports Device OTLBs Implementations reporting this field as set must also support Queued Invalidation QI 274 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 VCOPREMAP Address Offset 10 17h Reset Value 0000_0000_O0FO_10DAh Access RO V RO Size 64 bits BIOS Optimal Default 000_0000_0000h Reset RST a GROC Queued I nvalidation Support QI 1 RO V 1b Uncore 0 Hardware does not support queued invalidations 1 Hardware supports queued inva
152. appings specified by ADDR and AM fields Address Mask AM The value in this field specifies the number of low order bits of the ADDR field that must be masked for the invalidation operation This field enables software to request invalidation of contiguous mappings for size aligned regions For example Mask ADDR bits Pages Value Masked Invalidated None 1 12 2 5 0 RW 00h Uncore 13 12 4 14 12 8 When invalidating mappings for super pages software must specify the appropriate mask value For example when invalidating mapping for a 2 MB page software must specify an address mask value of at least 9 Hardware implementations report the maximum supported mask value through the Capability register 298 Datasheet Volume 2 Processor Configuration Registers intel 2 21 29 I OTLB_REG I OTLB I nvalidate Register Register to invalidate OTLB The act of writing the upper byte of the OTLB_REG with IVT field Set causes the hardware to perform the OTLB invalidation B D F Type 0 0 0 VCOPREMAP Address Offset 108 10Fh Reset Value 0000_0000_0000_0000h Access RW RO V RW V Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RST Description Value PWR p I nvalidate IOTLB IVT Software requests IOTLB invalidation by setting this field Software must also set the requested invalidation granularity by programming the IIRG field Hardware clears the IVT field to indicate the invalidation request
153. ardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements Device Specific Initialization DSI 21 Uncore Hardwired to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it 20 Wneore Auxillary Power Source APS Hardwired to 0 PME Clock PMECLK 19 Uncore Hardwired to 0 to indicate this device does NOT support PME generation PCI PM CAP Version PCIPMCV 18 16 011b Uncore Version A value of 011b indicates that this function complies with revision 1 2 of the PCI Power Management Interface Specification Pointer to Next Capability PNC This contains a pointer to the next item in the capabilities list If E MSICH CAPL 0 7Fh is 0 the next item in the capabilities list is 15 8 RO V 90h U TES the Message Signaled Interrupts MSI capability at 90h If MSICH CAPL 0 7Fh is 1 the next item in the capabilities list is the PCI Express capability at AOh Capability 1D CID 7 0 Olh Uncore Value of 01h identifies this linked list item capability structure as being for PCI Power Management registers Datasheet Volume 2 165 t i Processor Configuration Registers 2 10 26 PM_CS6 Power Management Control Status Register B D F Type 0 6 0 PCI Address Offset 84 87h Reset Value 0000_ 0008h Access RO RW Size 32 bits BIOS Optimal Default 000000h Reset RST T oew faer Gaie Bam Desert OOOO e e E e e a
154. are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 6 0 PCI Address Offset 2C 2Fh Reset Value 0000_0000h Access Size Prefetchable Memory Address Limit PMLI MI TU 0009 000 Uncore This field corresponds to A 63 32 of the upper limit of the prefetchable Memory range that will be passed to PCI Express G Reset RST Description Value PWR P CAPPTR6 Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities B D F Type 0 6 0 PCI Address Offset 34h Reset Value 88h Access RO Size 8 bits First Capability CAPPTR1 Uncore The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability Reset RST Ch V Datasheet Volume 2 161 Processor Configuration Registers intel 2 10 22 INTRLINE6 Interrupt Line Register This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information B D F
155. as illegal cycles Writes are aborted Reads are aborted and will return Unsupported Request status or Master abort in its completion packet This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the data is available This bit does not affect forwarding of Completions from the primary interface to the secondary interface Memory Access Enable MAE 0 Disable All of device s memory space is disabled 1 RW Uncore 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE MLIMIT PMBASE and PMLIMIT registers I O Access Enable I OAE 0 Disable All of the device I O space is disabled RW U er 1 Enable the I O address range defined in the OBASE and IOLIMIT registers Datasheet Volume 2 89 Processor Configuration Registers 2 6 4 PCISTS1 PCI Status Register This register reports the occurrence of error conditions associated with primary side of the virtual Host PCIl Express bridge embedded within the Root port B D F Type 0 1 0 2 PCI Address Offset 6 7h Reset Value 0010h Access RWIC RO RO V Size o bits BIOS Optimal Default Detected Parity Error DPE This bit is Set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register On a Function with a Type 1 Configuration header the bit is set when the
156. ase address of the target RCRB Link Valid LV RW O Uncore 0 Link Entry is not valid and will be ignored 1 Link Entry specifies a valid link 2 12 16 DMILE1A DMI Link Entry 1 Address Register This register provides the second part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 58 5Bh Reset Value 0000_0000h Access RW O Size 32 bits BIOS Optimal Default 000h Reset RST a GROC Link Address LA 31 12 RW O 00000h Uncore Memory mapped base address of the RCRB that is the target element egress port of PCH for this link entry pare eo oreo o Datasheet Volume 2 199 Processor Configuration Registers intel 2 12 17 DMILE2D DMI Link Entry 2 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 60 63h Reset Value 0000_ 0000h Access RO RW O Size 32 bits BIOS Optimal Default 0000h Paen RST Description Value PWR P Target Port Number TPN This field specifies the port number associated with the element 31 24 00h Uncore targeted by this link entry Egress Port The target port number is with respect to the component that contains this element as specified by the target component ID Target Component ID TCID This field identifies the physical or logical component that is 23 1
157. ay Controller i Sub Class Code SUBCC poh VGA compatible Programming I nterface PI ro ro oon unore 00h indicates a Display Controller 136 Datasheet Volume 2 Processor Configuration Registers intel 2 8 7 CLS Cache Line Size Register The IGD does not support this register as a PCI slave B D F Type 0 2 0 PCI Address Offset Ch Reset Value 00h Access RO Size 8 bits Reset RST ia GLEIC Cache Line Size CLS 7 0 00h Uncore This field is hardwired to Os The IGD as a PCI compliant master does not use the Memory Write and Invalidate command and in general does not perform operations based on cache line size 2 8 8 MTXT2 Master Latency Timer Register The IGD does not support the programmability of the master latency timer because it does not perform bursts B D F Type 0 2 0 PCI Address Offset Reset Value Access Size Valde a Description Value PWR p 7 0 00h Uncore Master Latency Timer Count Value MTXTCV Hardwired to Os 2 8 9 HDR2 Header Type Register This register contains the Header Type of the IGD B D F Type 0 2 0 PCI Address Offset Eh Reset Value 00h Access RO Size 8 bits Reset RST Description Value PWR p Multi Function Status MFUNC 7 Uncore This bit indicates if the device is a Multi Function Device The Value of this register is hardwired to 0 the processor graphics is a single function Header Code H 00h Uncor
158. b 5 0 GT s PCI Express Link All other encodings are reserved The value in this field is undefined when the Link is not up 2 10 40 SLOTCAP Slot Capabilities Register Note Hot Plug is not supported on Intel Xeon processor E3 1200 family platforms B D F Type 0 6 0 PCI Address Offset B4 B7h Reset Value 0004_0000h Access RW O RO Size 32 bits Reset RST boas je awe Ses Sm esermon Physical Slot Number PSN This field indicates the physical slot number attached to this Port Uncore BIOS Requirement This field must be initialized by BIOS to a value that assigns a slot number that is globally unique within the chassis No Command Completed Support NCCS When set to 1b this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot Plug Controller This bit is only permitted to be set to 1b if the hotplug capable port is able to accept writes to all fields of the Slot Control register without delay between successive writes Reserved for Electromechanical I nterlock Present EIP When set to 1b this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot Datasheet Volume 2 177 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset B4 B7h Reset Value 0004_0000h Access RW O RO Size 32 bits Slot Power Limit Scale SPLS This field specifies the scale used for th
159. be 0011101011100b when writing this register 2 12 25 AFE_BMUTO AFE BMU Configuration Test 0 Register B D F Type 0 0 0 DMI BAR Address Offset BCC BCGh Reset Value 1000_000h Access RO RW Size 32 bits Reset RST Description Value PWR P 31 25 RO oh Uncore Reserved Must be 0 when writing this register 24 RO 1b Uncore Reserved Must be 1 when writing this register 23 5 5 235 RO oh Uncore Reserved Must be 0 when writing this register Transmit at Half Rail PEG TXHALFRP This bit enables the transmitter to drive out a half rail to rail swing Uncore on TXP TXN when in PEG mode 0 Full swing for 16 PEG lanes 1 Half swing for 16 PEG lanes 30 RO Oh Uncore Reserved Must be 0 when writing this register 206 Datasheet Volume 2 Processor Configuration Registers intel 2 13 MCHBAR Registers in Memory Controller Channel 0 Table 2 15 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 15 MCHBAR Registers in Memory Controller Channel 0 Register Address Map Address 3 n Offset Register Symbol Register Name Reset Value Access 4000 4003h TC_DBP_CO Timing of DDR Bin Parameters 0000_0666h 4004 4007h TC_RAP_CO Timing of DDR Regular Access 0010_4044h Parameters 4028 402Bh SC_10_LATENCY_CO 10 Latency Configuration 0000_0000h 42A4 42A7h TC_SRFTP_CO Self Refresh Timing
160. bitration uses the VC Arbitration Table As a VC Arbitration Table is never used by this component this field will never be used Datasheet Volume 2 Processor Configuration Registers E t 2 7 4 VCORCAP VCO Resource Capability Register B D F Type 0 1 0 2 MMR Address Offset 110 113h Reset Value 0000_0001h Access RO Size 32 bits BIOS Optimal Default 00h Reset RST ete js awe Ses Se sermon 31 24 Ro oon Uncore Reserved for Port Arbitration Table Offset PATO S e ees 22 16 Ro oon unore Reserved for Maximum Time Slots MTS Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the 15 Uncore TLP header are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request pare oon Port Arbitration Capability PAC This field indicates types of Port Arbitration Supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic Each bit location within this field corresponds to a Port Arbitration Capability defined below When more than one bit in this field is set it indicates that the VC resource can be configured to provide different arbitration services Software selects amon
161. bits 31 20 of the base address of stolen 31 20 RW L 000h Uncore DRAM memory BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size PCI Device 0 offset 52h bits 6 4 from TOLUD PCI Device 0 offset BCh bits 31 20 past oo eea ooo Lock LOCK RW KL Uncore This bit will lock all writeable settings in this register including itself BGSM Base of GTT stolen Memory Register 2 5 29 This register contains the base address of stolen DRAM memory for the GTT BIOS determines the base of GTT stolen memory by subtracting the GTT graphics stolen memory size PCI Device 0 offset 52h bits 9 8 from the Graphics Base of Data Stolen Memory PCI Device 0 offset BOh bits 31 20 B D F Type 0 0 0 PCI Address Offset B4 B7h Reset Value 0010_0000h Access RW KL RW L Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR p Graphics Base of GTT Stolen Memory BGSM This register contains the base address of stolen DRAM memory for 1 20 RW L 001h the GTT BIOS determines the base of GTT stolen memory by 3 pneDIg subtracting the GTT graphics stolen memory size PCI Device 0 offset 52h bits 11 8 from the Graphics Base of Data Stolen Memory PCI Device 0 offset BOh bits 31 20 ma o o f eea ooo Lock LOCK RW KL Uncore This bit will lock all writeable settings in this register including itself Datasheet Volume 2 77 m t 1 Processor Confi
162. bles signaling of ERR_CORR to the Root RW Uncore Control register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting 15 11 7 5 3 2 1 172 Datasheet Volume 2 Processor Configuration Registers intel 2 10 37 DSTS Device Status Register This register reflects status corresponding to controls in the Device Control register The error reporting bits are in reference to errors detected by this device not errors messages received across the link B D F Type 0 6 0 PCI Address Offset AA ABh Reset Value 0000h Access RO RW1C Size 16 bits BIOS Optimal Default 000h E Reset RST bos Description Gn R Transactions Pending TP 0 All pending transactions including completions for any outstanding non posted requests on any used virtual channel have been completed 1 Indicates that the device has transaction s pending including completions for any outstanding non posted requests for all used Traffic Classes Not Applicable or Implemented Hardwired to 0 Unsupported Request Detected URD When set this bit indicates that the Device received an Unsupported Request Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register Additionally the Non Fatal Error Detected bit or the Fatal Error Detected bit is set according to the setting
163. cal Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change Link Bandwidth Management Status LBWMS This bit is set to 1 by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status e A link retraining initiated by a write of 1b to the Retrain Link bit has completed Note that this bit is set following any write of 1b to the Retrain Link bit including when the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an TXTSSM time out or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change Data Link Layer Link Active Optional DLLLA This bit indicates the status of the Data Link Control and Management State Machine It returns a 1b to indicate the DL_Active state Ob otherwise This bit must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the presence of a reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connecto
164. caused the error and the error syndrome are also logged and they ROS V Powerg are locked to further single bit errors until this bit is cleared A multiple bit error that occurs after this bit is set will override the address error syndrome information This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared 2 17 3 ECCERRLOG1 ECC Error Log 1 Register B D F Type 0 0 0 MCHBAR_MCBCAST Address Offset 4CCC 4CCFh Reset Value 0000_ 0000h Access ROS V Size 32 bits Reset RST ae ORES Error Column ERRCOL This field holds the DRAM column address of the read transaction that had the ECC error Error Row ERRROW This field holds the DRAM row page address of the read transaction that had the ECC error Datasheet Volume 2 223 Processor Configuration Registers intel 2 17 4 PM_CMD_PWR Power Management Command Power Register This register defines the power contribution of each command ACT PRE CAS read and CAS write Assumption is that the ACT is always followed by a PRE although not immediately and REF commands are issued in a fixed rate and there is no need to count them The register has three 8 bit fields B D F Type 0 0 0 MCHBAR_ MCBCAST Address Offset 4F84 4F87h Reset Value 0000_0000h Access RW LV Size 32 bits BIOS Optimal Default 00h Reset RST jee ew fie pk ee 23 16 RW LV CAA Power SS of CAS Write command PWR_CAS_W RW LV Power contribution
165. cc cee ce cette nett eee ne eee ee eee teen teat ees 142 2 8 18 MAXLAT Maximum Latency ReQiSter cece cece eee ne eee ee erect teeta enna tees 142 2 8 19 MSAC Multi Size Aperture Control Register cceeceeee eee ne eee ee eee en teat ees 143 2 9 Device 2 1 0 ROGISLENS iisisisscstiecsbicivsewbers toiling incense chased ceded deseea tia ianediadeee ste EE EEEE 144 2 9 1 INDEX MMIO Address Register ceceeeeeeee reenter teen eee eaten teeta een eeataas 144 2 9 2 DATA MMIO Data ReGISter cccceceeee cree eet cece eee eee eee naa ekani 144 2 10 PCI Device 6 Configuration Registers ssssssssrrrsssnnrnnnnrrrnuseerrnnnrrnnunerrnnnnnnunn 145 2 10 1 VID6 Vendor Identification Register cece eee eee ee eee ee eee eee teen een e ees 146 2 10 2 DID6 Device Identification REGiSter cece e cece e ee eee eee teen e eaten teas 147 2 10 3 PCICMD6 PCI Command ReGiIStel ccceceece eect erect ee eee ee teen eeatas 147 Datasheet Volume 2 5 5 r D 2 11 2 10 4 PCISTS6 PCI Status ReQiSter cece iene E Enn e Ekerin SEINS 149 2 10 5 RID6 Revision Identification Register cece teeter erent teeters 151 2 10 6 CC6 Class Code Reister cc iiaee eie nene REAR neta seen E EE ete 151 2 10 7 CL6 Cache Line Size ReEGiSter cece cece ceteris 152 2 10 8 HDR6 Header Type Register cceceee ete ee eee eee eee e eset ee tee teen tea eneeaee 152 2 10
166. ce If no hole is created the processor will route the request to DRAM If a hole is created the processor will route the request to DMI since the request does not target DRAM Graphics translated requests to the range will always route to DRAM 2 3 2 2 TSEG For processor initiated transactions the processor rely on correct programming of SMM Range Registers SMRR to enforce TSEG protection TSEG is below IGD stolen memory which is at the Top of Low Usable physical memory TOLUD BIOS will calculate and program the TSEG BASE in Device 0 TSEGMB used protect this region from DMA access The calculation is TSEGMB TOLUD DSM SIZE GSM SIZE TSEG SIZE SMM mode processor accesses to enabled TSEG access the physical DRAM at the same address When the extended SMRAM space is enabled processor accesses to the TSEG range without SMM attribute or without WB attribute are handled by the processor as invalid accesses Non processor originated accesses are not allowed to SMM space PCI Express DMI and Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle type with reads and writes to location C_0000h and byte enables turned off for writes 2 3 2 3 Protected Memory Range PMR programmable For robust and secure launch of the MVMM the MVMM code and private data needs to be loaded to a memory region protected from bus master accesses Support for protected memory region is required for DMA remapp
167. ce is always given to IGD The processor always positively decodes internally mapped devices namely the IGD Subsequent decoding of regions mapped to either PCI Express port or the DMI Interface depends on the Legacy VGA configurations bits VGA Enable and MDAP For the remainder of this section PCI Express can refer to either the device 1 port functions or the device 6 port VGA range accesses will always be mapped as UC type memory Datasheet Volume 2 41 m t Processor Configuration Registers Accesses to the VGA memory range are directed to IGD depend on the configuration The configuration is specified by e Internal Graphics Controller in Device 2 is enabled DEVEN D2EN bit 4 e Internal Graphics VGA in Device 0 function 0 is enabled through register GGC bit 1 e IGD memory accesses PCICMD2 04 05h MAE bit 1 in Device 2 configuration space are enabled e VGA Compatibility Memory accesses VGA Miscellaneous output Register MSR Register bit 1 are enabled e Software sets the proper value for VGA Memory Map Mode Register VGA GRO6 Register bits 3 2 See Table 2 4 for translations Table 2 4 IGD Frame Buffer Accesses Mem Access gt BOOOOh B7FFFh Zo __ _ 01 IGD PCI Express Bridge or DMI PCI Express Bridge or DMI Interface Interface 10 PCI Express Bridge or IGD PCI Express Bridge or DMI DMI Interface Interface 11 PCI Express Bridge or PCI Express Bridge or DMI IGD DMI Interface Inter
168. ched in the remapping caches Any software updates to the remapping structures including updates to not present or erroneous entries require explicit invalidation Hardware implementations of this architecture must support a value of 0 in this field Protected High Memory Region PHMR 0 Indicates protected high memory region is not supported 1 Indicates protected high memory region is supported Protected Low Memory Region PLMR 0 Indicates protected low memory region is not supported 1 Indicates protected low memory region is supported Required Write Buffer Flushing RWBF 0 No write buffer flushing is needed to ensure changes to memory resident structures are visible to hardware 1 Software must explicitly flush the write buffers to ensure updates made to memory resident remapping structures are visible to hardware Advanced Fault Logging AFL 0 Advanced fault logging is not supported Only primary fault logging is supported 1 Advanced fault logging is supported Number of domains supported ND 000 Hardware supports 4 bit domain ids with support for up to 16 domains 001 Hardware supports 6 bit domain ids with support for up to 64 domains 010 Hardware supports 8 bit domain ids with support for up to 256 domains f 011 Hardware supports 10 bit domain ids with support for up to 2 0 010b Uncore 1024 domains 100 Hardware supports 12 bit domain ids with support for up to 4K domains
169. cify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0O the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 82h Reset Value 00h Access RW Size a v BIOS Optimal Default Reset RST Description Value PWR p mefe o pee o OCC000 OCFFFF Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OCCOOOh to OCFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT sae means o 0C8000 OCBFFF Attribute LOENABLE This field controls the ste
170. claim Base x Main 1 MB aligned Memory Reclaim Reclaim BASE Add Range MESEG BASE 1 MB aligned i Main memory OS visible Address gt 4GB Range 1 MB aligned Flash APIC eee FECO_0000 me invisible 7 sa Reclaim TOLUD BASE PCI ee Memory GFX Stolen Add Range 0 256 MB subtractively GFX Stolen BASE decoded to DMI 1 MB aligned for reclaim 1 MB aligned GFX GTT STOLEN GFX GTT Stolen BASE S 0 2 MB 1 MB aligned TSEG 0 8 MB TSEG BASE 1 MB aligned Main Memory OS Add Range VISIBLE lt 4GB Legacy Add Range Datasheet Volume 2 17 m t 1 Processor Configuration Registers 2 3 1 Legacy Address Range This area is divided into the following address regions e 0 640 KB DOS Area e 640 768 KB Legacy Video Buffer Area e 768 896 KB in 16 KB sections total of 8 sections Expansion Area e 896 960 KB in 16 KB sections total of 4 sections Extended System BIOS Area e 960 KB 1 MB Memory System BIOS Area Figure 2 2 DOS Legacy Address Range OOOF_FFFFh System BIOS Upper 000F_0000h 64 KB 000E_FFFFh Extended System BIOS Lower 000E_0000h 64 KB 16 KB x 4 000D_FFFFh Expansion Area 128 KB 16 KB x 8 000C_0000h 000B_FFFFh Legacy Video Area SMM Memory 128 KB 000A_0000h 0009_FFFFh DOS Area 0000_0000h 2 3 1 1 DOS Range Oh 9_ FFFFh The DOS area is 640 KB 0000_0000h 0009_F
171. combined with the Device Identification register uniquely identifies any PCI device B D F Type 0 0 0 PCI Address Offset 0 1h Reset Value Access Size Reset RST Description Value PWR p Vendor Identification Number VID sosen ucore ucore 186 standard identification for Intel DI D Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 0 0 PCI Address Offset 2 3h Reset Value 0100h Access RO FW RO V Size 16 bits Reset RST POP jaw Seis She sent Device Identification Number MSB DID_MSB RO FW 010h Uncore This is the upper part of device identification assigned to the processor Device Identification Number SKU DID_SKU Uncore This is the middle part of device identification assigned to the processor po roy om Device Identification Number LSB DI D_LSB 1 0 RO FW Uncore This is the lower part of device identification assigned to the processor Datasheet Volume 2 Processor Configuration Registers n t 2 5 3 PCI CMD PCI Command Register Since Device 0 does not physically reside on PCI_A many of the bits are not implemented B D F Type 0 0 0 PCI Address Offset 4 5h Reset Value 0006h Access RO RW Size 16 bits BIOS Optimal Default 00h Reset RST Description Value PWR P Back to Back Enable FB2B This bit controls whether or not th
172. ct to address 31 RW Oh Uncore remapping and accessing ihe protected memory regions may or may not be blocked by hardware For such requests software must not depend on hardware protection of the protected memory regions and instead program the DMA remapping page tables to not allow DMA to protected memory regions Remapping hardware access to the remapping structures are not subject to protected memory region checks DMA requests blocked due to protected memory region violation are not recorded or reported as remapping faults Hardware reports the status of the protected memory enable disable operation through the PRS field in this register Hardware implementations supporting DMA draining must drain any in flight translated DMA requests queued within the Root Complex before indicating the protected memory region as enabled through the PRS field a e o eea o Protected Region Status PRS RO V Oh Wacore This bit indicates the status of protected memory region s 0 Protected memory region s disabled 1 Protected memory region s enabled Datasheet Volume 2 Processor Configuration Registers E t 2 18 15 PLMBASE_REG Protected Low Memory Base Register This register sets up the base address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always
173. cted in the PME Status bit of the Root Status Register A PME interrupt is also generated if the PME Status bit of the Root Status Register is set when this bit is set from a cleared state If the bit changes from 1 to 0 and an interrupt is pending the interrupt is de asserted E 7 System Error on Fatal Error Enable SEFEE Controls the Root Complex s response to fatal errors Uncore 0 Disable No SERR generated on receipt of fatal error 1 Enable SERR should be generated if a fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Non Fatal Uncorrectable Error Enable SENFUEE Controls the Root Complex s response to non fatal errors Uncore 0 Disable No SERR generated on receipt of non fatal error 1 Enable SERR should be generated if a non fatal error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself System Error on Correctable Error Enable SECEE Controls the Root Complex s response to correctable errors Uncore 0 Disable No SERR generated on receipt of correctable error 1 Enable SERR should be generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port or by the Root Port itself ee EE EG 124 Datasheet Volume 2 Processor Configuration Registers 5 P e 2 6 44 LCTL2 Link Control 2 Register B D
174. d this bit is set when a MRL Sensor state change is detected If an MRL sensor is not implemented this bit must not be set Reserved for Power Fault Detected PFD If a Power Controller that supports power fault detection is implemented this bit is set when the Power Controller detects a power fault at this slot Note that depending on hardware Capability it is possible that a power fault can be detected at any time independent of the Power Controller Control setting or the occupancy of the slot If power fault detection is not supported this bit must not be set Reserved for Attention Button Pressed ABP If an Attention Button is implemented this bit is set when the attention button is pressed If an Attention Button is not supported this bit must not be set RCTL Root Control Register This register allows control of PCI Express Root Complex specific parameters The system error control bits in this register determine if corresponding SERRs are generated when our device detects an error reported in this device s Device Status register or when an error message is received across the link Reporting of SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command Register B D F Type Address Offset Reset Value Access Size 16 bits BIOS Optimal Default 000h Reset RST Description Value PWR p 0 6 0 PCI BC BDh 0000h RW RO sfe o pee System Error on Fatal Error Enable SEFE
175. d across PEG11 when MAE PCICMD11 1 is set VGA and MDA I O cycles can only be routed across PEG11 if IOAE PCICMD11 0 is set 72 Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 0 0 PCI Address Offset 87h Reset Value 00h Access RW Size S aad BIOS Optimal Default Reset RST OREG PEG10 MDA Present MDAP10 This bit works with the VGA Enable bits in the BCTRL register of Device 1 Function 0 to control the routing of processor initiated transactions targeting MDA compatible 1 O and memory address ranges This bit should not be set if Device 1 Function 0 VGA Enable bit is not set If Device 1 Function 0 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 1 Function 0 if the address is within the corresponding OBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h 0B7FFFh 1 0 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode RN Ungcorg Any O reference that includes the I O locations listed above or their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA
176. d is effective only when interrupt remapping is enabled and Extended 23 wo Uncore Interrupt Mode x2APIC mode is not enabled 0 Block Compatibility format interrupts 1 Process Compatibility format interrupts as pass through bypass interrupt remapping Hardware reports the status of updating this field through the CFIS field in the Global Status register The value returned on a read of this field is undefined pao of mf Rees 278 Datasheet Volume 2 Processor Configuration Registers 2 21 5 GSTS_REG Global Status Register This register reports general remapping hardware status B D F Type 0 0 0 VCOPREMAP Address Offset 1C 1Fh Reset Value 0000_0000h Access RO RO V Size 32 bits BIOS Optimal Default 00_0000h Translation Enable Status TES This bit indicates the status of DMA remapping hardware 0 DMA remapping hardware is not enabled 1 DMA remapping hardware is enabled Root Table Pointer Status RTPS This bit indicates the status of the root table pointer in hardware 0 Cleared by hardware when software sets the SRTP field in the Global Command register 1 Set by hardware when hardware completes the Set Root Table Pointer operation using the value provided in the Root Entry Table Address register Fault Log Status FLS 0 Cleared by hardware when software Sets the SFL field in the Global Command register 1 Set by hardware when hardware completes the Set Fault Log P
177. d memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 2 PCI Address Offset 28 2Bh Reset Value 0000_0000h Access RW Size 32 bits Reset RST D ipti Value PWR SseniprHon 0000 000 Prefetchable Memory Base Address PMBASEU 31 0 RW OR Uncore This field corresponds to A 63 32 of the lower limit of the prefetchable memory range that will be passed to PCI Express G Datasheet Volume 2 101 Processor Configuration Registers intel 2 6 20 PMLI MI TU1 Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Limit Address register are read write and correspond to address bits A 38 32 of the 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Note Prefetchable memory range is supported to allow segregation b
178. d memory writes disabling the bus master enable bit prevents this device from generating MSI interrupt messages or passing them from its secondary 2 RW Uncore bus to its primary bus Upstream memory writes reads peer writes reads and MSIs will all be treated as illegal cycles Writes are aborted Reads are aborted and will return Unsupported Request status or Master abort in its completion packet 1 This device is allowed to issue requests to its primary bus Completions for previously issued memory read requests on the primary bus will be issued when the data is available This bit does not affect forwarding of Completions from the primary interface to the secondary interface Memory Access Enable MAE 0 All of device memory space is disabled 1 RW Uncore 1 Enable the Memory and Pre fetchable memory address ranges defined in the MBASE MLIMIT PMBASE and PMLIMIT registers 10 Access Enable I OAE 0 All of device I O space is disabled RW U pons 1 Enable the I O address range defined in the OBASE and IOLIMIT registers 148 Datasheet Volume 2 Processor Configuration Registers intel 2 10 4 PCISTS6 PCI Status Register This register reports the occurrence of error conditions associated with primary side of the virtual Host PCIl Express bridge embedded within the Root port B D F Type 0 6 0 PCI Address Offset 6 7h Reset Value 0010h Access RW1C RO RO V Size bits BIOS Optimal Default
179. d or cycle is a read If MCHBAR is disabled only read access is allowed e MCHTMBAR gt MCHBAR Thermal Monitor 1 Cycle to memory from processor AND 2 AND Targets MCHTMBAR base OBAR gt GTTMMADR gt MCHBAR Follows I OBAR rules See GTTMMADR information above as well oP WON Datasheet Volume 2 27 2 3 4 3 2 3 4 4 2 3 4 5 28 Processor Configuration Registers Memory Remapping An incoming address referred to as a logical address is checked to see if it falls in the memory re map window The bottom of the re map window is defined by the value in the REMAPBASE register The top of the re map window is defined by the value in the REMAPLIMIT register An address that falls within this window is remapped to the physical memory starting at the address defined by the TOLUD register The TOLUD register must be 1 MB aligned Hardware Remap Algorithm The following pseudo code defines the algorithm used to calculate the DRAM address to be used for a logical address above the top of physical memory made available using re claiming IF ADDRESS_IN 38 20 gt REMAP_BASE 35 20 AND ADDRESS_IN 38 20 lt REMAP_LIMIT 35 20 THEN ADDRESS_OUT 38 20 ADDRESS_IN 38 20 REMAP_BASE 35 20 0000000b and TOLUD 31 20 ADDRESS_OUT 19 0 ADDRESS_IN 19 0 Programming Model The memory boundaries of interest are e Bottom of Logical Address Remap Window defined by the REMAPBASE register which is calculated
180. dation performed using the domain id specified by software in the DID field This could be in response to a domain selective or device selective invalidation request Device selective invalidation performed using the source id and domain id specified by software in the SID and FM fields This can only be in response to a device selective invalidation request wa o o eea o Function Mask FM Software may use the Function Mask to perform device selective invalidations on behalf of devices supporting PCI Express Phantom Functions This field specifies which bits of the function number portion least significant three bits of the SID field to mask when performing device selective invalidations The following encodings are defined for this field 33 32 RW Oh Uncore 00 No bits in the SID field masked 01 Mask most significant bit of function number in the SID field 10 Mask two most significant bit of function number in the SID field 11 Mask all three bits of function number in the SID field The context entries corresponding to all the source ids specified through the FM and SID fields must have to the domain id specified in the DID field Source ID SID This field indicates the source id of the device whose 31 16 RW 0000h Uncore corresponding context entry needs to be selectively invalidated This field along with the FM field must be programmed by software for device selective invalidation requests Os o eea
181. ddress offset Register bit descriptions are in the sections following the table Table 2 20 Integrated Graphics VT d Remapping Engine Register Address Map Sheet 1 of 2 Address Register r Capability Register 0000 7 Extended Capability Register 0000 0000 2 18 1Bh GCMD_REG Global Command Register 0000_0000h RO WO 1C 1Fh GSTS_REG Global Status Register 0000_0000h RO RO V Root Entry Table Address Register 0000_0000 Context Command Register 0800_0000 RW Rw V Fault Status Register BE E ROS V TS E He ee a e eee Protected High Memory Base Register 0000_0000 78 7Fh ae ae RE Protected High Memory Limit Register 0000 0000 0000_0000h 80 87h QH_REG Invalidation Queue Head Register pete 88 8Fh IQT_REG Invalidation Queue Tail Register 0000 0000 90 97h IQA_REG Invalidation Queue Address Register 000 0000 pew seen ave e mS Datasheet Volume 2 225 Processor Configuration Registers intel Table 2 20 Integrated Graphics VT d Remapping Engine Register Address Map Sheet 2 of 2 Address Register r i Sym Pesistermame ResetValue acess A8 ABhh IEADDR_REG invalidation Event Address Register 0000_0000h AC AFh IEUADDR_REG Invalidation Event Upper Address Register 0000_0000h Interrupt Remapping Table Address Register 0000_0000_ 7 Invalidate Address Register 0000 0000 OTLB Invalidate Register 0200 0000 RW V RW Fault Recording Low Register 0000 0000 Fault Recording High Register 0000 00
182. ddress register Datasheet Volume 2 279 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 1C 1Fh Reset Value 0000_0000h Access RO RO V Size 32 bits BIOS Optimal Default 00_0000h Reset RST ae js awe Gs Site esermton Compatibility Format Interrupt Status CFIS This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt remapping The value reported in this field is applicable only when interrupt 23 RO V Uncore remapping is enabled and Extended Interrupt Mode x2APIC mode is not enabled 0 Compatibility format interrupts are blocked 1 Compatibility format interrupts are processed as pass through bypassing interrupt remapping je o eea 2 21 6 RTADDR_REG Root Entry Table Address Register This register provides the base address of root entry table B D F Type 0 0 0 VCOPREMAP Address Offset 20 27h Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 00_0000_0000h Reset RST Description Value PWR P ssf o o peen o Root Table Address RTA This register points to base of page aligned 4 KB sized root entry table in system memory Hardware ignores and not implements bits 63 HAW where HAW is the host address width aa Te Rw 0900000 Umepre Software specifies the base address of the root entry table through this register and programs it in hardware through the
183. des an address towards DRAM if the incoming address is less than the value programmed in this register The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and TSEG BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by TSEG size to determine base of TSEG All the Bits in this register are locked in Intel TXT mode This register must be 1MB aligned when reclaim is enabled a f e j o eens o Lock LOCK RW KL Uncore This bit will lock all writeable settings in this register including itself Datasheet Volume 2 79 Processor Configuration Registers ERRSTS Error Status Register This register is used to report various error conditions using the SERR DMI messaging mechanism An SERR DMI message is generated on a zero to one transition of any of these flags if enabled by the ERRCMD and PCICMD registers These bits are set regardless of whether or not the SERR is enabled and generated After the error processing is complete the error logging mechanism can be unlocked by clearing the appropriate status bit by software writing a 1 to it B D F Type 0 0 0 PCI Address Offset C8 C9h Reset Value 0000h Access RW1cS Size 16 bits BIOS Optimal Default 0000h Reset RST ne joe ace fe Bite eon O O te eee ee Multiple bit DRAM ECC Error Flag DMERR If this bit is set to 1 a memory read data transfer had
184. dicates the length of time this Port requires to complete the transition from L1 to LO The value 010b indicates the range of 2 us to less than 4 us 000 Less than 1us 001 1 us to less than 2 us 010 2 us to less than 4 us 17 15 RW O 010b Uncore 011 4 us to less than 8 us 100 8 us to less than 16 us 101 16 us to less than 32 us 32 us 64 us 111 More than 64 us Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate and undesired value from ever existing LOs Exit Latency LOSELAT This field indicates the length of time this Port requires to complete the transition from LOs to LO 000 Less than 64 ns 001 64 ns to less than 128 ns 14 12 010b Uncore 010 128 ns to less than 256 ns 011 256 ns to less than 512 ns 100 512 ns to less than 1 us 101 1 us to less than 2 us 110 2 us 4 us 111 More than 4 us 11 10 Wncore Active State Link PM Support ASLPMS LOs amp L1 entry supported Max Link Width MLW 04h Uncore This field indicates the maximum number of lanes supported for this link Max Link Speed MLS This Reset Value reflects gen1 3 0 RW OV 0001b Uncore 0001 2 5 GT s Link speed supported 0010 5 0 GT s and 2 5 GT s Link speeds supported All other combinations are reserved Datasheet Volume 2 201 t i Processor Configuration Registers 2 12 20 LCTL Link Control Register This register allows control of
185. dress Offset 68 6Fh Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 0_0000_0000h Reset RST ees jee ew fie pik meee ss e m pema ooo DMI Base Address DMI BAR This field corresponds to bits 38 12 of the base address DMI configuration space BIOS will program this register resulting in a base address for a 4 KB block of contiguous memory address 38 12 0000000h Uncore space This register ensures that a naturally aligned 4 KB space is allocated within the first 512 GB of addressable memory space System Software uses this base address to program the DMI register set All the Bits in this register are locked in Intel TXT mode mafo o pee oo DMI BAR Enable DMI BAREN 0 Disabled DMIBAR is disabled and does not claim any memory RW Uncore 1 Enabled DMIBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers ntel 2 5 16 PAMO Programmable Attribute Map 0 Register This register controls the read write and shadowing attributes of the BIOS range from F_0000h to F_FFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits a
186. e Writes to Reserved registers have no effect on the processor Registers that are marked as Intel Reserved must not be modified by system software Writes to Intel Reserved registers may cause system failure Reads from Intel Reserved registers may return a non zero value Upon a Full Reset the processor sets its entire set of internal configuration registers to predetermined default states Some register values at reset are determined by external strapping options The default state represents the minimum functionality feature set required to successfully bringing up the system Hence it does not represent the optimal system configuration It is the responsibility of the system initialization software usually BIOS to properly determine the DRAM configurations operating parameters and optional system features that are applicable and to program the processor registers accordingly Datasheet Volume 2 45 2 5 Table 2 7 46 Processor Configuration Registers 1 O Mapped Registers The processor contains two registers that reside in the processor I O address space the Configuration Address CONFIG_ADDRESS Register and the Configuration Data CONFIG_DATA Register The Configuration Address Register enables disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window PCI Device 0 Function 0 Configuration Registers Table 2 7 lists the registers arranged by
187. e esermton Selectable De emphasis selectabledeemphasis When the Link is operating at 5GT s speed selects the level of de emphasis Encodings 1 3 5 dB Powerg 0 6 dB RWS d me F a ies i 00 Reset Value is implementation specific unless a specific value is required for a selected form factor or platform When the Link is operating at 2 5 GT s speed the setting of this bit has no effect Components that support only the 2 5 GT s speed are permitted to hardwire this bit to Ob A Enter Compliance EC Power Software is permitted to force a link to enter Compliance mode at RWS ood 9 the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link Target Link Speed TLS For Downstream ports this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences Defined encodings are 0001 2 5 Gb s Target Link Speed 0010 5Gb s Target Link Speed All other encodings are reserved 3 0 RWS 2h Powerg If a value is written to this field that does not correspond to a speed included in the Supported Link Speeds field the result is undefined The Reset Value of this field is the highest link speed supported by the component as reported in the Supported Link Speeds field of the Link Capabilities Register unless the corresponding platform form factor requires a di
188. e 0 2 0 PCI Address Offset 20 23h Reset Value 0000_0001h Access RW RO Size 32 bits BIOS Optimal Default 00000h 000h FLR I eset aa ee Base Address I OBASE Uncore Set OO the OS these bits correspond to address signals 15 6 Memory Type Ee a e e e a Memory 10 Space MI OS o ro a oneee Fare to 1 ro ieme O space OOOO 2 8 13 SVI D2 Subsystem Vendor Identification Register This register is used to uniquely identify the subsystem where the PCI device resides B D F Type 0 2 0 PCI Address Offset 2C 2Dh Reset Value 0000h Access RW O Size 16 bits jw awe st Site esermton Subsystem Vendor ID SUBVID This value is used to identify the vendor of the subsystem This 15 0 RW O 0000h Uncore register should be programmed by BIOS during boot up Once written this register becomes Read Only This register can only be cleared by a Reset 140 Datasheet Volume 2 Processor Configuration Registers ntel 2 8 14 SID2 Subsystem Identification Register This register is used to uniquely identify the subsystem where the PCI device resides B D F Type 0 2 0 PCI Address Offset 2E 2Fh Reset Value 0000h Access RW O Size 16 bits Reset RST Description Value PWR p Subsystem Identification SUBI D This value is used to identify a particular subsystem This field 15 0 RW O 0000h Uncore should be programmed by BIOS during boot up Once written this register becomes Read Only This regis
189. e 1 Not ECC capable Ca fem ema Oooo i VT d Disable VTDD 23 RO KFW Uncore 0 Enable VT d 1 Disable VT d Ca fom ree o Can fron ee Reeves Ca fom o eena o EA a E N SS E moj fena SCS 2 DIMMS per Channel Disable DDPCD Allows Dual Channel operation but only supports 1 DIMM per channel RO FW Uncore 2 DIMMs per channel enabled 2 DIMMs per channel disabled This setting hardwires bits 2 and 3 of the rank population field for each channel to zero MCHBAR offset 260h bits 22 23 for channel 0 and MCHBAR offset 660h bits 22 23 for channel 1 efron me aes Co fom o eena o Ca fee o eea o Co foem o eena O o om o eena o Datasheet Volume 2 83 84 B D F Type Address Offset Default Value Access Size BIOS Optimal Default Processor Configuration Registers 0 0 0 PCI E4 E7h 0000_0000h RO FW RO KFW 32 bits 000000h pone ne iat Pun Sci oe o e O o a e a RO FW 000b DDR3 Maximum Frequency Capability DMFC This field controls which values may be written to the Memory Frequency Select field 6 4 of the Clocking Configuration registers MCHBAR Offset C00h Any attempt to write an unsupported value will be ignored 000 MC capable of All memory frequencies 101 Reserved 110 MC capable of up to DDR3 1333 111 MC capable of up to DDR3 1067 Datasheet Volume 2 Processor Configuration Registers 2 6 Table 2 8 intel PCI Device 1 Function 0
190. e implementations on platforms supporting Intel TXT are required to support protected high memory region6 if the platform supports main memory above 4 GB Once the protected low high memory region registers are configured bus master protection to these regions is enabled through the Protected Memory Enable register For platforms with multiple DMA remapping hardware units each of the DMA remapping hardware units must be configured with the same protected memory regions and enabled DRAM Protected Range DPR This protection range only applies to DMA accesses and GMADR translations It serves a purpose of providing a memory range that is only accessible to processor streams The DPR range works independent of any other range including the PMRC checks in VT d It occurs post any VT d translation Therefore incoming cycles are checked against this range after the VT d translation and faulted if they hit this protected range even if they passed the VT d translation The system will set up e Oto TSEG_BASE DPR size 1 for DMA traffic e TSEG_BASE to TSEG_BASE DPR size as no DMA After some time software could request more space for not allowing DMA It will get some more pages and make sure there are no DMA cycles to the new region DPR size is changed to the new value When it does this there should not be any DMA cycles going to DRAM to the new region If there were cycles from a rogue device to the new region then those co
191. e non prefetchable with the values that provide exclusive address ranges that is prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the processor hardware to enforce prevention of overlap and operations of the system in the case of overlap are not ensured B D F Type 0 6 0 PCI Address Offset 22 23h Reset Value 0000h Access RW Size a bits BIOS Optimal Default Memory Address Limit MLI MIT 000h Uncore This field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G se ee nese Reset RST Description Value PWR p Datasheet Volume 2 157 m t 1 Processor Configuration Registers 2 10 17 PMBASE6 Prefetchable Memory Base Address Register This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Base Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address ra
192. e 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 28 2Bh Reset Value 0000_ 0000h Access RW Size 32 bits Reset RST Description Value PWR 0000 000 Prefetchable Memory Base Address PMBASEU 31 0 RW oh Uncore This field corresponds to A 63 32 of the lower limit of the prefetchable memory range that will be passed to PCI Express G 160 Datasheet Volume 2 Processor Configuration Registers n t 2 10 20 2 10 21 PMLI MI TU6 Prefetchable Memory Limit Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Limit Address register are read write and correspond to address bits A 38 32 of the 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0
193. e Capability register The alignment of the protected low memory region limit depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position with O in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The Protected low memory base and limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits 31 N 1 specifies a protected low memory region of size 2 N 1 bytes e Programming the protected low memory limit register with a value less than the protected low memory base register disables the protected low memory region Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 6C 6Fh Reset Value 0000_ 0000h Access RW Size 32 bits BIOS Optimal Default 00000h Protected Low Memory Limit PLML 000h Uncore This field specifies the last host physical address of the DMA protected low memory region in system memory oo o eea Reset RST Description Value PWR p 246 Datasheet Volume 2 Processor Configuration Registers n t 2 18 17 PHMBASE_ REG Protected High Memory Base Register This register sets up the base address of DMA protected high memory region This register must be set
194. e Global Command register When implemented reads of this field return the value that was last programmed to it Fault Log Size FLS This field specifies the size of the fault log region pointed by the FLA field The size of the fault log region is 2 X 4KB where X is the value programmed in this register When implemented reads of this field return the value that was last programmed to it intel Processor Configuration Registers 2 21 14 PMEN_REG Protected Memory Enable Register 288 This register enables the DMA protected memory regions setup through the PLMBASE PLMLIMT PHMBASE PHMLIMIT registers This register is always treated as RO for implementations not supporting protected memory regions PLMR and PHMR fields reported as Clear in the Capability register Protected memory regions may be used by software to securely initialize remapping structures in memory To avoid impact to legacy BIOS usage of memory software is recommended to not overlap protected memory regions with any reserved memory regions of the platform reported through the Reserved Memory Region Reporting RMRR structures B D F Type 0 0 0 VCOPREMAP Address Offset 64 67h Reset Value 0000_ 0000h Access RW RO V Size 32 bits BIOS Optimal Default 0000_ 0000h Reset RST Description Value PWR p Enable Protected Memory EPM This field controls DMA accesses to the protected low memory and protected high memory regions 0 Protect
195. e Parity Error Enable bit in the Bridge Control register is set Wincore Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 e fo p o eea Uncore 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 oe o eea o Datasheet Volume 2 Processor Configuration Registers n t 2 6 15 MBASE1 Memory Base Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 1 0 2 PCI Address Offset 20 21h Reset Value FFFOh Access RW Size 16 bits BIOS Optimal Default Oh Reset RST ar fone ver St te mesenmton O Memory Address Base MBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G ofe o ee Datasheet Volume 2 97 m t 1 Processor Configuration Registers Note Note 98 MLI MI T1 Memory Limit Addres
196. e Slot Power Limit Value 00 1 0x 01 0 1x 10 0 01x 11 0 001x If this field is written the link sends a Set_Slot_Power_Limit message Slot Power Limit Value SPLV In combination with the Slot Power Limit Scale value this field specifies the upper limit on power supplied by slot Power limit in Watts is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set_Slot_Power_Limit message Reserved for Hot plug Capable HPC When set to 1b this bit indicates that this slot is capable of supporting hot plug operations Reserved for Hot plug Surprise HPS When set to 1b this bit indicates that an adapter present in this slot might be removed from the system without any prior notification This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation Reserved for Power Indicator Present PIP When set to 1b this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot Reserved for Attention Indicator Present Al P When set to 1b this bit indicates that an Attention Indicator is electrically controlled by the chassis Reserved for MRL Sensor Present MSP When set to 1b this bit indicates that an MRL Sensor is implemented on the chassis for this slot Reserved for Power Controlle
197. e This is a 7 bit value that indicates the Header Code for the IGD This code has the value 00h indicating a type 0 configuration space format Datasheet Volume 2 137 138 Processor Configuration Registers GTTMMADR Graphics Translation Table Memory Mapped Range Address Register This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range The range requires 4 MB combined for MMIO and Global GTT aperture with 2MB of that used by MMIO and 2 MB used by GTT GTTADR will begin at GTTMMADR 2 MB while the MMIO base address will be the same as GTTMMADR For the Global GTT this range is defined as a memory BAR in graphics device configuration space It is an alias into which software is required to write Page Table Entry values PTEs Software may read PTE values from the global Graphics Translation Table GTT PTEs cannot be written directly into the global GTT memory area The device snoops writes to this region in order to invalidate any cached translations within the various TLBs implemented on chip The allocation is for 4 MB and the base address is defined by bits 38 22 B D F Type 0 2 0 PCI Address Offset 10 17h Reset Value 0000_0000_0000_0004h Access RW RO Size 64 bits Reset RST Description Value PWR FLR Reserved for Memory Base Address RSVDRW 63 39 RW 0000000h 62 38 Rw oo00000h Fee Must be set to 0 since addressing above 51
198. e master can do fast back to back write Since device 0 is strictly a target this bit is not implemented and is hardwired to 0 Writes to this bit position have no effect SERR Enable SERRE This bit is a global enable bit for Device 0 SERR messaging The processor communicates the SERR condition by sending an SERR message over DMI to the PCH 1 The processor is enabled to generate SERR messages over DMI for specific Device 0 error conditions that are individually enabled in the ERRCMD and DMIUEMSK registers The error status is reported in the ERRSTS PCISTS and DMIUEST registers 0 The SERR message is not generated by the Host for Device 0 This bit only controls SERR messaging for Device 0 Other integrated devices have their own SERRE bits to control error reporting for error conditions occurring in each device The control bits are used in a logical OR manner to enable the SERR DMI message mechanism 0 Device 0 SERR disabled 1 Device 0 SERR enabled Address Data Stepping Enable ADSTEP Address data stepping is not implemented in the processor and this bit is hardwired to 0 Writes to this bit position have no effect Parity Error Enable PERRE This bit controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set 0 Disable Master Data Parity Error bit in PCI Status register can NOT be set 1 Enable Master Data Parity Error bit in PCI Status register CAN be set VGA
199. e of I O space claimed by the PCI Express device Datasheet Volume 2 Processor Configuration Registers n t The processor also forwards accesses to the Legacy VGA I O ranges according to the settings in the PEG configuration registers BCTRL VGA Enable and PCICMD IOAE unless a second adapter monochrome is present on the DMI Interface PCI or ISA The presence of a second graphics adapter is determined by the MDAP configuration bit When MDAP is set the processor will decode legacy monochrome I O ranges and forward them to the DMI Interface The I O ranges decoded for the monochrome adapter are 3B4h 3B5h 3B8h 3B9h 3BAh and 3BFh Note that the PEG I O address range registers defined above are used for all I O space allocation for any devices requiring such a window on PCI Express The PCICMD register can disable the routing of O cycles to PCI Express 2 3 12 MCTP and KVM Flows Refer to the DMI2 specification for details MCTP cycles are not processed within the processor MCTP cycles are merely passed from input port to destination port based on routing ID 2 3 13 Decode Rules and Cross Bridge Address Mapping 2 3 13 1 DMI Interface Decode Rules All SNOOP semantic PCI Express transactions are kept coherent with processor caches All Snoop not required semantic cycles must reference the main DRAM address range PCI Express non snoop initiated cycles are not snooped The processor accepts accesses fr
200. e processor locates MMIO space above 4 GB using these registers Datasheet Volume 2 33 m t 1 Processor Configuration Registers 2 3 7 2 3 7 1 2 3 7 2 34 Graphics Memory Address Ranges The MCH can be programmed to direct memory accesses to IGD when addresses are within any of five ranges specified using registers in the processor Device 2 configuration space 1 The Graphics Memory Aperture Base Register GMADR is used to access graphics memory allocated using the graphics translation table 2 The Graphics Translation Table Base Register GTTADR is used to access the translation table and graphics control registers This is part of GTTMMADR register These ranges can reside above the Top of Low DRAM and below High BIOS and APIC address ranges They MUST reside above the top of memory TOLUD and below 4 GB so they do not steal any physical DRAM memory space Alternatively these ranges can reside above 4 GB similar to other BARs which are larger than 32 bits in size GMADR is a Prefetchable range in order to apply USWC attribute from the processor point of view to that range The USWC attribute is used by the processor for write combining 1 OBAR Mapped Access to Device 2 MMIO Space Device 2 integrated graphics device contains an IOBAR register If Device 2 is enabled then IGD registers or the GTT table can be accessed using this IOBAR The IOBAR is composed of an index register and a data register MMI O_Ind
201. e that this is a multi function device 7 0 81h Uncore with bridge header layout Device 6 returns O1h to indicate that this is a single function device with bridge header layout 2 6 9 PBUSN1 Primary Bus Number Register This register identifies that this virtual Host PCl Express bridge is connected to PCI bus 0 B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI 18h 00h RO 8 bits Reset RST Description Value PWR P Primary Bus Number BUSN Configuration software typically programs this field with the 7 0 00h Uncore number of the bus on the primary side of the bridge Since the processor root port is an internal device and its primary bus is always 0 these bits are read only and are hardwired to 0 Datasheet Volume 2 93 Processor Configuration Registers 2 6 10 SBUSN1 Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the virtual bridge that is to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI 19h 00h RW 8 bits Reset RST er jose ace Gates te tesermton O Secondary Bus Number BUSN 7 0 RW 00h Uncore This field is programmed by configuration software with the bus number assigned to PCI Express G 2 6 11 SUBUSN1 Subordinate
202. e this device is an integrated part of the system and not an add in device it is anticipated that this capability will never be used However it is necessary because Microsoft will test for its presence B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 6 0 PCI 88 8Bh 0000_800Dh RO 32 bits 0000h Reset RST Description Value PWR p aoj o o pee o Pointer to Next Capability PNC Uncore This contains a pointer to the next item in the capabilities list that is the PCI Power Management capability Datasheet Volume 2 Capability ID CID Uncore Value of ODh identifies this linked list item capability structure as being for SSID SSVID registers in a PCIl to PCI Bridge 167 intel Processor Configuration Registers 2 10 28 SS Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset B D F Type Address Offset Reset Value Access Size 0 6 0 PCI 8C 8Fh 0000_8086h RW O 32 bits Reset RST Description Value PWR P Subsystem ID SSID ape dence Identifies the particular subsystem and is assigned by the vendor 15 0 RW O Subsystem Vendor ID SSVI D Uncore Identifies the manufacturer of the subsystem and is the same as the vendor ID which is assigned by the PCI Special Interest Group
203. e type is deprecated and can only be used to describe bits without persistent state Read Clear These bits can only be read by software but a read causes the bits to be cleared Hardware sets these bits Note Use of this attribute type is only allowed on legacy functions as side effects on reads are not desirable Read Set Write 1 to Clear These bits can be read and cleared by software Reading a bit will set the bit to 1 Writing a 1 to a bit will clear it while writing a 0 to a bit has no effect Read Clear Write These bits can be read and written by software but a read causes the bits to be cleared Note Use of this attribute type is only allowed on legacy functions as side effects on reads are not desirable Datasheet Volume 2 13 Processor Configuration Registers intel Table 2 2 Register Attribute Modifiers Attribute Applicable are RO w V Sticky These bits are only re initialized to their default value by a Power Good Reset RW1C Note Does not apply to RO constant bits Key These bits control the ability to write other bits identified with a Lock modifier Lock Hardware can make these bits Read Only via a separate configuration bit or other logic Note Mutually exclusive with Once modifier Once After reset these bits can only be written by software once after which they become Read Only Note Mutually exclusive with Lock modifier and does not make sens
204. e with Variant modifier Firmware Write The value of these bits can be updated by firmware PCU TAP etc RO Variant The value of these bits can be updated by hardware Note RWI1C and RC bits are variant by definition and therefore do not need a to be modified 2 2 PCI Devices and Functions on Processor e ee e Integrated Graphics Device 010Ah ae a ee PCI Express Controller 010Dh a f ee Note 1 Not all devices are enabled in all configurations 2 See Section 2 8 2 DID2 Device Identification Register for additional information on graphics DID values 14 Datasheet Volume 2 Processor Configuration Registers n t 2 3 System Address Map The processor supports 512 GB 39 bit of addressable memory space and 64 KB 3 of addressable I O space This section focuses on how the memory space is partitioned and what the separate memory regions are used for I O address space has simpler mapping and is explained near the end of this section The processor supports PEG port upper prefetchable base limit registers This allows the PEG unit to claim I O accesses above 32 bit Addressing of greater than 4 GB is allowed on either the DMI Interface or PCI Express interface The processor supports a maximum of 32 GB of DRAM No DRAM memory will be accessible above 32 GB DRAM capacity is limited by the number of address pins available There is no hardware lock to stop someone from inserting more
205. earing the IVT field At this time the granularity at which actual invalidation was performed is reported through the IAIG field ens Datasheet Volume 2 299 300 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 108 10Fh Reset Value 0000_0000_0000_0000h Access RW RO V RW V Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RST ae jw awe ss Sie esermton 1OTLB Actual I nvalidation Granularity 1 Al G Hardware reports the granularity at which an invalidation request was processed through this field when reporting invalidation completion by clearing the IVT field The following are the encodings for this field 00 Reserved This indicates hardware detected an incorrect invalidation request and ignored the request Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page selective invalidation requests 58 57 RO V Oh Uncore 01 Global Invalidation performed This could be in response to a global domain selective or page selective invalidation request 10 Domain selective invalidation performed using the domain id specified by software in the DID field This could be in response to a domain selective or a page selective invalidation request 11 Domain page selective invalidation performed using the address mask and hint specified by software in the Invalidate Address re
206. eceee teen eee teen e ee ee eee tentials 133 2 8 3 PCICMD2 PCI Command ReGiStel ceceee eee ee eee eee eee eee a teeta een eeataes 134 2 8 4 PCISTS2 PCI Status REgIStep secar nirca n ks nenni eee eee teens Eaa teen neat eee 135 2 8 5 RID2 Revision Identification REGiSter ccc cece eee e cent eee ee eee teen tent ees 136 2 8 6 CC Class Code REISTER sisi Antivir aii eTEN EREE NSE i 136 2 8 7 CLS Cache Line Size Register cece tee eee eens 137 2 8 8 MTXT2 Master Latency Timer ReEQISter cece eect ee ee eee ee teeta teat ees 137 2 8 9 HDR2 Header Type ReGiSter c cece cee eee ee eee eee e ee ee eee eee ee teeta eae en tentials 137 2 8 10 GTTMMADR Graphics Translation Table Memory Mapped Range Address ReGiSter ccccecee cette eee ee eee ee eee e ee eae eae eaeeeeaes 138 2 8 11 GMADR Graphics Memory Range Address Register eeeeeeeee eee ea ees 139 2 8 12 IOBAR I O Base Address Register cccceceece eee ee ene ee treet eae te eee eneeatees 140 2 8 13 SVID2 Subsystem Vendor Identification Register cceceeeee ene e eee 140 2 8 14 SID2 Subsystem Identification Register cece eee eee nett eee e enna 141 2 8 15 ROMADR Video BIOS ROM Base Address Register eceeeeee eee e ee eae 141 2 8 16 INTRPIN Interrupt Pin ReQiSter cece eter e cent eee ee eee eee ee eee ne ene eneees 141 2 8 17 MINGNT Minimum Grant Register c
207. ed e Upstream reads and writes above TOUUD are treated as invalid cycles e Remapped addresses remap starting at TOLUD They do not remap starting at TSEG_BASE DMI and PEG need to be careful with this for both snoop and non snoop accesses In other words for upstream accesses the range between TOLUD GfxStolensize GFXGTTstolensize TSEGSIZE DPR to TOLUD will never map directly to memory Accesses from PEG DMI should be decoded as to the type of access before they are remapped For instance a DMI write to FEEX_xxxx is an interrupt transaction but there is a DMI address that will be re mapped to the DRAM address of FEEXx_xxxx In all cases the remapping of the address is done only after all other decodes have taken place Unmapped Addresses between TOLUD and 4 GB Accesses that do not hit DRAM or PCI space are subtractive decoded to DMI Because the TOLUD register is used to mark the upper limit of DRAM space below the 4 GB boundary no address between TOLUD and 4 GB ever decodes directly to main memory Thus even if remap is disabled any address in this range has a non memory destination The top of DRAM address space is either e TOLUD if there is less then 4 GB of DRAM or 32 bit addressing or e TOUUD if there is more than 4 GB of DRAM and 36 bit addressing The system address space includes the remapped range For instance if there is 8 GB of DRAM and 1 GB of PCI space the system has a 9 GB address space where DRAM lies fr
208. ed 10 above TOM On FSB chipsets the TOM was used to allocate the Manageability Engine s stolen memory The Manageability Engine s ME stolen size register reflects the total amount of physical memory stolen by the Manageability Engine The ME stolen memory is located at the top of physical memory The ME stolen memory base is calculated by subtracting the amount of memory stolen by the Manageability Engine from TOM Top of Upper Usable DRAM TOUUD The Top of Upper Usable Dram TOUUD register reflects the total amount of addressable DRAM If remap is disabled TOUUD will reflect TOM minus Manageability Engine s stolen size If remap is enabled then it will reflect the remap limit Note when there is more than 4 GB of DRAM and reclaim is enabled the reclaim base will be the same as TOM minus ME stolen memory size to the nearest 1 MB alignment shown in case 2 below Top of Low Usable DRAM TOLUD TOLUD register is restricted to 4 GB memory A 31 20 but the processor can support up to 32 GB limited by DRAM pins For physical memory greater than 4 GB the TOUUD register helps identify the address range between the 4 GB boundary and the top of physical memory This identifies memory that can be directly accessed including remap address calculation which is useful for memory access indication and early path indication TOLUD can be 1 MB aligned TSEG_BASE The TSEG_BASE register reflects the total amount of low addressable D
209. ed as unsupported requests No pacer arbitration or TWRR arbitration will occur Never remaps to different port PCH takes care of Egress port remapping The PCH will meter TCm ME accesses and Azalia TC1 access bandwidth Internal Graphics GMADR writes and GMADR reads are not supported Datasheet Volume 2 Processor Configuration Registers Figure 2 7 e VCm accesses intel See the DMI2 specification for TC mapping to VCm VCm access only map to ME stolen DRAM These transactions carry the direct physical DRAM address no redirection or remapping of any kind will occur This is how the PCH Manageability engine accesses its dedicated DRAM stolen space DMI block will decode these transactions to ensure only ME stolen memory is targeted and abort otherwise VCm transactions will only route non snoop VCm transactions will not go through VT d remap tables The remapbase remaplimit registers to not apply to VCm transactions Example DMI Upstream VCO Memory Map Upstream Initiated VCO Cycle Memory Map REMAPLIMIT REMAPBASE 4GB FEE0_0000 FEEF_FFFF MSI TOM total physical DRAM TOLUD Gfx Stolen Gfx GTT stolen TSEG_BASE TSEG TSEG_BASE DPR A0000 BFFFF VGA mem writes gt peer write if matching PEG range else invalid mem reads gt Invalid transaction mem writes gt Route based on SNR bit mem reads gt Route based on SNR bit mem writes gt CPU I
210. ed memory regions are disabled 1 Protected memory regions are enabled DMA requests accessing protected memory regions are handled as follows When DMA remapping is not enabled all DMA requests accessing protected memory regions are blocked When DMA remapping is enabled DMA requests processed as pass through Translation Type value of 10b in Context Entry and accessing the protected memory regions are blocked DMA requests with translated address AT 10b and accessing the protected memory regions are blocked DMA requests that are subject to address 31 RW Oh Uncore remapping and accessing the protected memory regions may or may not be blocked by hardware For such requests software must not depend on hardware protection of the protected memory regions and instead program the DMA remapping page tables to not allow DMA to protected memory regions Remapping hardware access to the remapping structures are not subject to protected memory region checks DMA requests blocked due to protected memory region violation are not recorded or reported as remapping faults Hardware reports the status of the protected memory enable disable operation through the PRS field in this register Hardware implementations supporting DMA draining must drain any in flight translated DMA requests queued within the Root Complex before indicating the protected memory region as enabled through the PRS field a e o eea o Protected Region Status PR
211. ed to communicate with IOAPIC interrupt controllers that may be populated in the system Since it is difficult to relocate an interrupt controller using plug and play software fixed address decode regions have been allocated for them Processor accesses to the default IOAPIC region FECO_0000h to FEC7_FFFFh are always forwarded to DMI The processor optionally supports additional O APICs behind the PCI Express Graphics port When enabled using the APIC_BASE and APIC_LIMIT registers mapped PCI Express Configuration space offset 240h and 244h the PCI Express port s will positively decode a subset of the APIC configuration space Memory requests to this range would then be forwarded to the PCI Express port This mode is intended for the entry Workstation Server SKUs of the processor and would be disabled in typical Desktop systems When disabled any access within entire APIC Configuration space FECO_0000h to FECF_FFFFh is forwarded to DMI 2 3 3 2 HSEG FEDA_ 0000h FEDB_FFFFh This decode range is not supported on the Intel Xeon processor E3 1200 family platform 2 3 3 3 MSI Interrupt Memory Space FEE0_0000h FEEF_FFFFh Any PCI Express or DMI device may issue a Memory Write to OFEEx_xxxxh This Memory Write cycle does not go to DRAM The system agent will forward this Memory Write along with the data to the processor as an Interrupt Message Transaction 2 3 3 4 High BIOS Area For security reasons the processor will p
212. ee eee e eee e een eee 212 2 14 1 TC_DBP_C1 Timing of DDR Bin Parameters Register cee eee ees 212 2 14 2 TC_RAP_C1 Timing of DDR Regular Access Parameters Register 213 2 14 3 SC _1O_LATENCY_C1 IO Latency Configuration Register ce 213 2 14 4 TC_SRFTP_C1 Self Refresh Timing Parameters Register ccce 214 2 14 5 PM_PDWN_Config_C1 Power down Configuration Register 00 214 2 14 6 ECCERRLOGO_C1 ECC Error Log 0 Register cee ece cece cece e eee ne ee eee tees 215 2 14 7 ECCERRLOG1_C1 ECC Error Log 1 Register cceeceeeee eee eee ne eee ee eae 215 2 14 8 TC_RFP_C1l Refresh Parameters Register c eect eee 216 2 14 9 TC_RFTP_C1 Refresh Timing Parameters Register cceeeeeee eens eee 216 2 15 MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub IMPH cceceee eee e eee e eect eee ee eee ee tee ne ent ees 217 2 15 1 CRDTCTL3 Credit Control 3 ReQiSter cceceeeee eect eee eee eee eee eet eee een ees 217 2 16 MCHBAR Registers in Memory Controller COMMON ccceeeee ee eee eee ee eee eee eta eee 218 2 16 1 MAD_CHNL Address Decoder Channel Configuration Register 218 2 16 2 MAD_DIMM_ch0O Address Decode Channel 0 Register c cece 219 2 16 3 MAD_DIMM_ch1 Address Decode Channel 1 Register sssrrerrrrrrrrren 220 2 16 4 PM_SREF_config Self Refresh Configuratio
213. egister contains bits 38 20 of an address one byte above the maximum DRAM memory above 4 GB that is usable by the operating system Configuration software must set this value to TOM minus all ME stolen memory if reclaim is disabled If reclaim is k enabled this value must be set to reclaim limit 1 MB aligned since 38 20 RWE 00000h Uneorg reclaim limit 1 byte is 1 MB aligned Address bits 19 0 are assumed to be 000_0000h for the purposes of address comparison The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register and greater than 4 GB All the bits in this register are locked in Intel TXT mode ma e o eea o Lock LOCK RW KL Uncore This bit will lock all writeable settings in this register including itself Datasheet Volume 2 Processor Configuration Registers 2 5 28 intel BDSM Base Data of Stolen Memory Register This register contains the base address of graphics data stolen DRAM memory BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size PCI Device 0 offset 52 bits 7 4 from TOLUD PCI Device 0 offset BCh bits 31 20 B D F Type Address Offset Reset Value 0 0 0 PCI BO B3h 0000_ 0000h Access RW KL RW L Size 32 bits BIOS Optimal Default 00000h Reset RST PA jw awe Ses Sie sermon Graphics Base of Stolen Memory BDSM This register contains
214. emap engine registers GFXVTBAR 3 TCm accesses to ME stolen memory from PCH do not go through VT remap engines Some of the MMIO Bars may be mapped to this range or to the range above TOUUD Datasheet Volume 2 23 Figure 2 4 24 Processor Configuration Registers There are sub ranges within the PCI Memory address range defined as APIC Configuration Space MSI Interrupt Space and High BIOS Address Range The exceptions listed above for internal graphics and the PCI Express ports MUST NOT overlap with these ranges PCI Memory Address Range FFFF_FFFFh FFEO_0000h FEFO_0000h FEEO_0000h FEDO_0000h High BIOS DMI Interface subtractive decode MSI Interrupts DMI Interface subtractive decode FEC8_0000h Local CPU APIC FECO_0000h F000_0000h E000_0000h I O APIC DMI Interface subtractive decode 4 GB 256 MB PCI Express Configuration Space Possible address range size not ensured 4 GB 512 MB DMI Interface subtractive decode BARs Internal Graphics ranges PCI Express Port CHAPADR could be here TOLUD Datasheet Volume 2 Processor Configuration Registers 2 3 3 1 APIC Configuration Space FECO_0000h FECF_FFFFh This range is reserved for APIC configuration space The I O APIC s usually reside in the PCH portion of the chip set but may also exist as stand alone components like PXH The IOAPIC spaces are us
215. emented Hardwired to 0 Since the IGD belongs to the Uncore category of devices that does not corrupt programs or data in system memory or hard drives the IGD ignores any parity error that it detects and continues with normal operation Video Palette Snooping VPS 5 Uncore Reine This bit is hardwired to 0 to disable snooping Memory Write and Invalidate Enable MWIE Uncore Hardwired to 0 The IGD does not support memory write and invalidate commands Special Cycle Enable SCE 3 Uncore Seca This bit is hardwired to 0 The IGD ignores Special cycles FIR Bus Master Enable BME 2 RW Uncore 0 Disable IGD bus mastering 1 Enable the IGD to function as a PCI compliant master Memory Access Enable MAE FLR This bit controls the IGD s response to memory space accesses 1 RW U ncore 0 Disable 1 Enable I O Access Enable I OAE FLR This bit controls the IGD s response to I O space accesses RW U ncore 0 Disable 1 Enable 134 Datasheet Volume 2 Processor Configuration Registers 2 8 4 intel PCI STS2 PCI Status Register PCISTS is a 16 bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort PCISTS also indicates the DEVSEL timing that has been set by the IGD B D F Type 0 2 0 PCI Address Offset 6 7h Reset Value 0090h Access RO RO V Size bits BIOS Optimal Default Reset RST GCEIST Detected Parity Error D
216. en more than one bit in this field is set it indicates that the VC resource can be configured to provide different arbitration services Software selects among these capabilities by writing to the Port Arbitration Select field see below 7 0 Olh Uncore Defined bit positions are Bit 0 Non configurable hardware fixed arbitration scheme such as Round Robin RR Bit 1 Weighted Round Robin WRR arbitration with 32 phases Bit 2 WRR arbitration with 64 phases Bit 3 WRR arbitration with 128 phases Bit 4 Time based WRR with 128 phases Bit 5 WRR arbitration with 256 phases Bits 6 7 Reserved Processor only supported arbitration indicates Non configurable hardware fixed arbitration scheme Datasheet Volume 2 185 intel 2 11 5 186 Processor Configuration Registers VCORCTL VCO Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0 B D F Type 0 6 0 MMR Address Offset 114 117h Reset Value 8000_OOFFh Access RO RW Size 32 bits BIOS Optimal Default 000h Reset RST A jose ace e Ble on O O VCO Enable VCOE 31 1b Uncore For VCO this is hardwired to 1 and read only as VCO can never be disabled saf o o p peen o VCO ID VCOI D 26 24 000b Uncore Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only saj me om awed o Port Arbitration Select PAS This field configures the VC resource to provide a part
217. entifies the header layout of the configuration space No physical register exists at this location B D F Type 0 6 0 PCI Address Offset Eh Reset Value Olh Access RO Size 8 bits necer RST Description Value PWR P Header Type Register HDR Device 1 returns 81h to indicate that this is a multi function device 7 0 Olh Uncore with bridge header layout Device 6 returns O1h to indicate that this is a single function device with bridge header layout 2 10 9 PBUSN6 Primary Bus Number Register This register identifies that this virtual Host PCl Express bridge is connected to PCI bus 0 B D F Type Address Offset Reset Value 0 6 0 PCI 18h 00h Access RO Size 8 bits Reset RST Description Value PWR p Primary Bus Number BUSN Configuration software typically programs this field with the 7 0 00h Uncore number of the bus on the primary side of the bridge Since the processor root port is an internal device and its primary bus is always 0 these bits are read only and are hardwired to 0 152 Datasheet Volume 2 Processor Configuration Registers intel 2 10 10 SBUSN6 Secondary Bus Number Register This register identifies the bus number assigned to the second bus side of the virtual bridge that is to PCI Express G This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI Express G B D F Type Address Offset Reset Value
218. eported using this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space Capability ID CID 7 0 10h Uncore This field identifies this linked list item capability structure as being for PCI Express registers Datasheet Volume 2 170 Processor Configuration Registers 2 10 34 PEG _CAP PCI Express G Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 6 0 PCI Address Offset A2 A3h Reset Value 0142h Access RO RW O Size a bits BIOS Optimal Default Reset RST Description Value PWR P Interrupt Message e a ee IMN 13 9 00h U RIAA Not Applicable or Implemented Hardwired to 0 Slot I mplemented SI 0 The PCI Express Link associated with this port is connected to an integrated component or is disabled RW O 1b Uncore 1 The PCI Express Link associated with this port is connected to a slot BIOS Requirement This field must be initialized appropriately if a slot connection is not implemented Device Port Type DPT 7 4 4h U pra no an uncoe Hardwired to 4h to indicate root port of PCI Express Root Complex PCI Express Capability Version PCI ECV 3 0 2h Uncore Hardwired to 2h to indicate compliance to the PCI Express Capabilities Register Expansion ECN 2 10 35 DCAP Device Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 6 0 PCI Addres
219. er specific programming interface B D F Type Address Offset Reset Value 0 1 0 2 PCI 9 Bh 060400h Access RO Size 24 bits Reset RST Description Value PWR p EEGs fre me om fee 92 Base Class Code BCC This field indicates the base class code for this device This code has the value 06h indicating a Bridge device Sub Class Code SUBCC This field indicates the sub class code for this device The code is 04h indicating a PCI to PCI Bridge Programming I nterface PI This field indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device Datasheet Volume 2 Processor Configuration Registers intel 2 6 7 CL1 Cache Line Size Register B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI Ch 00h RW 8 bits Reser RST Description Value PWR P Cache Line Size CLS 7 0 RW 00h Uncore mplemented by PCI Express devices as a read write field for legacy compatibility purposes but has no impact on any PCI Express device functionality 2 6 8 HDR1 Header Type Register This register identifies the header layout of the configuration space No physical register exists at this location B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI Eh 81h RO 8 bits Ss Header Type Register HDR Device 1 returns 81h to indicat
220. ering of read and write cycles that address the BIOS area from 0C8000h to OCBFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are 1 0 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 65 66 Processor Configuration Registers PAM3 Programmable Attribute Map 3 Register This register controls the read write and shadowing attributes of the BIOS range from DOOOOh to D7FFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0O the host read accesses are directed to DMI WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0
221. es passed by the root port to PCI Express G oje o een IOLI MI T1 I O Limit Address Register This register controls the processor to PCI Express G I O access routing based on the following formula IO_BASE lt address lt IO_LIMIT Only upper 4 bits are programmable For the purpose of address decode address bits A 11 0 are assumed to be FFFh Thus the top of the defined I O address range will be at the top of a 4 KB aligned address block B D F Type 0 1 0 2 PCI Address Offset 1Dh Reset Value 00h Access RW Size 2 oo BIOS Optimal Default Reset RST Description Value PWR j 1 O Address Limit IOLI MIT This field corresponds to A 15 12 of the I O address limit of the ae us on nncorg root port Devices between this upper limit and IOBASE1 will be passed to the PCI Express hierarchy associated with this device ofe o eea Datasheet Volume 2 95 intel 2 6 14 96 Processor Configuration Registers SSTS1 Secondary Status Register SSTS is a 16 bit status register that reports the occurrence of error conditions associated with secondary side that is PCI Express G side of the virtual PCI PCI bridge embedded within the processor B D F Type 0 1 0 2 PCI Address Offset 1E 1Fh Reset Value 0000h Access RW1C RO Size 16 bits BIOS Optimal Default 00h Reset RST ae jose scr sist Be eseron Detected Parity Error DPE This bit is set by the Secondary Side for a
222. ese bytes enabled regardless of the other BEs C Else If VGA on PEG is enabled PEG gets x3BOh x3BBh x3COh x3CFh x3D0h x3DFh D Else if ISA Enable 1 DMI gets upper 768 bytes of each 1K block E Else IOBASE IOLIMIT apply Datasheet Volume 2 Processor Configuration Registers E t 2 4 Processor Register I ntroduction The processor contains two sets of software accessible registers accessed using the Host processor I O address space Control registers and internal configuration registers e Control registers are I O mapped into the processor I O space which control access to PCI and PCI Express configuration space see Section 2 4 1 e Internal configuration registers residing within the processor are partitioned into three logical device register sets logical since they reside within a single physical device The first register set is dedicated to Host Bridge functionality that is DRAM configuration other chipset operating parameters and optional features The second register block is dedicated to Host PCI Express Bridge functions controls PCI Express interface configurations and operating parameters The third register block is for the internal graphics functions The processor internal registers I O Mapped Configuration and PCI Express Extended Configuration registers are accessible by the Host processor The registers that reside within the lower 256 bytes of each device can be accessed as Byte
223. eserved for Data Link Layer State Changed DLLSC This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed In response to a Uncore Data Link Layer State Changed event software must read the Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device Reserved for Electromechanical I nterlock Status EIS If an Electromechanical Interlock is implemented this bit indicates Uncore the current status of the Electromechanical Interlock 0 Electromechanical Interlock Disengaged 1 Electromechanical Interlock Engaged Presence Detect State PDS In band presence detect state 0 Slot Empty 1 Card present in slot This bit indicates the presence of an adapter in the slot reflected by the logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power be applied to an adapter for its presence to be detected Consequently form factors that require a power controller for hot plug must implement a physical pin presence detect mechanism 0 Slot Empty 1 Card Present in slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to s
224. eset Value 0800_0000_0000_0000h Access RW RW V RO V Size 64 bits BIOS Optimal Default 000000000h Reset RST Description Value PWR Invalidate Context Cache ICC Software requests invalidation of context cache by setting this field Software must also set the requested invalidation granularity by programming the CIRG field Software must read back and check the ICC field is Clear to confirm the invalidation is complete Software must not update this register when this field is set Hardware clears the ICC field to indicate the invalidation request is complete Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field 63 RW V Oh Uncore Software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this remapping hardware unit Since information from the context cache may be used by hardware to tag IOTLB entries software must perform domain selective or global invalidation of IOTLB after the context cache invalidation has completed Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flush before invalidating the context cache Context I nvalidation Request Granularity CI RG Software provides the requested invalidation granularity through this field when setting the ICC field 00 Reserved 01 Global Invalidatio
225. essors I O reads that lie within 8 byte boundaries but cross 4 byte boundaries are issued from the processor as 1 transaction It will be broke into 2 separate transactions I O writes that lie within 8 byte boundaries but cross 4 byte boundaries will be split into 2 transactions by the processor PCI Express I O Address Mapping The processor can be programmed to direct non memory I O accesses to the PCI Express bus interface when processor initiated I O cycle addresses are within the PCI Express I O address range This range is controlled using the I O Base Address LOBASE and I O Limit Address IOLIMIT registers in Device 1 functions 0 1 2 or Device 6 configuration space Address decoding for this range is based on the following concept The top 4 bits of the respective I O Base and I O Limit registers correspond to address bits A 15 12 of an I O address For the purpose of address decoding the device assumes that lower 12 address bits A 11 0 of the I O base are zero and that address bits A 11 0 of the I O limit address are FFFh This forces the I O address range alignment to 4 KB boundary and produces a size granularity of 4 KB The processor positively decodes I O accesses to PCI Express I O address space as defined by the following equation 1 O_Base_Address lt processor I O Cycle Address lt I O_Limit_Address The effective size of the range is programmed by the plug and play configuration software and it depends on the siz
226. est Antel processor numbers are not a measure of performance Processor numbers differentiate features within each processor family not across different processor families See http www intel com products processor_number for details Over time processor numbers will increment based on changes in clock speed cache FSB or other features and increments are not intended to represent proportional or quantitative increases in any particular feature Current roadmap processor number progression is not necessarily representative of future roadmaps See www intel com products processor_number for details No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer system with Intel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured launched environment MLE The MLE could consist of a virtual machine monitor an OS or an application In addition Intel TXT requires the system to contain a TPM v1 2 as defined by the Trusted Computing Group and specific software for some uses For more information see http www intel com technology security Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will var
227. est address widths corresponding to various bit positions within this 12 8 00010b Uncore field are 0 30 bit AGAW 2 level page table 1 39 bit AGAW 3 level page table 2 48 bit AGAW 4 level page table 3 57 bit AGAW 5 level page table 4 64 bit AGAW 6 level page table Software must ensure that the adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field 228 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 GFXVTBAR Address Offset 8 Fh Reset Value 00CO_0000_20E6_0262h Access RO Size 64 bits BIOS Optimal Default 000h Reset RST os jw face Sets Be esermon Caching Mode CM 0 Not present and erroneous entries are not cached in any of the remapping caches Invalidations are not required for modifications to individual not present or invalid entries However any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective Not present and erroneous mappings may be cached in the remapping caches Any software updates to the remapping structures including updates to not present or erroneous entries require explicit invalidation Hardware implementations of this architecture must support a value of 0 in this field Protected High Memory Region PHMR 0 Protected high memory region is N
228. et in hardware through the SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Global Status register The value returned on read of this field is undefined 276 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 VCOPREMAP Address Offset 18 1Bh Reset Value 0000_0000h Access WO RO Size 32 bits BIOS Optimal Default 00_0000h Reset RST Description Value PWR P Write Buffer Flush WBF This bit is valid only for implementations requiring write buffer flushing Software sets this field to request that hardware flush the Root Complex internal write buffers This is done to ensure any updates 27 Uncore to the memory resident remapping structures are not held in any internal write posting buffers Hardware reports the status of the write buffer flushing operation through the WBFS field in the Global Status register Clearing this bit has no effect The value returned on a read of this field is undefined Queued I nvalidation Enable QIE This field is valid only for implementations supporting queued invalidations Software writes to this field to enable or disable queued invalidations Zo Wo ngore 0 Disable queued invalidations 1 Enable use of queued invalidations Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register
229. ex MMIO_INDEX is a 32 bit register A 32 bit all bytes enabled 1 O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed An I O Read returns the current value of this register An I O read write accesses less than 32 bits in size all bytes enabled will not target this register MMIO_ Data MMIO_DATA is a 32 bit register A 32 bit all bytes enabled I O write to this port is re directed to the MMIO register pointed to by the MMIO index register An I O read to this port is re directed to the MMIO register pointed to by the MMIO index register An I O read write accesses less than 32 bits in size all bytes enabled will not target this register The result of accesses through IOBAR can be e Accesses directed to the GTT table that is route to DRAM e Accesses to internal graphics registers with the device e Accesses to internal graphics display registers now located within the PCH that is route to DMI Note that GTT table space writes GTTADR are supported through this mapping mechanism This mechanism to access internal graphics MMIO registers must not be used to access VGA IO registers which are mapped through the MMIO space VGA registers must be accessed directly through the dedicated VGA I O ports Trusted Graphics Ranges No trusted graphics ranges are supported Datasheet Volume 2 Processor Configuration Registers n t 2 3 8 Table 2 3 2 3 9 2
230. f the VGA enable bit is not set then accesses to I O address range x3BCh x3BFh are treated just like any other I O accesses That is the cycles are forwarded to PCI Express if the address is within IOBASE and IOLIMIT and ISA enable bit is not set otherwise they are forwarded to DMI Interface MDA resources are defined as the following Memory 0B0000h 0B7FFFh 1 0 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh Including ISA address aliases A 15 10 are not used in decode Any I O reference that includes the I O locations listed above or their aliases will be forwarded to the DMI Interface even if the reference includes I O locations not listed above For I O reads which are split into multiple DWord accesses this decode applies to each DWord independently For example a read to x3B3 and x3B4 quadword read to x3B0 with BE E7h will result in a DWord read from PEG at 3B0 BE Eh and a DWord read from DMI at 3B4 BE 7h Since the processor will not issue I O writes crossing the DWord boundary this special case does not exist for writes Summary of decode priority A Internal Graphics VGA if enabled gets 03COh 0O3CFh always 03BOh O03BBh if MSR O 0 MSR is I O register 03C2h 03D0h 03DFh if MSR O 1 Note 03BCh O3BFh never decodes to IGD 3BCh 3BEh are parallel port I Os and 3BFh is only used by true MDA devices apparently B Else If MDA Present if VGA on PEG is enabled DMI gets x3B4 5 8 9 A F any access with any of th
231. face Note Additional qualification within IGD comprehends internal MDA support The VGA and MDA enabling bits detailed below control segments not mapped to IGD VGA I O range is defined as addresses where A 15 0 are in the ranges 03BOh to 03BBh and 03C0h to 03DFh VGA I O accesses are directed to IGD depends on the following configuration e Internal Graphics Controller in Device 2 is enabled through register DEVEN D2EN bit 4 e Internal Graphics VGA in Device 0 function 0 is enabled through register GGC bit 1 e IGD I O accesses PCICMD2 04 05h IOAE bit 0 in Device 2 are enabled e VGA I O decodes for IGD uses 16 address bits 15 0 there is no aliasing Note that this is different when compared to a bridge device Device 1 that used only 10 address bits A 9 0 for VGA I O decode e VGA I O input output address select VGA Miscellaneous output Register MSR Register bit 0 used to select mapping of I O access as defined in Table 2 5 Table 2 5 1GD VGA I O Mapping I O Access gt 3B0 3BB 3BC 3BF MSRbO IGD PCI Express Bridge or DMI IGD PCI Express Bridge or Interface DMI Interface PCI Express Bridge or PCI Express Bridge or IGD IGD DMI Interface DMI Interface Note Additional qualification within IGD comprehends internal MDA support The VGA and MDA enabling bits detailed below control ranges not mapped to IGD 42 Datasheet Volume 2 Processor Configuration Registers n t Table 2 6 For regions map
232. fferent Reset Value For both Upstream and Downstream ports this field is used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode Datasheet Volume 2 Processor Configuration Registers 2 7 Table 2 9 2 7 1 eee nte PCI Device 1 Function 0 2 Extended Configuration Registers Table 2 9 lists the registers arranged by address offset Register bit descriptions are in the sections following the table PCI Device 1 Function 0 2 Extended Configuration Register Address Map wer sa eem ee om PVCCAP1 Port VC Capability Register 1 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 1 0 2 MMR Address Offset 104 107h Reset Value 0000_ 0000h Access RO Size 32 bits BIOS Optimal Default 0000000h Reset RST Description Value PWR p fe o eea o Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in 000b Uncore addition to the default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other VC resources in a strict priority VC Arbitration The value of 0 in this field implies strict VC arbitration sae eaves o Extended VC Count EVCC 2 0 000b Uncore This field indicates the number of extended Virtual Channels in addition to the default VC supported by the de
233. ffset Register bit descriptions are in the sections following the table Table 2 21 PCU MCHBAR Register Address Map oe Register Symbol Register Name Reset Value access MEM_TRML_ESTI Memory Thermal Estimation Configuration MEM_TRML_THRE Memory Thermal Thresholds Configuration MEM_TRML_STAT Memory Thermal Status Report sees Rae S anions e x MEM_TRML_TEMP Memory Thermal Temperature Report soar Bittoneeeponr 979 ermal Tempsatwe neeo oon cooon Row 58A8 58AB MEME TAMER Memory Thermal Interrupt 0000_0000h RW Sticky Scratchpad Data 0000_0000_ 260 Datasheet Volume 2 Processor Configuration Registers intel 2 19 1 MEM_TRML_ESTIMATION_CONFIG Memory Thermal Estimation Configuration Register This register contains configuration regarding VTS temperature estimation calculations that are done by PCODE For the BW estimation mode the following formula is used VTS temperature estimation T n VTS_Offset where T n 1 VTS_TIME_CONSTANT T n 1 VTS_MUTXTIPLIER MEM_ACC n MEM_ACC n 1 where MEM_ACC n MEM_ACC n 1 equals memory bandwidth This register is read by PCODE only during Reset Phase 4 B D F Type 0 0 0 MCHBAR PCU Address Offset 5880 5883h Reset Value 438C_8324h Access RW Size bits BIOS Optimal Default Reset RST fone ver Sct te fevers O VTS multiplier VTS_MUTXTI PLI ER 31 22 RW 10Eh Uncore The VTS multiplier serves as a multiplier for the tran
234. figuration Registers 2 8 PCI Device 2 Configuration Registers Table 2 10 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 10 PCI Device 2 Configuration Register Address Map e eee ae set Symbol Value a e a pe as e a e ee E a a eee e See e a amn o pee Tm so 3an RomaDR Video BIOS ROM Base aadress foooo oooon ro passer Revo Reeves a Pape tare inert ae MINGNT nina Gre mR pam wantar Moximumtateney Tm oen svo Reeves CSS id pawn avo reeves ET 132 Datasheet Volume 2 Processor Configuration Registers intel 2 8 1 VID2 Vendor Identification Register This register combined with the Device Identification register uniquely identifies any PCI device B D F Type Address Offset Reset Value 0 2 0 PCI 0 1h 8086h Access RO Size 16 bits Reset RST Description Value PWR P Vendor Identification Number VID Bosen Uncore ucore 18g standard identification for Intel 2 8 2 DI D2 Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device This is a 16 bit value assigned to processor graphics device The DID values assigned for the processor are SKU Server B D F Type Address Offset Reset Value Access Size 5 4 3 2 DID 00 10 010Ah 0 2 0 PCI 2 3h 0102h RO V RO FW 16 bits Reset RST go joe
235. g is active an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in Fault Status register When advanced fault logging is active an interrupt condition occurs when hardware records a fault in the first fault record at index 0 of the current fault log and sets the APF field in the Fault Status register Hardware detected error associated with the Invalidation Queue setting the IQE field in the Fault Status register Hardware detected invalid Device OTLB invalidation completion setting the ICE field in the Fault Status register Hardware detected Device OTLB invalidation completion time out setting the ITE field in the Fault Status register If any of the status fields in the Fault Status register was already set at the time of setting any of these fields it is not treated as a new interrupt condition The IP field is kept set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being Set or other transient hardware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to e Software clearing the IM field Software servicing all the pending in
236. g on the value of MSAC 2 1 See MSAC Device 2 Function 0 offset 62h for details 256 MB Address Mask ADMSK256 27 RW L This bit is either part of the Memory Base Address R W or part of the Address Mask RO depending on the value of MSAC 2 1 See MSAC Device 2 Function 0 offset 62h for details Address Mask ADM 2Sa no coon Hardwired to Os to indicate at least 128 MB address range 3 lb incors Prefetchable Memory PREFMEM Hardwired to 1 to enable prefetching Memory Type MEMTYP 2 1 10b Uncore 00 32 bit address 10 64 bit address Wacore Memory 10 Space MIOS Hardwired to 0 to indicate memory space Datasheet Volume 2 139 Processor Configuration Registers ntel 2 8 12 IOBAR I O Base Address Register This register provides the Base offset of the I O registers within Device 2 Bits 15 6 are programmable allowing the I O Base to be located anywhere in 16 bit I O Address Space Bits 2 1 are fixed and return zero bit O is hardwired to a one indicating that 8 bytes of I O space are decoded Access to the 8Bs of I O space is allowed in PM state DO when I O Enable PCICMD bit 0 is set Access is disallowed in PM states D1 D3 or if I O Enable is clear or if Device 2 is turned off Note that access to this I O BAR is independent of VGA functionality within Device 2 If accesses to this I O bar is allowed then all 8 16 or 32 bit I O cycles from IA cores that falls within the 8B are claimed B D F Typ
237. g these capabilities by writing to the Port oih Arbitration Select field see below a 1 yneore Defined bit positions are Bit 0 Non configurable hardware fixed arbitration scheme such as Round Robin RR Bit 1 Weighted Round Robin WRR arbitration with 32 phases Bit 2 WRR arbitration with 64 phases Bit 3 WRR arbitration with 128 phases Bit 4 Time based WRR with 128 phases Bit 5 WRR arbitration with 256 phases Bits 6 7 Reserved Processor only supported arbitration indicates Non configurable hardware fixed arbitration scheme Datasheet Volume 2 129 intel 2 7 5 130 Processor Configuration Registers VCORCTL VCO Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0 B D F Type 0 1 0 2 MMR Address Offset 114 117h Reset Value 8000_OOFFh Access RO RW Size 32 bits BIOS Optimal Default 000h Reset RST A jose ace e Ble on O O VCO Enable VCOE 31 1b Uncore For VCO this is hardwired to 1 and read only as VCO can never be disabled saf o o p peen o VCO ID VCOI D 26 24 000b Uncore Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only saj me meee o Port Arbitration Select PAS This field configures the VC resource to provide a particular Port Arbitration service This field is valid for RCRBs Root Ports that support peer to peer traffic and Switch Ports but not for PCI 19 17 RW 000b
238. gister This 8 bit register controls steering of MDA cycles and a fixed DRAM hole from 15 16 MB There can only be at most one MDA device in the system B D F Type 0 0 0 PCI Address Offset 87h Reset Value 00h Access RW Size A ig BIOS Optimal Default Reset RST Description Value PWR p Hole Enable HEN This field enables a memory hole in DRAM space The DRAM that 7 RW wacere lies behind this space is not remapped 0 No memory hole 1 Memory hole from 15 MB to 16 MB This bit is Intel TXT lockable oa o o ea o o PEG60 MDA Present MDAP60 This bit works with the VGA Enable bits in the BCTRL register of Device 6 Function 0 to control the routing of processor initiated transactions targeting MDA compatible I O and memory address ranges This bit should not be set if the device 6 VGA Enable bit is not set If Device 6 Function 0 VGA enable bit is not set then accesses to I O address range x3BCh x3BFh remain on the backbone If the VGA enable bit is set and MDA is not present then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 6 Function 0 if the address is within the corresponding OBASE and IOLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory 0B0000h 0B7FFFh 1 0 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not used in decode Any O reference that includes the I O locations listed
239. gister including itself 2 5 25 REMAPLI MI T Remap Limit Address Register B D F Type 0 0 0 PCI Address Offset 98 9Fh Reset Value 0000_0000_0000_0000h Access RW KL RW L Size 64 bits BIOS Optimal Default 0000_0000_0000h Reset RST Description Value PWR p sa e m pema ooo Remap Limit Address REMAPLMT The value in this register defines the upper boundary of the Remap window The Remap window is inclusive of this address In the decoder A 19 0 of the remap limit address are assumed to be Fs 35 20 0000h Uncore Thus the top of the defined range will be one byte less than a 1 MB boundary When the value in this register is less than the value programmed into the Remap Base register the Remap window is disabled These Bits are Intel TXT lockable ma e o eea o Lock LOCK RW KL Uncore This bit will lock all writeable settings in this register including itself 74 Datasheet Volume 2 Processor Configuration Registers intel 2 5 26 TOM Top of Memory Register This register contains the size of physical memory BIOS determines the memory size reported to the OS using this register B D F Type 0 0 0 PCI Address Offset A0 A7h Reset Value 0000_007F_FFFO_0000h Access RW KL RW L Size 64 bits BIOS Optimal Default 000_0000_0000h Reset RST Description Value PWR P ree 0 o pena o Top of Memory TOM This register reflects the total amount of populated physic
240. gister and domain id specified in DID field This can be in response to a page selective invalidation request af no o reer o Drain Reads DR This field is ignored by hardware if the DRD field is reported as clear in the Capability register When the DRD field is reported as RW acre Set in the Capability register the following encodings are supported for this field 0 Hardware may complete the OTLB invalidation without draining any translated DMA read requests 1 Hardware must drain DMA read requests Drain Writes DW This field is ignored by hardware if the DWD field is reported as Clear in the Capability register When the DWD field is reported as 48 RW Uncore Set in the Capability register the following encodings are supported for this field 0 Hardware may complete the OTLB invalidation without draining DMA write requests 1 Hardware must drain relevant translated DMA write requests waj wo m ieee o Domain ID DID Indicates the ID of the domain whose IOTLB entries need to be selectively invalidated This field must be programmed by software for domain selective and page selective invalidation requests 39 32 RW 00h Uncore The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware ignores and not implements bits 47 32 N where N is the supported domain id width reported in the Capability register pare xe
241. guration Registers Note 2 5 31 78 G Memory Base Register This register contains the base address of TSEG DRAM memory BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory PCI Device 0 Offset B4h bits 31 20 BIOS must program TSEGMB to a 8 MB naturally aligned boundary B D F Type 0 0 0 PCI Address Offset B8 BBh Reset Value 0000_ 0000h Access RW KL RW L Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR P TESG Memory base TSEGMB This register contains the base address of TSEG DRAM memory RW L 000h Uncore BIOS determines the base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory PCI Device 0 Offset B4h bits 31 20 Lock LOCK Uncore This bit will lock all writeable settings in this register including itself 31 20 ma je o ea o TOLUD Top of Low Usable DRAM Register This 32 bit register defines the Top of Low Usable DRAM TSEG GTT Graphics memory and Graphics Stolen Memory are within the DRAM space defined From the top the Host optionally claims 1 to 64 MBs of DRAM for internal graphics if enabled 1 or 2 MB of DRAM for GTT Graphics Stolen Memory if enabled and 1 2 or 8 MB of DRAM for TSEG if enabled Programming Example e C1DRB3 is set to 4 GB e TSEG is enabled and TSEG size is set to 1 MB e Internal Graphics is enabled and Graphics Mode Select is set to 32 MB e GTT
242. h Reset RST ane je fae Ses She esermon DEVSEL Timing DEVT These bits are hardwired to 00 Writes to these bit positions have 10 9 Uncore no effect Device 0 does not physically connect to PCI_A These bits are set to 00 fast decode so that optimum DEVSEL timing for PCI_A is not limited by the Host Master Data Parity Error Detected DPD RWIC incre Mhig bit is set when DMI received a Poisoned completion from PCH This bit can only be set when the Parity Error Enable bit in the PCI Command register is set Fast Back to Back FB2B This bit is hardwired to 1 Writes to these bit positions have no 7 1b Uncore effect Device 0 does not physically connect to PCI_A This bit is set to 1 indicating fast back to back capability so that the optimum setting for PCI_A is not limited by the Host o p e o eena o ore 66 MHz Capable MC66 Does not apply to PCI Express Must be hardwired to 0 Capability List CLI ST This bit is hardwired to 1 to indicate to the configuration software that this device function implements a list of new capabilities A list 1b Uncore of new capabilities is accessed using register CAPPTR at configuration address offset 34h Register CAPPTR contains an offset pointing to the start address within configuration space of this device where the Capability Identification register resides se me anes Datasheet Volume 2 51 m t 1 Processor Configuration Registers 52 RI D
243. h e Extended System BIOS Area E_0000h E_FFFFh e System BIOS Area F_O000h F_FFFFh The processor decodes the Core request then routes to the appropriate destination DRAM or DMI Snooped accesses from PCI Express or DMI to this region are snooped on processor caches Non snooped accesses from PCI Express or DMI to this region are always sent to DRAM Graphics translated requests to this region are not allowed If such a mapping error occurs the request will be routed to C_0000h Writes will have the byte enables de asserted Main Memory Address Range 1 MB TOLUD This address range extends from 1 MB to the top of Low Usable physical memory that is permitted to be accessible by the processor as programmed in the TOLUD register The processor will route all addresses within this range to the DRAM unless it falls into the optional TSEG or optional ISA Hole or optional IGD stolen VGA memory Main Memory Address Range FFFF_FFFFh FLASH APIC Intel TXT Contains Dev 0 1 2 6 7 BARS amp PCH PCI PGI Memory Range ranges IGD IGGTT TSEG DPR TSEG_BASE Main Memory 0100_0000h ISA Hole optional 00F0_0000h Main Memory 0010_0000h DOS Compatibility Memory Datasheet Volume 2 Processor Configuration Registers n t 2 3 2 1 ISA Hole 15 MB 16 MB The ISA Hole is enabled in the Legacy Access Control Register in Device 0 configuration spa
244. h memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0O the host read accesses are directed to DMI WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 85h Reset Value 00h Access RW Size a are BIOS Optimal Default Reset RST Description Value PWR p mje o pea o 0E4000 0E7FFF Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from 0E4000h to OE7FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT afe o pee o 0E0000 OE3FFF Attribute LOENABLE This field controls the steering of read and write cycle
245. hat address the BIOS area from ODCOOOh to ODFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT sae o j pee o 0D8000 ODBFFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from 0D8000h to ODBFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are 1 0 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 67 68 Processor Configuration Registers PAM5 Programmable Attribute Map 5 Register This register controls the read write and shadowing attributes of the BIOS range from E_0000h to E_7FFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for eac
246. he super page sizes corresponding to various bit positions within this field are Oh 21 bit offset to page frame 2 MB aaa 09905 Unigor 1h 30 bit offset to page frame 1 GB 2h 39 bit offset to page frame 512 GB 3h 48 bit offset to page frame 1 TB Hardware implementations supporting a specific super page size must support all smaller super page sizes that is only valid values for this field are 0001b 0011b 0111b 1111b Fault recording Register offset FRO This field specifies the location to the first fault recording register relative to the register base address of this remapping hardware 33 24 020h Uncore unit If the register base address is X and the value reported in this field is Y the address for the first fault recording register is calculated as X 16 Y Datasheet Volume 2 271 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9_0080_2066_0262h Access Size BIOS Optimal Default Reset RST ee jw ace sist te esemton Isochrony I SOCH 0 Remapping hardware unit has no critical isochronous requesters in its scope Remapping hardware unit has one or more critical 23 Uncore isochronous requesters in its scope To guarantee isochronous performance software must ensure invalidation operations do not impact active DMA streams from such requesters This implies when DMA is active software performs page selective invalidatio
247. hysical Memory with 1 GB allocated to Memory Mapped I0 e Populated Physical Memory 5 GB e Address Space allocated to memory mapped 10 including Flash APIC and Intel TXT 1 GB e Remapped Physical Memory 1 GB e TOM 01_4000_0000h 5 GB e ME stolen size 00000b 0 MB e TOUUD 01_8000_0000h 6 GB 1 MB aligned e TOLUD 00_C000_000h 3 GB e REMAPBASE 01_4000_0000h 5 GB e REMAPLIMIT 01_7FFO_0000h 6 GB 1 30 Datasheet Volume 2 Processor Configuration Registers n t The Remap window is inclusive of the Base and Limit addresses In the decoder A 19 0 of the Remap Base Address are assumed to be Os Similarly A 19 0 of the Remap Limit Address are assumed to be Fhs Thus the bottom of the defined memory range will be aligned to a megabyte boundary and the top of the defined range will be one less than a MB boundary Setting the Remap Base register to a value greater than that programmed into the Remap Limit register disables the remap function Software Responsibility and Restrictions e BIOS is responsible for programming the REMAPBASE and REMAPLIMIT registers based on the values in the TOLUD TOM and ME stolen size registers e The amount of remapped memory defined by the REMAPBASE and REMAPLI MIT registers must be equal to the amount of physical memory between the TOLUD and the lower of either 4 GB or TOM minus the ME stolen size e Addresses of MMIO region must not overlap with any part of the
248. ice 1 Function 2 is disabled and hidden Uncore 1 Enabled Bus 0 Device 1 Function 2 is enabled and visible This bit will be set to Ob and remain Ob if PEG11 Enable D1F1EN 0 Disabled Bus 0 Device 1 Function 1 is disabled and hidden Uncore 1 Enabled Bus 0 Device 1 Function 1 is enabled and visible This bit will be set to Ob and remain Ob if e PEG12 is disabled by strap PEGOCFGSEL Host Bridge DOEN Uncore Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired to 1 PEG10 Enable D1FOEN 0 Disabled Bus 0 Device 1 Function 0 is disabled and hidden Uncore 1 Enabled Bus 0 Device 1 Function 0 is enabled and visible This bit will be set to Ob and remain Ob if PEG10 capability is disabled 59 60 Processor Configuration Registers PCIEXBAR PCI Express Register Range Base Address Register This is the base address for the PCI Express configuration space This window of addresses contains the 4 KB of configuration space for each PCI Express device that can potentially be part of the PCI Express Hierarchy associated with the Uncore There is no actual physical memory within this window of up to 256 MB that can be addressed The actual size of this range is determined by a field in this register Each PCI Express Hierarchy requires a PCI Express Base register The Uncore supports one PCI Express Hierarchy The region reserved by this register does not alias to any PCI2 3 complian
249. icular Port Arbitration service This field is valid for RCRBs Root Ports that support peer to peer traffic and Switch Ports but not for PCI 19 17 RW 000b core el e le devices or Root Ports that do not support peer to The permissible value of this field is a number corresponding to one of the asserted bits in the Port Arbitration Capability field of the VC resource This field does not affect the root port behavior e o emas ooo TC High VCO Map TCHVCOM 15 8 RW 00h Uncore Allow usage of high order TCs BIOS should keep this field zeroed to allow usage of the reserved TC 3 for other purposes TC VCO Map TCVCOM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations within this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this VC 7 1 RW 7Fh Uncore resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource To remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link 1b U core TCO VCO Map TCOVCOM Traffic Class 0 is always routed to VCO Datasheet Volume 2 Processor Configuration Registers 2 11 6 VCORSTS VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 6 0 MMR Address Offset 11A 11Bh Reset Value 00
250. id specified by software in the DID field This could be in response to a domain selective or a page selective invalidation request Domain page selective invalidation performed using the address mask and hint specified by software in the Invalidate Address register and domain id specified in DID field This can be in response to a page selective invalidation request f o on reer o Drain Reads DR This field is ignored by hardware if the DRD field is reported as clear in the Capability register When the DRD field is reported as 49 RW cere set in the Capability register the following encodings are supported for this bit 0 Hardware may complete the OTLB invalidation without draining any translated DMA read requests 1 Hardware must drain DMA read requests Drain Writes DW This bit is ignored by hardware if the DWD field is reported as clear in the Capability register When the DWD field is reported as set in RW Wace Gea register the following encodings are supported for 0 Hardware may complete the OTLB invalidation without draining DMA write requests 1 Hardware must drain relevant translated DMA write requests woj o o eea o Domain ID DID This field indicates the ID of the domain whose IOTLB entries need to be selectively invalidated This field must be programmed by software for domain selective and page selective invalidation requests 32 22 RW ogh MESES The Capability register reports the domain id width
251. ified Compliance entermodcompliance When this bit is set to 1b the device transmits modified compliance pattern if the TXTSSM enters Polling Compliance state Components that support only the 2 5GT s speed are permitted to hardwire this bit to Ob Transmit Margin txmargin This field controls the value of the non deemphasized voltage level at the Transmitter pins This field is reset to 000b on entry to the LTSSM Polling Configuration substate Encodings 000b Normal operating range 001b 111b As defined in the Transmitter Margining section of the PCI Express Base Specification 3 0 not all encodings are required to be implemented Powerg For a Multi Function device associated with an upstream port the oQ field in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this field is of type RsvdP Components that support only the 2 5 GT s speed are permitted to hardwire this bit to 000b This register is intended for debug compliance testing purposes only System firmware and software is allowed to modify this register only during debug or compliance testing In all other cases the system must ensure that this register is set to the default value 126 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset D0 D1h Reset Value 0002h Access RWS RWS V Size an bits BIOS Optimal Default Reset RST js awe Gs Si
252. ill not set this bit They are reported at the receiving port Unoa Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 e poe o ea ncore 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 Capabilities List CAPL Uncore Fane that a capabilities list is present Hardwired to 1 INTx Status INTAS Indicates that an interrupt message is pending internally to the device Only PME and Hot Plug sources feed into this status bit not Uncore PCI INTA INTD assert and deassert messages The INTA Assertion Disable bit PCICMD1 10 has no effect on this bit Note that INTA emulation interrupts received across the link are not reflected in this bit pe we nese o Uncore 150 Datasheet Volume 2 Processor Configuration Registers intel 2 10 5 RI D6 Revision Identification Register This register contains the revision number of the processor root port These bits are read only and writes to this register have no effect B D F Type 0 6 0 PCI Address Offset 8h Reset Value 00h Access RO FW Size 8 bits GOEIE Revision Identification Number MSB RI D_MSB A ig This is an 8 bit value that indicates the revision identification yen pl on pagers number for the root port Refer to the Intel Xeon Processor E3 1200 Family Specification Update for the value of the RID register Revision Identification Number RID 7 This is an 8 bit value that indicates the revisio
253. in this field correspond to TC values For example when bit 7 is set in this field TC7 is mapped to this 6 1 RW 3Fh Uncore VC resource When more than one bit in this field is set it indicates that multiple TCs are mapped to the VC resource To remove one or more TCs from the TC VC Map of an enabled VC software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link lb nears Traffic Class 0 Virtual Channel 0 Map TCOVCOM Traffic Class 0 is always routed to VCO Datasheet Volume 2 Processor Configuration Registers intel 2 12 7 DMI VCORSTS DMI VCO Resource Status Register This register reports the Virtual Channel specific status B D F Type 0 0 0 DMI BAR Address Offset 1A 1Bh Reset Value 0002h Access RO V Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P safe j o j pee o Virtual Channel 0 Negotiation Pending VCONP 0 The VC negotiation is complete 1 The VC resource is still in the process of negotiation initialization or disabling This bit indicates the status of the process of Flow Control initialization It is set by default on Reset as well as when the l RO V ab Uncore corresponding Virtual Channel is Disabled or the Link is in the DL_Down state It is cleared when the link successfully exits the FC_INIT2 state BIOS Requirement Before using a Virtual Channel software must check whether the VC Negotia
254. ines what the acceptable limit of the temperature is When this threshold is crossed severe throttling takes place The self refresh is also at double rate e The critical threshold continues to throttle a the hot threshold value while also generating an additional interrupt for other platform thermal management Cold Temperature TEMP lt WARM_TH Warm Temperature TEMP gt WARM_TH amp TEMP lt HOT_TH Hot Temperature TEMP gt HOT_TH amp TEMP lt CRITICAL_TH Critical Temperature TEMP gt CRITICAL_TH This register is read by PCODE only during Reset Phase 4 NOTE The threshold values must be programmed such that WARM_TH lt HOT_TH lt CRITICAL_TH B D F Type 0 0 0 MCHBAR PCU Address Offset 5888 588Bh Reset Value 00E4_D5D0h Access RW Size 32 bits BIOS Optimal Default 002AD0h Reset RST Description Value PWR p Hot SS Enable HOT_THRESHOLD_ENABLE 15 RW 1b Uncore ae This bit must be set to allow the hot threshold Hot Threshold HOT_THRESHOLD This threshold defines what is the acceptable temperature 14 8 RW 1010101 g Mncore limitation When this threshold is crossed severe throttling takes place The self refresh is also at double rate Warm Threshold Enable WARM_THRESHOLD_ ENABLE 7 RW 1b Uncore acd This bit must be set to allow the warm threshold Warm Threshold WARM_ THRESHOLD The warm temperature threshold defines when the self refresh is at RW 1010000b U pone double rate Throt
255. ing Table Address Register This register provides the base address of Interrupt remapping table This register is treated as RsvdZ by implementations reporting Interrupt Remapping IR as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset B8 BFh Reset Value 0000_0000_0000_0000h Access RW L Size 64 bits BIOS Optimal Default 0000_0000h Reset RST semm ee ss mo m pema O Interrupt Remapping Table Address IRTA This field points to the base of 4 KB aligned interrupt remapping table 38 12 RW L 0000000h U peers Hardware ignores and does not implement bits 63 HAW where HAW is the host address width Reads of this field returns value that was last programmed to it Extended Interrupt Mode Enable EI ME This field is used by hardware on Intel 64 platforms as follows 0 xAPIC mode is active Hardware interprets only low 8 bits of Destination D field in the IRTEs The high 24 bits of the Destination D field are treated as reserved AA et Uneare 1 x2APIC mode is active Hardware interprets all 32 bits of Destination D field in the IRTEs This bit is implemented as RsvdZ on implementations reporting Extended Interrupt Mode EIM field as Clear in Extended Capability register maj o o een o Size S 3 0 RW L Oh Uncore This field specifies the size of the interrupt remapping table The number of entries in the interrupt remapping table is 2 X 1 where X is
256. ing hardware implementations on platforms supporting Intel TXT and is optional for non Intel TXT platforms Since the protected memory region needs to be enabled before the MVMM is launched hardware must support enabling of the protected memory region independently from enabling the DMA remapping hardware As part of the secure launch process the SINIT AC module verifies the protected memory regions are properly configured and enabled Once launched the MVMM can setup the initial DMA remapping structures in protected memory to ensure they are protected while being setup before enabling the DMA remapping hardware units To optimally support platform configurations supporting varying amounts of main memory the protected memory region is defined as two non overlapping regions Protected Low memory Region This is defined as the protected memory region below 4 GB to hold the MVMM code private data and the initial DMA remapping structures that control DMA to host physical addresses below 4 GB DMA remapping hardware implementations on platforms supporting Intel TXT are required to support protected low memory region 5 e Protected High memory Region This is defined as a variable sized protected memory region above 4 GB enough to hold the initial DMA remapping structures Datasheet Volume 2 21 m t 1 Processor Configuration Registers 2 3 2 4 2 3 2 5 22 for managing DMA accesses to addresses above 4 GB DMA remapping hardwar
257. ing queued invalidations implement this bit as reserved Advanced Pending Fault APF When this field is Clear hardware sets this field when the first fault record at index 0 is written to a fault log At this time a fault event is generated based on the programming of the Fault Event 3 Uncore Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved Advanced Fault Overflow AFO Hardware sets this field to indicate advanced fault log overflow condition At this time a fault event is generated based on the 2 Uncore programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as reserved Datasheet Volume 2 283 Processor Configuration Registers B D F Type 0 0 0 VCOPREMAP Address Offset 34 37h Reset Value 0000_ 0000h Access RWI1CS ROS V RO Size 32 bits BI OS Optimal Default 0_0000h Reset RST oe jw awe ss Site esermton Primary Pending Fault PPF This field indicates if there are one or more pending faults logged in the fault recording registers Hardware computes this field as the logical OR of Fault F fields across all the fault recording registers of this remapping hardware unit Powerg 1 ROS V ood 0 No pending faults in any of the fault recording registers 1 One or mo
258. ing the Invalidation Event Data amp Invalidation Event Address register 31 RW L 1b Uncore values This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set Interrupt Pending IP Hardware sets the IP bit when it detects an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF bit set completed setting the IWC field in the Invalidation Completion Status register If the IWC bit in the I nvalidation Completion Status register was already Set at the time of setting this field it is not treated as a new interrupt condition The IP bit is kept set by hardware while the interrupt message is 30 RO V Uncore held pending The interrupt message could be held pending due to interrupt mask IM bit being set or due to other transient hardware conditions The IP bit is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM bit Software servicing the IWC bit in the Invalidation Completion Status register mofe o ee Datasheet Volume 2 251 Processor Configuration Registers intel 2 18 24 l EDATA_REG Invalidat
259. invalidation event interrupt control bits This register is treated as RsvdZ by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A0 A3h Reset Value 8000_ 0000h Access RW L RO V Size 32 bits BIOS Optimal Default 0000_ 0000h Reset RST A me foar E OO eon O O Interrupt Mask IM 0 No masking of interrupt When an invalidation event condition is detected hardware issues an interrupt message using the Invalidation Event Data amp Invalidation Event Address register 31 RW L 1b Uncore values This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is Set Interrupt Pending IP Hardware sets the IP field whenever it detects an interrupt condition Interrupt condition is defined as e An Invalidation Wait Descriptor with Interrupt Flag IF field Set completed setting the IWC field in the Invalidation Completion Status register If the IWC field in the Invalidation Completion Status register was already Set at the time of setting this field it is not treated as a new interrupt condition The IP field is kept set by hardware while the interrupt message is 30 RO V Uncore held pending The interrupt message could be held pending due to interrupt mask IM field being set or due to other transient hard
260. ion Value PWR P Link Autonomous Bandwidth Status LABWS This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width without the port 15 RW1C Uncore transitioning through DL_Down status for reasons other than to attempt to correct unreliable link operation This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was indicated as an autonomous change Link Bandwidth Management Status LBWMS This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status A link retraining initiated by a write of 1b to the Retrain Link bit has completed Note This bit is Set following any write of 1b to the Retrain Link 14 RW1C Uncore bit including when the Link is in the process of retraining for some other reason Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation either through an TXTSSM time out or a higher level process This bit must be set if the Physical Layer reports a speed or width change was initiated by the downstream component that was not indicated as an autonomous change Data Link Layer Link Active Optional DLLLA This bit indicates the status of the Data Link Control and Management State Machine It returns a 1b to indicate the 13 RO V Uncore DL_Active state Ob otherwise This b
261. ion Event Data Register This register specifies the Invalidation Event interrupt message data This register is treated as RsvdZ by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset A40000_0 A7h Reset Value 0000_ 0000h Access RW L Size 32 bits Reset RST Description Value PWR P Extended Interrupt Message Data EI MD This field is valid only for implementations supporting 32 bit 31 16 RW L 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data treat this field as RsvdZ 15 0 Rw L Gon Uncore nterrupt Message data IMD Data value in the interrupt request 2 18 25 IEUADDR_REG I nvalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address B D F Type 0 0 0 GFXVTBAR Address Offset AC AFh Reset Value 0000_0000h Access RW L Size 32 bits Reset RST Description Value PWR p Message Upper Address MUA Hardware implementations supporting Queued Invalidations and 31 0 RW L 00000000h Uncore Extended Interrupt Mode are required to implement this register Hardware implementations not supporting Queued I nvalidations or Extended Interrupt Mode may treat this field as reserved 252 Datasheet Volume 2 Processor Configuration Registers 2 18 26 intel IRTA_REG I nterrupt Remapp
262. ions 0 1 us granularity Powerg 00h 0 us 5 0 RWS 000000b ood Olh 0 1 us 02h 0 2 us 3Fh 6 3 us Datasheet Volume 2 267 t i Processor Configuration Registers 2 20 PXPEPBAR Registers Table 2 22 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 22 PXPEPBAR Register Address Map Address Register 7 Offset Symbol Register Name Reset Value Access 14 17h EPVCORCTL EP VC 0 Resource Control 8000_O0FFh RO RW 2 20 1 EPVCORCTL EP VC 0 Resource Control Register This register controls the resources associated with Egress Port Virtual Channel 0 B D F Type 0 0 0 PXPEPBAR Address Offset 14 17h Reset Value 8000_O0OFFh Access RO RW Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR p aaj e o pee o Port Arbitration Select PAS This field configures the VC resource to provide a particular Port 19 17 mn 0090 uae Arbitration service The value of Oh corresponds to the bit position of the only asserted bit in the Port Arbitration Capability field oje o ee 268 Datasheet Volume 2 Processor Configuration Registers intel 2 21 Default PEG DMI VT d Remapping Engine Registers Table 2 23 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 23 Default PEG DMI VT d Remapping Engine Register Address Map Sheet 1 of 2
263. ions setup through the PLMBASE PLMLIMT PHMBASE PHMLIMIT registers This register is always treated as RO for implementations not supporting protected memory regions PLMR and PHMR fields reported as Clear in the Capability register Protected memory regions may be used by software to securely initialize remapping structures in memory To avoid impact to legacy BIOS usage of memory software is recommended to not overlap protected memory regions with any reserved memory regions of the platform reported through the Reserved Memory Region Reporting RMRR structures B D F Type 0 0 0 GFXVTBAR Address Offset 64 67h Reset Value 0000_0000h Access RW RO V Size 32 bits BIOS Optimal Default 00000000h Reset RST Description Value PWR p Enable Protected Memory EPM This bit controls DMA accesses to the protected low memory and protected high memory regions 0 Protected memory regions are disabled 1 Protected memory regions are enabled DMA requests accessing protected memory regions are handled as follows When DMA remapping is not enabled all DMA requests accessing protected memory regions are blocked When DMA remapping is enabled DMA requests processed as pass through Translation Type value of 10b in Context Entry and accessing the protected memory regions are blocked DMA requests with translated address AT 10b and accessing the protected memory regions are blocked DMA requests that are subje
264. is complete Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field Software must not submit another invalidation request through 63 RW Oh Uncore this register while the IVT field is set nor update the associated Invalidate Address register Software must not submit OTLB invalidation requests when there is a context cache invalidation request pending at this remapping hardware unit Hardware implementations reporting write buffer flushing requirement RWBF 1 in Capability register must implicitly perform a write buffer flushing before invalidating the I OTLB Ce fo o ema o IOTLB Invalidation Request Granularity 11 RG When requesting hardware to invalidate the OTLB by setting the IVT field software writes the requested invalidation granularity through this field The following are the encodings for the field 00 Reserved 01 Global invalidation request 10 Domain selective invalidation request The target domain id must be specified in the DID field 61 60 omy Oh Uncore 11 Page selective invalidation request The target address mask and invalidation hint must be specified in the Invalidate Address register and the domain id must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by cl
265. is register resulting in a base address for a contiguous memory address space The size of the range is defined by bits 2 1 of this register This base address shall be assigned on a boundary consistent with the number of buses defined by the Length field in this register above TOLUD and still within the 39 bit addressable memory 38 28 RW 000h Uncore Space The address bits decoded depend on the length of the region defined by this register This register is locked by Intel TXT The address used to access the PCI Express configuration space for a specific device can be determined as follows PCI Express Base Address Bus Number 1MB Device Number 32KB Function Number 4KB This address is the beginning of the 4 KB space that contains both the PCI compatible configuration space and the PCI Express extended configuration space 128MB Base Address Mask ADMSK128 This bit is either part of the PCI Express Base Address RW or part 27 RW V U ncore of the Address Mask RO read 0b depending on the value of bits 2 1 in this register 64MB Base Address Mask ADMSK64 Z This bit is either part of the PCI Express Base Address RW or part 26 RW V U neers of the Address Mask RO read 0b depending on the value of bits 2 1 in this register pas e reseed ooo Length LENGTH This field describes the length of this region 00 256 MB buses 0 255 Bits 38 28 are decoded in the PCI Express Base Address field 2 1 RW Uncore 01
266. is electrically controlled by the chassis 119 Processor Configuration Registers intel 2 6 41 SLOTCTL Slot Control Register Note Hot Plug is not supported on Intel Xeon processor E3 1200 family platforms B D F Type 0 1 0 2 PCI Address Offset B8 B9h Reset Value Access Size BIOS Optimal Default FE o pee o Reserved for Data Link Layer State Changed Enable DLLSCE Reserved for Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented when set to 1b this field enables software notification when Data Link Layer Link Active field is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to be read only with a value of Ob Uncore Reserved for Electromechanical I nterlock Control EIC If an Electromechanical Interlock is implemented a write of 1b to this field causes the state of the interlock to toggle A write of Ob to this field has no effect A read to this register always returns a 0 Uncore Reserved for Power Controller Control PCC If a Power Controller is implemented this field when written sets the power state of the slot per the defined encodings Reads of this field must reflect the value from the latest write even if the corresponding hotplug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value i
267. it must be implemented if the corresponding Data Link Layer Active Capability bit is implemented Otherwise this bit must be hardwired to Ob Slot Clock Configuration SCC 0 The device uses an independent clock irrespective of the 12 1b Uncore presence of a reference on the connector 1 The device uses the same physical reference clock that the platform provides on the connector Link Training TXTRN This bit indicates that the Physical Layer TXTSSM is in the Configuration or Recovery state or that 1b was written to the 11 BOV nee Retrain Link bit but Link training has not yet begun Hardware clears this bit when the TXTSSM exits the Configuration Recovery state once Link training is complete pe o pee 176 Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 6 0 PCI Address Offset B2 B3h Reset Value 1001h Access RWI1C RO V RO Size a bits BIOS Optimal Default Reset RST jw awe Ses Sim esermon Negotiated Link Width NLW This field indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 00h Reserved RO V 00h Uncore 01h X1 02h X2 04h X4 08h X8 10h X16 All other encodings are reserved Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link 3 0 RO V 1h Uncore 0001b 2 5 GT s PCI Express Link 0010
268. lIOBAR Mapped Access to Device 2 MMIO Space ceceeeeeeeeene eee 34 2 3 7 2 Trusted Graphics Range cccceeeeee cece eee eee neta eee eaten teens 34 2 3 8 System Management Mode SMM ccccece eee ence teeter t etter eae 35 2 3 9 SMM and VGA Access through GTT TLB uu ceeceeee eee reenter een ea een e eens 35 2 3 10 ME Stolen Memory ACCESSES cceccece cece eee e et eee tenner teen eens ete e enna ees 35 2 3 11 1 O Address Space kiniita ain EE EENE wate ET bones saad bide dence 36 2 3 11 1 PCI Express I O Address Mapping ceceeeeee ee eee eee e eee eee eens 36 2 3 12 METP and KVM FlOWSiatscianeiies noer e y ved ania nian cians 37 2 3 13 Decode Rules and Cross Bridge Address Mapping ecceceseeneee teen eee ees 37 2 3 13 1 DMI Interface Decode Rules eee cette entree eee teeta enti 37 2 3 13 2 PCI Express Interface Decode Rules cceeeeeeeee eee eee ee eee teens 40 2 3 13 3 Legacy VGA and I O Range Decode RUIeS cccecee eee e ee eee een eeees 41 2 4 Processor Register INtroductiOn cceccece cence ee eee eee EENE R EEES A 45 2 4 1 O Mapped REGIStENS isis ccisieis cic scniseeenaeerierenia tities ikiden ia da aaa nnii 46 2 5 PCI Device 0 Function 0 Configuration Registers ccceceee ete e eee e nent teen eee neta eee 46 2 5 1 VID Vendor Identification Register cccccecce eee ee eee eee eee eee ee teeta eee en ees 48 2 5 2 DID Device Identificatio
269. ld 11 Mask all three bits of function number in the SID field The context entries corresponding to all the source ids specified through the FM and SID fields must have to the domain id specified in the DID field Source ID SID Indicates the source id of the device whose corresponding context 31 16 RW 0000h Uncore entry needs to be selectively invalidated This field along with the FM field must be programmed by software for device selective invalidation requests pare ne o o eea o Domain ID DID Indicates the id of the domain whose context entries need to be selectively invalidated This field must be programmed by software for both domain selective and device selective invalidation 7 0 RW 00h Uncore requests _ o The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware may ignore and not implement bits15 N where N is the supported domain id width reported in the Capability register 282 Datasheet Volume 2 Processor Configuration Registers 2 21 8 FSTS_REG Fault Status Register This register indicates the various error status B D F Type 0 0 0 VCOPREMAP Address Offset 34 37h Reset Value 0000_0000h Access RW1CS ROS V RO Size 32 bits BIOS Optimal Default 0_0000h Reset RST Description Value PWR P aof e awe o Fault Record Index FRI This field is valid only when the P
270. ld is undefined Write Buffer Flush WBF This bit is valid only for implementations requiring write buffer flushing Software sets this field to request that hardware flush the Root Complex internal write buffers This is done to ensure any updates 27 Uncore to the memory resident remapping structures are not held in any internal write posting buffers Hardware reports the status of the write buffer flushing operation through the WBFS field in the Global Status register Clearing this bit has no effect The value returned on a read of this field is undefined Queued I nvalidation Enable QIE This field is valid only for implementations supporting queued invalidations Software writes to this field to enable or disable queued invalidations 26 Wo U pee 0 Disable queued invalidations 1 Enable use of queued invalidations Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register The value returned on a read of this field is undefined Datasheet Volume 2 233 234 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 18 1Bh Reset Value 0000_ 0000h Access RO WO Size 32 bits BIOS Optimal Default 000000h Reset RST Description Value PWR p H H i H t aoj o o een Interrupt Remapping Enable IRE This field is valid only for implementations supporting interrupt remapping 0 Disable interrupt remapping hardware
271. le B64AC Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64 bit memory address This may need to change in future implementations when addressable system memory exceeds the 32b 4GB limit Multiple Message Enable MME System software programs this field to indicate the actual number of messages allocated to this device This number will be equal to or less than the number actually requested The encoding is the same as for the MMC field below Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device The encoding for the number of messages requested is 000 1 All of the following are reserved in this implementation 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved MSI Enable MSIEN Controls the ability of this device to generate MSIs 0 MSI will not be generated 1 MSI will be generated when we receive PME messages INTA will not be generated and INTA Status PCISTS1 3 will not be set Datasheet Volume 2 Processor Configuration Registers 2 6 31 2 6 32 2 6 33 intel MA Message Address Register B D F Type 0 1 0 2 PCI Address Offset 94 97h Reset Value 0000_0000h Access RW RO Size 32 bits Reset RST Description Value PWR P Message Address MA 0000_000 Used by system soft
272. le pointer is specified through the Interrupt Remapping Table Address IRTA_REG register Hardware reports the status of the Set Interrupt Remap Table Pointer operation through the IRTPS field in the Global Status register The Set Interrupt Remap Table Pointer operation must be performed before enabling or re enabling after disabling interrupt remapping hardware through the IRE field 24 wo Uncore after a Set Interrupt Remap Table Pointer operation software must globally invalidate the interrupt entry cache This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer and not any stale cached entries While interrupt remapping is active software may update the interrupt remapping table pointer through this field However to ensure valid in flight interrupt requests are deterministically remapped software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer Clearing this bit has no effect The value returned on a read of this field is undefined Compatibility Format Interrupt CFI This field is valid only for Intel 64 implementations supporting interrupt remapping Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms The value in this fiel
273. lectable De emphasis selectabledeemphasis ood When the Link is operating at 5 GT s speed this bit selects the level of de emphasis Encodings 1 3 5 dB RWS 0 6 dB When the Link is operating at 2 5 GT s speed the setting of this bit has no effect Components that support only the 2 5 GT s speed are permitted to hardwire this bit to Ob NOTE For DMI this bit has no effect in functional mode as DMI is half swing and will use 3 5 dB when de emphasis is enabled Hardware Autonomous Speed Disable HASD 1 Disables hardware from changing the link speed for reasons 5 RWS Powerg other than attempting to correct unreliable link operation by 0 reducing link speed 0 Enable Enter Compliance EC Powerg Software is permitted to force a link to enter Compliance mode at 4 RWS ood the speed indicated in the Target Link Speed field by setting this bit to 1 in both components on a link and then initiating a hot reset on the link Target Link Speed TLS For Downstream ports this field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences 0001b 2 5 Gb s Target Link Speed 0010b 5 Gb s Target Link Speed All other encodings are reserved 3 0 RWS 2h Powerg If a value is written to this field that does not correspond to a i ood speed included in the Supported Link Speeds field the result is undefined The Reset Value of this field is the highest link speed
274. lex Register Range Base Address Register 0 62 PAMO Programmable Attribute Map 0 Register ccceeeee nent teens eaten eee 63 PAM1 Programmable Attribute Map 1 Register ccceeeee ee eee eee ee eaten eee 64 PAM2 Programmable Attribute Map 2 Register ccceeeeee cent eee ee eaten ees 65 PAM3 Programmable Attribute Map 3 Register ccceeeee sent ee eee eae ea tees 66 PAM4 Programmable Attribute Map 4 Register ccceceeeeeee eee eee eaten eee 67 PAM5 Programmable Attribute Map 5 Register ccceeeeee ee eee eee ee eae ea eas 68 PAM6 Programmable Attribute Map 6 Register ceceeeeee nent eee ee eae ea ees 69 LAC Legacy Access Control REGiSter cceccte eee ee nee re een ee ee eee teeta ene ene ees 70 REMAPBASE Remap Base Address ReQiSter cccceeceeeeee ene ea teat eee ee enna 74 REMAPLIMIT Remap Limit Address Register c cceceeceee cnet ee ee eee ee enna 74 TOM Top of Memory ReGiSter ccecceceee eect eee eee e eee eee teen neat eee teeneeaeeas 75 TOUUD Top of Upper Usable DRAM Register ceceeceeee eee ee tees eae ea ees 76 BDSM Base Data of Stolen Memory ReGISter ccceceee este ee ee eee e eens 77 BGSM Base of GTT stolen Memory Register c cece eee e ee ee eee eee e teenies 77 G Memory Base R GISteP cc cece eee 78 TOLUD Top of Low Usable DRAM ReGiSter cccceeeeeeeee teeta eee
275. lidations Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent snooped or not Uncore 9 Indicates hardware accesses to remapping structures are non coherent 1 Indicates hardware accesses to remapping structures are coherent Hardware access to advanced fault log and invalidation queue are always coherent 2 21 4 GCMD_REG Global Command Register This register controls remapping hardware If multiple control fields in this register need to be modified software must serialize the modifications through multiple writes to this register B D F Type 0 0 0 VCOPREMAP Address Offset 18 1Bh Reset Value 0000_0000h Access WO RO Size 32 bits BIOS Optimal Default 00_0000h Reset RST pane GRIE Translation Enable TE Software writes to this field to request hardware to enable disable DMA remapping 0 Disable DMA remapping 1 Enable DMA remapping Hardware reports the status of the translation enable operation through the TES field in the Global Status register There may be active DMA requests in the platform when software 31 wo Uncore updates this field Hardware must enable or disable remapping logic only at deterministic transaction boundaries so that any in flight transaction is either subject to remapping or not at all Hardware implementations supporting DMA draining must drain any in flight DMA read write
276. lities Register must hardwire this bit to Ob Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state Uncore This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns Datasheet Volume 2 115 116 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset BO Bih Reset Value 0000h Access RW RO RW V Size 16 bits BIOS Optimal Default 00h Reset RST e js awe ss Site esermton Common Clock Configuration CCC 0 Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock RW acre 1 Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock The state of this bit affects the LOs Exit Latency reported in LCAP 14 12 and the N_FTS value advertised during link training See LOSLAT at offset 22Ch Retrain Link RL 0 Normal operation F 1 Full Link retraining is initiated by directing the Physical Layer E Bae Uncore TXTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0
277. lities list is present Hardwired to 1 INTx Status INTAS Indicates that an interrupt message is pending internally to the device Only PME and Hot Plug sources feed into this status bit not Uncore PCI INTA INTD assert and deassert messages The INTA Assertion Disable bit PCICMD1 10 has no effect on this bit Note that INTA emulation interrupts received across the link are not reflected in this bit ae ee reseed o Uncore Datasheet Volume 2 91 Processor Configuration Registers 2 6 5 RI D1 Revision Identification Register This register contains the revision number of the processor root port These bits are read only and writes to this register have no effect B D F Type 0 1 0 2 PCI Address Offset 8h Reset Value 00h Access RO FW Size 8 bits GOIE Revision Identification Number MSB RI D_MSB z This is an 8 bit value that indicates the revision identification qi RO EW oh pears number for the root port Refer to the Intel Xeon Processor E3 1200 Family Specification Update for the value of the RID register Revision Identification Number RID i 3 This is an 8 bit value that indicates the revision identification 3 0 aay oh uncore number for the root port Refer to the Intel Xeon Processor E3 1200 Family Specification Update for the value of the RID register 2 6 6 CC1 Class Code Register This register identifies the basic function of the device a more specific sub class and a regist
278. lock The state of this bit affects the LOs Exit Latency reported in LCAP 14 12 and the N_FTS value advertised during link training See LOSLAT at offset 22Ch Retrain Link RL 0 Normal operation 1 Full Link retraining is initiated by directing the Physical Layer 3 RWV Uncore TXTSSM from LO LOs or L1 states to the Recovery state This bit always returns 0 when read This bit is cleared automatically no need to write a 0 Link Disable LD 0 Normal operation 1 Link is disabled Forces the TXTSSM to transition to the RW Uncore Disabled state using Recovery from LO LOs or L1 states Link retraining happens automatically on 0 to 1 transition just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state Uncore Read Completion Boundary RCB Hardwired to 0 to indicate 64 byte eens Active State PM ASPM This field controls the level of ASPM Active State Power Management supported on the given PCI Express Link 1 0 RW Uncore 00 Disabled 01 LOs Entry Supported 10 Reserved 11 LOs and L1 Entry Supported Datasheet Volume 2 175 t i Processor Configuration Registers 2 10 39 LSTS Link Status Register This register indicates PCI Express link status B D F Type 0 6 0 PCI Address Offset B2 B3h Reset Value 1001h Access RWIC RO V RO Size ae bits BIOS Optimal Default Reset RST Descript
279. lock Note that prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 6 0 PCI Address Offset 26 27h Reset Value 0001h Access RW RO Size 16 bits Reset RST E SS Prefetchable Memory Address Limit PMLI MIT Es ome ume field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 64 bit Address Support AS64B Uncore This field indicates that the upper 32 bits of the prefetchable memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch Datasheet Volume 2 159 m t 1 Processor Configuration Registers 2 10 19 PMBASEU6 Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Base Address register are read write and correspond to address bits A 38 32 of th
280. lots where the Slot Implemented bit of the PCI Express Capabilities Register is 0b this bit must return 1b Uncore Reserved for MRL Sensor State MSS This register reports the status of the MRL sensor if it is Uncore implemented 0 MRL Closed 1 MRL Open Reserved for Command Completed CC If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register this bit is set when a hot plug command has completed and the Hot Plug Controller is ready to accept a subsequent command The Command Completed status bit is set as an indication to host software that the Hot Plug Controller has processed the previous command and is ready to receive the next command it provides no guarantee that the action corresponding to the command is complete If Command Completed notification is not supported this bit must be hardwired to Ob Uncore Datasheet Volume 2 181 2 10 43 182 Processor Configuration Registers B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 6 0 PCI BA BBh 0000h RO RO V RW1C 16 bits 00h Reset RST ae js awe ss Site esermton Presence Detect Changed PDC A pulse indication that the inband presence detect state has changed This bit is set when the value reported in Presence Detect State is changed Reserved for MRL Sensor Changed MSC If an MRL sensor is implemente
281. lt intel 0 6 0 PCI 84 87h 0000_ 0008h RO RW 32 bits 000000h Reset RST uae jae ase Gaie Pw Desert OOOO Power State PS This field indicates the current power state of this device and can be used to set the device into a new power state If software attempts to write an unsupported state to this field write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 01 D1 Not supported in this device 10 D2 Not supported in this device 11 D3 Support of D3cold does not require any special action 1 0 RW eee While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort that is not claim any downstream cycles with exception of type 0 configuration cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the processor logs as Master Aborts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States 2 10 27 Register SS_CAPID Subsystem ID and Vendor ID Capabilities This capability is used to uniquely identify the subsystem where the PCI device resides Becaus
282. lue is 63 DCLK cycles Delay Internal WR to RD Transaction 15 12 RW L 4h This field provides the delay from internal WR transaction to internal RD transaction The minimum delay is 4 DCLK cycles whereas the maximum delay is 8 DCLK cycles pare eo o o ema ooo Minimum Delay From CAS RD to PRE 7 4 RW L 4h The minimum delay is 4 DCLK cycles the maximum delay is 8 DCLK cycles Delay Between Two Act Commands 3 0 RW L 4h tRRD is the minimum delay between two ACT commands targeted to different banks in the same rank The minimum delay is 4 DCLK cycles the maximum delay is 7 cycles 2 13 3 SC_IO_LATENCY_CO IO Latency Configuration Register This register identifies the O latency per rank and I O compensation global B D F Type 0 0 0 MCHBAR MCO Address Offset 4028 402Bh Reset Value 0000_0000h Access RW L Size 32 bits Reset RST Description Value PWR p aope e pe o Ca wwe o fro teney narom ae fow o votateneynankopma EE Cra ow f o f fro tency narom EE o o o Gro eny nano ommo EE 208 Datasheet Volume 2 Processor Configuration Registers intel 2 13 4 TC_SRFTP_CO Self Refresh Timing Parameters Register This register provides Self refresh timing parameters B D F Type 0 0 0 MCHBAR MCO Address Offset 42A4 42A7h Reset Value 0000_B000h Access RW L Size 32 bits Reset RST Description Value PWR aoje o pee o Delay From SR Exit to First DDR Command 15 12 RW L Bh
283. lue of 2h represents an Internal Root Complex Link DMI 198 Datasheet Volume 2 Processor Configuration Registers intel 2 12 15 DMILE1LD DMI Link Entry 1 Description Register This register provides the first part of a Link Entry that declares an internal link to another Root Complex Element B D F Type 0 0 0 DMIBAR Address Offset 50 53h Reset Value 0000_0000h Access RW O RO Size 32 bits BIOS Optimal Default 0000h Reset RST Description Value PWR R Target Port Number TPN This field specifies the port number associated with the element targeted by this link entry egress port of PCH The target port number is with respect to the component that contains this 31 24 RW O 00h Uncore element as specified by the target component ID This can be programmed by BIOS but the Reset Value will likely be correct because the DMI RCRB in the PCH will likely be associated with the default egress port for the PCH meaning it will be assigned port number 0 Target Component ID TCID This field identifies the physical component that is targeted by this 23 16 RW O 00h Uncore link entry oe a BIOS Requirement Must be initialized according to guidelines in the PCI Express Isochronous Virtual Channel Support Hardware Programming Specification HPS pasa no om Reever o Link Type TXTYP This bit indicates that the link points to memory mapped space for 1 Uncore RCRB The link address specifies the 64 bit b
284. ma ooo Protected High Memory Limit PHML This register specifies the last host physical address of the DMA 38 20 RW 00000h Uncore protected high memory region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width moe o E pema o 248 Datasheet Volume 2 Processor Configuration Registers intel 2 18 19 IQH_REG Invalidation Queue Head Register This register indicates the invalidation queue head This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 80 87h Reset Value 0000_0000_0000_0000h Access RO V Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RST semm ee n o o j ena o Queue Head QH This field specifies the offset 128 bit aligned to the invalidation 18 4 RO V 0000h Uncore queue for the command that will be fetched next by hardware Hardware resets this field to 0 whenever the queued invalidation is disabled QIES field Clear in the Global Status register oe o E eena o 2 18 20 IQT_REG Invalidation Queue Tail Register This register indicates the invalidation tail head This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 88 8Fh Reset Value 00
285. maximum temperature of all ranks B D F Type 0 0 0 MCHBAR PCU Address Offset 58A4 58A7h Reset Value 0000_ 0000h Access RO V Size 32 bits BIOS Optimal Default 00h Reset RST des joe ame fetes ie eeenetn maj eo oe reseed Channel 1 VTS Estimated Max Temperature 15 8 RO V 00h Uncore CHANNEL1_ESTIMATED_MAX_TEMPERATURE VTS Estimated Temperature in Degrees C Channel 0 VTS Estimated Max Temperature Uncore CHANNELO_ESTIMATED_MAX_TEMPERATURE VTS Estimated Temperature in Degrees C MEM_TRML_INTERRUPT Memory Thermal Interrupt Register Hardware uses the information in this register to determine whether a memory thermal interrupt is to be generated or not B D F Type 0 0 0 MCHBAR PCU Address Offset 58A8 58ABh Reset Value 0000_0000h Access RW Size 32 bits BIOS Optimal Default 0000_ 0000h Reset RST Description Value PWR p a Critical Threshold Interrupt Enable Uneste CRITICAL_THRESHOLD_INT_ENABLE This bit controls the generation of a thermal interrupt when the Critical Threshold temperature is crossed E a Hot Threshold Interrupt Enable Gacere HOT_THRESHOLD_INT_ENABLE This bit controls the generation of a thermal interrupt when the Hot Threshold temperature is crossed E a Warm Threshold Interrupt Enable WARM_THRESHOLD_INT_ENABLE RW Uncore enact a This bit controls the generation of a thermal interrupt when the Warm Threshold temperature is crossed
286. memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet Volume 2 55 56 Processor Configuration Registers MCHBAR Host Memory Mapped Register Range Base Register This is the base address for the Host Memory Mapped Configuration space There is no physical memory within this 32 KB window that can be addressed The 32 KB reserved by this register does not alias to any PCI 2 3 compliant memory mapped space On reset the Host MMIO Memory Mapped Configuration space is disabled and must be enabled by writing a 1 to MCHBAREN Device 0 offset 48h bit 0 All the bits in this register are locked in Intel TXT mode The register space contains memory control initialization timing and buffer strength registers clocking registers and power and thermal management registers B D F Type 0 0 0 PCI Address Offset 48 4Fh Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 00_0000_0000h Reset RST Description Value PWR P s o o pe o Host Memory Mapped Base Address MCHBAR This field corresponds to bits 38 15 of the base address Host Memory Mapped configuration space BIOS will program this register resulting in a base address for a 32 KB block of contiguous 38 15 000000h Uncore memory address space This register ensures that a naturally aligned 32 KB space is allocated within the first 512 GB of addressable memory space System Softwa
287. memory than is addressable When running in internal graphics mode processor initiated Tilex Tiley linear reads writes to GMADR range are supported Write accesses to GMADR linear regions are supported from both DMI and PEG GMADR write accesses to tileX and tileY regions defined using fence registers are not supported from DMI or the PEG port GMADR read accesses are not supported from either DMI or PEG In the following sections it is assumed that all of the compatibility memory ranges reside on the DMI Interface The exception to this rule is VGA ranges which may be mapped to PCI Express DMI or to the internal graphics device IGD In the absence of more specific references cycle descriptions referencing PCI should be interpreted as the DMI Interface PCI while cycle descriptions referencing PCI Express or IGD are related to the PCI Express bus or the internal graphics device respectively The processor does not remap APIC or any other memory spaces above TOLUD Top of Low Usable DRAM The TOLUD register is set to the appropriate value by BIOS The remapbase remaplimit registers remap logical accesses bound for addresses above 4 GB onto physical addresses that fall within DRAM Datasheet Volume 2 15 16 intel Processor Configuration Registers The Address Map includes a number of programmable ranges Device 0 PXPEPBAR PxP egress port registers 4 KB window MCHBAR Memory mapped range for internal MCH registe
288. mory region in system memory Datasheet Volume 2 289 m t 1 Processor Configuration Registers 2 21 16 PLMLIMIT_REG Protected Low Memory Limit Register This register sets up the limit address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region limit depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding most significant zero bit position with O in the value read back from the register Bits N 0 of the limit register is decoded by hardware as all 1s The Protected low memory base and limit registers functions as follows e Programming the protected low memory base and limit registers with the same value in bits 31 N 1 specifies a protected low memory region of size 2 N 1 bytes e Programming the protected low memory limit register with a value less than the protected low memory base register disables the protected low memory region Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 6C 6Fh
289. n evo reed PO Prem ao ewes Pm sees nav Reseed O CH o Link Capabilities RW O RO 188 Datasheet Volume 2 Processor Configuration Registers 5 P D Table 2 14 DMI BAR Register Address Map Sheet 2 of 2 Address Register Offset Symbol Register Name Reset Value Access 2 12 1 88 89h LCTL Link Control 0000h RW RW V 8A 8Bh LSTS DMI Link Status 0001h BCC BCFh AFE BMU Configuration Test 0 DMI VCECH DMI Virtual Channel Enhanced Capability Register This register indicates DMI Virtual Channel capabilities B D F Type 0 0 0 DMI BAR Address Offset 0 3h Reset Value 0401_0002h Access RO Size 32 bits Reset RST Description Value PWR P Pointer to Next Capability PNC 31 20 040h Uncore This field contains the offset to the next PCI Express capability structure in the linked list of capabilities Link Declaration Capability PCI Express Virtual Channel Capability Version PCIEVCCV 19 16 ih Uncore Hardwired to 1 to indicate compliances with the 1 1 version of the PCI Express specification Note This version does not change for 2 0 compliance Extended Capability I D ECID 15 0 0002h Uncore The value of 0002h identifies this linked list item capability structure as being for PCI Express Virtual Channel registers Datasheet Volume 2 189 Processor Configuration Registers intel 2 12 2 DMI PVCCAP1 DMI Port VC Capability Register 1 This register describes the configuratio
290. n Intel 64 platforms hardware supports only 8 bit APIC IDs xAPIC mode RO V 1b Uncore 1 On Intel 64 platforms hardware supports 32 bit APIC IDs x2APIC mode This field is valid only on Intel 64 platforms reporting Interrupt Remapping support IR field Set Interrupt Remapping Support IR 0 Hardware does Not support interrupt remapping 3 RO V 1b Uncore 1 Hardware supports interrupt remapping Implementations reporting this field as set must also support Queued Invalidation QI Device I OTLB Support DI 0 Hardware does not support device OTLBs 2 Uncore 1 Hardware supports Device OTLBs Implementations reporting this field as set must also support Queued Invalidation QI 230 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 GFXVTBAR Address Offset 10 17h Reset Value 0000_0000_O0OFO_101Ah Access RO RO V Size 64 bits BIOS Optimal Default 00000000000h Reset RST ane jw awe Ss Se esermon Queued I nvalidation Support QI 1 RO V 1b Uncore 0 Hardware does Not support queued invalidations 1 Hardware supports queued invalidations Coherency C This field indicates if hardware access to the root context page table and interrupt remap structures are coherent snooped or not Uncore 0 Hardware accesses to remapping structures are non coherent 1 Hardware accesses to remapping structures are coherent Hardware access to advanced fault log
291. n REGiSter cece ee te eee cnet eee e ee eee teste ene eas 48 2 5 3 PCICMD PCI Command Register ccceeee ete e eee ee ene eee eee ee eee ee ete eneeae ees 49 2 5 4 PCISTS PCI Status Re GiSter ceccecee cece cence et eee E eee teeta nena ete SeNi 50 2 5 5 RID Revision Identification Register cece cee ee eee eee eee teat eee 52 2 5 6 CC Class Code REGISTE iniii nanii iria onun dese ESET TEE EEEREN EErEE 53 2 5 7 HDR Header Type RegisSter sssrsssssrrssrrrrrrsssrrrrtnrrrnnrrrrrtunrrrnnrrrrnrnns 53 2 5 8 SVI D Subsystem Vendor Identification Register sssssssssssssrsrerressrrrrsrens 54 Datasheet Volume 2 3 5 r D ORUE E E EUEOECE E E EUEUECEUE E EUEUEC ETE E EUEUECECECEY WWWWWWWWNNNNNNNNNN NOUBWNFOWOANDAUBWNE F OO NNNNNNNNNNNNNNNNNNNINNNNNNNNNNNNNNNNNNNNNNNNNNNNN UO DAADAAIAAIAIAAAAIAAAAAAA PREP RPRPRPRPHPHEPHPODMDYNOAUBWNE OANAUBWNE F O SID Subsystem Identification Register ccececeee ee eee eee eee eee e eaten 54 PXPEPBAR PCI Express Egress Port Base Address Register 0 eeeee 55 MCHBAR Host Memory Mapped Register Range Base Register 56 GGC GMCH Graphics Control Register RegisSter ccceeeeeeeeeee cnet tena eae 57 DEVEN Device Enable ReQiSter ccccceee ce eee eee eee ee eae eee teen e eae eeeteene nates 59 PCIEXBAR PCI Express Register Range Base Address Register 065 60 DMIBAR Root Comp
292. n Register cceeeeeeee eee 221 2 17 Memory Controller MMIO Registers Broadcast Group ccee cece eee eee eee eee eee eee 222 2 17 1 PM_PDWN_Config Power down Configuration Register ceeeeeee ee 222 2 17 2 ECCERRLOGO ECC Error Log O Register ccececeeee eee ee eee ee eee ee ene eaeees 223 2 17 3 ECCERRLOG1 ECC Error Log 1 Register cceeeececeeee stent teeta teeta tenes 223 2 17 4 PM_CMD_PWR Power Management Command Power Register 224 2 17 5 PM_BW_ LIMIT _config BW Limit Configuration Register ceeeeee es 224 2 18 Integrated Graphics VT d Remapping Engine ReGiSterS ceeeeee ee eee eee ee eee teen eee 225 2 18 1 VER_REG VersSion ReQiSter ceceesereeseeeecenetaecescenesrtaneneegeeneesaearsanan 226 2 18 2 CAP_REG Capability ReQiSter ccececeeee eter e eter tener eeeee neat ee teen ea tees 227 2 18 3 ECAP_REG Extended Capability Register ccceeeeeee eee eee eee ene ea eee ee es 230 2 18 4 GCMD_REG Global Command ReGiSter cece eect e eae 232 Datasheet Volume 2 7 5 r D 2 19 2 18 5 GSTS REG Global Status Register eee 235 2 18 6 RTADDR_REG Root Entry Table Address Register c cceeeeee ene ee eee ee ee 236 2 18 7 CCMD_REG Context Command Register cece eee eee e eee eae 237 2 18 8 FSTS_REG Fault Status Register ccccsccccseesercesereeeetesenensaeceseeeeaears 239 2 18 9 FE
293. n identification 20 BO ah Uncore number for the root port Refer to the Intel Xeon Processor E3 1200 Family Specification Update for the value of the RID register 2 10 6 CC6 Class Code Register This register identifies the basic function of the device a more specific sub class and a register specific programming interface B D F Type Address Offset Reset Value 0 6 0 PCI 9 Bh 060400h Access RO Size 24 bits Reset RST Description Value PWR p Base Class Code BCC 23 16 06h Uncore Indicates the base class code for this device This code has the value 06h indicating a Bridge device Sub Class Code SUBCC 15 8 04h Uncore Indicates the sub class code for this device The code is 04h indicating a PCI to PCI Bridge Programming I nterface PI 7 0 00h Uncore Indicates the programming interface of this device This value does not specify a particular register set layout and provides no practical use for this device Datasheet Volume 2 151 Processor Configuration Registers intel 2 10 7 CL6 Cache Line Size Register B D F Type 0 6 0 PCI Address Offset Ch Reset Value 00h Access RW Size 8 bits heset RST Description Value PWR P Cache Line Size CLS 7 0 RW 00h Uncore mplemented by PCI Express devices as a read write field for legacy compatibility purposes but has no impact on any PCI Express device functionality 2 10 8 HDR6 Header Type Register This register id
294. n of PCI Express Virtual Channels associated with this port B D F Type 0 0 0 DMIBAR Address Offset 4 7h Reset Value 0000_0000h Access RO RW O Size 32 bits BIOS Optimal Default 0000000h Reset RST Description Value PWR P fe o resent Low Priority Extended VC Count LPEVCC This field indicates the number of extended Virtual Channels in 000b Uncore addition to the default VC belonging to the low priority VC LPVC group that has the lowest priority with respect to other VC resources in a Sstrict priority VC Arbitration The value of 0 in this field implies strict VC arbitration o o o eea o Extended VC Count EVCC 2 0 RW O 000b Uncore This field indicates the number of extended Virtual Channels in addition to the default VC supported by the device 2 12 3 DMI PVCCAP2 DMI Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type 0 0 0 DMIBAR Address Offset 8 Bh Reset Value 0000_ 0000h Access RO Size 32 bits BIOS Optimal Default 0000h neser RST Description Value PWR P 31 24 RO oon Uncore Reserved for VC Arbitration Table Offset VCATO aef o o f Reeves zo ro oon Uncore Reserved for VC Arbitration Capability VCAC 190 Datasheet Volume 2 Processor Configuration Registers ntel 2 12 4 DMI PVCCTL DMI Port VC Control Register B D F Type 0 0 0 DMI BAR Addres
295. n request 10 Domain selective invalidation request The target domain id must be specified in the DID field 11 Device selective invalidation request The target source 62 61 RW Oh Uncore id s must be specified through the SID and FM fields and the domain id that was programmed in the context entry for these device s must be provided in the DID field Hardware implementations may process an invalidation request by performing invalidation at a coarser granularity than requested Hardware indicates completion of the invalidation request by clearing the ICC field At this time hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field Datasheet Volume 2 237 238 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 28 2Fh Reset Value 0800_0000_0000_0000h Access RW RW V RO V Size 64 bits BIOS Optimal Default 000000000h Reset RST ae js awe st Sie esermton Context Actual Invalidation Granularity CAI G Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion by clearing the ICC field The following are the encodings for this field 00 Reserved 01 Global Invalidation performed This could be in response to a global domain selective or device selective invalidation 60 59 RO V 1h Uncore request 10 Domain selective invali
296. nced Fault Log Register This register specifies the base address of the memory resident fault log region This register is treated as RsvdZ for implementations not supporting advanced translation fault logging AFL field reported as 0 in the Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 58 5Fh Reset Value 0000_0000_0000_0000h Access RO Size 64 bits BIOS Optimal Default 000h Reset RST be joe ace Sats Btn eon O O Fault Log Address FLA This field specifies the base of 4 KB aligned fault log region in system memory Hardware ignores and does not implement bits 63 12 00000000 U 63 HAW where HAW is the host address width 00000h ncore aa Software specifies the base address and size of the fault log region through this register and programs it in hardware through the SFL field in the Global Command register When implemented reads of this field return the value that was last programmed to it Fault Log Size FLS This field specifies the size of the fault log region pointed by the 11 9 Oh Uncore FLA field The size of the fault log region is 2 X 4KB where X is the value programmed in this register When implemented reads of this field return the value that was last programmed to it ae ea eena Datasheet Volume 2 243 intel Processor Configuration Registers 2 18 14 PMEN_REG Protected Memory Enable Register 244 This register enables the DMA protected memory reg
297. nd It is e Set by hardware when software sets the WBF field in the Global Command register e Cleared by hardware when hardware completes the write buffer flushing operation Queued I nvalidation Enable Status QIES This field indicates queued invalidation enable status 0 Disabled Queued invalidation is not enabled 1 Enabled Queued invalidation is enabled Interrupt Remapping Enable Status I RES This field indicates the status of Interrupt remapping hardware 0 Interrupt remapping hardware is Not enabled 1 Interrupt remapping hardware is enabled Interrupt Remapping Table Pointer Status IRTPS This field indicates the status of the interrupt remapping table pointer in hardware This field is cleared by hardware when software sets the SIRTP field in the Global Command register This field is set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register Datasheet Volume 2 235 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 1C 1Fh Reset Value 0000_ 0000h Access RO RO V Size 32 bits BIOS Optimal Default 000000h Reset RST ae js awe ss Site esermton Compatibility Format Interrupt Status CFIS This field indicates the status of Compatibility format interrupts on Intel 64 implementations supporting interrupt remapping The value reported in this field is
298. nded VC Count EVCC 2 0 000b Uncore This field indicates the number of extended Virtual Channels in addition to the default VC supported by the device Datasheet Volume 2 183 intel 2 11 2 Processor Configuration Registers PVCCAP2 Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 6 0 MMR 108 10Bh 0000_0000h RO 32 bits 0000h Reset RST Description Value PWR P VC Arbitration Table Offset VCATO This field indicates the location of the VC Arbitration Table This g field contains the zero based offset of the table in DQWORDS 16 31 24 Oh i Uncore bytes from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority e o o f peee oo zo ro ooh Uncore Reserved for VC Arbitration Capability VCAC 2 11 3 B D F Type Address Offset Reset Value Access Size BIOS Optimal Default PVCCTL Port VC Control Register 0 6 0 MMR 10C 10Dh 0000h RW RO 16 bits 000h Reset RST Description Value PWR P mafe o resend VC Arbitration Select VCAS This field will be programmed by software to the only possible 3 1 RW 000 U b aei value as indicated in the VC Arbitration Capability field Since there is no other VC suppo
299. nerated by the root port only under conditions enabled individually through the Device Control register The root port is enabled to generate SERR messages that will be sent to the PCH for specific root port error conditions generated detected or received on the secondary side of the virtual PCl to PCI bridge The status of SERRs generated is reported in the PCISTS register ened Datasheet Volume 2 147 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset 4 5h Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 00h Reset RST a jw awe Sst Sie esermton Parity Error Response Enable PERRE Controls whether or not the Master Data Parity Error bit in the PCI Status register can bet set Uncore _ 0 Master Data Parity Error bit in PCI Status register can NOT be set 1 Master Data Parity Error bit in PCI Status register CAN be set nc r VGA Palette Snoop VGAPS Not Applicable or Implemented Hardwired to 0 ncore Memory Write and Invalidate Enable MWI E Not Applicable or Implemented Hardwired to 0 3 neers Special Cycle Enable SCE l Not Applicable or Implemented Hardwired to 0 Bus Master Enable BME Controls the ability of the PEG port to forward Memory Read Write Requests in the upstream direction 0 This device is prevented from making memory requests to its primary bus Note that according to PCI Specification as MSI interrupt messages are in ban
300. nge will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 24 25h Reset Value FFF1h Access RW RO Size 16 bits Reset RST Description Value PWR p Prefetchable Memory Base Address PMBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20 of the lower limit of the memory range that will be passed to PCI Express G 64 bit Address Support AS64 This field indicates that the upper 32 bits of the prefetchable 3 0 1h Uncore A memory region base address are contained in the Prefetchable Memory base Upper Address register at 28h 158 Datasheet Volume 2 Processor Configuration Registers Py t 2 10 18 PMLIMIT6 Prefetchable Memory Limit Address Register This register in conjunction with the corresponding Upper Limit Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 40 bit address The lower 8 bits of the Upper Limit Address register are read write and correspond to address bits A 39 32 of the 40 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory b
301. nk Layer State Changed event software must read the Data Link Layer Link Active field of the Link Status register to determine if the link is active before initiating configuration cycles to the hot plugged device Reserved for Electromechanical I nterlock Status EIS If an Electromechanical Interlock is implemented this bit indicates Uncore the current status of the Electromechanical Interlock 0 Electromechanical Interlock Disengaged 1 Electromechanical Interlock Engaged Presence Detect State PDS In band presence detect state 0 Slot Empty 1 Card present in slot This bit indicates the presence of an adapter in the slot reflected by the logical OR of the Physical Layer in band presence detect mechanism and if present any out of band presence detect mechanism defined for the slot s corresponding form factor Note that the in band presence detect mechanism requires that power be applied to an adapter for its presence to be detected Consequently form factors that require a power controller for hot plug must implement a physical pin presence detect mechanism 0 Slot Empty 1 Card Present in slot This register must be implemented on all Downstream Ports that implement slots For Downstream Ports not connected to slots where the Slot Implemented bit of the PCI Express Capabilities Register is Ob this bit must return 1b Uncore Reserved for MRL Sensor State MSS This register reports the status of the
302. ns and not coarser invalidations Zero Length Read ZLR 0 Remapping hardware unit blocks and treats as fault zero length DMA read requests to write only pages 22 1b Uncore 1 Remapping hardware unit supports zero length DMA read requests to write only pages DMA remapping hardware implementations are recommended to report ZLR field as set Maximum Guest Address Width MGAW This field indicates the maximum DMA virtual addressability supported by remapping hardware The Maximum Guest Address Width MGAW is computed as N 1 where N is the value reported in this field For example a hardware implementation supporting 48 bit MGAW reports a value of 47h 101111b in this field If the value in this field is X untranslated and translated DMA requests to addresses above 2 x 1 1 are always blocked by 21 16 100110b Uncore hardware Translations requests to address above 2 x 1 1 from allowed devices return a null Translation Completion Data Entry with R W 0 Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page table structure Adjusted guest address widths supported by hardware are reported through the SAGAW field Implementations are recommended to support MGAW at least equal to the physical addressability host address width of the platform pass wo on ferae SSS Supported Adjusted Guest Address Wid
303. nsmits modified compliance 10 RWS ood pattern if the TXTSSM enters Polling Compliance state Components that support only the 2 5GT s speed are permitted to hardwire this bit to Ob Powerg Transmit Margin txmargin ood This field controls the value of the non deemphasized voltage level at the Transmitter pins This field is reset to 000b on entry to the LTSSM Polling Configuration substate Encodings 000b Normal operating range 001b 111b As defined in the Transmitter Margining section of the PCI Express Base Specification 3 0 not all encodings are required to be implemented 9 7 RWS V 000b For a Multi Function device associated with an upstream port the field in Function 0 is of type RWS and only Function 0 controls the component s Link behavior In all other Functions of that device this field is of type RsvdP Components that support only the 2 5 GT s speed are permitted to hardwire this bit to 000b This register is intended for debug compliance testing purposes only System firmware and software is allowed to modify this register only during debug or compliance testing In all other cases the system must ensure that this register is set to the default value 204 Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 0 0 DMI BAR Address Offset 98 99h Reset Value 0002h Access RWS RWS V Size S bits BIOS Optimal Default Reset RST Description Value PWR P Powerg Se
304. ntLogical IntPhysical mem reads gt Invalid transaction mem writes gt non snoop mem write mem reads gt invalid transaction mem writes gt peer write based on Dev1 VGA en else invalid mem reads gt Invalid transaction Datasheet Volume 2 39 m t 1 Processor Configuration Registers 2 3 13 2 2 3 13 2 1 40 PCI Express Interface Decode Rules All SNOOP semantic PCI Express transactions are kept coherent with processor caches All Snoop not required semantic cycles must reference the direct DRAM address range PCI Express non snoop initiated cycles are not snooped If a Snoop not required semantic cycle is outside of the address range mapped to system memory then it will proceed as follows e Reads Sent to DRAM address 000C_0000h non snooped and will return unsuccessful completion e Writes Sent to DRAM address 000C_0000h non snooped with byte enables all disabled Peer writes from PEG to DMI are not supported If PEG bus master enable is not set all reads and writes are treated as unsupported requests TC VC Mapping Details e VCO enabled by default Snoop port and Non snoop Asynchronous transactions are supported Internal Graphics GMADR writes can occur Unlike FSB chipsets these will NOT be snooped regardless of the snoop not required SNR bit Internal Graphics GMADR reads unsupported Peer writes are only supported between PEG por
305. o Domain ID DID This field indicates the id of the domain whose context entries need to be selectively invalidated This field must be programmed by software for both domain selective and device selective 7 0 RW 00h Uneore invalidation requests The Capability register reports the domain id width supported by hardware Software must ensure that the value written to this field is within this limit Hardware may ignore and not implement bits 15 N where N is the supported domain id width reported in the Capability register Datasheet Volume 2 Processor Configuration Registers 2 18 8 FSTS_REG Fault Status Register This register indicates the various error status B D F Type 0 0 0 GFXVTBAR Address Offset 34 37h Reset Value 0000_0000h Access RO ROS V RW1CS Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR P aof e o j pee o Fault Record Index FRI This field is valid only when the PPF field is set Powerg The FRI field indicates the index from base of the fault recording 15 8 ROS V 00h ood register to which the first pending fault was recorded when the PPF field was Set by hardware The value read from this field is undefined when the PPF field is clear o e oa ea Invalidation Time out Error ITE Hardware detected a Device IOTLB invalidation completion time out At this time a fault event may be generated based on the programming of the Fault Event Control register
306. o the processor by writing a predefined data item a message to a predefined memory address The reporting of the existence of this capability can be disabled by setting MSICH CAPL 0 7Fh In that case walking this linked list will skip this capability and instead go directly from the PCI PM capability to the PCI Express capability B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI 90 91h A005h RO 16 bits Reset RST Description Value PWR p Pointer to Next Capability PNC 15 8 AOh Uncore This contains a pointer to the next item in the capabilities list which is the PCI Express capability Capability 1D CID 7 0 05h Uncore Value of 05h identifies this linked list item capability structure as being for MSI registers Datasheet Volume 2 109 110 Processor Configuration Registers MC Message Control Register System software can modify bits in this register but the device is prohibited from doing so If the device writes the same message multiple times only one of those messages is ensured to be serviced If all of th the same message again until the B D F Type 0 1 0 2 Address Offset 92 93h Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default 00h Reset RST Value PWR Ee n 000b Uncore Uncore Uncore em must be serviced the device must not generate driver services the earlier one PCI Description 64 bit Address Capab
307. of GMADR are RW allowing 128 MB of GMADR Untrusted Aperture Size Low LHSASL This field is used in conjunction with LHSASH The description below is for both fields LHSASH and LHSASL 1 RW K lb ncore 11b Bits 28 27 of GMADR are RO allowing 512 MB of GMADR 10b Illegal Programming 01b Bit 28 of GMADR is RW but bit 27 of GMADR is RO allowing 256 MB of GMADR 00b Bits 28 27 of GMADR are RW allowing 128 MB of GMADR oe o eena Datasheet Volume 2 143 Processor Configuration Registers intel 2 9 Device 2 I O Registers Table 2 11 Device 2 O Register Address Map Address Register Offset Symbol Register Name Reset Value Access 2 9 1 I NDEX MMI O Address Register A 32 bit I O write to this port loads the offset of the MMIO register or offset into the GTT that needs to be accessed An I O Read returns the current value of this register This mechanism to access internal graphics MMIO registers must not be used to access VGA IO registers which are mapped through the MMIO space VGA registers must be accessed directly through the dedicated VGA IO ports B D F Type 0 2 0 PCI 10 Address Offset 0 3h Reset Value 0000_ 0000h Access RW Size 32 bits BI OS Optimal Default 0000_ 0000h jae ame fsics me eeeneton aaj o a penra Register GTT Offset REGGTTO This field selects any one of the DWORD registers within the MMIO register space of Device 2 if the target is MMIO Registe
308. of the Unsupported Request Error Severity bit In production systems setting the Fatal Error Detected bit is not an option as support for AER will not be RW1C reported Fatal Error Detected FED When set this bit indicates that fatal error s were detected Errors are logged in this register regardless of whether error RW1C Uncore reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask register Uncore Uncore Non Fatal Error Detected NFED When set this bit indicates that non fatal error s were detected Errors are logged in this register regardless of whether error RW1C Uncore reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this register regardless of the settings of the uncorrectable error mask RW1C register register regardless of the settings of the correctable error mask Datasheet Volume 2 173 register Correctable Error Detected CED When set this bit indicates that correctable error s were detected Errors are logged in this register regardless of whether Uncore error reporting is enabled or not in the Device Control register When Advanced Error Handling is enabled errors are logged in this Processor Configuration Registers intel 2 10 38 LCTL Link Control Register This regis
309. of this device and can be used to set the device into a new power state If software attempts to write an unsupported state to this field the write operation must complete normally on the bus but the data is discarded and no state change occurs 00 DO 01 D1 Not supported in this device 10 D2 Not supported in this device 11 D3 Support of D3cold does not require any special action 1 0 RW Uncore While in the D3hot state this device can only act as the target of PCI configuration transactions for power management control This device also cannot generate interrupts or respond to MMR cycles in the D3 state The device must return to the DO state in order to be fully functional When the Power State is other than DO the bridge will Master Abort that is not claim any downstream cycles with the exception of type 0 configuration cycles Consequently these unclaimed cycles will go down DMI and come back up as Unsupported Requests which the processor logs as Master Aborts in Device 0 PCISTS 13 There is no additional hardware functionality required to support these Power States SS_CAPID Subsystem ID and Vendor ID Capabilities Register This capability is used to uniquely identify the subsystem where the PCI device resides Because this device is an integrated part of the system and not an add in device it is anticipated that this capability will never be used However it is necessary because Microsoft will tes
310. ointer operation using the value provided in the Advanced Fault Log register Advanced Fault Logging Status AFLS This field is valid only for implementations supporting advanced fault logging It indicates the advanced fault logging status 0 Advanced Fault Logging is Not enabled 1 Advanced Fault Logging is enabled Write Buffer Flush Status WBFS This field is valid only for implementations requiring write buffer flushing This field indicates the status of the write buffer flush command It is e Set by hardware when software sets the WBF field in the Global Command register e Cleared by hardware when hardware completes the write buffer flushing operation Queued I nvalidation Enable Status QIES This field indicates queued invalidation enable status 0 queued invalidation is not enabled 1 queued invalidation is enabled Interrupt Remapping Enable Status IRES This field indicates the status of Interrupt remapping hardware 0 Interrupt remapping hardware is not enabled 1 Interrupt remapping hardware is enabled Interrupt Remapping Table Pointer Status IRTPS This field indicates the status of the interrupt remapping table pointer in hardware This field is cleared by hardware when software sets the SIRTP field in the Global Command register This field is Set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table A
311. om 0 3 GB and 4 9 GB BIOS will report an address space of 9 GB to the OS PCI Express Configuration Address Space Unlike previous platforms PCIEXBAR is located in device 0 configuration space as in FSB platforms The processor detects memory accesses targeting PCIEXBAR BIOS must assign this address range such that it will not conflict with any other address ranges See the configuration portion of this document for more details Datasheet Volume 2 Processor Configuration Registers E t 2 3 6 PCI Express Graphics Attach PEG The processor can be programmed to direct memory accesses to a PCI Express interface When addresses are within either of two ranges specified using registers in each PEG s configuration space e The first range is controlled using the Memory Base Register MBASE and Memory Limit Register MLIMIT registers e The second range is controlled using the Pre fetchable Memory Base PMBASE and Pre fetchable Memory Limit PMLIMIT registers Conceptually address decoding for each range follows the same basic concept The top 12 bits of the respective Memory Base and Memory Limit registers correspond to address bits A 31 20 of a memory address For the purpose of address decoding the processor assumes that address bits A 19 0 of the memory base are zero and that address bits A 19 0 of the memory limit address are F_FFFFh This forces each memory address range to be aligned to 1 MB boundary and to have
312. om DMI Interface to the following address ranges e All snoop memory read and write accesses to Main DRAM including PAM region except stolen memory ranges TSEG AOOOOh BFFFFh space e Write accesses to enabled VGA range MBASE MLIMIT and PMBASE PMLIMIT will be routed as peer cycles to the PCI Express interface e Write accesses above the top of usable DRAM and below 4 GB not decoding to PCI Express or GMADR space will be treated as master aborts e Read accesses above the top of usable DRAM and below 4 GB not decoding to PCI Express will be treated as unsupported requests e Reads and accesses above the TOUUD will be treated as unsupported requests on VCO VCp DMI Interface memory read accesses that fall between TOLUD and 4 GB are considered invalid and will master abort These invalid read accesses will be reassigned to address 000C_0000h and dispatch to DRAM Reads will return unsupported request completion Writes targeting PCI Express space will be treated as peer to peer cycles There is a known usage model for peer writes from DMI to PEG A video capture card can be plugged into the PCH PCI bus The video capture card can send video capture data writes directly into the frame buffer on an external graphics card writes to the PEG port As a result peer writes from DMI to PEG must be supported I O cycles and configuration cycles are not supported in the upstream direction The result will be an unsupported request completion
313. onfiguration Registers PAM1 Programmable Attribute Map 1 Register This register controls the read write and shadowing attributes of the BIOS range from C_0000h to C_7FFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI e WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 81h Reset Value 00h Access RW Size a ae BIOS Optimal Default Reset RST Description Value PWR p mje o pea 0C4000 0C7FFF Attribute HI ENABLE This field controls the steering of
314. or combined Graphics Translation Table Modification Range and Memory Mapped Range GTTADR will be at GTTMMADR 2 MB while the MMIO base address will be the same as GTTMMADR The rules for the above programmable ranges are 1 For security reasons the processor will now positively decode FFEO_0000h to FFFF_FFFFh to DMI This ensures the boot vector and BIOS execute off PCH ALL of these ranges MUST be unique and NON OVERLAPPING It is the BIOS or system designers responsibility to limit memory population so that adequate PCI PCI Express High BIOS PCI Express Memory Mapped space and APIC memory space can be allocated In the case of overlapping ranges with memory the memory decode will be given priority This is a Intel TXT requirement It is necessary to get Intel TXT protection checks avoiding potential attacks There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges Accesses to overlapped ranges may produce indeterminate results 6 Software must not access BO DO FO 32 bit memory mapped registers with requests that cross a DW boundary Datasheet Volume 2 Processor Configuration Registers Figure 2 1 represents system memory address map in a simplified form Figure 2 1 System Address Range Example HOST SYSTEM VIEW PHYSICAL MEMORY DRAM CONTROLLER VIEW 512 GB PCI Memory Add Range subtractively decoded to TOUUD BASE PN Reclaim Limit 1 MB aligned Re
315. ory Graphics Mode Select GMS This field is used to select the amount of main memory that is pre allocated to support the Internal Graphics device in VGA non linear and Native linear modes BIOS ensures that memory is pre allocated only when internal graphics is enabled This register is also Intel TXT lockable Hardware does not clear or set any of these bits automatically based on IGD being disabled enabled BIOS Requirement BIOS must not set this field to Oh if IVD bit 1 of this register is 0 Oh 0 MB 1h 32 MB 2h 64 MB 3h 96 MB Uncore 4h 128 MB 5h 160 MB 6h 192 MB 7h 224 MB 8h 256 MB 9h 288 MB Ah 320 MB Bh 352 MB Ch 384 MB Dh 416 MB Eh 448MB Fh 480 MB 10h 512 MB Other Reserved Datasheet Volume 2 57 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 50 51h Reset Value 0028h Access RW KL RW L Size 16 bits BIOS Optimal Default 00h Reset RST CACACE se meen o o o pee o IGD VGA Disable IVD 0 Enable Device 2 IGD claims VGA memory and I O cycles the Sub Class Code within Device 2 Class Code register is 00 1 Disable Device 2 IGD does not claim VGA cycles Memory and 1 O and the Sub Class Code field within Device 2 1 RW L Uncore function 0 Class Code register is 80h BIOS Requirement BIOS must not set this bit to 0 if the GMS field bits 7 3 of this register pre allocates no memory This bit MUST be
316. ositively decode this range to DMI This positive decode will ensure any overlapping ranges will be ignored The top 2 MB FFE0_0000h FFFF_FFFFh of the PCI Memory Address Range is reserved for System BIOS High BIOS extended BIOS for PCI devices and the A20 alias of the system BIOS The processor begins execution from the High BIOS after reset This region is positively decoded to DMI The actual address space required for the BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB so that full 2 MB must be considered Datasheet Volume 2 25 26 Processor Configuration Registers Main Memory Address Space 4 GB to TOUUD The processor supports 39 bit addressing The maximum main memory size supported is 32 GB total DRAM memory A hole between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger As aresult TOM and TOUUD registers and REMAPBASE REMAPLIMIT registers become relevant The remap configuration registers exist to remap lost main memory space The greater than 32 bit remap handling will be handled similar to other MCHs Upstream read and write accesses above 39 bit addressing are treated as invalid cycles by PEG and DMI Top of Memory TOM The Top of Memory TOM register reflects the total amount of populated physical memory This is NOT necessarily the highest main memory address holes may exist in main memory address map due to addresses allocated for memory mapp
317. ot Capabilities Register ssssssssssrrrrsrrrrnsrrrrrrrrrrrserrrrrsene 118 2 6 41 SLOTCTL Slot Control Register sscciiiiisaisiiadniis siisi kierinn asirik iaiia 120 2 6 42 SLOTSTS Slot Status ReGiSter rriten tee eee eee resets E aE aiai i 122 2 6 43 RCTL Root Control ReGiSter cece cece cece eee ee eee ee eee teeta eee nett tee ne ent ees 124 2 6 44 LCTL2 Link Control 2 Register ccecececeee eee ee eee ee eee eee eae teeta ene eatees 125 2 7 PCI Device 1 Function 0 2 Extended Configuration Registers eceeeee eens eens 127 2 7 1 PVCCAP1 Port VC Capability Register 1 0 ec ee eee erence ee eee eens 127 2 7 2 PVCCAP2 Port VC Capability Register 22 0 0 cece eeee eee teeta ee teenie eae 128 2 7 3 PVCCTL Port VC Control Register cceceecee cece eee eens etna tee ea een eeataes 128 2 7 4 VCORCAP VCO Resource Capability Register ccceceeeee eset ene eaten eee 129 2 7 5 VCORCTL VCO Resource Control ReQiSter ccceeece cece crete eee teen een enes 130 2 7 6 VCORSTS VCO Resource Status Register c cece eee ee eee teeter teens 131 2 7 7 PEG_TC PCI Express Completion Time out Register cceeeeee eee eee 131 2 8 PCI Device 2 Configuration Registers cece eect ee eee nee eee teeter ee tered 132 2 8 1 VID2 Vendor Identification Register ccceeceeeee eee ee eee teat eee teen neat ees 133 2 8 2 DID2 Device Identification REGiSter ce
318. ot Status RO RO V Link Control 2 Register Name ps lt ZR O lt D o 86 Datasheet Volume 2 Processor Configuration Registers intel 2 6 1 VI D1 Vendor Identification Register This register combined with the Device Identification register uniquely identify any PCI device B D F Type 0 1 0 2 PCI Address Offset 0 1h Reset Value 8086h Access RO Size 16 bits Reset RST Description Value PWR P Vendor Identification VID Bosen Uncore ucore 18g standard identification for Intel 2 6 2 DI D1 Device Identification Register This register combined with the Vendor Identification register uniquely identifies any PCI device B D F Type 0 1 0 2 PCI Address Offset 2 3h Reset Value See Section 2 2 Access RO FW Size 16 bits Reset RST ae GREJE s Device Identification Number MSB DID_MSB 15 0 RO FW Section 2 2 Uncore Identifier assigned to the processor root port virtual PCI to PCI bridge PCI Express Graphics port Datasheet Volume 2 87 t i Processor Configuration Registers 2 6 3 PCI CMD1 PCI Command Register B D F Type 0 1 0 2 PCI Address Offset 4 5h Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 00h Reset RST ES ee pm we a irene oOo INTA Assertion Disable INTAAD 0 This device is permitted to generate INTA interrupt messages 1 This device is prevented from generating interrupt
319. ot support draining of DMA read requests Hardware supports draining of DMA read requests DMA Write Draining DWD 0 Hardware does Not support draining of DMA write requests 1 Hardware supports draining of DMA write requests Maximum Address Mask Value MAMV The value in this field indicates the maximum supported value for 001001b Wncore the Address Mask AM field in the Invalidation Address register IVA_REG and IOTLB Invalidation Descriptor iotlb_inv_dsc This field is valid only when the PSI field in Capability register is reported as set Number of Fault recording Registers NFR Number of fault recording registers is computed as N 1 where N is the value reported in this field 00000000b Uncore Implementations must support at least one fault recording register NFR 0 for each remapping hardware unit in the platform The maximum number of fault recording registers per remapping hardware unit is 256 Page Selective I nvalidation PSI 0 Hardware supports only domain and global invalidates for IOTLB 1b 1 Hardware supports page selective domain and global invalidates for I OTLB Hardware implementations reporting this field as set are recommended to support a Maximum Address Mask Value MAMV value of at least 9 fej o pena ooo Super Page Support SPS This field indicates the super page sizes supported by hardware A value of 1 in any of these bits indicates the corresponding super page size is supported T
320. ot supported 1 Protected high memory region is supported Protected Low Memory Region PLMR 0 Protected low memory region is Not supported 1 Protected low memory region is supported Required Write Buffer Flushing RWBF 0 No write buffer flushing is needed to ensure changes to memory resident structures are visible to hardware 1 Software must explicitly flush the write buffers to ensure updates made to memory resident remapping structures are visible to hardware Advanced Fault Logging AFL 0 Advanced fault logging is not supported Only primary fault logging is supported 1 Advanced fault logging is supported Number of domains supported ND 000 Hardware supports 4 bit domain ids with support for up to 16 domains 001 Hardware supports 6 bit domain ids with support for up to 64 domains 010 Hardware supports 8 bit domain ids with support for up to 256 domains 011 Hardware supports 10 bit domain ids with support for up to 1024 domains 100 Hardware supports 12 bit domain ids with support for up to 4K domains 100 Hardware supports 14 bit domain ids with support for up to 16K domains 110 Hardware supports 16 bit domain ids with support for up to 64K domains 111 Reserved Datasheet Volume 2 229 Processor Configuration Registers intel 2 18 3 ECAP_REG Extended Capability Register This register reports remapping hardware extended capabilities B D F Type 0
321. ot the Master Data Parity Error bit in the Secondary Status register is set when the root port receives RW Gacore across the link upstream a Read Data Completion Poisoned TLP 0 Master Data Parity Error bit in Secondary Status register can NOT be set 1 Master Data Parity Error bit in Secondary Status register CAN be set Datasheet Volume 2 105 Processor Configuration Registers intel 2 6 25 PM_CAPID1 Power Management Capabilities Register B D F Type 0 1 0 2 PCI Address Offset 80 83h Reset Value C803_9001h Access RO RO V Size 32 bits Reset RST Description Value PWR j PME Support PMES This field indicates the power states in which this device may indicate PME wake using PCI Express messaging DO D3hot amp 31 27 19h Uncore D3cold This device is not required to do anything to support D3hot amp D3cold it simply must report that those states are supported Refer to the PCI Power Management 1 1 Specification for encoding explanation and other power management details D2 Power State Support D2PSS 26 Uncore Hardwired to 0 to indicate that the D2 power management state is NOT supported D1 Power State Support D1PSS 25 Uncore Hardwired to 0 to indicate that the D1 power management state is NOT supported Auxiliary Current AUXC 24 22 000b Uncore Hardwired to 0 to indicate that there are no 3 3Vaux auxiliary current requirements Device Specific Initialization DSI 21 Uncore Hardwired
322. ows 0 Clock power management is disabled and device must hold CLKREQ signal low Uncore 1 Device is permitted to use CLKREQ signal to power manage link clock according to protocol defined in appropriate form factor specification Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabilities Register must hardwire this bit to Ob Extended Synch ES 0 Standard Fast Training Sequence FTS 1 Forces the transmission of additional ordered sets when exiting the LOs state and when in the Recovery state Uncore This mode provides external devices such as logic analyzers monitoring the Link time to achieve bit and symbol lock before the link enters LO and resumes communication This is a test mode only and may cause other undesired side effects such as buffer overflows or underruns 174 Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 6 0 PCI Address Offset BO B1h Reset Value 0000h Access RO RW RW V Size 16 bits BIOS Optimal Default 00h Reset RST A jw face Ses Se esermon Common Clock Configuration CCC 0 Indicates that this component and the component at the opposite end of this Link are operating with asynchronous reference clock RW Uncore 1 Indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference c
323. pe can be enabled B D F Type Address Offset Reset Value 0 0 0 PCI CC CDh 0000h Access RW Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR p Uncore Uncore Datasheet Volume 2 SMI on Multiple Bit DRAM ECC Error DMESMI 1 The Host generates an SMI DMI message when it detects a multiple bit error reported by the DRAM controller 0 Reporting of this condition using SMI messaging is disabled For systems not supporting ECC this bit must be disabled SMI on Single bit ECC Error DSESMI 1 The Host generates an SMI DMI special cycle when the DRAM controller detects a single bit error 0 Reporting of this condition using SMI messaging is disabled For systems that do not support ECC this bit must be disabled 81 Processor Configuration Registers 2 5 35 SCI CMD SCI Command Register This register enables various errors to generate an SMI DMI special cycle When an error flag is set in the ERRSTS register it can generate an SERR SMI or SCI DMI special cycle when enabled in the ERRCMD SMICMD or SCICMD registers respectively Note that one and only one message type can be enabled B D F Type 0 0 0 PCI Address Offset CE CFh Reset Value 0000h Access RW Size 16 bits BIOS Optimal Default 0000h Reset RST Pa jose ace Ssiss te esermton OE SCI on Multiple Bit DRAM ECC Error DMESCI 1 The Host generates an SCI DMI message when it detects a multi
324. ped outside of the IGD or if IGD is disabled the legacy VGA memory range AOOOOh BFFFFh is mapped either to the DMI Interface or PCI Express depending on the programming of the VGA Enable bit in the BCTRL configuration register in the PEG configuration space and the MDAPxx bits in the Legacy Access Control LAC register in Device 0 configuration space The same register controls mapping VGA I O address ranges VGA I O range is defined as addresses where A 9 0 are in the ranges 3BOh to 3BBh and 3COh to 3DFh inclusive of ISA address aliases A 15 10 are not decoded The function and interaction of these two bits is described below VGA Enable Controls the routing of processor initiated transactions targeting VGA compatible I O and memory address ranges When this bit is set the following processor accesses will be forwarded to the PCI Express e memory accesses in the range 0A0000h to OBFFFFh e I O addresses where A 9 0 are in the ranges 3BOh to 3BBh and 3COh to 3DFh including ISA address aliases A 15 10 are not decoded When this bit is set to a 1 Forwarding of these accesses issued by the processor is independent of the I O address and memory address ranges defined by the previously defined base and limit registers Forwarding of these accesses is also independent of the settings of the ISA Enable settings if this bit is 1 Accesses to I O address range x3BCh x3BFh are forwarded to DMI Interface When this bit is set to a
325. ple bit error reported by the DRAM controller 0 Reporting of this condition using SCI messaging is disabled For systems not supporting ECC this bit must be disabled SCI on Single bit ECC Error DSESCI 1 The Host generates an SCI DMI special cycle when the DRAM Uncore controller detects a single bit error 0 Reporting of this condition using SCI messaging is disabled For systems that do not support ECC this bit must be disabled 2 5 36 SKPD Scratchpad Data Register This register holds 32 writable bits with no functionality behind them It is for the convenience of BIOS and graphics drivers B D F Type Address Offset Reset Value 0 0 0 PCI DC DFh 0000_ 0000h Access RW Size 32 bits Reset RST Description Value PWR P 0000 000 Scratchpad Data SKPD 31 0 RW U j rw 00080 unore T ORE St data wore 82 Datasheet Volume 2 Processor Configuration Registers 2 5 37 intel CAPIDO_A Capabilities A Register This register control of bits in this register are only required for customer visible SKU differentiation B D F Type 0 0 0 PCI Address Offset E4 E7h Default Value 0000_0000h Access RO FW RO KFW Size 32 bits BIOS Optimal Default 000000h Reset RST Description Value PWR p Ro KFw o f Ro KFw ob f Reserved S Ro KFw o f Reserved o Ro KFw ob Reserved o 4 Row ob Reserved o Row Reserved Cis ECC Disable ECCDIS RO FW Uncore 0 ECC capabl
326. port ZLR field as set Maximum Guest Address Width MGAW This field indicates the maximum DMA virtual addressability supported by remapping hardware The Maximum Guest Address Width MGAW is computed as N 1 where N is the value reported in this field For example a hardware implementation supporting 48 bit MGAW reports a value of 47 101111b in this field If the value in this field is X untranslated and translated DMA requests to addresses above 2 x 1 1 are always blocked by hardware Translations requests to address above 2 x 1 1 from 21 16 100110b pniente allowed devices return a null Translation Completion Data Entry with R W 0 Guest addressability for a given DMA request is limited to the minimum of the value reported through this field and the adjusted guest address width of the corresponding page table structure Adjusted guest address widths supported by hardware are reported through the SAGAW field Implementations are recommended to support MGAW at least equal to the physical addressability host address width of the platform sofe a resend ooo Supported Adjusted Guest Address Widths SAGAW This 5 bit field indicates the supported adjusted guest address widths which in turn represents the levels of page table walks for the 4 KB base page size supported by the hardware implementation A value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported The adjusted gu
327. ported If when translated the resulting physical address is to enable SMM DRAM space the request will be remapped to address 000C_0000h with de asserted byte enables PCI Express and DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns PCI Express and DMI Interface reads to GMADR will be remapped to address 000C_0000h The read will complete with UR unsupported request completion status GTT fetches are always decoded at fetch time to ensure not in SMM actually anything above base of TSEG or 640K 1M Thus they will be invalid and go to address 000C_0000h but that is not specific to PCI Express or DMI it applies to processor or internal graphics engines ME Stolen Memory Accesses There are only 2 ways to legally access ME stolen memory e PCH accesses mapped to VCm will be decoded to ensure only ME stolen memory is targeted These VCm accesses will route non snooped directly to DRAM This is the means by which the ME engine located within the PCH is able to access the ME stolen range e The Display engine is allowed to access MEstolen memory as part of KVM flows Specifically Display initiated HHP reads for displaying a KVM frame and display initiated LP non snoop writes for display writing a KVM captured frame to ME stolen memory are allowed Datasheet Volume 2 35 m t 1 Processor Configuration Registers 2 3 11 1 36 1 O Address Space The sys
328. pplied by slot Power limit in Watts is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field If this field is written the link sends a Set_Slot_Power_Limit message Reserved for Hot plug Capable HPC When set to 1 this bit indicates that this slot is capable of supporting hot plug operations Reserved for Hot plug Surprise HPS When set to 1 this bit indicates that an adapter present in this slot might be removed from the system without any prior notification This is a form factor specific capability This bit is an indication to the operating system to allow for such removal without impacting continued software operation Reserved for Power I ndicator Present PIP When set to 1 this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot Reserved for Attention Indicator Present Al P When set to 1b this bit indicates that an Attention Indicator is electrically controlled by the chassis Reserved for MRL Sensor Present MSP When set to 1 this bit indicates that an MRL Sensor is implemented on the chassis for this slot Reserved for Power Controller Present PCP When set to 1 this bit indicates that a software programmable Power Controller is implemented for this slot adapter depending on form factor Reserved for Attention Button Present ABP When set to 1 this bit indicates that an Attention Button for this slot
329. prefetchable from the processor perspective B D F Type 0 1 0 2 PCI Address Offset 26 27h Reset Value 0001h Access RW RO Size 16 bits Reset RST Description Value PWR P Prefetchable Memory Address Limit PMLI MIT Ea ua unos field corresponds to A 31 20 of the upper limit of the address range passed to PCI Express G 64 bit Address Support AS64B Uncore This field indicates that the upper 32 bits of the prefetchable memory region limit address are contained in the Prefetchable Memory Base Limit Address register at 2Ch Datasheet Volume 2 Processor Configuration Registers PT t 2 6 19 PMBASEU1 Prefetchable Memory Base Address Upper Register The functionality associated with this register is present in the PEG design implementation This register in conjunction with the corresponding Upper Base Address register controls the processor to PCI Express G prefetchable memory access routing based on the following formula PREFETCHABLE_MEMORY_BASE lt address lt PREFETCHABLE_MEMORY_LIMIT The upper 12 bits of this register are read write and correspond to address bits A 31 20 of the 39 bit address The lower 7 bits of the Upper Base Address register are read write and correspond to address bits A 38 32 of the 39 bit address This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the define
330. quest Hardware implementations not supporting Device OTLBs DI field 61 60 Uncore clear in Extended Capability register treat this field as RsvdZ When supported this field is valid only when the F bit is set and when the fault reason FR indicates one of the DMA remapping fault conditions Powerg Fault Reason FR 39 32 ROS V efet ood This field is relevant only when the F bit is set I dentifier SID 0000000 power 0000000 g Requester id associated with the fault condition 00b ood This field is relevant only when the F bit is set 258 Datasheet Volume 2 Processor Configuration Registers intel 2 18 31 VTPOLICY DMA Remap Engine Policy Control Register This register contains all the policy bits related to the DMA remap engine B D F Type 0 0 0 GFXVTBAR Address Offset FFO FF3h Reset Value 0000_0000h Access RO RO KFW RW KL RW L Size 32 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P DMA Remap Engine Policy Lock Down DMAR_LCKDN This bit protects all the DMA remap engine specific policy 31 RW KL Uncore configuration registers Once this bit is set by software all the DMA remap engine registers within the range FOOh to FFCh will be read only This bit can only be cleared through platform reset FN o i eea o Datasheet Volume 2 259 Processor Configuration Registers 2 19 PCU MCHBAR Registers Table 2 21 lists the registers arranged by address o
331. r Link Training TXTRN This bit indicates that the Physical Layer TXTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun Hardware clears this bit when the TXTSSM exits the Configuration Recovery state once Link training is complete pe o peen Datasheet Volume 2 Processor Configuration Registers B D F Type 0 1 0 2 PCI Address Offset B2 B3h Reset Value 1001h Access RO V RW1C RO Size ar bits BIOS Optimal Default Reset RST js awe ss Sie esermton Negotiated Link Width NLW This field indicates negotiated link width This field is valid only when the link is in the LO LOs or L1 states after link width negotiation is successfully completed 00h Reserved RO V 00h Uncore 01h X1 02h X2 04h X4 08h X8 10h X16 All other encodings are reserved Current Link Speed CLS This field indicates the negotiated Link speed of the given PCI Express Link 3 0 RO V 1h Uncore 0001b 2 5 GT s PCI Express Link 0010b 5 0 GT s PCI Express Link All other encodings are reserved The value in this field is undefined when the Link is not up 2 6 40 SLOTCAP Slot Capabilities Register Note Hot Plug is not supported on Intel Xeon processor E3 1200 family platforms B D F Type 0 1 0 2 PCI Address Offset B4 B7h Reset Value 0004_ 0000h Access RW O RO Size 32 bits Reset RST se js awe Gs
332. r the device must not generate TLPs exceeding the value set in this field RO ob Uncore Reserved for Enable Relaxed Ordering ROE Unsupported Request Reporting Enable URRE When set allows signaling ERR_NONFATAL ERR_FATAL or ERR_CORR to the Root Control register when detecting an RW Uncore Unmasked Unsupported Request UR An ERR_CORR is signaled when an unmasked Advisory Non Fatal UR is received An ERR_FATAL or ERR_NONFATAL is sent to the Root Control register when an uncorrectable non Advisory UR is received with the severity bit set in the Uncorrectable Error Severity register Fatal Error Reporting Enable FERE When set enables signaling of ERR_FATAL to the Root Control RW Uncore register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Non Fatal Error Reporting Enable NERE When set enables signaling of ERR_NONFATAL to the Rool Control RW Uncore register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting Correctable Error Reporting Enable CERE When set enables signaling of ERR_CORR to the Root Control RW Uncore register due to internally detected errors or error messages received across the link Other bits also control the full scope of related error reporting 15 11 7 5 3 2 1 Datasheet Volume 2 113 114
333. r Present PCP When set to 1b this bit indicates that a software programmable Power Controller is implemented for this slot adapter depending on form factor Reserved for Attention Button Present ABP When set to 1b this bit indicates that an Attention Button for this slot is electrically controlled by the chassis 178 Datasheet Volume 2 Processor Configuration Registers intel 2 10 41 SLOTCTL Slot Control Register Note Hot Plug is not supported on Intel Xeon processor E3 1200 family platforms B D F Type 0 6 0 PCI Address Offset B8 B9h Reset Value 0000h Access RO Size 16 bits BIOS Optimal Default Oh Reset RST Description Value PWR P 15 13 Ro on f Reseved S Reserved for Data Link Layer State Changed Enable DLLSCE If the Data Link Layer Link Active capability is implemented when Uncore set to 1b this field enables software notification when Data Link Layer Link Active field is changed If the Data Link Layer Link Active capability is not implemented this bit is permitted to be read only with a value of Ob Reserved for Electromechanical I nterlock Control EIC If an Electromechanical Interlock is implemented a write of 1b to this field causes the state of the interlock to toggle A write of Ob to this field has no effect A read to this register always returns a 0 Uncore Reserved for Power Controller Control PCC If a Power Controller is implemented this field
334. r is also set to 1 enabling VGA I O decoding and forwarding by the bridge 0 Execute 10 bit address decodes on VGA I O accesses 1 Execute 16 bit address decodes on VGA I O accesses VGA Enable VGAEN 3 RW Uncore This bit controls the routing of processor initiated transactions targeting VGA compatible I O and memory address ranges See the VGAEN MDAP table in Device 0 offset 97h 0 ISA Enable ISAEN Needed to exclude legacy resource decode to route ISA resources to legacy decode path Modifies the response by the root port to an I O access issued by the processor that target ISA I O addresses This applies only to I O addresses that are enabled by the OBASE 2 RW U and IOLIMIT registers ncore 0 All addresses defined by the IOBASE and IOLIMIT for processor I O transactions will be mapped to PCI Express G The root port will not forward to PCI Express G any I O transactions addressing the last 768 bytes in each 1KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers Datasheet Volume 2 163 Processor Configuration Registers B D F Type 0 6 0 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Size R bits BIOS Optimal Default Reset RST js awe ss Site esermton SERR Enable SERREN 0 No forwarding of error messages from secondary side to 1 RW U primary side that could result in an SERR ncore 3 ERR_COR ERR_NONFATAL and ERR_FATAL messages
335. rank idle period in DCLK cycles that causes power down entrance Datasheet Volume 2 Processor Configuration Registers intel 2 17 2 ECCERRLOGO ECC Error Log 0 Register B D F Type 0 0 0 MCHBAR_ MCBCAST Address Offset 4cCC8 4CCBh Reset Value 0000_0000h Access ROS V Size 32 bits BIOS Optimal Default 0000h Reset RST zaii GLEIC p Error Bank ERRBANK 31 29 ROS V 000b ST This field holds the Bank Address of the read transaction that had the ECC error p Error Rank ERRRANK 28 27 ROS V S This field holds the Rank ID of the read transaction that had the ECC error Powerg Error Chunk ERRCHUNK 26 24 ROS V 000b 2s 24 ros ooo Pogo Holds the chunk number of the error stored in the register p Error Syndrome ERRSYND 23 16 ROS V 00h pee This field contains the error syndrome A value of FFh indicates that the error is due to poisoning mafo o j eena o ooo Uncorrectable Error Status MERRSTS This bit is set when an uncorrectable multiple bit error occurs on a P memory read data transfer When this bit is set the address that 1 ROS V owerg caused the error and the error syndrome are also logged and they ood RREA are locked until this bit is cleared This bit is cleared when the corresponding bit in 0 0 0 PCI ERRSTS is cleared Correctable Error Status CERRSTS This bit is set when a correctable single bit error occurs on a memory read data transfer When this bit is set the address that
336. ration Registers intel 2 19 8 SSKPD Sticky Scratchpad Data Register This register holds 64 writable bits with no functionality behind them It is for the convenience of BIOS and graphics drivers B D F Type 0 0 0 MCHBAR PCU Address Offset 5D10 5D17h Reset Value 0000_0000_0000_0000h Access RWS Size 64 bits Reset RST Description Value PWR p Scratchpad Data SKPD Field 34 32 contains the value to match with the PCI PMSYNC p configuration done by BIOS required for discrete USB2PCI cards 63 32 RWS 00000000h OWENS Refer to BWG for more details Field 47 35 contains the timer value on top of the PCH hysteresis value It is given in units of 10 24 us Refer to BWG for more details Reserved for Future Use RWSVD3 31 30 RWS Powerg Bit 30 controls the way BIOS calculate WM3 value It reflects the ood value of PCU_MISC_ENABLES LNPLLfastLockDisable Bit 31 is reserved for future use MPLL Shutdown Latency Time WM3 Number of microseconds to access memory if memory is in Self Refresh SR with MDLLs and Memory PLLs shut off 0 5us granularity 00h 0 us Olh 0 5 us p Powerg 02h 1 us 29 24 RWS 00h ood 3Fh 31 5 us NOTE The value in this field corresponds to the memory latency requested to the Display Engine when Memory PLL Shutdown is enabled The Display LP3 latency and watermark values GTTMMADR offset 0x45110 should be programmed to match the latency in this register 23 22 J ws oo
337. re fault recording registers has pending faults The FRI field is updated by hardware whenever the PPF field is set by hardware Also depending on the programming of Fault Event Control register a fault event is generated when hardware sets this field Primary Fault Overflow PFO Powerg Hardware sets this field to indicate overflow of fault recording RW1CS ood registers Software writing 1 clears this field When this field is set hardware does not record any new faults until software clears this field 284 Datasheet Volume 2 Processor Configuration Registers 2 21 9 FECTL_REG Fault Event Control Register This register specifies the fault event interrupt message control bits B D F Type 0 0 0 VCOPREMAP Address Offset 38 3Bh Reset Value 8000_0000h Access RW RO V Size 32 bits BIOS Optimal Default 0000_0000h Reset RST Description Value PWR P ofo o peen Datasheet Volume 2 Interrupt Mask IM 0 No masking of interrupt When an interrupt condition is detected hardware issues an interrupt message using the Fault Event Data and Fault Event Address register values 1 This is the value on reset Software may mask interrupt message generation by setting this field Hardware is prohibited from sending the interrupt message when this field is set Interrupt Pending IP Hardware sets the IP field when it detects an interrupt condition which is defined as e When primary fault loggin
338. re may be obtained by calling 1 800 548 4725 or by visiting Intel s website at http www intel com Intel Intel Core Intel Xeon and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2011 Intel Corporation All Rights Reserved 2 Datasheet Volume 2 Contents 1 DP NtrOCU CHOON EAR hanecii ic oe aie oe a IG ad ed dei 11 Processor Configuration Registers c ccc eerie eae 13 2 1 Register TEMMIinGlOGy iicccsvccesticietic aes detent Miao Got odie aE A eee seh 13 2 2 PCI Devices and Functions ON Processor cee ce cece teen eee eee eee eee teeta eee nett eet te es 14 23 System Address Map s sick sccavsiies demdeniseeisi seid EEE RE tase tents nia bid ore NE TEREE 15 2 3 1 Legacy Address RAnge eccccccese eee e eect eet eee eer teen eee eet tennant eaten nent tes 18 2 3 1 DOS Range Oh 9_FFFFh cceeeeeeene sent eee ea eee e nets eeeeena teens 18 2 3 1 Legacy Video Area A_OOOOh B_FFFFh c cece eee e eee 19 2 31 7 PAM C_ 0000M F FFERR visiecids cagietoi spinania oi saaneiden 20 2 3 2 Main Memory Address Range 1 MB TOLUD ccc ceeeeee eee e ee eeeee eee ees 20 2 3 2 1 ISA Hole 15 MB 16 MB cccceceee cece ee eee ee ee eee eee ER ni 21 23 22 TSEG diseectohiantimemavietaienn Gavan ied Minti a Montieteteade saan ant 21 2 3 2 3 Protected Memory Range PMR programm
339. re used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read accesses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 80h Reset Value 00h Access RW Size 8 bits BIOS Optimal Default 00h Reset RST Description Value PWR p mefe o pee o OFOOOO OFFFFF Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OF_0000h to OF_FFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Oe o pee Datasheet Volume 2 63 64 Processor C
340. re uses this base address to program the Host Memory Mapped register set All the bits in this register are locked in Intel TXT mode paar eo oe ema ooo MCHBAR Enable MCHBAREN 0 Disabled MCHBAR is disabled and does not claim any memory RW Uncore 1 Enabled MCHBAR memory mapped accesses are claimed and decoded appropriately This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers 2 5 12 GGC GMCH Graphics Control Register Register All the bits in this register are Intel TXT lockable B D F Type 0 0 0 PCI Address Offset 50 51h Reset Value 0028h Access RW KL RW L Size 16 bits BIOS Optimal Default 00h Reset RST Description Value PWR P pus f ro o Reseved S sofe m fema o ooo GTT Graphics Memory Size GGMS This field is used to select the amount of Main Memory that is pre allocated to support the Internal Graphics Translation Table The BIOS ensures that memory is pre allocated only when Internal graphics is enabled GSM is assumed to be a contiguous physical DRAM space with DSM and BIOS needs to allocate a contiguous memory chunk Hardware will derive the base of GSM from DSM only using the Uncore GSM size programmed in the register Hardware functionality in case of programming this value to Reserved is not ensured Encoding 1h 1 MB of pre allocated memory 2h 2 MB of pre allocated memory 3h Reserved Oh No pre allocated mem
341. read and write cycles that address the BIOS area from OC_4000h to OC_7FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT see means o 0CO000 OC3FFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OCO000h to OC3FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are 1 0 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers intel 2 5 18 PAM2 Programmable Attribute Map 2 Register This register controls the read write and shadowing attributes of the BIOS range from C_8000h to C_FFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to spe
342. register Hardware detected Device OTLB invalidation completion time out setting the ITE bit in the Fault Status register If any of the status fields in the Fault Status register was already Set at the time of setting any of these bits it is not treated as a new interrupt condition The IP bit is kept set by hardware while the interrupt message is held pending The interrupt message could be held pending due to interrupt mask IM field being Set or other transient hardware conditions The IP bit is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to e Software clearing the IM bit Software servicing all the pending interrupt status bits in the Fault Status register as follows e When primary fault logging is active software clearing the Fault F bit in all the Fault Recording registers with faults causing the PPF bit in Fault Status register to be evaluated as clear e Software clearing other status bit in the Fault Status register by writing back the value read from the respective bits 241 t i Processor Configuration Registers 2 18 10 FEDATA_REG Fault Event Data Register This register specifies the interrupt message data B D F Type 0 0 0 GFXVTBAR Address Offset 3C 3Fh Reset Value 0000_
343. rflow condition At this time a fault event is generated based on the programming of the Fault Event Control register Software writing 1 to this field clears it Hardware implementations not supporting advanced fault logging implement this bit as RsvdZ Datasheet Volume 2 239 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 34 37h Reset Value 0000_0000h Access RO ROS V RW1CS Size 32 bits BIOS Optimal Default 00000h Reset RST oe js awe ss Sie esermton Primary Pending Fault PPF This bit indicates if there are one or more pending faults logged in the fault recording registers Hardware computes this bit as the logical OR of Fault F fields across all the fault recording registers of this remapping hardware unit Powerg i 1 ROS V ood 0 No pending faults in any of the fault recording registers 1 One or more fault recording registers has pending faults The FRI field is updated by hardware when the PPF bit is set by hardware Also depending on the programming of Fault Event Control register a fault event is generated when hardware sets this field Primary Fault Overflow PFO Powerg Hardware sets this bit to indicate overflow of fault recording RW1CS ood registers Software writing 1 clears this bit When this bit is set hardware does not record any new faults until software clears this bit 240 Datasheet Volume 2 Processor Configuration Registers
344. ription Value PWR P Set Fault Log SFL This field is valid only for implementations supporting advanced fault logging Software sets this field to request hardware to set update the fault log pointer used by hardware The fault log pointer is specified through Advanced Fault Log register 29 Uncore Hardware reports the status of the Set Fault Log operation through the FLS field in the Global Status register The fault log pointer must be set before enabling advanced fault logging through EAFL field Once advanced fault logging is enabled the fault log pointer may be updated through this field while DMA remapping is active Clearing this bit has no effect The value returned on read of this field is undefined Enable Advanced Fault Logging EAFL This field is valid only for implementations supporting advanced fault logging Software writes to this field to request hardware to enable or disable advanced fault logging 0 Disable advanced fault logging In this case translation faults 28 Uncore are reported through the Fault Recording registers 1 Enable use of memory resident fault log When enabled translation faults are recorded in the memory resident log The fault log pointer must be set in hardware through the SFL field before enabling advanced fault logging Hardware reports the status of the advanced fault logging enable operation through the AFLS field in the Global Status register The value returned on a read of this fie
345. roller Channel 0 June 2011 Added four registers to Section 2 14 MCHBAR Registers in Memory Controller Channel 1 SS 10 Datasheet Volume 2 Introduction intel 1 Introduction This is Volume 2 of the Datasheet for the following products e Intel Xeon processor E3 1200 family The processor contains one or more PCI devices within a single physical component The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket This document describes these configuration space registers or device specific control and status registers CSRs only This document does NOT include Model Specific Registers MSRs Note Throughout this document the Intel Xeon processor E3 1200 family may be referred to as processor Note Throughout this document the Intel C200 Series Chipset Platform Controller Hub may also be referred to as PCH Note The term SRV refers to server platforms The term WS refers to workstation platforms Datasheet Volume 2 11 12 Introduction Datasheet Volume 2 Processor Configuration Registers 2 Processor Configuration Registers This chapter contains the following e Register terminology e PCI Devices and Functions on processor e System address map e Processor register introduction Detailed register bit descriptions 2 1 Register Terminology Table 2 1 shows the register related terminology and
346. rome Adapter MDA Range B_0000h B_ 7FFFh Legacy support requires the ability to have a second graphics controller monochrome in the system Accesses in the standard VGA range are forwarded to IGD PCI Express or the DMI Interface depending on configuration bits Since the monochrome adapter may be mapped to any of these devices the processor must decode cycles in the MDA range 000B_0000h 000B_7FFFh and forward either to IGD PCI Express or the DMI Interface This capability is controlled by the VGA steering bits and the legacy configuration bit MDAP bit In addition to the memory range BOOOOh to B7FFFh the processor decodes O cycles at 3B4h 3B5h 3B8h 3B9h 3BAh and 3BFh and forwards them to either IGD PCI Express and or the DMI Interface PEG 16 bit VGA Decode In the PCI to PCI Bridge Architecture Specification Revision 1 2 it is required that 16 bit VGA decode be a feature When 16 bit VGA decode is disabled the decode of VGA I O addresses is performed on 10 lower bits only essentially mapping also the aliases of the defined I O addresses Datasheet Volume 2 19 m t 1 Processor Configuration Registers 2 3 1 3 2 3 2 Figure 2 3 20 PAM C_0000h F_ FFFFh The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory Area Each section has Read enable and Write enable attributes The PAM registers are mapped in Device 0 configuration space e ISA Expansion Area C_0000h D_FFFF
347. rotected Low Memory Base Register eeeee eee 289 Datasheet Volume 2 2 21 16 PLMLIMIT_REG Protected Low Memory Limit Register eeeeeeees 290 2 21 17 PHMBASE_ REG Protected High Memory Base Register ccce 291 2 21 18 PHMLIMIT_REG Protected High Memory Limit Register ceeee 292 2 21 19 IQH_REG Invalidation Queue Head Register ccccceeee eect eee ee ee ena 293 2 21 20 EG Invalidation Queue Tail Register c ccc cece ence ne eee ete eee eeenaaes 293 2 21 21 IQA REG Invalidation Queue Address Register ccceeeee ene ee eee ee een n 294 2 21 22 ICS_REG Invalidation Completion Status Register ecce 294 2 21 23 IECTL_REG Invalidation Event Control Register c cece eee ee enna 295 2 21 24 EDATA_REG Invalidation Event Data Register cece eee eee 296 2 21 25 EADDR_REG Invalidation Event Address Register cceeee eee eee ees 296 2 21 26 IEUADDR_REG Invalidation Event Upper Address Register 506 297 2 21 27 IRTA_REG Interrupt Remapping Table Address Register 0 eeeee 297 2 21 28 IVA_REG Invalidate Address Register c icc eee eee eee e ee en nae 298 2 21 29 I OTLB_REG IOTLB Invalidate Register cetera e nena eae 299 Figures 2 1 System Address Range Example cccecece eee eee eee 17 2 2 DOS Legacy Address RANGEC cccc ccna ee ete 18 2 3 Main Memory Address Range
348. rs 32 KB window DMIBAR This window is used to access registers associated with the processor PCH Serial Interconnect DMI register memory range 4 KB window GGC GMS Graphics Mode Select Used to select the amount of main memory that is pre allocated to support the internal graphics device in VGA non linear and Native linear modes 0 512 MB options GGC GGMS GTT Graphics Memory Size Used to select the amount of main memory that is pre allocated to support the Internal Graphics Translation Table 0 2 MB options For each of the following four device functions Device 1 Function 0 Device 1 Function 1 Device 1 Function 2 Device 6 Function 0 MBASE MLIMIT PCI Express port non prefetchable memory access window PMBASE PMLIMIT PCI Express port prefetchable memory access window PMUBASE PMULIMIT PCI Express port upper prefetchable memory access window OBASE IOLIMIT PCI Express port I O access window Device 2 Function 0 IOBAR I O access window for internal graphics Through this window address data register pair using I O semantics the IGD and internal graphics instruction port registers can be accessed Note this allows accessing the same registers as GTTMMADR The OBAR can be used to issue writes to the GTTMMADR or the GTT table GMADR Internal graphics translation window 128 MB 256 MB 512 MB window GTTMMADR This register requests a 4 MB allocation f
349. rs This field selects a GTT offset if the target is the GTT Target TARG 00 MMIO Registers 01 GTT 1X Reserved 2 9 2 DATA MMI O Data Register A 32 bit I O write to this port is re directed to the MMIO register GTT location pointed to by the INDEX register A 32 bit 1O read to this port is re directed to the MMIO register GTT location pointed to by the INDEX register B D F Type 0 2 0 PCI 10 Address Offset 4 7h Reset Value 0000_0000h Access RW Size 32 bits Reset RST fate GUJE 31 0 RW 0000_000 FLR MMI O Data Window DATA Oh Uncore This field is the data field associated with the O2MMIO access 144 Datasheet Volume 2 Processor Configuration Registers ntel 2 10 PCI Device 6 Configuration Registers Table 2 12 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 12 PCI Device 6 Register Address Map Sheet 1 of 2 Address Register F 0 1h VID6 Vendor Identification 8086h Ro O 2 3h DD Device Identification 010Dh RO FW 4 5h PCICMD6 PCI Command 0000h RW RO 6 PCISTS6 PCI Status 0010h RWIE RO 9 7h T a e a J m ro feen O En mn I o i Dh 0 34h h Dh SUBUSN6 Subordinate Bus Number 0 0 1 1C IOBASE6 1 O Base Address 1 V Ww T h Ww WwW Ww IOLIMIT6 1 0 Limit Address oon O w 1E 1Fh SSTS6 Secondary Status 0000h RWIC RO 20 21h MBASE6 Memory Base Address FFFOh WwW WwW WwW WwW h Ww
350. rsrrrrrrrrrsssrrrrrrrrrnnne 104 Datasheet Volume 2 2 6 25 PM_CAPID1 Power Management Capabilities Register cesses 106 2 6 26 PM_CS1 Power Management Control Status Register 107 2 6 27 SS_CAPID Subsystem ID and Vendor ID Capabilities Register 108 2 6 28 SS Subsystem ID and Subsystem Vendor ID Register cseeee eee ees 109 2 6 29 MSI_CAPID Message Signaled Interrupts Capability ID Register 109 2 6 30 MC Message Control Register ccecceee cece eee eee ee eee eee eee e eee eee teen nesta 110 2 6 31 MA Message Address Register ceceee cece nee e reenter teeta eae ent eee teenie eae ees 111 2 6 32 MD Message Data Register ccc cece eee eee eee tee eee eee e teen e eat ee teeta teat tes 111 2 6 33 PEG_CAPL PCI Express G Capability List Register cceceeeeee eee ee eee 111 2 6 34 PEG_CAP PCI Express G Capabilities Register cece eee eens etree nee 112 2 6 35 DCAP Device Capabilities REGiSter cic ceceee cece e tener teen eee eee ea eee eaes 112 2 6 36 DCTL Device Control ReQiSter cccccece cee ee cette eee ee sees teens eae eeeteeneeattes 113 2 6 37 DSTS Device Status R GIStEr cece ce eee e reece nets eee e teats eae en eeataes 114 2 6 38 LCTL Link Control REGiStel ispi iiras EE enue Eai ENSKE 115 2 6 39 LSTS Link Status RegiSteF iiipienaidi sinnini inueni nni a aiai aa i 117 2 6 40 SLOTCAP Sl
351. rted than the default this field is reserved Reserved for Load VC Arbitration Table VCARB Uncore Used for software to update the VC Arbitration Table when VC arbitration uses the VC Arbitration Table As a VC Arbitration Table is never used by this component this field will never be used 184 Datasheet Volume 2 Processor Configuration Registers t 2 11 4 VCORCAP VCO Resource Capability Register B D F Type 0 6 0 MMR Address Offset 110 113h Reset Value 0000_0001h Access RO Size 32 bits BIOS Optimal Default 00h Reset RST ete js awe Ses Sie esermon 31 24 Ro oon Uncore Reserved for Port Arbitration Table Offset PATO S e ees 22 16 Ro oon unore Reserved for Maximum Time Slots MTS Reject Snoop Transactions RSNPT 0 Transactions with or without the No Snoop bit set within the 15 Uncore TLP header are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request paws oon Port Arbitration Capability PAC Indicates types of Port Arbitration supported by the VC resource This field is valid for all Switch Ports Root Ports that support peer to peer traffic and RCRBs but not for PCI Express Endpoint devices or Root Ports that do not support peer to peer traffic Each bit location within this field corresponds to a Port Arbitration Capability defined below Wh
352. ructure as being for PCI Express registers Datasheet Volume 2 111 intel 2 6 34 2 6 35 112 Processor Configuration Registers PEG CAP PCI Express G Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 1 0 2 PCI Address Offset A2 A3h Reset Value 0142h Access RO RW O Size is bits BIOS Optimal Default Reset RST Description Value PWR p Interrupt Message Number SS MN FORA Not Applicable or Implemented Hardwired to 0 Slot I mplemented SI 0 The PCI Express Link associated with this port is connected to an integrated component or is disabled RW O 1b Uncore 1 The PCI Express Link associated with this port is connected to a slot BIOS Requirement This field must be initialized appropriately if a slot connection is not implemented 7 4 4h ncore Device Port Type DPT Hardwired to 4h to indicate root port of PCI Express Root Complex PCI Express Capability Version PCI ECV 3 0 2h Uncore Hardwired to 2h to indicate compliance to the PCI Express Capabilities Register Expansion ECN DCAP Device Capabilities Register This register indicates PCI Express device capabilities B D F Type 0 1 0 2 PCI Address Offset A4 A7h Reset Value 0000_8000h Access RO RW O Size 32 bits BIOS Optimal Default 0000000h Reset RST Description Value PWR p aef e o resem Role Based Error Reporting RBER 15 1b Uncore ndicates that
353. s RO RW Size 16 bits BIOS Optimal Default 00h Reset RST Value PWR Ee B 000b Uncore Uncore Uncore Datasheet Volume 2 Description 64 bit Address Capable B64AC Hardwired to 0 to indicate that the function does not implement the upper 32 bits of the Message Address register and is incapable of generating a 64 bit memory address This may need to change in future implementations when addressable system memory exceeds the 32b 4 GB limit Multiple Message Enable MME System software programs this field to indicate the actual number of messages allocated to this device This number will be equal to or less than the number actually requested The encoding is the same as for the MMC field below Multiple Message Capable MMC System software reads this field to determine the number of messages being requested by this device Encodings for the number of messages requested are 000 1 All of the following are reserved in this implementation 001 2 010 4 011 8 100 16 101 32 110 Reserved 111 Reserved MSI Enable MSIEN Controls the ability of this device to generate MSIs 0 MSI will not be generated 1 MSI will be generated when we receive PME messages INTA will not be generated and INTA Status PCISTS1 3 will not be set 169 intel Processor Configuration Registers 2 10 31 MA Message Address Register B D F Type Address Offset Reset Value Access Size 0
354. s 2 X 8 2 18 22 1I1CS_REG Invalidation Completion Status Register This register reports the completion status of invalidation wait descriptor with the Interrupt Flag IF Set This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset 9C 9Fh Reset Value 0000_0000h Access Rwics Size 32 bits BIOS Optimal Default 0000_0000h Reset RST Description Value PWR P sui Ro f on Reserved S Invalidation Wait Descriptor Complete IWC This bit indicates completion of Invalidation Wait Descriptor with Interrupt Flag IF field Set Hardware implementations not supporting queued invalidations implement this field as RsvdZ 250 Datasheet Volume 2 Processor Configuration Registers intel 2 18 23 IECTL_REG Invalidation Event Control Register This register specifies the invalidation event interrupt control bits This register is treated as RsvdZ by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 GFXVTBAR Address Offset A0 A3h Reset Value 8000_0000h Access RW L RO V Size 32 bits BIOS Optimal Default 0000_ 0000h Reset RST A me foar E OO eon O O Interrupt Mask IM 0 No masking of interrupt When an invalidation event condition is detected hardware issues an interrupt message us
355. s Offset A4 A7h Reset Value 0000_ 8000h Access RO RW O Size 32 bits BIOS Optimal Default 0000000h Reset RST Description Value PWR P aof e o j pee o Role Based Error Reporting RBER 15 1b Uncore Indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1 1 specification me e j o O een ooo ncar Extended Tag Field Supported ETFS Hardwired to indicate support for 5 bit Tags as a Requestor Phantom Functions Supported PFS 4 3 U OEIC Not Applicable or Implemented Hardwired to 0 Max Payload Size MPS 2 0 RW O 000b Uncore Default indicates 128B maximum supported payload for Transaction Layer Packets TLP Datasheet Volume 2 171 Processor Configuration Registers intel 2 10 36 DCTL Device Control Register This register provides control for PCI Express device specific capabilities The error reporting enable bits are in reference to errors detected by this device not error messages received across the link The reporting of error messages ERR_CORR ERR_NONFATAL ERR_FATAL received by Root Port is controlled exclusively by Root Port Command Register B D F Type 0 6 0 PCI Address Offset A8 A9h Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh Reset RST Be jae o oa ena o 14 12 000b Reserved for Max Read Request Size MRRS pu 0b f Uncore Reserved for Enable No Snoop NSE Co f feee o
356. s Offset C Dh Reset Value 0000h Access RW RO Size 16 bits BIOS Optimal Default 000h Reset RST pee ew tats ih seem pase e reseed VC Arbitration Select VCAS This field will be programmed by software to the only possible value as indicated in the VC Arbitration Capability field The value 000b when written to this field will indicate the VC arbitration scheme is hardware fixed in the root complex This 3 1 RW 000b Uncore field cannot be modified when more than one VC in the LPVC group is enabled 000 Hardware fixed arbitration scheme such as Round Robin Others Reserved See the PCI express specification for more details o RO ob Uncore Reserved for Load VC Arbitration Table LVCAT 2 12 5 DMI VCORCAP DMI VCO Resource Capability Register B D F Type 0 0 0 DMIBAR Address Offset 10 13h Reset Value 0000_0001h Access RO Size 32 bits BIOS Optimal Default 00h Reset RST Description Value PWR 31 24 RO oon Uncore Reserved for Port Arbitration Table Offset PATO afoj o f fena o 22 16 Ro oon Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the 15 Uncore TLP header are allowed on this VC 1 Any transaction for which the No Snoop attribute is applicable but is not set within the TLP Header will be rejected as an Unsupported Request rams mo oe reseed Por
357. s Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCI Express memory access performance Configuration software is responsible for programming all address range registers prefetchable non prefetchable with the values that provide exclusive address ranges that is prevent overlap with each other and or with the ranges covered with the main memory There is no provision in the processor hardware
358. s a protected low memory region of size 2 N 1 bytes e Programming the protected high memory limit register with a value less than the protected high memory base register disables the protected high memory region Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 VCOPREMAP Address Offset 78 7Fh Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 000000000000h Reset RST Description Value PWR P ssf o m pema ooo Protected High Memory Limit PHML This register specifies the last host physical address of the DMA 38 20 RW 00000h Uncore protected high memory region in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width moe o E pema o 292 Datasheet Volume 2 Processor Configuration Registers intel 2 21 19 IQH_REG Invalidation Queue Head Register Register indicating the invalidation queue head This register is treated as RsvdZ by implementations reporting Queued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset 80 87h Reset Value 0000_0000_0000_0000h Access RO V Size 64 bits BIOS Optimal Default 0_0000_0000_0000h Reset RST jee ew fete ok ee n o o j ena o Queue Head QH This field specifies the offset 128 bit aligned to the invalidation 18
359. s that address the BIOS area from 0E0000h to OE3FFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are 1 0 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 Processor Configuration Registers intel 2 5 22 PAM6 Programmable Attribute Map 6 Register This register controls the read write and shadowing attributes of the BIOS range from E_8000h to E_FFFFh The Uncore allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768 KB to 1 MB address range Seven Programmable Attribute Map PAM registers are used to support these features Cacheability of these areas is controlled using the MTRR register in the core Two bits are used to specify memory attributes for each memory segment These bits apply to host accesses to the PAM areas These attributes are e RE Read Enable When RE 1 the host read accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when RE 0 the host read accesses are directed to DMI WE Write Enable When WE 1 the host write accesses to the corresponding memory segment are claimed by the Uncore and directed to main memory Conversely when WE 0 the host read acces
360. s undefined Depending on the form factor the power is turned on off either to the slot or within the adapter Note that in some cases the power Uncore controller may autonomously remove slot power or not respond to a power up request based on a detected fault condition independent of the Power Controller Control setting The defined encodings are 0 Power On 1 Power Off If the Power Controller Implemented field in the Slot Capabilities register is set to Ob then writes to this field have no effect and the read value of this field is undefined Reserved Power Indicator Control PIC If a Power Indicator is implemented writes to this field set the Power Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined 00 Reserved 01 On 10 Blink 11 Off If the Power Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Uncore 120 Datasheet Volume 2 Processor Configuration Registers ntel B D F Type 0 1 0 2 PCI Address Offset B8 B9h Reset Value 0000h Access RO Size Ce bits BIOS Optimal Default Reset RST jw awe Set Be esermon Reserved for Attention Indicator Control AIC If an Atten
361. ses are directed to DMI The RE and WE attributes permit a memory segment to be Read Only Write Only Read Write or Disabled For example if a memory segment has RE 1 and WE 0 the segment is Read Only B D F Type 0 0 0 PCI Address Offset 86h Reset Value 00h Access RW Size a w BIOS Optimal Default Reset RST Description Value PWR p mefe o pee o OECOOO OEFFFF Attribute HI ENABLE This field controls the steering of read and write cycles that address the BIOS area from OECOOOh to OEFFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM all writes are 5 4 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM all reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT sae means oo 0E8000 OEBFFF Attribute LOENABLE This field controls the steering of read and write cycles that address the BIOS area from OE8000h to OEBFFFh 00 DRAM Disabled All accesses are directed to DMI 01 Read Only All reads are sent to DRAM All writes are 1 0 RW Uncore forwarded to DMI 10 Write Only All writes are sent to DRAM All reads are serviced by DMI 11 Normal DRAM Operation All reads and writes are serviced by DRAM This register is locked by Intel TXT Datasheet Volume 2 69 70 Processor Configuration Registers LAC Legacy Access Control Re
362. slation of the memory BW to temperature The units are given in 1 power 2 44 VTS time constant VTS_TIME_CONSTANT This factor is relevant only for BW based temperature estimation 21 12 RW OC8h Uncore It is equal to 1 minus alpha The value of the time constant 1 alpha is determined by VTS_TIME_CONSTANT power 2 25 per 1 mSec a ened oo VTS offset adder VTS_ OFFSET 10 4 RW 32h Uncore The offset is intended to provide a temperature proxy offset so the option of having a fixed adder to VTS output is available a o Disable EXTTS DISABLE_EXTTS 2 RW 1b Uncore When set PCODE should ignore EXTTS indication that is obtained from the PCH and will rely on PECI or DDR BW estimations Disable Bandwidth Estimation DI SABLE_BW_ ESTI MATION When set PCODE should ignore DDR BW estimation that is 1 RW Uncore obtained from the memory controller and will rely on PECI or EXTTS Disable PECI Control DI SABLE_PECI_CONTROL RW Uncore When set PCODE should ignore DDR temperature that is given by PECI Datasheet Volume 2 261 Processor Configuration Registers ntel 2 19 2 MEM_TRML_THRESHOLDS_CONFIG Memory Thermal Thresholds Configuration Register This register describes the thresholds for the memory thermal management in the MC e The warm threshold defines when self refresh is at double rate Throttling can also be applied at this threshold based on the configuration in the MC e The hot threshold def
363. status Datasheet Volume 2 37 m t Processor Configuration Registers 2 3 13 1 1 38 DMI Interface Accesses to the Processor that Cross Device Boundaries The processor does not support transactions that cross device boundaries This should never occur because PCI Express transactions are not allowed to cross a 4 KB boundary For reads the processor will provide separate completion status for each naturally aligned 64 byte block or if chaining is enabled each 128 byte block If the starting address of a transaction hits a valid address the portion of a request that hits that target device PCI Express or DRAM will complete normally If the starting transaction address hits an invalid address the entire transaction will be remapped to address 000C_0000h and dispatched to DRAM A single unsupported request completion will result TC VC Mapping Details e VCO enabled by default Snoop port and Non snoop Asynchronous transactions are supported Internal Graphics GMADR writes can occur Unlike FSB chipsets these will NOT be snooped regardless of the snoop not required SNR bit Internal Graphics GMADR reads unsupported Peer writes can occur The SNR bit is ignored MSI can occur These will route and be sent to the cores as Intlogical IntPhysical interrupts regardless of the SNR bit VLW messages can occur These will route and be sent to the cores as VLW messages regardless of the SNR bit
364. ster provides extensions to the PCICMD register that are specific to PCI to PCl bridges The BCTRL provides additional control for the secondary interface that is PCI Express G as well as some bits that affect the overall behavior of the virtual Host PCI Express bridge embedded within the processor such as VGA compatible address ranges mapping B D F Type 0 6 0 PCI Address Offset 3E 3Fh Reset Value 0000h Access RO RW Size 16 bits BIOS Optimal Default Oh Reset RST Value PWR Description Timer SERR Enable DTSERRE Not Applicable or Implemented Hardwired to 0 Discard Timer Status DTSTS icable or Implemented Hardwired to 0 Secondary Discard Timer SDT Not Applicable or Implemented Hardwired to 0 Primary Discard Timer PDT icable or Implemented Hardwired to 0 Fast Back to Back Enable FB2BEN Not Applicable or Implemented Hardwired to 0 Secondary Bus Reset SRESET Uncore Setting this bit triggers a hot reset on the corresponding PCI Express Port This will force the TXTSSM to transition to the Hot Reset state using Recovery from LO LOs or L1 states 5 Wneore Master Abort Mode MAMODE Does not apply to PCI Express Hardwired to 0 VGA 16 bit Decode VGA16D This bit enables the PCI to PCI bridge to provide 16 bit decoding of VGA 1 0 address precluding the decoding of alias addresses every 4 RW Uncore 1 KB This bit only has meaning if bit 3 VGA Enable of this registe
365. supported by hardware Software must ensure that the value written to this field is within this limit Hardware ignores and does not implement bits 47 32 N where N is the supported domain id width reported in the Capability register Fs o eea Datasheet Volume 2 Processor Configuration Registers intel 2 18 29 FRCDL_REG Fault Recording Low Register This register records fault information when primary fault logging is active Hardware reports the number and location of fault recording registers through the Capability register This register is relevant only for primary fault logging This register is sticky and can be cleared only through power good reset or by software clearing the RWIC fields by writing a 1 B D F Type 0 0 0 GFXVTBAR Address Offset 200 207h Reset Value 0000_0000_0000_0000h Access ROS V Size 64 bits BIOS Optimal Default 0000_0000_0000_0000h Reset RST ee ORQJ Fault I nfo FI When the Fault Reason FR field indicates one of the DMA remapping fault conditions bits 63 12 of this field contain the page address in the faulted DMA request Hardware treats bits 63 N as reserved 0 where N is the maximum guest address width 63 12 Ros v 00000000 MGAW supported When the Fault Reason FR field indicates one of the interrupt remapping fault conditions bits 63 48 of this field indicate the interrupt_index computed for the faulted interrupt request and bits 47 12 are cleared
366. sure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer Clearing this bit has no effect The value returned on read of this field is undefined Set Fault Log SFL This field is valid only for implementations supporting advanced fault logging Software sets this field to request hardware to set update the fault log pointer used by hardware The fault log pointer is specified through Advanced Fault Log register 29 Uncore Hardware reports the status of the Set Fault Log operation through the FLS field in the Global Status register The fault log pointer must be set before enabling advanced fault logging through EAFL field Once advanced fault logging is enabled the fault log pointer may be updated through this field while DMA remapping is active Clearing this bit has no effect The value returned on read of this field is undefined Enable Advanced Fault Logging EAFL This field is valid only for implementations supporting advanced fault logging Software writes to this field to request hardware to enable or disable advanced fault logging 0 Disable advanced fault logging In this case translation faults 28 Uncore are reported through the Fault Recording registers 1 Enable use of memory resident fault log When enabled translation faults are recorded in the memory resident log The fault log pointer must be s
367. t then accesses to I O address range x3BCh x3BFh are forwarded to PCI Express through Device 1 Function 2 if the address is within the corresponding OBASE and OLIMIT otherwise they remain on the backbone MDA resources are defined as the following Memory OBOOOOh 0OB7FFFh 1 0 3B4h 3B5h 3B8h 3B9h 3BAh 3BFh including ISA address aliases A 15 10 are not s used in decode RN Ungcorg Any O reference that includes the I O locations listed above or their aliases will remain on the backbone even if the reference also includes I O locations not listed above The following table shows the behavior for all combinations of MDA and VGA VGAEN MDAP Description 0 All References to MDA and VGA space are not claimed by Device 1 Function 2 Illegal combination All VGA and MDA references are routed to PCI Express Graphics Attach Device 1 Function 2 All VGA references are routed to PCI Express Graphics Attach Device 1 Function 2 MDA references are not claimed by Device 1 Function 2 VGA and MDA memory cycles can only be routed across PEG12 when MAE PCICMD12 1 is set VGA and MDA I O cycles can only be routed across PEG12 if OAE PCICMD12 0 is set Datasheet Volume 2 71 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 87h Reset Value 00h Access RW Size r Tales BIOS Optimal Default Reset RST jw awe ss Site esermton PEG11 MDA Present MDAP11 This bit works with the VGA
368. t Arbitration Capability PAC 7 0 Olh Uncore Having only bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed Datasheet Volume 2 191 intel 2 12 6 192 Processor Configuration Registers DMI VCORCTL DMI VCO Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 0 B D F Type 0 0 0 DMIBAR Address Offset 14 17h Reset Value 8000_007Fh Access RO RW Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR P Virtual Channel 0 Enable VCOE 31 1b Uncore For VCO this is hardwired to 1 and read only as VCO can never be disabled saf o o p peen o Virtual Channel 0 ID VCOID 26 24 000b Uncore Assigns a VC ID to the VC resource For VCO this is hardwired to 0 and read only saj me om Reeves o Port Arbitration Select PAS Configures the VC resource to provide a particular Port Arbitration service Valid value for this field is a number corresponding to one 19 17 RW 000b Uncore of the asserted bits in the Port Arbitration Capability field of the VC resource Because only bit 0 of that field is asserted This field will always be programmed to 1 pase Re a a 7 Ro o Uncore Traffic Class m Virtual Channel 0 Map TCMVCOM Traffic Class Virtual Channel 0 Map TCVCOM Indicates the TCs Traffic Classes that are mapped to the VC resource Bit locations with
369. t for its presence B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 1 0 2 PCI 88 8Bh 0000_800Dh RO 32 bits 0000h Reset RST Description Value PWR P aoj e o pea o Pointer to Next Capability PNC This contains a pointer to the next item in the capabilities list that is the PCI Power Management capability Uncore Capability ID CID Value of ODh identifies this linked list item capability structure as being for SSID SSVID registers in a PCI to PCI Bridge Uncore Datasheet Volume 2 Processor Configuration Registers intel 2 6 28 SS Subsystem ID and Subsystem Vendor ID Register System BIOS can be used as the mechanism for loading the SSID SVID values These values must be preserved through power management transitions and a hardware reset B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI 8C 8Fh 0000_8086h RW O 32 bits Reset RST Description Value PWR P Subsystem ID SSID 31 1 RW O 0000h U 31 16 Amo 0000n uncore Identifies the particular subsystem and is assigned by the vendor 15 0 RW O Subsystem Vendor ID SSVI D Uncore Identifies the manufacturer of the subsystem and is the same as the vendor ID which is assigned by the PCI Special Interest Group 2 6 29 MSI _ CAPI D Message Signaled Interrupts Capability I D Register When a device supports MSI it can generate an interrupt request t
370. t has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob Link Bandwidth Management Interrupt Enable LBMI E When Set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Uncore Hardware Autonomous Width Disable HAWD When Set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as follows 0 Clock power management is disabled and device must hold CLKREQ signal low Uncore 1 When this bit is set to 1 the device is permitted to use CLKREQ signal to power manage link clock according to protocol defined in the appropriate form factor specification Components that do not support Clock Power Management as indicated by a Ob value in the Clock Power Management bit of the Link Capabi
371. t memory mapped space For example the range reserved for MCHBAR is outside of PCIEXBAR space On reset this register is disabled and must be enabled by writing a 1 to the enable field in this register This base address shall be assigned on a boundary consistent with the number of buses defined by the length field in this register above TOLUD and still within 39 bit addressable memory space The PCI Express Base Address cannot be less than the maximum address written to the Top of physical memory register TOLUD Software must ensure that these ranges do not overlap with known ranges located above TOLUD Software must ensure that the sum of the length of the enhanced configuration region TOLUD any other known ranges reserved above TOLUD is not greater than the 39 bit addressable limit of 512 GB In general system implementation and the number of PCI PCI Express PCI X buses supported in the hierarchy will dictate the length of the region All the bits in this register are locked in Intel TXT mode Datasheet Volume 2 Processor Configuration Registers B D F Type 0 0 0 PCI Address Offset 60 67h Reset Value 0000_0000_0000_0000h Access RW RW V Size 64 bits BIOS Optimal Default 0000_0000_0000h Reset RST Description Value PWR P rere o o pena ooo PCI Express Base Address PCIEXBAR This field corresponds to bits 38 28 of the base address for PCI Express enhanced configuration space BIOS will program th
372. t support all smaller super page sizes that is only valid values for this field are 0001b 0011b 0111b 1111b Fault recording Register offset FRO This field specifies the location to the first fault recording register relative to the register base address of this remapping hardware 33 24 020h Uncore unit If the register base address is X and the value reported in this field is Y the address for the first fault recording register is calculated as X 16 Y Datasheet Volume 2 227 Processor Configuration Registers B D F Type 0 0 0 GFXVTBAR Address Offset 8 Fh Reset Value 00CO_0000_20E6_0262h Access Size BIOS Optimal Default Reset RST js awe ss Sie esermton Isochrony I SOCH 0 Remapping hardware unit has no critical isochronous requesters in its scope 1 Remapping hardware unit has one or more critical isochronous 23 1b Uncore requesters in its scope To ensure isochronous performance software must ensure invalidation operations do not impact active DMA streams from such requesters This implies when DMA is active software performs page selective invalidations and not coarser invalidations Zero Length Read ZLR 0 Remapping hardware unit blocks and treats as fault zero length DMA read requests to write only pages 22 1b Uncore 1 Remapping hardware unit supports zero length DMA read requests to write only pages DMA remapping hardware implementations are recommended to re
373. t to 1b this bit enables software notification on a presence detect changed event Reserved for MRL Sensor Changed Enable MSCE When set to 1b this bit enables software notification on a MRL sensor changed event Reset Value of this field is Ob If the MRL Sensor Present field in the Slot Capabilities register is set to Ob this bit is permitted to be read only with a value of Ob Reserved for Power Fault Detected Enable PFDE When set to 1b this bit enables software notification on a power fault event Reset Value of this field is Ob If Power Fault detection is not supported this bit is permitted to be read only with a value of 0b Reserved for Attention Button Pressed Enable ABPE When set to 1b this bit enables software notification on an attention button pressed event Datasheet Volume 2 121 Processor Configuration Registers intel 2 6 42 SLOTSTS Slot Status Register This is for PCI Express Slot related registers Note Hot Plug is not supported on Intel Xeon processor E3 1200 family platforms B D F Type 0 1 0 2 PCI Address Offset BA BBh Reset Value 0000h Access RO RO V RW1C Size 16 bits BIOS Optimal Default 00h Reset RST nar js awe ss Sie esermton eo ee a Reserved for Data Link Layer State Changed DLLSC This bit is set when the value reported in the Data Link Layer Link Active field of the Link Status register is changed In response to a Uncore Data Li
374. tXS tRFC 10ns Setup of tXS_offset is of cycles for 10 ns Range is between 3 and 11 DCLK cycles mofe o pee o 2 13 5 PM_PDWN_config_CO Power down Configuration Register This register defines the power down CKE off operation power down mode idle timer and global per rank decision B D F Type 0 0 0 MCHBAR MCO Address Offset 40B0 40B3h Reset Value 0000_0000h Access RW L Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR p aafe o ea o Global power down GLPDN 12 RW L Uncore 1 Power down decision is global for channel 0 A separate decision is taken for each rank pare eo onsen Datasheet Volume 2 209 intel 2 13 6 B D F Type Address Offset Reset Value Access Size BIOS Optimal Default Processor Configuration Registers ECCERRLOGO_CO ECC Error Log O Register 0 0 0 MCHBAR MCO 40C8 40CBh 0000_0000h ROS V 32 bits 0000h Reset RST D ipti Value PWR escription p Error Bank ERRBANK 31 29 ROS V 000b pe This field holds the Bank Address of the read transaction that had the ECC error p Error Rank ERRRANK 28 27 ROS V MAS This field holds the Rank ID of the read transaction that had the ECC error l Powerg Error Chunk ERRCHUNK an a4 ROSY 0005 Holds the chunk number of the error stored in the register p Error Syndrome ERRSYND 23 16 ROS V 00h oa This field contains the error syndrome A value of FFh indicates
375. te that tREFI counter is incremented in DCLK cycles default is 4100 216 Datasheet Volume 2 Processor Configuration Registers 2 15 intel MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub 1 MPH Table 2 17 lists the registers arranged by address offset Register bit descriptions are in the sections following the table Table 2 17 MCHBAR Registers in Memory Controller Integrated Memory Peripheral Hub Address 2 Reset Offset Register Symbol Register Name Seiad Access 2 15 1 740C 740Fh CRDTCTL3 Credit Control 3 B124_F851h CRDTCTL3 Credit Control 3 Register This register will have the minimum Read Return Tracker credits for each of the PEG DMI GSA streams B D F Type 0 0 0 MCHBAR I MPH Address Offset 740C 740Fh Reset Value B124_F851h Access RW L Size 32 bits Default RST er je access Rite Bite Peen O O GSA VC1 Minimum Completion Credits GSAVC1 31 27 RGL teh Minimum number of credits for GSA VC1 completions GSA VCO Minimum Completion Credits GSAVCO 26 24 RAL th ee Minimum number of credits for GSA VCO completions PEG60 VCO Minimum Completion Credits PEG60VCO edil RWL nneare Minimum number of credits for PEG60 VCO completions f PEG12 VCO Minimum Completion Credits PEG12VCO 20 18 eee Minimum number of credits for PEG12 VCO completions PEG11 VCO Minimum Completion Credits PEG11VCO Minimum number of credits for PEG11 VCO completions
376. tem agent generates either DMI Interface or PCI Express bus cycles for all processor I O accesses that it does not claim Configuration Address Register CONFIG_ADDRESS and the Configuration Data Register CONFIG_DATA are used to generate PCI configuration space access The processor allows 64 KB 3 bytes to be addressed within the I O space Note that the upper 3 locations can be accessed only during I O address wrap around when address bit 16 is asserted Address bit 16 is asserted on the processor bus whenever an I O access is made to 4 bytes from address OFFFDh OFFFEh or OFFFFh Address bit 16 is also asserted when an I O access is made to 2 bytes from address OFFFFh A set of I O accesses are consumed by the internal graphics device if it is enabled The mechanisms for internal graphics I O decode and the associated control is explained later The I O accesses are forwarded normally to the DMI Interface bus unless they fall within the PCI Express I O address range as defined by the mechanisms explained below I O writes are NOT posted Memory writes to PCH or PCI Express are posted The PCI Express devices have a register that can disable the routing of I O cycles to the PCI Express device The processor responds to I O cycles initiated on PCI Express or DMI with an UR status Upstream I O cycles and configuration cycles should never occur If one does occur the transaction will complete with an UR completion status Similar to FSB proc
377. ter allows control of PCI Express link B D F Type 0 6 0 PCI Address Offset BO Bih Reset Value 0000h Access RO RW RW V Size 16 bits BIOS Optimal Default 00h Reset RST Description Value PWR p 15 12 Ro on f Reseved S Link Autonomous Bandwidth Interrupt Enable LABI E When Set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Devices that do not implement the Link Bandwidth Notification capability must hardwire this bit to Ob Link Bandwidth Management Interrupt Enable LBMIE When Set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set This bit is not applicable and is reserved for Endpoint devices PCI Express to PCI PCI X bridges and Upstream Ports of Switches Uncore Hardware Autonomous Width Disable HAWD When Set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width Devices that do not implement the ability autonomously to change Link width are permitted to hardwire this bit to Ob Enable Clock Power Management ECPM Applicable only for form factors that support a Clock Request CLKREQ mechanism this enable functions as foll
378. ter can only be cleared by a Reset 2 8 15 ROMADR Video BIOS ROM Base Address Register The IGD does not use a separate BIOS ROM therefore this register is hardwired to Os B D F Type 0 2 0 PCI Address Offset 30 33h Reset Value 0000_0000h Access RO Size 32 bits BIOS Optimal Default 000h Reset RST Description Value PWR P 31 18 ooooh Uncore ROM Base Address RBA Hardwired to Os 17 11 eee Address Mask ADMSK Hardwired to Os to indicate 256 KB address range E E na me F acura ROM BIOS Enable RBE 0 ROM not accessible 2 8 16 INTRPIN Interrupt Pin Register This register indicates which interrupt pin the device uses The Integrated Graphics Device uses INTA B D F Type 0 2 0 PCI Address Offset 3Dh Reset Value Olh Access RO Size 8 bits Reset RST EOF ORES Interrupt Pin I NTPI N 7 0 Olh Uncore oe single function device the IGD specifies INTA as its interrupt Olh INTA Datasheet Volume 2 141 Processor Configuration Registers intel 2 8 17 MI NGNT Minimum Grant Register The Integrated Graphics Device has no requirement for the settings of Latency Timers B D F Type Address Offset Reset Value Access Size 0 2 0 PCI 3Eh 00h RO 8 bits Reset RST eee joe awe ts Sie esermton Minimum Grant Value MGV zo ro oon unore The IGD does not burst as a PCI compliant master MAXLAT Maximum Latency Register 2
379. terrupt status fields in the Fault Status register as follows e When primary fault logging is active software clearing the Fault F field in all the Fault Recording registers with faults causing the PPF field in Fault Status register to be evaluated as clear Software clearing other status fields in the Fault Status register by writing back the value read from the respective fields t i Processor Configuration Registers 2 21 10 FEDATA_REG Fault Event Data Register This register specifies the interrupt message data B D F Type 0 0 0 VCOPREMAP Address Offset 3C 3Fh Reset Value 0000_0000h Access RW Size 32 bits Reset RST ree joe ace Sates fim eon O O Extended Interrupt Message Data EI MD This field is valid only for implementations supporting 32 bit 31 16 RW 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data may treat this field as RsvdZ Data value in the interrupt request 2 21 11 FEADDR_REG Fault Event Address Register Register specifying the interrupt message address B D F Type 0 0 0 VCOPREMAP Address Offset 40 43h Reset Value 0000_0000h Access Size BIOS Optimal Default Reset RST COLIER Message Address MA When fault events are enabled the contents of this register 1 2 RW 0000_0000h U z ae specify the DWORD aligned address bits 31 2 for the interrupt request ofe o eena o 2 21 12 FEU
380. ths SAGAW This 5 bit field indicates the supported adjusted guest address widths which in turn represents the levels of page table walks for the 4 KB base page size supported by the hardware implementation A value of 1 in any of these bits indicates the corresponding adjusted guest address width is supported The adjusted guest address widths corresponding to various bit positions within this 12 8 00010b Uncore field are Oh 30 bit AGAW 2 level page table 1h 39 bit AGAW 3 level page table 2h 48 bit AGAW 4 level page table 3h 57 bit AGAW 5 level page table 4h 64 bit AGAW 6 level page table Software must ensure that the adjusted guest address width used to setup the page tables is one of the supported guest address widths reported in this field 272 Datasheet Volume 2 Processor Configuration Registers intel B D F Type 0 0 0 VCOPREMAP Address Offset 8 Fh Reset Value 00C9_0080_2066_0262h Access RO Size 64 bits BIOS Optimal Default 000h Reset RST ae js fae a Bite serton Caching Mode CM 0 Not present and erroneous entries are Not cached in any of the remapping caches Invalidations are not required for modifications to individual not present or invalid entries However any modifications that result in decreasing the effective permissions or partial permission increases require invalidations for them to be effective Not present and erroneous mappings may be ca
381. tion Indicator is implemented writes to this field set the Attention Indicator to the written state Reads of this field must reflect the value from the latest write even if the corresponding hot plug command is not complete unless software issues a write without waiting for the previous command to complete in which case the read value is undefined If the indicator is electrically controlled by chassis the indicator is controlled directly by the 7 6 Uncore downstream port through implementation specific mechanisms 00 Reserved 01 On 10 Blink 11 Off If the Attention Indicator Present bit in the Slot Capabilities register is Ob this field is permitted to be read only with a value of 00b Reserved for Hot plug Interrupt Enable HPIE When set to 1 this bit enables generation of an interrupt on enabled hot plug events If the Hot Plug Capable field in the Slot Capabilities register is set to 0 this bit is permitted to be read only with a value of 0 Reserved for Command Completed I nterrupt Enable CCI If Command Completed notification is supported as indicated by No Command Completed Support field of Slot Capabilities Register when set to 1b this bit enables software notification when a hot plug command is completed by the Hot Plug Controller Reset Value of this field is 0 If Command Completed notification is not supported this bit must be hardwired to 0 Presence Detect Changed Enable PDCE When se
382. tion Pending fields for that Virtual Channel are cleared in both Components on a Link oe neon 2 12 8 DMI VC1RCAP DMI VC1 Resource Capability Register B D F Type 0 0 0 DMI BAR Address Offset 1C 1Fh Reset Value 0000_8001h Access RO Size 32 bits BIOS Optimal Default 00h neser RST Description Value PWR P 31 24 RO oon Uncore Reserved for Port Arbitration Table Offset PATO a fof o pema ooo 22 16 Ro ooh Uncore Reserved for Maximum Time Slots MTS Reject Snoop Transactions REJ SNPT 0 Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC 15 th ngore 1 When set any transaction for which the No Snoop attribute is applicable but is not Set within the TLP Header will be rejected as an Unsupported Request mje o een Port Arbitration Capability PAC 7 0 Olh Uncore Having only bit 0 set indicates that the only supported arbitration scheme for this VC is non configurable hardware fixed Datasheet Volume 2 193 intel 2 12 9 194 Processor Configuration Registers DMI VC1RCTL DMI VC1 Resource Control Register This register controls the resources associated with PCI Express Virtual Channel 1 B D F Type 0 0 0 DMIBAR Address Offset 20 23h Reset Value 0100_0000h Access RO RW Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR P Virtual Channel 1 Enable VC1E 0 Disabled 1 Enabled See
383. tling can also be applied at this threshold based on the configuration in the MC 262 Datasheet Volume 2 Processor Configuration Registers intel 2 19 3 MEM_TRML_STATUS_REPORT Memory Thermal Status Report Register This register reports the thermal status of DRAM B D F Type 0 0 0 MCHBAR PCU Address Offset 58A0 58A3h Reset Value 0000_0000h Access RO V Size 32 bits BIOS Optimal Default 00h Reset RST Description Value PWR k aafe o j pee o Double Self refresh DSR 24 RO V Uncore 0 Normal self refresh 1 Double self refresh passe wow om eee o Channel 1 Status CHANNEL1_ STATUS The format is for each channel is defined as follows 00b Cold 01b Warm 15 8 RO V 00h Uncore 11b Hot Bits 8 9 Rank 0 Channel 1 Bits 10 11 Rank 1 Channel 1 Bits 12 13 Rank 2 Channel 1 Bits 14 15 Rank 3 Channel 1 Channel 0 Status CHANNELO_STATUS The format is for each channel is defined as follows 00b Cold 01b Warm 7 0 RO V 00h Uncore 11b Hot Bits 0 1 Rank 0 Channel 0 Bits 2 3 Rank 1 Channel 0 Bits 4 5 Rank 2 Channel 0 Bits 6 7 Rank 3 Channel 0 Datasheet Volume 2 263 intel 2 19 4 2 19 5 264 Processor Configuration Registers MEM_TRML_TEMPERATURE_REPORT Memory Thermal Temperature Report Register This register is used to report the estimated thermal status of the memory The Channel VTS estimated maximum temperature field is used to report the estimated
384. to 0 Master Data Parity Error SMDPE When set indicates that the processor received across the link RW1C Uncore upstream a Read Data Completion Poisoned TLP EP 1 This bit can only be set when the Parity Error Enable bit in the Bridge Control register is set h core Fast Back to Back FB2B Not Applicable or Implemented Hardwired to 0 e oe o eena o Wincore 66 60 MHz capability CAP66 Not Applicable or Implemented Hardwired to 0 OO o i ee o Datasheet Volume 2 155 m t 1 Processor Configuration Registers 2 10 15 MBASE6 Memory Base Address Register This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be 0 Thus the bottom of the defined memory address range will be aligned to a 1 MB boundary B D F Type 0 6 0 PCI Address Offset 20 21h Reset Value FFFOh Access RW Size 16 bits BIOS Optimal Default Oh Reset RST rane fone ver See Be mesenmton O Memory Address Base MBASE 15 4 RW FFFh Uncore This field corresponds to A 31 20 of the lo
385. to 0 to indicate that special initialization of this device is NOT required before generic class device driver is to use it 20 neor Auxiliary Power Source APS Hardwired to 0 PME Clock PMECLK 19 Uncore Hardwired to 0 to indicate this device does NOT support PME generation PCI PM CAP Version PCI PMCV 18 16 011b Uncore Version A value of 011b indicates that this function complies with revision 1 2 of the PCI Power Management Interface Specification Pointer to Next Capability PNC This contains a pointer to the next item in the capabilities list If j 5 MSICH CAPL 0 7Fh is 0 then the next item in the capabilities 15 8 RO V 90h U NEON list is the Message Signaled Interrupts MSI capability at 90h If MSICH CAPL 0 7Fh is 1 then the next item in the capabilities list is the PCI Express capability at AOh Capability ID CID 7 0 Olh Uncore Value of O1h identifies this linked list item capability structure as being for PCI Power Management registers 106 Datasheet Volume 2 Processor Configuration Registers intel 2 6 26 PM_CS1 Power Management Control Status Register B D F Type 0 1 0 2 Address Offset 84 87h PCI Reset Value 0000_0008h Access RO RW Size 32 bits BIOS Optimal Default 000000h Reset RST Value PWR H i Datasheet Volume 2 Bie Oee O PME Status PMESTS This bit indicates that this device does not support PME generation from D3cold Data Sc
386. treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in the Capability register The alignment of the protected low memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1s to this register and finding the most significant zero bit position with 0 in the value read back from the register Bits N 0 of this register is decoded by hardware as all Os Software must setup the protected low memory region below 4 GB Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 68 6Bh Reset Value 0000_0000h Access RW Size 32 bits BIOS Optimal Default 00000h Reset RST Description Value PWR P Protected Low Memory Base PLMB 31 20 RW 000h Uncore This register specifies the base of protected low memory region in system memory Datasheet Volume 2 245 m t 1 Processor Configuration Registers 2 18 16 PLMLIMIT_REG Protected Low Memory Limit Register This register sets up the limit address of DMA protected low memory region below 4 GB This register must be set up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected low memory region PLMR field reported as Clear in th
387. ts PEG to DMI peer write accesses are NOT supported MSI can occur These will route to the cores IntLogical IntPhysical regardless of the SNR bit e VCI is not supported e VCm is not supported Datasheet Volume 2 Processor Configuration Registers C t Figure 2 8 PEG Upstream VCO Memory Map Upstream Initiated VCO Cycle Memory Map 2TB 64GB gt TOM total physical DRAM REMAPLIMIT REMAPBASE 4GB gt FEE0_0000 FEEF_FFFF MSI TOLUD TOLUD Gfx Stolen Gfx GTT stolen TSEG_BASE gt se TSEG_BASE DPR gt A0000 BFFFF VGA mem writes gt peer write if matching PEG range else invalid mem reads gt Invalid transaction mem writes gt Route based on SNR bit mem reads gt Route based on SNR bit mem writes gt CPU IntLogical IntPhysical mem reads gt Invalid transaction mem writes gt non snoop mem write mem reads gt invalid transaction mem writes gt invalid transaction mem reads gt Invalid transaction 2 3 13 3 Legacy VGA and I O Range Decode Rules The legacy 128 KB VGA memory range 000A_0000h 000B_FFFFh can be mapped to IGD Device 2 PCI Express Device 1 functions or Device 6 and or to the DMI Interface depending on the programming of the VGA steering bits Priority for VGA mapping is constant in that the processor always decodes internally mapped devices first Internal to the processor decode preceden
388. ued Invalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A8 ABh Reset Value 0000_ 0000h Access RW L Size Aa bits BIOS Optimal Default neser RST Description Value PWR P Message address MA 31 2 RW L 00000000h Uncore When fault events are enabled the contents of this register specify the DWORD aligned address bits 31 2 for the interrupt request oje o i eena o 296 Datasheet Volume 2 Processor Configuration Registers intel 2 21 26 EUADDR_REG Invalidation Event Upper Address Register This register specifies the Invalidation Event interrupt message upper address B D F Type 0 0 0 VCOPREMAP Address Offset AC AFh Reset Value 0000_0000h Access RW L Size 32 bits Reset RST aie GRUEN Message Upper Address MUA 0000 000 Hardware implementations supporting Queued Invalidations and 31 0 RW L OR Uncore Extended Interrupt Mode are required to implement this register Hardware implementations not supporting Queued Invalidations or Extended Interrupt Mode may treat this field as RsvdZ 2 21 27 IRTA_REG Interrupt Remapping Table Address Register This register provides the base address of Interrupt remapping table This register is treated as RsvdZ by implementations reporting Interrupt Remapping IR as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset B8 BFh
389. uld use the previous decode until the new decode can guarantee PV No flushing of cycles is required On a clock by clock basis proper decode with the previous or new decode needs to be ensured All upstream cycles from 0 to TSEG_BASE 1 DPR size and not in the legacy holes VGA are decoded to DRAM Because Bus Master cycles can occur when the DPR size is changed the DPR size needs to be treated dynamically Pre allocated Memory Voids of physical addresses that are not accessible as general system memory and reside within system memory address range lt TOLUD are created for SMM mode legacy VGA graphics compatibility and GFX GTT stolen memory It is the responsibility of BI OS to properly initialize these regions Datasheet Volume 2 Processor Configuration Registers n t 2 3 2 6 2 3 2 6 1 2 3 2 7 2 3 3 GFX Stolen Spaces GTT Stolen Space GSM GSM is allocated to store the GFX translation table entries GSM always exists regardless of VT d as long as internal GFX is enabled This space is allocated to store accesses as page table entries are getting updated through virtual GTTMMADR range Hardware is responsible to map PTEs into this physical space Direct accesses to GSM are not allowed only hardware translations and fetches can be directed to GSM ME UMA ME the iAMT Manageability Engine can be allocated UMA memory ME memory is stolen from the top of the Host address map The ME stolen
390. up before enabling protected memory through PMEN_REG and must not be updated when protected memory regions are enabled This register is always treated as RO for implementations not supporting protected high memory region PHMR field reported as Clear in the Capability register The alignment of the protected high memory region base depends on the number of reserved bits N 0 of this register Software may determine N by writing all 1 s to this register and finding most significant zero bit position below host address width HAW in the value read back from the register Bits N 0 of this register are decoded by hardware as all Os Software may setup the protected high memory region either above or below 4 GB Software must not modify this register when protected memory regions are enabled PRS field Set in PMEN_REG B D F Type 0 0 0 GFXVTBAR Address Offset 70 77h Reset Value 0000_0000_0000_0000h Access RW Size 64 bits BIOS Optimal Default 0000_0000_0000h Reset RST Description Value PWR P ssf o o j pee o Protected High Memory Base PHMB This register specifies the base of protected high memory region 38 20 RW 00000h Uncore in system memory Hardware ignores and does not implement bits 63 HAW where HAW is the host address width pase wooed o Datasheet Volume 2 247 m t 1 Processor Configuration Registers 2 18 18 PHMLIMIT_REG Protected High Memory Limit Register This register sets up
391. us system errors Since the Host Bridge does not have an SERRB signal SERR messages are passed from the processor to the PCH over DMI When a bit in this register is set a SERR message will be generated on DMI whenever the corresponding flag is set in the ERRSTS register The actual generation of the SERR message is globally enabled for Device 0 using the PCI Command register B D F Type 0 0 0 PCI Address Offset CA CBh Reset Value 0000h Access RW Size 16 bits BIOS Optimal Default 0000h Reset RST Description Value PWR P SERR Multiple Bit DRAM ECC Error DMERR 1 The Host Bridge generates an SERR message over DMI when it detects a multiple bit error reported by the DRAM controller 0 Reporting of this condition using SERR messaging is disabled For systems not supporting ECC this bit must be disabled SERR on Single bit ECC Error DSERR 1 The Host Bridge generates an SERR special cycle over DMI when the DRAM controller detects a single bit error 0 Reporting of this condition using SERR messaging is disabled For systems that do not support ECC this bit must be disabled Uncore Uncore 2 5 34 SMI Command Register This register enables various errors to generate an SMI DMI special cycle When an error flag is set in the ERRSTS register it can generate an SERR SMI or SCI DMI special cycle when enabled in the ERRCMD SMICMD or SCICMD registers respectively Note that one and only one message ty
392. validate the interrupt entry cache This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer and not any stale cached entries While interrupt remapping is active software may update the interrupt remapping table pointer through this field However to ensure valid in flight interrupt requests are deterministically remapped software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer Clearing this bit has no effect The value returned on a read of this field is undefined Compatibility Format I nterrupt CFI This field is valid only for Intel 64 implementations supporting interrupt remapping Software writes to this field to enable or disable Compatibility Format interrupts on Intel 64 platforms The value in this field is effective only when interrupt remapping is enabled and Extended Interrupt Mode x2APIC mode is not enabled 0 Block Compatibility format interrupts 1 Process Compatibility format interrupts as pass through bypass interrupt remapping Hardware reports the status of updating this field through the CFIS field in the Global Status register The value returned on a read of this field is undefined Datasheet Volume 2 Processor Configuration Registers 2 18 5 GSTS_REG
393. vice Datasheet Volume 2 127 2 7 3 128 Processor Configuration Registers PVCCAP2 Port VC Capability Register 2 This register describes the configuration of PCI Express Virtual Channels associated with this port B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 1 0 2 MMR 108 10Bh 0000_ 0000h RO 32 bits 0000h Reset RST Description Value PWR P VC Arbitration Table Offset VCATO Indicates the location of the VC Arbitration Table This field 31 24 Oh contains the zero based offset of the table in DQWORDS 16 bytes i Uncore from the base address of the Virtual Channel Capability Structure A value of 0 indicates that the table is not present due to fixed VC priority rae no om Renee ooo zo ro ooh Uncore Reserved for VC Arbitration Capability VCAC PVCCTL Port VC Control Register B D F Type Address Offset Reset Value Access Size BIOS Optimal Default 0 1 0 2 MMR 10C 10Dh 0000h RW RO 16 bits 000h Reset RST Description Value PWR P mafe o O ea VC Arbitration Select VCAS This field will be programmed by software to the only possible 3 1 RW 000 U b aei value as indicated in the VC Arbitration Capability field Since there is no other VC supported than the default this field is reserved Reserved for Load VC Arbitration Table VCARB Uncore Used for software to update the VC Arbitration Table when VC ar
394. ware conditions The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced This could be due to either e Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field Software servicing the WC field in the Invalidation Completion Status register moje o ee Datasheet Volume 2 295 Processor Configuration Registers intel 2 21 24 EDATA_REG I nvalidation Event Data Register This register specifies the Invalidation Event interrupt message data This register is treated as RsvdZ by implementations reporting Queued I nvalidation QI as not supported in the Extended Capability register B D F Type 0 0 0 VCOPREMAP Address Offset A4 A7h Reset Value 0000_ 0000h Access RW L Size 32 bits Reset RST Description Value PWR P Extended Interrupt Message Data EI MD This field is valid only for implementations supporting 32 bit 31 16 RW L 0000h Uncore interrupt data fields Hardware implementations supporting only 16 bit interrupt data treat this field as Rsvd 15 0 Rw L Gee Uncore nterrupt Message data IMD Data value in the interrupt request 2 21 25 IEADDR_REG Invalidation Event Address Register This register specifies the Invalidation Event Interrupt message address This register is treated as RsvdZ by implementations reporting Que
395. ware to assign an MSI address to the device 1 2 RW U 2 oh a The device handles an MSI by writing the padded contents of the MD register to this address Force DWord Align FDWA 1 0 Uncore Hardwired to 0 so that addresses assigned by system software are always aligned on a dword address boundary MD Message Data Register B D F Type 0 1 0 2 PCI Address Offset 98 99h Reset Value 0000h Access RW Size 16 bits Reset RST Description Value PWR P Message Data MD Base message data pattern assigned by system software and used to handle an MSI from the device 15 0 RW 0000h Uncore When the device must generate an interrupt request it writes a 32 bit value to the memory address specified in the MA register The upper 16 bits are always set to 0 The lower 16 bits are supplied by this register PEG_CAPL PCI Express G Capability List Register Enumerates the PCI Express capability structure B D F Type 0 1 0 2 PCI Address Offset A0 A1h Reset Value Access Size Reset RST Description Value PWR Pointer to Next Capability PNC This value terminates the capabilities list The Virtual Channel 15 8 00h Uncore capability and any other PCI Express specific capabilities that are reported using this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space Capability ID CID 7 0 10h Uncore Identifies this linked list item capability st
396. ways 0 B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5000 5003h Reset Value 0000_0024h Access RW L Size 32 bits BIOS Optimal Default 0000000h Reset RST D ane Value PWR escription Ee ee O e w e ee Channel B assignment CH_B CH_B defines the mid size channel Uncore 00 Channe 01 Channe 10 Channe Channel A assignment CH_A CH_A defines the largest channel Uncore 00 Channe 01 Channe 10 Channe Datasheet Volume 2 Processor Configuration Registers intel 2 16 2 MAD_DIMM_ch0O Address Decode Channel 0 Register This register defines channel characteristics number of DIMMs number of ranks size ECC interleave options and ECC options B D F Type 0 0 0 MCHBAR_MCMAIN Address Offset 5004 5007h Reset Value 0060_0000h Access RW L Size 32 bits BIOS Optimal Default 00h neser RST Description Value PWR P ECC is active in the channel ECC 00 No ECC active in the channel 25 24 01 ECC is active in I O ECC logic is not active In this case on write accesses the data driven on ECC byte is copied from DQ 7 0 to be used in training or IOSAV 10 ECC is disabled in 1 0 but ECC logic is enabled to be used in ECC4ANA mode 11 ECC active in both I O and ECC logic O pema ooo Enhanced Interleave mode Enh_Interleave off On Uncore Rank Interleave RI off On DI MM B DDR Width DBW DIMM B width of DDR chips 0 X8 chips 1 X16 chips
397. wer limit of the memory range that will be passed to PCI Express G ofe o eea 156 Datasheet Volume 2 Processor Configuration Registers E t 2 10 16 MLIMIT6 Memory Limit Address Register Note Note This register controls the processor to PCI Express G non prefetchable memory access routing based on the following formula MEMORY_BASE lt address lt MEMORY_LIMIT The upper 12 bits of the register are read write and correspond to the upper 12 address bits A 31 20 of the 32 bit address The bottom 4 bits of this register are read only and return zeroes when read This register must be initialized by the configuration software For the purpose of address decode address bits A 19 0 are assumed to be FFFFFh Thus the top of the defined memory address range will be at the top of a 1 MB aligned memory block Memory range covered by MBASE and MLIMIT registers are used to map non prefetchable PCI Express G address ranges typically where control status memory mapped I O data structures of the graphics controller will reside and PMBASE and PMLIMIT are used to map prefetchable address ranges typically graphics local memory This segregation allows application of USWC space attribute to be performed in a true plug and play manner to the prefetchable address range for improved processor PCIl Express memory access performance Configuration software is responsible for programming all address range registers prefetchabl
398. when read This bit is cleared automatically no need to write a 0 Link Disable LD 0 Normal operation 1 Link is disabled Forces the TXTSSM to transition to the RW Uncore Disabled state using Recovery from LO LOs or L1 states Link retraining happens automatically on 0 to 1 transition just like when coming out of reset Writes to this bit are immediately reflected in the value read from the bit regardless of actual Link state lincore Read Completion Boundary RCB Hardwired to 0 to indicate 64 byte ea nese Active State PM ASPM This field controls the level of ASPM Active State Power Management supported on the given PCI Express Link 1 0 RW Uncore 00 Disabled 01 LOs Entry Supported 10 Reserved 11 LOs and L1 Entry Supported Datasheet Volume 2 Processor Configuration Registers 2 6 39 LSTS Link Status Register This register indicates PCI Express link status B D F Type 0 1 0 2 PCI Address Offset B2 B3h Reset Value 1001h Access RO V RW1C RO Size a bits BIOS Optimal Default Reset RST Description Value PWR P 7 BE i eej e e em fe e ee Link Autonomous Bandwidth Status LABWS This bit is set to 1 by hardware to indicate that hardware has autonomously changed link speed or width without the port transitioning through DL_Down status for reasons other than to attempt to correct unreliable link operation This bit must be set if the Physi
399. y depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor Intel Active Management Technology Intel AMT requires the computer system to have an Intel AMT enabled chipset network hardware and software as well as connection with a power source and a corporate network connection Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality It may also require modifications of implementation of new business processes With regard to notebooks Intel AMT may not be available or certain capabilities may be limited over a host OS based VPN or when connecting wirelessly on battery power sleeping hibernating or powered off For more information see http www intel com technology platform technology intel amt Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Copies of documents which have an order number and are referenced in this document or other Intel literatu
400. y the configuration software between the memory ranges that must be defined as UC and the ones that can be designated as a USWC that is prefetchable from the processor perspective B D F Type 0 1 0 2 PCI Address Offset 2C 2Fh Reset Value 0000_0000h Access RW Size 32 bits Prefetchable Memory Address Limit PMLI MI TU 0000_0000h Uncore This field corresponds to A 63 32 of the upper limit of the prefetchable Memory range that will be passed to PCI Express G RST 2 6 21 CAPPTR1 Capabilities Pointer Register The capabilities pointer provides the address offset to the location of the first entry in this device s linked list of capabilities B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI 34h 88h RO 8 bits First Capability CAPPTR1 Uncore The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability Reset RST Description Value PWR p 102 Datasheet Volume 2 Processor Configuration Registers intel 2 6 22 INTRLI NE1 I nterrupt Line Register This register contains interrupt line routing information The device itself does not use this value rather it is used by device drivers and operating systems to determine priority and vector information B D F Type Address Offset Reset Value Access Size 0 1 0 2 PCI 3Ch 00h RW 8 bits Reset RST Description Value PWR P Interrupt Connection
401. ype 0 6 0 PCI Address Offset 1E 1Fh Reset Value 0000h Access RWI1C RO Size 16 bits BIOS Optimal Default 00h Reset RST a GCEIST Detected Parity Error DPE This bit is set by the Secondary Side for a Type 1 Configuration 15 Uncore Space header device when it receives a Poisoned TLP regardless of the state of the Parity Error Response Enable bit in the Bridge Control Register Received System Error RSE 14 Uncore This bit is set when the Secondary Side for a Type 1 configuration space header device receives an ERR_FATAL or ERR_NONFATAL Received Master Abort RMA This bit is set when the Secondary Side for Type 1 Configuration 13 Uncore Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Unsupported Request Completion Status Received Target Abort RTA This bit is set when the Secondary Side for Type 1 Configuration Uncore Space Header Device for requests initiated by the Type 1 Header Device itself receives a Completion with Completer Abort Completion Status Signaled Target Abort STA Not Applicable or Implemented Hardwired to 0 The processor ncore does not generate Target Aborts The root port will never complete a request using the Completer Abort Completion status UR detected inside the processor such as in iMPH MC will be reported in primary side status i DEVSELB Timing DEVT aos ro oop uncore Not Applicable or Implemented Hardwired

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