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Intel S5500HCV

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1. ABCDE F G H J K IT Jmm o0 0009 99 L O 4 Po S DO N aa d 8 3 Wu Wl au ah 3 T o PP OI OO E ss E Q NN d gei MM F Oo LL H d ICH10R KK H JJ F Il HH d CCF el e o FF ei E EE SPE DD NI IOH fri is mi Le BB S S r HESS AA Sisi Ei ea tu feli e A BO S al I8 RH S 12 Do DIR B o CPU 2 Socket O pal SE EHI P l o WJU X V T S R Q Callout Description Callout Description A Slot 1 32 bit 33 MHz PCI Keying for 5V and w System Fan 2 Header 6 pin Universal B Intel RMM3 Slot X System Fan 1 Header 6 pin C Slot 2 PCI Express x4 x8 Mechanically Y Main Power Connector D Low profile USB Solid State Drive Header Z LCP IPMB Header E Slot 3 PCI Express Gen2 x8 AA Type A USB Port F Slot 4 PCI Express Gen2 x8 BB SATA SGPIO Header Slot 5 PCI Express Gen2 x8 Empty on Intel G Server Board S5500HCV Sic SATA POO H S5520HC Slot 6 PCI Express Gen2 x8 x16 DD SATA Port 1 6 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Overview Callout Description Callout Description Mechanically S5500HCV Slot 6 PCI Express Gen2 x4 x16 Mechanically I Batt
2. CPU 2 Fan Fault LED Figure 55 Fan Fault LED s Location Revision 1 8 123 Intel order number E39529 013 Intel Light Guided Diagnostics Intel Server Boards 5520HC S5500HCV and 5520HCT TPS 8 3 System ID LED and System Status LED The server boards provide LEDs for both system ID and system status These LEDs are located in the rear I O area of the server board as shown in the following figure SUE lo CPU 1 Socket LILILILILIL O 9 CPU 2 Socket a E E S E S Ki Figure 56 System Status LED Location A System ID LED B System Status LED You can illuminate the blue System ID LED using either of the following two mechanisms e By pressing the System ID Button on the system front control panel the ID LED displays a solid blue color until the button is pressed again 124 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S
3. Pause 85AT DIMM A2UncomedableECCemorencounered Pass 85A2 DIM BiUncomedableECCemorencounered Pass 5A3 DIMM_B2 Uncorrectable ECC error encountered James 85M4 DIMM C1 Uncorrectable ECG error encountered Pass 85A5 DIMM C2 Uncorrectable ECG error encountered Pass 85A6 DIMM_D1 Uncorrectable ECG error encountered Pass 85A7 DIMM D2 Uncorrectabie ECC error encountered Paus 85A8 DIMM EiUncomedableECCemorencounered Pass eeng DIMM E2UncomectableECCemorencounered Pause aen DIMIM_F1 Uncorrectable EGC error encountered Pase SSCS 85A8 DIMM F2 Uncorrectabie ECC error encountered Pass 9000 Unspecified processor component has encountered a non specific error Pause 9268 Local Console component encountered an output error No Pause 9288 Remote Console component encountered an output error No Pause Revision 1 8 167 Intel order number E39529 013 Appendix E POST Error Messages and Handling Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS eu Setalpotcompanenwasnolddeded Pase 8249 Serial port component encountered a resource conficteror Jee LPC component encountered a resource conflict error 95A6 PCI component encountered a controller error No Pause Unspecified software component encountered a start error No Pause 0 A022 Processor component encountered a mismatch eror Jas
4. CPU2Socket CO i DIMM Fault LEDs Fl F2 El E2 D1 D2 D2 E2 and F2 DIMM slot and Fault LED s are empty in Intel Server Board SSSOOHCV Figure 57 DIMM Fault LED s Location 126 Revision 1 8 Intel order number E39529 013 Intel Server Boards SS520HC S5500HCV and 5520HCT TPS Intel Light Guided Diagnostics 8 Post Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server boards in the rear I O area of the server boards by the serial A connector During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the given POST code to the POST code diagnostic LED s on the back edge of the server boards To assist in troubleshooting a system hang during the POST process you can use the diagnostic LEDs to identify the last POST process executed See Appendix E for a complete description of how these LEDs are read and a list of all supported POST codes 60660 A Diagnostic LED 7 MSB LED E Diagnostic LED 3 B Diagnostic LED 6 F Diagnostic LED 2 C Diagnostic LED 5 G Diagnostic LED 1 D Diagnostic LED 4 H Diagnostic LED 0 LSB LED Figure 58 POST Code Diagnostic LED Locations Revision 1 8 127 Intel order number E39529 013 Design and Environ
5. Enable 1 2 or All cores of installed processors packages Execute Disable Bit can help prevent certain classes of malicious buffer overflow attacks Contact your OS vendor regarding OS support of this feature Intel Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions Note A change to this option requires the system to be powered off and then back on before the setting takes effect Intel order number E39529 013 Information only Current speed that the QPI Link is using Information only Current frequency that the QPI Link is using This option is only visible if all processors in the system support Intel Turbo Boost Technology Revision 1 8 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Setup Item Enabled Help Text Intel Virtualization Enable Disable Intel Virtualization Technology for Directed Disabled Technology for Directed I O y o Report the I O device assignment to VMM through DMAR ACPI Tables Enable Disable Intel VT d Interrupt Remapping support Enabled Disabled Interrupt Remapping Enable Disable Intel VT d Coherency support Enabled Disabled Coherency Support Enable Disable Intel VT d Address Translation Services ATS support ATS Support Enabled Disabled Enabled Disabled Enable Disable Intel VT d Pass through DMA support Pass through Support Enabled
6. e CE EMC Directive 89 336 EEC Europe e AS NZS 3548 Emissions Australia New Zealand e VCCI Emissions Japan Revision 1 8 137 Intel order number E39529 013 Regulatory and Certification Information Intel Server Boards 5520HC 5500HCV and S5520HCT TPS e BSMI CN 13438 Emissions Taiwan e RRL Notice No 1997 41 EMC amp 1997 42 EMI Korea e GOST R 29216 91 Emissions Russia Listed on System License e GOST R 50628 95 Immunity Russia Listed on System License e Belarus License Belarus Listed on System License Certifications Registrations Declarations e UL Certification or NRTL US Canada e CB Certifications International e CE Declaration of Conformity CENELEC Europe e FCC ICES 003 Class A Attestation USA Canada e C Tick Declaration of Conformity Australia e MED Declaration of Conformity New Zealand e BSMI Certification Taiwan e RRL KCC Certification Korea e Ecology Declaration International 10 2 Product Regulatory Compliance Markings Regulatory Compliance Country Marking UL Mark USA Canada VAY C US CE Mark Europe C EMC Marking Class A Canada CANADA ICES 003 CLASS A CANADA NMB 003 CLASSE A BSMI Marking Class A Taiwan EH iB ARARV A aA ne TEER IS WREST COBTEISAU GERE REE RRA SE UU TRE C tick Marking Australia New Zealand RRL KCC Mark Korea d esse EFUP Mark China 6m Country of Origin Exporting Requirements
7. 43 1 Memory Open and Closed Loop Thermal Throttling Open Loop Thermal Throttling OLTT Throttling is a solution to cool the DIMMs by reducing memory traffic allowed on the memory bus which reduces power consumption and thermal output With OLTT the system throttles in response to memory bandwidth demands instead of actual memory temperature Since there is no direct temperature feedback from the DDR3 DIMMs the throttling behavior is preset rather than conservatively based on the worst cooling conditions for example high inlet temperature and low fan speeds Additionally the fans that provide cooling to the memory region are also Set to conservative settings for example higher minimal fan speed OLTT produces a slightly louder system than CLTT because minimal fan speeds must be set high enough to support any DDR3 DIMMs in the worst memory cooling conditions Closed Loop Thermal Throttling CLTT CLTT works by throttling the DDR3 DIMMs response directly to memory temperature via thermal sensors integrated on the Serial Presence Detect SPD of the DDR3 DIMMs This is the preferred throttling method because this approach lowers limitations on both memory power and thermal threshold therefore minimizing throttling impact on memory performance This reduces the utilization of high fan speeds because CLTT does not have to accommodate for the worst memory cooling conditions with a higher thermal threshold CLTT enables memory performance to ac
8. Revision 1 8 35 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC 5500HCV and S5520HCT TPS 14 15 16 17 18 The minimal population upgrade recommended for enabling CPU 2 socket are DIMM A1 and DIMM D1 This configuration supports only the Independent Channel mode In the Mirrored Channel mode memory population on Channels A and B should be identical including across adjacent slots on the channels memory population on Channels D and E should be identical including across adjacent slots on the channels The DIMMs on successive slots are not required to be identical and can have different sizes and or timings but the overall channel timing reduces according to the slowest DIMM If Channels A and B are not identical or Channels D and E are not identical the BIOS selects default Independent Channel Mode If Channel C or F is not empty the BIOS disables the Mirrored Channel Mode When only CPU1 socket is populated minimal population upgrade for Mirrored Channel Mode are DIMM A1 and DIMM B1 DIMM A1 and DIMM B1 must be identical otherwise they will revert to Independent Channel Mode When both CPU sockets are populated minimal population upgrade for the Mirrored Channel Mode are DIMM A1 DIMM B1 DIMM D1 and DIMM E1 DIMM A1 and DIMM B1 as a pair must be identical and so must DIMM D1 and DIMM E1 as a pair The DIMMs on different CPU sockets need not be identical in size and or sizi
9. TMP75 Ox9E e REPEATER POWER SUPPLY T 3 3VSB 5V PRU OxAC PCA9515 J cst HSBP Conn A l OxC0 2 S l HSBP S i ISO Ezieg Conn B b B Iso PA 5vse 5v 0xC2 z z ssvsrovww eus 3vsB svsB IPMI T r Conn 3 2 1 o SM Bus Ports r Video ISO A E Integrated BMC ETE C PA conn GFX DDC 33v sTBY OFX DOC 3 3VSB sv orao Figure 27 SMBUS Block Diagram BIOS Setup Utility Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 5 BIOS Setup Utility 5 1 Logo Diagnostic Screen The Logo Diagnostic Screen displays in one of two forms e f Quiet Boot is enabled in the BIOS setup a logo splash screen is displayed By default Quiet Boot is enabled in the BIOS setup If the logo displays during POST press Esc to hide the logo and display the diagnostic screen e Ifa logo is not present in the flash ROM or if Quiet Boot is disabled in the system configuration the summary and diagnostic screen is displayed The diagnostic screen displays the following information e BIOS ID e Platform name e Total memory detected Total size of all installed DDR3 DIMMs e Processor information Intel branded string speed and number of physical processors identified e Keyboards detected if plugged in e Mouse devices detected if plugged in 5 2 BIOS Boot Popup Menu The BIOS Boot Specification BBS provides for a Boot Popup Menu invoked by pressing the F6 key during POST The BBS popup menu
10. nec mm 13 nara i 3 O Processor 2 Version Help Text Comments Information only Processor CPUID Information only Current frequency of the processor Information only Revision of the loaded microcode Information only Size of the Processor L1 Cache Information only Size of the Processor L2 Cache Information only Size of the Processor L3 Cache Information only ID string from the Processor Information only ID string from the Processor Current Intel QPI Link Speed Intel QPI Link Frequency Enabled Disabled Intel Turbo Boost Technolgy Enabled Disabled Enhanced Intel SpeedStep Tech Enabled Disabled Intel Hyper Threading Tech Core Multi Processing Enabled Disabled Execute Disable Bit Enabled Disabled Intel Virtualization Technology 80 Intel Turbo Boost Technology allows the processor to automatically increase its frequency if it is running below power temperature and current specifications Enhanced Intel SpeedStep Technology allows the system to dynamically adjust processor voltage and core frequency which can result in decreased average power consumption and decreased average heat production Contact your OS vendor regarding OS support of this feature Intel HT Technology allows multithreaded software applications to execute threads in parallel within each processor Contact your OS vendor regarding OS support of this feature
11. 2 n 0 158 MEMORY VR HEATSINK PUSH PIN KEEPOUT AREA NO COMPONENT ALLOWED 2 PLACES Ys YY E 2 AZ ZA v 0 100 2 54MM lt A MAX COMPONENT HEIGHT 450 400 GROUND PADS 10 PLACES 110 16 0 458 d i PIN THRU HOLE COMPONENT ZONE 10 PLACES 16 51 SHH S SOCKET ILM KEEP IN AREA NO COMPONENT 2 PLACES COMPONENT HEIGHT RESTRICTIO 0 130 MAX S z SEE DETAIL p em N D A lt L PP B TYLERSBURG NO COMPONENT ZONE TYLERSBURG BARE DIE HEATSINK 0 063 1 6MM MAX COMPONENT HEIGHT ZONE HEATSINK BASE AREA MAX COMPONENT HEIGHT 0 0394 CH 9 77 QL QQ 2 YV S S BZ WG A Yl SN Gf MAX COMPONENT HEIGHT 0 1 FOR SAS MODULE KET LLL DSSA S VY LES Ki fe SC W SSS E A AN M E gt 277 NG 7 MAX COMPONENT HEIGHT 0 100 FOR SAS MODUL d D DI wf NO COMPONENT TONE FOR ADD ON CARD RETENTION 0 150 MAX COMPONENT HEIGHT IAX COMPONENT HEIGHT 0 360 FOR SAS MOOULE MAX COMPONENT HEIGHT 0 137 MAX COMPONENT HEIGHT 0 236 PU HEATSINK AREA 0 118 3MM MAX COMPONENT WEIGHT RESTRICTION 4 PLACES SOCKET CAVITY 0 070 1 8MM MAX COMPONENT REIGHT RESTRICTION 2 PLACES 0 276 IMM MAX COMPONENT HEIGHT RESTRICTION 2 PLACES PU VR HEATSINK LANDING FEET NO COMPONENT 2 PLACES d PU VR HEATSINK 0 033 MAX COMPONENT HEIGHT RESTRICTION 2 PLACES 0 236 CPU ILM MOUNTING HOLE 6 00 BOARD ROUNTING KEEP
12. 25 27 29 31 33 35 37 39 41 43 45 47 49 Name PE ICH10 SAS SW C TP1 GND PE ICH10 SAS SW C TN2 GND PE ICH10 SAS SW C TN3 GND PE WAKE N P3V3 P3V3 GND PE ICH10 SAS SW RXNO GND PE ICH10 SAS SW RXN1 GND PE ICH10 SAS SW RXN2 GND PE ICH10 SAS SW RXN3 GND CLK 100M SAS DN GND P3V3 Serial Port Connectors Pin 0 PE_ICH10_ 2 4 PE ICH10 6 8 PE ICH10 SAS SW C TN3 20 FM SAS PRSNTN 2 FM SAS RSTN d PERXN 22 e P3v3AUX 8 PE CH10 SAS SW RXPO 0 2 4 6 8 0 2 4 6 8 2 2 2 2 1 1 1 1 1 3 3 3 3 3 4 4 4 4 4 50 P3V3 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS The server boards provide one external DB9 Serial A port J8A1 and one internal 9 pin Serial B header J1B1 The following tables define the pin outs 114 Table 60 External DB9 Serial A Port Pin out J8A1 ABIO N 2 GND Table 61 Internal 9 pin Serial B Header Pin out J1B1 oo o Ke Signal Name Description SPB DCD DCD carrier detect SPB DSR 5 7 DSR data set ready SPB SIN L i RI Ring indicate Intel order number E39529 013 Revision 1 8 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 6 5 6 USB Connector The following table details the pin out of the external USB connectors J5A1 J6A1 found on the back edge of the server bo
13. BEV Device Order Fields Setup Item Options Help Text BEV Device 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group BEV Device 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 7 Boot Manager Screen The Boot Manager screen allows the user to view a list of devices available for booting and to select a boot device for immediately booting the system To access this screen from the Main screen select Boot Manager Main Advanced Security Server Management Boot Options Boot Manager Internal EFI Shell lt Boot device 1 gt lt Boot Option x gt Figure 50 Setup Utility Boot Manager Screen Display Table 43 Setup Utility Boot Manager Screen Fields Help Text Internal EFI Shell Select this option to boot now Note This list is not the system boot option order Use the Boot Options menu to view and configure the System boot option order Boot Device x Select this option to boot now Note This list is not the system boot option order Use the Boot Options menu to view and configure the system boot option order Revision 1 8 105 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 5 3 2 8 Error Manager Screen The Error Manager screen displays any errors encountered during POST Error
14. COE e OxAGAO DXE boot services driver Not enough memory available to shadow a legacy No Pause option ROM OxB6A3 DXE boot services driver Unrecognized Pause 168 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Appendix F POST Error Messages and Handling POST Error Beep Codes The following table lists the POST error beep codes Prior to system video initialization the BIOS uses these beep codes to inform users of error conditions The beep code is followed by a user visible code on the POST Progress LED s Table 87 POST Error Beep Codes Beeps POST Progress Code Multiple System halted because a fatal error related to the memory was detected The BMC may generate beep codes upon detection of failure conditions Beep codes are sounded each time the problem is discovered such as on each power up attempt but are not sounded continuously Each digit in the code is represented by a sequence of beeps whose count is equal to the digit Table 88 BMC Beep Codes Code Associated Sensors 1 5 2 1 CPU Empty slot Population error CPU sockets are populated incorrectly CPU1 must be populated before CPU2 1 5 4 2 Power fault DC power unexpectedly lost power good Power unit power unit failure offset dropout 1 5 4 4 Power control fault power good assertion timeout Power unit soft power control failure offset Revision 1 8 169 Intel order
15. Current Date is replaced by the actual current date e Information enclosed in square brackets in the tables identifies areas where the user must type in text instead of selecting from a provided option e Whenever information is changed except Date and Time the systems requires a save and reboot to take place Pressing lt ESC gt discards the changes and boots the system according to the boot order set from the last boot Revision 1 8 75 Intel order number E39529 013 BIOS Setup Utility 5 3 2 1 Main Screen Unless an error occurred the Main screen is the first screen displayed when the BIOS Setup is entered If an error occurred the Error Manager screen displays instead Advanced Security Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Server Management Boot Options Boot Manager Figure 28 Setup Utility Main Screen Display Table 21 Setup Utility Main Screen Fields Setup Item Options Help Text Comments Logged in as Information only Displays password level that setup is running in Administrator or User With no passwords set Administrator is the default mode Platform ID Information only Displays the Platform ID System BIOS Version Information only Displays the current BIOS version xx 7 major version yy minor version ZZZZ 7 build number Build Date Information only Displays the current BIOS build date Memory 76 Revision 1 8 Intel order number E
16. Made in xxxxx Model Designation Regulatory Examples Server Board S5520HC for boxed type boards or Board 138 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Regulatory and Certification Information Identification PB number for non boxed boards typically high end boards 10 3 Electromagnetic Compatibility Notices FCC USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation For questions related to the EMC performance of this product contact Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 6497 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to r
17. Supports entry hardware RAID 0 RAID 1 and RAID 1E and native SAS pass through mode 3 6 1 2 Intel ESRTII Mode The Intel Embedded Server RAID Technology II Intel ESRTII feature provides RAID modes 0 1 and 10 If RAID 5 is needed with Intel ESRTII you must install the optional Intel RAID Activation Key AXXRAKSWB accessory This activation key is placed on the SAS Software RAID 5 connector located on the Intel SAS Entry RAID Module AXX4SASMOD For installation instructions see the documentation included with the SAS Module AXXASASMOD and the activation key When Intel Embedded Server RAID Technology II is enabled with the SAS Module AXXASASMOD enclosure management is provided through the GA SGPIO or SES connector on the SAS Module AXXASASMOD when a cable is attached between this connector and the backplane or DC interface 46 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Functional Architecture 3 7 Baseboard Management Controller The Intel Server Boards S5520HC S5500HCV and S5520HCT have an integrated BMC controller based on ServerEngines Pilot l The BMC controller is provided by an embedded ARM controller and associated peripheral functionality that is required for IPMI based server management The following is a summary of the BMC management hardware features used by the BMC e 250 MHz 32 bit ARM9 Processor e Memory Management Unit MMU e Two 10 100 Et
18. This is not user configurable 4 2 6 Local Directory Authentication Protocol LDAP The BMC firmware supports the Linux Local Directory Authentication Protocol LDAP protocol for user authentication IPMI users passwords and sessions are not supported over LDAP A user can configure LDAP usage through the embedded web server for authentication of future embedded web sessions Note Supports LDAP for Linux only 66 Revision 1 8 Intel order number E39529 013 Intel Server Boards SS520HC S5500HCV and 5520HCT TPS Platform Management 4 3 Platform Control This server platform has embedded platform control which is capable of automatically adjusting system performance and acoustic levels Performance Performance Management Throttling I ntegrated Acoustic Control Thermal Management Monitoring Fan Speed Control Figure 26 Platform Control Platform control optimizes system performance and acoustics levels through e Performance management e Performance throttling e Thermal monitoring e Fan speed control e Acoustics management The platform components used to implement platform control include e Integrated baseboard management controller e Platform sensors e Variable speed system fans e System BIOS e BMC firmware e Sensor data records as loaded by the FRUSDR Utility e Memory type Revision 1 8 67 Intel order number E39529 013 Platform Management Intel Server Boards 5520HC S5500HCV and S5520HCT TPS
19. features This screen also provides an access point to the screens for configuring console redirection and displaying system information To access this screen from the Main screen select Server Management 94 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Advanced Assert NMI on SERR Assert NMI on PERR Resume on AC Power Loss Clear System Event Log FRB 2 Enable O S Boot Watchdog Timer O S Boot Watchdog Timer Policy O S Boot Watchdog Timer Timeout ACPI 1 0 Support Plug amp Play BMC Detection Security Server Management Boot Options Enabled Disabled Enabled Disabled Stay Off Last state Reset Enabled Disabled Enabled Disabled Enabled Disabled Power off Reset 5 minutes 10 minutes 15 minutes 20 minutes Enabled Disabled Enabled Disabled BIOS Setup Utility Boot Manager gt Console Redirection gt System Information Figure 39 Setup Utility Server Management Configuration Screen Display Table 32 Setup Utility Server Management Configuration Screen Fields Enabled On SERR generate an NMI and log an error Disabled Note Enabled must be selected for the Assert NMI on PERR setup option to be visible On PERR generate an NMI and log an error Note This option is only active if the Assert NMI on SERR option is Enabled selected Setup Item Assert NMI on SERR Assert NMI on PERR Enabled Disabled Resume on AC Power L
20. 1 8 Intel order number E39529 013 Intel Server Boards SS520HC S5500HCV and 5520HCT TPS BIOS Setup Utility 5 3 2 6 4 CDROM Order Screen The CDROM Order screen allows the user to control the CDROM devices To access this screen from the Main screen select Boot Options gt CDROM Order Boot Options CDROM 1 lt Available CDROM devices gt CDROM 2 lt Available CDROM devices gt Figure 46 Setup Utility CDROM Order Screen Display Table 39 Setup Utility CDROM Order Fields CDROM 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group CDROM 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 5 Floppy Order Screen The Floppy Order screen allows the user to control the floppy drives To access this screen from the Main screen select Boot Options Floppy Order Boot Options Floppy Disk 1 lt Available Floppy Disk gt Floppy Disk 2 lt Available Floppy Disk gt Figure 47 Setup Utility Floppy Order Screen Display Table 40 Setup Utility Floppy Order Fields Floppy Disk 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Revision 1 8 103 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Setup It
21. BIOS provides the option for Dual Monitor Video operation when an add in video card is configured in the system 3 11 1 Video Modes The integrated video controller supports all standard IBM VGA modes The following table shows the 2D modes supported for both CRT and LCD Revision 1 8 49 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Table 14 Video Modes 2D Mode SEE ees Mode supot SETS Supported Supported Supported Supported 640x480 S0 72 75 85 60 72 75 85 60 72 75 85 60 72 75 85 on Rate Supported Supported Supported Supported 809x609 56 60 72 75 85 56 60 72 75 85 56 60 72 75 85 56 60 72 75 85 Ha pom Supported Supported Supported Supported 1024x768 60 70 75 85 60 70 75 85 60 70 75 85 60 70 75 85 bod Rate Supported Supported Supported N A 1152 x 864 75 75 75 N A Ch Rate Supported Supported Supported N A 1280 x 1024 50 75 85 60 75 85 60 NA Ti Rate Supported Supported Supported N A 1440 x 900 60 60 60 NA Ox Rate Supported Supported N A N A 1600 x 1200 60 65 70 75 85 60 65 70 N A N A iia Rate 3 11 2 Dual Video The BIOS supports single and dual video modes The dual video mode is enabled by default e In single mode the onboard video controller is disabled when an add in video card is detected e In dual mode enable Dual Monitor Vi
22. BMC Update jumper J1H1 set to the enabled position pins 2 3 You should never run the server with the Force BMC Update jumper set in this position and should only use the jumper in this position when the standard BMC firmware update process fails This jumper must remain in the default disabled position pins 1 2 when the server is running normally e This server board no longer supports the Rolling BIOS two BIOS banks It implements the BIOS Recovery mechanism instead e When performing a normal BIOS update procedure you must set the BIOS Recovery jumper J1E5 to its default position pins 1 2 e Locate the device that generates System Event Log SEL PCI device event the SEL PCI device event may not specify which PCI device in the system that generates the event entry users can follow below tips to locate the PCI device Step1 Identify the PCI device location number the SEL event entry in Hex code see the SEL viewer utility help text instruction for read of Hex code provides the PCI device bus number device number and function number with last two bytes ED2 and ED3 The byte of ED2 provides the PCI device bus number the higher four bits of ED3 byte provides the device number and the lower four bits of ED3 byte provides the function number Revision 1 8 145 Intel order number E39529 013 Appendix A Integration and Usage Tips Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 146 Step 2 Decide the PC
23. CONN B4 5 7 10 11 12 13 V IO VSYNC CONN VSYNC vertical sync V IO DDCCLK DDCCLK 112 Intel order number E39529 013 Revision 1 8 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Connector Header Locations and Pin outs 6 5 2 NIC Connectors The server boards provide two stacked RJ 45 2xUSB connectors side by side on the back edge of the board J5A1 J6A1 The pin out for NIC connectors is identical and defined in the following table Table 57 RJ 45 10 100 1000 NIC Connector Pin out J5A1 J6A1 JL GND 7 10 11 12 13 6 5 3 SATA Connectors The server boards provide up to six SATA connectors SATA 0 J1G5 SATA 1 J1G4 SATA 2 J1G1 SATA 3 J1F4 SATA 4 J1F1 and SATA 5 J1E3 The pin configuration for each connector is identical and defined in the following table Table 58 SATA SAS Connector Pin out J1E3 J1G1 J1G4 J1G5 J1F1 J1F4 Signal Name Ground S y O Ground 6 5 4 SAS Module Slot The server boards provide one SAS module slot J2J1 to support the Intel SAS Entry RAID Module AXX4SASMOD card The following table defines the pin out Table 59 SAS Module Slot Pin out J2J1 j Name Pin Name 1 P3V3 AUX 2 RST LPC SAS N SW RAID MODE PE ICH10 SAS SW C TPO 6 PE ICH10 SAS SW C TNO LI GND GND Revision 1 8 113 Intel order number E39529 013 Connector Header Locations and Pin outs 6 5 5 Pin 11 13 15 17 19 21 23
24. DMMBiDad Pase O en DIMM_B2 Disabled Pase eu DMM Disabled Pas M45 DMM C2Dsabd E en DIMM_D1 Disabled Pmse ssar DIMM_D2 Disabled Pase DIMM E1 Disabled 549 DIMWE2Dkabd e 854A DIMM F1 Disabled Pause 8560 DIMM A1 Component encountered a Serial Presence Detection SPD Seng Pause DIMM A2 Component encountered a Serial Presence Detection em fail error 8562 DIMM B Component encountered a Serial Presence Detection SPD fallemor Pause 8563 DIMM B2 Component encountered a Serial Presence Detection SPD fail error Pause 8564 DIMM C1 Component encountered a Serial Presence Detection SPD falemor Pause 2565 DIMM CZ Component encountered a Serial Presence Detection SPD falemor Pause 8566 L Di Component encountered a Serial Presence Detection SPD falemor Pause 8567 DIMM D2 Component encountered a Serial Presence Detection SPD falleror Pause 2568 DIMM_E1 Component encountered a Serial Presence Detection SPD fallerror Pause 8560 DIMM E2 Component encountered a Serial Presence Detection SPD falemor Pause 856A DIMM F1 Component encountered a Serial Presence Detection SPD fail error Pause 2568 DIMM F2 Component encountered a Serial Presence Detection SPD fail error Pause eeng DIM _A1 Uncorrectable ECC error encountere
25. Description Pin Signal Name Description 1 P3V3 STBY Power LED 2 P3V3_STBY Front Panel Power_LED_Anode Power 3 Key No Connection 4 P5V_STBY ID ID LED LED Anode 5 FP_PWR_LED_N PowerLED 6 FP_ID_LED BU IDLED Joe FN Power 7 P3V3 HDD Activity 8 FP LED STATU Status LED LED ID HDD ACTIVITY Ano LED S GREEN N Green L LED de S 9 LED HDD ACTIVITY HDD Activity 10 FP LED STATU Status LED ril ped o N LED S_AMBERN_ Amber 11 FP PWR BTN N Power Button 12 NIC1 ACT LED NIC 1 Activity Power NIC 1 _N LED Button L Link Activity 13 GND Power Button Power Button 14 NIC1 LINK LED NIC 1 Link GND Ground N LED Reset SM Bus 15 BMC RST BTN N Reset Button 16 SMB SENSOR SMB Sensor Button tOO Se 3V3STB DATA DATA ID Button She h 17 BND Reset GND Reset Button 18 SMB SENSOR SMB Sensor Temp Sensor Ground 3V3STB_CLK Clock NIC2 19 FP ID BTN N ID Button 20 FP CHASSIS IN Chassis NMI Activity LED TRU Intrusion 23 2 21 FM SIO TEMP SEN Front Panel 22 NIC2 ACT LED NIC 2 Activity SOR Temperature _N LED Sensor 23 FP NMI BTN N NMI Button 24 NIC2 LINK LED NIC 2 Link _N LED 6 5 1 0 Connectors 6 5 1 VGA Connector The following table details the pin out definition of the VGA connector J7A1 that is part of the stacked video serial port A connector Table 56 VGA Connector Pin out J7A1 Signal Name Blue analog color signal B Description 4 TP VID
26. EFI Optimized Boot If enabled the BIOS only loads modules required for booting EFl aware Operating Systems Enabled Disabled Use Legacy Video for EFI OS If enabled the BIOS will use the legacy video ROM instead of the EFI video ROM Enabled Disabled Enabled Disabled Boot Option Retry If enabled this continually retries non EFl based boot options without waiting for user input USB Boot Priority If enabled newly discovered USB devices will be put to the top of their boot device category If disabled newly discovered USB devices will be put at the bottom of the respective list 100 Intel order number E39529 013 Comments After entering the necessary timeout press the Enter key to register that timeout value to the system These settings are in seconds Displays when one or more hard disk drives are in the system Displays when one or more CD ROM drives are in the system Displays when one or more floppy drives are in the system Displays when one or more of these devices are available in the system Displays when one or more of these devices are available in the system This option is only displayed if an EFI bootable device is available to the system for example a USB drive If the EFI shell is deleted it is restored on the next system reboot It cannot be permanently deleted Grayed out when SW RAID SATA Mode is Enabled SW RAID can only be used in Leg
27. Em Platform Ges Event Reading Event Offset Contrib To Assert De Sensor name in SDR Applicability yp Type Triggers System Status assert Value Offs ets Catastrophic Error Processor Digital 01 State Di t x fs i CATERR 07h jo e Assertad Non fatal Trig Offset m Digital CPU Missing Processor Discrete 01 State Trig Offset CPU Missing 07h 03h Asserted IOH Thermal Trip 6Ah All Temperature E 01 State Fatal As and Tria Offset M IOH Thermal Trip 01h Gg Asserted De g Note 1 Sensor only present on systems that have applicable redundancy for instance a fan or power supply Revision 1 8 159 Intel order number E39529 013 Appendix D Platform Specific BMC Appendix Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS Appendix D Platform Specific BMC Appendix Table 83 Platform Specific BMC Features Y Support Intel Server Chassis Intel Server Chassis Intel Server Chassis Intel Server Chassis Intel Server Chassis N Not Support SC5650DP SC5650BRP SC5600Base SC5600BRP SC5600LX Intel Server Board 55520HC Compatible Compatible Compatible Compatible Compatible Intel Server Board SSSOOHCV Compatible Compatible Compatible Compatible Compatible CPU 1 Fan Sensor 31 Y Y Y Y N J CPU 2 Fan Sensor 30 Y Y Y Y N Ca zi System Fan 1 Sensor 37 Y Y Y Y Y S amp System Fan 2 Sensor 36 N N N N Y amp System Fan 3 Sensor 35 Y
28. GND 2 2 KEY pin removed RMII TXDO RMII TXD1 6 1 1 GND 14 1 1 4 3V3 AUX 2 0 2 6 GND 8 0 2 3V3 AUX 6 Em 21 110 RMII TX EN bi SPI CS N NC spare Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Connector Header Locations and Pin outs 30 F 2 GND 34 RMM3_Present_N pulled high on baseboard and shorted to ground on the plug in module 6 3 2 LCP IPMB Header Table 52 LCP IPMB Header Pin out J1G6 6 3 3 HSBP Header Table 53 HSBP Header Pin out J1F5 J1G3 SMB_IPMB_5V_CLK BMC IMB 5V Clock Line P5V HSBP A 5 V for HSBP A GND HSBP B Ground for HSBP B 6 3 4 SGPIO Header Table 54 SGPIO Header Pin out J1G2 Pin Signal Name Description 1 SGPIO CLOCK SGPIO Clock Signal 2 SGPIO LOAD SGPIO Load Signal 3 SGPIO DATAOUTO SGPIO Data Out 4 SGPIO DATAOUT1 SGPIO Data In 6 4 Front Panel Connector The server boards provide a 24 pin SSI front panel connector J1B3 for use with Intel and third party chassis The following table provides the pin out for this connector Revision 1 8 111 Intel order number E39529 013 Connector Header Locations and Pin outs Table 55 Front Panel SSI Standard 24 pin Connector Pin out J1B3 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Pin Signal Name
29. Optional Advanced Management Feature Support sssssssssssss 63 4 2 1 Enabling Advanced Management Features ccccccceeeeeeeeeeeeeeeeeeeeneeeeeeeetenees 63 4 2 2 Keyboard Video and Mouse KVM Redirechon 63 4 2 3 Media Redirection EE 64 4 2 4 Web Services for Management NS MAN 65 4 2 5 Embedded Web server AE 66 4 2 6 Local Directory Authentication Protocol DAP 66 4 3 Platform Control es AER ges dead RE be deed de nae nape etl asa 67 4 3 1 Memory Open and Closed Loop Thermal Throttling ssseeseessssss 68 4 3 2 Fan Speed Control ce ertet ire eer eie ee P wand 68 4 4 Intel Intelligent Power Node Manager 70 4 4 1 Manageability Engine ME 70 5 BIOS Setup Utility 1 icai cura geed deene psina nis dses oton inini E 72 5 1 Logo Diagnostic Green 72 5 2 BIOS Boot Popup Men 72 Revision 1 8 V Intel order number E39529 013 Table of Contents Intel Server Boards S5520HC S5500HCV and S5520HCT TPS 5 3 BIOS Setup Utility cett n nee e RR ede La LONE r rent LR 72 5 3 1 ijo uM as 72 5 3 2 Server Platform Setup Utility Screens cece ceeeeeceeeeceeeeeeeeeeeeeneeeeeeeeeesnananeees 75 6 Connector Header Locations and Pin outs c c ccesseeeceeseeeeeeesneeeeeseeeeeeseseeeeenseeeeens 108 6 1 Board Connector Information 108 6 2 Power Connectors cda ue dh dede de edi nena 109 6 3 System Management Headers neeeeeeeneeteeeeeertrtn
30. RAID Module option is enabled by default once the Intel SAS Entry RAID Module AXX4SASMOD is present When enabled you can set the Configure Intel SAS Entry RAID Module to either LSI Integrated RAID or Intel ESRTII mode Revision 1 8 45 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Table 12 Intel SAS Entry RAID Module AXXASASMOD Storage Mode SW RAID Intel Embedded Server RAID Technology II ESRTII IT IR RAID IT IR RAID Entry Hardware RAID Storage m RAID Types and Levels RAID Management RAID Compatible a Description Driver Software Mode Supported Software SC Backplane User s Guide Native SAS pass through mode without RAID function SAS MPT NDA EU driver Fully IT IR RAID IT IR RAID SEN dri Entry Hardware open source Inte RAID Web Software vn e e RAID driver Console 2 Users Mapa ee RAID 1 IM mode Broad OS Guide AXX6DRV3GR p RAID 10 10E IME support AXX4DRV3GR mode AXX6DRV3GEXP RAID 0 IS Mode AXX4DRV3GEXP 4 SAS Ports SW RAID 0 1 10 ESR AIDING 5 Up to 8 SAS or standard Microsoft a Intel RAID SW RAID SKTA dri SW RAID 5 with Windows and Intel RAID Web Software f yes M selected Console 2 Users via expander optional Linux Guide backplanes AXXRAKSW5 Versions only Select in BIOS Setup Configure Intel SAS Entry RAID Option on Advanced Mass Storage Controller Configuration Screen 3 6 1 1 IT IR RAID Mode
31. Revision 1 8 vii Intel order number E39529 013 List of Figures Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS List of Figures Figure 1 Intel Server Board S5520HQ EA 5 Figure 2 Intel Server Board S5500HQOW sott ine neces rhe dee fe aud 5 Figure 3 Major Board Components sse nennen tenen nennen nnns 7 Figure 4 Mounting Hole Locations 8 Figure 5 Major Connector Pin 1 Locations 1 oft 9 Figure 6 Major Connector Pin 1 Locations 2 of 2 10 Figure 7 Primary Side Keep out Zone oft 11 Figure 8 Primary Side Keep out Zone 2 of 12 Figure 9 Primary Side Air Duct Keep out Zone 13 Figure 10 Primary Side Card Side Keep out Zone ee 14 Figure 11 Second Side Keep out Zone 15 Figure 12 Rear e Ne 16 Figure 13 Intel Server Board S5520HC Functional Block Diagram eeee 18 Figure 14 Intel Server Board S5500HCV Functional Block Diagramm 19 Figure 15 Unified Retention System and Unified Back Plate Aesemblv nenene 26 Figure 16 Intel Server Board S5520HC DIMM Slots Arrangement 28 Figure 17 Intel Server Board S5500HCV DIMM Slots Arrangement 29 Figure 18 Intel SAS Entry RAID Module AXX4SASMOD Component and Connector Layout 44 Figure 19 Intel SAS Entry RAID Module AXX4SASMOD Functional Block Diagram 45 Figure 20 Integrated BMC Hardware eee 48 Figure 21 Setup Utility TPM Configuration Green 54 Figure 22 Setting Administrator password in BIO 56 Fig re 23 Activating TPM i in
32. Setup Utility Table 31 Setup Utility Security Configuration Screen Fields Help Text Comments Administrator Password Installed Information only Indicates Status Not Installed the status of the administrator password User Password Status Installed Information only Indicates Not Installed the status of the user password Set Administrator 123aBcD Administrator password is used This option is only to control Password to control change access in access to the setup BIOS Setup Utility Administrator has full Only alphanumeric characters access to all the setup can be used Maximum length is items Clearing the 7 characters It is case Administrator password sensitive also clears the user Note Administrator password password must be set in order to use the user account Set User Password 123aBcD User password is used to Available only if the control entry access to BIOS administrator password is Setup Utility installed This option only Only alphanumeric characters protects the setup can be used Maximum length is User password only has 7 characters It is case limited access to the setup sensitive items Note Removing the administrator password also automatically removes the user password Front Panel Lockout Enabled If enabled locks the power Disabled button and reset button on the system s front panel If Enabled is selected power and reset must be controlled via a system management inter
33. Sup poms EE 41 3 5 PGI S bSystem xio one irr tete nat e tu Rte te ri b EENS EE 42 3 5 1 PCI Express Riser Slot 85520HC Slot pi 43 3 6 Intel SAS Entry RAID Module AXX4SASMOD Optional Accessory 44 3 6 1 SAS RAID SU p OTi cioe tet rg e ee eite e tue er o CL enc ee rad 45 3 7 Baseboard Management Controller eere trtrtsrerrertntrteerennrnneernene 47 3 7 1 BMC Embedded LAN Channel 48 3 8 Serial Ports uc cnn eae ae EUR RE e ere eed es 49 3 9 Floppy Disk Controller AAA 49 3 10 Keyboard and Mouse Support eene eene nnn 49 3 11 Video Support it t TR nd ob e am ec GU e e e E p E ecd 49 SANI Video Modes s ee me tec ic e ead 49 3 4 1227 tel Video torpe te teret e eee rete a Idem 50 3 12 Network Interface Controller NIC 51 3 12 1 MAC Address Definition EE 51 3 13 Trusted Platform Module TPM Supported only on S5520HCT 52 SRL TII ME 52 3 132 TPM security BIOS hector epo E ded pet ERE RYE PORE d eua EiS 52 3 13 3 Intel Trusted Execution Technology Intel TXT 55 3 14 Le ET 59 3 15 Intel Virtualization Technology soie e bte et te ab fetus 60 3 15 1 Intel Virtualization Technology for Directed IO ONT 60 4 Platform Management i i crim notnm tuna n epa nsn aug Chiara a na 23S a Ya ua auc n eb Lao ara EEN bag 61 4 1 Feature SUPPOM EE 61 4 1 1 IPME2 O Eeatures ee mte ee e te tent 61 4 1 2 Non IPMI Features nee ener en nmnnerr enne nhe nere n nenne renes nnn 61 4 2
34. a specific type of discrete sensors that only have two states Event Offset Triggers Event Thresholds are event generating thresholds for threshold type sensors u nr c onc upper non recoverable upper critical upper non critical lower non recoverable lower critical lower non critical uc Ic upper critical lower critical Event triggers are supported event generating offsets for discrete type sensors You can find the offsets in the generic event reading type code or sensor type code tables in the ntelligent Platform Management Interface Specification Second Generation v2 0 depending on whether the sensor event reading type is generic or a sensor specific response Assertion De assertion Enables Assertion and de assertion indicators reveal the type of events the sensor generates As Assertions De De assertion Readable Value Offsets Readable Values indicate the type of value returned for threshold and other non discrete type sensors Readable Offsets indicate the offsets for discrete sensors that are readable with the Get Sensor Reading command Unless otherwise indicated all event triggers are readable Readable Offsets consist of the reading type offsets that do not generate events Event Data Event data is the data included in an event message generated by the sensor For threshold based sensors the following abbreviations are used R Reading value T Threshold value Revision 1 8 Intel order nu
35. a sub menu or pick list is displayed The lt Tab gt key is used to move between fields For example you can use lt Tab gt to move from hours to minutes in the time item in the main menu The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full list The plus key on the keypad is used to change the value of the current menu item to the next value This key scrolls through the values in the associated pick list without displaying the full list On 106 key Japanese keyboards the plus key has a different scan code than the plus key on the other keyboards but will have the same effect Pressing lt F9 gt causes the following to display Load Optimized Defaults Yes No If Yes is highlighted and Enter is pressed all Setup fields are set to their default values If No is highlighted and lt Enter gt is pressed or if the lt Esc gt key is pressed the user is returned to where they were before lt F9 gt was pressed without affecting any existing field values Pressing lt F10 gt causes the following message to display Save configuration and reset Yes No If Yes is highlighted and Enter is pressed all changes are saved and the Setup is exited If No is highlighted and lt Enter gt is pressed or the lt Esc gt key is pressed the user is ret
36. amber Diagnostic LEDs The POST codes are divided into two nibbles an upper nibble and a lower nibble The upper nibble bits are represented by Diagnostic LED s 4 5 6 and 7 The lower nibble bits are represented by Diagnostics LED s 0 1 2 and 3 If the bit is set in the upper and lower nibbles the corresponding LED lights up If the bit is clear the corresponding LED is off Diagnostic LED 7 is labeled MSB Most Significant Bit and Diagnostic LED 0 is labeled LSB Least Significant Bit 60660 A Diagnostic LED 7 MSB LED E Diagnostic LED 3 B Diagnostic LED 6 F Diagnostic LED 2 C Diagnostic LED 5 G Diagnostic LED 1 D Diagnostic LED 4 H Diagnostic LED 0 LSB LED Figure 63 Diagnostic LED Placement Diagram In the following example the BIOS sends a value of EDh to the diagnostic LED decoder The LED s are decoded as follows Table 84 POST Progress Code LED Example Upper Nibble LED s Lower Nibble LED s LED s LED LED LED LED LED LED LED LED 7 6 5 4 3 2 1 0 8h 4h 2h 1h 8h 4h 2h 1h Status ON ON ON ON ON ON OFF ON 1 1 1 0 1 1 0 1 Results ER Dh Revision 1 8 161 Intel order number E39529 013 Appendix E POST Code Diagnostic LED Decoder Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Upper nibble bits 1110b Eh Lower nibble bits 1101b Dh the two are concatenated
37. and not being used as redundant units in Mirrored Channel Mode e f Quiet Boot is disabled the BIOS displays the total system memory on the diagnostic screen at the end of POST This total is the same as the amount described by the first bullet 3 3 4 1 Memory Reservation for Memory mapped Functions A region of size of 40 MB of memory below 4 GB is always reserved for mapping chipset processor and BIOS flash spaces as memory mapped l O regions This region appears as a loss of memory to the operating system This and other reserved regions are reclaimed by the operating system if PAE is enabled in the operating system In addition to this memory reservation the BIOS creates another reserved region for memory mapped PCI Express functions including a standard 64 MB or 256 MB of standard PCI Express MMIO configuration space This is based on the setup selection Maximize Memory below 4GB If this is set to Enabled the BIOS maximizes usage of memory below 4 GB for an operating system without PAE capability by limiting PCI Express Extended Configuration Space to 64 buses rather than the standard 256 buses 3 3 4 2 High Memory Reclaim When 4 GB or more of physical memory is installed physical memory is the memory installed as DDR3 DIMMs the reserved memory is lost However the Intel 5500 5520 I O Hub provides a feature called high memory reclaim which allows the BIOS and the operating system to remap the lost phys
38. as EDh Find the meaning of POST Code EDh in below table Memory Population Error RDIMMs and UDIMMs cannot be mixed in the system Table 85 POST Codes and Messages Progress Code Progress Code Definition Multi use Code This POST Code is used in different contexts OxF2 Seen at the start of Memory Reference Code MRC Start of the very early platform initialization code Very late in POST it is the signal that the OS has switched to virtual memory mode Memory Error Codes Accompanied by a beep code These codes are used in early POST by Memory Reference Code Later in POST these same codes are used for other Progress Codes These progress codes are subject to change as per Memory Reference Code OxE8 No Usable Memory Error No memory in the system or SPD bad so no memory could be detected or all memory failed Hardware BIST System is halted OxEB Memory Test Error One or memory DIMMs Channels failed Hardware BIST but usable memory remains System continues POST OxED Population Error RDIMMs and UDIMMs cannot be mixed in the system OxEE Mismatch Error more than 2 Quad Ranked DIMMS in a channel Host Processor 0x04 Early processor initialization where system BSP is selected 0x10 Power on initialization of the host processor Boot Strap Processor 0x11 Host processor cache initialization incl
39. displays all available boot devices The list order in the popup menu is not the same as the boot order in the BIOS setup it simply lists all the bootable devices from which the system can be booted When a User Password or Administrator Password is active in Setup the password is to access the Boot Popup Menu 5 3 BIOS Setup Utility The BIOS Setup utility is a text based utility that allows the user to configure the system and view current settings and environment information for the platform devices The Setup utility controls the platform s built in devices boot manager and error manager The BIOS Setup interface consists of a number of pages or screens Each page contains information or links to other pages The advanced tab in Setup displays a list of general categories as links These links lead to pages containing a specific category s configuration The following sections describe the look and behavior for platform setup 5 3 1 Operation The BIOS Setup has the following features 72 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS BIOS Setup Utility Localization The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard The Intel server board BIOS is only available in English Console Redirection The BIOS Setup is functional via console redirection over various terminal emulation
40. for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits 9 2 MTBF The following is the calculated Mean Time Between Failures MTBF 30 C ambient air These values are derived using a historical failure rate and multiplied by factors for application electrical and or thermal stress and for device maturity You should view MTBF estimates as reference numbers only e Calculation Model Telcordia Issue 1 method case 3 e Operating Temperature Server in 30 C ambient air e Operating Environment Ground Benign Controlled 128 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS e Duty Cycle 100 e Quality Level Il Table 72 MTBF Estimate Design and Environmental Specifications S5520HC MTBF S5500HCV MTBF Ambient Air Temperature C Air Temp at Board for 10 C rise CC hours hours 79 000 89 000 45 55 99 000 111 000 40 50 124 000 140 000 35 45 158 000 178 000 30 40 201 000 227 000 25 35 Revision 1 8 Intel order number E39529 013 128 Design and Environmental Specifications Intel Server Board 5520HC and SS5520HCSSSOOHCV TPS 9 3 Server Board Power Requirements This section provides power supply design guidelines for a system using the In
41. gt System Information Revision 1 8 97 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number Asset Tag BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 41 Setup Utility Server Management System Information Screen Display Table 34 Setup Utility Server Management System Information Fields Setup Item Board Part Number Information only Board Serial Number Information only Information only HSC Firmware Revision Information only If there is no HSC installed the Firmware Revision Number will appear as 0 00 ME Firmware Revision Information only SDR Revision Information only UUID Information only 5 3 2 6 Boot Options Screen The Boot Options screen displays any bootable media encountered during POST and allows the user to configure the desired boot device To access this screen from the Main screen select Boot Options 98 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S 5500HCV and S5520HCT TPS BIOS Setup Utility Main Advanced Security Server Management Boot Options Boot Manager System Boot Timeout Boot Option 1 Boot Option 2 Boot Option x Hard Disk Order CDROM Order Floppy Order Netwo
42. hard disk drives 3 4 1 1 1 Intel Embedded Server RAID Technology Il Option ROM The Intel Embedded Server RAID Technology II for SATA Option ROM provides a pre operating system user interface for the Intel Embedded Server RAID Technology II implementation and provides the ability to use an Intel Embedded Server RAID Technology II volume as a boot disk and detect any faults in the Intel Embedded Server RAID Technology II volume s 3 4 1 2 Onboard SATA Storage Mode Matrix Table 7 Onboard SATA Storage Mode Matrix SW RAID Intel Embedded Server RAID Technology II ESRTII Storage T RAID Types and RAD PAD Compatible Storage Mode Description Driver Management Software Controller Levels Supported PUMA Backplane Software User s Guide Chipset driver or operating 6 SATA ports at system Enhanced Native mode NA embedded N A NA Broad OS support 6 SATA ports Chipset driver port 0 1 2 3 at or operating Compatibility IDE Legacy N A Seed Ge N A N A Onboard mode port 4 5 Broad OS SATA at Native mode euer AXX6DRV3GF Controller PP AXX4DRV3GF ICH10R 6 SATA ports AHCI driver using the or OS AHCI Advanced Host N A embedded N A N A Controller Broad OS Interface support ESRTII Driver SW RAID 0 1 10 Microsoft e Intel RAID standard Windows Intel RAID Software SW RAID 6 SATA Ports SW RAID 5 with Web optional and selected Console 2 Users Linux Guide sn Versions only Select in BI
43. intel Intel Server Boards S5520HC S5500HCV and S5520HCT Technical Product Specification Intel order number E39529 013 Revision 1 8 May 2010 Enterprise Platforms and Services Division Revision History Date Revision Number February 2008 March 2008 March 2008 April 2008 August 2008 September 2008 February 2009 March 2009 July 2009 August 2009 November 2009 January 2010 March 2010 April 2010 May 2010 Poe LN 0 1 0 3 0 5 0 55 1 6 1 7 8 Intel Server Boards S5520HC SSSOOHCV and S5520HCT TPS Revision History Modifications Preliminary Draft Content Update Updated sections 2 1 and 3 2 Updated product code and processor support related information Updated product code and memory support related information S5500HCV DIMM slot population change and Chassis Intrusion header location change Jumper block location change Updated Block Diagram Updated Functional Architecture Section added BIOS Setup Utility Section and updated Appendix Updated Section 3 3 4 1 Memory Reservation for Memory mapped Functions Updated Section 3 4 1 2 onboard SATA Storage Mode Matrix table Added Fan Domain Table in Section 4 3 2 2 1 Updated Section 9 2 MTBF Added Appendix G Installation Guidelines Added Processor Stepping Mismatching on Table 2 Updated Boot Option BIOS Setup Menu Table 34 and Figure 36 Updated Table 4 Memory Running Frequency Updated Table 12 Inte
44. le 7 external RTC O Subsystem SPI Memory 1x PCI Express Interface to Host Figure 20 Integrated BMC Hardware 3 7 1 BMC Embedded LAN Channel The BMC hardware includes two dedicated 10 100 network interfaces which are given below Interface 1 This interface is available from either of the available NIC ports in system that can be shared with the host Only one NIC may be enabled for management traffic at any time The default active interface is onboard NIC1 Interface 2 This interface is available from Intel Remote Management Module 3 Intel RMM3 which is a dedicated management NIC and not shared with the host For these channels you can enable support for IPMI over LAN and DHCP For security reasons embedded LAN channels have the following default settings IP Address Static All users disabled IPMI enabled network interfaces may not be placed on the same subnet This includes the Intel RMM3 s onboard network interface and either of the BMC s embedded network interfaces 48 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Functional Architecture 3 8 Serial Ports The Intel Server Boards S5520HC S5500HCV and S5520HCT provide two serial ports an external DB9 serial port and an internal DH 10 serial header The rear DB9 serial A port is a fully functional serial port that can support any standard serial device Serial B is an optional port ac
45. memory discovery the BIOS arrives at a fastest common frequency that matches the requirements of all components of the memory system and then configures the DDR3 DIMMs for the fastest common frequency In addition rules on the following tables Tables 3 and 4 also decide the global common memory system frequency 30 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Table 3 Memory Running Frequency vs Processor SKU Functional Architecture DIMM Type DDR3 800 DDR3 1066 DDR3 1333 800 800 800 800 Processor Integrated Memory Running Frequency Memory Controller Hz Fastest Common IMC Max 1066 800 1066 1066 Frequency of Processor Frequency Hz IMC and Memory 1333 800 1066 1333 Table 4 Memory Running Frequency vs Memory Population DIMM Memory Running Frequency Command nae Per DIMM Y N SR Single Rank S DIMM Type Populated Address DR Dual Rank Description Per Channel 800MHz 1066MHz 1333MHz Rate QR Quad Rank All RDIMMs run at the fastest RDIMM 1 Y Y Y AN SR or DR common frequency of processo IMCs and installed memory 800MHz 1066MHz or 133MHz All RDIMMs run at 800MHz or 1066MHz when Quad Rank N RDIMM 1 Y S TN QR only RDIMM is installed in any channel All RDIMMs run at 800MHz or 1066MHz when two RDIMMs RDIMM S Y d n TN SSES Single Rank or Dual Rank are installed in the same channel All RDIM
46. minutes timeout value used by the BIOS to configure the Watchdog Timer is 15 minutes Watchdog timer disabled 20 minutes Plug amp Play BMC Enabled If enabled the BMC is detectable by OSs that support Detection Disabled plug and play loading of an IPMI driver Do not enable if your OS does not support this driver ACPI 1 0 Support Enabled Enabled Publish ACPI 1 0 version of FADT in Root Needs to be Enabled for Disabled System Description Table Microsoft Windows 2000 May be required for compatibility with OS versions support that only support ACPI 1 0 Console Redirection View Configure console redirection information and Takes the user to the settings Console Redirection screen System Information View system information Takes the user to the System Information screen 5 3 2 4 1 Console Redirection Screen The Console Redirection screen allows the user to enable or disable console redirection and configure the connection options for this feature To access this screen from the Main screen select Server Management Console Redirection Server Management Console Redirection Console Redirection Disabled Serial Port A Serial Port B Flow Control None RTS CTS Baud Rate 9 6k 19 2k 38 4k 57 6k 115 2k Terminal Type PC ANSI VT100 VT100 VT UTF8 Legacy OS Redirection Disabled Enabled Figure 40 Setup Utility Console Redirection Screen Display 96 Revision 1 8 Intel order number E39529 013 Intel Serv
47. monitor the fan speed Fan PWM FAN PWM signal to control fan speed Table 68 SSI 6 pin Fan Header Pin out J1K1 J1K2 J1K4 J1K5 Pin Signal Name Type Description 1 Grund GND__ Groundisthepowersupplyground Cd 3 FanTach_ Dn FAN TACH signal is connected to the BMC to monitor the fan speed Fan PWM FAN PWM signal to control fan speed 5 FanPresence In Indicates the fan is present 6 Fan Fault LED Lights the fan fault LED Note Intel Corporation server boards support peripheral components and can contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits Revision 1 8 117 Intel order number E39529 013 Jumper Blocks 7 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Jumper Blocks The server boards have several 3 pin jumper blocks that
48. number E39529 013 Appendix G Installation Guidelines Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Appendix G Installation Guidelines 1 Drivers for Sun Solaris 10 U5 05 08 Device Description Chipset No driver required under Sun Solaris Enhanced SATA mode Onboard SATA No driver required under Sun Solaris AHCI Onboard SATA No driver required under Sun Solaris Onboard NIC Intel 82575EB No driver required under Sun Solaris AXX4SASMOD Native SAS pass through mode No driver required under Sun Solaris AXXROMBSASMR Driver is available from http support intel com support motherboards server S5520HC ESRTII Onboard SATA AXX4SASMOD Not currently supported under Sun Solaris Onboard Video ServerEngines No driver required under Sun Solaris Intel Hot Swap Hard Drive back plane No driver required under Sun Solaris 2 Sun Solaris 10 U5 05 08 hangs during early boot when EHCI 2 is enabled Description Sun Solaris 10 U5 may hang during early boot in the Intel Server Board S5520HC or S5500HCV when USB 2 0 is Enabled Guideline Disable USB 2 0 Controller option in BIOS Setup Menu or follow the instructions listed at the following website in order to accomplish this http bugs opensolaris org view bug do bug id 6681221 3 Sun Solaris 10 U5 05 08 may fail to boot into graphics display Description Sun Solaris 10 U5 may fail to boot into graphics display with Inte
49. of all outputs should not exceed the rated output power of the power supply The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions Table 74 670 W Load Ratings Voltage Minimum Continuous Maximum Continuous Peak 3 3 V 1 0A 24 A 5 V 200A 30A 12 V1 0 5 A 16A 18A 12 V2 1 0A 16A 18A 12 V3 0 5 A 31A 33A 12 V4 1 0A 16A 18A 12V OA 0 5A 5 VSB 0 1A 3 0A 5A 1 Maximum continuous total output power must not exceed 670 W Maximum continuous load on the combined 12 V output must not exceed 48 A Peak load on the combined 12 V output must not exceed 52 A Peak total DC output power must not exceed 730 W For 12 V peak power and current loading are supported for a minimum of 12 seconds For 5 VSB 5 VSB must withstand 5 A for 500 ms under the first turn on condition Combined 3 3 V and 5 V power must not exceed 170 W 9 4 1 Grounding The output ground of the pins of the power supply provides the output power return path The output connector ground pins are connected to the safety ground power supply enclosure 9 4 2 Stand by Outputs The 5 VSB output should be present when an AC input is greater than the power supply turn on voltage is applied FN oO VOT ode Revision 1 8 131 Intel order number E39529 013 Design and Environmental Specifications Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 9 4 3 Remote Se
50. on o J L PANEO Callout Description Callout Description A System Status LED E Video NIC Port 1 1 Gb Default Management B ID LED F Port USB Port 2 top 3 bottom NIC Port 2 1 Gb c Diagnostics LED S E USB Port 0 top 1 bottom D Serial Port A Figure 12 Rear UO Layout 16 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture 3 Functional Architecture The architecture and design of the Intel Server Boards S5520HC S5500HCV and S5520HCTis based on the Intel 5520 5500 and ICH10R chipset The chipset is designed for systems based on the Intel Xeon Processor 5500 Series in an FC LGA 1366 Socket B package with Intel QuickPath Interconnect Intel QPI speed at 6 40 GT s 5 86 GT s and 4 80 GT s The chipset contains two main components Intel 5520 I O Hub or 5500 UO Hub which provides a connection point between various I O components and the Intel QuickPath Interconnect Intel QPI based processors Intel ICH10 RAID ICH10R I O controller hub for
51. or disable the Intel Virtualization Technology for Directed I O in the BIOS Setup The default behavior is disabled Note After changing the Intel Virtualization Technology for Directed UO options disable or enable in the BIOS setup users must perform an AC power cycle before the changes can take effect 60 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCYV and S5520HCT TPS Platform Management 4 Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines Pilot Il The onboard platform management subsystem consists of communication buses sensors and the system BIOS and server management firmware Figure 27 provides an illustration of the Server Management Bus SMBUS architecture as used on these server boards 41 Feature Support 4 1 1 IPMI 2 0 Features e Baseboard management controller BMC e IPMI Watchdog timer e Messaging support including command bridging and user session support e Chassis device functionality including power reset control and BIOS boot flags support e Event receiver device The BMC receives and processes events from other platform subsystems e Field replaceable unit FRU inventory device functionality The BMC supports access to system FRU devices using IPMI FRU commands e System event log SEL device functionality The BMC supports and provides access to a SEL e Sensor data record SDR reposi
52. providing the Intel Server Platform Services SPS The controller is also commonly referred to as the Manageability Engine ME 3 1 5 Controller Link CL The Controller Link is a private low pin count LPC low power communication interface between the IOH and the ICH10 portions of the Manageability Engine subsystem Revision 1 8 21 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC 5500HCV and S5520HCT TPS 3 2 Processor Support The Intel Server Boards S5520HC S5500HCV and S5520HCT support the following processors e One or two Intel Xeon Processor 5500 Series with a 4 8 GT s 5 86 GT s or 6 4 GT s Intel QPI link interface and Thermal Design Power TDP up to 95 W e Oneortwo Intel Xeon Processor 5600 Series with a 6 4 GT s Intel QPI link interface and Thermal Design Power TDP up to 130 W The server boards do not support previous generations of the Intel Xeon Processors For a complete updated list of supported processors see http support intel com support motherboards server S5520HC On the Support tab look for Compatibility and then Supported Processor List 3 2 1 Processor Population Rules You must populate processors in sequential order Therefore you must populate Processor socket 1 CPU 1 before processor socket 2 CPU 2 When only one processor is installed it must be in the socket labeled CPU1 which is located near the rear edge of the server boa
53. specific Temperature Threshold 01h 01h nc Degraded c Non fatal u c nc Analog Power Supply 2 Temperature PS2 Temperature Processor 1 Status P1 Status Chassis specific All Threshold T t emperature Oth Sensor Specific 6Fh Processor 07h nc Degraded c Non fatal 01 Thermal trip u c nc Analog Trig Offset Processor 2 Status P2 Status Processor 1 Thermal Margin P1 Therm Margin Processor 2 Thermal Margin P2 Therm Margin Processor 1 Thermal Control 96 P1 Therm Ctrl 96 Processor 2 Thermal Control 96 P2 Therm Ctrl 96 Dual processor only Dual processor only Dual processor only Sensor Specific 6Fh Processor 07h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Threshold 01h 01h Temperature 07 Presence OK 01 Thermal trip Fatal u cnc Non fatal u c nc Trig Offset Analog LIEN Trig Offset Non fatal Trig Offset Processor 1 VRD Temp P1 VRD Hot All Digital Discrete 05h Temperature 01h 01 Limit excesdad Trig Offset Processor 2 VRD Temp P2 VRD Hot 158 Dual processor only Digital Discrete 05h Temperature 01h 01 Limit Set Trig Offset Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS Appendix C BMC Sensor Tables Readable Full Sensor Name
54. standards This may limit some functionality for compatibility for example color usage or some keys or key sequences or support of pointing devices 5 3 1 1 Setup Page Layout The setup page layout is sectioned into functional areas Each occupies a specific area of the screen and has dedicated functionality The following table lists and describes each functional area Table 19 BIOS Setup Page Layout Functional Area Description Title Bar The title bar is located at the top of the screen and displays the title of the form page the user is currently viewing It may also display navigational information Setup Item List The Setup Item List is a set of controllable and informational items Each item in the list occupies the left column of the screen A Setup Item may also open a new window with more options for that functionality on the board Item Specific Help Area The Item Specific Help area is located on the right side of the screen and contains help text for the highlighted Setup Item Help information may include the meaning and usage of the item allowable values effects of the options and so forth Keyboard Command Bar The Keyboard Command Bar is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys 5 3 1 2 Entering BIOS Setup To enter the BIOS Setup press the F2 function key during boot time when the OEM or Intel logo displays The
55. 1 Il 1 4 351 110 67 rot 1 1 S A titan 1 1 1 90 126 NOLE FoR r REI ADD ON CARD RETENTION 6 100 1180 2 PLACES 154 94 CPU VA HEATSINK MOUNTING HOLES LI Ve EI ig n 4 311 E 7 150 1 000 181 61 177 80 95 0382 2X2 4 PLACES d A e code 1 1 910 202 44 ln PLATED THROUGH HOLES 1 1 FOR ANCHOR SOLDERING 8 950 227 33 9 395 1238 63 9 945 2x 9 1189 HOLE FOR 252 60 1 065 179 45 8 340 211 84 1 1 r Sdt CPU SOCKET ILM MOUNTING HOLE 4X2 8 PLACES H L L T opm 213 04 Kiem be OD SLI 11 120 10 145 EN E WEATSINK i 1257 68 PUSH PIN RETENTION 10 788 o r 10 150 274 05 11 310 262 44 287 27 11 331 287 80 Wi Ab 2 PLACES 12 300 ftf i 13 0 312 42 CPU Wu HEATSINK MOUNTING HOLES 12 443 520 m 316 05 es s F E P z z am E eo em 09 er oe OS Ed E eun g W I an Salis X Zo gs ER K Nene 72 ou RH Le Lues e EE or oo ven TT E SS Sasa Se Jo sf ef Sen S Figure 4 Mounting Hole Locations 8 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Overview z z CHE EEGEN z 3 wc P e lt ed SS 52 3 258 4 et 7 S 8s Ce Se od O4 T ef m Sw Ef o o aso lt EE e 94 S e S e 8 eS SOLIS 25 0 WE E SE oc 0 000 0 00 1 225 31 12 1 3
56. 10 3 Electromagnetic Compatibility Notices sssseeemeem 139 BCG USA eise uerit EES 139 IGES 003 Canada rote red RERO c Hd HR Fer Metern a 140 Europe CE Declaration of Conformity ssssssssssseeenenneeeeennnenes 140 NGC Sa Pan WEE 140 ed EGET S 140 RRC Korea tct trt rte rrr tet dde Rae EE PETER gree epe e papaver abba etg 141 10 4 Product Ecology Change EU RoH 141 10 5 Product Ecology Change CROoHS s ss sssssssesrnrnesserrrneerererrrrererrrrnrnsererrnn renererien 141 10 6 China Packaging Recycle Marks or GB18455 2001 sess 144 10 7 CA Perchlorate Warning nennen ennemis 144 10 8 End of Life Product Recycling sse 144 Appendix A Integration and Usage Tips eese nennen nennen 145 Appendix B Compatible Intel Server Chassis eese entente tenerent tnnennns 147 Appendix C BMC Sensor Tables essei eese eseeee eene nnne nnnm nana situa nennen 150 Appendix D Platform Specific BMC Appendix eere 160 Appendix E POST Code Diagnostic LED Decoder eene 161 Appendix F POST Error Messages and Handling eere 165 Appendix G Installation Guidelines cesses eeeee eee eene nennen nnne 170 Glossa EE 172 Reference DOCUMENTS Eege 176
57. 1h nc u I c nc Degraded c Non fatal BB 3 3V Voltage Threshold BB 3 3V 02h 01h nc u I c nc Degraded c Non fatal BB 3 3V STBY Voltage Threshold BB 3 3V STBY 02h 01h nc u I c nc Degraded c Non fatal BB 3 3V Vbat Voltage Threshold BB 3 3V Vbat 02h 01h nc u I c nc Degraded c Non fatal BB 5 0V Voltage Threshold BB 5 0V 02h 01h 154 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS Appendix C BMC Sensor Tables Readable Full Sensor Name Platform Event Reading Event Offset Contrib To Assert De Sensor name in SDR SE Applicability SCHEER Type Triggers System Status assert Value Offs ets nc u c nc Degraded Analog c Non fatal BB 5 0V STBY Voltage Threshold BB 5 0V STBY 02h 01h nc u I c nc Degraded c Non fatal BB 12 0V Voltage Threshold BB 12 0V 02h 01h nc u I c nc Degraded c Non fatal BB 12 0V BB 12 0V Voltage Threshold 02h Oth nc Temperature Threshold ing Degraded oth 01h c Non fatal All All Temperature Threshold ee All p u I c nc Degraded 01h 01h c Non fatal Baseboard Temperature Baseboard Temp IOH Thermal Margin IOH Therm Margin Processor 1 Memory Thermal Margin Mem P1 Thrm Mrgn Temperature Threshold 01h 01h Temperature Threshold 01h 01h Dual Temperature Threshold Thermal Margin processor 01h 0
58. 1h Mem P2 Thrm Mrgn only ka eun Sensors 30h 39h Chassis Threshold I c nc Degraded e j specific 01h c Non fatal2 Revision 1 8 155 Intel order number E39529 013 Processor 2 Memory 1Ch 20h Front Panel Temperature 21h Front Panel Temp Intel Server Boards S5520HC SSSOOHCV and SS520HCT TPS Readable Event Reading Event Offset Contrib To Assert De Rearm Stand Triggers System Status assert Value Offs by ets Generic 01 Device Triggered Auto 08h inserted Offset Appendix C BMC Sensor Tables Platform Applicability Full Sensor Name Sensor name in SDR Sensor H Sensor Type Chassis specific Fan Present Sensors Fan x Present 40h 45h Fan Redundancy Fan Redundancy 56 RoB Chassis specific Generic Intel order number E39529 013 00 Fully redundant 01 Redundancy lost Degraded 02 Redundancy degraded Degraded 03 Non redundant Sufficient Degraded resources Transition from redundant OBh 04 Non e ie Trig Offset redundant Sufficient Degraded resources Transition from insufficient 05 Non redundant Non fatal insufficient resources 06 Non Redundant degraded from Degraded fully redundant Revision 1 8 Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS Appendix C BMC Sensor Tables Readable Full Sensor Name Snort Platform Ea Tg Event Reading Event Offset Contrib To Assert De Rearm Stand Sensor name in SD
59. 2 4 Web Services for Management WS MAN The BMC firmware supports the Web Services for Management WS MAN specification version 1 0 4 2 4 1 Profiles The BMC supports the following DMTF profiles for WS MAN e Base Server Profile e Fan Profile e Physical Asset Profile e Power State Management Profile e Profile Registration Profile e Record Log Profile e Sensor Profile e Software Inventory Profile FW Version Note WS MAN features will be made available after production launch Revision 1 8 65 Intel order number E39529 013 Platform Management Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 4 2 5 Embedded Web server The BMC provides an embedded web server for out of band management User authentication is handled by IPMI user names and passwords Base functionality for the embedded web server includes e Power Control e Sensor Reading e SEL Reading e KVM Media Redirection Only available when the Intel RMM3 is present e IPMI User Management The web server is available on all enabled LAN channels If a LAN channel is enabled properly configured and accessible the web server is available The web server may be contacted via HTTP or HTTPS A user can modify the SSL certificates using the web server You cannot change the web server s port 80 81 For security reasons you cannot use the null user user 1 to access the web server The session inactivity timeout for the embedded web server is 30 minutes
60. 39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS BIOS Setup Utility Setup Item Options Comments Size Information only Displays the total physical memory installed in the system in MB or GB The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs Quiet Boot Enabled Enabled Display the logo screen Disabled during POST Disabled Display the diagnostic screen during POST POST Error Pause Enabled Enabled Go to the Error If enabled the POST Error Pause Disabled Manager for critical POST errors option takes the system to the error Disabled Attempt to boot and do manager to review the errors when not go to the Error Manager for major errors occur Minor and fatal critical POST errors error displays are not affected by this setting System Date Day of week System Date has configurable MM DD YYYY fields for Month Day and Year Use Enter or Tab key to select the next field Use or key to modify the selected field System Time HH MM SS System Time has configurable Revision 1 8 fields for Hours Minutes and Seconds Hours are in 24 hour format Use Enter or Tab key to select the next field Use or key to modify the selected field Intel order number E39529 013 77 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 5 3 2 2 Advanced Screen The Advanced screen provid
61. 4 from the default operating position covering pins 1 and 2 to the password clear position covering pins 2 and 3 Close the server chassis Power up the server and then press F2 to enter the BIOS menu to check if the password is cleared Power down the server Open the chassis and move the jumper back to its default position covering pins 1 and Close the server chassis Power up the server The password is now cleared and you can reset it by going into the BIOS setup Revision 1 8 119 Intel order number E39529 013 Jumper Blocks Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 7 2 Force BMC Update Procedure When performing a standard BMC firmware update procedure the update utility places the BMC into an update mode allowing the firmware to load safely onto the flash device In the unlikely event the BMC firmware update process fails due to the BMC not being in the proper update state the server boards provide a Force BMC Update jumper J1H1 that forces the BMC into the proper update state In the event the standard BMC firmware update process fails complete the following procedure Power down and remove the AC power cord Open the server chassis See your server chassis documentation for instructions Move the jumper J1H1 from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 Close the server chassis Reconnect the AC power cord and power up th
62. 5500HCV and S5520HCT TPS Intel Light Guided Diagnostics e By issuing the appropriate hex IPMI Chassis Identify value the ID LED will either blink blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issue to turn it off The bi color green amber System Status LED operates as follows Table 70 System Status LED System degraded Non critical temperature threshold asserted Non critical voltage threshold asserted Non critical fan threshold asserted Fan redundancy lost sufficient system cooling maintained This does not apply to non redundant systems Power supply predictive failure Power supply redundancy lost This does not apply to non redundant systems Correctable errors over a threshold of 10 and migrating to a mirrored DIMM memory mirroring This indicates the user no longer has spare DIMMs indicating a redundancy lost condition The corresponding DIMM LED should light up Non fatal alarm system is likely to fail Critical temperature threshold asserted J CATERR asserted Critical voltage threshold asserted VRD hot asserted SMI Timeout asserted Fatal alarm system has failed or shut down CPU Missing Thermal Trip asserted Non recoverable temperature threshold asserted Non recoverable voltage threshold asserted Amber Solid on Critical Power fault Power Control Failure recoverable Fan redundancy lost insufficie
63. 89 35 29 6 445 163 101 6 815 174 631 ZT raaa a 4 o wan iun nl un an 9 ememnemuoueu a S ONNM eT ON To EE Figure 5 Major Connector Pin 1 Locations 1 of 2 Revision 1 8 9 Intel order number E39529 013 Intel Server Boards S5520HC 5500HCV and S5520HCT TPS Overview m m Y ooor om EI Seat oH 29 eS of e Le ON Ee Do a owo os Ty o o am am IRCH CEA 092 3 pa 280 LIRE 2S1 01 h0 692 Z ol 171921 l 082 0 0s pi2 Chr 215 90 a P EI 7 346 8 500 TD 66 12 ec eg ir a EN RI 18 00 0 0s1 0 000 0 d DIE te eu EIN j Een Een vue P SU 0L 21 j lec i 0050 orb 0 ee vil 80 08 21 d 3950 MH Sis 0 mses o SG Gu z z z 3 fe M SE ae e mo es wo 0901 ox E E E uw eT o ovor ZS m S93 o o n o n Sr 8 3 amp det Se Ze 060 5 Gm Ss Se Ce Sr Qo Z en Res el2s2 om CS TS d a 2 52 27 FR T7 2 S aS See Se o et Ss so o oc M v Z0 CMS Revision 1 8 2 ot 2 IONS Intel order number E39529 013 6 Major Connector Pin 1 Locat igure F 10 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Overview MEMORY VR HEATSINK KEEPOUT AREA MAX COMPONENT HEIGHT 0 029 INCHES 2 PLACES COMPONENT HEIGHT RESTRICTIO 0 185 MAX MEMORY CR HS SIDE FIN KEEPOUT AREA MAX COMPONENT HEIGHT 0 295 INCHS 2PLACES e
64. CT TPS System pre requirements Processor B1 or later stepping Intel Xeon Processor 5600 Series Server Board Intel Server Board S5520HCT PBA version E80888 553 or later Memory At least 1 GB memory installed Intel TXT Setup 1 Enable TPM module Go to BIOS setup Menu page Security Tab set administrator password fiptio Setup Utility Copyright C 2009 American Megatrends Inc UNEA Security SWS MEU Ce ae EUG EET Set Administrator Password set User Password Version 1 23 1114 Copyright C 2009 American Megatrends Inc Figure 22 Setting Administrator password in BIOS 2 After administrator password is setup press F10 to save and exit BIOS setup 3 System will automatically reboot go to BIOS setup Menu page Security Tab set TPM Administrative Control as Turn ON press F10 to save and exit BIOS setup 56 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Functional Architecture Aptio Setup Utility Copyright C 2009 American Megatrends Inc DERE UE SZ Security EI Management Boot Options Boot Manager Enables s TPM Password Disabled TPM A TPM Administrative Control No Operation Turn ON Turn OFF Clear Ownership Version 1 23 1114 Copyright C 2009 American Megatrends Inc Figure 23 Activating TPM 4 Go to BIOS setup Menu Security Tab TPM State should be Enabled amp Activated Revision 1 8 57 In
65. CT TPS Appendix B Compatible Intel Server Chassis CPU Fan Air Flow Air Flow saae C L IL LI oooooo oe op JULI Figure 62 Active Processor Heatsink Installation Requirement Revision 1 8 149 Intel order number E39529 013 Appendix C BMC Sensor Tables Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Appendix C BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type name supported thresholds assertion and de assertion information and a brief description of the sensor purpose See the ntelligent Plattorm Management Interface Specification Version 2 0 for sensor and event reading type table information 150 Sensor Type The Sensor Type references the values in the sensor type codes table in the ntelligent Platform Management Interface Specification Version 2 0 for sensor and event reading type table information Event Reading Type The event reading type references values from the event reading type code ranges and the generic event reading type code tables in the ntelligent Platform Management Interface Specification Second Generation v2 0 Digital sensors are
66. D Module AXX4SASMOD provides four SAS connectors that support up to four hard drives with a non expander backplane or up to eight hard drives with an expander backplane The Intel SAS Entry RAID Module AXX4SASMOD also provides a SGPIO Serial General Purpose Input Output connector and a SCSI Enclosure Services SES connector for backplane drive LED control Warning Either the SGPIO or the SES connector supports backplane drive LED control Do not connect both SGPIO and SES connectors at the same time Standoff Mounting SES Holes Software RAID 5 Key Header SAS Module ts Connector SAS 0 Figure 18 Intel SAS Entry RAID Module AXX4SASMOD Component and Connector Layout 44 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Functional Architecture B i gt UART E conn 4pin Software RAID 5 Activation Key header SAS Module Connector 50pin RST PWRGD PS SGPIO FM SAS RESET N conn 4pin SW_RAID_Mode gt PCI Express x4 LED HDD ACT SES i 4 SAS PRSNT conn 3pin Figure 19 Intel SAS Entry RAID Module AXX4SASMOD Functional Block Diagram 3 6 1 SAS RAID Support The BIOS Setup Utility provides drive configuration options on the Advanced Mass Storage Controller Configuration setup page for the Intel SAS Entry RAID Module AXX4SASMOD some of which affect the ability to configure RAID The Intel SAS Entry
67. Devices number of USB devices in the system USB Controller Enabled Enabled All onboard USB controllers are turned on and Disabled accessible by the OS Disabled All onboard USB controllers are turned off and inaccessible by the OS Legacy USB Enabled USB device boot support and PS 2 emulation for USB Grayed out if the USB Controller is Support Disabled keyboard and USB mouse devices disabled Auto Auto Legacy USB support is enabled if a USB device is attached Port 60 64 Enabled UO port 60h 64h emulation support Grayed out if the USB Controller is Emulation Disabled Note This may be needed for legacy USB keyboard disabled support when using an OS that is USB unaware Make USB Enabled Exclude USB in Boot Table Grayed out if the USB Controller is Devices Non Disabled Enabled This removes all USB Mass Storage devices disabled Bootable as Boot options Disabled This allows all USB Mass Storage devices as Boot options Device Reset USB Mass Storage device Start Unit command timeout Grayed out if the USB Controller is timeout Setting to a larger value provides more time for a mass disabled storage device to be ready if needed One line for each Auto Auto USB devices less than 530 MB are emulated as Hidden if no USB Mass storage mass storage Floppy floppies devices are installed device in system Forced FDD Forced FDD HDD formatted drive are emulated as a Grayed out if the USB Controller is Hard Disk FDD
68. Diagnostics on field replaceable units e Support for Intel System Management Software 3 1 and beyond e Support for Intel Intelligent Power Node Manager Need PMBus compliant power supply BIOS Flash e Winbond W25X64 Compatible Intel e Intel Server Chassis SC5650DP Server Chassis e Intel Server Chassis SC5650BRP PMBus compliant Power Supply e Intel Server Chassis SC5600Base e Intel Server Chassis SC5600BRP PMBus compliant Power Supply e Intel Server Chassis SC5600LX PMBus compliant Power Supply The PCI Express Gen 1 slot x8 Mechanically x4 Electrically is not available when the SAS module slot is in use and vice versa The Trusted Platform Module is only availabe in 5520HCT 4 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Overview Server Board Layout Figure 2 Intel Server Board S5500HCV 2 1 1 Server Board Connector and Component Layout The following figure shows the layout of the server board Each connector and major component is identified by a number or letter and a description is given below the figure Revision 1 8 5 Intel order number E39529 013 Overview Intel Server Boards S5520HC 5500HCV and S5520HCT TPS
69. Disabled Hardware Prefetcher Hardware Prefetcher is a speculative prefetch unit within the processor s Note Modifying this setting may affect system performance Enabled Cache lines are fetched in pairs even line odd line Disabled Only the current cache line required is fetched Note Modifying this setting may affect system performance Allows processors to increase the I O performance by placing data from I O devices directly into the processor cache Enabled Disabled Adjacent Cache Line Prefetch Enabled Disabled Direct Cache Access DCA Revision 1 8 Intel order number E39529 013 BIOS Setup Utility Comments Only appears when Intel Virtualization Technology for Directed I O is enabled Only appears when Intel Virtualization Technology for Directed I O is enabled Only appears when Intel Virtualization Technology for Directed I O is enabled Only appears when Intel Virtualization Technology for Directed I O is enabled 8 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 5 3 2 2 2 Memory Screen The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed This screen also allows the user to open the Configure Memory RAS and Performance screen To access this screen from the Main screen select Advanced Memory Advanced Memory Configuration Total Memory Effective Memory Current Configura
70. Disabled and Deactivated A disabled TPM device will not execute commands that use TPM functions and TPM security operations will not be available An enabled and deactivated TPM is in the same state as a disabled TPM except setting of TPM ownership is allowed if not present already An enabled and activated TPM executes all commands that use TPM functions and TPM security operations will be available TPM No Operation No Operation No changes to current Administrative Turn On state Control Turn Off Turn On Enables and activates TPM Clear Ownership Turn Off Disables and deactivates TPM Clear Ownership Removes the TPM ownership authentication and returns the TPM to a factory default state Note The BIOS setting returns to No Operation on every boot cycle by default 54 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture 3 13 3 Intel Trusted Execution Technology Intel TXT 3 13 3 1 Overview Intel Trusted Execution Technology Intel TXT for safer computing formerly code named LaGrande Technology is a versatile set of hardware extensions to Intel processors and chipsets that enhance the platform with security capabilities such as measured launch and protected execution Intel TXT provides hardware based mechanisms that help protect against software based attacks and protects the confidentiality and integrity of data stored or created
71. EI LG GS DEE E use USB xt DVD Fioppy USB x2 conn Ange USB xi i coool USB elejelele Front Panel USB x2 conn UEA 550 Header x1 Figure 14 Intel Server Board S5500HCV Functional Block Diagram Revision 1 8 19 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC 5500HCV and S5520HCT TPS 3 1 Intel 5520 and 5500 1 0 Hub IOH The Intel 5520 and 5500 I O Hub IOH in the Intel Server Boards S5520HC S5500HCV and S5520HCT provide a connection point between various I O components and Intel QPI based processors which includes the following core platform functions e Intel QPI link interface for the processor subsystem e PCI Express Ports e Enterprise South Bridge Interface ESI for connecting Intel ICH10R e Manageability Engine ME e Controller Link CL e SMBus Interface e Intel Virtualization Technology for Directed I O Intel VT d The following table shows the high level features of the Intel 5520 and 5500 IOH Table 1 IOH High Level Summary IOH SKU Intel QPI Ports Supported Processor PCI Express Manageability Lanes 5520 2 Intel Xeon Processor 5500 Series 36 Intel Intelligent Power Node Manager 5500 2 Intel Xeon Processor 5500 Series 24 Intel Intelligent Power Node Manager 3 1 1 Intel QuickPath Interconnect The Intel Server Boards S5520HC S5500HCV and S5520HCT provide two full width cache coherent link based Intel
72. HCT TPS List of Figures Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Revision 1 8 Setup Utility Console Redirection Screen Display 96 Setup Utility Server Management System Information Screen Display 98 Setup Utility Boot Options Screen Display 99 Setup Utility Add New Boot Option Screen Display 101 Setup Utility Delete Boot Option Screen Display 102 Setup Utility Hard Disk Order Screen Display 102 Setup Utility CDROM Order Screen Display 103 Setup Utility Floppy Order Screen Display 103 Setup Utility Network Device Order Screen Display 104 Setup Utility BEV Device Order Screen Display 104 Setup Utility Boot Manager Screen Display 105 Setup Utility Error Manager Screen Display 106 Setup Utility Exit Screen Display 106 Jumper Blocks J1E2 J1E4 J1E5 J1E6 JH 118 5 volt Stand by Status LED Location 122 Fan Fault LEDS Location ect aree ter eicere dede cette deri ee nea 123 System Status LED Location 124 DIMM Fault LED s Location 126 POST Code Diagnostic LED Locations esseeseeeeeeeeerett tete tertrtrttrttrnrteneerrrernee rne 127 Power Distribution Block Diagram sssssssss
73. I device with location number Bus number Device number and Function number using PCI map dump from the system generating the PCI device SEL event There are multiple means to dump the PCI map For example read the location number from the device general property page in device manager under Microsoft Windows Operating Systems or type PCI and execute under the server board EFI shell Example of deciding the PCI device that generates SEL event entry 1 Provided a PCI device SEL event entry in Hex code reads the ED2 as 01 and ED3 as 00 that is the PCI device has bus number 1 device number 0 and function number 0 2 The PCI dump from this system indicates the device with bus number 1 device number 0 and function number 0 as Network Controller Ethernet controller and there is no add in NIC inserted thus the PCI device generate the SEL event entry is onboard NIC controller Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC SSSOOHCV and 5520HCT TPS Appendix B Compatible Intel Server Chassis Appendix B Compatible Intel Server Chassis Refer to the following table for the compatible Intel Server Chassis of Intel Server Boards S5520HC S5500HCV and S5520HCT Passive tower processor heatsink s product code FXXRGTHSINK is required when installing the Intel Server Board S5520HC or S5500HCV in the Intel Server Chassis SC5600LX Active processor heatsink s is required when installing the I
74. Intel Server Board S5500HCV are PCI PCI Express Gen1 and PCI Express Gen2 with five independent PCI bus segments PCI Express Gen and Gen2 are dual simplex point to point serial differential low voltage interconnects A PCI Express topology can contain a Host Bridge and several endpoints I O devices The signaling bit rate is 2 5 Gb s one direction per lane for Gen1 and 5 0 Gb s one direction per lane for Gen2 Each port consists of a transmitter and receiver pair A link between the ports of two devices is a collection of lanes x1 x2 x4 x8 x16 and so forth All lanes within a port must transmit data using the same frequency The PCI buses comply with the PC Local Bus Specification Revision 2 3 The following tables list the characteristics of the PCI bus segments Details about each bus segment follow the tables Table 8 Intel Server Board S5520HC PCI Bus Segment Characteristics PCI Bus Segment PCI O Card Slots PCI32 5V p bit FEN MHz p PCI Slot 1 ICH10R PE1 PE2 PE3 E a E x4 PCI Express Gen1 throughput to Slot DEA Express 2 x8 mechanically and Intel SAS Entry ICH10R PCI Gen1 RAID Module AXX4SASMOD slot Express Ports Default to Slot 2 and switch to SAS Module slot when Intel SAS Entry RAID Module AXX4SASMOD is detected This PCI Express Gent slot is not available when the SAS module slot is in use and vice versa PE5 2 5 Gb s PCI x1 PCI Express Gen1 throughput to ICH10R PCI Express onboard Integr
75. Manager ERROR CODE SEVERITY INSTANCE Figure 51 Setup Utility Error Manager Screen Display Table 44 Setup Utility Error Manager Screen Fields Setup Item Displays System Errors Information only Displays errors that occurred during POST 5 3 2 9 Exit Screen The Exit screen allows the user to choose whether to save or discard the configuration changes made on the other screens It also allows the user to restore the server to the factory defaults or to save or restore them to the set of user defined default values If Load Default Values is selected the factory default settings noted in bold in the tables in this chapter are applied If Load User Default Values is selected the system is restored to previously saved user defined default values Error Manager Save Changes and Exit Discard Changes and Exit Save Changes Discard Changes Load Default Values Save as User Default Values Load User Default Values Figure 52 Setup Utility Exit Screen Display 106 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS BIOS Setup Utility Table 45 Setup Utility Exit Screen Fields Help Text Save Changes and Exit Exit the BIOS Setup utility after saving changes User prompted for confirmation only if The system reboots if required any of the setup fields were modified The F10 key can also be used Discard Changes and Exit the BIOS Setup uti
76. Ms run at 800MHz whe two RDIMMs either or both are SEKR 2 Y N TM sony Quad Rank RDIMMs are installed in the same channel All UDIMMs run at the fastest UDIMM common frequency of processo w or w o 1 Y Y Y 1N SR or DR IMCs and installed memory ECC 800MHz 1066MHz or 1333MHz UDIMM All UDIMMs run at 800MHz or Wi orwio 2 y Y N 2N SR or DR 1066MHz when two UDIMMs Single or Dual Rank are ECC d installed in the same channel 1N One clock cycle for the DRAM commands arrive at the DIMMs to execute 2N Two clock cycles for the DRAM commands arrive at the DIMMs to execute Revision 1 8 Intel order number E39529 013 ER Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 3 34 Publishing System Memory e The BIOS displays the Total Memory of the system during POST if the Quiet Boot is disabled in the BIOS Setup This is the total size of memory discovered by the BIOS during POST and is the sum of the individual sizes of installed DDR3 DIMMs in the system e The BIOS also provides the total memory of the system in the BIOS setup Main page and Advanced Memory Configuration Page This total is the same as the amount described by the previous bullet e The BIOS displays the Effective Memory of the system in the BIOS Setup Advanced Memory Configuration Page The term Effective Memory refers to the total size of all active DDR3 DIMMs not disabled
77. OS Setup SATA Mode Option on Advanced Mass Storage Controller Configuration Screen 40 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Functional Architecture 3 4 2 USB 2 0 Support The USB controller functionality integrated into the ICH10R provides the server boards with an interface for up to ten USB 2 0 ports All ports are high speed full speed and low speed capable Four external connectors are located on the back edge of the server boards One internal 2x5 header J1D1 is provided capable of supporting two optional USB 2 0 ports One internal 2x5 header J1D2 is provided for Intel Server or Workstation chassis front panel USB ports capable of supporting two optional USB 2 0 ports One internal USB port type A connector J1H2 is provided to support the installation of a USB device inside the server chassis One internal low profile 2x5 header J2D2 is provided to support a low profile USB Solid State Drive Note Each USB port supports a maximum 500 mA current Only supports up to eight USB ports to draw maximum current concurrently Revision 1 8 4 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 3 5 PCI Subsystem The primary UO buses for the Intel Server Board S5520HC are PCI PCI Express Gent and PCI Express Gen2 with six independent PCI bus segments The primary I O buses for the
78. OS provides data to the BMC telling it which fan profile the platform is set up for Acoustics Mode or Performance Mode The BIOS uses the parameters retrieved from the thermal sensor data records SDR fan profile setting from BIOS Setup and altitude setting from the BIOS Setup to configure the system for memory throttling and fan speed control If the 68 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCYV and S5520HCT TPS Platform Management BIOS fails to get the Thermal SDRs then it uses the Memory Reference Code MRC default settings for the memory throttling settings The F2 BIOS Setup Utility provides options to set the fan profile or operating mode the platform will operate under Each operating mode has a predefined profile for which specific platform targets are configured which in turn determines how the system fans operate to meet those targets Platform profile targets are determined by which type of platform is selected when running the FRUSDR utility and by the BIOS settings configured using the F2 BIOS Setup 4 3 2 2 1 Fan Domains System fan speeds are controlled through pulse width modulation PWM signals which are driven separately for each domain by integrated PWM hardware Fan speed is changed by adjusting the duty cycle which is the percentage of time the signal is driven high in each pulse Refer to Appendix D for system specific fan domains Table 18 S5520HC S5500HCV and
79. OUT ZONE COPPER PAD ON SURFACE 4X2 8 PLACES 40 236 CPU HEATSING MOUTNIGN ROLE 16 00 BOARD ROUNTING KEEP QUT ZONE 4X2 8 PLACES HEATSINK RETENTION MODULE TOUCH AREA WO COMPONENT ZONE 8 PLACES Figure 7 Primary Side Keep out Zone 1 of 2 Revision 1 8 Intel order number E39529 013 Overview Intel Server Boards S5520HC 5500HCV and S5520HCT TPS BARE DIE HEATSINK WIRE CLIP AREA MAX COMPONENT HEIGHT 0 078 2MM PLATED AREA NO COMPONENT FOR ANCHORS SOLDERING BARE DIE HEATSINK ANCHOR SOLDERING AREA M NO COMPONENT ALLOWED DETAIL A SCALE 4 000 Figure 8 Primary Side Keep out Zone 2 of 2 12 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Overview o Oo o o o H H o0 o 1 o o t H d j H H 4 H 4 H i H 4 Max component height 0 0 mil H n 4 H H LG d o H H 8 d P i H G d R o o g m H Ho go OF i 4 D i i H Beer d CH n tA i H Hen teh er ter ve 5 H ox component height 0 0 mil A BENE use e o f d di 1j ez GM MCA FC i j Ao l j o o BN G d e Mox component height 50 mil o o g o ox componen height 250 mil 4 9 places 9 Max component height 83 mil Mor component height 472 mil 8 o S Lo o 4 j EO O0 o o PSAS Mox component height 4T2mil Oo o o d Wm vert D NN D ox component height 0 0 mil Figure 9 Primary Side Air Duct Keep
80. Profile USB Connector for Solid State Drive J2D2 116 Internal Type A USB Port Pin out UH 116 SSI 4 pin Fan Header Pin out J7K1 J9A2 JOAN 117 SSI 6 pin Fan Header Pin out J1K1 J1K2 J1K4 JK 117 Server Board Jumpers J1E6 J1E2 J1E4 J1E5 JH 118 System Status EED eite ce d cb ie d eet eto Po Redde oed bae 125 Server Board Design Specifications ccccccecceeeeeeeeeeeeeeeeeeeeeeeeeeeeseeceeeeeeeeeeeeaea 128 MTBEF Estimate eere e ad eS EEN 129 Intel Xeon Processor Dual Processor TDP Guidelines sese 131 670 W Load Ratings ten iuge rt e EE EENEG 131 Voltage Regulation Limits eene 132 Transient Load Requirements eene ener 133 Capacitive Loading Conditions 133 Ripple and Noise eren enn nemenen nenne nnt rtr trn nnn teretes nnns nnne 133 Output Voltage Timing 134 xi Intel order number E39529 013 List of Tables Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 xii Turm On Off TIMING EE 135 Compatible Chassis Heatsink Matrix ssessssesssssesseeeeeenne nennen 147 Integrated BMC Core Sensors nennen 152 Platform Specific BMC Features nnne 160 POST Progress Code LED Example nennen 161 POST Codes and Messages 162 POST Error Messages and Handimg rnern renn 166 POST Error Beep Codes eise EENS 169 BMG Beep Mee 169 Revision 1 8 Intel o
81. QuickPath Interconnect interfaces from Intel 5520 and 5500 IOH for connecting Intel QPI based processors The two Intel QPI link interfaces support full width communication only and have the following main features e Packetized protocol with 18 data protocol bits and 2 CRC bits per link per direction Supporting 4 8 GT s 5 86 GT s and 6 4 GT s e Fully coherent write cache with inbound write combining e Read Current command support e Support for 64 byte cache line size 3 1 2 PCI Express Ports The Intel 5520 IOH is capable of interfacing with up to 36 PCI Express Gen lanes which support devices with the following link width x16 x8 x4 x2 and x1 The Intel 5500 IOH is capable of interfacing with up to 24 PCI Express Gen2 lanes which support devices with the following link width x16 x8 x4 x2 and x1 All ports support PCI Express Gen1 and Gen2 transfer rates For a detailed PCI Express Slots definition in the Intel Server Boards S5520HC S5500HCV and S5520HCT see 3 5 PCI Subsystem 20 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture 3 1 3 Enterprise South Bridge Interface ESI One x4 ESI link interface supporting PCI Express Gen1 2 5 Gbps transfer rate for connecting Intel ICH10R in the Intel Server Boards S5520HC S5500HCV and S5520HCT 3 1 4 Manageability Engine ME An embedded ARC controller is within the IOH
82. R Applicability yp Triggers System Status assert Value Offs by ets 07 Redundant degraded from Degraded non redundant 01 Failure Degraded 02 Predictive P Supply 1 Stat ps 9 bk upply 1 Status Ed Gees Specific Failure i Trig Offset A X tatus p 6Fh 03 A C lost Degraded 06 Configuration OK error 01 Failure Degraded 02 Predictive Power Supply 2 Status Chassis Sensor Failure Degraded l PS2 S specific Specific Trig Offset f Ge S 6Fh 03 A C lost Degraded 06 Configuration OK error Power Supply 1 nc AC Power Input Hors SL Bieden u c nc Degraded PS1 Power In c Non fatal Power Supply 2 i nc AC Power Input pisa POM chos u cnc Degraded PS2 Power In c Non fatal Power Supply 1 12V 96 of Maximum Current Output yh u c nc Degraded fi PS1 Curr Out Lacu Ger SCH c Non fatal Power Supply 2 12V of nc Maximum Current Output Se e boca u c nc Degraded PS2 Curr Out c Non fatal Chassis Current Threshold bd Revision 1 8 157 Intel order number E39529 013 Appendix C BMC Sensor Tables Full Sensor Name Sensor name in SDR Sensor Platform Applicability Sensor Type Type Event Reading Event Offset Intel Server Boards S5520HC SSSOOHCV and S5520HCT TPS Readable Assert De assert Contrib To Triggers System Status Value Offs ets Power Supply 1 Temperature PS1 Temperature Chassis
83. S5520HCT Fan Domain Table Fan Domain Onboard Fan Header Fan Domain 0 CPU 1 Fan CPU 2 Fan Fan Domain 1 System Fan 5 Fan Domain 2 System Fan 1 System Fan 2 Fan Domain 3 System Fan 3 System Fan 4 4 3 2 3 Configuring the Fan Profile Using the BIOS Setup Utility The BIOS uses options set in the F2 BIOS Setup Utility to determine what fan profile the system should operate under These options include THROTTLING MODE ALTITUDE and SET FAN PROFILE Refer to Section 5 3 2 2 7 System Acoustic and Performance Configuration for details of the BIOS options The ALTITUDE option is used to determine appropriate memory performance settings based on the different cooling capability at different altitudes At high altitude memory performance must be reduced to compensate for thinner air Be advised selecting an Altitude option to a setting that does not meet the operating altitude of the server may limit the system fans ability to provide adequate cooling to the memory If the air flow is not sufficient to meet the needs of the server even after throttling has occurred the system may shut down due to excessive platform thermals By default the Altitude option is set to 301 m 900 m which is believed to cover the majority of the operating altitudes for these server platforms You can set the SET FAN PROFILE option to either the Performance mode Default or Acoustics mode Refer to th
84. SROMBSASMR AXXROMBSASMR provides RAID 0 1 5 6 and striping capability for spans 10 50 60 USB Drive Support One internal type A USB port with USB 2 0 support that supports a peripheral such as a floppy drive One internal low profile USB port for USB Solid State Drive UO control support External connections DB9 serial port A connection One DH 10 serial port connector optional Two RJ 45 NIC connectors for 10 100 1000 Mb connections Dual GbE through the Intel 82575EB Network Connection Four USB 2 0 ports at the back of the board Internal connections Two 9 pin USB headers each supports two USB 2 0 ports One DH10 serial port B header Six SATA connectors at 1 5 Gbps and 3 Gbps Four SAS connectors at 3 Gbps optional One SSI compliant 24 pin front control panel header Video Support ServerEngines LLC Pilot US with 64 MB DDR2 memory 8 MB allocated to graphics Integrated 2D video controller Dual monitor video mode is supported Two Gigabit through Intel 82575EB PHYs with Intel I O Acceleration Technology 2 support e Trusted Platform Module Revision 1 8 3 Intel order number E39529 013 Overview Intel Server Boards S5520HC 5500HCV and S5520HCT TPS Server Management e Onboard ServerEngines LLC Pilot II Controller Integrated Baseboard Management Controller Integrated BMC IPMI 2 0 compliant Integrated Super I O on LPC interface e Support for Intel Remote Management Module 3 e Intel Light Guided
85. Supported DIMM Population under the Dual Processors Configuration N CPU1 Socket Populated CPU2 Socket Populated M A A2 Bl B2 Cl C2 DI D2 El E2 Fl F2 1 1 X N 2 2 X X N 3 2 X X N 4 2 X X N 5 3 X X X N 6 3 X X X N 7 3 X X X N 8 4 X X X X N 9 4 X X X X Y 10 6 X X X X X X Y 11 6 X X X X X X N 12 7 X X X X X X X N 13 8 X X X X X X X X Y 14 8 X X X X X X X X N 15 9 X X X X X X X X X N 16 12 X X X X X X X X X X X X N Table 6 Supported DIMM Population under the Single Processor Configuration N CPU1 Socket Populated CPU2 Socket Empty M Al A2 Bl B2 C1 C2 D1 D2 El E2 Fl F2 1 1 X N 2 2 X X N 3 2 X X Y 4 3 X X X N 5 4 X X X X N 6 4 X X X X Y 7 6 X X X X X X N Note The generic principles and guidelines described in the above sections also apply to the above two tables Revision 1 8 37 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 3 3 11 Memory Error Handling The BIOS classifies memory errors into the following categories Correctable ECC errors This correction could be the result of an ECC correction a successfully retried memory cycle or both Unrecoverable Fatal ECC Errors The ECC engine detects these errors but cannot correct them Address Parity Errors An Address Pa
86. TPM You use this option to clear security settings for a newly initialized system or to clear a system for which the TPM ownership security key was lost 3 13 2 3 Security Screen The Security screen provides fields to enable and set the user and administrative passwords and to lock out the front panel buttons so they cannot be used The Intel Server Board 5520HCT provides TPM settings through the security screen To access this screen from the Main screen select the Security option Revision 1 8 53 Intel order number E39529 013 Functional Architecture Main Advanced Security Administrator Password Status User Password Status Set Administrator Password Set User Password Front Panel Lockout TPM State TPM Administrative Control Figure 21 Setup Utility TPM Configuration Screen Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Server Management Installed Not Installed Installed Not Installed 1234aBcD 1234aBcD Enabled Disabled Boot Options Boot Manager Enabled amp Activated Enabled amp Deactivated Disabled amp Activated Disabled amp Deactivated gt No Operation Turn On Turn Off Clear Ownership Table 16 TPM Setup Utility Security Configuration Screen Fields Setup Item Options Help Text Comments TPM State Enabled and Activated Information only Enabled and Deactivated Shows the current TPM device state Disabled and Activated
87. V and S5520HCT TPS a Mixing of RDIMMs and UDIMMs is not supported Mixing memory type size speed and or rank on this platform has not been validated and is not supported a Mixing memory vendors is not supported on this platform by Intel a Non ECC memory is not supported and has not been validated in a server environment e Both Intel Server Board S5520HC and Intel Server Board S5500HCV support the following DIMM and DRAM technologies a RDIMMs Single Dual and Quad Rank X4orx8 DRAM with 1 Gb and 2 Gb technology no support for 2 Gb DRAM based 2 GB or 4 GB RDIMMs DDR3 1333 Single and Dual Rank only DDR3 1066 and DDR3 800 a UDIMMSs Single and Dual Rank x8 DRAM with 1 Gb or 2 Gb technology DDR3 1333 DDR3 1066 and DDR3 800 3 3 3 Processor Cores QPI Links and DDR3 Channels Frequency Configuration The Intel Xeon 5500 series processor connects to other Intel Xeon 5500 series processors and Intel 5500 5520 IOH through the Intel QPI link interface The frequencies of the processor cores and the QPI links of Intel Xeon 5500 series processor are independent from each other There are no gear ratio requirements for the Intel Xeon Processor 5500 Series Intel 5500 5520 IOH supports 4 8 GT s 5 86 GT s and 6 4 GT s frequencies for the QPI links During QPI initialization the BIOS configures both endpoints of each QPI link to the same supportable speeds for the correct operation During
88. Xecution E nvironment DXE Core not accompanied by a beep code OxE4 Entered EFI driver execution phase DXE OxE5 Started dispatching drivers OxE6 Started connecting drivers DXE Drivers not accompanied by a beep code OxE7 Waiting for user input OxE8 Checking password OxE9 Entering the BIOS Setup OxEA Flash Update OxEE Calling Int 19 One beep unless silent boot is enabled OxEF Unrecoverable Boot failure Runtime Phase EFI Operating System Boot OxF4 Entering the sleep state OxF5 Exiting the sleep state OxF8 Operating system has requested EFI to close boot services ExitBootServices has been called OxF9 Operating system has switched to virtual address mode SetVirtualAddressMap has been called OxFA Operating system has requested the system to reset ResetSystem has been called Pre EFI Initializatio 0x30 n Module PEIM Recovery Crisis recovery has been initiated because of a user request 0x31 Crisis recovery has been initiated by software corrupt flash 0x34 Loading crisis recovery capsule 0x35 Handing off control to the crisis recovery capsule Ox3F Unable to complete crisis recovery 164 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and SS520HCT TPS Appendix E POST Error Messages and Handling Appendix F POST Error Messages and Handling Whenever possible
89. Y Y Y Y 8 System Fan 4 Sensor 34 N N N N Y System Fan 5 Sensor 33 Y Y Y Y N 1 mm System Fan 1 Presence Sensor 40 N N N N Y d D System Fan 2 Presence Sensor 41 N N N N Y 3 B 2 System Fan 3 Presence Sensor 42 N N N N Y System Fan 4 Presence Sensor 43 N N N N Y F3mPOmamo CPU 1 Ej CPU2 CPU 1 Fan CPU 2 CPU 1 Fan CPU 2 Fan CPU 1 Fan CPU 2 N A c an Fan Fan 5 Fan Domain 1 System Fan 5 System Fan 5 System Fan 5 System Fan 5 N A 3 Fan Domain 2 System Fan 1 System Fan 1 System Fan 1 System Fan 1 Pi eas 2 Fan Domain 3 System Fan 3 System Fan 3 System Fan 3 System Fan 3 pni iu p Hot plug Fan Support N N N N Y Fan Redundancy Support N N N N Y Hot Swap HDD Backplane HSC Availability Y Y V Y Y Power Unit Redundancy Support PMBus compliant Power Supply Support N H N id i 160 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS Appendix E POST Code Diagnostic LED Decoder Appendix E POST Code Diagnostic LED Decoder During the system boot process the BIOS executes a number of platform configuration processes each of which is assigned a specific hex POST code number As each configuration routine is started the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board To assist in troubleshooting a system hang during the POST process you can use the Diagnostic LEDs to identify the last POST process executed Each POST code is represented by eight
90. acy Boot mode Only displays when EFI Optimized Boot is enabled Revision 1 8 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS BIOS Setup Utility If all types of bootable devices are installed in the system then the default boot order is CD DVD ROM Floppy Disk Drive Hard Disk Drive PXE Network Device BEV Boot Entry Vector Device EFI Shell and EFI Boot paths ootomv 5 3 2 6 1 Add New Boot Option Screen The Add Boot Option screen allows the user to remove an EFI boot option from the boot order To access this screen from the Main screen select Boot Options Delete Boot Options Boot Options Add New Boot Option Add boot option label Select File system Available File systems Path for boot option Save Figure 43 Setup Utility Add New Boot Option Screen Display Table 36 Setup Utility Add New Boot Option Fields Setup Item Options Help Text Add boot option label Create the label for the new boot option Select File system Select one from list Select one file system from the list provided Enter the path to boot option in the format Path for boot option Save Revision 1 8 path filename efi Save the boot option 101 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 5 3 2 6 2 Delete Boot Option Screen The Delete Boot Option screen allows the user to remove an EFI boot option from the boot o
91. adio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna e Increase the separation between the equipment and the receiver e Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected e Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product Only peripherals computer input output devices terminals printers etc that comply with FCC Class A or B limits may be attached to this computer product Operation with noncompliant peripherals is likely to result in interference to radio and TV reception All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception Revision 1 8 139 Intel order number E39529 013 Regulatory and Certification Information Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS ICES 003 Canada Cet appareil num rique respecte les limites bruits radio lectriques applicables aux appareils num riques de Classe A prescr
92. al property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Server Boards S5520HC S5500HCV and S5520HCT may contain design defects or errors known as errata which may cause the product to deviate from published specifications Refer to the Intel Server Boards S5520HC S5500HCV and S5520HCT Specification Update for published errata Intel Corporation server baseboards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated syst
93. alts during post at a blank screen with the text Unrecoverable fatal error found System will not boot until the error is resolved and Press lt F2 gt to enter setup The POST Error Pause option setting in the BIOS setup does not have any effect with this class of error After entering the BIOS setup the error message displays on the Error Manager screen and an error is logged to the SEL with the error code The system cannot boot unless the error is resolved The user must replace the faulty part and restart the system Revision 1 8 165 Intel order number E39529 013 Appendix E POST Error Messages and Handling Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Table 86 POST Error Messages and Handling i2 cMOSdaeMmenose Pase attempt to reflash the firmware 0140 PCI component encountered a PERR error Pause 0146 0192 Halt 0193 No Pause 0194 Hall 0195 0196 Halt 0197 Halt 0198 Hal O19F 5220 5221 5224 B160 3161 8180 No Pause 8190 8198 8500 ES ES ES Sr No Pause 8500 8520 DIMM Af failed Self Test Esn 8521 DIMM_A2 failed Self Test BI ST 8522 DIMM B1 failed Self Test BIST Pause 852B DIMM F2 failed Self Test BIST 8540 DIMM AT Disabled Pause 8541 DIMM A2 Disabled Pause 166 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and SS520HCT TPS Appendix E POST Error Messages and Handling e542
94. anagement Configuration Screen Fields 95 Table 33 Setup Utility Console Redirection Configuration Fields ssssssss 97 Table 34 Setup Utility Server Management System Information Fields 98 Table 35 Setup Utility Boot Options Screen Fields cccccccceeeececsssseesseeesseesseeeeseeeeeees 100 Table 36 Setup Utility Add New Boot Option Fields nnnnennneeeeeeeeeeeeeeeeeeeeeeerrrrrrrrnnenneeee 101 Table 37 Setup Utility Delete Boot Option Fields eessssseeeeeeeeeeen 102 Table 38 Setup Utility Hard Disk Order Fields 102 X Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS List of Tables Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Revision 1 8 Setup Utility CDROM Order Fields 103 Setup Utility Floppy Order Fields 103 Setup Utility Network Device Order Fields ssesssssseeeeeee 104 Setup Utility BEV Devic
95. annels per processor with two DIMM slots per channel thus supporting up to twelve DIMMs in two processor configuration See Figure 16 for the Intel Server Board 5520HC DIMM slots arrangement The Intel Server Board S5500HCV supports six DDR3 memory channels three channels per processor with two DIMM slots per channel at Channels A B and C and one DIMM slot per channel at Channels D E and F thereby supporting up to nine DIMMs in a two processor configuration See Figure 17 for the Intel Server Board S5500HCV DIMM slots arrangement Revision 1 8 27 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC 5500HCV and S5520HCT TPS CPU 1 Sod E fe sche D Di Al b DIMM A2 A1 B2 B1 C2 C1 DIMM F1 F2 E1 E2 D1D2 Server Board CPU Socket DIMM Identifier Channel Slot A1 Blue Channel A Slot 0 A2 Black Channel A Slot 1 CPU 1 B1 Blue Channel B Slot 0 B2 Black Channel B Slot 1 C1 Blue Channel C Slot 0 e C2 Black Channel C Slot 1 Intel Server Board S5520HC D1 Blue Channel D Slot O D2 Black Channel D Slot 1 E1 Blue Channel E Slot 0 SES E2 Black Channel E Slot 1 F1 Blue Channel F Slot 0 F2 Black Channel F Slot 1 Figure 16 Intel Server Board S5520HC DIMM Slots Arrangement 28 Intel order num
96. ard used and the number of add in cards installed Table 11 PCI Riser Support PCI Express Gen Slot 6 Riser Support One Add in card Two Add in cards Type 1 Riser Card x8 N A Type 2 Riser Card x4 x4 There are no population rules for installing a single add in card in the Type 2 riser card you can install a single add in card in either PCI Express slot Revision 1 8 43 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 3 6 Intel SAS Entry RAID Module AXX4SASMOD Optional Accessory The Intel Server Boards S5520HC S5500HCV and S5520HCT provide a Serial Attached SCSI SAS module slot J2J1 for the installation of an optional Intel SAS Entry RAID Module AXX4SASMOD Once the optional Intel SAS Entry RAID Module AXX4SASMOD is detected the x4 PCI Express links from the ICH10R to Slot 2 x8 mechanically x4 electrically switches to the SAS module slot The Intel SAS Entry RAID Module AXX4SASMOD includes a SAS1064e controller that supports x4 PCI Express link widths and is a single function PCI Express end point device The SAS controller supports the SAS protocol as described in the Serial Attached SCSI Standard version 1 0 and also supports SAS 1 1 features A 32 bit external memory bus off the SAS1064e controller provides an interface for Flash ROM and NVSRAM Non volatile Static Random Access Memory devices The Intel SAS Entry RAI
97. ards EE USB_PN DATALO RORIS Deren dais ine paved W TDATAHUS data line paired with DATAHO USB PP DATAHO Differential data line paired with DATALO Ground A4 O Table 62 External USB Connector Pin out J5A1 J6A1 Signal Name USB OC 5VSB USB PWR Ground Connector Header Locations and Pin outs Two 2x5 connectors on the server boards J1D1 J1D2 provide support for four additional USB ports J1D2 is recommended for front panel USB ports Table 63 Internal USB Connector Pin out J1D1 2 USB PWR45 5V USBpower port5 6 USB ICH P5P CONN USB portbpositivesignal Ground fe i 8 Ground LI egener Table 64 Internal USB Connector Pin out J1D2 2 USB PWR68 5VSB USBpower pot8 6 USB ICH PBP CONN USB port 8 positive signal Ground E 8 Ground J One low profile 2x5 connector J2D2 on the server boards provides an option to support a low profile USB Solid State Drive Revision 1 8 Intel order number E39529 013 115 Connector Header Locations and Pin outs Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Table 65 Pin out of Internal Low Profile USB Connector for Solid State Drive J2D2 2 NC Not Connected 6 Nc NotConnected 8 NC Q NotConneted 9 Ke No pin ke Nopin LED Activity LED The server boards provide one additional Type A USB port J1H2 to suppor
98. ated BMC Express Port Gen1 PE1 PE2 n Gb s PCI x4 PCI Express Gen1 throughput to 5520 IOH PCI Express onboard NIC 82575EB Express Ports Gen1 PE3 PE4 ER Gb S PCI x8 PCI Express Gen2 throughput to Slot 5520 IOH PCI Express 6 x16 mechanically Express Ports Gen2 DER PEG 3 3V x8 40 Gb S PCI x8 PCI Express Gen2 throughput to Slot 5520 IOH PCI Express 5 x8 mechanically Express Ports Gen2 PE7 PE8 3 3 V x8 40 Gb S PCI x8 PCI Express Gen2 throughput to Slot 5520 IOH PCI Express 4 x8 mechanically Express Ports Gen2 PE9 PE10 3 3 V x8 40 Gb S PCI x8 PCI Express Gen2 throughput to Slot 5520 IOH PCI Express 3 x8 mechanically Express Ports Gen2 42 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Functional Architecture Table 9 Intel Server Board S5500HCV PCI Bus Segment Characteristics PCI Bus Segment PCI 1 0 Card Slots PCI32 5V 32 bit 33 MHz PCI PCI Slot 1 ICH10R DEI PE2 PES 10 Gb s PCI x4 PCI Express Gen1 throughput to Slot DEA Express 2 and Intel SAS Entry RAID Module ICH10R PCI Gen1 AXX4SASMOD slot x8 mechanically Express Ports Default to Slot 2 and switch to SAS Module slot when Intel SAS Entry RAID Module AXX4SASMOD is detected This PCI Express Gent slot is not available when the SAS module slot is in use and vice versa PE5 WE 5 Gb s PCI x1 PCI Express Gen throughput to ICH10R PCI Express onboar
99. ation after loss of ms AC 21 N A Tpwok holdup Delay from loss of AC to de assertion of PWOK 20 N A ms Tpson on delay Delay from PSON active to output voltages within 5 400 ms regulation limits Tpson pwok Delay from PSON deactivate to PWOK being de asserted 50 ms Tpwok on Delay from output voltages within regulation limits to PWOK ms 100 500 asserted at turn on Tpwok off Delay from PWOK de asserted to output voltages 3 3 V 5 ms V 1 N A 12 V and 12 V dropping out of regulation limits Tpwok low Duration of PWOK being in the de asserted state during an 100 N A ms off on cycle using AC or the PSON signal Tsb vout Delay from 5 VSB being in regulation to O Ps being in ms 50 1000 regulation at AC turn on T5VSB holdup Time the 5 VSB output voltage stays within regulation after ms 70 N A loss of AC AC Input ur et k T vout holdup l Ta on dia K PWOK am Revision 1 8 TAC on delay l i i E H s j 3i Tsvss holdup i AC turn on off cycle _ Figure 61 Turn On Off Timing Power Supply Signals Intel order number E39529 013 Tpson on delay j PSON turn on off cycle 3 Tpwok ort Tpson pwok 135 Design and Environmental Specifications Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 9 4 9 Residual Voltage Immunity in Stand by Mode The power supply should be immune to any residual v
100. ber E39529 013 Revision 1 8 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Functional Architecture Tn m m q i 4 In f q f QO 3 q d S q i q J D l H F ay a 1 gd eme lOO CPUT Sod oa i ICH10 Yat DIMM A2 A1 B2 B1C2 C1 al IN DIMM Fi E1 D1 Server Board CPU Socket DIMM Identifier Channel Slot 1 Blue Channel A Slot 0 2 Black Channel A Slot 1 CPU 1 1 Blue Channel B Slot 0 Intel She Board 2 Black Channel B Slot 1 S5500HCV C1 Blue Channel C Slot 0 2 Black Channel C Slot 1 1 Blue Channel D Slot 0 CPU 2 1 Blue Channel E Slot 0 1 Blue Channel F Slot 0 Figure 17 Intel Server Board S5500HCV DIMM Slots Arrangement 3 3 2 Supported Memory e Both Intel Server Board S5520HC and Intel Server Board S5500HCV support 1 5 V DDR3 DIMMs Intel Server Board S5520HC supports up to 12 DIMMs with a maximum of 192GB memory capacity Inte Server Board S5500HCV supports up to 9 DIMMs with a maximum of 144GB memory capacity e Both Intel Server Board S5520HC and Intel Server Board S5500HCV support Registered DDR3 DIMMs RDIMMs and ECC Unbuffered DDR3 DIMMs UDIMMs Revision 1 8 29 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHC
101. board NIC Status LED 51 Table 16 TSetup Utility Security Configuration Screen Eielde 54 Table 17 Basic and Advanced Management Features 63 Table 18 S5520HC SS500HCV and S5520HCT Fan Domain Table ssssssssssesseneeneeeereeeesneeeeeene 69 Table 19 BIOS Setup Page Layout 73 Table 20 BIOS Setup Keyboard Command Bar 74 Table 21 Setup Utility Main Screen Fields 76 Table 22 Setup Utility Advanced Screen Display Fields cccceesceeeceeeeeeeeeteeeeeeeeenaees 78 Table 23 Setup Utility Processor Configuration Screen Fields 0nnsnnnnnnnnennnenineeneeeeeneeeee eee 80 Table 24 Setup Utility Memory Configuration Screen Fields sseeeeseeesessess 83 Table 25 Setup Utility Configure RAS and Performance Screen Fields nnnn0aneeenaeaeeea 84 Table 26 Setup Utility Mass Storage Controller Configuration Screen Fields 86 Table 27 Setup Utility Serial Ports Configuration Screen Fields sssss 87 Table 28 Setup Utility USB Controller Configuration Screen Fields 89 Table 29 Setup Utility PCI Configuration Screen Fields 90 Table 30 Setup Utility System Acoustic and Performance Configuration Screen Fields 92 Table 31 Setup Utility Security Configuration Screen Fields sesssssssss 93 Table 32 Setup Utility Server M
102. boot with pins 2 3 connected The system only boots from EFl bootable recovery media with a recovery BIOS image present J1H1 Force BMC 1 2 BMC Firmware Force Update Mode Disabled Default Update 2 3 BMC Firmware Force Update Mode Enabled 118 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Jumper Blocks 7 1 CMOS Clear and Password Reset Usage Procedure The CMOS Clear J1E6 and Password Reset J1E4 recovery features are designed to achieve the desired operation with minimum system down time The usage procedure for these two features has changed from previous generation Intel server boards The following procedure outlines the new usage model 7 1 1 Oe Et 4e Clearing the CMOS Power down the server and unplug the AC power cord Open the server chassis For instructions see your server chassis documentation Move the jumper J1E6 from the default operating position covering pins 1 and 2 to the reset clear position covering pins 2 and 3 Wait five seconds Move the jumper back to the default position covering pins 1 and 2 Close the server chassis and reconnect the AC power cord Power up the server The CMOS is now cleared and you can reset it by going into the BIOS setup 7 1 2 2 Clearing the Password Power down the server Do not unplug the power cord Open the chassis For instructions see your server chassis documentation Move the jumper J1E
103. by the BIOS The memory operational mode is configurable at the channel level The following two modes are supported Independent Channel Mode and Mirrored Channel Mode The BIOS selects the mode that enables all the installed memory by default Since the Independent Channel Mode enables all the channels simultaneously this mode becomes the default mode of operation When only CPU1 socket is populated Mirrored Channel mode is selected only if the DIMMs are populated to conform to that channel RAS mode If it fails to comply with the population rule then the BIOS configures the CPU1 socket to default to the Independent Channel mode If both CPU sockets are populated and the installed DIMMs are associated with both CPU sockets then Mirrored Channel Mode can only be selected if both the CPU Sockets are populated to conform to that mode If either or both sockets fail to comply with the population rule the BIOS configures both the CPU sockets to default to the Independent Channel mode DIMM parameters matching requirements for Mirrored Channel Mode is local to the CPU socket For example while CPU1 memory channels A B and C have one match of timing technology and size CPU 2 memory channels D E and F can have a different match of the parameters channel RAS still functions The Minimal memory population possible is DIMM AT In this configuration the system operates in the Independent Channel Mode Mirrored Channel Mode is not possible
104. ced to ReturnS The 43 3 V 5 V 12 V1 and 12 V2 are measured at its remote sense signal located at the signal connector Table 75 Voltage Regulation Limits Parameter Tolerance Minimum Nominal Maximum Units 3 3 V 5 5 3 14V 3 30V 3 46V Vrms 5 V 5 5 4 75V 5 00V 5 25V Vrms 12 V1 5 5 11 40V 12 00V 12 60V Vrms 12 V2 5 5 11 40V 12 00V 12 60V Vrms 12 V3 5 5 11 40V 12 00V 12 60V Vrms 12 V4 5 5 11 40V 12 00V 12 60V Vrms 12V 5 9 11 40V 12 00V 13 08V Vrms 5 VSB 5 5 4 75V 5 00V 5 25V Vrms Dynamic Loading The output voltages remain within limits for the step loading and capacitive loading specified in the following table You should test the load transient repetition rate between 50 Hz and 5 kHz at duty cycles ranging from 10 to 90 The load transient repetition rate is only a test specification The A step load may occur anywhere within the minimum load to the maximum load range 132 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Design and Environmental Specifications Table 76 Transient Load Requirements Output A Step Load Size 1 Load Slew Rate Test Capacitive Load 43 3 V TOA 0 25A usec 4700uF 5V TOA 0 25A usec 1000uF 12 V 25A 0 25A usec 4700uF 5 VSB 0 5A 0 25A usec 20uF 1 Step loads on each 12 V output may happen simul
105. cessible through a 9 pin internal DH 10 header You can use a standard DH 10 to DB9 cable to direct serial B to the rear of a chassis The serial B interface follows the standard RS232 pin out as defined in the following table Table 13 Serial B Header Pin out Pin Signal Name Serial Port B Header Pin out DCD DSR RX RTS TX CTS DTR RI GND OO om P N OOo Wow oo D OOOO CO C N OD or amp hM 3 9 Floppy Disk Controller The Intel Server Boards S5520HC S5500HCV and S5520HCT do not support a floppy disk controller interface However the system BIOS recognizes USB floppy devices 3 10 Keyboard and Mouse Support The Intel Server Boards S5520HC S5500HCV and S5520HCT do not support PS 2 interface keyboards and mice However the system BIOS recognizes USB Specification compliant keyboards and mice 3 11 Video Support The Intel Server Boards S5520HC S5500HCV and S5520HCT integrated BMC include a 2D SVGA video controller and 8 MB video memory The 2D SVGA subsystem supports a variety of modes up to 1024 x 768 resolution in 8 16 24 32 bpp It also supports both CRT and LCD monitors with up to an 85 Hz vertical refresh rate Video is accessed using a standard 15 pin VGA connector found on the back edge of the server boards You can disable the onboard video controller using the BIOS Setup Utility or when an add in video card is detected The system
106. d Integrated BMC Express Port Gen1 PE1 PE2 LL Gb s PCI x4 PCI Express Gen2 throughput to 5500 IOH PCI Express onboard NIC 82575EB Express Ports Gen1 PE3 3 3V x4 10 Gb S PCI x4 PCI Express Gen1 throughput to Slot 5500 IOH PCI Express 6 x16 mechanically Express Port Gen2 PE7 PE8 3 3 V x8 40 Gb S PCI x8 PCI Express Gen2 throughput to Slot 5500 IOH PCI Express 4 x8 mechanically Express Ports Gen2 PE9 PE10 3 3 V x8 40 Gb S PCI x8 PCI Express Gen2 throughput to Slot 5500 IOH PCI Express 3 x8 mechanically Express Ports Gen2 3 5 1 PCI Express Riser Slot S5520HC Slot 6 One PCI Express pin is designated as Riser Card Type pin with the definitions noted in the following table for Intel Server Board S5520HC PCI Express slot 6 Table 10 Intel Server Board S5520HC PCI Riser Slot Slot 6 OH PEWIDTH 2 PCI Riser Strap PCI Express Gen Slot 6 Setup PCI Express Pin A50 RVSD Type 1 Riser One x8 PCI Express Slot2 i Type 2 Riser Two x4 PCI Express Slot3 0 1 Maximum power rating of Slot 6 for riser is 75 W provided no card is in slots 3 4 and 5 2 The type 1 riser card must follow the standard PCI Express Adapter pin out and leave pin A50 as a No Connect NC 3 The type 2 riser card must connect the PCI Express pin A50 with a 4 7K ohm resistor to pull up to 3 3 V The following table provides the supported bus throughput for the given riser c
107. d by the system BIOS The KVM video resolutions and refresh rates will always match the values set in the operating system 4 2 2 3 Availability Up to two remote KVM sessions are supported An error displays on the web browser attempting to launch more than two KVM sessions The default inactivity timeout is 30 minutes but you may change the default through the embedded web server Remote KVM activation does not disable the local system keyboard video or mouse Unless the feature is disabled locally remote KVM is not deactivated by local system input KVM sessions will persist across system reset but not across an AC power loss 4 2 3 Media Redirection The embedded web server provides a Java applet to enable remote media redirection You may use this in conjunction with the remote KVM feature or as a standalone applet The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD ROM floppy drive or a USB flash disk as a remote device to the server Once mounted the remote device appears as a local device to the server allowing system administrators or users to boot the server or install software including operating systems copy files update the BIOS and so forth or boot the server from this device The following capabilities are supported e The operation of remotely mounted devices is independent of the local devices on the server Both remote and local devices are usab
108. deo in the BIOS setup the onboard video controller is enabled and is the primary video device The add in video card is allocated resources and considered the secondary video device e The BIOS Setup utility provides options on Advanced PCI Configuration Screen to configure the feature as follows Onboard Video Enabled default Disabled Dual Monitor Video Enabled Shaded if onboard video is set to Disabled Disabled Default 50 Intel order number E39529 013 Revision 1 8 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Functional Architecture 3 12 Network Interface Controller NIC The Intel Server Boards S5520HC S5500HCV and S5520HCT provide dual onboard LAN ports with support for 10 100 1000 Mbps operation The two LAN ports are based on the onboard Intel 82575EB controller which is a single compact component with two fully integrated GbE Media Access Control MAC and Physical Layer PHY ports The Intel 82575EB controller provides a standard IEEE 802 3 Ethernet interface for 1000BASE T 100BASE TX and 10BASE T applications 802 3 802 3u and 802 3ab and is capable of transmitting and receiving data at rates of 1000 Mbps 100 Mbps or 10 Mbps Each network interface controller NIC port provides two LEDs Link activity LED at the left of the connector Indicates network connection when on and transmit receive activity when blinking The speed LED at the r
109. ds Enabled Disabled IT IR RAID Intel ESRTII Setup Item Intel Entry SAS RAID Module Configure Intel Entry SAS RAID Module Help Text Enabled or Disable the Intel SAS Entry RAID Module IT IR RAID Supports Entry Level HW RAID 0 RAID 1 and RAID 1e as well as native SAS pass through mode Intel ESRTII Intel Embedded Server RAID Technology II which supports RAID 0 RAID 1 RAID 10 and RAID 5 mode RAID 5 support requires optional Software RAID 5 Activation Key Comments Unavailable if the SAS Module AXX4SASMOD is not present Unavailable if the SAS Module AXX4SASMOD is disabled or not present Onboard SATA Controller SATA Mode Enabled Disabled Enhanced Compatibility AHCI SW RAID SATA Port 0 lt Not Installed Driv e information gt SATA Port 1 lt Not Installed Driv e information gt SATA Port 2 lt Not Installed Driv e information gt SATA Port 3 lt Not Installed Driv e information gt Onboard Serial ATA SATA controller ENHANCED Supports up to 6 SATA ports with IDE Native Mode COMPATIBILITY Supports up to 4 SATA ports 0 1 2 3 with IDE Legacy mode and 2 SATA ports 4 5 with IDE Native Mode AHCI Supports all SATA ports using the Advanced Host Controller Interface SW RAID Supports configuration of SATA ports for RAID via RAID configuration software No longer displays when the Onboard SATA Controller is disabled Changing this s
110. e Independent Channel mode provides less RAS capability but better DIMM isolation in case of errors Moreover it allows the best interleave mode possible and thereby increases performance and thermal characteristics Adjacent slots on a DDR3 Channel from the Intel Xeon Processor 5500 series do not need matching size and organization in independent channel mode However the speed of the channel is configured to the maximum common speed of the DIMMs The Single Channel mode is established using the Independent Channel mode by populating the DIMM slots from Channel A 3 3 8 3 Mirrored Channel Mode The Mirrored Channel mode is a RAS feature in which two identical images of memory channel data are maintained providing maximum redundancy On the Intel Xeon Processor 5500 series based Intel server boards the mirroring is achieved across channels Active channels hold the primary image and the other channels hold the secondary image of the system memory The integrated memory controller in the Intel Xeon Processor 5500 series alternates between both channels for read transactions Write transactions are issued to both channels under normal circumstances The mirrored image is a redundant copy of the primary image therefore the system can continue to operate despite the presence of sporadic uncorrectable errors resulting in 10096 data recovery In Mirrored Channel mode channel A or D and channel B or E function as the mirrors while Chan
111. e Order Fields 0 cccccceeceeeeeeeeeeeeeeeeneeeeeeeteneeeeeeeeeeees 105 Setup Utility Boot Manager Screen Fields sssssssssessss 105 Setup Utility Error Manager Screen Fields 106 Setup Utility Exit Screen Fields sss 107 Board Connector Matrix sessssssssssssseeseeenee eee en nnne nnne 108 Main Power Connector Pin out OU3K 109 CPU 1 Power Connector Pin out GOOAT cece eeeeeee eerste teneeeeeeeeeseeieeeeeeteteee 109 CPU 2 Power Connector Pin out OORT 110 Power Supply Auxiliary Signal Connector Pin out J9K2 ssssssssssss 110 Intel RMM3 Connector Pin out LC 110 LCP IPMB Header Pin out LI1Gp eene 111 HSBP Header Pin out J1F5 Jh 111 SGPIO Header Pin out IG 111 Front Panel SSI Standard 24 pin Connector Pin out J1B3 sessss 112 VGA Connector Pin out UZAT eene nennen 112 RJ 45 10 100 1000 NIC Connector Pin out J5A1 JoA1 eee eeeeeeeteeeeteee terete 113 SATA SAS Connector Pin out J1E3 J1G1 J1G4 J1G5 J1F 1 J1F4 113 SAS Module Slot Pin out LI 113 External DB9 Serial A Port Pin out U9A7 reee 114 Internal 9 pin Serial B Header Pin out J1B1 ssssssssseeeeeee 114 External USB Connector Pin out J5A1 J6A1 ssssssssssssseeee 115 Internal USB Connector Pin out GO1DI1 115 Internal USB Connector Pin out ID 115 Pin out of Internal Low
112. e following sections for details describing the differences between each mode Changing the fan profile to Acoustics mode may affect system performance The SET FAN PROFILE BIOS option is hidden when CLTT is selected as the THROTTLING MODE option 4 3 2 3 1 Performance Mode Default With the platform running in Performance mode Default several platform control algorithm variables are set to enhance the platform s capability of operating at maximum performance targets for the given system In doing so the platform is programmed with higher fan speeds at lower ambient temperatures This results in a louder acoustic level than is targeted for the given Revision 1 8 69 Intel order number E39529 013 Platform Management Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS platform but the increased airflow of this operating mode greatly reduces both possible memory throttling from occurring and dynamic fan speed changes based on processor utilization 4 3 2 3 2 Acoustics Mode With the platform running in Acoustics mode several platform control algorithm variables are set to ensure acoustic targets are not exceeded for specified Intel platforms In this mode the platform is programmed to set the fans at lower speeds when the processor does not require additional cooling due to high utilization power consumption Memory throttling is used to ensure memory thermal limits are not exceeded Note Fan speed control for a non Intel chassi
113. e g ZIP drive disabled CD ROM This setup screen can show a maximum of eight devices on this Screen If more than eight devices are installed in the system the USB Devices Enabled displays the correct count but only the first eight devices can display here USB 2 0 Enabled Onboard USB ports are enabled to support USB 2 0 Grayed out if the USB Controller is controller Disabled mode disabled Contact your OS vendor regarding OS support of this feature Revision 1 8 89 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 5 3 2 2 6 PCI Screen The PCI Screen allows the user to configure the PCI add in cards onboard NIC controllers and video options To access this screen from the Main screen select Advanced PCI Advanced PCI Configuration Maximize Memory below 4GB Enabled Disabled Memory Mapped UO above 4GB Enabled Disabled Onboard Video Enabled Disabled Dual Monitor Video Enabled Disabled Onboard NIC1 ROM Enabled Disabled Onboard NIC2 ROM Enabled Disabled Onboard NIC iSCSI ROM Enabled Disabled NIC 1 MAC Address lt MAC gt NIC 2 MAC Address lt MAC gt Figure 36 Setup Utility PCI Configuration Screen Display Table 29 Setup Utility PCI Configuration Screen Fields Maximize Memory Enabled BIOS maximizes memory usage below 4GB for below 4GB Disabled an OS without PAE support depending on the system configuration Only enable
114. e or Disable Serial port A Enable Disabled Select Serial port A base I O address IRQ 3 Select Serial port A interrupt request IRQ line 4 Serial B Enabled Enable or Disable Serial port B Enable Disabled Address Select Serial port B base I O address Select Serial port B interrupt request IRQ line Revision 1 8 87 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 5 3 2 2 5 USB Configuration Screen The USB Configuration screen allows the user to configure the USB controller options To access this screen from the Main screen select Advanced USB Configuration Advanced USB Configuration Detected USB Devices USB Controller Enabled Disabled Legacy USB Support Enabled Disabled Auto Port 60 64 Emulation Enabled Disabled Make USB Devices Non Bootable Enabled Disabled USB Mass Storage Device Configuration Device Reset timeout 10 seconds 20 seconds 30 seconds 40 seconds Mass Storage Devices lass sto levices one line device gt Auto Floppy Forced FDD Hard Disk CD ROM USB 2 0 controller Enabled Disabled Figure 35 Setup Utility USB Controller Configuration Screen Display 88 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS BIOS Setup Utility Table 28 Setup Utility USB Controller Configuration Screen Fields Setup Item Options Help Text Detected USB Information only Shows the
115. e regardless of if the Post Error Pause setup option is enabled or disabled The user may want to replace the erroneous unit 22 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture Table 2 Mixed Processor Configurations System Action Processor family not Halt The BIOS detects the error condition and responds as follows identical Logs the error into the system event log SEL Alerts the Integrated BMC about the configuration error Does not disable the processor Displays 0194 Processor Ox family mismatch detected message in the Error Manager Halts the system and will not boot until the fault condition is remedied Otherwise this is a stepping mismatch error and the BIOS responds as follows Processor stepping Pause The BIOS detects the stepping difference and responds as follows mismatch Checks to see whether the steppings are compatible typically one stepping If so no error is generated this is not an error condition Continues to boot the system successfully Displays 0193 Processor 0x stepping mismatch message in the Error Manager and logs it into the SEL Takes Minor Error action and continues to boot the system Processor cache not Halt The BIOS detects the error condition and responds as follows identical Logs the error into the SEL A Alerts the Integrated BMC about the configuration error Does not disable the
116. e server Perform the BMC firmware update procedure as documented in the Update Instruction txt file included in the given BMC firmware update package After successful completion of the firmware update process the firmware update utility may generate an error stating the BMC is still in update mode Power down and remove the AC power cord Open the server chassis Move the jumper J1H1 from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 10 Close the server chassis 11 Reconnect the AC power cord and power up the server Note When the Force BMC Update jumper is set to the enabled position normal BMC functionality is disabled You should never run the server with the Force BMC Update jumper set in this position You should only use this jumper setting when the standard firmware update process fails When the server is running normally this jumper must remain in the default disabled position 7 3 BIOS Recovery Jumper Power down the system and remove the AC power cord 2 Open the server chassis See your server chassis documentation for instructions o Move the BIOS recovery jumper J1E5 from the default operating position covering pins 1 and 2 to the enabled position covering pins 2 and 3 Close the server chassis Reconnect the AC power cord and power up the server Perform the BIOS Recovery procedure as documented in the BIOS release notes zl Si 9 4e After successf
117. ecoder Appendix F POST Error Messages and Handling Appendix G Installation Guidelines Glossary Reference Documents 1 2 Server Board Use Disclaimer Intel Server Boards contain a number of high density VLSI Very large scale integration and power delivery components that require adequate airflow for cooling Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system meets the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of the published operating or non operating limits Revision 1 8 Intel order number E39529 013 Overview Intel Server Boards S5520HC 5500HCV and S5520HCT TPS 2 Overview The Intel Server Boards S5520HC S5500HCV and S5520HCT are monolithic printed circuit boards PCBs with features designed to support the pedestal server markets 2 1 Intel Server Boards S5520HC S5500HCV and S5520HCT Feature Set Processors Support for one or two Intel Xeon Processor s 5500 series up to 95W Thermal Design Power Support f
118. ed for optimal performance and efficiency and no RAS is enabled Mirror Mode System memory is configured for maximum reliability in the form of memory mirroring Information only Displays the speed the memory is running at Select to configure the memory RAS and performance This takes the user to a different screen Displays the state of each DIMM socket present on the board Each DIMM socket field reflects one of the following possible states Installed There is a DDR3 DIMM installed in this slot Not Installed There is no DDR3 DIMM installed in this slot Disabled The DDR3 DIMM installed in this slot was disabled by the BIOS to optimize memory configuration Failed The DDR3 DIMM installed in this slot is faulty malfunctioning Note X denotes the Channel Identifier and Y denote the DIMM Identifier within the Channel 83 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 5 3 2 2 2 1 Configure Memory RAS and Performance Screen The Configure Memory RAS and Performance screen allows the user to customize several memory configuration options such as whether to use Memory Mirroring To access this screen from the Main screen select Advanced gt Memory gt Configure Memory RAS and Performance Advanced Memory RAS and Performance Configuration Capabilities Memory Mirroring Possible Yes No Select Memory RAS Configuration Maximu
119. em Help Text Floppy Disk 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 6 Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices To access this screen from the Main screen select Boot Options Network Device Order Boot Options Network Device 1 Available Network devices Network Device 2 Available Network devices Figure 48 Setup Utility Network Device Order Screen Display Table 41 Setup Utility Network Device Order Fields Setup Item Options Help Text Network Device 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Network Device 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 5 3 2 6 7 BEV Device Order Screen The BEV Device Order screen allows the user to control the BEV bootable devices To access this screen from the Main screen select Boot Options BEV Device Order Boot Options BEV Device 1 lt Available BEV devices gt BEV Device 2 lt Available BEV devices gt Figure 49 Setup Utility BEV Device Order Screen Display 104 Revision 1 8 Intel order number E39529 013 Intel Server Boards SS520HC S5500HCV and 5520HCT TPS BIOS Setup Utility Table 42 Setup Utility
120. em is used together It is the responsibility of the System integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation can not be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright O Intel Corporation 2009 2010 Revision 1 8 ii Intel order number E39529 013 Table of Contents Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Table of Contents AE Introduction EE 1 1 1 Chapter Outline te bee e e ane iue Re ERE 1 1 2 Server Board Use Disclaimer 1 2 FOVeILVIGW eege resa re T ap oH SE sd POE Ee RETO NE NRI OWN N Eat ses ee begiers 2 2 1 Intel Server Boards S5520HC S5500HCV and S5520HCT Feature Set 2 2 1 1 Server Board Connector and Component Layout 5 2 1 2 Server Board Mechanical Drawings sssssssseeeeeeeennenen 8 2 1 3 Server Board Rear UO Layout 16 Seo GIN edel TE 17 3 1 Intel 5520 and 5500 UO Hub OH 20 3 1 1 Intel Qui kPath Interconnect uc er pente terere tet eq qti 20 3 1 2 PCGI ExpresS E 20 3 1 3 Enterprise South Br
121. ent ITE which may be installed in offices schools computer rooms and similar commercial type locations The suitability of this product for other product categories and environments such as medical industrial telecommunications NEBS residential alarm systems test equipment etc other than an ITE application may require further evaluation 10 1 1 Product Safety Compliance The Intel Server Boards 5520HC S5500HCV and S5520HCT comply with the following safety requirements UL60950 CSA 60950 USA Canada EN60950 Europe IEC60950 International CB Certificate amp Report IEC60950 report to include all country national deviations GS License Germany GOST R 50377 92 License Russia Listed on System License Belarus License Belarus Listed on System License CE Low Voltage Directive 73 23 EEE Europe IRAM Certification Argentina 10 1 2 Product EMC Compliance Class A Compliance The Intel Server Boards S5520HC S5500HCV and S5520HCT have been tested and verified to comply with the following electromagnetic compatibility EMC regulations when installed a compatible Intel host system For information on compatible host system s refer to http support intel com support motherboards server S5520HC or contact your local Intel representative e FCC ICES 003 Emissions USA Canada Verification e CISPR 22 Emissions International e EN55022 Emissions Europe e EN55024 Immunity Europe
122. ent Practices for Perchlorate Materials The State of California requires a warning to be included for products containing a device using Lithium Perchlorate Intel understands CA Lithium Perchlorate require a printed warning to be included with all products containing a Lithium battery either as an insert in existing product literature or as part of the shipping memo wording Wording is as follows Perchlorate Material special handling may apply See www dtsc ca gov hazardouswaste perchlorate This notice is required by California Code of Regulations Title 22 Division 4 5 Chapter 33 Best Management Practices for Perchlorate Materials This product part includes a battery that contains Perchlorate material 10 8 End of Life Product Recycling Product recycling and end of life take back systems and requirements vary by country Contact the retailer or distributor of this product for information about product recycling and or take back 144 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Appendix A Integration and Usage Tips Appendix A Integration and Usage Tips e Prior to adding or removing components or peripherals from the server board you must remove the AC power cord With AC power plugged into the server board 5 V standby is still present even though the server board is powered off e This server board supports Intel Xeon Processor 5500 Series only This serv
123. er Boards 5520HC SSSOOHCV and S5520HCT TPS BIOS Setup Utility Table 33 Setup Utility Console Redirection Configuration Fields Help Text Disabled Serial Port A Serial Port B Console Redirection Flow Control None RTS CTS Baud Rate Terminal Type PC ANSI VT100 VT100 VT UTF8 Legacy OS Disabled Redirection Enabled 5 3 2 5 Console redirection allows a serial port to be used for server management tasks Disabled No console redirection Serial Port A Configure serial port A for console redirection Serial Port B Configure serial port B for console redirection Enabling this option disables the display of the Quiet Boot logo screen during POST Flow control is the handshake protocol Setting must match the remote terminal application None Configure for no flow control RTS CTS Configure for hardware flow control Serial port transmission speed Setting must match the remote terminal application Character formatting used for console redirection Setting must match the remote terminal application This option enables legacy OS redirection i e DOS on serial port If it is enabled the associated serial port is hidden from the legacy OS Server Management System Information Screen The Server Management System Information screen allows the user to view part numbers serial numbers and firmware revisions To access this screen from the Main screen select Server Management
124. er board does not support previous generation Intel Xeon processors e You must install processors in order CPU 1 socket is located near the back edge of the server board and must be populated to operate the board and enable CPU 2 socket e On the back edge of the server board there are EIGHT diagnostic LEDs that display a sequence of amber POST codes during the boot process If the server board hangs during POST the LEDs display the last POST event run before the hang e Only Registered DDR3 DIMMs RDIMMs and Unbuffered DDR3 DIMMs UDIMMs are supported on this server board Mixing of RDIMMs and UDIMMs is not supported e Must always start populating DDR3 DIMMs in the first slot on each memory channel Memory slot A1 B1 C1 D1 E1 or F1 e Must populate Quad Rank RDIMM starting with the first slot Memory slot A1 B1 C1 D1 E1 or F1 on each memory channel e For the best performance you should balance the number of DDR3 DIMMs installed across both processor sockets and memory channels For example with two processors installed a 6 DIMM configuration with identical DIMMs in slot A1 B1 C1 D1 E1 and F1 performs better than a 6 DIMM configuration with identical DIMMs at A1 A2 B1 B2 C1 and C2 e The Intel RMM3 connector is not compatible with the Intel Remote Management Module Product Code AXXRMM or the Intel Remote Management Module 2 Product Code AXXRMM2 e Normal BMC functionality is disabled with the Force
125. ery EE HSBP B J Back Panel I O Ports FF SATA Port 2 K Diagnostic and Identify LED s GG HSBP_A L System Fan 5 Header 4 pin HH SATA Port 3 M Power Connector for Processor 1 and Memory T SATA Software RAID 5 Key Header attached to Processor 1 N Processor 1 Fan Header 4 pin JJ Chassis Intrusion Header O DIMM Sockets of Memory Channel A B and C KK SATA Port 4 P Power Connector for Processor 2 and Memory LL SATA Port 5 attached to Processor 2 HDD Activity LED Header Connect to Q Auxiliary Power Signal Connector MM Add in Card HDD Activity LED Header f USB Connector 9 pin for front panel R Processor 2 Fan Header 4 pin NN USB ports S DIMM Sockets of Memory Channel D E and F OO USB Connector 9 pin T SAS Module Slot PP Front Control Panel header U System Fan 3 Header 6 pin QQ DH 10 Serial B header V System Fan 4 Header 6 pin Figure 3 Major Board Components Revision 1 8 Intel order number E39529 013 Overview Intel Server Boards S5520HC 5500HCV and S5520HCT TPS 2 1 2 Server Board Mechanical Drawings a ei sts S z 33 EK 2 os oF nk ae 2 So ante 29 3 S 5o ess Se zz an 0 400 2 X Q0 1180H0LE FOR MEMORY VR HEATSINK PUSH PIN RETENTION 10 161 y 3 001 0 000 LT a 10 00 0 553 Vis 2n T 22 861 BASEBOARD MOUNTING HOLE 1 10 PLACES D 1 i Vy 4 1 E d 65 291 i 1 i i i d i 0 1587 CPU HEATSINK MOUNTING HOLE 4X258 PLACES a d i 4 03
126. es an access point to configure several options On this screen the user selects the option they must configure Configurations are performed on the selected screen and not directly on the Advanced screen To access this screen from the Main screen press the right arrow until the Advanced screen is selected Advanced Security Server Management Boot Options Boot Manager gt Processor Configuration gt Memory Configuration gt Mass Storage Controller Configuration gt Serial Port Configuration gt USB Configuration gt PCI Configuration gt System Acoustic and Performance Configuration Figure 29 Setup Utility Advanced Screen Display Table 22 Setup Utility Advanced Screen Display Fields Setup Item Help Text Processor Configuration View Configure processor information and settings Memory Configuration View Configure memory information and settings Mass Storage Controller Configuration View Configure mass storage controller information and settings Serial Port Configuration View Configure serial port information and settings USB Configuration View Configure USB information and settings PCI Configuration View Configure PCI information and settings System Acoustic and Performance View Configure system acoustic and Configuration performance information and settings 78 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS BIOS Se
127. et 09h 6Fh control failure De Fatal 06 Power unit failure Power Unit Status Pwr Unit Status 00 Fully 01 Redundancy Degraded lost 02 Redundancy degraded Degraded 03 Non redundant sufficient resources Degraded Power Unit Redundancy1 S Chassis Power Unit Generic Transition from Tria Offset Pwr Unit Redund specific 09h OBh full redundant g state 04 Non redundant sufficient Degraded resources Transition from insufficient state 05 Non redundant insufficient resources 152 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC SSSOOHCV and 55520HCT TPS Full Sensor Name Sensor name in SDR Sensor Platform Applicability Sensor Type Event Reading Type Event Offset Triggers Appendix C BMC Sensor Tables Contrib To System Status Assert De assert 06 Redundant degraded from fully redundant state Degraded 07 Redundant Transition from Readable Rearm Stain Value Offs by ets non redundant Degraded state 00 Timer expired status E only ensor IPMI Watchdog Watchdog 2 doe 01 Hard reset Specific Trig Offset A X IPMI Watchdog 23h e 02 Power down E E 03 Power cycle 08 Timer interrupt Chassis 00 Chassis OK Physical Security Intrusion is Physical Sensor intrusion Security Specific Trig Offset Physical Scrty chassis 05h 6Fh 04 LAN leash specific
128. etting requires a reboot before you can set the HDD boot order SW RAID option is unavailable when EFI Optimized Boot is Enabled SW RAID can only be used in Legacy Boot mode Information only This field is unavailable when RAID Mode is enabled Information only This field is unavailable when RAID Mode is enabled Information only This field is unavailable when RAID Mode is enabled Information only This field is unavailable when RAID Mode is enabled SATA Port 4 Not Installed Driv e information Information only This field is unavailable when RAID Mode is enabled SATA Port 5 Not Information only This field is Installed Driv unavailable when RAID Mode is e enabled information 86 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCYV and S5520HCT TPS BIOS Setup Utility 5 3 2 2 4 Serial Ports Screen The Serial Ports screen allows the user to configure the Serial A COM 1 and Serial B COM2 ports To access this screen from the Main screen select Advanced Serial Port Advanced Serial Port Configuration Serial A Enable Enabled Disabled Address 3F8h 2F8h 3E8h 2E8h IRQ 3or4 Serial B Enable Enabled Disabled Address 3F8h 2F8h 3E8h 2E8h IRQ 30r 4 Figure 34 Setup Utility Serial Port Configuration Screen Display Table 27 Setup Utility Serial Ports Configuration Screen Fields Setup Hem Options Help Text Serial A Enabled Enabl
129. executed This is accomplished by placing the data from the I O devices directly into the processor cache through hints to the processor to perform a data pre fetch and install it in its local caches The BIOS setup provides an option to enable or disable this feature The default behavior is enabled 3 2 9 Unified Retention System Support The server boards comply with Unified Retention System URS and Unified Backplate Assembly The server boards ship with Unified Backplate Assembly at each processor socket The URS retention transfers load to the server boards via the Unified Backplate Assembly The URS spring captive in the heatsink provides the necessary compressive load for the thermal interface material TIM All components of the URS heatsink solution are captive to the heatsink and only require a Phillips screwdriver to attach to the Unified Backplate Assembly See the following figure for the stacking order of URS components The Unified Backplate Assembly is removable allowing for the use of non Intel heatsink retention solutions Revision 1 8 25 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS SCREW HEATSINK COMPRESSION SPRING ja Wl RETENTION CUP e wN d SS v LT UD RETANINGRING d k DS E m ILM amp SOCKET MOTHERBOARD ILM ATTACH STUDS HEATSINK ATTACH STUDS UNIFIED BACK PLATE Figure 15 Unified Retenti
130. f configuration screen hot keys were pressed during POST See 32MB video memory of onboard video controller after install onboard video driver Description After install driver of Intel Server Boards S5520HC S5500HCV and S5520HCT onboard video controller the video driver will report 32MB video memory instead of 8MB Guideline The memory reported by onboard video driver is attached memory which is accessed by the video controller for internal operations The graphic memory size for display function is still 8MB Revision 1 8 171 Intel order number E39529 013 Glossary Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Glossary Term Definition ACPI Advanced Configuration and Power Interface 5 C mp fe lem P p CLTT Closed Loop Thermal Throttling In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board B E Electromagnetic Compatibility 172 Revision 1 8 Intel order number E39529 013 S S V S e A C E C S B U M P R T B E M yt L C M P X C M M P S M R R T C A C P H Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Glossary Inter Integrated Circuit Bus ICH UO Controller Hub Interrupt eo Wempteqes OOOO WMKB MTBF Mean Time Between Failures NVSRAM Non volatile Static Random Access Memory Ohm Untefeecticalesstanes SSS Physica
131. face TPM State Enabled and Activated Information only Enabled and Deactivated Shows the current TPM Disabled and Activated device state Disabled and A disabled TPM device Deactivated does not execute commands that use the TPM functions and TPM security operations are not available An enabled and deactivated TPM is in the same state as a disabled TPM except setting of the TPM ownership is allowed if not present already An enabled and activated TPM executes all commands that use the TPM functions and TPM security operations are also available Revision 1 8 93 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Setup Item Help Text Comments TPM Administrative No Operation No Operation No changes to Control Turn On current state Turn Off Turn On Enables and activates TPM Turn Off Disables and deactivates TPM Clear Ownership Removes the TPM ownership authentication and returns the TPM to a factory default state Note The BIOS setting returns to No Operation on every boot cycle by default Not Available in Intel Server Boards S5520HC S5500HCV and S5520HCT which have no TPM Clear Ownership Grayed out at No Operation state in Intel Server Boards S5520HC S5500HCV and S5520HCT which have no TPM 5 3 2 4 Server Management Screen The Server Management screen allows the user to configure several server management
132. following message displays on the diagnostics screen and under the Quiet Boot logo screen Press F2 to enter setup When the Setup is entered the Main screen displays However serious errors cause the system to display the Error Manager screen instead of the Main screen 5 3 1 3 Keyboard Commands The bottom right portion of the Setup screen provides a list of commands used to navigate through the Setup utility These commands display at all times Each Setup menu page contains a number of features Each feature is associated with a value field except those used for informative purposes Each value field contains configurable parameters Depending on the security option selected and in effect by the password a menu feature s value may or may not change If a value cannot be changed its field is made inaccessible and appears grayed out Revision 1 8 73 Intel order number E39529 013 BIOS Setup Utility Key Enter Esc Tab F9 lt F10 gt 74 Option Execute Command Exit Select Item Select Item Select Menu Select Field Change Value Change Value Setup Defaults Save and Exit Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Table 20 BIOS Setup Keyboard Command Bar The lt Enter gt key is used to activate sub menus when the selected feature is a sub menu or to display a pick list if a selected option has a value field or to select a sub field for multi va
133. for an OS without PAE support Memory Mapped UO Enabled Enable or disable memory mapped I O of 64 bit above 4GB Disabled PCI devices to 4 GB or greater address space Onboard Video Enabled Onboard video controller When disabled the system Disabled Warning System video is completely disabled if requires an add in video this option is disabled and an add in video card for the video to be adapter is not installed Seen Dual Monitor Video Enabled If enabled both the onboard video controller and Disabled an add in video adapter are enabled for system video The onboard video controller becomes the primary video device Onboard NIC1 ROM Enabled If enabled loads the embedded option ROM for Disabled the onboard network controllers Warning If Disabled is selected NIC1 cannot be used to boot or wake the system Onboard NIC2 ROM Enabled If enabled loads the embedded option ROM for Disabled the onboard network controllers Warning If Disabled is selected NIC2 cannot be used to boot or wake the system 90 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS BIOS Setup Utility Onboard NIC iSCSI Enabled If enabled loads the embedded option ROM for This option is grayed out ROM Disabled the onboard network controllers and not accessible if either the NIC1 or NIC2 ROMs Warning If Disabled is selected NIC1 and NIC2 are enabled cannot be used to boot or
134. he SATA ports and or configure them by accessing the BIOS Setup utility during POST 3 4 1 1 Intel Embedded Server RAID Technology II Support The Intel Embedded Server RAID Technology II Intel ESRTII feature provides RAID modes 0 1 and 10 If RAID 5 is needed with Intel ESRTII you must install the optional Intel RAID Activation Key AXXRAKSWB accessory You must place this activation key on the SATA Software RAID 5 connector located on the Intel Server Boards S5520HC S5500HCV and 5520HCT For installation instructions see the documentation accompanying the server boards and the activation key When Intel Embedded Server RAID Technology II of the SATA controller is enabled enclosure management is provided through the SATA SGPIO connector on the server boards when a cable is attached between this connector and the backplane or C interface See Figure 3 Major Board Components for the locations of Intel RAID Activation Key connector and SATA SGPIO connector Intel Embedded Server RAID Technology II functionality requires the following items e ICH10R I O Controller Hub e Software RAID option is selected on the BIOS menu for the SATA controller Revision 1 8 39 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCYV and S5520HCT TPS Intel Embedded Server RAID Technology Il Option ROM e Intel Embedded Server RAID Technology Il drivers most recent revision e Atleast two SATA
135. hernet Controllers with NC SI support e 16 bit DDR2 667 MHz interface e Dedicated RTC e 12 10 bit ADCs e Eight Fan Tachometers e Four PWMs e Battery backed Chassis Intrusion I O Register e JTAG Master e Six lC interfaces e General purpose I O Ports 16 direct 64 serial Additionally the BMC integrates a super I O module with the following features e Keyboard style BT interface e Two 16550 compatible serial ports e Serial IRQ support e 16 GPIO ports shared with the BMC e LPC to SPI bridge for system BIOS support e SMI and PME support The BMC also contains an integrated KVMS subsystem and graphics controller with the following features e USB 2 0 for Keyboard Mouse and Storage devices e USB 1 1 interface for legacy PS 2 to USB bridging e Hardware Video Compression for text and graphics e Hardware encryption e 2D Graphics Acceleration e DDR2 graphics memory interface e Up to 1600x1200 pixel resolution e PCI Express x1 support Revision 1 8 47 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Fan Tach ADC LPC Master Interrupt 8 JTAG Master Controller PWM amp 4 SPI Flach ARM926E 5 ioKD amp l Ca RICA Crypto General Purpose UART Fo amp Timars 3 8 Video 3 Accelaralor che Ethernet MAC Kou RMII interface 2 DDR 2 ipto 667 MHz LPC interface to Host Real Time clock Caen Watchdog Timer ein asl
136. hieve optimal levels 4 3 2 Fan Speed Control BIOS and BMC software work cooperatively to implement system thermal management support During normal system operation the BMC will retrieve information from the BIOS and monitor several platform thermal sensors to determine the required fan speeds In order to provide the proper fan speed control for a given system configuration the BMC must have the appropriate platform data programmed Platform configuration data is programmed using the FRUSDR utility during the system integration process and by System BIOS during run time 4 3 2 1 System Configuration Using the FRUSDR Utility The Field Replaceable Unit and Sensor Data Record Update Utility FRUSDR utility is a program used to write platform specific configuration data to NVRAM on the server board It allows the user to select which supported chassis Intel or Non Intel and platform chassis configuration is used Based on the input provided the FRUSDR writes sensor data specific to the configuration to NVRAM for the BMC controller to read each time the system is powered on 4 3 2 2 Fan Speed Control from BMC and BIOS Inputs Using the data programmed to NVRAM by the FRUSDR utility the BMC is configured to monitor and control the appropriate platform sensors and system fans each time the system is powered on After power on the BMC uses additional data provided to it by the System BIOS to determine how to control the system fans The BI
137. iagrams show the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied Revision 1 8 133 Intel order number E39529 013 Design and Environmental Specifications Table 79 Output Voltage Timing Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Intel order number E39529 013 Item Description Minimum Maximum Units Tvout rise Output voltage rise time from each main output 5 0 1 701 ms Tvout_rise All main outputs must be within regulation of each other within this N A 50 ms time Tvout rise All main outputs must leave regulation within this time N A 400 ms 1 The 5 VSB output voltage rise time is from 1 0 ms to 25 ms j V out 10 V out Ma sae v2 d d v3 i i d V4 i J pos Le ri Tvout off lt gt Tyout rise lx Tvout_on TP02313 Figure 60 Output Voltage Timing 134 Revision 1 8 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Table 80 Turn On Off Timing Design and Environmental Specifications Item Description Minimum Maximum Units Tsb on delay Delay from AC being applied to 5 VSB being within N A 4500 ms regulation Tac on delay Delay from AC being applied to all output voltages being ms SE N A 2500 within regulation Tvout holdup Time all output voltages stay within regul
138. ical memory into system memory above 4 GB the system memory is the memory the processor can see The BIOS always enables high memory reclaim if it discovers installed physical memory equal to or greater than 4 GB For the operating system you can recover the reclaimed memory only if the PAE feature in the processor is supported and enabled Most operating systems support this feature For details see your operating system s relevant manuals 3 3 5 Memory Interleaving The Intel Xeon Processor 5500 Series supports the following memory interleaving mode 32 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture e Bank Interleaving Interleave cache line data between participant ranks e Channel Interleaving Interleave between channel when not in Mirrored Channel Mode e Socket Interleaving Interleaved memory can spread between both CPU sockets when NUMA mode is disabled given both CPU sockets are populated and DDR3 DIMMs are installed in slots for both sockets 3 3 6 Memory Test 3 3 6 1 Integrated Memory BIST Engine The Intel Xeon Processor 5500 series incorporate an integrated Memory Built in Self Test BIST engine enabled to provide extensive coverage of memory errors at both the memory cells and the data paths emanating from the DDR3 DIMMs The BIOS also uses the Memory BIST to initialize memory at the end of the memory discovery process 3 3 7 Mem
139. idge Interface EI 21 3 1 4 Manageability Engine ME 21 3 1 5 Controller Link CL eee NEEN ren entente nen arn etna nada 21 3 2 Processor Support inet e ee a Ha e dente ae Exe ER eet a 22 3 2 1 Processor Population Rules eene nenne 22 3 2 2 Mixed Processor Configurations cccccccceceeceeeeeeeeeeeaeeeeeeeeeecneeeeseeeeeeeneeeeeeeetee 22 3 23 Intel Hyper Threading Technology Intel HT 24 3 2 4 Enhanced Intel SpeedStep Technology EIST 24 3 2 5 Intel Turbo Boost ag VE 24 3 2 6 Execute Disable Bit Feature E 24 3 2 7 Core Mut Prorcessing EE 25 3 2 8 Direct Cache Access DCA crinii ear n e e a e aea eiS 25 3 2 9 Unified Retention System Gupport n 25 3 3 Memory Gubevstem AE 27 3 3 1 Memory Subsystem Nomenclature 27 3 3 2 Supported Memonm nenne nnne ET 29 3 3 3 Processor Cores QPI Links and DDR3 Channels Frequency Configuration 30 3 3 4 Publishing System Memory ssssssssssseeeeeeeeeeeeenn emen enne nnn 32 3 3 5 Memory Interleaving EE 32 3 3 6 Memory T6St dote At ect dH e e d me tete 33 3 3 7 Memory Scrub Engine EE 33 3 3 8 Memory EAS EE 33 3 3 9 Memory Population and Upgrade Hues 34 3 3 10 Supported Memory Configuration ssssssssssssseeeeenene enne 36 3 3 11 Memory Error Handling nnns 38 3 4 IG HT ll 39 3 4 1 HERE 39 iv Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Table of Contents 3 4 2 USB 2 0
140. if the part is operating below power temperature and current limits If the processor supports this feature the BIOS setup provides an option to enable or disable this feature The default is enabled 3 2 6 Execute Disable Bit Feature The Execute Disable Bit feature XD bit can prevent data pages from being used by malicious software to execute code A processor with the XD bit feature can provide memory protection in one of the following modes e Legacy protected mode if Physical Address Extension PAE is enabled 24 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Functional Architecture e Intel 64 mode when 64 bit extension technology is enabled Entering Intel 64 mode requires enabling PAE You can enable and disable the XD bit in the BIOS Setup The default behavior is enabled 3 2 7 Core Multi Processing The BIOS setup provides the ability to selectively enable one or more cores The default behavior is to enable all cores You can do this through the BIOS setup option for active core count The BIOS creates entries in the Multi Processor Specification Version 1 4 tables to describe multi core processors 3 2 8 Direct Cache Access DCA Direct Cache Access DCA is a system level protocol in a multi processor system to improve I O network performance thereby providing higher system performance The basic idea is to minimize cache misses when a demand read is
141. ight of the connector indicates 1000 Mbps operation when amber 100 Mbps operation when green and 10 Mbps when off The following table provides an overview of the LEDs Table 15 Onboard NIC Status LED Link Activity Speed LED LED LED Color LED State NIC State ONN Off Green Amber Right 3 12 1 MAC Address Definition Each Intel Server Board S5520HC or S5500HCV has the following four MAC addresses assigned to it at the Intel factory e NIC 1 MAC address e NIC2MAC address is assigned the NIC 1 MAC address 1 e BMC LAN Channel MAC address is assigned the NIC 1 MAC address 2 e Intel Remote Management Module 3 Intel RMM3 MAC address is assigned the NIC 1 MAC address 3 During the manufacturing process each server board has a white MAC address sticker placed on the top of the NIC 1 port The sticker displays the NIC 1 MAC address and Intel RMM3 MAC in both bar code and alphanumeric formats Revision 1 8 51 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 3 13 Trusted Platform Module TPM Supported only on 5520HCT 3 13 1 Overview Trusted Platform Module TPM is a hardware based security device that addresses the growing concern on boot process integrity and offers better data protection TPM protects the system start up process by ensuring it is tamper free before releasing system control to the operating sys
142. ional BIOS version 1 2 and to the TPM Interface specification version 1 2 The BIOS adheres to the Microsoft Vista BitLocker requirement The role of the BIOS for TPM security includes the following e Measures and stores the boot process in the TPM microcontroller to allow a TPM enabled operating system to verify system boot integrity e Produces EFI and legacy interfaces to a TPM enabled operating system for using TPM e Produces ACPI TPM device and methods to allow a TPM enabled operating system to send TPM administrative command requests to the BIOS e Verifies operator physical presence Confirms and executes operating system TPM administrative command requests e Provides BIOS Setup options to change TPM security states and to clear TPM ownership For additional details refer to the TCG PC Client Specific Implementation Specification the TCG PC Client Specific Physical Presence Interface Specification and the Microsoft BitLocker Requirement documents 52 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Functional Architecture 3 13 2 1 Physical Presence Administrative operations to the TPM require TPM ownership or physical presence indication by the operator to confirm the execution of administrative operations The BIOS implements the operator presence indication by verifying the setup Administrator password A TPM administrative sequence invoked from the operating syste
143. it e D at a EXE Rep ideo be Ren Le tna 57 Figure 24 TP M activated cn de eee rd E pede eE lee eva ae epe Ee dep 58 Figure 25 BIOS Setting for RUE 59 Figure 26 Platform Control 67 Figure 27 SMBUS Block Diagram sssssssssssssseseeeeene nennen rennen nemen 71 Figure 28 Setup Utility Main Screen Display 76 Figure 29 Setup Utility Advanced Screen Display 78 Figure 30 Setup Utility Processor Configuration Screen Display 79 Figure 31 Figure 32 Figure 33 Setup Utility Memory Configuration Screen Display sssssssesssss 82 Setup Utility Configure RAS and Performance Screen Display 84 Setup Utility Mass Storage Controller Configuration Screen Display 85 Figure 34 Setup Utility Serial Port Configuration Screen Display 87 Figure 35 Setup Utility USB Controller Configuration Screen Display 88 Figure 36 Setup Utility PCI Configuration Screen Display ssseseeesseeeeeeeeenneneeeenerneneerrenee 90 Figure 37 Setup Utility System Acoustic and Performance Configuration Screen Display 91 Figure 38 Setup Utility Security Configuration Screen Display 92 Figure 39 Setup Utility Server Management Configuration Screen Display 95 viii Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and 5520
144. ites dans lanorme sur le mat riel brouilleur Apparelis Num riques NMB 003 dictee par le Ministre Canadian des Communications English translation of the notice above This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications Europe CE Declaration of Conformity This product has been tested in accordance too and complies with the Low Voltage Directive 73 23 EEC and EMC Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance VCCI Japan CORES PHUBLES RE ERES RI VCCI OZ CED VIABWHRARECT CORB RAR CHAT SCE S BL Lruugdig CORBPIV APT LEY ay FERTELT Sait BME SFRCTCEMPHVETF WIR AAS CH gt TEL UCHRRU RU EUCT EU English translation of the notice above This is a Class B product based on the standard of the Voluntary Control Council for Interference VCCI from Information Technology Equipment If this is used near a radio or television receiver in a domestic environment it may cause radio interference Install and use the equipment according to the instruction manual BSMI Taiwan The BSMI Certification Marking and EMC warning is located on the outside rear area of the product BAAS ie ARRAS ER TEPER ER EH OS ABS WR Se HATIZ iawn EAS BR KIF WH EES BSR 140 Revision 1 8 Inte
145. l Server Board S5520HC or Intel Server Board S5500HCV onboard video controller Guideline Edit the script usr bin X11 Xserver and modify arguments as following in order to accomplish graphics display SERVERARGS depth 16 fbbpp 16 4 System may experience high power consumption under Microsoft Windows Server 2003 when the processor is idle Description Intel Server Board S5520HC or Intel Server Board S5500HCV based system may experience high power consumption under Microsoft Windows Server 2003 when the processor is idle and there is a discontinuity in the C states Guideline Follow the instructions listed at the following website to apply the hot fix only to systems that are experiencing this problem http support microsoft com kb 94 1838 170 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Appendix G Installation Guidelines 5 When EFI Shell is selected as the first device on the BIOS boot option list some RAID adapters may not enter their configuration screen before the server board boots into EFI Shell Description In an Intel Server Board 5520HC or S5500HCV based system with EFI shell as first boot device after users press hot keys to enter RAID adapter configuration screen that hooks option ROM on INT 19h the system may boot in to EFI shell instead Guideline Type exit and execute under the EFI shell the RAID adapter configuration screen will show up i
146. l SAS Entry RAID Module AXX4SASMOD Storage Mode Updated Table 47 and Table 48 CPU 1 and CPU2 power connectors pin out Updated Table 84 POST Codes and Messages Updated Table 87 BMC Beep Codes Updated Figure 21 SMBUS Block Diagram revised components code name Updated Figure 53 Power Distribution Block Diagram revised components code name Updated Section 2 1 the feature set table Updated Section 3 3 2 supported memory Updated Section 3 3 3 Added Section 3 15 Updated Appendix A adding PCI device SEL event decoding tips Updated Appendix G Updated Section 4 2 2 Keyboard Video and Mouse KVM Redirection Updated Table 2 Table 8 Table 9 Table 25 Figure 13 and Figure 14 Updated Section 3 15 and 7 3 Updated Section 3 3 3 Updated Section 3 3 9 supported memory population Updated Section 2 1 added security feature for 5520HCT Added Section 3 13 Trusted Platform Module Updated Section 2 1 added Intel Xeon Processor 5600 series support Updated Section 3 2 added Intel Xeon Processor 5600 series support Removed CCC related notices Added Section 3 13 3 Intel Trusted Execution Technology Intel TXT Update section 3 3 2 memory capacity Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectu
147. l Address Extension Revision 1 8 173 Intel order number E39529 013 Glossary Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Platform Management Interrupt PWM Pulse Width Modulation Reliability Availability and Serviceability Reliability Availability Serviceability Usability and Manageability ROMM Registered Dual nine Memory Mode TDP Thermal Design Power uge User Datagram Protocol SSCS UHCI Universal Host Controller Interface s ne een Sy uss UnvmalSelBus ure rivera ie eset OOU Video Graphic Array 174 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Glossary WS MAN Web Service for Management Revision 1 8 175 Intel order number E39529 013 Reference Documents Intel Server Board S5520HC SSSOOHCV TPS Reference Documents See the following documents for additional information Inte Server Boards S5520HC and S5500HCV Specification Update 176 Revision 1 8 Intel order number E39529 013
148. l not boot until the fault condition is remedied Processor microcode The BIOS detects the error condition and responds as follows missing Logs the error into the SEL Does not disable the processor Displays 8180 Processor Ox microcode update not found message in the Error Manager or on the screen The system continues to boot in a degraded state regardless of the setting of POST Error Pause in Setup 3 2 3 Intel Hyper Threading Technology Intel HT If the installed processor supports the Intel Hyper Threading Technology the BIOS Setup provides an option to enable or disable this feature The default is enabled The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors The SMBIOS Type 4 structure shows only the installed physical processors It does not describe the virtual processors Because some operating systems are not able to efficiently use the Intel HT Technology the BIOS does not create entries in the Multi Processor Specification Version 1 4 tables to describe the virtual processors 3 24 Enhanced Intel SpeedStep Technology EIST If the installed processor supports the Enhanced Intel SpeedStep Technology the BIOS Setup provides an option to enable or disable this feature The Default is enabled 3 2 5 Intel Turbo Boost Technology Intel Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency
149. l order number E39529 013 Intel Server Boards 5520HC S5500HCV and 5520HCT TPS Regulatory and Certification Information RRL KCC Korea 43554923 10 4 Product Ecology Change EU RoHS Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002 95 EC Compliance is based on declaration that materials banned in the RoHS Directive are either 1 below all applicable threshold limits or 2 an approved pending RoHS exemption applies RoHS implementation details are not fully defined and may change Threshold limits and banned substances are noted below e Quantity limit of 0 1 by mass 1000PPM for Lead Mercury Hexavalent Chromium Polybrominated Biphenyls Diphenyl Ethers PBDE e Quantity limit of 0 0196 by mass 100 PPM for Cadmium 10 5 Product Ecology Change CRoHS CRoHS China RoHS or Ministry of Information Industry Order 39 Management Methods for Controlling Pollution by Electronic Information Products e China bans the same substances and limits as noted for EU RoHS however require product marking and controlled substance information Environmental Friendly Usage Period EFUP Marking Is defined in number of years in which controlled listed substances will not leak or chemically deteriorate while in the product Intel understands the end seller entity placing product into market place is responsible for providing EFUP marking e Intel
150. le in parallel 64 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCYV and S5520HCT TPS Platform Management e You can mount either IDE CD ROM floppy or USB devices as a remote device to the server e Itis possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE IMG and CD ROM or DVD ROM ISO files For more information refer to the Tested supported Operating System List e tis possible to mount at least two devices concurrently e The mounted device is visible to and usable by the managed system s operating system and BIOS in both the pre and post boot states e The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to boot from this remote device e Itis possible to install an operating system on a bare metal server no operating system present using the remotely mounted device This may also require the use of KVM r to configure the operating system during install If either a virtual IDE or virtual floppy device is remotely attached during system boot both virtual IDE and virtual floppy are presented as bootable devices It is not possible to present only a single mounted device type to the system BIOS 4 2 3 1 Availability The default inactivity timeout is 30 minutes and is not user configurable Media redirection sessions persist across system reset but not across an AC power loss 4
151. lity without saving User prompted for confirmation only if Exit changes any of the setup fields were modified The Esc key can also be used Save Changes Save changes without exiting the BIOS Setup User prompted for confirmation only if Utility any of the setup fields were modified Note Saved changes may require a system reboot before taking effect Discard Changes Discard changes made since the last Save User prompted for confirmation only if Changes operation was performed any of the setup fields were modified Load Default Values Load factory default values for all BIOS Setup User prompted for confirmation utility options The F9 key can also be used Save as User Default Save current BIOS Setup utility values as User prompted for confirmation Values custom user default values If needed the user default values can be restored via the Load User Default Values option below Note Clearing the CMOS or NVRAM does not cause the User Default values to be reset to the factory default values Load User Default Load user default values User prompted for confirmation Values Revision 1 8 107 Intel order number E39529 013 Connector Header Locations and Pin outs Intel Server Boards 5520HC 5500HCV and S5520HCT TPS 6 Connector Header Locations and Pin outs 6 1 Board Connector Information The following section provides detailed information regarding all connectors headers and jumpers on the server boards The followi
152. lost OK d Critical Sensor 00 Front panel FP Interrupt Ge Interrupt Specific NMI diagnostic OK Trig Offset FP NMI Diag Int p 13h 6Fh interrupt SMI Timeout All SMI Timeout D 01 State Tia Otet SMI Timeout F3h SCH asserted g Event Sensor System Event Log Logging Specifi 02 Log area System Event Log Disabled S reset cleared Trig Offset 6Fh 10h System Event System Sensor epee EVER 08h All Event Specific 04 PEF action OK As Trig Offset All x System Event 12h 6Fh Revision 1 8 153 Intel order number E39529 013 Appendix C BMC Sensor Tables Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS Readable Full Sensor Name Platform Event Reading Event Offset Contrib To Assert De Sensor name in SDR sensory Applicability SCHEER Type Triggers System Status assert Value Offs ets nc u c nc Degraded Analog c Non fatal BB 1 1V IOH Voltage Threshold BB 1 1V IOH 02h 01h nc u c nc Degraded Analog c Non fatal BB 1 1V P1 Vccp Voltage Threshold BB 1 1V P1 Vccp 02h 01h nc u I c nc Degraded c Non fatal BB 1 1V P2 Vccp Voltage Threshold BB 1 1V P2 Vccp 02h 01h BB 1 5V P1 DDR3 Voltage Threshold bp BB 1 5V P1 DDR3 02h 01h i ene Ex bone c Non fatal nc u I c nc Degraded c Non fatal BB 1 5V P2 DDR3 Voltage Threshold BB 1 5V P2 DDR3 02h Oth nc u I c nc Degraded c Non fatal BB 1 8V AUX Voltage Threshold BB 1 8V AUX 02h 0
153. lued features like time and date If a pick list is displayed the lt Enter gt key selects the currently highlighted item undoes the pick list and returns the focus to the parent menu The lt Esc gt key provides a mechanism for backing out of any field When the lt Esc gt key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the lt Esc gt key is pressed in any sub menu the parent menu is re entered When the lt Esc gt key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded If No is selected and the lt Enter gt key is pressed or if the lt Esc gt key is pressed the user is returned to where they were before lt Esc gt was pressed without affecting any existing settings If Yes is selected and the lt Enter gt key is pressed the setup is exited and the BIOS returns to the main System Options Menu screen The up arrow is used to select the previous value in a pick list or the previous option in a menu item s option list The selected item must then be activated by pressing the lt Enter gt key The down arrow is used to select the next value in a menu item s option list or a value field s pick list The selected item must then be activated by pressing the lt Enter gt key The left and right arrow keys are used to move between the major menu pages The keys have no effect if
154. m Performance Mirroring NUMA Optimized Disabled Enabled Figure 32 Setup Utility Configure RAS and Performance Screen Display Table 25 Setup Utility Configure RAS and Performance Screen Fields Help Text Memory Mirroring Yes No Information only Only displayed Possible on systems with chipsets capable of Memory Mirroring Select Memory Maximum Available modes depend on the current Only available if Mirroring is RAS Configuration Performance memory population possible Mirroring Maximum Performance Optimizes system performance Mirroring Optimizes reliability by using half of physical memory as a backup NUMA Optimized Enabled If enabled BIOS includes ACPI tables Disabled that are required for NUMA aware Operating Systems 84 Revision 1 8 Intel order number E39529 013 Intel Server Boards SS5520HC SSSOOHCV and 5520HCT TPS BIOS Setup Utility 5 3 2 2 3 Mass Storage Controller Screen The Mass Storage screen allows the user to configure the SATA SAS controller when it is present on the baseboard module card of an Intel system To access this screen from the Main menu select Advanced Mass Storage Figure 33 Setup Utility Mass Storage Controller Configuration Screen Display Revision 1 8 85 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Table 26 Setup Utility Mass Storage Controller Configuration Screen Fiel
155. m proceeds as follows 1 User makes a TPM administrative request through the operating system s security software The operating system requests the BIOS to execute the TPM administrative command through TPM ACPI methods and then resets the system 3 The BIOS verifies the physical presence and confirms the command with the operator 4 The BIOS executes TPM administrative command s inhibits BIOS Setup entry and boots directly to the operating system which requested the TPM command s 3 13 2 2 TPM Security Setup Options The BIOS TPM Setup allows the operator to view the current TPM state and to carry out rudimentary TPM administrative operations Performing TPM administrative options through the BIOS setup requires TPM physical presence verification Using BIOS TPM Setup the operator can turn ON or OFF TPM functionality and clear the TPM ownership contents After the requested TPM BIOS Setup operation is carried out the option reverts to No Operation The BIOS TPM Setup also displays the current state of the TPM whether TPM is enabled or disabled and activated or deactivated Note that while using TPM a TPM enabled operating system or application may change the TPM state independent of the BIOS setup When an operating system modifies the TPM state the BIOS Setup displays the updated TPM state The BIOS Setup TPM Clear option allows the operator to clear the TPM ownership key and allows the operator to take control of the system with
156. mber E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Appendix C BMC Sensor Tables e Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states You can rearm the sensors manually or automatically This column indicates the type supported by the sensor These abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm Rearm by init agent e Default Hysteresis The hysteresis setting applies to all thresholds of the sensor This column provides the count of hysteresis for the sensor which is 1 or 2 positive or negative hysteresis e Criticality Criticality is a classification of the severity and nature of the condition It also controls the behavior of the Control Panel Status LED e Standby Some sensors operate on standby power You can access these sensors and or generate events when the main system power is off but AC power is present Revision 1 8 15 Intel order number E39529 013 Appendix C BMC Sensor Tables Intel Server Boards 5520HC SSSOOHCV and 5520HCT TPS Table 82 Integrated BMC Core Sensors Readable Full Sensor Name Sanok Platform Gebees Event Reading Event Offset Contrib To Assert De Sensor name in SDR Applicability yp Triggers System Status assert Value Offs ets 00 Power down OK Power Unit Semar A d Specific 05 Soft power Say Trig Offs
157. ment Feature Support This section explains the advanced management features supported by the BMC firmware Table 17 lists basic and advanced feature support Individual features may vary by platform For more information refer to Appendix C Table 17 Basic and Advanced Management Features i Advanced x ARP DHCP Support PECI Thermal Management Support E mail Alerting Embedded Web Server SSH Support Integrated KVM Integrated Remote Media Redirection Local Directory Access Protocol LDAP for Linux mK XK OK OK OK OK OK OK OK DK OK x lt gt lt OK lt x lt Xx Intel Intelligent Power Node Manager X Support SMASH CLP X WS Management Basic management features provided by integrated BMC Advanced management features available with optional Intel Remote Management Module 3 Intel Intelligent Power Node Manager Support requires PMBus compliant power supply X lt X lt 4 2 1 Enabling Advanced Management Features BMC will enable advanced management features only when it detects the presence of the Intel Remote Management Module 3 Intel RMM3 card Without the Intel RMM3 the advanced features are dormant 4 2 1 1 Intel Remote Management Module 3 Intel RMM3 The Intel RMM3 provides the BMC with an additional dedicated network interface The dedicated interface consumes its own LAN channel Additionally the Intel RMM3 provides additional flash sto
158. mental Specifications Intel Server Boards 5520HC SSSOOHCV and SS520HCT TPS 9 Design and Environmental Specifications 9 1 Intel Server Boards S5520HC S5500HCV and S5520HCT Design Specifications Operation of the Intel Server Boards S5520HC and or S5500HCV at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 71 Server Board Design Specifications PCW C TZ F to TTF Shock Packaged 20 pounds 36 inches 20 to 40 pounds 30 inches 40 to 80 pounds 24 inches 80 to 100 pounds 18 inches 100 to 120 pounds 12 inches 120 pounds 9 inches Vibration Unpackaged 5 Hz to 500 Hz 3 13 g RMS random Note Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature Disclaimer Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required
159. multiple fan profiles e Signal testing support The BMC provides test commands for setting and getting platform signal states e The BMC generates diagnostic beep codes for fault conditions e System GUID storage and retrieval e Front panel management The BMC controls the system status LED and chassis ID LED It supports secure lockout of certain front panel functionality and monitors button presses The chassis ID LED is turned on using a front panel button or a command e Power state retention e Power fault analysis e Intel Light Guided Diagnostics e Power unit management Support for power unit sensor The BMC handles power good dropout conditions e DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings e Address Resolution Protocol ARP The BMC sends and responds to ARPs supported on embedded NICs e Dynamic Host Configuration Protocol DHCP The BMC performs DHCP supported on embedded NICs e Platform environment control interface PECI thermal management support e E mail alerting e Embedded web server e Integrated KVM e Integrated Remote Media Redirection e Local Directory Access Protocol LDAP support e Intel Intelligent Power Node Manger support 62 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Platform Management 4 2 Optional Advanced Manage
160. nel C or F is unused The effective system memory is reduced by at least one half For example if the system is operating in the Mirrored Channel mode and the total size of the DDR3 DIMMs is 2 GB then the effective memory size is 1 GB because half of the DDR3 DIMMs are the secondary images If Channel C or F is populated the BIOS will disable the Mirrored Channel mode This is because the BIOS always gives preference to the maximization of memory capacity over memory RAS because RAS is an enhanced feature The BIOS provides a setup option to enable mirroring if the current DIMM population is valid for the Mirrored Channel mode of operation When memory mirroring is enabled the BIOS attempts to configure the memory system accordingly If the BIOS finds the DIMM population is not suitable for mirroring it falls back to the default Independent Channel mode with maximum interleaved memory 3 3 9 Memory Population and Upgrade Rules Populating and upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the following factors e Current RAS mode of operation e Existing DDR3 DIMM population e DDR3 DIMM characteristics 34 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture Optimization techniques used by the Intel Xeon Processor 5500 Series to maximize memory bandwidth In the Independent Channel mode all the DDR3 channels operate inde
161. ng although overall channel timing reduces according to the slowest DIMM 3 3 10 Supported Memory Configuration 3 3 10 1 Supported Memory Configurations The following sections describe the memory configurations supported and validated on the Intel Server Boards S5520HC S5500HCV and S5520HCT 3 3 10 1 1 Levels of support The following categories of memory configurations are supported Supported These configurations were verified by Intel to work but only limited validation was performed Not all possible DDR3 DIMM configurations were validated due to the large number of possible configuration combinations Supported configurations are highlighted in light gray in Tables 5 and 6 Validated These configurations have received broad validation by Intel Intel can provide customers with information on specific configurations that were validated Validated configurations are highlighted in dark gray in Tables 5 and 6 All populated DIMMs are identical The following is a description of the columns in Tables 5 and 6 36 X Indicates the DIMM is populated M Indicates whether the configuration supports the Mirrored Channel mode of operation It is one of the following Y indicating Yes N indicating No N Identifies the total number of DIMMs that constitute the given configuration Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture Table 5
162. ng table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen Table 46 Board Connector Matrix Connector Quantity Reference Designators Connector Type Pin Count Main power CPU 1 power Power supply 4 P S aux IPMB CPU U7J1 U7C1 CPU sockets 366 J4F1 J5F1 J5F2 J5F3 J6F1 Main memory 12 J6F2 J8F1 J8F2 J8F3 J9F1 J9F2 DIMM sockets 240 J9F3 24 8 CPU 2 Power 8 5 1 wo SAS Module Slot 1 J2J1 Mezzanine 50 Battery Mo BT5B1 Battery holder Stacked RJ45 2xUSB eg and duae 22 Wi woh ARI OD ALA TRIN 108 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Connector Header Locations and Pin outs Connector Quantity Reference Designators Connector Type Pin Count J1E6 CMOS Clear J1E2 ME Force Update J1E4 Password Clear J1E5 BIOS Recovery J1H1 BMC Force Update Empty on Intel Server Board S5500HCV Configuration jumpers 4 6 2 Power Connectors The main power supply connection uses an SSl compliant 2x12 pin connector J1K3 Three additional power related connectors also exist Two SSl compliant 2x4 pin power connectors J9A1 J9K1 to provide 12 V power to the CPU voltage regulators and memory One SSI compliant 1x5 pin connector J9K2 to provide 1 C monitoring of the power supply The following tables define these co
163. nnector pin outs Table 47 Main Power Connector Pin out J1K3 GND 5 Vde GND GND L sck 5 Vdc enD gea 7 GND Black 8 PWR OK SUE 5V White 9 svsB 5Vdc Red 12 Vdc 5Vde Red 12 Vdc bVdc Red Table 48 CPU 1 Power Connector Pin out J9A1 12 Vdc CPU1 Yellow black 6 12 Vdc CPU1 Yellow black DDR3_CPU1 Je gzen P DDR3 CPU1 Revision 1 8 109 Intel order number E39529 013 Connector Header Locations and Pin outs Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Table 49 CPU 2 Power Connector Pin out J9K1 1 GND of Pin 5 Black 2 GND of Pin 6 Black 6 12Vdc CPU2 Yellow black DDR3 CPU2 8 12 Vdc Yellow black DDR3 CPU2 Table 50 Power Supply Auxiliary Signal Connector Pin out J9K2 Pin Signal Color 1 SMB CLK FP PWR R Orange SMB DAT FP PWR R SMB_ALRT 3 ESB R Red 4 3 3 V SENSE Yellow 5 3 3 V SENSE Green 6 3 System Management Headers 6 3 1 A 34 pin Intel RMM3 connector J1C1 is includ Intel Remote Management Module 3 Connector ed on the server boards to support the optional Intel Remote Management Module 3 These server boards do not support third party management cards Note This connector is not compatible with the ntel Remote Management Module Intel RMM or the Intel Remote Management Module 2 Intel RMM2 Table 51 Intel RMM3 Connector Pin out J1C1 GND GND
164. nse The power supply should have remote sense return ReturnS to regulate out ground drops for all output voltages 3 3 V 5 V 12 V1 12 V2 12 V3 12 V4 12 V and 5 VSB The power supply should use remote sense to regulate out drops in the system for the 3 3 V 5 V and 12 V1 outputs The 12 V1 12 V2 12 V3 12 VA 12 V and 5V SB outputs only use remote sense referenced to the ReturnS signal The remote sense input impedance to the power supply must be greater than 200 O on 3 3 VS and 5 VS This is the value of the resistor connecting the remote sense to the output voltage internal to the power supply Remote sense must be able to regulate out a minimum of 200 mV drop The remote sense return ReturnS must be able to regulate out a minimum of 20 OmV drop in the power ground return The current in any remote sense line should be less than 5 mA to prevent voltage sensing errors The power supply must operate within specification over the full range of voltage drops from the power supply s output connector to the remote sense points 9 4 4 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise All outputs are measured with reference to the return remote sense signal ReturnS The 12 V3 12 V4 12 V and 5 VSB outputs are measured at the power supply connectors referen
165. nsions to the chipset deliver support for key elements of this new more protected platform They include 1 the capability to enforce memory protection policy 2 enhancements to protect data access from memory 3 protected channels to graphics and input output devices 4 and interfaces to the Trusted Platform Module Version 1 2 Keyboard and Mouse Enhancements to the keyboard and mouse enable communication between these input devices and applications running in a protected partition to take place without being observed or compromised by unauthorized software running on the platform Graphics Enhancements to the graphic subsystem enable applications running within a protected partition to send display information to the graphics frame buffer without being observed or compromised by unauthorized software running on the platform The TPM v 1 2 device Also called the Fixed Token is bound to the platform and connected to the PC s LPC bus The TPM provides the hardware based mechanism to store or seal keys and other data to the platform It also provides the hardware mechanism to report platform attestations 3 13 3 3 Enabling Intel TXT on Intel Server Board Intel TXT can be supported by Intel Server Board S5520HCT PBA E80888 553 or later version following steps describe how to set up Intel TXT feature Revision 1 8 55 Intel order number E39529 013 Functional Architecture Intel Server Boards S5520HC S5500HCV and S5520H
166. nt system cooling This does not apply to non redundant systems Power supply redundancy lost insufficient system power This does not apply to non redundant systems Note This state also occurs when AC power is first applied to the system This indicates the BMC is booting Green Blink Degraded Amber Blink Non critical AC power off if no degraded non critical critical or non recoverable conditions exist ot ES Notready System is powered down or S5 states if no degraded non critical critical or non recoverable conditions exist When the server is powered down transitions to the DC off state or S5 the BMC is still on standby power and retains the sensor and front panel status LED state established before the power down event If the system status is normal when the system is powered down the LED is in a solid green state the system status LED is off Revision 1 8 125 Intel order number E39529 013 Intel Light Guided Diagnostics Intel Server Boards 5520HC S5500HCV and 5520HCT TPS 8 4 DIMM Fault LEDs The server boards provide memory fault LED for each DIMM socket These LEDs are located as shown in the following figure The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs icu X H prc Keen CH O ii CPU 1 Socket bt 10H
167. ntel Server Board S5520HC or S5500HCV in any of following Intel Server Chassis Intel Server Chassis SC5600Base Intel Server Chassis SC5600BRP Intel Server Chassis SC5650DP Intel Server Chassis SC5650BRP Table 81 Compatible Chassis Heatsink Matrix Intel Thermal Solution i FXXRGTHSINK S5520HC S5500HCV Chassis SKU Heatsink includes STS100C w fan Active tel Thermal Solution j gedet STS100A Active Passive Tower Heatsink Y Y SC5600Base No Y Y N Y Y SC5600BRP No Y Y N Y Y SC5600LX No N N Required Y Y SC5650DP No Y Y N Y Y SC5650BRP No Y Y N Y Support Maximum CPU N Not Support Sahel 95W 80 W 95 W Support in Intel Server Revision 1 8 Intel order number E39529 013 147 Appendix B Compatible Intel Server Chassis Intel Server Boards S5520HC SSSOOHCV and S5520HCT TPS Heatsink Includes Intel Thermal Solution STS100C w fan Active Intel Thermal Solution FXXRGTHSINK S5520HC S5500HCV Chassis SKU STS100A Active Passive Tower Heatsink mode Chassis Boxed BXSTS100C BXSTS100A FXXRGTHSINK Product Code Note Must install active processor heatsink with the airflow direction as shown in the following figure when installing in a compatible Intel Server Chassis 148 Intel order number E39529 013 Revision 1 8 Intel Server Boards 5520HC SSSOOHCV and SSS20H
168. oard 0x91 Disabling the keyboard 0x92 Detecting the presence of the keyboard 0x93 Enabling the keyboard 0x94 Clearing keyboard input buffer 0x95 Instructing keyboard controller to run Self Test PS 2 only Mouse only USB 0x98 Resetting the mouse 0x99 Detecting the mouse Ox9A Detecting the presence of mouse Ox9B Enabling the mouse Fixed Media O0xBO Resetting fixed media device OxB1 Disabling fixed media device 0xB2 Detecting the presence of a fixed media device hard drive detection etc 0xB3 Enabling configuring a fixed media device Removable Media Revision 1 8 Intel order number E39529 013 163 Appendix E POST Code Diagnostic LED Decoder Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Progress Code Progress Code Definition 0xB8 Resetting the removable media device OxB9 Disabling the removable media device OxBA Detecting the presence of a removable media device CDROM detection etc OxBC Enabling configuring a removable media device Boot Device Select ion OxDy Trying boot selection y where y 0 to F Pre EFI Initializatio n PEI Core not accompanied by a beep code OxEO Started dispatching early initialization modules PEIM OxE2 Initial memory found configured and installed correctly OxE1 0xE3 Reserved for initialization module use PEIM Driver e
169. of the server boards and is labeled 5VSB LED It is illuminated when AC power is applied to the platform and 5 V stand by voltage is supplied to the server board by the power supply SUERG Enn SMES mm mm umm o ES o IOH B 5 volt Standy by LED Oo Sl ms OLI sie EIE IR LID sls gie HI HAS 8 8 s o0 Figure 54 5 volt Stand by Status LED Location 122 Revision 1 8 Intel order number E39529 013 Intel Server Boards SS520HC S5500HCV and 5520HCT TPS Intel Light Guided Diagnostics 8 2 Fan Fault LED s Fan fault LEDs are present for the two CPU fans and the one rear system fan The fan fault LEDs illuminate when the corresponding fan has fault System Fan 5 Fault LED CPU 1 Fan Fault LED
170. of this part is below the limit requirement in SJ T 11363 2006 x XGRUCB SB EUIS JE E 199 8 Tir 852 BB SJ T 11363 2006 f PATE AY IR EB BE SK x Indicates that this hazardous substance contained in at least one of the homogeneous materials of this part is above the limit requirement in SJ T 11363 2006 WHE 2 HBSHIEEST m ZR S o2 n E SERA e ER m ECARE ER E r mt A RES th RISE SS E PUR PH TIA SIME This table shows where these substances may be found in the supply chain of our electronic information products as of the date of sale of the enclosed product Note that some of the component types listed above may or may not be a part of the enclosed product Revision 1 8 143 Intel order number E39529 013 Regulatory and Certification Information Intel Server Boards 5520HC S5500HCV and S5520HCT TPS 10 6 China Packaging Recycle Marks or GB18455 2001 Intel EPSD has the following ecological compliances Cardboard and fiberboard packaging will be marked as recyclable in China China Packaging Recycling Marks is required on retail packaging to be marked as recyclable using China s recycling logo Due to regional variances in mark acceptances all three marks accepted worldwide will be implemented on Intel s cardboard and fiberboard Examples of marks are shown below EI es S Ce 10 7 CA Perchlorate Warning CA Lithium Perchlorate Warning California Code of Regulations Title 22 Division 4 5 Chapter 33 Best Managem
171. oller is within the IOH providing the Intel Server Platform Services SPS The controller is also commonly referred to as the Manageability Engine ME The functionality provided by the SPS firmware is different from Intel Active Management Technology Intel AMT provided by the ME on client platforms 70 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS CPU2 QPI ISO A r 1 3 3VSB 3 3v 5B amp CPU 1 L3 I amp CH D IOH SMBus OxE 0 PEHPSMB ME T d e Es T d i ICH10R SMBus 0x88 SMLink NIC 82575EB SMBus OxC6 OaC8 Revision 1 8 Qi 33V STBY LAN BUS a c WSTBYUNKBUS He Platform Management Intel order number E39529 013 REPEATER SMBus 5 3 3VSB 3 3V ux PCA9515 1 DDR3 DIMMS 2 3 CPU2 CH AO CPU1 CH AO 4 CLK509B E 74HC4052 34 oxao SG 0xA0 2 c cN CPU2 CH A1 CPU1 CH A1 pum 8 XDPO LD E QxA2 L DB803 CPU2 CH BO CPU1 CH BO 1 OxAA KL OxAA L J 0xDC r FRU Geen CPU2 CH B1 CPU1 CH B1 1 wao OxA8 ch AT24C64 ISL90728 OnAB Pi VREF FOR DIMM E E CHANNEL A B C FRONT PANEL FRU OxAE Y CPU2 CH CO CPU1 CH CO rege d 1SL90727 1 xa Oxas NEP IR NES VREF FOR DIMM r CHANNEL DEE CPU2 CH C1 CPU1 CH C1 TEMP SENSOR ox5c L OxAA QxAA
172. oltage placed on its outputs typically a leakage voltage through the system from stand by output up to 500 mV There should be no additional heat generated or stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously It also should not trip the power supply protection circuits during turn on Residual voltage at the power supply outputs for a no load condition should not exceed 100 mV when AC voltage is applied and the PSON signal is de asserted 136 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and 5520HCT TPS Regulatory and Certification Information 10 Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations before computer integration make sure that the chassis power supply and other modules have passed EMC testing using a server board with a microprocessor from the same family or higher and operating at the same or higher speed as the microprocessor used on this server board The final configuration of your end system product may require additional EMC compliance testing For more information please contact your local Intel Representative This is an FCC Class A device Integration of it into a Class B chassis does not result in a Class B device 10 1 Product Regulatory Compliance Intended Application This product was evaluated as Information Technology Equipm
173. on the system It does this by enabling an environment where applications can run within their own space protected from all other software on the system These capabilities provide the protection mechanisms rooted in hardware that are necessary to provide trust in the application s execution environment In turn this can help to protect vital data and processes from being compromised by malicious software running on the platform Long available on client platforms Intel is now enabling Intel TXT on selected server platforms as well 3 13 3 2 Intel TXT hardware overview Implementation of a Trusted Execution Technology enabled platform requires a number of hardware enhancements Key hardware elements of this platform are Processor Extensions to the IA 32 architecture allow for the creation of multiple execution environments or partitions This allows for the coexistence of a standard legacy partition and protected partition where software can run in isolation in the protected partition free from being observed or compromised by other software running on the platform Access to hardware resources such as memory is hardened by enhancements in the processor and chipset hardware Other processor enhancements include 1 event handling to reduce the vulnerability of data exposed through system events 2 instructions to manage the protected execution environment 3 and instructions to establish a more secure software stack Chipset Exte
174. on System and Unified Back Plate Assembly 26 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture 3 3 Memory Subsystem The Intel Xeon Processor 5500 Series on the Intel Server Boards S5520HC S5500HCV and S5520HCT are populated on CPU sockets Each processor installed on the CPU socket has an integrated memory controller IMC which supports up to three DDR3 channels and groups DIMMs on the server boards into autonomous memory 3 3 1 Memory Subsystem Nomenclature The nomenclature for DIMM sockets implemented in the Intel Server Boards S5520HC S5500HCV and S5520HCT is represented in the following figures e DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets e The memory channels for CPU 1 socket are identified as Channels A B and C The memory channels for CPU 2 socket are identified as Channels D E and F e The DIMM identifiers on the silkscreen on the board provide information about which channel CPU Socket they belong to For example DIMM A is the first slot on Channel A of CPU 1 socket DIMM D1 is the first slot on Channel D of CPU 2 Socket e Processor sockets are self contained and autonomous However all configurations in the BIOS setup such as RAS Error Management and so forth are applied commonly across sockets The Intel Server Board S5520HC supports six DDR3 memory channels three ch
175. ons cerent 128 9 1 Intel Server Boards S5520HC S5500HCV and S5520HCT Design Specifications128 9 2 OR EE 128 9 3 Server Board Power Requirements ssssssssssssssseeeen een 130 9 3 1 Processor Power Support ssesssssssssssesse eene nennen tenete nennen 131 9 4 Power Supply Output Requirements ssssssssssseee 131 9 4 1 Grounding s nii tee ne bec M tea 131 9 4 2 otand by Re 131 9 4 3 Remote Serse uei tee e LEER tha Ee ERE Ert EE Rex eehed eaaa ten 132 vi Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Table of Contents 9 4 4 Voltage Regulation te rt Fe RR ERE ERR ELE RR ERE EANA 132 9 4 5 Dynamic Loading icr eee Re EPOR Pete ree ete uo Hein 132 9 4 6 Capacitive Loading EE 133 9 4 7 A ojel Thr e 133 9 4 8 Timing Requirements AE 133 9 4 9 Residual Voltage Immunity in Stand by Mode 136 10 Regulatory and Certification Information eeeeeeeeeee eere 137 10 1 Product Regulatory Compliance seen 137 10 1 1 Product Safety Compliance 20 0 0 cece cccececeeececceceeeeeeeeeeeeeeeseeteseceaeeeeeeeseseneeeeeeees 137 10 1 2 Product EMC Compliance Class A Complance rne 137 10 1 3 Certifications Registrations Declarations sssssseseeseenrree terrer tnrererrrrnrnereerrrnee ee 138 10 2 Product Regulatory Compliance Markings ssssseeeeee 138
176. or one or two Intel Xeon Processor s 5600 series up to 130W Thermal Design Power 4 8 GT s 5 86 GT s and 6 4 GT s Intel QuickPath Interconnect Intel QPI FC LGA 1366 Socket B Enterprise Voltage Regulator Down EVRD 11 1 Memory Six memory channels three channels for each processor socket Channels A B C D E and F Support for 800 1066 1333 MT s ECC Registered DDR3 Memory RDIMM ECC Unbuffered DDR3 memory UDIMM No support for mixing of RDIMMs and UDIMMs Intel Server Board 5520HC S5520HCT 12DIMM slots Two DIMM slots per channel Intel Server Board S5500HCV Nine DIMM slots Two DIMM slots on Channels A B and C One DIMM slot on Channels D E and F Chipset Intel Server Board 5520HC S5520HCT Intel 5520 Chipset Intel 82801JIR I O Controller Hub ICH10R Intel Server Board S5500HCV Intel 5500 Chipset Intel 82801JIR I O Controller Hub ICH10R Cooling Fan Support Support for e Two processor fans 4 pin headers e Four front system fans 6 pin headers e One rear system fans 4 pin header e 3 pin fans are compatible with all fan headers 2 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Overview Add in Card Slots e Intel Server Board S5520HC S5520HCT Six expansion slots One full length full height PCI Express Gen2 slot x16 Mechanically x8 Electrically Three full length full height PCI Express Gen2 x8 slo
177. ory Scrub Engine The Intel Xeon Processor 5500 Series incorporates a memory scrub engine which performs periodic checks on the memory cells and identifies and corrects single bit errors Two types of scrubbing operations are supported e Demand scrubbing Executes when an error is encountered during normal read write of data e Patrol scrubbing Proactively walks through populated memory space seeking soft errors The BIOS enables both demand scrubbing and patrol scrubbing by default Demand scrubbing is not possible when memory mirroring is enabled Therefore if the memory is configured for mirroring the BIOS disables it automatically 3 3 8 Memory RAS 3 3 8 1 RAS Features The Intel Server Boards S5520HC S5500HCV and S5520HCT support the following memory channel modes e Independent Channel Mode e Mirrored Channel Mode providing Channel RAS feature These channel modes are used in conjunction with the standard Memory Test Built in Self Test BIST and Memory Scrub engines to provide full RAS support Channel RAS feature are supported only if both CPU sockets are populated and support the right population For more information refer to Section 3 3 9 Revision 1 8 33 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 3 3 8 2 Independent Channel Mode In the Independent Channel mode you can populate multiple channels on any channel in any order Th
178. oss Stay Off Last state Reset System action to take on AC power loss recovery Stay Off System stays off Last State System returns to the same state before the AC power loss Reset System powers on If enabled clears the System Event Log All current entries will be lost Note This option is reset to Disabled after a reboot Clear System Event Enabled Log Disabled FRB 2 Enable Enabled Fault Resilient Boot FRB Disabled If enabled the BIOS programs the BMC watchdog timer for approximately 6 minutes If the BIOS does not complete POST before the timer expires the BMC resets the system Revision 1 8 95 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC S5500HCV and S5520HCT TPS Setup Item Help Text O S Boot Watchdog Enabled If enabled the BIOS programs the watchdog timer Timer Disabled with the timeout value selected If the OS does not complete booting before the timer expires the BMC resets the system and an error is logged Requires OS support or Intel Management Software O S Boot Watchdog Power Off If the OS boot watchdog timer is enabled this is the Grayed out when O S Boot Timer Policy Reset system action taken if the watchdog timer expires Watchdog Timer is Reset System performs a reset disabled Power Off System powers off O S Boot Watchdog 5 minutes If the OS watchdog timer is enabled this is the Grayed out when O S Boot Timer Timeout 10
179. out Zone Revision 1 8 13 Intel order number E39529 013 Overview Intel Server Boards S5520HC 5500HCV and S5520HCT TPS COMPONENT HEIGHT RESTRICTION 0 200 MAX 2 PLACES COMPONENT HEIGHT RESTRICTIO 0 200 MAX 24 PLACES COMPONENT HEIGHT RESTRICTION 0 250 MAX 5 PLACES o o L2 CARD SIDE COMPONENT HEIGHT LIMIT 0 500 MAX Oo AALALA Figure 10 Primary Side Card Side Keep out Zone 14 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Overview 450 400 GROUND PADS 10 PLACES 10 16 SOCKEY CAVITY 1 8MM COMPONENT HEIGHT RESTRICTION 2 PLACES 1 8MM COMPONENT HEIGHT RESTRICTION 2 PLACES Oh K BACKPLATE ERA NO COMPONENT TONE 2 PLACES PU HEATSIN NTING Al 2 000 TYP OTHER BOARD MOUNTING KEEPOUT AREA NO COMPONENT ZONE 10 PLACES BASEBOARD MOUNTING RESTRICTED AREA LIMITED COMPONENT HEIGHT 0 058 MAX 10 PLACES 1 000 TYP D 25 40 R BASEBOARD MOUNTING KEEPOUT AREA NO COMPONENT ZONE 10 PLACES 0 236 MOUNTING HOLE AREA 6 00 NO COMPONENT NO ROUTING ZONE 16 PLACES RUBBER PAD LOCATION NO COMPONENT ZONE 5 PLACES Figure 11 Second Side Keep out Zone Revision 1 8 15 Intel order number E39529 013 Overview Intel Server Boards S5520HC 5500HCV and S5520HCT TPS 2 1 3 Server Board Rear UO Layout The following drawing shows the layout of the rear UO components for the server boards i l
180. pendently Also you can use the Independent Channel mode to support single DIMM configuration in Channel A and in the Single Channel mode You must observe and apply the following general rules when selecting and configuring memory to obtain the best performance from the system Pu Se ES 10 11 12 13 Mixing RDIMMs and UDIMMs is not supported You must populate CPU1 socket first in order to enable and operate CPU2 socket When CPU2 socket is empty DIMMs populated in slots D1 through F2 are unusable If both CPU sockets are populated but Channels A through C are empty the platform can still function with remote memory in Channels D through F However platform performance suffers latency due to remote memory Must always start populating DDR3 DIMMs in the first slot on each memory channel Memory slot A1 B1 C1 D1 E1 or F1 For example if memory slot A1 is empty slot A2 is not available Must always populate the Quad Rank DIMM starting with the first slot Memory slot A1 B1 C1 D1 E1 or F1 on each memory channel For example when installing one Quad Rank RDIMM with one Single or Dual Rank RDIMM in memory channel A you must populate the Quad Rank RDIMM in slot A1 If an installed DDR3 DIMM has faulty or incompatible SPD data it is ignored during memory initialization and is essentially disabled by the BIOS If a DDR3 DIMM has no or missing SPD information the slot in which it is placed is treated as empty
181. processor Displays 0192 Processor 0x cache size mismatch detected message in the Error Manager Halts the system and will not boot until the fault condition is remedied If the frequencies for all processors cannot be adjusted to be the same then the BIOS remedied Processor frequency Halt The BIOS detects the error condition and responds as follows speed not identical Adjusts all processor frequencies to the highest common frequency No error is generated this is not an error condition Continues to boot the system successfully Logs the error into the SEL Displays 0197 Processor Ox family is not supported message in the Error Manager Halts the system and will not boot until the fault condition is Revision 1 8 23 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS System Action Processor Intel Halt The BIOS detects the error condition and responds as follows QuickPath Adjusts all processor QPI frequencies to highest common frequency Interconnect speeds N d thisi diti not identical o error is generated this is not an error condition Continues to boot the system successfully If the link speeds for all QPI links cannot be adjusted to be the same then the BIOS Logs the error into the SEL Displays 0195 Processor 0x Intel QPI speed mismatch message in the Error Manager Halts the system and wil
182. rage for advanced features such as WS MAN 4 2 2 Keyboard Video and Mouse KVM Redirection The advanced management features include support for keyboard video and mouse redirection KVM over LAN This feature is available remotely from the embedded web server as a Java applet The client system must have a Java Runtime Environment JRE Version 1 6 Revision 1 8 63 Intel order number E39529 013 Platform Management Intel Server Boards 5520HC SSSOOHCYV and S5520HCT TPS JRE6 or later to run the KVM or media redirection applets You can download the latest Java Runtime Environment JRE update http java com en download index jsp This feature is only enabled when the Intel RMM3 is present Note KVM Redirection is only available with onboard video controller and the onboard video controller must be enabled and used as the primary video output The BIOS will detect one set of USB keyboard and mouse for the KVM redirection function of Intel RMM3 even if no presence of RMM3 is detected Users will see one set of USB keyboard and mouse in addition to the local USB connection on the BIOS Setup USB screen with or without RMM3 installed 4 2 2 1 Keyboard and Mouse The keyboard and mouse are emulated by the BMC as USB human interface devices 4 2 2 2 Video Video output from the KVM subsystem is equivalent to video output on the local console via onboard video controller Video redirection is available once video is initialize
183. rd When a single processor is installed no terminator is required in the second processor socket For optimum performance when two processors are installed both must be the identical revision and have the same core voltage and Intel QPl core speed 3 2 2 Mixed Processor Configurations The following table describes mixed processor conditions and recommended actions for the Intel Server Boards S5520HC S5500HCV and S5520HCT Errors fall into one of three categories e Halt If the system can boot it pauses at a blank screen with the text Unrecoverable fatal error found System will not boot until the error is resolved and Press F2 to enter setup regardless of if the Post Error Pause setup option is enabled or disabled After entering setup the error message displays on the Error Manager screen and an error is logged to the System Event Log SEL with the error code The system cannot boot unless the error is resolved The user needs to replace the faulty part and restart the system e Pause If the Post Error Pause setup option is enabled the system goes directly to the Error Manager screen to display the error and log the error code to SEL Otherwise the system continues to boot and no prompt is given for the error although the error code is logged to the Error Manager and in a SEL message e Minor The message is displayed on the screen or on the Error Manager screen The system continues booting in a degraded stat
184. rder Note that while you can delete the Internal EFI Shell in this screen it is restored to the Boot Order on the next reboot You cannot permanently delete the Internal EFI Shell To access this screen from the Main screen select Boot Options Delete Boot Options Boot Options Delete Boot Option Delete Boot Option Select one to Delete Internal EFI Shell Figure 44 Setup Utility Delete Boot Option Screen Display Table 37 Setup Utility Delete Boot Option Fields Setup Item Help Text Delete Boot Option Select one to Delete Remove an EFI boot option from the If the EFI shell is deleted Internal EFI Shell boot order it is restored on the next system reboot It cannot be permanently deleted 5 3 2 6 3 Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks To access this screen from the Main screen select Boot Options Hard Disk Order Boot Options Hard Disk 1 lt Available Hard Disks gt Hard Disk 2 lt Available Hard Disks gt Figure 45 Setup Utility Hard Disk Order Screen Display Table 38 Setup Utility Hard Disk Order Fields Setup Hem Options Help Text Hard Disk 1 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group Hard Disk 2 Available Set system boot order by selecting the boot Legacy devices option for this position for this Device group 102 Revision
185. rder number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS List of Tables This page intentionally left blank Revision 1 8 xiii Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Introduction 1 Introduction This Technical Product Specification TPS provides board specific information detailing the features functionality and high level architecture of the Intel Server Boards S5520HC S5500HCV and S5520HCT In addition you can obtain design level information for a given subsystem by ordering the External Product Specifications EPS for the specific subsystem EPS documents are not publicly available and you must order them through your local Intel representative 1 1 Chapter Outline This document is divided into the following chapters Chapter 1 Introduction Chapter 2 Overview Chapter 3 Functional Architecture Chapter 4 Platform Management Chapter 5 BIOS Setup Utility Chapter 6 Connector Header Locations and Pin outs Chapter 7 Jumper Blocks Chapter 8 Intel Light Guided Diagnostics Chapter 9 Design and Environmental Specifications Chapter 10 Regulatory and Certification Information Appendix A Integration and Usage Tips Appendix B Compatible Intel Server Chassis Appendix C BMC Sensor Tables Appendix D Platform Specific BMC Appendix Appendix E POST Code Diagnostic LED D
186. retail products are provided with EFUP marking e For Business to Business products Intel intends to place EFUP marking on product for customer convenience e EFUP for Intel server products has been determined as 20 years Below is an example of EFUP mark applied to Intel server products Go Revision 1 8 141 Intel order number E39529 013 Regulatory and Certification Information Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS CROHS Substance Tables China CRoHS requires products to be provided with controlled substance information Intel understands the end seller entity placing product into market place is responsible for providing the controlled substance information Controlled substance information is required to be in Simplified Chinese Substance table for this board product is as follows 142 Revision 1 8 Intel order number E39529 013 Intel Server Boards 55520HC S5500HCV and 5520HCT TPS Regulatory and Certification Information ew CC TE eg SAXESEISZE HEB Management Methods on Control of Pollution from Electronic Information Products China RoHS declaration Pug UBERBEUBRIBSTESE Sim A88 EM SIUS Parts f E fa AUME SOREUCR SRAM Pb Hg Cd Cr6 PBB PBDE m Metal Parts FD p dx 8 It Printed Board Assemblies x PBA o RUCBSBEURIERSMEUSISIE MT REEE SIT 11363 2006 En SE xe RS PR KIA o Indicates that this hazardous substance contained in all homogeneous materials
187. rity Error is logged as such in the SEL but in all other ways is treated the same as an Uncorrectable ECC Error 38 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Functional Architecture 3 4 CH10R The ICH10R provides extensive I O support Functions and capabilities include PCI Express Base Specification Revision 1 1 support PCI Local Bus Specification Revision 2 3 support for 33 MHz PCI operations supports up to four REQ GNT pairs ACPI Power Management Logic Support Revision 3 0a Enhanced DMA controller interrupt controller and timer functions Integrated Serial ATA host controllers with independent DMA operation on up to six ports and AHCI support USB host interface with support for up to 12 USB ports six UHCI host controllers and two EHCI high speed USB 2 0 host controllers Integrated 10 100 1000 Gigabit Ethernet MAC with System Defense System Management Bus SMBus Specification Version 2 0 with additional support for I C devices Low Pin Count LPC interface support Firmware Hub FWH interface support Serial Peripheral Interface SPI support 3 4 1 Serial ATA Support The ICH10R has an integrated Serial ATA SATA controller that supports independent DMA operation on six ports and supports data transfer rates of up to 3 0 Gb s The six SATA ports on the server boards are numbered SATA O through SATA 5 You can enable disable t
188. rk Device Order BEV Device Order Add New Boot Option gt Delete Boot Option EFI Optimized Boot Enabled Disabled Use Legacy Video for EFI OS Enabled Disabled Boot Option Retry Enabled Disabled USB Boot Priority Enabled Disabled Figure 42 Setup Utility Boot Options Screen Display Revision 1 8 99 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards S5520HC 5500HCV and S5520HCT TPS Table 35 Setup Utility Boot Options Screen Fields 0 65535 Setup Item Boot Timeout Help Text The number of seconds the BIOS should pause at the end of POST to allow the user to press the F2 key for entering the BIOS Setup utility Valid values are 0 65535 Zero is the default A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot Set system boot order by selecting the boot option for this position Boot Option x Available boot devices Hard Disk Order Set the order of the legacy devices in this group CDROM Order Set the order of the legacy devices in this group Floppy Order Set the order of the legacy devices in this group Network Device Order Set the order of the legacy devices in this group BEV Device Order Set the order of the legacy devices in this group Add New Boot Option Add a new EFI boot option to the boot order Delete Boot Option Remove an EFI boot option from the boot order Enabled Disabled
189. s as configured after running the FRUSDR utility and selecting the Non Intel Chassis option is limited to only the CPU fans The BMC only requires the processor thermal sensor data to determine how fast to operate these fans The remaining system fans will operate at 10096 operating limits due to unknown variables associated with the given chassis and its fans Therefore regardless of whether the system is configured for Performance Mode or Acoustics Mode the system fans will always run at 10096 operating levels providing for maximum airflow In this scenario the Performance and Acoustic mode settings only affect the allowable performance of the memory higher BW for the Performance mode 44 Intel Intelligent Power Node Manager Intel Intelligent Power Node Manager is a platform system level solution that provides the system with a method of monitoring power consumption and thermal output and adjusting system variables to control those factors The BMC supports Intel Intelligent Power Node Manager specification version 1 5 Additionally the platform must have an Intel Intelligent Power Node Manager capable Manageability Engine ME firmware installed The BMC firmware implements power management features based on the Power Management Bus PMBus 1 1 Specification Note Intelligent Power Node Manager is only available on platforms that support PMBus compliant power supplies 44 1 Manageability Engine ME An embedded ARC contr
190. seeeemmeenmemeen 130 Output Voltage Timing 134 Turn On Off Timing Power Supply Signals sees 135 Active Processor Heatsink Installation Reouirement 149 Diagnostic LED Placement Diagram sssssssssssenemmen 161 Intel order number E39529 013 List of Tab les Intel Server Boards S5520HC S5500HCV and S5520HCT TPS List of Tables Table 1 IOH High Level Summary ssssssssssssssseeseeneenmeneee nennen nnne n nennen nennen 20 Table 2 Mixed Processor Configurations nennen 23 Table 3 Memory Running Frequency vs Processor SKU ccccccecececeeeseeessseesssseeseesaeeeaeeees 31 Table 4 Memory Running Frequency vs Memory Populatton nnee 31 Table 5 Supported DIMM Population under the Dual Processors Configuration 37 Table 6 Supported DIMM Population under the Single Processor Configuration 37 Table 7 Onboard SATA Storage Mode Matrix 40 Table 8 Intel Server Board S5520HC PCI Bus Segment Characteristics 42 Table 9 Intel Server Board S5500HCV PCI Bus Segment Characteristics 43 Table 10 Intel Server Board S5520HC PCI Riser Slot Slot pi 43 Table 11 PCI Riser Support 43 Table 12 Intel SAS Entry RAID Module AXX4SASMOD Storage Mode n se 46 Table 13 Serial B Header Pin out sess nenne rines nnns 49 Table 14 Video Modes teret tres eR E EE Ee 50 Table 15 On
191. t the installation of a USB device inside the server chassis Table 66 Internal Type A USB Port Pin out J1H2 Signal Name USB_PWR7_5V USB_PWR 2 USB ICH P7N USB port 7 negative signal 3 USB ICH P7P USB port 7 positive signal 4 GND Ground 6 6 Fan Headers The server boards provide three SSI compliant 4 pin and four SSI compliant 6 pin fan headers to use as CPU and I O cooling fans 3 pin fans are supported on all fan headers 6 pin fans are supported on headers J1K1 J1K2 J1K4 and J1K5 4 pin fans are supported on headers J1K1 J1K2 J1K4 J1K5 J7K1 J9A2 and J9A3 The pin configuration for each of the 4 pin and 6 pin fan headers is identical and defined in the following tables e Two 4 pin fan headers are designated as processor cooling fans CPU1 fan J9A2 CPU2 fan J7K1 e Four 6 pin fan headers are designated as hot swap system fans Hot swap system fan 1 J1K1 Hot swap system fan 2 J1K4 Hot swap system fan 3 J1K2 Hot swap system fan 4 J1K5 e One 4 pin fan header is designated as a rear system fan System fan 5 J9A3 116 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Connector Header Locations and Pin outs Table 67 SSI 4 pin Fan Header Pin out J7K1 J9A2 J9A3 Signal Name 1 Ground GND Ground is the power supply ground 2 12V Power Power supply 12 V 3 FanTach in FAN TACH signal is connected to the BMC to
192. taneously 9 4 6 Capacitive Loading The power supply should be stable and meet all requirements within the following capacitive loading range Table 77 Capacitive Loading Conditions Output Minimum Maximum Units 3 3V 250 6800 uF 5V 400 4700 uF 12V1 12V2 12V3 12V4 500 each 11 000 uF 12V 1 350 uF 5VSB 20 350 uF 9 4 7 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in the following table This is measured over a bandwidth of 0 Hz to 20 MHZ at the power supply output connectors A 10 uF tantalum capacitor in parallel with a 0 1 uF ceramic capacitor are placed at the point of measurement Table 78 Ripple and Noise 3 3V 5V 12V1 12V2 12V3 12V4 12V 5 VSB 50 mVp p 50 mVp p 120 mVp p 120 mVp p 50 mVp p 9 4 8 Timing Requirements The following are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tvout_rise within 5 ms to 70 ms 5 VSB is allowed to rise from 1 0 ms to 25 ms 3 3 V 5 V and 12 V output voltages should start to rise approximately at the same time All outputs must rise monotonically Each output voltage should reach regulation within 50 ms Tyout on of each other during turn on of the power supply Each output voltage should fall out of regulation within 400 msec Tyout_o of each other during turn off The following tables and d
193. tel Server Boards S5520HC S5500HCV and 5520HCT including voltage and current specifications and power supply on off sequencing characteristics The following diagram shows the power distribution implemented on these server boards 0 75V ODRI Vtt SO 4 1A kd 9 75V DORI Vit 5024 1A Y ICH10R 1 05V Sa Figure 59 Power Distribution Block Diagram 130 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Design and Environmental Specifications 9 3 1 Processor Power Support The server boards support the Thermal Design Power TDP guideline for Intel Xeon processors The Flexible Motherboard Guidelines FMB were also followed to determine the suggested thermal and current design values for anticipating future processor needs The following table provides maximum values for lc TDP power and TcAse for the compatible Intel Xeon Processor 5500 series Table 73 Intel Xeon Processor Dual Processor TDP Guidelines Max Tcase TDE Power Thermal Profile A Thermal Profile B Ice Max 95 W 75 C 81 C 120A 9 4 Power Supply Output Requirements This section is for reference purposes only The intent is to provide guidance to system designers to determine a power supply to use with these server boards This section specifies the power supply requirements Intel used to develop a power supply for its 5U server system The combined power
194. tel order number E39529 013 Functional Architecture Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Aptio Setup Utility Copyright C 2009 American Megatrends Inc EUREN Securit idm nistrator to contro Set Administrator Password set User Password F Panel Toko Note rront Panel LOCKOUT L Note must be set in order tc fuser account iNo perationl Select S Se lect Change Version 1 23 1114 Copyright C 2009 American Megatrends Inc Figure 24 TPM activated 5 Go to BIOS Setup Menu Advanced gt Processor Configuration set Intel VT for directed UO and Intel TXT option as Enabled 58 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Functional Architecture fiptio Setup Utility Copyright C 2009 American Megatrends Inc Advanced ion Technology cted L U T h 1M D F TF wil ugn DMA L LEN ii Intel R TXT Enabled Hardware Prefetcher Enabled nt Cache Line Lache Access DLA Version 1 23 1114 Copyright C 2009 American Megatrends Inc Figure 25 BIOS setting for TXT 6 Press F10 to save and exit now Intel TXT is successfully enabled 3 14 ACPI Support The Intel Server Boards S5520HC S5500HCV and S5520HCT support S0 S1 and S5 states S1 is considered a sleep state The Intel Server Boards S5520HC S5500HCV and S5520HCT can wake up from S1 state using the USB devices in addition to
195. tem A TPM device provides secured storage to store data such as security keys and passwords In addition a TPM device has encryption and hash functions The Intel Server Board S5520HCT implements TPM as per TPM PC Client specifications revision 1 2 by the Trusted Computing Group TCG A TPM device is affixed to the motherboard of the server and is secured from external software attacks and physical theft A pre boot environment such as the BIOS and operating system loader uses the TPM to collect and store unique measurements from multiple factors within the boot process to create a system fingerprint This unique fingerprint remains the same unless the pre boot environment is tampered with Therefore it is used to compare to future measurements to verify the integrity of the boot process After the BIOS complete the measurement of its boot process it hands off control to the operating system loader and in turn to the operating system If the operating system is TPM enabled it compares the BIOS TPM measurements to those of previous boots to make sure the system was not tampered with before continuing the operating system boot process Once the operating system is in operation it optionally uses TPM to provide additional system and data security for example Microsoft Vista supports Bitlocker drive encryption 3 13 2 TPM security BIOS The BIOS TPM support conforms to the TPM PC Client Specific Implementation Specification for Convent
196. teretrrntrterttrnrtntrrrnrnrnneeerrrne reene 110 6 3 1 Intel Remote Management Module 3 Connector 110 6 3 2 EGP IPMB Header 2 6 er meto a ald em RH uere a 111 6 3 3 HSBR Ee 111 6 3 4 SGPIO Header oet RU b aec a GER ER eee 111 6 4 Front Panel Connector den bip baec demande call 111 6 5 ege elle TEE 112 6 5 1 VGA ln ue e nine Bue cet eee OM LO ae Meese Lees 112 6 5 2 NIC Conrnectors a a RE e e ni HERE EE E t e REEL Rea tate 113 6 5 3 SATA e elei ee c ES 113 6 5 4 SAS Module Slot hinein erected ec d eee tede dct a rive eee pes 113 6 5 5 Serial Port Connectors EE 114 6 5 6 USB Gornn eGtor eerie beide ere aee tee dite ep ab eee beee red 115 6 6 Farm Headers EE 116 ONE Te Blocks aaa iate NT PUES 118 7 1 CMOS Clear and Password Reset Usage Procedure ssssesssssseserrrreererrrrereeee 119 7 1 1 Clearing tlie C MOS uiuere AAA te ce epe EE eee Seneca HEP o a ee edd 119 7 1 2 Clearing the Password 119 7 2 Force BMC Update Procedure enne 120 7 8 BIOS Recovery Jumper nennen nere nnne nennen nens 120 8 Intel Light Guided Diagnostics esee rennen ternera ttes te ttn sn sea tte sa sensnias 122 8 1 b volt Stand by LED iii cer pron e o ee ER pede 122 8 2 Fan Fault BED S 5 eo itr eo d a Ha eb con eon T v Fed Te elen 123 8 3 System ID LED and System Status LED 124 8 4 DIMM Fault LEDS iet phe ertet end ecran dede tI 126 8 5 Post Code Diagnostic LED 127 9 Design and Environmental Specificati
197. the BIOS outputs the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information The class and subclass fields point to the type of hardware being initialized The operation field represents the specific initialization activity Based on the data bit availability to display progress codes you can customize a progress code to fit the data width The higher the data bit the higher the granularity of information that can be sent on the progress port The system BIOS or option ROMs may report progress codes The Response section in the following table is divided into three types e No Pause The message is displayed on the screen or on the Error Manager screen The system continues booting in a degraded state The user may want to replace the erroneous unit The POST Error Pause option setting in the BIOS setup does not have any effect on this error e Pause The message is displayed on the Error Manager screen and an error is logged to the SEL The POST Error Pause option setting in the BIOS setup determines whether the system pauses to the Error Manager for this type of error so the user can take immediate corrective action or the system continues booting Note that for 0048 Password check failed the system will halt and then after the next reset reboot it displays the error code in the Error Manager screen e Halt The system h
198. the I O subsystem This chapter provides a high level description of the functionality associated with each chipset component and the architectural blocks that make up the server boards Revision 1 8 17 Intel order number E39529 013 Functional Architecture Intel Server Boards S5520HC S5500HCV and S5520HCT TPS T 9o 8 i i9 d DDR3 Xeon pg bel DIMMs per Channel 2 DIMMs per Channel TE ntel meer aaa QuickPath Ss Ee 2 yied42IND HEADING 7 E SS 5520 575EB IOH Slot Slot 5 Slot 4 Slot 3 Default switch to slot2 PETER SAS Module Slot 5 SATA II x6 ul SB x Pip FLASH RMM3 Slot Em 21 09 seria emma SE Internal Sen al Con nn ENS use x1 gt Gap PICS Ad Ga USB x1 DVD Floppy USB x2 conn o uuse Front Panel USB deem Slot gt ICH10R A type USB x1 Figure 13 Intel Server Board S5520HC Functional Block Diagram Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Functional Architecture DDR3 DDR3 QuickPath DDR3 DDR3 Xeon GE C F m 2 DIMMs per Channel DIMM per Channel wied4IIND TEE Slot 6 x16 conn PE1 2 Default switch eee SAS Module Slot FA SATA II x6 m Ja 82575EB com 1 Slot 4 Slot 3 SB x RMM3 Slot md RS Slot 1 CJ ICH10R SB x2 LP sere Internal Serial Conn Serial A
199. the sources described in the following paragraph The wake up sources are enabled by the ACPI operating systems with cooperation from the drivers the BIOS have no direct control over the wake up sources when an ACPI operating system is loaded The role of the BIOS is limited to describing the wake up sources to the operating system The S5 state is equivalent to the operating system shutdown No system context is saved when going into S5 Revision 1 8 59 Intel order number E39529 013 Functional Architecture Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS 3 15 Intel Virtualization Technology Intel Virtualization Technology is designed to support multiple software environments sharing the same hardware resources Each software environment may consist of an operating system and applications You can enable or disable the Intel Virtualization Technology in the BIOS Setup The default behavior is disabled Note After changing the Intel Virtualization Technology option disable or enable in the BIOS setup users must perform an AC power cycle before the change takes effect 3 15 1 Intel Virtualization Technology for Directed IO VT d The Intel Server Boards S5520HC S5500HCV and S5520HCT support DMA remapping from inbound PCI Express memory Guest Physical Address GPA to Host Physical Address HPA PCI devices are directly assigned to a virtual machine leading to a robust and efficient virtualization You can enable
200. ting at high elevation Higher than 1500m 4920ft or greater Optimal performance setting at the highest elevations Set Fan Profile Performance Performance Fan control provides primary system If CLTT is enabled Acoustics cooling before attempting to throttle memory this option is hidden Acoustic The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met 5 3 2 3 Security Screen The Security screen allows the user to enable and set the user and administrative password This is done to lock out the front panel buttons so they cannot be used This screen also allows the user to enable and activate the Trusted Platform Module TPM security settings To access this screen from the Main screen select Security Main Advanced Security Server Management Boot Options Boot Manager Administrator Password Status lt Installed Not Installed gt User Password Status lt Installed Not Installed gt Set Administrator Password 1234aBcD Set User Password 1234aBcD Front Panel Lockout Enabled Disabled Enabled amp Activated Enabled amp Deactivated Disabled amp Activated Disabled amp Deactivated gt TPM Administrative Control No Operation Turn On Turn Off Clear Ownership TPM State Figure 38 Setup Utility Security Configuration Screen Display 92 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS BIOS
201. tion Current Memory Speed Memory RAS and Performance Configuration DIMM Information DIMM A1 DIMM A2 DIMM B1 DIMM B2 DIMM C1 DIMM C2 DIMM D1 DIMM D2 DIMM E1 DIMM E2 DIMM F1 DIMM F2 Figure 31 Setup Utility Memory Configuration Screen Display 82 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Setup Item Total Memory Effective Memory Current Configuration Current Memory Speed Memory RAS and Performance Configuration DIMM XY Revision 1 8 BIOS Setup Utility Table 24 Setup Utility Memory Configuration Screen Fields Options Help Text Configure memory RAS Reliability Availability and Serviceability and view current memory performance information and settings Comments Information only The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB Information only The amount of memory available to the operating system in MB or GB The Effective Memory is the difference between Total Physical Memory and the sum of all memory reserved for internal usage RAS redundancy and SMRAM This difference includes the sum of all DDR3 DIMMs that failed Memory BIST during POST or were disabled by the BIOS during memory discovery phase in order to optimize memory configuration Information only Displays one of the following ndependent Mode System memory is configur
202. tory device functionality The BMC supports storage and access of system SDRs e Sensor device and sensor scanning monitoring The BMC provides IPMI management of sensors It polls sensors to monitor and report system health e PMl interfaces Host interfaces include system management software SMS with receive message queue support and server management mode SMM IPMB interface LAN interface that supports the IPMI over LAN protocol RMCP RMCP e Serial over LAN SOL e ACPI state synchronization The BMC tracks ACPI state changes provided by the BIOS e BMC Self test The BMC performs initialization and run time self tests and makes results available to external entities See also the ntelligent Platform Management Interface Specification Second Generation v2 0 4 1 2 Non IPMI Features The BMC supports the following non IPMI features This list does not preclude support for future enhancements or additions Jjn circuit BMC firmware update Revision 1 8 61 Intel order number E39529 013 Platform Management Intel Server Boards 5520HC S5500HCV and S5520HCT TPS e Fault resilient booting FRB FRB2 is supported by the watchdog timer functionality e Chassis intrusion detection dependant on platform support e Basic fan control using TControl version 2 SDRs e Fan redundancy monitoring and support e Power supply redundancy monitoring and support e Hot swap fan support e Acoustic management Supports
203. ts One full length full height PCI Express Gen1 slot x8 Mechanically x4 Electrically shared with SAS Module slot One 32 bit 33 MHz PCI slot keying for 5 V and Universal PCI add in card Intel Server Board S5500HCV Five expansion slots One full length full height PCI Express Gen2 slot x16 Mechanically x4 Electrically Two full length full height PCI Express Express Gen2 x8 slots One full length full height PCI Express Gent slot x8 Mechanically x4 Electrically shared with SAS Module slot One 32 bit 33 MHz PCI slot keying for 5 volt and Universal PCI add in card Hard Drive and Optical devices are supported Optical Drive Six SATA connectors at 1 5 Gbps and 3 Gbps Support Four SAS connectors at 3 Gbps through optional Intel SAS Entry RAID Module AXX4SASMOD RAID Support Intel Embedded Server RAID Technology II through onboard SATA connectors provides SATA RAID 0 1 and 10 with optional RAID 5 support provided by the Intel RAID Activation Key AXXRAKSW5 Intel Embedded Server RAID Technology II through optional Intel SAS Entry RAID Module AXX4SASMOD provides SAS RAID 0 1 and 10 with optional RAID 5 support provided by the Intel RAID Activation Key AXXRAKSW5 IT IR RAID through optional Intel SAS Entry RAID Module AXX4SASMOD provides entry level hardware RAID O0 1 10 10E and native SAS pass through mode 4 ports full featured SAS SATA hardware RAID through optional Intel Integrated RAID Module
204. tup Utility 5 3 2 2 1 Processor Configuration Screen The Processor screen allows the user to view the processor core frequency system bus frequency and to enable or disable several processor options This screen also allows the user to view information about a specific processor To access this screen from the Main screen select Advanced Processor Advanced Processor Configuration Processor Socket Processor ID Processor Frequency Microcode Revision Processor 1 Version Processor 2 Version Current Intel QPI Link Speed Intel QPI Link Frequency Intel Turbo Boost Technology Enhanced Intel SpeedStep Tech Intel Hyper Threading Tech Core Multi Processing Execute Disable Bit Intel Virtualization Technology Intel VT for Directed I O Interrupt Remapping Coherency Support ATS Support Pass through DMA Support Hardware Prefetcher Adjacent Cache Line Prefetch Direct Cache Access DCA Enabled Disabled Enabled Disabled Enabled Disabled All 1 2 Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Figure 30 Setup Utility Processor Configuration Screen Display Revision 1 8 Intel order number E39529 013 79 BIOS Setup Utility Intel Server Boards S5520HC S5500HCV and S5520HCT TPS Table 23 Setup Utility Processor Configuration Screen Fields Eaa E
205. uding AP 0x12 Starting application processor initialization 0x13 SMM initialization Chipset 0x21 Initializing a chipset component Memory 0x22 Reading configuration data from memory SPD on DIMM 0x23 Detecting presence of memory 0x24 Programming timing parameters in the memory controller 0x25 Configuring memory parameters in the memory controller 0x26 Optimizing memory controller settings 0x27 Initializing memory such as ECC init 0x28 Testing memory PCI Bus 0x50 Enumerating PCI buses 0x51 Allocating resources to PCI buses 0x52 Hot plug PCI controller initialization 0x53 0x57 Reserved for PCI Bus 162 Revision 1 8 Intel order number E39529 013 Intel Server Boards S5520HC SSSOOHCV and S5520HCT TPS Appendix E POST Code Diagnostic LED Decoder Progress Code Progress Code Definition USB 0x58 Resetting USB bus 0x59 Reserved for USB devices ATA ATAPI SATA 0x5A Resetting SATA bus and all devices 0x5B Reserved for ATA SMBUS 0x5C Resetting SMBUS 0x5D Reserved for SMBUS Local Console 0x70 Resetting the video controller VGA 0x71 Disabling the video controller VGA 0x72 Enabling the video controller VGA Remote Console 0x78 Resetting the console controller 0x79 Disabling the console controller Ox7A Enabling the console controller Keyboard only US B 0x90 Resetting the keyb
206. ul completion of the BIOS recovery the BIOS has been updated successfully message displays 120 Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC 5500HCV and S5520HCT TPS Jumper Blocks 8 Power down the system and remove the AC power cord 9 Open the server chassis 10 Move the BIOS recovery jumper J1E5 from the enabled position covering pins 2 and 3 to the disabled position covering pins 1 and 2 11 Close the server chassis 12 Reconnect the AC power cord and power up the server Warning DO NOT interrupt the BIOS POST during the first boot after the BIOS recovery Revision 1 8 121 Intel order number E39529 013 Intel Light Guided Diagnostics Intel Server Boards 5520HC S5500HCV and 5520HCT TPS 8 Intel Light Guided Diagnostics Both server boards have several onboard diagnostic LEDs to assist in troubleshooting board level issues This section provides a description of the location and function of each LED on the server boards 8 1 5 volt Stand by LED Several server management features of these server boards require a 5 V stand by voltage supplied from the power supply The features and components that require this voltage must be present when the system is power down include the Integrated BMC onboard NICs and optional Intel RMM3 installed in the Intel RMM3 slot The LED is located near the Intel SAS Entry RAID Module AXX4SASMOD slot in the lower left corner
207. urned to where they were before lt F10 gt was pressed without affecting any existing values Revision 1 8 Intel order number E39529 013 Intel Server Boards 5520HC S5500HCV and S5520HCT TPS BIOS Setup Utility 5 3 1 4 Menu Selection Bar The Menu Selection Bar is located at the top of the BIOS Setup Utility screen It displays the major menu selections available to the user By using the left and right arrow keys the user can select the menus listed here Some menus are hidden and become available by scrolling off the left or right of the current selections 5 3 2 Server Platform Setup Utility Screens The following sections describe the screens available for the configuration of a server platform In these sections tables are used to describe the contents of each screen These tables follow the following guidelines e The Setup Item Options and Help Text columns in the tables document the text and values that also display on the BIOS Setup screens e Inthe Options column the default values are displayed in bold These values are not displayed in bold on the BIOS Setup screen The bold text in this document serves as a reference point e The Comments column provides additional information where it may be helpful This information does not display on the BIOS Setup screens e Information enclosed in angular brackets lt gt in the screen shots identifies text that can vary depending on the option s installed For example
208. wake the system NIC 1 MAC Address No entry Information only 12 hex allowed digits of the MAC address NIC 2 MAC Address No entry Information only 12 hex allowed digits of the MAC address 5 3 2 2 7 System Acoustic and Performance Configuration The System Acoustic and Performance Configuration screen allows the user to configure the thermal characteristics of the system To access this screen from the Main screen select Advanced System Acoustic and Performance Configuration Advanced System Acoustic and Performance Configuration Set Throttling Mode Auto CLTT OLTT Altitude 300m or less 301m 900m 901 m 1500m Higher than 1500m Set Fan Profile Performance Acoustic Figure 37 Setup Utility System Acoustic and Performance Configuration Screen Display Revision 1 8 9 Intel order number E39529 013 BIOS Setup Utility Intel Server Boards 5520HC SSSOOHCV and S5520HCT TPS Table 30 Setup Utility System Acoustic and Performance Configuration Screen Fields Setup Item Help Text Set Throttling Auto Auto Auto Throttling mode Mode CLTT CLTT Closed Loop Thermal Throttling Mode OLTT OLTT Open Loop Thermal Throttling Mode Altitude 300m or less 300m or less 980ft or less 301m 900m Optimal performance setting near sea level 901m 1500m 301m 900m 980ft 2950ft Higher than 1500m i Optimal performance setting at moderate elevation 901m 1500m 2950ft 4920ft Optimal performance set
209. you can use to configure protect or recover specific features of the server boards The following symbol identifies Pin 1 on each jumper block on the silkscreen V Update Disable Enable 4 ME Force Disable Enable 4 Password Clear Disable 4 Enable 4 Chassis Intrusion Header A SEA BMC Force Update Disable Enable 1 1 Figure 53 Jumper Blocks J1E2 J1E4 J1E5 J1E6 J1H1 Table 69 Server Board Jumpers J1E6 J1E2 J1E4 J1E5 J1H1 Jumper Name Pins System Results 4 2 These pins should have a jumper in place for normal system operation Default J1E6 CMOS Clear E 2 3 If pins 2 3 are connected when AC power unplugged the CMOS settings clear in 5 seconds Pins 2 3 should not be connected for normal system operation J1E2 ME Force 1 2 ME Firmware Force Update Mode Disabled Default Update 2 3 ME Firmware Force Update Mode Enabled 4 2 These pins should have a jumper in place for normal system operation Default J1E4 Password Clear To clear administrator and user passwords power on the system with pins 2 3 2 3 connected The administrator and user passwords clear in 5 10 seconds after power on Pins 2 3 should not be connected for normal system operation 1 2 Pins 1 2 should be connected for normal system operation Default J1ES BIOS Recovery 2 3 The main system BIOS does not

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