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Intel Celeron T1700

1. eene 28 10 Open Drain Signal Group DC Specifications cece eee erect eee ee eee 28 11 The Coordinates of the Processor Pins as Viewed from the Top of the Package Sheet 1 0f 2 UNUM 34 12 The Coordinates of the Processor Pins as Viewed from the Top of the Package Sheet 20f 2 D 35 13 Pin Listing by Pim Natme uie ai taam dace MAR EE ERA cabbie daeaateneuane 37 14 Pin Listing by Pin NUMBER se nenne tree Aaaa ERE REIR ER M RE n Na 44 15 Signal Description vedas datas dundee bale a gea bie 53 16 Power Specifications for the Intel Celeron Dual Core Processor Standard Voltage 61 17 Thermal Diode ipd tete kie sh aa aAa E r2 RRU I PaaRid 62 18 Thermal Diode Parameters Using Diode Model 63 19 Thermal Diode Parameters Using Transistor 64 20 Thermal Diode ntrim and Diode Correction Toffset
2. Signal Name Beso e D 20 R41 D 21 W41 D 22 N43 D 23 U41 D 24 AA41 D 25 AB40 D 26 AD40 D 27 AC41 D 28 AA43 D 29 Y40 D 30 Y44 D 31 T44 D 32 AP44 D 33 AR43 D 34 AH40 D 35 AF40 D 36 AJ43 D 37 AG41 D 38 AF44 D 39 AH44 D 40 AM44 D 41 AN43 D 42 AM40 D 43 AK40 D 44 AG43 D 45 AP40 46 4 AN41 D 47 AL41 D 48 AV38 D 49 AT44 D 50 AV40 D 51 AU41 D 52 AW41 D 53 AR41 D 54 BA37 D 55 BB38 D 56 AY36 D 57 AT40 62 Signal Name le D 58 BC35 D 59 BC39 D 60 BA41 D 61 BB40 D 62 BA35 D 63 AU43 DBR J7 DBSY 11 DEFER N5 DINV O P40 DINV 1 R43 DINV 2 AJ41 DINV 3 BC37 DPRSTP G7 DPSLP B8 DPWR C41 DRDY F38 DSTBN 0 K40 DSTBN 1 U43 DSTBN 2 AK44 DSTBN 3 AY40 DSTBP 0 141 DSTBP 1 W43 DSTBP 2 AL43 DSTBP 3 AY38 FERR D4 GTLREF AW43 HIT H2 HITM F2 IERR B40 IGNNE F10 INIT D8 LINTO C9 LINT1 C5 LOCK N1 PRDY AV10 PREQ AV2 PROCHOT D38 Package Mechanical Specifications and Pin Information Datasheet Package Mechanical Specifications and Pin Information
3. Signal Name Pie VSS B6 VSS B36 VSS B42 VSS BA1 VSS BA3 VSS BA9 VSS BA11 VSS BA13 VSS BA15 VSS BA17 VSS BA19 VSS BA21 VSS BA23 VSS BA25 VSS BA27 VSS BA29 VSS BA31 VSS BA33 VSS BA39 VSS BA43 VSS BB2 VSS BB6 VSS BB12 VSS BB36 VSS BB42 VSS BC3 VSS BC9 VSS BC11 VSS BC15 VSS BC17 VSS BC19 VSS BC21 VSS BC23 VSS BC25 VSS BC27 VSS BC29 VSS BC31 VSS BC33 Datasheet Signal Name Tec VSS BC41 VSS BD4 VSS BD6 VSS BD36 VSS BD38 VSS BD40 VSS C3 VSS C11 VSS ci5 VSS C17 VSS C19 VSS C21 VSS C23 VSS C25 VSS C27 VSS C29 VSS C31 VSS C39 VSS D2 VSS D6 VSS D36 VSS D42 VSS D44 VSS E1 VSS E3 VSS E9 VSS E15 VSS E17 VSS E19 VSS E21 VSS E23 VSS E25 VSS E27 VSS E29 VSS E31 VSS E39 VSS F6 VSS F42 71 intel Signal Name Bs e VSS F44 VSS G1 VSS G3 VSS G9 VSS G15 VSS G17 VSS G19 VSS G21 VSS G23 VSS G25 VSS G27 VSS G29 VSS G31 VSS G37 VSS H6 VSS H10 VSS H34 VSS H38 VSS H42 VSS 13 VSS J15 VSS J17 VSS J19 VSS J21 VSS J23 VSS J25 VSS J27 VSS J29 VSS J31 VSS J39 VSS K6 VSS K8 VSS K34 VSS K42 VSS L3 VSS L15 VSS L17 VSS L19 72 Package Mechanical Specifications and Pin Information
4. Signal Name MS VCCP AK14 VCCP AK36 VCCP AK38 VCCP AL7 VCCP AL9 VCCP AL11 VCCP AL13 VCCP AL35 VCCP AL37 VCCP AN7 VCCP AN9 VCCP AN11 VCCP AN13 VCCP AN35 VCCP AN37 VCCP AP10 VCCP AP12 VCCP AP36 VCCP AP38 VCCP AR7 VCCP AR9 VCCP AR11 VCCP AR13 VCCP AU11 VCCP AU13 VCCP B12 VCCP B14 VCCP B32 VCCP C13 VCCP C33 VCCP D12 VCCP D14 VCCP D32 VCCP E11 VCCP E13 VCCP E33 VCCP E35 VCCP F12 Datasheet Signal Name Too VCCP F14 VCCP F34 VCCP F36 VCCP G11 VCCP G13 VCCP G35 VCCP H12 VCCP H14 VCCP H36 VCCP J11 VCCP J13 VCCP 135 VCCP J37 VCCP K10 VCCP K12 VCCP K14 VCCP K36 VCCP K38 VCCP L7 VCCP L9 VCCP L11 VCCP L13 VCCP L35 VCCP L37 VCCP M14 VCCP N7 VCCP N9 VCCP N11 VCCP N13 VCCP N35 VCCP N37 VCCP P10 VCCP P12 VCCP P14 VCCP P36 VCCP P38 VCCP R7 VCCP R9 67 intel Signal Name Pss e VCCP R11 VCCP R13 VCCP R35 VCCP R37 VCCP T14 VCCP U7 VCCP U9 VCCP U11 VCCP U13 VCCP U35 VCCP U37 VCCP V10 VCCP V12 VCCP V14 VCCP V36 VCCP V38 VCCP W7 VCCP w9 VCCP Wil VCCP W13 VCCP W35 VCCP W37 VCCP Y14 VCCSENSE BD12 VID 0 BD8 VID 1 BC7 VID 2 BB10 VID 3 BB8 VID 4 BC5 VID 5 BB4 VID 6 AY4 VSS A5 VSS A7 VSS A9 VSS A11 VSS A15 VSS A17 VSS A19 68 Package Mechanical Specificatio
5. Signal Name ae VSS L21 VSS L23 VSS L25 VSS L27 VSS L29 VSS L31 VSS L39 VSS M6 VSS M8 VSS M10 VSS M12 VSS M34 VSS M36 VSS M38 VSS M42 VSS N3 VSS N15 VSS N17 VSS N19 VSS N21 VSS N23 VSS N25 VSS N27 VSS N29 VSS N31 VSS N39 VSS P6 VSS P8 VSS P34 VSS P42 VSS R3 VSS R15 VSS R17 VSS R19 VSS R21 VSS R23 VSS R25 VSS R27 Datasheet Package Mechanical Specifications and Pin Information Signal Name Tio VSS Y6 VSS Y8 VSS Y10 VSS Y12 VSS Y34 VSS Y36 VSS Y38 VSS Y42 VSSSENSE BC13 Signal Name ML VSS R29 VSS R31 VSS R39 VSS T6 VSS T8 VSS T10 VSS T12 VSS T34 VSS T36 VSS T38 VSS T42 VSS U3 VSS U5 VSS U15 VSS U17 VSS U19 VSS U21 VSS U23 VSS U25 VSS U27 VSS U29 VSS U31 VSS U39 VSS V6 VSS V8 VSS V34 VSS V42 VSS w3 VSS W15 VSS W17 VSS W19 VSS W21 VSS W23 VSS W25 VSS W27 VSS W29 VSS W31 VSS w39 Datasheet 73 74 Package Mechanical Specifications and Pin Information Datasheet Package Mechanical Specifications and Pin Information m 4 3 Table 22 Alphabetical Signals Reference Signal Description Sheet 1 of 7 Name Type Description A 35 3 Input Output A 35 3 Address define a 235 byte physical memory address space In su
6. Signal Name Mud PSI BD10 PWRGOOD E7 REQ O R1 REQ 1 R5 REQ 2 U1 REQ 3 P4 REQ 4 w5 RESET G5 RS 0 K2 RS 1 H4 RS 2 K4 RSVDO1 V2 RSVD02 Y2 RSVDO3 AG5 RSVD04 AL5 RSVDO5 J9 RSVD06 F4 RSVD07 H8 SLP D10 SMI E5 STPCLK F8 TCK AV4 TDI AW7 TDO AU1 TEST1 E37 TEST2 D40 TEST3 C43 TEST4 AE41 TESTS AY10 TEST6 AC43 THERMTRIP B10 THRMDA BB34 THRMDC BD34 TMS AW5 TRDY L1 TRST AV8 VCC AA33 VCC AB16 Datasheet Signal Name es VCC AB18 VCC AB20 VCC AB22 VCC AB24 VCC AB26 VCC AB28 VCC AB30 VCC AB32 VCC AC33 VCC AD16 VCC AD18 VCC AD20 VCC AD22 VCC AD24 VCC AD26 VCC AD28 VCC AD30 VCC AD32 VCC AE33 VCC AF16 VCC AF18 VCC AF20 VCC AF22 VCC AF24 VCC AF26 VCC AF28 VCC AF30 VCC AF32 VCC AG33 VCC AH16 VCC AH18 VCC AH20 VCC AH22 VCC AH24 VCC AH26 VCC AH28 VCC AH30 VCC AH32 63 intel Signal Name E VCC AJ33 VCC AK16 VCC AK18 VCC AK20 VCC AK22 VCC AK24 VCC AK26 VCC AK28 VCC AK30 VCC AK32 VCC AL33 VCC AM14 VCC AM16 VCC AM18 VCC AM20 VCC AM22 VCC AM24 VCC AM26 VCC AM28 VCC AM30 VCC AM32 VCC AN33 VCC AP14 VCC AP16 VCC AP18 VCC AP20 VCC AP22 VCC AP24 VCC AP26 VCC AP28 VCC AP30 VCC AP32 VCC AR33 VCC AT14 VCC AT16 VCC AT18 VCC AT20 VCC AT22 64 Package Mechanical Specifications and P
7. Table 20 Pin Listing by Pin Number Table 20 Pin Listing by Pin Number Sheet 16 of 17 Sheet 17 of 17 Pin Signal Pin Signal Pin Name Number Buffer Type Direction Pin Name Number Buffer Type Direction Input Input A 18 U5 Source Synch Output D 41 W22 Source Synch Output vss U6 Power Other VSS W23 Power Other vom Her POSU DIENST D 43 W24 Source Synch did DINV 2 U22 Source Synch ene TET P D 44 w25 Source Synch Input D 39 Mea Source Synch Output vss W26 Power Other m ua Power otner COMP 3 Y1 Power Other alate 3814 U25 Source Synch ad Du P A 17 amp Y2 Source Synch Input COMPLET Power Other Output VSS Y3 Power Other Input Input ADSTB 1 Vi Source Synch Output A 29 Y4 Source Synch Output VSS ve Power other A 22 YS Source Synch ad RSVD v3 Reserved VSS Y6 Power Other A 31 v4 Source Synch I Put Output VSS Y21 Power Other ws MS Power other D 32 Y22 Source Synch d VCCP V6 Power Other VCCP V21 Power Other D 42 Y23 Source Synch ici Power Other VSS Y24 Power Other 36 4 23 Source Synch Input Input y Output D 40 Y25 Source Synch P Output Input v24 Source Synch Output DSTBN 2 Y26 Source Synch vss V25 Power Other Input D 35 V26 Source Synch Output vss Power Other Input A 27 W2 Source Synch Output A 32 w3 Source Synch InPut Output vss Power Other Input A 28 w5 Sourc
8. 12 2 1 1 3 C1 MWAIT Powerdown 5 8 6 13 DATA CORE C2 States LUCES 13 2 1 1 5 COPE C3 State ciui nrn eE oia 13 2 1 1 6 Core C4 State iesu oe e EUR UIBRIRRUERSRTD AAAA ENR 13 2 1 2 Package Low Power 5 8 5 13 24 2 1 State cep vein tameu Gv DRE RR RR RUE 13 2 1 2 2 StopsGraht State eee esee reet en aime erni E uxo pr a Rad nad i rRR 13 2 1 2 3 Stop Grant Snoop 8 6 saxea dta vaa nt pecu NER RR RA ERR 14 2 1 2 4 Sl ep State saab ea ga IR telnet 14 2 1 2 5 Deep Sleep State ironic dese ka r tuae aes Ente Ea 15 2 1 2 6 Deeper Sleep St t eeeti ense meg at XR ha Rau Ear ERA SERRA DATE 15 2 2 Enhanced Intel SpeedStep Technology sssssssssseeenem emen 15 2 3 Low Power EFSB Featres sede 16 2 4 Processor Power Status Indicator PSI 5 17 3 Electrical Specifications eco dence hades Die ip ene Me e ea E 19 3 1 Power and Ground Pins rrr tener nana ERN RENE na up Ra ERE 19
9. gt NOILVHOd3JOO TALNI JO LNASNOD N3LITHM HOINd IHL LNOHLIM G3ISIGOW YO daAvidsiad aaonaoxdan GASOTDSIC 38 LON AVW SLNILNOD SLI ANY 3ON3GIJNOO NI G3SO I2SIG SI LI NOLIVWWVOJNI TIVLLN3OIJNOO NOILVYOdYOD TALNI SNIVLNOD 9NIMVSG SIHL Datasheet 38 Package Mechanical Specifications and Pin Information 4 2 Processor Pinout and Pin List intel Table 13 shows the top view pinout of the Intel Celeron Dual Core processor The pin list arranged in two different formats is shown in the following pages m um C 4H v Z Bo AC AD AE AF Table 13 The Coordinates of the Processor Pins as Viewed from the Top of the Package Sheet 1 of 2 1 2 3 4 5 6 7 s 9 10 11 12 13 A vss smi vss FERR A20M amp vcc vss vss RSVD INIT LINT1 DPSLP VSS vcc VSS VCC VSS vcc VSS c RESET vss rsvp IGNNE vss Gro THERM vss vcc vss vcc vcc D vss rsvp Rsvp vss STPELK PWRGO sipz vss vcc vec vss vcc vss E pesy BNR vss HiTm DPRSTP vcc vss vcc vss vcc vcc F BRO vss 4 5 114 vss RSvD vcc vss vss vss G VSS TRDY RS 2 VSS BPRI HIT H aps REO vss Lock DEFER vss J 914 vss
10. Table 19 Pin Listing by Pin Name Sheet 1 of 16 Pin Name DEL Direction A 3 J4 Source Synch ud A 4 L5 Source Synch 5 4 4 Source Synch afer A 6 K5 Source Synch AL7 M3 Source Synch uate A 8 N2 Source Synch avant A 9 11 Source Synch N3 Source Synch A 11 P5 Source Synch dA A 12 P2 Source Synch uut A 13 L2 Source Synch m A 14 P4 Source Synch zd A 15 P1 Source Synch d A 16 R1 Source Synch A 17 Y2 Source Synch A 18 U5 Source Synch W A 19 R3 Source Synch nn A 20 W6 Source Synch Input Output A 21 U4 Source Synch A 22 Y5 Source Synch onan Al 23 Ui Source Synch Ut Datasheet Table 19 Pin Listing by Pin Name Sheet 2 of 16 Pin Signal Buffer z Pin Name Number Type Direction Input A 24 R4 Source Synch Output Input A 25 T5 Source Synch Output Input A 26 T3 Source Synch Output Input A 27 W2 Source Synch Output Input A 28 w5 Source Synch Output Input A 29 Y4 Source Synch Output Input A 30 U2 Source Synch Output Input A 31 V4 Source Synch Output 32 4 w3 Source Synch Input Output Input A 33 AA4 Source Synch Output Input A 34 AB2 Source Synch Output A 35 3 Source Synch y Output A20M A6 CMOS Input Input ADS H1 Common Clock Output ADSTB O Source Synch 1nPut y Output ADSTB 1 Vi Source Synch Input y Output
11. Termination Resistor 55 Q 11 Vin Input High Voltage GTLREF 0 10 Vccp Vccpt 0 10 V 3 6 Vu Input Low Voltage 0 10 0 GTLREF 0 10 V 2 4 VoH Output High Voltage Vccp 0 10 Vccp Vccp 6 Termination Resistance 50 55 61 7 Ron Buffer On Resistance 22 25 28 5 Ij Input Leakage Current 100 HA 8 Cpad Pad Capacitance 1 6 2 1 2 55 pF 9 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 is defined as the maximum voltage level at a receiving agent that is interpreted as a logical low value 3 Vin is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high value 4 and Voy may experience excursions above Vccp However input signal drivers must comply with the signal quality specifications 5 This is the pull down driver resistance Measured at 0 31 Vccp min 0 4 Rq Ron typ 0 455 Ry Roy max 0 51 R 7 Rr typical value of 55 Q is used for Roy typ min max calculations 6 GTLREF should be generated from Vccp with a 1 tolerance resistor divider The Vccp referred to in these specifications is the instantaneous Vccp 7 Rrr is the on die termination resistance measured at Vo of the AGTL output driver Measured at 0 31 Vccp Ry is connected to Vccp on die 8 Specified with on die Rz and Roy turned off Vin between 0 and Vecp 9 Cpad includes die capacitance only No package parasitics are included 10 This
12. eene mener 29 4 2 Processor Pinout amd Pin List 3 5 ite In pen nh mb me dale o n Ra nik gi Mna 33 4 3 Alphabetical Signals Reference i ieeeeceee nnns narena san iie na CRX RR EXERCERE TERRE ce 53 5 Thermal Specifications and Design Considerations s usus 61 5 1 Monitoring Die Temperature iieiiire eene hanh an rt eaa anh ma Naai eae ted rada ne 61 5 1 1 Thermal Diode serrer oer opea A Qu Ra rex ia EDEN UNI EX EXEAN EE 62 5 1 2 Thermal Diode e nans nnn essa ka uana nena saga nana 64 5 1 3 Intel Thermal MOnitO iiri ph Cre nR A RPM U TAE DER e EAN 65 5 1 4 Digital Thermal SENSO irinenn iaa ne nha ka a neun ase ga away aa RR 66 5 1 5 O tof Specification Detection esce seines e eka cheated cea deca seven cetewel aa 67 5 1 6 PROCHOT Signal Pin er reprennent ta vege eine ad ux Rega Fare v agi de E E 67 Datasheet 3 Figures 1 Package Level Low Power States cc eeeceee eens een sena n senken hana RR naX AR RR AR GG ea enensestieeeeseeneennee 11 2 Core Low Power States uere ee ex eu fal Mawes REN PER 12 3 4 MB and Fused 2 MB Micro FCPGA Processor Package Drawing Sheet 1 of 2 30 4 4 MB and Fused 2 MB Micro FCPGA Processor Package Drawing Sheet 2 of 2 31 5 2
13. symbol after a signal name refers to an active low signal indicating a signal is in the active state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level XXXX means that the specification or value is yet to be determined Refers to the interface between the processor and system core logic also known as the chipset components AGTL Storage Conditions Advanced Gunning Transceiver Logic Used to refer to Assisted GTL signaling technology on some Intel processors Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air i e unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Enhanced Intel
14. 65 Datasheet Revision History Document Number Revision Number Description Date 321111 001 Initial Release November 2008 321111 002 Added T3000 T3100 T3300 and T3500 processors June 2009 321111 003 Added specifications for SFF processor SU2300 Added C4 state support information for SU2300 SFF processor Added Speedstep technology suppport information for SU2300 SFF processor details Chapter 1 updated feature list for SFF processor Section 2 1 added C4 deeper sleep state information Figure 1 updated C4 deeper sleep state information Figure 2 updated C4 deeper sleep state information Table 1 Added C4 deeper sleep state information Section Section 2 1 1 6 Section 2 1 2 6 Added C4 deeper sleep state information Section 2 2 Added information on Intel speedstep technology description Table 8 added table for SU2300 processor DC specifications Table 25 added table for SU2300 thermal specifications Figure 7 Table 19 Table 20 Table 17 Table 23 added SU2300 pin and package information September 2009 Datasheet Datasheet Introduction 1 Note Datasheet intel Introduction This document provides electrical mechanical and thermal specifications for the Intel Celeron Mobile Processor Dual Core T1x00 Intel R Celeron Processors T3x00 and Intel R Celeron Dual core SFF Processors The processor supports the Mobile Int
15. Reserved VSS R22 Power Other VCCP N6 Power Other D 19 4 R23 Source Synch InPut VCCP N21 Power Other y Output Input Input D 16 N22 Source Synch Output D 28 R24 Source Synch Output VSS N23 Power Other VSS R25 Power Other Input Input DINV 1 N24 Source Synch Output COMP 0 R26 Power Other Output D 31 N25 Source Synch NE vum Lis POWT OENET RSVD T2 Reserved VSS N26 Power Other Input 26 4 T3 Source Synch Input Output A 15 P1 Source Synch Output P vss T4 Power Other A 12 P2 Source Synch 1 Input y Output A 25 T5 Source Synch p Output VSS BS Power Other VCCP T6 Power Other Input A 14 P4 Source Synch Output VCCP T21 Power Other Input A 11 P5 Source Synch InPut D 37 Tee Source Synch Output Output VSS P6 Power Other VSS T23 Power Other Input VSS P21 Power Other D 27 T24 Source Synch Output Input pee Source Synch Output D 30 T25 Source Synch Output D 25 P23 Source Synch I Put vss T26 Power Other y Output 55 24 Power Other A 23 U1 Source Synch InPut y Output Input D 24 x Source Synch Output 3014 2 Source Synch Input Output D 18 P26 Source Synch I Put vss U3 Power Other y Output Input A 16 R1 Source Synch Input A 21 DE Output Output Datasheet 59 intel Package Mechanical Specifications and Pin Information
16. BCLK 0 A22 Bus Clock Input BCLK 1 A21 Bus Clock Input BNR E2 Common Clock Input Output BPM 0 AD4 Common Clock Input Output BPM 1 AD3 Common Clock Output BPM 2 AD1 Common Clock Output Input BPM 3 AC4 Common Clock Output BPRI G5 Common Clock Input 45 intel Package Mechanical Specifications and Pin Information Table 19 Pin Listing by Pin Name Table 19 Pin Listing by Pin Name Sheet 3 of 16 Sheet 4 of 16 Pin Signal Buffer z a Pin Signal Buffer A Pin Name Number Type Direction Pin Name Number Type Direction Input Input BRO Common Clock Output D 15 H23 Source Synch Output BSEL 0 B22 CMOS Output see NUS sire BSEL 1 B23 CMOS Output RM Input BSEL 2 C21 CMOS Output D 17 K25 Source Synch Input SOME R26 Power Other Output D 18 P26 Source Synch Output Input COMP L 558 Power Other Output D 19 R23 Source Synch Output Input COMPIZ AAI Power Other Output D 20 L23 Source Synch Output Input COMPS Power Other Output D 21 M24 Source Synch Output Input D 0 E22 Source Synch Output D 22 L22 Source Synch 1nput Output Input D 1 F24 Source Synch Output D 23 M23 Source Synch Input Output Input D 2 pen Source Synch outo
17. Io Output Low Current 16 50 mA ILo Output Leakage Current 200 HA 4 Cpad Pad Capacitance 1 9 2 2 2 45 pF NOTES Unless otherwise noted all specifications in this table apply to all processor frequencies Measured at 0 2 V Von is determined by value of the external pull up resistor to Vccp For Vin between 0 V and Voy Cpad includes die capacitance only No package parasitics are included 8 OV Pn 32 Datasheet m e Package Mechanical Specifications and Pin Information n t el 4 4 1 Note Datasheet Package Mechanical Specifications and Pin Information Package Mechanical Specifications The processor is available in a 1 MB 478 pin Micro FCPGA package The package mechanical dimensions keep out zones processor mass specifications and package loading specifications are shown in Figure 3 through Figure 6 The SFF processor ULV DC is available 956 ball Micro FCBGA packages The package mechanical dimensions are shown in Figure 7 The maximum outgoing co planarity is 0 2 mm 8 mils for SFF Package The mechanical package pressure specifications are in a direction normal to the surface of the processor This requirement is to protect the processor die from fracture risk due to uneven die pressure distribution under tilt stack up tolerances and other similar conditions These specifications assume that a mechanical attach is designed specifically to load one type of processor Moreover the processor packa
18. KORR RR OO QNOD KO o oo SRS DE 0 0 o 0007070000000000000000p707000000070700 1202020202020207 Oo o 00000 oS Ox n o X 5 5 5 5 5 5 5 5 5 o o o o ARR 00 0 0 o c Oo o x PO 020202000 0 0 0 0 0 0 0 0 0 o 9 9 0 0 0 0 O0 Y l 99 9 9 9 999 9 09999 0 0 0 050500 0 0 Oc 0 0c o 0 0 0 0 0 x o 22 4z22 5cuo 5 zm E 5 T 9 Coco o 208 co co o 0 0 D 0 0 0 0 xi X o o oco 0 0 0 0 OO o SFF ULV DC Die Micro FCBGA Processor Package Drawing intel Figure 7 Sy aos v 3 a aid eensqns ebexoeg Iljjopur Axod3 M3IA a J yr Vlad 33S r4 3 15 2 M3IA dOL lt p 39V3DVd Se 4 amp 3lId aanaannnnnnannanannnnnnanonnnnnnnannnnnnn a a A vieoz 0 7
19. SpeedStep Technology Technology that provides power management capabilities to laptops Processor Core Processor core die with integrated L1 and L2 cache All AC timing and signal integrity specifications are at the pads of the processor core Intel 64 64 bit memory extensions to the IA 32 architecture Technology Intel Processor virtualization which when used in conjunction with Virtual Virtualization Machine Monitor software enables multiple robust independent software Technology environments inside a single platform TDP Thermal Design Power Vcc The processor core power supply Vss The processor ground Datasheet Introduction 1 2 Datasheet References intel Material and concepts available in the following documents may be beneficial when reading this document Document Document Number Intel Celeron Dual Core T1x00 Processors Specification Update for Platforms Based on Mobile Intel 4 Series Express Chipset Family See http www intel com design mobile specupdt 319734 htm Mobile Intel 4 Series Express Chipset Family Datasheet 355969 Mobile Intel 4 Series Express Chipset Family Specification Update 320123 See http Intel I O Controller Hub 9 ICH9 I O Controller Hub 9M ICH9M www intel com Assets Datasheet PDF datasheet 316972 pdf See http Intel I O Controller Hub 8 ICH8 I O Controller Hub 8M ICH8M www intel com A
20. VCC AB15 Power Other VCC B7 Power Other VCC AB17 Power Other vcc B9 Power Other vcc AB18 Power Other vcc B10 Power Other VCC AB20 Power Other VCC B12 Power Other VCC AC7 Power Other VCC B14 Power Other VCC AC9 Power Other VCC B15 Power Other VCC AC10 Power Other VCC B17 Power Other VCC AC12 Power Other VCC B18 Power Other VCC AC13 Power Other VCC B20 Power Other VCC AC15 Power Other VCC C9 Power Other VCC AC17 Power Other VCC C10 Power Other VCC AC18 Power Other VCC C12 Power Other VCC AD7 Power Other VCC C13 Power Other vcc AD9 Power Other vcc C15 Power Other VCC AD10 Power Other VCC C17 Power Other VCC AD12 Power Other VCC C18 Power Other VCC AD14 Power Other VCC D9 Power Other VCC AD15 Power Other VCC D10 Power Other VCC AD17 Power Other VCC D12 Power Other VCC AD18 Power Other VCC D14 Power Other VCC AE9 Power Other VCC D15 Power Other VCC AE10 Power Other VCC D17 Power Other VCC AE12 Power Other VCC D18 Power Other VCC AE13 Power Other VCC E7 Power Other VCC AE15 Power Other VCC E9 Power Other VCC AE17 Power Other VCC E10 Power Other Datasheet 49 intel Package Mechanical Specifications and Pin Information Table 19 Pin Listing by Pin Name Table 19 Pin Listing by Pin Name Sheet 11 of 16 Sheet 12 of 16 Pin Name TOUR M Direction Pin Name uL TS Direction VCC E12 Power Other VID 2 AE5 CMOS Output V
21. vss vec vss vec vec vss vcc BCLK 1 BCLK O VSS THRMDA VSS TESTe A B vcc vec vss vec vec vss VCC VSS BSEL 1 VSS THRMDC vCCA B c vcc vss vec vec vss pene BSEL 2 VSS TESTI TEST3 VSS veca c D vec vec vss vec vec vss reRR amp PROCHO Rsvp vss DPWR TEST2 vss D E vss vcc vss vcc vcc vss VCC VSS D 0 D 7 4 VSS D 6 amp D 2 E F vcc vec vss vec vec vss vec DRDY VSS D 4 D 1 VSS 1313 F G VCCP D 3 amp VSS D 9 D 5 vss G H vss D 12 D 15 4 vss DINV O Ed H J VCCP vss D 11 D 10 vss ponl J K VCCP D 14 amp VSS D 8 D 17 vss L vss D 22 D 20 vss D 29 iu L M VCCP vss D 23 D 21 vss EU d M N VCCP D 16 amp VSS DINV 1 D 31 vss n P VSS D 26 D 25 VSS D 24 ppisj P R VCCP vss D 19 D 28 vss COMPLE R T VCCP D 37 amp VSS D 27 D 30 vss U vss 214 D 39 vss D 38 SURE U v VCCP VSS D 36 D 34 VSS D 35 amp v w VCCP D 41 amp VSS D 43 4 D 44 4 vss w Y vss D 32 D 42 vss 40 4 Ex Y AA vss vcc vss vec vec vss vcc D 50 vss D 45 D 46 vss A AB vcc vss vcc vec vss vcc D s2 amp D 5i vss D 33 amp D 47 4 vss AC vss vcc vss vec vec vss uu 3 vss D 60 D 63 vss D 57 f D 53 AC A vec vec vss vec vec vss 5414 59 4 vss D 61 D 49 vss GTLREF AE vss vcc vss vec vec vss v
22. 1 1 1 2125 0 0 1 1 0 0 0 1 2000 0 0 1 1 0 0 1 1 1875 0 0 1 1 0 1 0 1 1750 0 0 1 1 0 1 1 1 1625 0 0 1 1 1 0 0 1 1500 0 0 1 1 1 0 1 1 1375 0 0 1 1 1 1 0 1 1250 0 0 1 1 1 1 1 1 1125 0 1 0 0 0 0 0 1 1000 0 1 0 0 0 0 1 1 0875 0 1 0 0 0 1 0 1 0750 0 1 0 0 0 1 1 1 0625 0 1 0 0 1 0 0 1 0500 0 1 0 0 1 0 1 1 0375 0 1 0 0 1 1 0 1 0250 0 1 0 0 1 1 1 1 0125 0 1 0 1 0 0 0 1 0000 0 1 0 1 0 0 1 0 9875 0 1 0 1 0 1 0 0 9750 0 1 0 1 0 1 1 0 9625 0 1 0 1 1 0 0 0 9500 0 1 0 1 1 0 1 0 9375 0 1 0 1 1 1 0 0 9250 0 1 0 1 1 1 1 0 9125 0 1 1 0 0 0 0 0 9000 0 1 1 0 0 0 1 0 8875 0 1 1 0 0 1 0 0 8750 0 1 1 0 0 1 1 0 8625 0 1 1 0 1 0 0 0 8500 0 1 1 0 1 0 1 0 8375 0 1 1 0 1 1 0 0 8250 0 1 1 0 1 1 1 0 8125 0 1 1 1 0 0 0 0 8000 0 1 1 1 0 0 1 0 7875 0 1 1 1 0 1 0 0 7750 0 1 1 1 0 1 1 0 7625 0 1 1 1 1 0 0 0 7500 0 1 1 1 1 0 1 0 7375 0 1 1 1 1 1 0 0 7250 0 1 1 1 1 1 1 0 7125 1 0 0 0 0 0 0 0 7000 1 0 0 0 0 0 1 0 6875 1 0 0 0 0 1 0 0 6750 1 0 0 0 0 1 1 0 6625 1 0 0 0 1 0 0 0 6500 Datasheet Electrical Specifications Table 2 Datasheet Voltage Identification Definition Sheet 3 of 4 VID6 VID5 VID4 VID3 VID2 VID1 VIDO Vcc V 1 0 0 0 1 0 1 0 6375 1 0 0 0 1 1 0 0 6250 1 0 0 0 1 1 1 0 6125 1 0 0 1 0 0 0 0 6000 1 0 0 1 0 0 1 0 5875 1 0 0 1 0 1 0 0 5750 1 0 0 1 0 1 1 0 5625 1 0 0 1 1 0 0 0 5500 1 0 0 1 1
23. 3 2 FSB Clock BCLK 1 0 and Processor Clocking essem HII 19 3 9 Voltage Identification eerie noe onte ceded espe badass se pne ko RER ARA RA Orb UP ar MR ERN 19 3 4 Catastrophic Thermal nemen nemen ene 22 3 5 Reserved and Unused 5 hash nan sa ararnar sanas inda nan 22 3 6 FSB Frequency Select Signals BSEL 2 0 sese 23 3 7 FSB SIGNal Group rcm 23 3 8 CMOS e E 25 3 9 Maximum RAGS Bcc share teni cece aerate dente carne lel iene ince ERE sic ete a Pee eee oai 25 3 10 Processor DC Specifications iocos iie inina ca A c aaaics aa iaa aaa 26 4 Package Mechanical Specifications and Pin 33 4 1 Package Mechanical 33 4 2 Processor Pinout and Pin List memes emen ead 39 4 5 Alphabetical Signals tanta 33a X4 SA HR ERR ARR RR 75 5 Thermal Specifications and D
24. DSTBN Output Group DSTBP DINV D 63 0 D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high DBR Data Bus Reset is used only in processor systems where no debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect in the system DBR is not a processor signal DBR Output DBSY Data Bus Busy is asserted by the agent responsible for driving data on Input the FSB to indicate that the data bus is in use The data bus is released after Output DBSY is deasserted This signal must connect the appropriate pins on both FSB agents DBSY DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of both FSB agents DEFER Input 76 Datasheet Package Mechanical Specifications and Pin Information Table 22 intel Signal Description Sheet 3 of 7 Name Type Description DINV 3 0 Input Ou
25. Icc Deeper Sleep 3 2 A 3 4 Vcc Power Supply Current Slew Rate at dIcc or a die 600 A us 7 Processor Package Pin IccA Icc for Vcc Supply 130 mA I Icc for Vccp Supply before Vcc Stable 4 5 A 8 nd for VecpSupply after Vec Stable B 2 5 A 9 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and can not be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event ex Extended Halt State The voltage specifications are assumed to be measured across Vecsense and Vsssense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 mQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 100 C Tj Specified at nominal Vcc Datasheet 29 intel Electrical Specifications 5 800 MHz FSB supported 6 Measured at the bulk capacitors on the motherboard 7 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 8 This is a power up peak current spe
26. Lower Left 5 6 43 18 SFF Processor Top View Lower Right 5 6 44 19 Pin Listing DY Pin ten er ak eaaa ER ERA mUNE DUE 45 20 Pin Listing by Pin Number 52 21 SFF Listing by Ball Name cese cricidneatnccenes nr tnm aa E A EE EE 61 22 Signal Description 2o sa Dra exta db us 75 23 Power Specifications for the 3x00 Celeron 6 eee eset nnm 83 24 Power Specifications for the Intel Celeron Dual Core Processor Standard Voltage 83 25 Power Specifications for the Ultra Low Voltage Dual Core 1M Cache Intel Celeron SFF Genuine Intel Processor iiis eue dece ci ure cael sor ar tuner oa de a a me 84 26 Thermal Diode Interface MEAE ERR cine 85 27 Thermal Diode Parameters Using Diode 86 28 Thermal Diode Parameters Using Transistor 87 29 Thermal Diode ntrim and Diode Correction To
27. PLL and stops all internal clocks The Sleep state is entered through assertion of the SLP signal while in the Stop Grant state The SLP pin should only be asserted when the processor is in the Stop Grant state SLP assertions while the processor is not in the Stop Grant state is out of specification and may result in unapproved operation In the Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions or assertions of signals with the exception of SLP DPSLP or RESET are allowed on the FSB while the processor is in Sleep state Snoop events that occur while in Sleep state or during a transition into or out of Sleep state causes unpredictable behavior Any transition on an input signal before the processor has returned to the Stop Grant state results in unpredictable behavior If RESET is driven active while the processor is in the Sleep state and held active as specified in the RESET pin specification then the processor resets itself ignoring the transition through Stop Grant state If RESET is driven active while the processor is in the Sleep state the SLP and STPCLK signals should be deasserted immediately after RESET is asserted to ensure the processor correctly executes the Reset sequence While in the Sleep state the processor is capable of entering an even lower power state the Deep Sleep state by asserting the DPSLP pin See Section 2 1 2 5 While the p
28. Reserved INIT B3 CMOS Input D 55 AE22 Source Synch d LINT1 B4 CMOS Input VSS AE23 Power Other DPSLP Ba GMOS input VSS B6 Power Other D 48 AE24 Source Synch IP Output VCC B7 Power Other DSTBN 3 AE25 Source Synch ne MSS Pe Power CUIRE vcc B9 Power Other VSS AE26 Power Other VCC B10 Power Other TESIS iis lest VSS B11 Power Other VSS AF2 Power Other VCC B12 Power Other VID 5 AF3 CMOS Output VSS B13 Power Other VID 3 AF4 CMOS Output VCC B14 Power Other VID 1 AF5 CMOS Output VCC B15 Power Other VSS AF6 Power Other B16 Power Other VCCSENSE AF7 Power Other VCC B17 Power Other VSS AF8 Power Other VCC B18 Power Other vcc AF9 Power Other VSS B19 Power Other VCC AF10 Power Other VCC B20 Power Other VSS AF11 Power Other VSS B21 Power Other VCC AF12 Power Other Datasheet 55 intel Package Mechanical Specifications and Pin Information Table 20 Pin Listing by Pin Number Table 20 Pin Listing by Pin Number Sheet 8 of 17 Sheet 9 of 17 Pin Name VE Buffer Direction Pin Name ae Buteet Tune Direction BSEL 0 B22 CMOS Output STPCLK D5 CMOS Input BSEL 1 B23 CMOS Output PWRGOOD D6 CMOS Input vss B24 Power Other SLP D7 CMOS Input THRMDC B25 Power Other VSS D8 Power Other VCCA B26 Power Other VCC D9 Power Other RESET Ci i Input vcc D10
29. T22 Source Synch Output D 59 AD21 Source Synch Output D 38 U25 Source Synch D 60 4 AC22 Source Synch 1nPut Output Output 3914 U23 Source Synch InPut D 61 4 AD23 Source Synch l PuU Output Output D 40 Y25 Source Synch In Put D 62 AF22 Source Synch Input Output Output D 41 w22 Source Synch I Put D 63 4 AC23 Source Synch Input Output Output D 42 4 Y23 Source Synch UE c20 CMS Output Input DBSY E1 Common Clock cad D 43 amp W24 Source Synch ou PN P DEFER H5 Common Clock Input Input w25 Source Synch Output DINV 0 H25 Source Synch Input Output Input Didala AA23 Source Synch Output DINV 1 N24 Source Synch InPut Output Input D 46 AA24 Source Synch Output DINV 2 U22 Source Synch Input Output Input ADAS Source Synch Output DINV 3 AC20 Source Synch IPPut Output D 48 AE24 Source Synch e DPRSTP E5 CMOS Input TET DPSLP BS CMOS Input D 49 AD24 Source Synch Bur d TET DPWR D24 Common Clock D 50 AA21 Source Synch ie T P DRDY F21 Common Clock D 51 AB22 Source Synch did DU P DSTBN 0 126 Source Synch D 52 AB21 Source Synch id TN P DSTBN 1 L26 Source Synch 5314 AC26 Source Synch dd pu DSTBN 2 Y26 Source Synch mt D 54 AD20 Source Synch di DUTY P DSTBN 3 AE25 Source Synch ona 5514 22 Source Synch P DSTBP 0 H26 Source Synch Su D 56 AF23 Source Synch TY P DST
30. and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error IGNNE Input IGNNE has no effect when the NE bit in control register 0 CRO is set IGNNE is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an Input Output Write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must connect the appropriate pins of both FSB agents If INIT is sampled active on the active to inactive transition of RESET then the processor executes its Built in Self Test BIST INIT Input 78 Datasheet Package Mechanical Specifications and Pin Information Table 22 intel Signal Description Sheet 5 of 7 Name Ty
31. are driven by the processor The voltage supply for these pins must be valid before the VR can supply Vcc to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations See Table 2 for definitions of these pins The VR must supply the voltage that is requested by the pins or disable itself Vss SENSE Output Vss sENsE together with Vcc sense are voltage feedback signals to Intel MVP 6 that control the 2 1 mQ loadline at the processor die It should be used to sense ground near the silicon with little noise Datasheet 8 81 82 Package Mechanical Specifications and Pin Information Datasheet m Thermal Specifications and Design Considerations n tel 5 Thermal Specifications and Design Considerations Maintaining the proper thermal environment is key to reliable long term system operation A complete thermal solution includes both component and system level thermal management features The system processor thermal solution should be designed so that the processor remains within the minimum and maximum junction temperature Tj specifications at the corresponding thermal design power TDP value listed in Table 24 through Table 26 Caution Operating the processor outside
32. internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK Input TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI Input TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for JTAG specification support TDO Output TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for JTAG specification support TEST1 TEST2 TEST3 TESTA TESTS TEST6 Input TEST1 and TEST2 must have a stuffing option of separate pulldown resistors to Vss For the purpose of testability route the TEST3 and TESTS5 signals through a ground referenced Zo 55 trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection THRMDA THRMDC Other Other Thermal Diode Anode Thermal Diode Cathode 80 Datasheet Package Mechanical Specifications and Pin Information Table 22 intel Signal Description Sheet 7 of 7 Name Type Description THERMTRIP Output The process
33. is high and Vcc core is low 10 This is a steady state Icc current specification which is applicable when both Vccp and Vcc coRE are high 11 512 KB L2 cache 28 Datasheet Electrical Specifications i n tel Table 8 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages The Highest Frequency Mode HFM and Lowest Frequency Mode LFM refer to the highest and lowest core operating frequencies supported on the Genuine Intel Processor Unless specified otherwise all specifications for the processor are at Tjunction 2100 C Care should be taken to read all notes associated with each parameter Table 8 Voltage and Current Specifications for the Ultra Low Voltage Dual Core 1M Cache Intel Celeron SFF Genuine Intel Processor Symbol Parameter Min Typ Max Unit Notes Vcc of the Processor Core 0 8 1 1 V 1 2 Vcc Boor Default Vcc Voltage for Initial Power Up 1 20 V 2 8 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VccA PLL Supply Voltage 1 425 1 5 1 575 V IccpEs Icc for Processors Recommended Design Target 18 A 5 Icc for processors A Processor Icc i i Number Frequency Die Variant SU2300 1 2GHz 1MB 17 6 A 3 4 Ian Icc Auto Halt amp Stop Grant A 3 4 IsaNr 6 3 5 9 Isip Icc Sleep A 3 4 Ipsip Icc Deep Sleep 5 0 A 3 4 TpprsLp
34. is the external resistor on the comp pins 11 On die termination resistance measured at 0 33 Vccp 31 Electrical Specifications intel Table 11 CMOS Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vccp I O Voltage 1 00 1 05 1 10 V Vin Input High Voltage 0 7 Vccp Vccp Vccp 0 1 V 2 Input Low Voltage Val MOS 9 0 10 0 00 0 3 Vccp V 2 VoH Output High Voltage 0 9 Vccp Vccp Vccp t 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 Vccp V 2 Tou Output High Current 1 5 4 1 mA 5 Io Output Low Current 1 5 4 1 mA 4 Input Leakage Current 100 HA 6 Cpadi Pad Capacitance 1 6 2 1 2 55 pF 7 Pad Capacitance for Cpad2 CMOS Input 0 95 1 2 1 45 3 NOTES 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccp referred to in these specifications refers to instantaneous Vccp 3 Cpad2 includes die capacitance for all other CMOS input signals No package parasitics are included 4 Measured at 0 1 Vccp 5 Measured at 0 9 Vccp 6 For Vin between 0 V and Vccp Measured when the driver is tristated 7 Cpad1 includes die capacitance only for DPRSTP DPSLP PWRGOOD No package parasitics are included Table 12 Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes VoH Output High Voltage Vccp 5 Vccp Vccpt 596 V 3 VoL Output Low Voltage 0 0 20 V
35. m e t Deeper Sleep includes the Deeper Sleep state and Deep C4 sub state 11 Low Power Features intel Figure 2 Core Low Power States 2 1 1 2 1 1 1 2 1 1 2 12 lt STI POLK srake asserted deasserted N STPCLK N STPCLK gU deasserted asserted LT x E STPCLK NC EN V amp d deasserted STPCLK Y ci Auto v Halt J CL MWATT asserted Core state C es break E instruction Pu P mE L TS Pd MWAT CD b M _Halt break co a P_LVL2 or L MWAIT C2 Core State a 2 p break how Core state u break cr P_LVL4 PLLVL3 or MWAIT C4 Core MWAIT C3 N 2 ha a state d el k N uM x m break A20M transition INIT INTR NMI PREQ RESET SMI or APIC interrupt state break halt break OR Monitor event AND STPCLK high not asserted STPCLK assertion and de assertion have no effect if a core is in C2 C3 or C4 Core C4 state supports the package level Deep C4 sub state Core Low Power States CO State This is the normal operating state of the processor C1 AutoHALT Powerdown State C1 AutoHALT is a low power state entered when the processor core executes the HALT instruction The processor core transitions to the CO state upon the occurrence of SMI INIT LINT 1 0 NMI INTR or FSB interrupt message RESET causes the processor to immediat
36. of the Intel Thermal Monitor Thermal Diode Interface Signal Name Pin Ball Number Signal Description THERMDA A24 Thermal diode anode THERMDC A25 Thermal diode cathode 85 Table 27 86 intel Thermal Specifications and Design Considerations Thermal Diode Parameters Using Diode Model Symbol Parameter Min Typ Max Unit Notes Igw Forward Bias Current 5 200 HA 1 n Diode Ideality Factor 1 000 1 009 1 050 2 3 4 Ry Series Resistance 2 79 4 52 6 24 Q 2 3 5 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range 2 Characterized across a temperature range of 50 100 C 3 Not 100 tested Specified by design characterization 4 The ideality factor n represents the deviation from ideal diode behavior as exemplified by the diode equation Igw Ig e QVp nKT 1 where Is saturation current q electronic charge Vp voltage across the diode k Boltzmann Constant and T absolute temperature Kelvin 5 The series resistance Ry is provided to allow for a more accurate measurement of the junction temperature Ry as defined includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote di
37. processor is in Deep Sleep state Any transition on an input signal before the processor has returned to Stop Grant state results in unpredictable behavior Deeper Sleep State The Deeper Sleep state is similar to the Deep Sleep state but further reduces core voltage levels One of the potential lower core voltage levels is achieved by entering the base Deeper Sleep state The Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep state The following lower core voltage level is achieved by entering the Intel Enhanced Deeper Sleep state which is a sub state of Deeper Sleep state Intel Enhanced Deeper Sleep state is entered through assertion of the DPRSTP pin while in the Deep Sleep only when the L2 cache has been completely shut down Exit from Deeper Sleep is initiated by DPRSTP deassertion when either core requests a core state other than C4 or either core requests a processor performance state other than the lowest operating point Enhanced Intel SpeedStep Technology Some processors feature Enhanced Intel SpeedStep Technology See each processor s DCL to see if it supports Enhanced Intel SpeedStep Technology Following are the key features of Enhanced Intel SpeedStep Technology e Multiple voltage and frequency operating points provide optimal performance at the lowest power Voltage and frequency selection is software controlled by writing to processor MSRs If the target frequency is
38. rising edge of BCLKO ADS HIT HITM etc and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as the rising edge of BCLKO Asychronous signals are still present A20M IGNNE etc and can become active at any time during the clock cycle Table 4 identifies which signals are common clock source synchronous and asynchronous 23 intel Electrical Specifications Table 4 FSB Pin Groups Signal Group Type Signals AGTL Common Clock Input SYNChronous BPRI DEFER PREQ 5 RESET RS 2 0 TRDY to BCLK 1 0 Synchronous ADS BNR BPM 3 0 2 BRO DBSY DRDY HIT AGTL Common Clock I O to BCLK 1 0 HITM LOCK PRDY 3 DPWR AGTL Strobes to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 Signals Associated Strobe REQ 4 0 A 16 3 ADSTB 0 A 35 17 ADSTB 1 Synchronous D 15 0 DSTBPO siu Source Synchronous ao assoc DINVO DSTBNO strobe D 31 16 DSTBP1 DINV1 DSTBN1i D 47 32 DSTBP2 DINV2 DSTBN2 D 63 48 DSTBP3 DINV3 DSTBN3 Synchronous A20M DPRSTP DPSLP IGNNE INIT LINTO INTR CMOS Input Asynchronous INT1 NMI PWRGOOD SMI SLP STPCLK Open Drain Output Asynchronous FERR IERR THERMTRIP Open Drain 1 0 Asynchronous PROCHOT 4 CMOS Output Asynchronous PSI VID 6 0 BSEL 2 0 Synchro
39. vec vec vec vec vec vec vec vec 34 M TM vss vss vec vss vss vss vss vss vss 35 DISS Diez vss vss vss VCCP vecP VCCP 36 vss vss ee vss vss vss vccP vss vss DINVIS 37 Disaj vss vss vss vccP DSTBP 38 vss DISS ph 8 vss VCCP vss vccP vss VCCP vss 39 D 59y vss vss vss vss vss vss vss vss vss vss DSTBN 40 vss Diet E Diso D 57 Djs Diaz Dj43yf D 34 3518 D 26y DINVI2 41 vss Deo D52 DIS3 6 DIATH M D 37 TESTA D 27y 42 vss vss vss vss vss vss vss vss vss vss 43 vss uia D ey Disa Djan gil D 36ji p TEST6 44 vss vss DIAS 2 DISS ud 43 intel Table 18 44 Package Mechanical Specifications and Pin Information SFF Processor Top View Lower Right Side 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 BSEL 1 38 BSEL 2 39 40 41 D 25 D 24 DI17 D 23 Dt t D 20 DINV O Djo Di12 Di13 42 43 D 19 D 30 D 28 DINV 1 D 16jf D 22jf D 14f D 159f Datasheet Package Mechanical Specifications and Pin Information intel
40. 0 1 0 5375 1 0 0 1 1 1 0 0 5250 1 0 0 1 1 1 1 0 5125 1 0 1 0 0 0 0 0 5000 1 0 1 0 0 0 1 0 4875 1 0 1 0 0 1 0 0 4750 1 0 1 0 0 1 1 0 4625 1 0 1 0 1 0 0 0 4500 1 0 1 0 1 0 1 0 4375 1 0 1 0 1 1 0 0 4250 1 0 1 0 1 1 1 0 4125 1 0 1 1 0 0 0 0 4000 1 0 1 1 0 0 1 0 3875 1 0 1 1 0 1 0 0 3750 1 0 1 1 0 1 1 0 3625 1 0 1 t t 0 0 0 3500 1 0 1 1 1 0 1 0 3375 1 0 1 1 1 1 0 0 3250 1 0 1 1 1 1 1 0 3125 1 1 0 0 0 0 0 0 3000 1 1 0 0 0 0 1 0 2875 1 1 0 0 0 1 0 0 2750 1 1 0 0 0 1 1 0 2625 1 1 0 0 1 0 0 0 2500 1 1 0 0 1 0 1 0 2375 1 1 0 0 1 1 0 0 2250 1 1 0 0 1 1 1 0 2125 1 1 0 1 0 0 0 0 2000 1 1 0 1 0 0 1 0 1875 1 1 0 1 0 1 0 0 1750 1 1 0 1 0 1 1 0 1625 1 1 0 t t 0 0 0 1500 1 1 0 1 1 0 1 0 1375 1 1 0 1 1 1 0 0 1250 1 1 0 1 1 1 1 0 1125 1 1 1 0 0 0 0 0 1000 1 1 1 0 0 0 1 0 0875 1 1 1 0 0 1 0 0 0750 1 1 1 0 0 1 1 0 0625 21 i n t el Electrical Specifications Table 2 3 4 3 5 22 Voltage Identification Definition Sheet 4 of 4 VID6 VID5 VIDA VID3 VID2 VID1 VIDO Vcc V 1 1 1 0 1 0 0 0 0500 1 1 1 0 1 0 1 0 0375 1 1 1 0 1 1 0 0 0250 1 1 1 0 1 1 1 0 0125 1 1 1 1 0 0 0 0 0000 1 1 1 1 0 0 1 0 0000 1 1 1 1 0 1 0 0 0000 1 1 1 1 0 1 1 0 0000 1 1 1 1 1 0 0 0 0000 1 1 1 1 1 0 1 0 0000 1 1 1 1 1 1 0 0 0000 1 1 1 1 1 1 1 0 0000 Catastrophic Thermal Protection The processor supports the THERMTRIP signal for catastrophic thermal pro
41. AL27 VSS AL29 VSS AL31 VSS AL39 VSS AM6 VSS AM8 VSS AM10 VSS AM12 VSS AM34 VSS AM36 VSS AM38 VSS AM42 VSS AN3 VSS AN15 VSS AN17 VSS AN19 69 intel Signal Name e VSS AN21 VSS AN23 VSS AN25 VSS AN27 VSS AN29 VSS AN31 VSS AN39 VSS AP6 VSS AP8 VSS AP34 VSS AP42 VSS AR3 VSS AR15 VSS AR17 VSS AR19 VSS AR21 VSS AR23 VSS AR25 VSS AR27 VSS AR29 VSS AR31 VSS AR35 VSS AR37 VSS AR39 VSS AT6 VSS AT8 VSS AT10 VSS AT12 VSS AT36 VSS AT38 VSS AT42 VSS AU3 VSS AU7 VSS AU9 VSS AU15 VSS AU17 VSS AU19 VSS AU21 70 Package Mechanical Specifications and Pin Information Signal Name VSS AU23 VSS AU25 VSS AU27 VSS AU29 VSS AU31 VSS AU35 VSS AU37 VSS AU39 VSS AV6 VSS AV12 VSS AV34 VSS AV36 VSS AV42 VSS AV44 VSS AW1 VSS AW3 VSS AW9 VSS AW11 VSS AW13 VSS AW15 VSS AW17 VSS AW19 VSS AW21 VSS AW23 VSS AW25 VSS AW27 VSS AW29 VSS AW31 VSS AW33 VSS AW35 VSS AW37 VSS AW39 VSS AY6 VSS AY12 VSS AY34 VSS AY42 VSS AY44 VSS B4 Datasheet Package Mechanical Specifications and Pin Information
42. BASIC H5 15 875 BASIC 0 3560 C A B 2 0340 08 m 1 27 BASIC go 254 C 72 1 27 BASIC 20 65 MAX gp P 0 255 0 355 P DIE 689 kPa Detail A w 6g Scale 20 Keying Pins A1 B1 36 Datasheet Package Mechanical Specifications and Pin Information n t e Figure 6 2 Micro FCPGA Processor Package Drawing Sheet 2 of 2 4X 7 00 4X 7 00 5 00 Side View Edge Keep Out Corner Keep Out Zone 4X Zone 4X Top View 0 305 0 25 90 406 WCA B 13 97 60 254 C 1 625 9o Lisz 99 6 00000000000 00000 v 1 5 Max Allowable Component Height Bottom View Datasheet 37 I0 85 98 2ISV8 9 0 DISva 9 0 1598 v Z OT z 91598 TH DISVE 9 53 956 91998 89b 0Z Ty er aoe sse o soz o 5 gia Guiuedo 151591 19 09 Lv9 l 9260 ajeweig PN v0 0T9v 00 XV NIW SW313WITIIMW SLNIWWOD TOSWAS Package Mechanical Specifications and Pin Information M3IA WOLLOd Tc g 11v13a aas by Zh Ob BE 9E VEZE OE SC IZ vC ZZ OC ST9T VTZL OT 8 9 Eb Th 6 LE SEEE TE 6Z SZ EC TC 6T T STETIT 6 L S I le o Lo
43. BP 1 M26 Source Synch uu D 57 AC25 Source Synch eae P DSTBP 2 AA26 Source Synch Su Input D 58 AE21 Source Synch Output Datasheet 47 intel Package Mechanical Specifications and Pin Information Table 19 Pin Listing by Pin Name Table 19 Pin Listing by Pin Name Sheet 7 of 16 Sheet 8 of 16 r Pin Signal Buffer i Pin Signal Buffer Pin Name Number Type Direction Pin Name Number Type Direction DSTBP 3 AF24 Source Synch ai RSVD Fe Reserved P RSVD M4 Reserved FERR A5 Open Drain Output RSVD N5 Reserved GTLREF AD26 Power Other Input RSVD T2 Reserved HIT G6 Common Clock Input RSVD V3 Reserved Output SLP D7 CMOS Input HITM E4 Common Clock Input Output SMI A3 CMOS Input IERR D20 Open Drain Output STPCLK D5 CMOS Input IGNNE C4 CMOS Input TCK AC5 CMOS Input INIT B3 CMOS Input TDI AA6 CMOS Input LINTO C6 CMOS Input TDO AB3 Open Drain Output LINT1 B4 CMOS Input TEST1 C23 Test LOCK H4 Common Clock pase D25 Test spe TEST3 C24 Test PRDY AC2 Common Clock Output TEST4 AF26 Test PREQ AC1 Common Clock Input TESTS Test PROCHOT D21 Open Drain Input TEST6 A26 Test Output PSI AEG CMOS Output pean Neg Open Drain Output CMOS Input THRMDA A24 Power Other REQ 0 K3 Source Synch Sut THRMDC B25 Power Other TMS AB5 CMOS I
44. C N33 VCC P16 VCC P18 VCC P20 VCC P22 VCC P24 VCC P26 VCC P28 VCC P30 VCC P32 VCC R33 VCC T16 65 intel Signal Name Piso E VCC T18 VCC T20 VCC T22 VCC T24 VCC T26 VCC T28 VCC T30 VCC T32 VCC U33 VCC V16 VCC V18 VCC V20 VCC V22 VCC V24 VCC V26 VCC V28 VCC v30 VCC V32 VCC w33 VCC Y16 VCC Y18 VCC Y20 VCC Y22 VCC Y24 VCC Y26 VCC Y28 VCC Y30 VCC Y32 VCCA B34 VCCA D34 VCCP A13 VCCP A33 VCCP AA7 VCCP AA9 VCCP AA11 VCCP AA13 VCCP AA35 VCCP AA37 66 Package Mechanical Specifications and Pin Information Signal Name m VCCP AB10 VCCP AB12 VCCP AB14 VCCP AB36 VCCP AB38 VCCP AC7 VCCP AC9 VCCP AC11 VCCP AC13 VCCP AC35 VCCP AC37 VCCP AD14 VCCP AE7 VCCP AE9 VCCP AE11 VCCP AE13 VCCP AE35 VCCP AE37 VCCP AF10 VCCP AF12 VCCP AF14 VCCP AF36 VCCP AF38 VCCP AG7 VCCP AG9 VCCP AG11 VCCP AG13 VCCP AG35 VCCP AG37 VCCP AH14 VCCP AJ7 VCCP AJ9 VCCP AJ11 VCCP AJ13 VCCP AJ35 VCCP AJ37 VCCP AK10 VCCP AK12 Datasheet Package Mechanical Specifications and Pin Information
45. CC E13 Power Other VID 3 AF4 CMOS Output VCC E15 Power Other VID 4 AE3 CMOS Output VCC E17 Power Other VID 5 AF3 CMOS Output VCC E18 Power Other VID 6 AE2 CMOS Output vcc E20 Power Other VSS A2 Power Other vcc F7 Power Other VSS A4 Power Other vcc F9 Power Other VSS A8 Power Other vcc F10 Power Other VSS A11 Power Other vcc F12 Power Other VSS A14 Power Other vcc F14 Power Other VSS A16 Power Other VCC F15 Power Other VSS A19 Power Other VCC F17 Power Other VSS A23 Power Other VCC F18 Power Other VSS A25 Power Other VCC F20 Power Other VSS AA2 Power Other VCCA B26 Power Other VSS AA5 Power Other VCCA C26 Power Other VSS AA8 Power other VCCP G21 Power Other VSS AA11 Power Other VCCP J6 Power Other VSS AA14 Power Other VCCP J21 Power Other VSS AA16 Power Other VCCP K6 Power Other VSS AA19 Power Other VCCP K21 Power Other VSS AA22 Power Other VCCP M6 Power Other VSS AA25 Power Other VCCP M21 Power Other VSS AB1 Power Other VCCP N6 Power Other VSS ABA Power Other VCCP N21 Power Other VSS 8 Power Other VCCP R6 Power Other VSS AB11 Power Other VCCP R21 Power Other VSS AB13 Power Other VCCP T6 Power Other VSS AB16 Power Other VCCP T21 Power Other VSS AB19 Power Other VCCP V6 Power Other VSS AB23 Power Other VCCP V21 Power Other VSS AB26 Power Other VCCP W21 Power Other VSS AC3 Power Other VCCSENSE AF7 Power Other VSS AC6 Power Other VID O0 AD6 CMOS Output VSS AC8 Power Other VID 1 AF5 CMOS Output VSS AC11 Power Other 50 Datasheet Pac
46. Celeron Mobile Processors 28 8 Voltage and Current Specifications for the Ultra Low Voltage Dual Core 1M Cache Intel Celeron SFF Genuine Intel ProC SSOF cceeceeee eee eee enses nennen eee 29 9 FSB Differential BCLK Specifications ener anne nna nhau 30 10 AGTL Signal Group DC 5 31 11 CMOS Signal Group DC Specifications 0 cece cece 32 12 Open Drain Signal Group DC 5 eene 32 13 The Coordinates of the Processor Pins as Viewed from the Top of the Package eae Rode 39 14 The Coordinates of the Processor Pins as Viewed from the Top of the Package Sheet 2 of RE needs 15 SFF Processor Top View Upper Left 8 6 n enn 41 16 SFF Processor Top View Upper Right 5 6 42 17 SFF Processor Top View
47. Considerations 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached Refer to Section 5 1 for details The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications At Tj of 100 C At Tj of 50 C At Tj of 35 C 512 KB L2 cache gt ee os Table 25 Power Specifications for the Ultra Low Voltage Dual Core 1M Cache Intel Celeron SFF Genuine Intel Processor Processor Thermal Design s Symbol Number Core Frequency Power Unit Notes TDP SU2300 1 2 GHz 10 WwW 1 4 5 Symbol Parameter Min Typ Max Unit Notes Pau Auto Halt Stop Grant Power 2 9 Ww 2 6 PsGnt Psip Sleep Power 2 9 Ww 2 6 Ppsip Deep Sleep Power 1 3 Ww 2 7 PDPRSLP Deeper Sleep Power 0 6 WwW 2 7 T Junction Temperature 0 100 e 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on die Intel Thermal Monitor The Intel Thermal Monitor s automatic mode is used to indicate that the maximum T has been reached Refer to Sectio
48. DSTBN 1 amp L26 Source Synch IPut D 10 J24 Source Synch pu g y Output Output 55 125 Power Other ADSTB O M1 Source Synch IPPuU y Output Input DSTBN O 126 Source Synch Output VSS M2 Power Other Input VSS K1 Power Other A 7 M3 Source Synch Output REQ 2 K2 Source Synch InPut RSVD M4 Reserved y Output VSS M5 Power Other REQ O K3 Source Synch Input y Output VCCP M6 Power Other VSS K4 Power Other VCCP M21 Power Other 614 K5 Source Synch VSS M22 Power Other Input VCCP K6 Power Other D 23 Mas Source Synch Output MEME Ret D 21 M24 Source Synch Input D 14 mee Source Synch Output vss M25 Power Other 58 Datasheet Package Mechanical Specifications and Pin Information intel Table 20 Pin Listing by Pin Number Table 20 Pin Listing by Pin Number Sheet 14 of 17 Sheet 15 of 17 Pin Signal Pin Signal i 3 Pin Name Number Buffer Type Direction Pin Name Number Buffer Type Direction DSTBP 1 M26 Source Synch d Vm Be Power ON er Input VSS N1 Power Other A 19 Ba Source Synch Output Input Input A 8 N2 Source Synch Output A 24 R4 Source Synch Output A 10 N3 Source Synch dud Wee Ra Pow r other P VCCP R6 Power Other VSS i Power Other VCCP R21 Power Other Reve
49. Intel Celeron Mobile Processor Dual Core on 45 nm Process Datasheet For Platforms Based on Mobile Intel 4 Series Express Chipset Family September 2009 Document Number 321111 003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS OTHERWISE AGREED IN WRITING BY INTEL THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH MAY OCCUR Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The information here is subject to change without notice Do not finalize a design wit
50. MB Micro FCPGA Processor Package Drawing Sheet 1 of 2 32 6 2 MB Micro FCPGA Processor Package Drawing Sheet 2 of 2 33 Tables 1 Coordination of Core Level Low Power States at the Package 11 2 Voltage Identification Definition ease nnnan hene na nan hens n aa sanus ane dana 17 3 BSEL 2 0 Encoding for BCLK 21 4 FSB Pin Groups ME 22 5 Processor Absolute Maximum nee 23 6 DC Voltage and Current cece eee eee eee ens 25 7 5 Differential BCLK 5 iraia ian nn Ea E E TA 26 8 AGTL Signal Group DC Specifications cece 27 9 CMOS Signal Group DC
51. Pin Number Table 20 Pin Listing by Pin Number Sheet 10 of 17 Sheet 11 of 17 Pin Signal A Pin Signal z Pin Name Number Buffer Type Direction Pin Name Number Buffer Type Direction vcc E12 Power Other vcc F18 Power Other VCC E13 Power Other VSS F19 Power Other VSS E14 Power Other VCC F20 Power Other VCC E15 Power Other DRDY F21 did vss E16 Power Other P VCC E17 Power Other vss F22 Power Other Input VCC E18 Power Other D 4 F23 Source Synch Output vss E19 Power Other 114 F24 Source Synch Input vcc E20 Power Other Output vss E21 Power Other VSS F25 Power Other Input Input D 0 E22 Source Synch Output D 13 F26 Source Synch Output D 7 E23 Source Synch we G1 Power Other Common VSS E24 Power Other 55 Clock Input Input Common D 6 E25 Source Synch Output RS 2 G3 Clock Input D 2 E26 Source Synch dowd MES 64 Power Stier Common Common Input G5 Clock Input BRO F1 Clock Output HIT G6 Common Input VSS F2 Power Other Clock Output RS 0 F3 m Input VCCP G21 Power Other 314 G22 Source Synch a RS 1 F4 E Input P VSS G23 Power Other VSS F5 Power Other D 9 G24 Source Synch IPut RSVD F6 Reserved Output uC Power 514 G25 Source Synch re vss F8 Power Other P VCC F9 Power Other VSS G26 Power Other Common Input vcc F10 Power Other ADS 1 Clock Output VSS F11 Power Other REQ 1 H2 Source Synch IPut VCC F12 Power Other y Output VSS F13 Power Other VSS H3 Pow
52. Power Other VSS D11 Power Other yen Ca Power other VCC D12 Power Other RSVD Reserved VSS D13 Power Other IGNNE C4 CMOS Input VCC D14 Power Other ves G gt Power other VCC D15 Power Other CINTO es cmos Input VSS D16 Power Other eee C7 Open Drain Output VCC D17 Power Other vss C8 Power Other vcc D18 Power Other VCC C9 Power Other VSS D19 Power Other VCC C10 Power Other IERR D20 Open Drain Output VSS C11 Power Other PROCHOT D21 Open Drain en vcc C12 Power Other RSVD D22 Reserved iin ic VSS D23 Power Other VSS C14 Power Other NEN m Commo Input VCC C15 Power Other Clock Output VSS C16 Power Other TEST2 D25 Test vcc C17 Power Other VSS D26 Power Other VCC C18 Power Other DBSY vss C19 Power Other DBR C20 CMOS Output BNR E2 Een 2 C21 CMOS Output vss E3 Power Other VSS C22 Power Other mW 7 Pominen Input TEST1 C23 Test Clock Output TEST3 C24 Test DPRSTP E5 CMOS Input vss C25 Power Other VSS E6 Power Other VCCA C26 Power Other VCC E7 Power Other VSS D1 Power Other VSS E8 Power Other RSVD D2 Reserved VCC E9 Power Other RSVD D3 Reserved VCC E10 Power Other VSS D4 Power Other VSS E11 Power Other 56 Datasheet Package Mechanical Specifications and Pin Information intel Table 20 Pin Listing by
53. REGIS aps vss VCCP K vss REQ 2 REGIO vss A 6 amp vCCP L REQ 4 A 13 vss asje A 4 vss M ADSTBLO vss A 7 RSVD vss VCCP N vss A 8 A 10 amp vss RSVD VCCP P acisj A2 vss atiaj atiij vss R 6 vss 9 4 2411 vss VCCP f vss rsvp A 26 vss 2514 u A23 3011 vss at2ij 1811 vss AE vss RSVD 3114 vss VCCP w vss 27 ats2j vss 2814 2014 v cowe3 A27 vss 29 4 2211 vss AA CoMP 2 vss 3514 3311 vss TDI vss vss vcc vcc vss 4 TDO vss TMS TRST vcc vss vcc vcc vss vcc vss PREQ amp pRoy vss 3 vss vcc vss vcc vss vcc vcc AD 214 vss wss vippo vss vcc vcc vss vcc vss vss viote VID 4 vss VIDI2 psi vss vcc vcc vss vcc vcc AF TESTS vss VID S VID 3 VID vss o S amp vss vcc vcc vss vcc vss 1 2 3 4 5 6 7 8 9 10 11 12 13 Datasheet 39 m n tel Package Mechanical Specifications and Pin Information Table 14 The Coordinates of the Processor Pins as Viewed from the Top of the Package Sheet 2 of 2 14 15 16 17 18 19 20 21 22 23 24 25 26 a
54. RRA Ra Xa RA uad 13 2 2 Low PowerFSB cies cates serere ees ce xen ia Rame a SR RER MEER RN a IRR eeeatectavents 15 2 3 Processor Power Status Indicator PSI 5 8 15 3 Electrical Specifications oreei re renean erwewehtielnd a auin ea dene n et heneteeedensiadeveannae 17 3 1 Powerand Ground Pins cie eere ring pd eat Dad eos AR Aue HERD E ex Eum 17 3 2 FSB Clock BCLK 1 0 and Processor Clocking esee 17 3 3 Woltage IdentificatiOm z i iu cete ep IRR ER RA ED FORME ERE aes 17 3 4 Catastrophic Thermal Protection cccceceee cece e eee eee eee eee eee ee ee nemen emen nene 20 3 5 Reserved and Unused Pis oa ext hare a px aAA Rar ku ea EX INR rian RA 20 3 6 FSB Frequency Select Signals BSEL 2 0 sese 21 3 7 FSB iecit es E SIE ERE ADDE 21 358 CMOS ERE 23 3 9 Maximum Ratings UE E NEA EA 23 3 10 Processor DC Specifications srr sari oramsa s ce ded ies ve paga ka oa PaSa 24 4 Package Mechanical Specifications and Pin Information sssessesss 29 4 1 Package Mechanical
55. S AD25 Power Other D 60 AC22 Source Synch Output GTLREF AD26 Power Other Input D 63 4 AC23 Source Synch dd AES Rae eer P VID 6 AE2 CMOS Output VSS AC24 Power Other VID 4 AE3 CMOS Output Input D 57 AC25 Source Synch Output VSS AE4 Power Other 54 Datasheet Package Mechanical Specifications and Pin Information intel Table 20 Pin Listing by Pin Number Table 20 Pin Listing by Pin Number Sheet 6 of 17 Sheet 7 of 17 Pin Name now NL aves Direction Pin Name dS dunes aves Direction VID 2 AE5 CMOS Output VSS AF13 Power Other PSI AE6 CMOS Output VCC AF14 Power Other VSSSENSE AE7 Power Other Output vcc AF15 Power Other vss AE8 Power Other VSS AF16 Power Other vcc AE9 Power Other vcc AF17 Power Other vcc AE10 Power Other vcc AF18 Power Other VSS AE11 Power Other VSS AF19 Power Other vcc AE12 Power Other vcc AF20 Power Other vcc AE13 Power Other vss AF21 Power Other ee ATIE FONR ORIET D 62 AF22 Source Synch Suite VCC AE15 Power Other VSS AE16 Power Other D 56 AF23 Source Synch VCC AE17 Power Other Input VCC AE18 Power Other DSTBP 3 AF24 Source Synch Output VSS AE19 Power Other VSS AF25 Power Other VCC AE20 Power Other TEST4 AF26 Test D 58 AE21 Source Synch RSVP
56. b phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents on the processor FSB A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before RESET is deasserted A20M Input If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Input Output ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 and REQ 4 0 pins All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 BCLK 1 0 Input Output Input Address strobes are used to latch A 35 3 and REQ 4 0 on their
57. but the processor does not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK pin is also asserted The processor in C2 state processes only the bus snoops The processor enters a snoopable sub state not shown in Figure 2 to process the snoop and then return to the C2 state Core C3 State Core C3 state is a very low power state the processor core can enter while maintaining context The core of the processor can enter the C3 state by initiating a P LVL3 I O read to the P BLK or an MWAIT C3 instruction Before entering the C3 state the processor core flushes the contents of its L1 cache into the processor s L2 cache Except for the caches the processor core maintains all its architectural state in the C3 state The Monitor remains armed if it is configured All of the clocks in the processor core are stopped in the C3 state Because the core s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB The processor core transitions to the CO state upon the occurrence of a Monitor event SMI INIT LINT 1 0 NMI INTR or FSB interrupt message RESET causes the processor core to immediately initialize itself Core C4 State Individual cores of the dual core processor that have C4 can enter the C4 state by initiating a P_LVL4 I O read to the P BLK or an MWAIT C4 instruction The processor core behavior in the C4 state is nearly identical to the behavior in the C3 sta
58. c for Vccp Supply after Vcc Stable 2 5 A 10 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing in such a way that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 or Extended Halt State 2 The voltage specifications are assumed to be measured across Vcc sense and Vss sense Pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 mQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 3 Specified at 100 C Tj 4 Specified at the nominal Vcc 5 667 MHz FSB supported 6 Instantaneous current Icc core inst Of 55 A has to be sustained for short time tnst of 10 us Average current is less than maximum specified Iccpgs VR OCP threshold should be high enough to support current levels described herein 7 Measured at the bulk capacitors on the motherboard 8 Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested 9 This is a power up peak current specification which is applicable when Vccp
59. cification which is applicable when Vccp is high and Vcc core is low 9 This is a steady state Icc current specification which is applicable when both Vccp and Vec core are high 10 SU2300 processor operates at same core frequency in HFM and LFM Table 9 FSB Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Notes VcRoss Crossing Voltage 0 3 0 55 V 2 7 8 AVcRoss Range of Crossing Points 140 mV 2 7 5 VswinG Differential Output Swing 300 mV 6 Ij Input Leakage Current 5 T5 HA 3 Cpad Pad Capacitance 0 95 1 2 1 45 pF 4 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Crossing Voltage is defined as absolute voltage where rising edge of BCLKO is equal to the 30 ca dl falling edge of BCLK1 For Vin between 0 V and Vj Cpad includes die capacitance only No package parasitics are included AVcnoss is defined as the total variation of all crossing voltages as defined in Note 2 Measurement taken from differential waveform Measurement taken from single ended waveform Only applies to the differential rising edge Clock rising and Clock falling Datasheet Electrical Specifications Table 10 Datasheet AGTL Signal Group DC Specifications Symbol Parameter Min Typ Max Unit Notes Vccp I O Voltage 1 00 1 05 1 10 V GTLREF Reference Voltage 2 3 Vccp 6 Rcomp Compensation Resistor 27 23 27 5 27 78 Q 10
60. commended that routing channels to these pins on the board be kept open for possible future use SLP Input SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state does not recognize snoops or interrupts The processor recognizes only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor exits the Sleep state and transition to the Deep Sleep state SMI Input SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enters System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If an SMI is asserted during the deassertion of RESET then the processor tristates its outputs STPCLK Input STPCLK Stop Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing
61. cpes sal Me opa Targets n A 2 Icc for processors A Icc qund Frequency Die Variant Number T3000 1 8 GHz 1 MB 47 A 3100 1 9 GHz 1 MB 47 3 ae Icc Auto Halt amp Stop Grant 25 4 A 3 4 Isi p Icc Sleep 24 7 A 3 4 Ipsip Deep Sleep 22 9 A 3 4 dico Current Slew Rate at 600 A us 6 7 Icc for Veca Supply 130 mA T c Icc for Vccp Supply before Vcc Stable 4 5 A 9 Icc for Vccp Supply after Vcc Stable 2 5 A 10 NOTES 1 Each processor is programmed with a maximum valid voltage identification value VID which is set at QUT d N 10 manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing in such a way that two processors at the same frequency may have different settings within the VID range Note that this differs from the VID employed by the processor during a power management event Intel Thermal Monitor 2 or Extended Halt State The voltage specifications are assumed to be measured across Vcc sense and Vss sense pins at socket with a 100 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 mQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe Specified at 105 C Tj Specified at the nominal Vcc 800 MHz FSB supported Instantaneous current Icc core inst Of 55 A has to be sustained for short time tis of 10 us Average current is l
62. d be deasserted ten or more bus clocks after the deassertion of SLP AC Specification T75 While in the Stop Grant state the processor services snoops and latch interrupts delivered on the FSB The processor latches SMI INIT and LINT 1 0 interrupts and services only upon return to the Normal state The PBE signal may be driven when the processor is in Stop Grant state PBE is asserted if there is any pending interrupt or monitor event latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear still cause assertion of PBE Assertion of PBE indicates to system logic that the processor should return to the Normal state A transition to the Stop Grant Snoop state occurs when the processor detects a snoop on the FSB see Section 2 1 2 3 A transition to the Sleep state see Section 2 1 2 4 occurs with the assertion of the SLP signal Stop Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop Grant state by entering the Stop Grant Snoop state The processor stays in this state until the snoop on the FSB has been serviced whether by the processor or another agent on the FSB or the interrupt has been latched The processor returns to the Stop Grant state once the snoop has been serviced or the interrupt has been latched Sleep State The Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop
63. e Synch Output Input A 20 W6 Source Synch Output VCCP W21 Power Other 60 Datasheet Package Mechanical Specifications and Pin Information Table 21 SFF Listing by Ball Name Signal Name MUS A 3 P2 414 V4 A 5 W1 A 6 T4 A 7 AA1 A 8 AB4 A 9 T2 A 10 AC5 A 11 AD2 A 12 AD4 A 13 5 A 14 AES 15 4 AB2 16 4 AC1 A 17 AN1 A 18 AK4 19 4 AG1 A 20 AT4 A 21 AK2 A 22 AT2 23 4 AH2 A 24 AF4 A 25 AJ5 A 26 AH4 A 27 AM4 A 28 AP4 A 29 AR5 A 30 AJ1i A 31 AL1 A 32 AM2 A 33 AU5 A 34 AP2 A 35 AR1 A20M C7 ADS M4 ADSTB 0 Y4 Datasheet Signal Name Parn ADSTB 1 AN5 BCLK 0 A35 BCLK 1 C35 BNR J5 BPM 0 AY8 BPM 1 BA7 BPM 2 BA5 BPM 3 AY2 BPRI L5 BRO M2 BSEL 0 A37 BSEL 1 C37 BSEL 2 B38 COMP 0 AE43 COMP 1 AD44 COMP 2 AE1 COMP 3 AF2 D 0 F40 D 1 G43 D 2 E43 D 3 J43 D 4 H40 D 5 H44 D 6 G39 D 7 E41 D 8 L41 D 9 K44 D 10 N41 D 11 T40 D 12 M40 D 13 G41 D 14 M44 D 15 L43 D 16 P44 D 17 40 18 4 V44 D 19 AB44 ntel 61 intel
64. e an interrupt upon the assertion or deassertion of PROCHOT PROCHOT is not be asserted when the processor is in the Stop Grant Sleep Deep Sleep and Deeper Sleep low power states hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification the system must initiate an orderly shutdown to prevent damage If the processor enters one of the above low power states with PROCHOT already asserted PROCHOT will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point If Intel Thermal Monitor automatic mode is disabled the processor will be operating out of specification Regardless of enabling the automatic or on demand modes in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached a temperature of approximately 125 C At this point the THERMTRIP signal will go active THERMTRIP activation is independent of processor activity and does not generate any bus cycles When THERMTRIP is asserted the processor core voltage must be shut down within the time specified in Chapter 3 In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification Digital Thermal Sen
65. e lowest programmed Intel Thermal Monitor 2 performance state It is important to note that Intel recommends both Intel Thermal Monitor 1 and 2 to be enabled Datasheet m Thermal Specifications and Design Considerations i n tel When PROCHOT is driven by an external agent if only Intel Thermal Monitor 1 is enabled on both cores then both processor cores will have their core clocks modulated If Intel Thermal Monitor 2 is enabled on both cores then both processor cores will enter the lowest programmed Intel Thermal Monitor 2 performance state It should be noted that Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2 enabled via BIOS does not have any effect on external PROCHOT If PROCHOT is driven by an external agent when Intel Thermal Monitor 1 Intel Thermal Monitor 2 and Force Intel Thermal Monitor 1 on Intel Thermal Monitor 2 are all enabled then the processor will still apply only Intel Thermal Monitor 2 PROCHOT may be used for thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached By asserting PROCHOT pulled low and activating the TCC the VR will cool down as a result of reduced processor power consumption Bi directional PROCHOT can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the VR and rely o
66. ec D 58 amp D 55 vss pp48 PSTBNIS vss AE vcc vcc vss vec vec vss vcc vss D 62 p seje DSTEPI3 vss TEST4 AF 14 15 16 17 18 19 20 21 22 23 24 25 26 40 Datasheet Package Mechanical Specifications and Pin Information Table 15 Datasheet SFF Processor Top View Upper Left Side BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC 1 vss vss TDO 35 6 ATH ABO ALO EE 2 vss PPS PREQ Ala Alaa S2 AE Al23 3 vss vss vss vss vss vss vss vss vss vss vss 4 vss VIDIS VIDI6 TCK Alo 28 ATI A 18y 6 Alay 120 5 n TMS 33 A 29yie in sepa A Sy ot 4 6 vss vss vss vss vss vss vss vss vss vss vss BPM 1 7 M TDI vss vecP vccP vecP BPM O 8 vino viD 3 bh TRST vss vss vss vss vss vss vss 9 vss vss vss vss veep vecP vccP veep vecP 10 Psi ving TESTS PRDY vss vss vccP vss vss 11 vss vss vss vccP vecP vccP vecP 12 ice vss vss vss vss vss veep vss vss VSSSE 13 Re vss vss vccP vecP vecP 14 vec vec vec vec vec vec vccP vecP vccP 15 vss vss vss vss vss vss vss vss vss vss vss 16 vcc
67. el 4 Series Express Chipset and Intel 828011BM ICH9M Controller Hub Based Systems In this document the Celeron processor is referred to as the processor and Mobile Intel 4 Series Express Chipset family is referred to as the G MCH The following list provides some of the key features on this processor Dual Core processor for mobile with enhanced performance Intel architecture with Intel Wide Dynamic Execution L1 Cache to Cache C2C transfer On die primary 32 KB instruction cache and 32 KB write back data cache in each core On die 1 MB second level shared cache with advanced transfer cache architecture Streaming SIMD Extensions 2 SSE2 Streaming SIMD Extensions 3 SSE3 and Supplemental Streaming SIMD Extensions 3 SSSE3 667 MHz Source Synchronous Front Side Bus FSB for the T1x00 Series and 800 MHz Source Synchronous Front Side Bus FSB for the T3x00 Series processors and SFF processors Digital Thermal Sensor DTS Intel 64 Technology PSI2 functionality Execute Disable Bit support for enhanced security Half ratio support N 2 for Core to Bus ratio Supports enhanced Intel Virtualization Technology SFF processor only Intel Deeper Sleep low power state with P_LVL4 I O Support SFF processor only Advanced power management feature includes Enhanced Intel SpeedStep Technology SFF processor only intel 1 1 Introduction Terminology Term Definition Front Side Bus FSB A
68. ely initialize itself A System Management Interrupt SMI A System Management Interrupt SMI handler returns execution to either Normal state or the C1 AutoHALT Powerdown state See the Intel 64 and IA 32 Intel Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information The system can generate a STPCLK while the processor is in the C1 AutoHALT Powerdown state When the system deasserts the STPCLK interrupt the processor returns execution to the HALT state The processor in C1 AutoHALT powerdown state process only the bus snoops The processor enters a snoopable sub state not shown in Figure 2 to process the snoop and then return to the C1 AutoHALT Powerdown state Datasheet m e Low Power Features n tel 2 1 1 3 2 1 1 4 2 1 1 5 2 1 1 6 2 1 2 2 1 2 1 2 1 2 2 Datasheet C1 MWAIT Powerdown State C1 MWAIT is a low power state entered when the processor core executes the MWAIT instruction Processor behavior in the C1 MWAIT state is identical to the C1 AutoHALT state except that there is an additional event that can cause the processor core to return to the CO state the Monitor event See the Intel 64 and IA 32 Intel Architecture Software Developer s Manual Volume 2A 2B Instruction Set Reference for more information Core C2 State The core of the processor can enter the C2 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C2 instruction
69. er Other VSS AF16 Power Other VSS E19 Power Other VSS AF19 Power Other VSS E21 Power Other VSS AF21 Power Other VSS E24 Power Other VSS AF25 Power Other VSS F2 Power Other VSS B6 Power Other VSS F5 Power Other VSS B8 Power Other VSS F8 Power Other VSS Bii Power Other VSS F11 Power Other VSS B13 Power Other VSS F13 Power Other Datasheet 51 intel Package Mechanical Specifications and Pin Information Table 19 Pin Listing by Pin Name Table 19 Pin Listing by Pin Name Sheet 15 of 16 Sheet 16 of 16 Pin Name ae pa ig Direction Pin Name ae TEE Direction VSS F16 Power Other VSS R2 Power Other VSS F19 Power Other VSS R5 Power Other VSS F22 Power Other VSS R22 Power Other VSS F25 Power Other VSS R25 Power Other VSS G1 Power Other VSS T1 Power Other VSS G4 Power Other VSS T4 Power Other VSS G23 Power Other VSS T23 Power Other VSS G26 Power Other VSS T26 Power Other VSS H3 Power Other VSS U3 Power Other VSS H6 Power Other VSS U6 Power Other VSS H21 Power Other VSS U21 Power Other VSS H24 Power Other VSS U24 Power Other VSS J2 Power Other VSS V2 Power Other VSS J5 Power Other VSS V5 Power Other VSS J22 Power Other VSS V22 Power Other VSS J25 Power Other VSS V25 Power Other VSS K1 Power Other VSS Wil Power Other VSS K4 Power Other VSS W4 Power Other vss K23 Power Other VSS W23 P
70. er Other vcc F14 Power Other LOCK H4 TE A VCC F15 Power Other AspS vss F16 Power Other DEFER H5 Input vcc F17 Power Other Datasheet 57 intel Package Mechanical Specifications and Pin Information Table 20 Pin Listing by Pin Number Table 20 Pin Listing by Pin Number Sheet 12 of 17 Sheet 13 of 17 s Pin Signal x Pin Signal a Pin Name Number Buffer Type Direction Pin Name Number Buffer Type Direction VSS H6 Power Other VSS K23 Power Other VSS H21 Power Other D 8 K24 Source Synch a D 12 H22 Source Synch cin T 1714 K25 Source Synch UA Input D 15 nes Source Synch Output VSS K26 Power Other MS pen REQI4 L1 Source Synch DINV O H25 Source Synch Pee ju A 13 amp L2 Source Synch Input DSTBP O H26 Source Synch Output vss L3 Power Other 914 11 Source Synch I Put 514 L4 Source Synch IPPut y Output y Output Vm J2 Power Other A 4 L5 Source Synch aA Input REQ 3 B Source Synch Output VSS L6 Power Other A 3 4 14 Source Synch aurea VSS L21 Power Other Input vss J5 Power Other D 22 L22 Source Synch Output VCCP J6 Power Other 2014 23 Source Synch vise VCCP 121 Power Other utpu VSS 122 Power Other VSS L24 Power Other Input D 29 4 L25 Source Synch Input D 11 123 Source Synch Output Output Input
71. ermal Sensor and Out of Specification detection Intel Thermal Monitor 1 TM1 in addition to Intel Thermal Monitor 2 TM2 in case of unsuccessful TM2 transition Dual core thermal management synchronization Each core in the dual core processor implements an independent MSR for controlling Enhanced Intel SpeedStep Technology but both cores must operate at the same frequency and voltage The processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole If both cores request the same frequency and voltage then the processor will transition to the requested common frequency and voltage If the two cores have different frequency and voltage requests then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage Caution Enhanced Intel SpeedStep Technology transitions are multistep processes that require clocked control These transitions cannot occur when the processor is in the Sleep or Deep Sleep package low power states since processor clocks are not active in these states 2 3 Low Power FSB Features The processor incorporates FSB low power enhancements Dynamic On Die Termination disabling Low Vccp I O termination voltage The On Die Termination on the processor FSB buffers is disabled when the signals are driven low r
72. esign Considerations s usse 83 5 1 Monitoring Die Temperat re ecce Ern tpe niae ur a ebrei E rna k ca denies 84 5 1 1 Thermal Diode irte exa reden ren pa DERE KE E NOn E AE 85 5 1 2 Thermal Diode 5 iter Dex tant tex RE eb rex naP AE N tea va IM EAR EE 87 5 1 3 Intel Thermal nne nha nan hens nan sanas dn tan 88 5 1 4 Digital Thermal Sensor iier eripitur teenie sx xa aa vaa i na Rada 89 5 1 5 Out of Specification Detection eee nuces n nana nexa iretur hu Ra aia 90 5 1 0 PROCHOT Signal Pfizer aesti gaat bye ADR REA gels da Rc pi AR RPAR QR KR 90 Datasheet 1 Datasheet
73. ess than maximum specified Iccpgs VR OCP threshold should be high enough to support current levels described herein Measured at the bulk capacitors on the motherboard Based on simulations and averaged over the duration of any change in current Specified by design characterization at nominal Vcc Not 100 tested This is a power up peak current specification which is applicable when Vccp is high and Vcc core is low This is a steady state Icc current specification which is applicable when both Vccp and Vcc conE are high 1 MB L2 cache Datasheet 27 intel Electrical Specifications Table 7 DC Voltage and Current Specifications for the T1x00 Celeron Mobile Processors Symbol Parameter Min Typ Max Unit Notes Vcc Vcc of the Processor Core 0 95 1 15 1 30 V 1 2 Vcc BOOT Default Vcc Voltage for Initial Power Up 1 20 V 2 8 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VCCA PLL Supply Voltage 1 425 1 5 1 575 V Icc for processors I 36 A 5 CODES Recommended Design Targets Icc for processors A Processo Icc de i Frequency Die Variant T1600 1 66 GHz 1 MB 41 A T1700 1 83 GHz 1 MB 41 A i Ian An Icc Auto Halt amp Stop Grant 21 A 3 4 IsGNT Isi p Icc Sleep 20 5 A Ipsip Icc Deep Sleep 18 6 A i Vcc Power Supply Current Slew Rate at dIcc pr CPU Package Pin 699 A us 6 7 Icca Icc for VCCA Supply 130 mA I Icc for Vccp Supply before Vcc Stable 4 5 A 9 pun Ic
74. esulting in power savings The low I O termination voltage is on a dedicated voltage plane independent of the core voltage enabling low I O switching power at all times 16 Datasheet Low Power Features 2 4 Datasheet Processor Power Status Indicator PSI Signal The PSI signal is asserted when the processor is in a reduced power consumption state PSI can be used to improve light load efficiency of the voltage regulator resulting in platform power savings and extended battery life The algorithm that the processor uses for determining when to assert PSI is different from the algorithm used in previous processors 17 18 Low Power Features Datasheet Electrical Specifications 3 Electrical Specifications 3 1 Power and Ground Pins intel For clean on chip power distribution the processor has a large number of Vcc power and Vss ground inputs All power pins must be connected to Vcc power planes while all Vss pins must be connected to system ground planes Use of multiple power and ground planes is recommended to reduce I R drop The processor Vcc pins must be supplied the voltage determined by the VID Voltage ID pins 3 2 FSB Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous generation processors the processor core frequency is a multiple of the BCLK 1 0 frequency The processor uses a differe
75. ffset eens eens ee ee eee nene 88 Datasheet 1 Datasheet 1 Package Level Low Power States ccccccscaceceee eens eceeeeeeeesasesseesenenhaeechessenteseaeesentaneeener 11 2 Core LOW POWER States isses rh TERME RACEM RNLERE 12 3 4 MB and Fused 2 MB Micro FCPGA Processor Package Drawing Sheet 1 of 2 34 4 4 MB and Fused 2 MB Micro FCPGA Processor Package Drawing Sheet 2 of 2 35 5 2 MB Micro FCPGA Processor Package Drawing Sheet 1 of 2 36 6 2 Micro FCPGA Processor Package Drawing Sheet 2 of 2 37 7 SFF ULV DC Die Micro FCBGA Processor Package Drawing essen 38 Datasheet 1 Datasheet 1 7 WORM UMOO GY staal iue sa Ke 8 MEE iip a 9 2 Low Power F Ature eed he Rau kd ed ena Para Ead 11 2 1 Clock Control and Low Power States ee eases ememen nenne 11 2 1 1 Core Low Power States iecore eerte noii nnn pa PEE en a AR ERE A naaER A ARM EK 12 BNET 12 2 1 1 2 C1 AutoHALT Powerdown State
76. fications and Pin Information n t e Figure 4 4 MB and Fused 2 Micro FCPGA Processor Package Drawing Sheet 2 of 2 4X 7 00 Hi 7 00 Edge Keep Out Corner Keep Out Side View Zone 4X Zone 4X Top View 60 905 0 25 G0 406 ClA B 1 625 20 254 M C ee 13 97 6 985 1 5 Max Allowable Component Height Bottom View Datasheet 35 im 8 n t el Package Mechanical Specifications and Pin Information Figure 5 2 MB Micro FCPGA Processor Package Drawing Sheet 1 of 2 Bi E Hy i 5 5 I I es Ee 8 NI e Cy Bottom View Top View 478 Pins 5 5 p b Ti TTT bE Front View ML z p p h SYMBOL MILLIMETERS COMMENTS Side View By 34 95 35 05 B5 34 95 35 05 Die Underfill Cy 10 Package Substrate C5 10 3 F5 0 89 20 37 MAX i F3 1 823 2 063 N Fo d Gi 31 75 BASIC i 3 52 31 75 BASIC 0 65 MAX Hy 15 875
77. ge substrate should not be used as a mechanical reference or load bearing surface for the thermal or mechanical solution Please refer to the Santa Rosa Platform Mechanical Design Guide for more details For M step based processors refer to the 2 MB package drawings 33 t e Package Mechanical Specifications and Pin Information Figure 3 4 MB and Fused 2 MB Micro FCPGA Processor Package Drawing Sheet 1 of 2 00000 0 ji A i Gi A Bottom View Top View Pins hs n h p TTTTTTTTTTTYTTY Front View pn b b hh n f D SYMBOL COMMENTS Side View Bi 34 95 35 05 B5 34 95 35 05 Die Underfill Cy 10 5 Package Substrate C2 13 8 F gt 0 89 0 37 F3 1 903 2 163 3E F2 2 Gi 31 75 BASIC i 3 G 31 75 BASIC j 9 65 MAX 7 Hy 15 875 BASIC H5 15 875 BASIC 80 356 9 C A B 2 0340 08 Jy 1 27 BASIC 0 254 C 12 1 27 BASIC 20 65 MAX 0 255 0 355 P DIE 689 kPa Detail A w 6g Scale 20 Keying Pins A1 B1 34 Datasheet m e Package Mechanical Speci
78. h this information The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality Enhanced Intel SpeedStep Technology for specified units of this processor is available See the Processor Spec Finder at http processorfinder intel com or contact your Intel representative for more information Intel Virtualization Technology requires a computer system with an enabled Intel processor BIOS virtual machine monitor VMM and for some uses certain platform software enabled for it Functionality performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update Software applications may not be compatible with all operating systems Please check with your application vendor This device is protected by U S patent numbers 5 315 448 and 6 516 132 and other intellectual property rights The use of Macrovision s copy protection technology in the device must be authorized b
79. he maximum operating temperature then Intel Thermal Monitor 1 also activates to help cool down the processor The TCC may also be activated via on demand mode If Bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1 the TCC activates immediately independent of the processor temperature When using on demand mode to activate the TCC the duty cycle of the clock modulation is programmable via bits 3 1 of the same ACPI Intel Thermal Monitor control register In automatic mode the duty cycle is fixed at 50 on 50 off however in on demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On demand mode may be used at the same time automatic mode is enabled however if the system tries to enable the TCC via on demand mode at the same time automatic mode is enabled and a high temperature condition exists automatic mode takes precedence An external signal PROCHOT processor hot is asserted when the processor detects that its temperature is above the thermal trip point Bus snooping and interrupt latching are also active while the TCC is active Besides the thermal sensor and thermal control circuit the Intel Thermal Monitor also includes one ACPI register one performance counter register three MSR and one I O pin PROCHOT All are available to monitor and control the state of the Intel Thermal Monitor feature The Intel Thermal Monitor can be configured to generat
80. higher than the current frequency Vcc is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency If the target frequency is lower than the current frequency the PLL locks to the new frequency and the is changed through the VID pin mechanism Software transitions are accepted at any time If a previous transition is in progress the new transition is deferred until the previous transition completes 15 m n tel Low Power Features e The processor controls voltage ramp rates internally to ensure glitch free transitions e Low transition latency and large number of transitions possible per second Processor core including L2 cache is unavailable for up to 10 us during the frequency transition The bus protocol BNR mechanism is used to block snooping Improved Intel Thermal Monitor mode When the on die thermal sensor indicates that the die temperature is too high the processor can automatically perform a transition to a lower frequency and voltage specified in a software programmable MSR The processor waits for a fixed time period If the die temperature is down to acceptable levels an up transition to the previous frequency and voltage point occurs An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management e Enhanced thermal management features Digital Th
81. in Information Signal Name edm VCC AT24 VCC AT26 VCC AT28 VCC AT30 VCC AT32 VCC AT34 VCC AU33 VCC AV14 VCC AV16 VCC AV18 VCC AV20 VCC AV22 VCC AV24 VCC AV26 VCC AV28 VCC AV30 VCC AV32 VCC AY14 VCC AY16 VCC AY18 VCC AY20 VCC AY22 VCC AY24 VCC AY26 VCC AY28 VCC AY30 VCC AY32 VCC B16 VCC B18 VCC B20 VCC B22 VCC B24 VCC B26 VCC B28 VCC B30 VCC BB14 VCC BB16 VCC BB18 Datasheet Package Mechanical Specifications and Pin Information Signal Name Me VCC BB20 VCC BB22 VCC BB24 VCC BB26 VCC BB28 VCC BB30 VCC BB32 VCC BD14 VCC BD16 VCC BD18 VCC BD20 VCC BD22 VCC BD24 VCC BD26 VCC BD28 VCC BD30 VCC BD32 VCC D16 VCC D18 VCC D20 VCC D22 VCC D24 VCC D26 VCC D28 VCC D30 VCC F16 VCC F18 VCC F20 VCC F22 VCC F24 VCC F26 VCC F28 VCC F30 VCC F32 VCC G33 VCC H16 VCC H18 VCC H20 Datasheet Signal Name ees VCC H22 VCC H24 VCC H26 VCC H28 VCC H30 VCC H32 VCC J33 VCC K16 VCC K18 VCC K20 VCC K22 VCC K24 VCC K26 VCC K28 VCC K30 VCC K32 VCC L33 VCC M16 VCC M18 VCC M20 VCC M22 VCC M24 VCC M26 VCC M28 VCC M30 VCC M32 VC
82. kage Mechanical Specifications and Pin Information intel Table 19 Pin Listing by Pin Name Table 19 Pin Listing by Pin Name Sheet 13 of 16 Sheet 14 of 16 Pin Name MA Am e Direction Pin Name m AN ird Direction VSS AC14 Power Other VSS B16 Power Other VSS AC16 Power Other VSS B19 Power Other VSS AC19 Power Other VSS B21 Power Other VSS AC21 Power Other VSS B24 Power Other VSS AC24 Power Other VSS C2 Power Other VSS AD2 Power Other VSS C5 Power Other VSS AD5 Power Other VSS C8 Power Other VSS AD8 Power Other VSS C11 Power Other VSS AD11 Power Other VSS C14 Power Other VSS AD13 Power Other VSS C16 Power Other VSS AD16 Power Other VSS C19 Power Other VSS AD19 Power Other VSS C22 Power Other VSS AD22 Power Other VSS C25 Power Other VSS AD25 Power Other VSS D1 Power Other VSS AE1 Power Other VSS D4 Power Other VSS AE4 Power Other VSS D8 Power Other VSS AE8 Power Other VSS D11 Power Other VSS AE11 Power Other VSS D13 Power Other VSS AE14 Power Other VSS D16 Power Other VSS AE16 Power Other VSS D19 Power Other VSS AE19 Power Other VSS D23 Power Other VSS AE23 Power Other VSS D26 Power Other VSS AE26 Power Other VSS E3 Power Other VSS AF2 Power Other VSS E6 Power Other VSS AF6 Power Other VSS E8 Power Other VSS AF8 Power Other VSS E11 Power Other VSS AF11 Power Other VSS E14 Power Other VSS AF13 Power Other VSS E16 Pow
83. measurements a temperature offset value specified as Toffset is programmed in the processor MSR which contains thermal diode characterization data During manufacturing each processor thermal diode is evaluated for its behavior relative to the theoretical diode Using the equation above the temperature error created by the difference Nirim and the actual ideality of the particular processor is calculated 87 m n tel Thermal Specifications and Design Considerations Table 29 5 1 3 Note 88 If the ntrim value used to calculate the Toffset differs from the Nirim value used to in a temperature sensing device the Terror nf may not be accurate If desired the Toffset can be adjusted by calculating Nactuai and then recalculating the offset using the Nirim as defined in the temperature sensor manufacturer s datasheet The Ntrim used to calculate the Diode Correction Toffset are listed in Table 29 Thermal Diode nj jm and Diode Correction Toffset Symbol Parameter Value trim Diode Ideality used to calculate Toffset 1 01 Intel amp Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC Thermal Control Circuit when the processor silicon reaches its maximum operating temperature The temperature at which the Intel Thermal Monitor activates the TCC is not user configurable Bus traffic is snooped in the normal manner and interrupt requests are latched a
84. n 5 1 for more details 4 The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications 5 At Tj of 100 C 6 At Tj of 50 C 7 At Tj of 35 C 5 1 Monitoring Die Temperature The processor incorporates three methods of monitoring die temperature e Thermal Diode e Intel Thermal Monitor Digital Thermal Sensor 84 Datasheet m Thermal Specifications and Design Considerations n tel 5 1 1 Table 26 Datasheet Thermal Diode The processor incorporates an on die PNP transistor whose base emitter junction is used as a thermal diode with its collector shorted to ground The thermal diode can be read by an off die analog digital converter a thermal sensor located on the motherboard or a stand alone measurement kit The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a reliable indication that the maximum operating temperature of the processor has been reached When using the thermal diode a temperature offset value must be read from a processor MSR and applied See Section 5 1 2 for more details Please see Section 5 1 3 for thermal diode usage recommendation when the PROCHOT signal is not asserted The reading of the external thermal sensor on the motherboard connected to the processor thermal diode signals does not reflect the temperature of the hottest location on the die This is due t
85. n bi directional PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP With a properly designed and characterized thermal solution it is anticipated that bi directional PROCHOT would only be asserted for very short periods of time when running the most power intensive applications An under designed thermal solution that is not able to prevent excessive assertion of PROCHOT in the anticipated ambient environment may cause a noticeable performance loss 8 Datasheet 91 92 Thermal Specifications and Design Considerations Datasheet 1 Coordination of Core Level Low Power States at the Package 11 2 Voltage Identification Definition cece eee eee eee memes eee eee eae 19 3 BSEL 2 0 Encoding for BCLK Frequency 23 4 FSB Pim GEOUDS tse 24 5 Processor Absolute Maximum Ratings ee eee nena nemen eene 25 6 DC Voltage and Current Specifications for the T3x00 Celeron Processors ss 27 7 DC Voltage and Current Specifications for the T1x00
86. nd serviced during the time that the clocks are on while the TCC is active With a properly designed and characterized thermal solution it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be minor and hence not detectable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously The Intel Thermal Monitor controls the processor temperature by modulating starting and stopping the processor core clocks when the processor silicon reaches its maximum operating temperature The Intel Thermal Monitor uses two modes to activate the TCC automatic mode and on demand mode If both modes are activated automatic mode takes precedence There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal Monitor 2 These modes are selected by writing values to the MSRs of the processor After automatic mode is enabled the TCC activates only when the internal die temperature reaches the maximum allowed value for operation When Intel Thermal Moni
87. nous CMOS Input to TCK TCK TDI TMS TRST Open Drain Output Synchronous TDO P P to TCK FSB Clock Clock BCLK 1 0 COMP 3 0 DBR 2 GTLREF RSVD TEST2 TEST1 THERMDA Power Other THERMDC Vcc Vcca Vccp 5 Vss Vss SENSE NOTES 1 Refer to Chapter 4 for signal descriptions and termination requirements 2 In processor systems where there is no debug port implemented on the system board these signals are used to support a debug port interposer In systems with the debug port implemented on the system board these signals are no connects 24 BPM 2 1 and PRDY are AGTL output only signals PROCHOT signal type is open drain output and CMOS input On die termination differs from other AGTL signals Datasheet Electrical Specifications i n tel 3 8 3 9 Caution Caution Table 5 Datasheet CMOS Signals CMOS input signals are shown in Table 4 Legacy output FERR IERR and other non AGTL signals THERMTRIP and PROCHOT utilize Open Drain output buffers These signals do not have setup or hold time specifications in relation to BCLK 1 0 However all of the CMOS signals are required to be asserted for more than four BCLKs in order for the processor to recognize them See Section 3 10 for the DC specifications for the CMOS signal groups Maximum Ratings Table 5 specifies absolute maximum and minimum ratings If the processor stays within functional operation limits functionality and l
88. nput REQ 1 H2 Source Synch 1nput H y Output TRDY G2 Common Clock Input REQ 2 K2 Source Synch a TRST AB6 CMOS Input eee VCC A7 Power Other Input REQ 3 J3 Source Synch Output VCC A9 Power Other VCC A10 Power Other REQ 4 11 Source Synch I Put y Output VCC A12 Power Other RESET C1 Common Clock Input VCC A13 Power Other RS 0 F3 Common Clock Input VCC A15 Power Other RS 1 F4 Common Clock Input VCC A17 Power Other RS 2 G3 Common Clock Input VCC A18 Power Other RSVD B2 Reserved vcc A20 Power Other RSVD C3 Reserved VCC AA7 Power Other RSVD D2 Reserved VCC AA9 Power Other RSVD D3 Reserved VCC AA10 Power Other RSVD D22 Reserved VCC AA12 Power Other 48 Datasheet Package Mechanical Specifications and Pin Information intel Table 19 Pin Listing by Pin Name Table 19 Pin Listing by Pin Name Sheet 9 of 16 Sheet 10 of 16 Pin Name MA Am e Direction Pin Name LN a T Direction VCC AA13 Power Other VCC AE18 Power Other VCC AA15 Power Other VCC AE20 Power Other VCC AA17 Power Other VCC AF9 Power Other VCC AA18 Power Other VCC AF10 Power Other VCC AA20 Power Other VCC AF12 Power Other VCC AB7 Power Other VCC AF14 Power Other VCC AB9 Power Other VCC AF15 Power Other VCC AB10 Power Other VCC AF17 Power Other VCC AB12 Power Other VCC AF18 Power Other VCC AB14 Power Other VCC AF20 Power Other
89. ns and Pin Information Signal Name ae VSS A21 VSS A23 VSS A25 VSS A27 VSS A29 VSS A31 VSS A39 VSS A41 VSS AA3 VSS AA15 VSS AA17 VSS AA19 VSS AA21 VSS AA23 VSS AA25 VSS AA27 VSS AA29 VSS AA31 VSS AA39 VSS AB6 VSS AB8 VSS AB34 VSS AB42 VSS AC3 VSS AC15 VSS AC17 VSS AC19 VSS AC21 VSS AC23 VSS AC25 VSS AC27 VSS AC29 VSS AC31 VSS AC39 VSS AD6 VSS AD8 VSS AD10 VSS AD12 Datasheet Package Mechanical Specifications and Pin Information Signal Name Pie VSS AD34 VSS AD36 VSS AD38 VSS AD42 VSS AE3 VSS AE15 VSS AE17 VSS AE19 VSS AE21 VSS AE23 VSS AE25 VSS AE27 VSS AE29 VSS AE31 VSS AE39 VSS AF6 VSS AF8 VSS AF34 VSS AF42 VSS AG3 VSS AG15 VSS AG17 VSS AG19 VSS AG21 VSS AG23 VSS AG25 VSS AG27 VSS AG29 VSS AG31 VSS AG39 VSS AH6 VSS AH8 VSS AH10 VSS AH12 VSS AH34 VSS AH36 VSS AH38 VSS AH42 Datasheet Signal Name un VSS AJ3 VSS AJ15 VSS AJ17 VSS AJ19 VSS AJ21 VSS AJ23 VSS AJ25 VSS AJ27 VSS AJ29 VSS AJ31 VSS AJ39 VSS AK6 VSS AK8 VSS AK34 VSS AK42 VSS AL3 VSS AL15 VSS AL17 VSS AL19 VSS AL21 VSS AL23 VSS AL25 VSS
90. ntial clocking implementation 3 3 Voltage Identification The processor uses seven voltage identification pins VID 6 0 to support automatic selection of power supply voltages The VID pins for processor are CMOS outputs driven by the processor VID circuitry Table 2 specifies the voltage level corresponding to the state of VID 6 0 A 1 refers to a high voltage level and a 0 refers to low voltage level Table 2 Voltage Identification Definition Sheet 1 of 4 VID6 VID5 VID4 VID3 VID2 VID1 VIDO Vcc V 0 0 0 0 0 0 0 1 5000 0 0 0 0 0 0 1 1 4875 0 0 0 0 0 1 0 1 4750 0 0 0 0 0 1 1 1 4625 0 0 0 0 1 0 0 1 4500 0 0 0 0 1 0 1 1 4375 0 0 0 0 1 1 0 1 4250 0 0 0 0 1 1 1 1 4125 0 0 0 1 0 0 0 1 4000 0 0 0 1 0 0 1 1 3875 0 0 0 1 0 1 0 1 3750 0 0 0 1 0 1 1 1 3625 0 0 0 1 1 0 0 1 3500 0 0 0 1 1 0 1 1 3375 0 0 0 1 1 1 0 1 3250 0 0 0 1 1 1 1 1 3125 0 0 1 0 0 0 0 1 3000 0 0 1 0 0 0 1 1 2875 0 0 1 0 0 1 0 1 2750 0 0 1 0 0 1 1 1 2625 0 0 1 0 1 0 0 1 2500 0 0 1 0 1 0 1 1 2375 Datasheet 19 intel Table 2 Voltage Identification Definition Sheet 2 of 4 Electrical Specifications 20 VID6 VID5 VID4 VID3 VID2 VID1 VIDO Vcc V 0 0 1 0 1 1 0 1 2250 0 0 1 0 1
91. o inaccuracies in the external thermal sensor on die temperature gradients between the location of the thermal diode and the hottest location on the die and time based variations in the die temperature measurement Time based variations can occur when the sampling rate of the thermal diode by the thermal sensor is slower than the rate at which the T temperature can change Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may be characterized using the Intel Thermal Monitor s Automatic mode activation of the thermal control circuit This temperature offset must be taken into account when using the processor thermal diode to implement power management events This offset is different than the diode Toffset value programmed into the processor Model Specific Register MSR Table 26 to Table 29 provide the diode interface and specifications The diode model parameters apply to the traditional thermal sensors that use the diode equation to determine the processor temperature Transistor model parameters have been added to support thermal sensors that use the transistor equation method The Transistor model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits Contact your external sensor supplier for recommendations The thermal diode is separate from the Intel Thermal Monitor s thermal sensor and cannot be used to predict the behavior
92. ode thermal sensor Ry can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation Terror Rr N71 Ifwmin nk q In N where Terror sensor temperature error N sensor current ratio k Boltzmann Constant q electronic charge Datasheet Thermal Specifications and Design Considerations n tel Table 28 5 1 2 Datasheet Thermal Diode Parameters Using Transistor Model Symbol Parameter Min Typ Max Unit Notes Igw Forward Bias Current 5 200 pA 1 2 Ig Emitter Current 5 200 pA 1 no Transistor Ideality 0 997 1 001 1 005 3 4 5 Beta 0 3 0 760 3 4 Ry Series Resistance 2 79 4 52 6 24 Q 3 6 NOTES 1 Intel does not support or recommend operation of the thermal diode under reverse bias 2 Same as Ipy in Table 27 3 Characterized across a temperature range of 50 100 C 4 Not 100 tested Specified by design characterization 5 The ideality factor nQ represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current Ic Ig e 9Vgg okT 1 where Is saturation current q electronic charge Vgg voltage across the transistor base emitter junction same nodes as VD k B
93. oltzmann Constant and T absolute temperature Kelvin 6 The series resistance Rz provided in the Diode Model Table Table 27 can be used for more accurate readings as needed When calculating a temperature based on the thermal diode measurements a number of parameters must be either measured or assumed Most devices measure the diode ideality and assume a series resistance and ideality trim value although are capable of also measuring the series resistance Calculating the temperature is then accomplished using the equations listed under Table 27 In most sensing devices an expected value for the diode ideality is designed in to the temperature calculation equation If the designer of the temperature sensing device assumes a perfect diode the ideality value also called ntrim is 1 000 Given that most diodes are not perfect the designers usually select an Nirim value that more closely matches the behavior of the diodes in the processor If the processor diode ideality deviates from that of the Nirim each calculated temperature offsets by a fixed amount This temperature offset can be calculated with the equation Terror nf T measured 1 Nactual Mtrim where Terror nf is the offset in degrees C Tmeasurea iS in Kelvin Nactual is the measured ideality of the diode and Nirim is the diode ideality assumed by the temperature sensing device Thermal Diode Offset In order to improve the accuracy of the diode based temperature
94. ong term reliability can be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected At conditions exceeding absolute maximum and minimum ratings neither functionality nor long term reliability can be expected Precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Processor storage TSTORAGE temperature 40 85 C 2 3 4 Any processor supply voltage Vcc with respect to Vas o y AGTL buffer DC input VinAGTL voltage with respect to Vss gu 133 CMOS buffer DC input Vinasynch_CMOS voltage with respect to Vss ot Sem M NOTES 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits does not affect the long term reliability of the device For functional operation please refer to the processor case temperature specifications 3 This rating applies to the processor and does not include any tray or packaging 4 Failure to adhere to this specification can affect the long term reliability of the proce
95. or protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor stops all execution when the junction temperature exceeds approximately 125 C This is signalled to the system by the THERMTRIP Thermal Trip pin TMS Input TMS Test Mode Select is a JTAG specification support signal used by debug tools TRDY Input TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both FSB agents TRST Input TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset Voc Input Processor core power supply Vss Input Processor core ground node Veca Input Vcca provides isolated power for the internal processor core PLL s Voce Input Processor I O Power Supply Voc_SENSE Output Vcc sENsE together with Vss sense are voltage feedback signals to Intel MVP 6 that control the 2 1 mQ loadline at the processor die It should be used to sense voltage near the silicon with little noise VID 6 0 Output VID 6 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that
96. ower Other VSS K26 Power Other VSS W26 Power Other VSS L3 Power Other VSS Y3 Power Other VSS L6 Power Other VSS Y6 Power Other VSS L21 Power Other VSS Y21 Power Other VSS L24 Power Other VSS Y24 Power Other VSS M2 Power Other VSSSENSE AE7 Power Other Output VSS M5 Power Other VSS M22 Power Other i vss M25 Power Other Table 20 Number VSS Ni Power Other g vss N4 Power Other Pin Name Buren Tne Direction vss N23 Power Other VSS A2 Power Other vss N26 Power Other SMI A3 CMOS Input eS iid Power otner VSS A4 Power Other vss PP power other FERR A5 Open Drain Output VSS P21 Power Other A20M A6 CMOS Input VSS P24 Power Other VCC A7 Power Other 52 Datasheet Package Mechanical Specifications and Pin Information intel Table 20 Pin Listing by Pin Number Table 20 Pin Listing by Pin Number Sheet 2 of 17 Sheet 3 of 17 Pin Name m Bolts vns Direction Pin Name Um aves Direction VSS A8 Power Other VSS AA16 Power Other VCC A9 Power Other VCC AA17 Power Other VCC A10 Power Other VCC AA18 Power Other VSS A11 Power Other VSS AA19 Power Other VCC A12 Power Other VCC AA20 Power Other Nee a Power other D 50 AA21 Source Synch alee VSS A14 Power Other VCC A15 Power Other VSS AA22 Power Other VSS A16 Powe
97. pe Description LINT 1 0 Input LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Intel Pentium processor Both signals are asynchronous Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration LOCK Input Output LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of both FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the FSB it waits until it observes LOCK deasserted This enables symmetric agents to retain ownership of the FSB throughout the bus locked operation and ensure the atomicity of lock PRDY Output Probe Ready signal used by debug tools to determine processor debug readiness PREQ Input Probe Request signal used by debug tools to request debug operation of the processor PROCHOT Input Out
98. put As an output PROCHOT Processor Hot goes active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system activates the TCC if enabled The TCC remains active until the system deasserts PROCHOT By default PROCHOT is configured as an output The processor must be enabled via the BIOS for PROCHOT to be configured as bidirectional This signal may require voltage translation on the motherboard PSI Output Processor Power Status Indicator signal This signal is asserted when the processor is in both in the Normal state HFM to LFM and in lower power states Deep Sleep and Deeper Sleep PWRGOOD Input PWRGOOD Power Good is a processor input The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal remains low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the proces
99. r Other D 45 AA23 Source Synch cutee vcc A17 Power Other Input VCC A18 Power Other Eisele AA24 Source Synch Output VSS A19 Power Other VSS AA25 Power Other EE Ap Power Other DSTBP 2 AA26 Source Synch Butt BCLK 1 A21 Bus Clock Input BCLK 0 A22 Bus Clock Input a ABI Power Other VSS A23 Power Other A 34 AB2 Source Synch THRMDA A24 Power Other TDO AB3 Open Drain Output VSS A25 Power Other VSS ABA Power Other TESTS R26 ist TMS ABS CMOS Input COMP 2 AA1 Power Other TRST AB6 CMOS Input VSS AA2 Power Other vee oer orner Input VSS AB8 Power Other A 35 AA3 Source Synch Output VCC AB9 Power Other A 33 4 4 Source Synch Mee ABIO Power Other VSS AB11 Power Other ves ae FOWSI RIREF VCC AB12 Power Other Im AAG eee Input VSS AB13 Power Other Ve dd Power Otner VCC ABi4 Power Other WES db Power amet VCC AB15 Power Other Wes An Power other VSS AB16 Power Other vcc AA10 Power Other VCC AB17 Power Other VSS AA11 Power Other VCC AB18 Power Other VCC AA12 Power Other vss AB19 Power Other VCC AA13 Power Other VCC AB20 Power Other VSS AA14 Power Other Input 5 Power Other DIssqr AB21 Source Synch Output Datasheet 53 intel Package Mechanical Specifications and Pin Information Table 20 Pin Listing by Pin N
100. responds to the Intel Thermal Monitor 1 Intel Thermal Monitor 2 trigger point When the DTS indicates maximum processor core temperature has been reached the Intel Thermal Monitor 1 or 2 hardware thermal control mechanism will activate The DTS and Intel Thermal Monitor 1 Intel Thermal Monitor 2 temperature may not correspond to the thermal diode reading because the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS Additionally the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power mechanical and thermal attach and software application The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs These thresholds have the capability of generating interrupts via the core s local APIC Refer to the Intel 64 and IA 32 Architectures Software Developer s Manual for specific register and programming details Out of Specification Detection Overheat detection is performed by monitoring the processor temperature and temperature gradient This feature is intended for graceful shut down before the THERMTRIP is activated If the processor s Intel Thermal Monitor 1 or 2 are triggered and the temperature remains high an Out Of Spec status and sticky bit are la
101. rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe REQ 4 0 A 16 3 A 35 17 ADSTB 0 ADSTB 1 The differential pair BCLK Bus Clock determines the FSB frequency All FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcgoss BNR Input Output BNR Block Next Request is used to assert a bus stall by any bus agent who is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BPM 2 1 BPM 3 0 Output Input Output BPM 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all processor FSB agents This includes debug or performance monitoring tools BPRI Input BPRI Bus Priority Request is used to arbitrate for ownership of the FSB It must connect the appropriate pins of both FSB agents Observing BPRI active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its reque
102. rocessor is in the Sleep state the SLP pin must be deasserted if another asynchronous FSB event needs to occur Datasheet m Low Power Features n tel 2 1 2 5 2 1 2 6 2 2 Datasheet Deep Sleep State Deep Sleep state is a very low power state the processor can enter while maintaining context Deep Sleep state is entered by asserting the DPSLP pin while in the Sleep state BCLK may be stopped during the Deep Sleep state for additional platform level power savings BCLK stop restart timings on appropriate chipset based platforms with the CK505 clock chip are as follows e Deep Sleep entry the system clock chip may stop tristate BCLK within 2 BCLKs of DPSLP assertion It is permissible to leave BCLK running during Deep Sleep e Deep Sleep exit the system clock chip must drive BCLK to differential DC levels within 2 3 ns of DPSLP deassertion and start toggling BCLK within 10 BCLK periods To re enter the Sleep state the DPSLP pin must be deasserted BCLK can be re started after DPSLP deassertion as described above A period of 15 microseconds to allow for PLL stabilization must occur before the processor can be considered to be in the Sleep state Once in the Sleep state the SLP pin must be deasserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transitions of signals are allowed on the FSB while the
103. rted to insert idle clocks This signal must connect the appropriate pins of both FSB agents DSTBN 3 0 Input Output Data strobe used to latch in D 63 0 Associated Strobe Signals D 15 0 DINV 0 D 31 16 DINV 1 D 47 32 DINV 2 D 63 48 DINV 3 DSTBN 0 DSTBN 1 DSTBN 2 DSTBN 3 DSTBP 3 0 Input Output Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV O D 31 16 DINV 1 D 47 32 DINV 2 D 63 48 DINV 3 DSTBP 0 DSTBP 1 DSTBP 2 DSTBP 3 Datasheet 77 m n tel Package Mechanical Specifications and Pin Information Table 22 Signal Description Sheet 4 of 7 Name Type Description FERR Floating point Error PBEz Pending Break Event is a multiplexed signal and its meaning is qualified with STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state When FERRZ PBEZ is asserted indica
104. sor The processor also contains an on die Digital Thermal Sensor DTS that can be read via an MSR no I O interface Each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor MSRs The DTS is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor The DTS is only valid while the processor is in the normal operating state the Normal package level low power state 89 m n tel Thermal Specifications and Design Considerations 5 1 5 5 1 6 90 Unlike traditional thermal devices the DTS will output a temperature relative to the maximum supported operating temperature of the processor T max It is the responsibility of software to convert the relative temperature to an absolute temperature The temperature returned by the DTS will always be at or below T max Catastrophic temperature conditions are detectable via an Out Of Spec status bit This bit is also part of the DTS MSR When this bit is set the processor is operating out of specification and immediate shutdown of the system should occur The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set The DTS relative temperature readout cor
105. sor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation REQ 4 0 Input Output REQ 4 0 Request Command must connect the appropriate pins of both FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to 4 Datasheet 79 intel Table 22 Package Mechanical Specifications and Pin Information Signal Description Sheet 6 of 7 Name Type Description RESET Input Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least two milliseconds after Vcc and BCLK have reached their proper specifications On observing active RESET both FSB agents deasserts their outputs within two clocks All processor straps must be valid within the specified setup time before RESET is deasserted There is a 55 Q nominal on die pull up resistor on this signal RS 2 0 Input RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both FSB agents RSVD Reserved No Connect These pins are RESERVED and must be left unconnected on the board However it is re
106. ssets Specification Update PDF specupdate 316973 pdf See http Intel 64 and IA 32 Architectures Software Developer s Manual www intel com design pentium4 manuals index new htm Intel 64 and IA 32 Architectures Software Developer s Manuals Documentation Change See http developer intel com design processor specupdt 252046 htm Volume 1 Basic Architecture 253665 Volume 2A Instruction Set Reference A M 253666 Volume 2B Instruction Set Reference N Z 253667 Volume 3A System Programming Guide 253668 Volume 3B System Programming Guide 253669 em 10 Introduction Datasheet im e Low Power Features n tel 2 2 1 Table 1 Figure 1 Datasheet Low Power Features Clock Control and Low Power States The processor supports the C1 AutoHALT C1 MWAIT C2 C3 and some support the C4 core low power states along with their corresponding package level states for power management See Chapter 3 to see if C4 is supported These package states include Normal Stop Grant Stop Grant Snoop Sleep and Deep Sleep The processor s central power management logic enters a package low power state by initiating a P_LVLx P LVL2 P LVL3 P LVL4 I O read to the G MCH Figure 1 shows the package level low power states and Figure 2 shows the core low power states Refer to Table 1 for a mapping of core low power states to package low power states The processor implements two sof
107. ssor 25 i n t el Electrical Specifications 3 10 26 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Table 4 for the pin signal definitions and signal pin assignments Table 7 through Table 10 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature clock frequency and input voltages The Highest Frequency Mode HFM and Super Low Frequency Mode SuperLFM refer to the highest and lowest core operating frequencies supported on the processor Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states Vcc goor is the default voltage driven by the voltage regulator at power up in order to set the VID values Unless specified otherwise all specifications for the processor are at Tjunction 100 C Care should be taken to read all notes associated with each parameter Datasheet Electrical Specifications intel Table 6 DC Voltage and Current Specifications for the T3x00 Celeron Processors Symbol Parameter Min Typ Max Unit Notes Vcc Vcc of the Processor Core 0 8 1 25 V 1 2 Vcc BooT Default Vcc Voltage for Initial Power Up 1 20 V 2 8 Vccp AGTL Termination Voltage 1 00 1 05 1 10 V VccA PLL Supply Voltage 1 425 1 5 1 575 V Icc for processors Ic
108. sts are completed then releases the bus by deasserting BPRI BRO Input Output BRO is used by the processor to request the bus The arbitration is done between processor Symmetric Agent and G MCH High Priority Agent Datasheet 75 m n tel Package Mechanical Specifications and Pin Information Table 22 Signal Description Sheet 2 of 7 Name Type Description BSEL 2 0 Bus Select are used to select the processor input clock frequency Table 3 defines the possible combinations of the signals and the frequency BSEL 2 0 Output associated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency COMP 3 0 must be terminated on the system board using precision 19 6 COMP 3 0 Analog tolerance resistors D 63 0 Data are the data signals These signals provide a 64 bit data path between the FSB agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and are driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals corresponds to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Quad Pumped Signal Groups Input Data
109. tched in the status MSR register and generates thermal interrupt PROCHOT Signal Pin An external signal PROCHOT processor hot is asserted when the processor die temperature has reached its maximum operating temperature If Intel Thermal Monitor 1 or 2 is enabled then the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT Refer to the Inte 64 and IA 32 Architectures Software Developer s Manual for specific register and programming details The processor implements a bi directional PROCHOT capability to allow system designs to protect various components from overheating situations The PROCHOT signal is bi directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the TCC The ability to activate the TCC via PROCHOT can provide a means for thermal protection of system components Only a single PROCHOT pin exists at a package level of the processor When either core s thermal sensor trips the PROCHOT signal will be driven by the processor package If only Intel Thermal Monitor 1 is enabled PROCHOT will be asserted and only the core that is above TCC temperature trip point will have its core clocks modulated If Intel Thermal Monitor 2 is enabled then regardless of which core s are above TCC temperature trip point both cores will enter th
110. te The only difference is that if both processor cores are in C4 the central power management logic will request that the entire processor enter the Deeper Sleep package low power state see Section 2 1 2 6 Package Low Power States Package level low power states are applicable to the processor Normal State This is the normal operating state for the processor The processor enters the Normal state when the core is in the CO C1 AutoHALT or C1 MWAIT state Stop Grant State When the STPCLK pin is asserted the core of the processor enters the Stop Grant state within 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle When the STPCLK pin is deasserted the core returns to the previous core low power state 13 58 8 n tel Low Power Features 2 1 2 3 2 1 2 4 14 Since the AGTL signal pins receive power from the FSB these pins should not be driven allowing the level to return to Vccp for minimum power drawn by the termination resistors in this state In addition all other input pins on the FSB should be driven to the inactive state RESET causes the processor to immediately initialize itself but the processor stays in Stop Grant state When RESET is asserted by the system the STPCLK SLP and DPSLP pins must be deasserted more than 480 us prior to RESET deassertion AC Specification T45 When re entering the Stop Grant state from the Sleep state STPCLK shoul
111. tection An external thermal sensor should also be used to protect the processor and the system against excessive temperatures Even with the activation of THERMTRIP which halts all processor internal clocks and activity leakage current can be high enough that the processor cannot be protected in all conditions without power removal to the processor If the external thermal sensor detects a catastrophic processor temperature of 125 C maximum or if the THERMTRIP signal is asserted the Vcc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor THERMTRIP functionality is not guaranteed if the PWRGOOD signal is not asserted Reserved and Unused Pins All RESERVED RSVD pins must remain unconnected Connection of these pins to Vcc Vss Or to any other signal including each other may result in component malfunction or incompatibility with future processors See Section 4 2 for a pin listing of the processor and the location of all RSVD pins For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active low AGTL inputs may be left as no connects if AGTL termination is provided on the processor silicon Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnected The TEST1 and TEST2 pins must have a stuffing option of separate pull down resis
112. these limits may result in permanent damage to the processor and potentially other components in the system Table 23 Power Specifications for the 3x00 Celeron Processors Processor Thermal Design gt Symbol Number Core Frequency amp Voltage Power Unit Notes TDP T1600 1 66 GHz 35 Ww 1 4 5 6 9 TDP T1700 1 83 GHz 35 Ww 1 4 5 6 9 Symbol Parameter Min Typ Max Unit P AH Auto Halt Stop Grant Power at HFM Vcc 139 W 2 5 7 Psi p Sleep Power at Vcc 13 1 Ww 2 5 7 PpsLP Deep Sleep Power at Vcc 5 5 Ww 2 5 8 Tj Junction Temperature 0 105 C 3 4 Table 24 Power Specifications for the Intel Celeron Dual Core Processor Standard Voltage Processor Thermal Design i Symbol Number Core Frequency amp Voltage Power Unit Notes TDP T1600 1 66 GHz 35 Ww 1 4 5 6 9 TDP T1700 1 83 GHz 35 Ww 1 4 5 6 9 Symbol Parameter Min Typ Max Unit P Ar Auto Halt Stop Grant Power at HFM Vcc 13 5 w 2 5 7 Psi p Sleep Power at Vcc 12 9 Ww 2 5 7 Ppsip Deep Sleep Power at Vcc 7 7 Ww 2 5 8 Tj Junction Temperature 0 100 C 3 4 NOTES 1 The TDP specification should be used to design the processor thermal solution The TDP is not the maximum theoretical power the processor can generate 2 Not 100 tested These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated Datasheet 83 m n tel Thermal Specifications and Design
113. ting a break event it remains asserted until STPCLK is deasserted Assertion of PREQ when STPCLK is active also causes an FERR break event For additional information on the pending break event functionality including identification of support of the feature and enable disable information refer to Volumes 3A and 3B of the Inte 64 and IA 32 Architectures Software Developer s Manual and the Intel Processor Identification and CPUID Instruction application note FERR PBE Output GTLREF determines the signal reference level for AGTL input pins GTLREF should GTLREF Input be set at 2 3 Vccp GTLREF is used by the AGTL receivers to determine if a signal is a logical O or logical 1 HITZ Input HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation Output results Either FSB agent may assert both HIT and HITM together to indicate Input that it requires a snoop stall which can be continued by reasserting HIT and Output HITM together IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the IERR Output FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor keeps IERR asserted until the assertion of RESET BINIT or INIT IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error
114. tor 1 is enabled and a high temperature situation exists the clocks modulates by alternately turning the clocks off and on at a 50 duty cycle Cycle times are processor speed dependent and decreases linearly as processor core frequencies increase Once the temperature has returned to a non critical level modulation ceases and TCC goes inactive A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the trip point The duty cycle is factory configured and cannot be modified Also automatic mode does not require any additional hardware software drivers or interrupt handling routines Processor performance decreases by the same amount as the duty cycle when the TCC is active Intel Thermal Monitor 1 and Intel Thermal Monitor 2 features are collectively referred to as Adaptive Thermal Monitoring features Intel recommends Intel Thermal Monitor 1 and 2 be enabled on the processors Datasheet m Thermal Specifications and Design Considerations i n tel 5 1 4 Datasheet Intel Thermal Monitor 1 and 2 can co exist within the processor If both Intel Thermal Monitor 1 and 2 bits are enabled in the auto throttle MSR Intel Thermal Monitor 2 takes precedence over Intel Thermal Monitor 1 However if Force Intel Thermal Monitor 1 over Intel Thermal Monitor 2 is enabled in MSRs via BIOS and Intel Thermal Monitor 2 is not sufficient to cool the processor below t
115. tors to Vss For the purpose of testability route the TEST3 and TESTS signals through a ground referenced Zo 55 0 trace that ends in a via that is near a GND via and is accessible through an oscilloscope connection Datasheet Electrical Specifications i n tel 3 6 Table 3 3 7 Datasheet FSB Frequency Select Signals BSEL 2 0 The BSEL 2 0 signals are used to select the frequency of the processor input clock BCLK 1 0 These signals should be connected to the clock chip and the appropriate chipset on the platform The BSEL encoding for BCLK 1 0 is shown in Table 3 BSEL 2 0 Encoding for BCLK Frequency BSEL 2 BSEL 1 BSEL 0 BCLK Frequency L L L RESERVED L L H 133 MHz L H H RESERVED L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED FSB Signal Groups The FSB signals have been combined into groups by buffer type in the following sections AGTL input signals have differential input buffers which use GTLREF as a reference level In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving With the implementation of a source synchronous data bus two sets of timing parameters need to be specified One set is for common clock signals which are dependent upon the
116. tput DINV 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent inverts the data bus signals if more than half the bits within the covered group would change level in the next cycle DINV 3 0 Assignment To Data Bus Data Bus Bus Signal Signals DINV 3 DINV 2 DINV 1 DINV 0 D 63 48 4 D 47 32 D 31 16 D 15 0 DPRSTP Input DPRSTP when asserted on the platform causes the processor to transition from the Deep Sleep State to the Deeper Sleep state In order to return to the Deep Sleep State DPRSTP must be deasserted DPRSTP is driven by the Intel 82801HBM ICH8M I O Controller Hub based chipset DPSLP Input DPSLP when asserted on the platform causes the processor to transition from the Sleep State to the Deep Sleep state In order to return to the Sleep State DPSLP must be deasserted DPSLP is driven by the Intel 82801HBM ICH8M chipset DPWR Input Output DPWR is a control signal used by the chipset to reduce power on the processor data bus input buffers The processor drives this pin during dynamic FSB frequency switching DRDY Input Output DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasse
117. tware interfaces for requesting low power states MWAIT instruction extensions with sub state hints and LVLx reads to the ACPI P BLK register block mapped in the processor s I O address space The P_LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads on the processor FSB The monitor address does not need to be setup before using the P_LVLx I O read interface The sub state hints used for each P LVLx read can be configured through the IA32 MISC ENABLES Model Specific Register MSR If the processor encounters a chipset break event while STPCLK is asserted it asserts the PBE output signal Assertion of PBE when STPCLK is asserted indicates to system logic that the processor should return to the Normal state Coordination of Core Level Low Power States at the Package Level Core States Package States CO Normal c1 Normal C2 Stop Grant C3 Deep Sleep C4 Deeper Sleep NOTE AutoHALT or MWAIT C1 Package Level Low Power States M STPCLK asserted SLP asserted N DPSLP asserted DPRSTP asserted l Stop Deep Deeper Nermal Grat Sleep Sleep Sleep LN AN RAI A A RE Pi p ma STPCLK deasserted b d SLP deasserted N _ DPSLP deasserted _ DPRSTP deasserted _ P TERES 4 et ee Snoop Snoop serviced occurs ire N Stop Grant Snoop
118. umber Table 20 Pin Listing by Pin Number Sheet 4 of 17 Sheet 5 of 17 s Pin Signal z Pin Signal Pin Name Number Buffer Type Direction Pin Name Number Buffer Type Direction Input Input D 51 AB22 Source Synch Output D 53 AC26 Source Synch Output vss AB23 Power Other BPM 2 AD1 Output Input D 33 AB24 Source Synch Output VSS AD2 Power Other Input Common D 47 AB25 Source Synch Output BPM 1 AD3 Clock Output VSS AB26 Power Other Common Input Common BPM 0 AD4 Clock Output PREQ ACI Clock Input VSS ADS Power Other PRDY AC2 ae Output VID 0 AD6 CMOS Output vcc AD7 Power Other Mes nes Powerotner VSS AD8 Power Other Common Input BPM 3 AC4 Clock Output VCC AD9 Power Other TCK ACS CMOS Input VCC AD10 Power Other vss ACG Power Other VSS AD11 Power Other VCC ACT Power Other VCC AD12 Power Other vss AC8 Power Other VSS AD13 Power Other VCC AC9 Power Other VCC AD14 Power Other VCC AC10 Power Other vcc AD15 Power Other vss ACLL Power Other VSS AD16 Power Other VCC AC12 Power Other VCC AD17 Power Other VCC ACI3 Power Other vcc AD18 Power Other vss AC14 Power Other VSS AD19 Power Other VCC AC15 Power Other D 54 AD20 Source Synch n VSS AC16 Power Other Input VCC AC17 Power Other D 53 AD21 Source Synch Output VCC AC18 Power Other VSS AD22 Power Other VSS ACLA es ie D 61 AD23 Source Synch DINV 3 AC20 Source Synch TRY P 4914 AD24 Source Synch VSS AC21 Power Other upu Input VS
119. ut D 24 4 P25 Source Synch 1nPut Output Input D 3 G22 Source Synch Output D 25 P23 Source Synch 1nPut Output Input D 4 Fes Source Synch Output D 26 4 P22 Source Synch 1nPut Output Input D 5 Source Synch o eut D 27 T24 Source Synch 1nPut Output Input D 6 pen Source Synch Output D 28 R24 Source Synch 1nPut Output Input D 7 E23 Source Synch Output D 29 L25 Source Synch Input Output Input D 8 Kaa Source Synch Output D 30 T25 Source Synch 1nPut Output Input D 9 G24 source Synch Output D 31 N25 Source Synch Input Output Input J24 Source Synch Output D 32 Y22 Source Synch I Put Output Input D 11 es Source Synch Output D 33 4 AB24 Source Synch Output Input D 12 nee Sauce Synch Output D 34 V24 Source Synch Input Output Input D 13 F26 Source Synch Output D 35 v26 Source Synch Input Output Input D 14 Source Synch Output D 36 4 23 Source Synch 1nPut Output 46 Datasheet Package Mechanical Specifications and Pin Information intel Table 19 Pin Listing by Pin Name Table 19 Pin Listing by Pin Name Sheet 5 of 16 Sheet 6 of 16 Pin Signal Buffer P Pin Signal Buffer z x Pin Name Number Type Direction Pin Name Number Type Direction Input Input D 37
120. vec vec vec vec vec vec vec vec vec vec 17 vss vss vss vss vss vss vss vss vss vss vss 18 vec vec vec vec vec 19 vss vss vss vss vss vss vss vss vss vss vss 20 vec vec vec vec vec vec vec vec vec vec vec 21 vss vss vss vss vss vss vss vss vss vss vss 22 vec vec vec vec vec vec vec vec vec vec vec 41 intel Table 16 42 Package Mechanical Specifications and Pin Information SFF Processor Top View Upper Right Side REQ O RS 1 Datasheet Package Mechanical Specifications and Pin Information Table 17 Datasheet SFF Processor Top View Lower Left Side BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC 23 vss vss vss vss vss vss vss vss vss vss vss 24 vec vec vec vec vec vec vec vec vec vec 25 vss vss vss vss vss vss vss vss vss vss vss 26 vec vec vec vec vec vec vec vec vec vec vec 27 vss vss vss vss vss vss vss vss vss vss vss 28 vec vec vec vec vec vec vec vec vec vec 29 vss vss vss vss vss vss vss vss vss vss vss 30 vec vec vec vec vec vec vec vec vec vec 31 vss vss vss vss vss vss vss vss vss vss vss 32 vec vec vec vec vec vec vec vec vec vec 33 vss vss vss
121. y Macrovision and is intended for home and other limited pay per view uses only unless otherwise authorized in writing by Macrovision Reverse engineering or disassembly is prohibited 64 bit computing on Intel architecture requires a computer system with a processor chipset BIOS operating system device drivers and applications enabled for Intel 64 architecture Processors will not operate including 32 bit operation without an Intel 64 architecture enabled BIOS Performance will vary depending on your hardware and software configurations Consult with your system vendor for more information Intel Pentium Intel Core Intel Core 2 Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2008 Intel Corporation All rights reserved 2 Datasheet Contents 1 Introduction eem epe rar n De Sede Ste a 7 Del we rminology didi ny cise Bal 8 1 2 ieu EE 9 2 Low Power FeatUr s eicere nnn tha nd Rma ERR X REY DUAE TRE ER adn 11 2 1 Clock Control and Low Power 5 8 65 11 2 1 1 Core Low Power IA a Esa Y eR n D Ree aiaa ia 12 2 1 2 Package Low Power States ceci esse nha a n cess nu ERR A

Intel Celeron T1700

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