Super Talent Technology 512MB DDR SC Kit
Contents
1. CQ A pgs A DO30 DQ51 DII Doss Do4 boas D Q S3 rr i ST N DM3 DQS12 v DN DOSI6 r DQ DQ37 A DUIE A DI A Dai 1 D51 4 I DUEL a DQ AE Vp SPL SPD VREF Di D15 DO D15 Vag Voom i Sirap see Note 4 Nater SAD SAl 5A2 l DQ to l 0 wimg is shown as recommended but may be changed 2 DOVDOSDM CKE S relationships must be mamtamed as shown 3 DO DOS DM DOS resistors 22 ohms 5 a 4 Voom sap commections CEQCEO 4 SDRAM a oe ae ro OU 1 W m RAS SDRAMs DO DIS CELCEL 6 SDRAMs Taran man a nog CEITES 6 SDRAM eee ae oe Ps LL 5 Al Th F s j T f TRAP a 4 zg DO F DOQ BAJ BAI j BAD EA1 SDRAMs Do D13 A0 Al a ADAL SDEAM D0 D13 CRE1 _ CEE SDRAMs DE D15 RAS CAS W CAS SDRAMs DO D13 TE TE SDRAMs Di D7 Wire per Clock Loading B oa aon a Tee iaram 5 BAx Ax RAS CAS WE resistors 3 ohms WE oe WE SDRAMs D0 D15 7 52 Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 5 512MB Unbuffered DOSO DMODOS9 DI M DQ SUPER TALENT THE POWER OF MEMORY DIMM 0 aa 4 TI N DQ y pgs A DQ A DS SOLOS DQSE M nT wt DOS 1 DM1 DOS10 DOSI DMG3 DOQS12 pq D25 D26 D027 D9 T30 D DOSE DMSDQS172. Cho A CEL A CH2 wWi CHS wi CH4 CHi n CHE A CH7 4 BA0 EBEAIL p AQ A13 M TAS N i CEEO _ Pr 1 jr a i gt 1 Ay BA0 BAL SDRAMs DO DS AQ Al3 SDRAMs DO D8 FAS SDRAMs Do D8 CAS SDRAMs Do D8 CEE SDRAMs Dd D3 WE SDRAM D0 Dg VP D Tr Ip Vor Ving VREF Vag Viti BAST DM4 DOS13 DOSS DM5 DQS14 DOS DM DQS15 DOST _ DM7 DQS16 v _ gt DO Ds Dd DE Ti Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 6 7 3 512MB 64mx72 Module populated as 1 rank of 64x8 SDRAMs DOI A DQI3 W DOH A D33 A DE A DIIT A DIE N DII 4 Ti Tas DQ M DQ w DQE A DQ A DH A posi AM D6 N DoT AM i DDR SDRAM DHE 10 DGH ae DQ wy DGI A DG32 A pqs D Q za A DG35 A mT D0 DE 3 Strap see Note KILED CKILICE CKICK2 Wire per Clock Loading Table Winng Diagrams DO te 10 winme is shown as recommended but may be changed 2 DODOS DM CEE S relationships must be maintained as shown DQ BOS DMTQS resistors 22 ohms 5 4 Voor strap commections for memory device Von Vong STRAP OUT OPEN Vip Vong STRAP IN Vee Von Ving B x Ax RAS CAS WE resistors
3. Data out high impedance time fromCK CK tHZ 0 65 0 65 07 07 ns T Mode register set cycle time MRD 10 R SS DQ amp DM setup ime 1oD05 mws o4 los ns DQ amp DM hold timeto DQS DH 04 Ss Control amp Address input pulse width PW 22 22 a DQ amp DM input pulsewidth DPW 175 15 a Exit self refresh to non Read command XSNR 735 5 aBa Pex self refresh to Rend command f sro 20 a o oons f C a jotta a T a Data hold skew factor os S SS f as DQS write postamble time tWRST 04 06 04 06 K Active to Read with Auto precharge command tRAP 15 Autoprecharge write recovery Precharged time tWR tCK m tWR tCK S tRP tCK tRP tCK Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 9 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM 12 0 Physical Dimensions 64Mbx8 based component 64x64 amp 64x72 Modules populated as 1 Rank FRONT Note All dimensions are typical unless otherwise state millimeters inches Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 10 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM 32Mbx8 based component 64x64 amp 64x72 Modules populated as 2 Ranks FRONT 133 35 5 250 131 35 5
4. a a ee Output high current Half strengh driver Vour Vrr 0 45V 9 0 AC Operating Conditions Vin AC _ Input High Logic 1 Voltage DQ DQS and DM signals Vre 0 31 Syo o Vu AC _ Input Low Logic 0 Voltage DQ DQS and DM signals Vane 0 31 V f Vin AC _ Input voltage level CK and CK inputs Vt 6 V Vix AC _ Input crossing point voltage CK and CK inputs 0 5 Vppo 0 2 0 5 Vpn9 0 2 V 10 Input Output Capacitance Vpp 2 9V Vppg 2 9V Ta 25 C f 1MHZ Symbol Parameter Condition DS2PASIZN Unit Input capacitance AO A12 BAO BAI1 RAS CAS WE 49 57 51 60 pF Cm3 Cra Cms Input capacitance DMO DM7 DM8 for ECC 6 7 6 7 p Couri Data amp DQS input output capacitance DQO DQ63 6 7 6 7 p Cour Data input output capacitance CBO CB o d 1 6 7 PF Symbol Parameter Condition D32PB12025 Unit Input capacitance A0 A12 BAO BA1 RAS CAS WE 65 81 69 87 p Cm2 C3 Cina Cour Data input output capacitance CBO CB7 p Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 8 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM 11 0 AC Timing Parameters amp Specifications B3 Parameter Symbol R e 0 COSIO 5 Unit Note Mn Mx O Mi Ma Row cycletime RC 55 O A T T ae T OOE EE E A E T E Row activetime Ras
5. gt CEE SDRAM D9 D17 neran maintained az shown senal PD q DM asistos 2 ohus 5 Tat ieee RAS SDRAM DO DIT i DQ DOS DMTDQS re istors 22 ohms 5 Voom Sap comections CAS jit TAS SDRAM D0 D17 for memory device Vip Vp Dg CKE __ CEE SDRAM D0 D8 STRAP OUT OFEN Vip Vong WE N WE SDRAMs DO D17 SAD SAl SA STRAP IN Vz Vip Vong 5 BAx Ax RAS CAS WE resistors 3 ohms 5 a Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 7 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM 8 0 DC Operating Conditions Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 C Parameter Min Max Unit Note Veer WO Reference voltage 49 Vg 0 51 Vpng V Vin DC _ Input logic high voltage Vn 0 15 Vooot0 3 V fo o o Vi DC Inputlogic low voltage 8 SVs OV Vix DC _ Input voltage level CK and CK inputs __ 03 Vt 3 V Vin DC _ Input differential voltage CK and CK inputs T0386 Vomot06 V VRatio V I Matching Pullup to Pulldown Current Ration 07n 14 Input leake current ooo o 2 Imn Input leake current loz Output leakage current Output high current Normal strengh driver Vour Vrr 0 84V Output high current Normal strengh driver Vour Vrr 0 84V Output high current Half strengh driver Vour Vrr 0 45V
6. 171 128 93 5 076 2 50 mal oh 0 098 ao 88 pe P m SIDE BACK 4 00 1 157 MAX Front 1 27 0 10 0 050 0 004 Note All dimensions are typical unless otherwise state millimeters inches Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 11 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM Revision History Revision 1 0 Mar 2006 Initial Release Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 12 DDR SDRAM
7. 3 CL 2 5 BBM Speed CL2 5 166MHz 166MHz Speed CL3 200Mhz CL tRCD tRP 2 5 3 3 4 0 Absolute Maximum DC Rating Symbol Voltage on any pin relative to Vss 0 5 3 6 Voltage on Von amp Vddq supply relative to Vss Short circuit current Pd Power dissipation 1 5 of component Storage Temperature 55 150 Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 2 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM 5 0 DIMM Pin Configurations Front side Back side Front DDR SDRAM aie Ra i ia e of Dei 1 93 VSS 2 94 DQ4 ma 3 95 DQ5 VDDQ 4 96 VDDQ CS0 5 97 DMO CS1 6 98 DQ6 DM5 7 99 DQ7 VSS 8 100 VSS DQ46 101 NC DQ47 102 NC CS3 103 NC VDDQ 104 VDDQ DQ52 105 DQ12 DQ53 106 DQ13 A13 107 DM1 VDD 108 VDD DM6 109 DQ14 DQ54 110 DQ15 DQ55 111 CKE1 VDDQ 112 VDDQ NC 113 BA2 DQ60 114 DQ20 KEY DQ61 115 Al2 VSS VSS 116 VSS DQ36 DM7 117 DQ21 DQ37 DQ62 118 All VDD DQ63 119 DM2 DM4 VDDQ 120 VDD DQ38 SAO 121 DQ22 DQ39 SA1 122 A8 VSS SA2 123 DQ23 DQ44 VDDSPD Note These pins are not use in this module 6 0 Dimm Pin Description Pin Name Fun
8. 4 OK 2 IK nss RAS to CAS delay o J RoD S ts f Row prechargetime RP i J B a Row active to Row active delay RRD 10 J 2 a Write recovery time R 5 J s a Last data in to Read command WTR 2 f 1 _ fx C lead 73 pp Il Clock cycle time tK 6 2 6 R nm 30 0 oo ee ee eee eee Clock high level width tH 045 055 045 055 CK SE ae Clocklowlevelwidh ee ee ee ee ae ae ee 2 DQS out access time fromCK CK tDQSCK 0 55 0 55 06 06 ns Output data access time fromCK CK tAC 0 65 0 65 07 07 ns Data strobe edge o output data edge wosa wa eoa a Read Preamble TC tRPRE 09 11 09 11 K Read Postamble RPST 04 06 04 06 K CK to valid DQS in tDQSS 072 128 075 125 CK DQS insetuptime _ _ _ WRES 0 0 a a DQS inholdtime WPR 025 0235 CK DQS falling edge to CK rising setup time tDSS_ 02 02 x DQS falling edge from CK rising setup time DSH 02 02 x DQS in high level width tDQSH 035 035 x DQS in low level width DQsL 035 035 CK Address and Control input setup time fas us o6 os ms Aee and Control input hold time fas alt 06 078s Address and Control input setup time slow as 07 its Address and Control input hold time slow H 07 is
9. 5 1 ohm EF 570 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM 7 4 512MB 64x72 Module populated as 2 rank of 32x8 SDRAMs A it Ce 3513 Baiba DOSO DMODQS9 j a FF sf 5 DQs DY ao ae poo M DOL A D A D A D l 4 Fao DAS M k e e e ri i i ri DQSS m DM5DQSI4 DQ 4 AS D1 Fa Do Ar DHI Ae DoH A D5 MO DHS A DHT A DOSS m DM6 amp DQS15 DOSI w DMIDQS10 Ta LF LA de La be cS 20000 0a 0 DM D8 A DQ A DQs0 W Daal A DJI A D53 M DQ A D5 K 7 i if D DMFDQOS516 r r sal OF I li I I I I I rm ml m ay rm i ml mm a rm i ml D m I Tml Pag I BEAR DDBE boa bo bo bo F Li ba me O LS a DOS3 Ar DM3 DOS12 w QH DRS i T935 DOT N D26 DOIE i DQ27 DQ An 19 DOs A i DOS A Po 30 DOSZ yi allt fog Pp DOSS pp Clock Wiring a EOE Te ma re MS DOQS17 m oe Input DaD CBO big KORO 6SDRAMs CEI Ves CKLCE 6 SDRAMs cB CKLTE 6 SDRAMs CBS va a cB4 Wire per Clock Loading CHS Strap see Mote 4 Table Winns Diagrams CHE Notes CH7 i 1 DQ to L O wmng is shown as recommended BA BAI i BAO BAI SDRAM D0 D17 but may be changed AD A13 me AO A13 SDRAM DO D17 2 DODOS DM CKE S relationships must be CEE
10. CKLCE CKICRI Wire per Clock Loading Notez Table Winne Diagrams yo E a m BAQ BA BA BAL SDRAM DO D7 l ae sipam 4 i ee ee ee DQDOS DM CKE S relationships must be RAS i e FAS SDRAMs DO D7 mamtamed a shown Vinp SPD DQ DOS DMDOS resistors 22 ohms 3 CAS i m CAS SDRAMs DO D7 SPD 1 Vv ee 4 Vopr tap commections CEEQ CEE 5DRAM D0 D7 Vopn Vpng Gi DI for memory device Vi pg WE v WE SDRAM D0 D7 Vers mo DT E OUT OPEN Von Vppg mo TRAP lgs Von Vong BAx Ax RAS CAS WE resistors 5 1 ohms a a 7 bat Lal Voom Sirap see Note 4 Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 4 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM 7 2 512MB 8x64 Module populated as 2 rank of 32x8 SDRAMs D iE S O f Ar S 7 DQSO PNA DOSI DMODQS9 Iga A CII ahs TIH A TIS A DOIS iT DII TO bos N DJS SATO 7 DOSS _w DM5DQSI4 poo A DQ A DQ A DJ A DCH DOS AS DOS A DQ A Li ooo oo oo a I li I li DOS i DMLDQS10 DJ A Il yi DHI wi DH AN DIH a DGH A DRE A DO A Dolo A DOI DQ Ae DOL A DQ Ar DQ A a cc es DM2 DQS11 DM6DQSI5S W C1 ca taco co SSS SSeS eS LA Je iai ee ff
11. SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM DDR SDRAM Unbuffered MODULE 184pin Unbuffered Module based on 32Mbx8 amp 64Mbx8 64 72 bit Non ECC ECC Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 1 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM 1 0 Feature Vpop 2 5V 0 2V Vppa 2 5V 0 2V for DDR333 Vpp 2 6V 0 1V Vppoa 2 6V 0 2V for DDR400 Double data rate architecture two data transfers per clock cycle Bidirectional data strobe DQ x8 Differential clock inputs CK and CK DLL aligns DQ and DQS transition with CK transition Programmable Read latency DDR333 2 5 Clock DDR400 3 Clock Programmable Burst length 2 4 8 Programmable Burst type sequential amp interleave Edge aligned data output center aligned data input Auto amp Self refresh 7 8us refresh interval 8K 64ms refresh Serial presence detect with EEPROM PCB Height 1 250 mil amp single 512MB double 512MB sided SSTL_2 Interface 66pin TSOP II package 2 0 Ordering Information Component composition Height TE ME x64 Non ECC o O N D32PB12C25 512MB 64x64 32mx8 TSOP II x72 ECC DDR SDRAM D32PA512N 512MB 64x64 64Mx8 TSOP II licen mentees een ES 0 CO po 512M 64x72 32mx8 TSOP 2 Pp 51MB 64x72 64Mx8 TSOP 1 3 0 Operating Frequencies Speed CL2 133MHz CC DR400 CL 3 B3 DDR33
12. ction Pin Name Function AO A12 Address input multiplex DMO DM7 Power Supply BAO BAI Pane teeters vo o 2 5V for DDR333 2 6V FOR DDR400 Power Supply for DQS DQ0 DQ63 Data input output eee 2 5V for DDR333 2 6V for DDR400 DQS0 DQS7 Data Strobe input output Ground sis CKO CKO CK2 CK2 Power Supply for reference Clock input VREF Products and Specifications discussed herein are subject to change without notice 2006 Super Talent Tech Corporation 3 SUPER TALENT THE POWER OF MEMORY 512MB Unbuffered DIMM DDR SDRAM 7 0 Functional Block Diagram 7 1 512MB 64x64 Module populated as 1 rank of 64x8 SDRAMs 50 DOSO w DMO DQS9 DOSA DMA DQS13 D32 Ar D33 A DOH Ah D33 A DE A DoI A DII A DII w DIJ A I DIH TO DS WV DIT M DS WV pqas W nq Ww Dq38 Ww a DOQS5 DMADQS14 DOSI w DM 1 TQS i DO An Dga A DUA wW DAI A DE td Do fir I DQ WLIO 2 DOW Wo DQ M me hiipi DU M nos A DQ A DQ A DOI aw boa ite DOS Dy A TAQS11 i DMG DOQS15 5 DE A TJ 17 AM DHS Ay Dos A ps iy Dis M D SI A DO A DoI i DQs3 A DOH DOSS A DOS DMT DQS16 v Dose At DS i i 18 a 9 A T r Teel i Dea THS Clock Wiring SDA CKOCKO
Download Pdf Manuals
Related Search