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Fujitsu Intel Xeon 5110

1. Symbol Parameter Min Typ Max Unit Notes VID B2 step VID range 1 0000 1 5000 VID GO step VID range 0 8500 1 5000 Vcc Vcc for processor core See Table 2 14 and Figure 2 4 V 2 3 4 6 10 Vec poor Default VCC Voltage for 1 10 V 2 initial power up Vvip STEP VID step size during a 12 5 mV i transition VVID SHIFT Total allowable DC load line 450 mV 11 shift from VID steps Vr FSB termination voltage DC 1 14 1 20 1 26 V 9 14 AC specification VccPLL PLL supply voltage DC AC 1 455 1 500 1 605 V specification lec Icc for Dual Core Intel 45 A 4 5 6 10 Xeon Processor LV 5148 5138 5128 core with multiple VID lec Icc for Dual Core Intel 75 A 4 5 6 10 Xeon Processor 5100 Series core with multiple VID lec Icc for Dual Core Intel 90 A 4 5 6 10 Xeon Processor 5160 core with multe VID ICC RESET lec reset for Dual Core 45 A 3 i Intel Xeon Processor LV 5148 5138 5128 core with multiple VID lec RESET lec RESET for Dual Core 75 A 7 i Intel Xeon Processor 5100 Series core with multiple VID lec RESET lec RESET for Dual Core 90 A 7 H Intel Xeon Processor 5160 core with multiple VID Ir FSB termination current 4 60 A 16 Dual Core Intel Xeon Processor 5100 Series Datasheet 29 intel Electrical Specifications Table 2 13 Voltage and Current Specifications Sheet 2 of 2 30
2. Power W TcasE MAX C P_PROFILE_MIN 26 50 0 30 51 6 35 53 5 40 55 4 45 57 3 50 59 3 55 61 2 60 63 1 65 65 0 76 Dual Core Intel Xeon Processor 5100 Series Datasheet Thermal Specifications Table 6 3 Figure 6 2 intel Dual Core I ntel amp Xeon Processor LV 5138 Thermal Specifications Thermal Design Minimum Maximum Processor Power TCASE TCASE Notes W C C 5138 35 5 See Figure 6 2 1 2 3 4 5 Table 6 4 Table Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and Icc combination wherein Vcc exceeds Vcc max at specified Il cc Please refer to the loadline specifications in Section 2 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VIDs found in Table 2 3 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements Dual Core Intel Xeon Processor LV 5138 Nominal amp Short Ter
3. Symbol Parameter Min Typ Max Unit Notes lh Icc for Vz supply before Vec 4 5 A 16 stable Icc for Vr supply after Vcc 4 6 stable lcc TDC Thermal Design Current 35 A 6 15 u TDC Dual Core Intel Xeon Processor LV 5148 5138 5128 lcc TDC Thermal Design Current 60 A 6 15 TDC Dual Core Inte Xeon Processor 5100 Series lcc Toc Thermal Design Current 70 A 6 15 T TDC Dual Core Intel Xeon Processor 5160 lcc vrr out DC current that may be 580 mA 17 Ta drawn from Vr our per land cc_GTLREF lcc for 200 HA 8 GTLREF_DATA and GTLREF_ADD lec VCCPLL lec for PLL supply 130 mA 13 Itcc Icc for Dual Core Intel 45 A Xeon Processor LV 5148 5138 5128 during active thermal control circuit TCC Itec Icc for Dual Core Intel 65 A Xeon Processor 5100 Series during active thermal control circuit TCC Itcc I cc for Dual Core Intel 90 A Xeon Processor 5160 during active thermal control circuit TCC Notes 1 Unless otherwise noted all specifications in this table apply to all processors and are based on estimates and simulations not empirical data These specifications will be updated with characterized data from silicon measurements at a later date 2 These voltages are targets only A variable voltage source should exist on systems in the event that a different voltage is required See Section 2 5 for more information 3 The voltage specification requirements are measured across the VCC DIE SENSE a
4. ES o j ES lt zje a FERE Ni ME s H 8 mr g m 2 EA ls TI a A o ls E z S E H EG a o 5 tn oc m Ira 2 d IL Ed aui 5 f E g E Elo 3 z gt K PE e 2 m s e e e gt co Dual Core Intel Xeon Processor 5100 Series Datasheet 103 e n tel Boxed Processor Specifications Figure 8 8 Volumetric Height Keep Ins a e 1 oO lt 06 po NOT SCALE DRAWING SHEET 5 OF 6 s n R EE E 2 als 3 3 an ie Tal ka EE 3 E lt L gt K 2 wo D en T E i Lu x E T eo id s E L r zs sz g s5 E iu z 2 pe re gt Y Y oo 104 Dual Core Intel Xeon Processor 5100 Series Datasheet ntel 4 Pin Fan Cable Connector For Active CEK Heat Sink L y f j dO 133HS 9NIAVIQ 31Y08 LON OO 1 7 30Y9S HS INI NOI123fFONd 319NV QUIHI 3NO Nid 200 T xxx 52 0 x SOF w VOTE 7532NV83101 4313N1 1I NI JAY SNOLSNGMIO POGING PIA MSY H TA JONVOROD9 NI S3ONVETTOL ONY SNOISNIMIG 134dH31N1 031412345 ISIAAILO 5531Nf 6118 25056 Y VN YLNYS dil09 61185 X08 O d Q8 3931100 NOISSIN 002 621
5. Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 9 of 20 Sheet 10 of 20 uc Pin Name Direction Ne Pin Name ako s Direction AM26 VCC Power Other B11 VSS Power Other AM27 VSS Power Other B12 D134 Source Sync Input Output AM28 VSS Power Other B13 RESERVED AM29 VCC Power Other B14 VSS Power Other AM3 VID2 Power Other Output B15 D53 Source Sync Input Output AM30 VCC Power Other B16 D55 Source Sync Input Output AM4 VSS Power Other B17 VSS Power Other AM5 VID6 Power Other Output B18 D57 Source Sync Input Output AM6 RESERVED B19 D60 Source Sync Input Output AM7 VSS Power Other B2 DBSY Common Clk Input Output AM8 VCC Power Other B20 VSS Power Other AM9 VCC Power Other B21 D59 Source Sync Input Output AN1 VSS Power Other B22 D63 Source Sync Input Output AN10 VSS Power Other B23 RESERVED AN11 VCC Power Other B24 VSS Power Other AN12 VCC Power Other B25 VIT Power Other AN13 VSS Power Other B26 VIT Power Other AN14 VCC Power Other B27 VIT Power Other AN15 VCC Power Other B28 VIT Power Other AN16 VSS Power Other B29 VIT Power Other AN17 VSS Power Other B3 RSO Common Clk Input AN18 VCC Power Other B30 VIT Power Oth
6. ee ere kk aed 22 2 5 Loadline Selection Truth Table for LL ID 1 0 1 0 eect kk 23 2 6 Market Segment Selection Truth Table for MS ID 1 0 seem 23 2 7 FSB Signal Gro ps reri ert e rer dere oleae DR ERR naa a ban bana bbe BI Pb EPIS FR dead Lanes 24 2 8 AGTL Signal Description Table s ssssssssrssrissrrurirt ttt me ememememe kk ka inns 25 2 9 Non AGTL Signal Description Table ssssssssssessememmemenmememene nnn 25 2 10 Signal Reference Voltages M hk QMkkKK kk kk memes sese eem kaka k kk kake 25 2 11 PECI DC Electrical Limits smoren ireren sennae eee nns 26 2 12 Processor Absolute Maximum Ratings sssssssssse menm memes 28 2 13 Voltage and Current Specifications sssssssssssssesses enemies 29 2 14 VCC Static and Transient Tolerance MhL hkhWwlllkk kk kk kk kk kk kk kk eene mene 32 2 15 AGTL Signal Group DC Specifications eee meme 34 2 16 CMOS Signal Group and TAP Signal Group DC Specifications kWhWkh kh kk 34 2 17 Open Drain Signal Group DC Specifications sssessssssseme HH 35 2 18 VCC Overshoot Specifications cece ennemi emen 35 3 1 Package Loading Specifications ccc kya k 41 3 2 Package Handling GuidelineS cc ene emen 42 3 3 Processor MaterialS 4 5 cided tree ue eene haa n h lor e ni d ban t baka n Pod d n P kac Ys 43 4 1 Land Listing by Land Name sssssssssesee eme Hmm kak
7. and must connect the appropriate pins of all processor FSB agents DRDY 1 0 DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of all processor FSB agents Dual Core Intel Xeon Processor 5100 Series Datasheet 67 intel Table 5 1 Signal Definitions Signal Definitions Sheet 4 of 7 Name DSTBN 3 0 Type 1 0 Description Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBNO D 31 16 DBI1 DSTBN1 D 47 32 DBI2 DSTBN2 DSTBN3 D 63 48 DBI3 Notes DSTBP 3 0 1 0 Data strobe used to latch in D 63 0 Signals Associated Strobes D 15 0 DBIO DSTBPO D 31 16 DBI1 DSTBP1 D 47 32 DBI2 DSTBP2 D 63 48 DBI3 DSTBP3 FERR PBE FERR PBE floating point error pending break event is a multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point error and will be asserted when the processor detects an unmasked floating point error When STPCLK is not asserted FERR PBE is similar to the ERROR signal on the Intel 387 coprocessor and is included for compatibility with systems usi
8. 2 These signals may be driven simultaneously by multiple agents Wired OR Table 2 9 outlines the signals which include on die termination R77 Table 2 9 outlines non AGTL signals including open drain signals Table 2 10 provides signal reference voltages AGTL Signal Description Table AGTL signals with Ryr AGTL signals with no Ry A 35 3 ADS ADSTB 1 0 AP 1 0 BINIT BPM 5 0 RESET BNR BPRI D 63 0 DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 HIT HITM LOCK MCERR REQ 4 0 RS 2 0 RSP Non AGTL Signal Description Table Signals with Ry Signals with no RTT FORCEPR PROCHOT A20M BCLK 1 0 BSEL 2 0 FERR PBE GTLREF ADD GTLREF_DATA IERR IGNNE INIT LINTO INTR LINT1 NMI LL_ID 1 0 MS ID 1 0 PECI PWRGOOD SKTOCC SMI STPCLK TCK TDI TDO TESTHI 11 0 THERMTRIP TMS TRDY TRST VCC DIE SENSE VCC DIE SENSE2 VID 6 1 VID SELECT VSS DIE SENSE VSS DIE SENSE2 VIT SEL Note 1 Signals that have RTT in the package with 50 Q pullup to Vy Signal Reference Voltages GTLREF CMOS A 35 3 ADS ADSTB 1 0 AP 1 0 BINIT A20M LINTO INTR LINT1 NMI IGNNEZ INIT BNR BPM 5 0 BPRI BR 1 0 D 63 0 PWRGOOD SMI STPCLK TCK TDI TMS TRST DBI 3 0 DBSY DEFER DP 3 0 DRDY DSTBN 3 0 DSTBP 3 0 FORCEPR HIT HITM LOCK MCERR RESET REQ 4 0
9. 8 Dual Core Intel Xeon Processor 5100 Series Datasheet 89 90 Thermal Specifications Dual Core Intel Xeon Processor 5100 Series Datasheet Features 7 7 1 Table 7 1 7 2 intel Features Power On Configuration Options Several configuration options can be configured by hardware The Dual Core Intel9 Xeon Processor 5100 Series samples its hardware configuration at reset on the active to inactive transition of RESET Z For specifics on these options please refer to Table 7 1 The sampled information configures the processor for subsequent operation These configuration options cannot be changed except by another reset All resets reconfigure the processor for reset purposes the processor does not distinguish between a warm reset PWRGOOD signal remains asserted and a power on reset Power On Configuration Option Lands Configuration Option Land Name Notes Output tri state SMI 1 2 Execute BIST Built In Self Test A3 1 2 Disable MCERR observation AQ 1 2 Disable BINIT observation A10 1 2 Symmetric agent arbitration ID BR 1 0 1 2 Notes 1 Asserting this signal during RESET will select the corresponding option 2 Address lands not identified in this table as configuration options should not be asserted during RESET Clock Control and Low Power States The Dual Core Intel Xeon Processor 5100 Series supports the Extended HALT state also referred to as
10. Dual Core Intel Xeon Processor 5100 Series Datasheet 81 Figure 6 5 Case Temperature TcAsg Measurement Location 6 2 6 2 1 6 2 1 1 82 Measure from the edge of the top surface of processor IHS 14 75mm 7 Measure Tcase geometric center of the top surface of the IHS 14 75mm i i i i ZERER RES BERN 37 5 mm x 37 5mm Substrate Note Figure is not to scale and is for reference only Processor Thermal Features Thermal Monitor Features Dual Core Intel Xeon Processor 5100 Series provides two thermal monitor features Thermal Monitor TM1 and Enhanced Thermal Monitor TM2 The Thermal Monitor and Enhanced Thermal Monitor must both be enabled in BIOS for the processor to be operating within specifications When both are enabled TM2 will be activated first and TM1 will be added if TM2 is not effective Thermal Monitor TM1 The Thermal Monitor TM1 feature helps control the processor temperature by activating the Thermal Control Circuit TCC when the processor silicon reaches its maximum operating temperature The TCC reduces processor power consumption as needed by modulating starting and stopping the internal processor core clocks The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible Bus traffic is snooped in the normal manner and interrupt requests are latched and serviced during the time that the c
11. ERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor FSB This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET This signal does not have on die termination IGNNE Z IGNNEZ Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a noncontrol floating point instruction if a previous floating point instruction caused an error GNNE has no effect when the NE bit in control register 0 CRO is set GNNE is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction 68 Dual Core Intel Xeon Processor 5100 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 5 of 7 intel Name INIT Type l Description INIT Initialization when asserted resets integer registers inside all processors without affecting their internal caches or floating point registers Each processor then begins execution at the power on Reset vector configured during power
12. Processor 5100 Series 2 Individual processors operate only at or below the frequency marked on the package 3 For valid processor core frequencies refer to the Dual Core Intel Xeon Processor 5100 Series Specification Update 4 The lowest bus ratio supported by the Dual Core Intel Xeon Processor 5100 Seriesis 1 6 2 4 1 Front Side Bus Frequency Select Signals BSEL 2 0 Upon power up the FSB frequency is set to the maximum supported by the individual processor BSEL 2 0 are CMOS outputs which must be pulled up to Vy and are used to select the FSB frequency Please refer to Table 2 16 for DC specifications Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The frequency is determined by the processor s chipset and clock synthesizer All FSB agents must operate at the same core and FSB frequency See the appropriate platform design guidelines for further details Table 2 2 BSEL 2 0 Frequency Table Sheet 1 of 2 BSEL2 BSEL1 BSELO Bus Clock Frequency 0 0 0 266 666 MHz 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 333 333 MHz Dual Core Intel Xeon Processor 5100 Series Datasheet 19 e n tel Electrical Specifications Table 2 2 2 4 2 2 5 20 BSEL 2 0 Frequency Table Sheet 2 of 2 BSEL2 BSEL1 BSELO Bus Clock Frequency 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved PLL Power Supply An on die PLL fil
13. n tel Thermal Specifications Figure 6 8 Temperature Data Format Comparison Thermal Diode vs PECI Digital 6 3 1 2 6 3 2 6 3 2 1 6 3 2 2 88 Thermal Sensor TCC Activation TControl Temperature setting I Max Tdiode 80C PECI 10C Fan Speed RPM Tdiode 70C PECI 20C Temperature Conceptual Fan Control Diagram on Desktop Platforms not intended to depict actual implementation Processor Thermal Data Sample Rate and Filtering The DTS provides an improved capability to monitor device hot spots which inherently leads to more varying temperature readings over short time intervals The DTS sample interval range can be modified and a data filtering algorithm can be activated to help moderate this The DTS sample interval range is 82 us default to 20 ms max This value can be set in BIOS To reduce the sample rate requirements on PECI and improve thermal data stability vs time the processor DTS also implements an averaging algorithm that filters the incoming data This is an alpha beta filter with coefficients of 0 5 and is expressed mathematically as Current filtered temp Previous filtered temp 2 new sensor temp 2 This filtering algorithm is fixed and cannot be changed It is on by default and can be turned off in BIOS Host controllers should utilize the min max sample times to determine the appropriate sample rate based on the controller s fan control algorith
14. If more than half the data bits within within a 16 bit group would have been asserted electronically low the bus agent may invert the data bus signals for that particular sub phase for that 16 bit group DBI 3 0 Assignment to Data Bus Bus Signal Data Bus Signals DBIO D 15 0 D 31 16 D 47 32 D 63 48 DBI1 DBI2 DBI3 DBR DBR is used only in systems where no debug port connector is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port connector is implemented in the system DBR is a no connect on the Dual Core Intel Xeon Processor 5100 Series package DBR is not a processor signal DBSY 1 0 DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on all processor FSB agents DEFER DEFER is asserted by an agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or I O agent This signal must connect the appropriate pins of all processor FSB agents DP 3 0 1 0 DP 3 0 Data Parity provide parity protection for the D 63 0 signals They are driven by the agent responsible for driving D 63 0
15. M5 Source Sync Input Output A04 P6 Source Sync Input Output A05 L5 Source Sync Input Output A06 L4 Source Sync Input Output AO7 M4 Source Sync Input Output A08 R4 Source Sync Input Output A09 T5 Source Sync Input Output A10 U6 Source Sync Input Output A11 T4 Source Sync Input Output A12 U5 Source Sync Input Output A13 U4 Source Sync Input Output A143 V5 Source Sync Input Output A153 v4 Source Sync Input Output A16 W5 Source Sync Input Output A173 AB6 Source Sync Input Output A185 W6 Source Sync Input Output A195 Y6 Source Sync Input Output A20 Y4 Source Sync Input Output A20M K3 CMOS Async Input A21 AA4 Source Sync Input Output A22 AD6 Source Sync Input Output A23 AA5 Source Sync Input Output A24 AB5 Source Sync Input Output A25 AC5 Source Sync Input Output A26 AB4 Source Sync Input Output A27 AF5 Source Sync Input Output A28 AF4 Source Sync Input Output Dual Core Intel Xeon Processor 5100 Series Datasheet Table 4 1 Land Listing by Land Name Sheet 2 of 20 Pin Name E m Direction A29 AG6 Source Sync Input Output A30 AG4 Source Sync Input Output A31 AG5 Source Sync Input Output A32 AH4 Source Sync Input Output A334 AH5 Source Sync Input Output A34 AJ5 Source Sync Input Output A35 AJ6 Source Sync Input Output ADS D2 Common Clk Input Output ADSTBO R6 Source Sync Input Output ADSTB1 AD5 Sourc
16. Other U24 VCC Power Other P5 RESERVED U25 VCC Power Other P6 A04 Source Sync Input Output U26 VCC Power Other P7 VSS Power Other U27 VCC Power Other P8 VCC Power Other U28 VCC Power Other R1 RESERVED U29 VCC Power Other R2 VSS Power Other U3 AP1 Common Clk Input Output Dual Core Intel Xeon Processor 5100 Series Datasheet 63 intel eens Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 19 of 20 Sheet 20 of 20 us Pin Name Nu m Direction us Pin Name Bude sk Direction uxo vcc Powe Oher Y1 RESERVED U4 A13 Source Sync Input Output Y2 VSS Power Other U5 Al2 Source Sync Input Output Y23 VCC Power Other U6 A10 Source Sync Input Output Y24 VCC Power Other U7 VSS Power Other Y25 VCC Power Other U8 VCC Power Other Y26 VCC Power Other V1 MS ID1 Power Other Output Y27 VCC Power Other V2 LL IDO Power Other Output Y28 VCC Power Other V23 VSS Power Other Y29 VCC Power Other v24 vss Power ter Y3 RESERVED V25 VSS Power Other Y30 VCC Power Other V26 VSS Power Other Y4 A20 Source Sync Input Output v27 vss Power 0ther s vys TPowerf tber V28 VSS Power Other Y6 A19 Source Sync Input Output V29 VSS Power Other Y7 VSS Power Other V3 VSS Power Other Y8 VCC Power Other v30 VSS Power Other v4 A15 Source Sync Inpu
17. RESERVED AH2 RESET G23 Common Clk Input Dual Core Intel Xeon Processor 5100 Series Datasheet 47 intel Land Listing 48 Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 7 of 20 Sheet 8 of 20 Pin Signal Pin Signal Pin Name No Buffer Type Direction Pin Name No Buffer Type Direction RSO B3 Common Clk Input VCC AD25 Power Other RS1 F5 Common Clk Input VCC AD26 Power Other RS2 A3 Common Clk Input VCC AD27 Power Other RSP H4 Common Clk Input VCC AD28 Power Other SKTOCC AE8 Power Other Output VCC AD29 Power Other SMI P2 CMOS Async Input VCC AD30 Power Other STPCLK M3 CMOS Async Input VCC AD8 Power Other TCK AE1 TAP Input VCC AE11 Power Other TDI AD1 TAP Input VCC AE12 Power Other TDO AF1 TAP Output VCC AE14 Power Other TESTHI 00 F26 Power Other Input VCC AE15 Power Other TESTHIO1 W3 Power Other Input VCC AE18 Power Other TESTHI 02 F25 Power Other Input VCC AE19 Power Other TESTHI03 G25 Power Other Input VCC AE21 Power Other TESTHI04 G27 Power Other Input VCC AE22 Power Other TESTHI 05 G26 Power Other Input VCC AE23 Power Other TESTHIO6 G24 Power Other Input VCC AE9 Power Other TESTHI 07 F24 Power Other Input VCC AF11 Power Other TESTHI
18. The Dual Core Intel Xeon Processor 5100 Series package is a Land Grid Array consisting of a processor core mounted on a pinless substrate with 771 lands and includes an integrated heat spreader IHS LGA771 socket The Dual Core Intel Xeon Processor 5100 Series interfaces to the baseboard through this surface mount 771 Land socket See the LGA771 Socket Design Guidelines for details regarding this socket Processor core Processor core with integrated L1 cache L2 cache and system bus interface are shared between the two cores on the die All AC timing and signal integrity specifications are at the pads of the processor core FSB Front Side Bus The electrical interface that connects the processor to the chipset Also referred to as the processor system bus or the system bus All memory and I O transactions as well as interrupt messages pass between the processor and chipset over the FSB Dual I ndependent Bus DIB A front side bus architecture with one processor on each bus rather than a FSB shared between two processor agents The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth Flexible Motherboard Guidelines FMB Are estimates of the maximum values the Dual Core Intel Xeon Processor 5100 Series will have over certain time periods The values are only estimates and actual specifications for future processors may differ Functional Operation Refers to the normal opera
19. These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VIDs found in Table 2 3 The Dual Core Intel Xeon Processor LV 5148 may be shipped under multiple VI Ds for each frequency 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements 78 Dual Core Intel Xeon Processor 5100 Series Datasheet Thermal Specifications intel Figure 6 3 Dual Core Intel Xeon Processor LV 5148 and Dual Core I ntel Xeon Table 6 7 Table 6 8 Processor LV 5128 Thermal Profile 59 TCASE_MAX TDP 57 55 53 Y 0 450 x 40 0 51 Temperature C 49 47 45 20 22 24 26 28 30 32 34 36 38 40 Power W Notes 1 Please refer to Table 6 7 for discrete points that constitute the thermal profile 2 Refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines for system and environmental implementation details Dual Core I ntel Xeon Processor LV 5148 and Dual Core Intel Xeon Processor LV 5128 Thermal Profile Table Power W Tcase_max C P pRoriLE MIN722 2 50 0 25 51 3 30 53 5 35 55 8 40 58 0 Dual Core Intel Xeon Processor 5160 Thermal Specifications Cadre Maximum Thermal Mi
20. When using On Demand mode the duty cycle of the clock modulation is programmable via bits 3 1 of the same 1A32 CLOCK MODULATION MSR In On Demand mode the duty cycle can be programmed from 12 5 on 87 5 off to 87 5 on 12 5 off in 12 5 increments On Demand mode may be used in conjunction with the Thermal Monitor however if the system tries to enable On Demand mode at the same time the TCC is engaged the factory configured duty cycle of the TCC will override the duty cycle selected by the On Demand mode PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor die temperature of either processor cores has reached its factory configured trip point If Thermal Monitor is enabled note that Thermal Monitor must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT Refer to the Intel Architecture Software Developer s Manual and the Conroe and Woodcrest Processor Family BIOS Writer s Guide for specific register and programming details PROCHOT is designed to assert at or a few degrees higher than maximum Tease as specified by Thermal Profile A when dissipating TDP power and cannot be interpreted as an indication of processor case temperature This temperature delta accounts for processor package lifetime and manufacturing variations and a
21. refer to the appropriate platform design guidelines Front Side Bus AGTL Decoupling The Dual Core Intel Xeon Processor 5100 Seriesintegrates signal termination on the die as well as a portion of the required high frequency decoupling capacitance on the processor package However additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the FSB Bulk decoupling must also be provided by the baseboard for proper AGTL bus operation Decoupling guidelines are described in the appropriate platform design guidelines Front Side Bus Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previous processor generations the Dual Core Intel Xeon Processor 5100 Series core frequency is a multiple of the BCLK 1 0 frequency The processor bus ratio multiplier is set during manufacturing The default setting is for the maximum speed of the processor It is possible to override this setting using software see the Conroe and Woodcrest Processor Family BIOS Writer s Guide This permits operation at lower frequencies than the processor s tested frequency Dual Core Intel Xeon Processor 5100 Series Datasheet Electrical Specifications intel The processor core frequency is configured during reset by using values stored internally during manufacturing The stored value sets the highest bus fraction a
22. voltage level for the processor VIT SEL is a no connect on the Dual Core Intel Xeon Processor 5100 Series package Notes 1 For this processor land on the Dual Core Intel Xeon Processor 5100 Series the maximum number of symmetric agents is one Maximum number of priority agents is zero 2 For this processor land on the Dual Core Intel Xeon Processor 5100 Series the maximum number of symmetric agents is two Maximum number of priority agents is zero 3 For this processor land on the Dual Core Intel Xeon Processor 5100 Series the maximum number of symmetric agents is two Maximum number of priority agents is one 8 Dual Core Intel Xeon Processor 5100 Series Datasheet 71 72 Signal Definitions Dual Core Intel Xeon Processor 5100 Series Datasheet Bi Thermal Specifications n tel 6 6 1 Note 6 1 1 Thermal Specifications Package Thermal Specifications The Dual Core Intel Xeon Processor 5100 Series requires a thermal solution to maintain temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system As processor technology changes thermal management becomes increasingly crucial when building computer systems Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes b
23. 08 G3 Power Other Input VCC AF12 Power Other TESTHI 09 G4 Power Other Input VCC AF14 Power Other TESTHI10 P1 Power Other Input VCC AF15 Power Other TESTHI11 L2 Power Other Input VCC AF18 Power Other THERMTRI P M2 Open Drain Output VCC AF19 Power Other Async d VCC AF21 Power Other TMS AC1 TAP Input VCC AF22 Power Other TRDY E3 Common Clk Input VCC AF8 Power Other TRST AG1 TAP Input VCC AF9 Power Other VCC AA8 Power Other VCC AG11 Power Other VCC AB8 Power Other VCC AG12 Power Other VCC AC23 Power Other VCC AG14 Power Other VCC AC24 Power Other VCC AG15 Power Other VCC AC25 Power Other VCC AG18 Power Other VCC AC26 Power Other VCC AG19 Power Other VCC AC27 Power Other VCC AG21 Power Other VCC AC28 Power Other VCC AG22 Power Other VCC AC29 Power Other VCC AG25 Power Other VCC AC30 Power Other VCC AG26 Power Other VCC AC8 Power Other VCC AG27 Power Other VCC AD23 Power Other VCC AG28 Power Other VCC AD24 Power Other VCC AG29 Power Other Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 9 of 20 Sheet 10 of 20 Pin Name N M i m Direction Pin Name N ER e we Direction VCC AG30 Power Other VCC AK26 P
24. 1 A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level The definition provided in Table 2 3 is not related in any way to previous Intel Xeon processors or voltage regulator designs If the processor socket is empty VID 6 1 111111 or the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself See the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details Although the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines defines VID 7 0 VID 7 and VID 0 are not used on the Dual Core Intel Xeon Processor 5100 Series The Dual Core Intel Xeon Processor 5100 Series provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage Vcc This will represent a DC shift in the load line It should be noted that a low to high or high to low voltage state change may result in as many VID transitions as necessary to reach the target core voltage Transitions above the specified VID are not permitted Table 2 13 includes VID step sizes and DC shift ranges Minimum and maximum voltages must be maintained as shown in Table 2 14 and Table 2 2 The VRM or EVRD utilized must be capable of regulating its output to the value defined by the new VID DC specifications for dynamic VID transitions are
25. 1 1 1750 0 0 0 1 0 0 1 5625 1 0 0 0 1 0 1 1875 0 0 0 0 1 1 1 5750 1 0 0 0 0 1 1 2000 0 0 0 0 1 0 1 5875 1 0 0 0 0 0 1 2125 0 0 0 0 0 1 1 6000 0 1 1 1 1 1 1 2250 0 0 0 0 0 0 OFF Dual Core Intel Xeon Processor 5100 Series Datasheet 21 e n tel Electrical Specifications Table 2 4 Voltage I dentification Definition VID6 VID5 VI D4 VI D3 VI D2 VID1 VID6 VID5 VI D4 VI D3 VID2 VI DI HEX 400 200 100 50 25 12 5 Vcc Max HEX 400 200 100 50 25 12 5 Vcc max mV mV mV mV mV mV mV mV mV mV mV mV 7A 1 1 1 1 0 1 0 8500 3C 0 1 1 1 i 0 1 2375 78 1 1 1 1 0 0 0 8625 3A 0 di 1l 1 0 1 1 2500 76 1 1 1 0 1 1 0 8750 38 0 1 1 1 0 0 1 2625 74 1 1 1 0 1 0 0 8875 36 0 1 1 0 1 1 1 2750 72 1 1 1 0 0 1 0 9000 34 0 1 1 0 1 0 1 2875 70 1 1 1 0 0 0 0 9125 32 0 1 1 0 0 1 1 3000 6E 1 1 0 1 1 1 0 9250 30 0 1 1 0 0 0 1 3125 6C 1 1 0 1 1 0 0 9375 2E 0 1 0 1 1 1 1 3250 6A 1 1 0 1 0 1 0 9500 2C 0 1 0 1 1 0 1 3375 68 1 1 0 1 0 0 0 9625 2A 0 1 0 1 0 1 1 3500 66 1 1 0 0 1 1 0 9750 28 0 1 0 1 0 0 1 3625 64 1 1 0 0 1 0 0 9875 26 0 1 0 0 1 1 1 3750 62 1 1 0 0 0 1 1 0000 24 0 1 0 0 1 0 1 3875 60 1 1 0 0 0 0 1 0125 22 0 1 0 0 0 1 1 4000 5E 1 0 1 di il 1 1 0250 20 0 1 0 0 0 0 1 4125 5C 1 0 1 1 1 0 1 0375 1E 0 0 1 1 1 1 1 4250 5A 1 0 1 1 0 1 1 0
26. 1 70 N A 4 70 mA 5 lu Input Leakage Current N A N A 100 HA 6 Notes Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The V4 referred to in these specifications refers to instantaneous Vr 3 Refer to the EE ls 1 O Buffer Models for I V characteristics 4 Measured at 0 1 V 5 6 Measured at 0 9 V For Vin between 0 V and V Measured when the driver is tristated Table 2 17 Open Drain Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VoL Output Low Voltage 0 N A 0 20 V Vou Output High Voltage 0 95 Vir Vr 1 05 Vr V 3 lot Output Low Current 16 N A 50 mA 2 lio Leakage Current N A N A 200 HA 4 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 Measured at 0 2 Vr 3 Voy is determined by value of the external pullup resistor to Vr Refer to platform design guide for details 4 For Viy between 0 V and Voy 2 13 1 Vcc Overshoot Specification The Dual Core Intel Xeon Processor 5100 Series can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high to low current load condition This overshoot cannot exceed VID Vos max Vos max IS the maximum allowable overshoot above VID These specifications apply to the processor die voltage as measured across the VCC DIE SENSE and VSS DIE SENSE lands and across th
27. 7 Name REQ 4 0 Type 1 0 Description REQ 4 0 Request Command must connect the appropriate pins of all processor FSB agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB 1 0 Refer to the AP 1 0 signal description for details on parity checking of these signals Notes RESET Asserting the RESET signal resets all processors to known states and invalidates their internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least 1 ms after VCC and BCLK have reached their proper specifications On observing active RESET all FSB agents will deassert their outputs within two clocks RESET must not be kept asserted for more than 10 ms while PWRGOOD is asserted A number of bus signals are sampled at the active to inactive transition of RESET for power on configuration These configuration options are described in the Section 7 1 This signal does not have on die termination and must be terminated on the system board RS 2 0 RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of all processor FSB agents RSP RSP Response Parity is driven by the response agent the agent responsible for completion of the current transaction during assertion of
28. Clock State Machine rie e Daha n hana kel lepan necne bana nn nn OR benen bet dae 94 8 1 Boxed Dual Core Intel Xeon Processor 5100 Series 1U Passive 3U Active Combination Heat Sink With Removable Fan 97 8 2 Boxed Dual Core Intel Xeon Processor 5100 Series 2U Passive Heat Sink 98 8 3 2U Passive Dual Core Intel Xeon Processor 5100 Series Thermal Solution Exploded View ccceccece ete ete reer eee eee kk kk mnm nnn 98 8 4 Top Side Board Keepout Zones Part 1 cceccccece eect eee eee ee nemen 100 8 5 Top Side Board Keepout Zones Part 2 c cece eee eee mene 101 8 6 Bottom Side Board Keepout ZONES cece emen nemen nene 102 8 7 Board Mounting Hole Keepout Zones sssssssssss emen nee 103 8 8 Volumetric Height Keep Ins 2 0 cece eee eee eee ee eem senes 104 8 9 4 Pin Fan Cable Connector For Active CEK Heat Sink Lkh hkWe k kk 105 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink sss 106 8 11 Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution 108 Table 1 1 Dual Core Intel Xeon Processor 5100 Series 12 2 1 Core Frequency to FSB Multiplier Configuration sssssssssem e 19 2 2 BSEL 2 0 Frequency Table sssssssssssseseeen ennemi 19 2 3 Voltage Identification Definition ssssssssssssesssss ere etree eater raed 21 2 4 Voltage Identification Definition
29. INTEL CORPORATION E RN 299909098890909 900000000 000000000000000 900000000000000 900000000C000000Q00000000Q000000 00000000000000 0000000006o060000Q0 OOOOOOOOOOCOOOOO OOOOOODOOOCOOOOO OQOOOOOOOOOCCOOOOO g000C0000 000000000 000000000 000000000 000000000 000000000 p 00000000000000 CC O00000000000000 O00060600000000008 0000000000000000 000000000 900000000 000000000 000000000 000000000 000000000 00000C000 OOOOCOCOOOOOOODOOO O000000000000000 000000060 000000000 O00000000 000000006 900000000 9600000000 5 000000000 000000000 000000000 000000900 000000000 000000000 QoooOoOO0000 000000000 OOO60000000000o00 000000o 00000006 OOOOOOOOOOCOOOOO OOOOOODOOOCOOOOO OO0O00000000COOOOO0 OoO000000000COOOOO OO0O0OO00000CcOOOOO OoO000000000000000 e6000000060000009000000000000000 0000000000000000 OOO0CCOOOOOOODOOO gg00000C00C00000 0000000000000000 O000000000000000 0000000000000000 Cir W c s H us MSN MLLMETERS D mamac Er tnnc ABAK ki Ti n be 20 3 D14326 DONT CALE DAWK En i Al kar DOOMSSON COLLEGE BLVD PORK BND SANTA GARA CASSIS D E Dual Core Intel Xeon Processor 5100 Series Datasheet 39 intel Figure 3 4 Pr
30. M4 AO7 Source Sync Input Output R24 VSS Power Other M5 A03 Source Sync Input Output R25 VSS Power Other M6 REQ2 Source Sync Input Output R26 VSS Power Other M7 VSS Power Other R27 VSS Power Other M8 VCC Power Other R28 VSS Power Other N1 PWRGOOD CMOS Async Input R29 VSS Power Other N2 IGNNE CMOS Async Input R3 FERR PBE Open Drain Output Async N23 VCC Power Other y R30 VSS Power Other N24 VCC Power Other R4 A08 Source Sync Input Output N25 VEC Power Other R5 VSS Power Other N26 VCC Power Other R6 ADSTBO Source Sync Input Output N27 VCC Power Other R7 VSS Power Other N28 VCC Power Other R8 VCC Power Other N29 VCC Power Other T1 RESERVED N3 VSS Power Other T2 RESERVED N30 VCC Power Other T23 VCC Power Other N4 RESERVED T24 VCC Power Other N5 RESERVED T25 VCC Power Other N6 VSS Power Other T26 VCC Power Other N7 VSS Power Other T27 VCC Power Other N8 VCC Power Other T28 VCC Power Other P1 TESTHI 10 Power Other Input T29 VCC Power Other P2 SMI CMOS Async Input T3 VSS Power Other P23 VSS Power Other T30 VCC Power Other P24 VSS Power Other T4 A11 Source Sync Input Output P25 VSS Power Other T5 A09 Source Sync Input Output P26 VSS Power Other T6 VSS Power Other P27 VSS Power Other T7 VSS Power Other P28 VSS Power Other T8 VCC Power Other P29 VSS Power Other U1 VSS Power Other P3 INIT CMOS Async Input U2 APO Common Clk Input Output P30 VSS Power Other U23 VCC Power Other P4 VSS Power
31. ON Q Y LN3MLNY430 J NO1 12111938 1H913H LN3NOdNOO XVM MW O L SEZT0 V3UV AIGWISSYSIO XNISIV3H 8 780112131538 1H913H LNINOdNOD XVH NN O L SLZ O V3BY WNISIV3H O W0112141 38 1H913H 1N3NOdNOO XVM NM 0 E 91170 j 083931 T SS NN N WY 1 MTS SHIQ 403 2 LHS 339 SNIQ 301 3811100 XN151V3H Ini 3313N193d TWG 830105 134208 EMG r1 o 403 ONIMYYO NId33N SHIQ M04 Z LHS 33S 3N11100 NISLY3H NO NMOHS M 3d6 AHVWIHd 04802 VALNI JO 1N3SNOO N3LLIMM MOINd IHL LOONLIM 03141004 NO Q3V1451Q Q320008434 10 38 10N AVN D SLI ONY 308301402 NI 038010810 SI LI NOILYNOJNI 1YI1N3014NO2 NOIIVMORHOO 13MI gt OWING SIHI Dual Core Intel Xeon Processor 5100 Series Datasheet Figure 8 4 Top Side Board Keepout Zones Part 1 100 Top Side Board Keepout Zones Part 2 L L S L 9 L 8 101 Tyee A HT i co evoh Q38011V SLNINOdWOD QUYOGH3HION ON 1004334 39814 GYVOG ONIYdS M32 W0112181534 1H913H LNINOdNOD QNYOGH3HION XYN WWII EEP 0 V 038011V 183N32V1d 1N3NO4MO QUYOQU3HIOM ON Q 6L SL NOIL2IBIS3N 189 3H 1N3NOdMOO XVN NM O L SLZ 0 V3HY J18W3SSYSIO XNISIV3H m f 6 2 3 W0112131538 1H913H 1N3NOdNOO XVW MM O L GL2 0 V3uV WNISLV3H Q 1009 2 B C 0 3 W0112181534 1H913H 1N3NOdNOO XVW NM 0 E 911 0 j to0r 21 20N3937 O 7 ty 77 777 f tI90721 F E E Ue A
32. Other G19 DSTBP2 Source Sync Input Output H28 VSS Power Other G2 RESERVED H29 VSS Power Other Dual Core Intel Xeon Processor 5100 Series Datasheet 61 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 15 of 20 Sheet 16 of 20 Pin Signal a Pin Signal x No Pin Name Buffer Type Direction No Pin Name Buffer Type Direction H3 VSS Power Other K23 VCC Power Other H30 BSEL1 Power Other Output K24 VCC Power Other H4 RSP Common Clk Input K25 VCC Power Other H5 BR1 Common Clk Input K26 VCC Power Other H6 VSS Power Other K27 VCC Power Other H7 VSS Power Other K28 VCC Power Other H8 VSS Power Other K29 VCC Power Other H9 VSS Power Other K3 A20M CMOS Async Input J1 VTT_OUT Power Other Output K30 VCC Power Other J10 VCC Power Other K4 REQO Source Sync Input Output J11 VCC Power Other K5 VSS Power Other J12 VCC Power Other K6 REQ3 Source Sync Input Output J13 VCC Power Other K7 VSS Power Other J14 VCC Power Other K8 VCC Power Other J15 VCC Power Other L1 LINT1 CMOS Async Input J16 DPO Common Clk Input Output L2 TESTHI11 Power Other Input J17 DP3 Common Clk Input Output L23 VSS Power Other J18 VCC Power Other L24 VSS Power Other J19 VCC Power Other L25 VSS Power Other J2 RESERVED L26 VSS Power Other J20 VCC Power Other L27
33. Other VSS AB27 Power Other VCC Y27 Power Other VSS AB28 Power Other VCC Y28 Power Other VSS AB29 Power Other VCC Y29 Power Other VSS AB30 Power Other VCC Y30 Power Other VSS AB7 Power Other VCC Y8 Power Other VSS AC3 Power Other VCC DIE SENSE AN3 Power Other Output VSS AC6 Power Other VCC DIE SENSE2 AL8 Power Other Output VSS AC7 Power Other VCCPLL D23 Power Other Input VSS AD4 Power Other VID_SELECT AN7 Power Other Output VSS AD7 Power Other VID1 AL5 Power Other Output VSS AE10 Power Other VI D2 AM3 Power Other Output VSS AE13 Power Other VID3 AL6 Power Other Output VSS AE16 Power Other VIDA AKA Power Other Output VSS AE17 Power Other VID5 AL4 Power Other Output VSS AE2 Power Other VID6 AM5 Power Other Output VSS AE20 Power Other VSS A12 Power Other VSS AE24 Power Other VSS A15 Power Other VSS AE25 Power Other VSS A18 Power Other VSS AE26 Power Other VSS A2 Power Other VSS AE27 Power Other VSS A21 Power Other VSS AE28 Power Other VSS A24 Power Other VSS AE29 Power Other VSS A6 Power Other VSS AE30 Power Other VSS AQ Power Other VSS AE5 Power Other VSS AA23 Power Other VSS AE7 Power Other VSS AA24 Power Other VSS AF10 Power Other VSS AA25 Power Other VSS AF13 Power Other VSS AA26 Power Other VSS AF16 Power Other VSS AA27 Power Other VSS AF17 Power Other VSS AA28 Power Other VSS AF20 Power Other VSS AA29 Power Other VSS AF23 Power Other VSS AA3 Power Other VSS AF24 P
34. Output Y AB23 VSS Power Other A15 VSS Power Other AB24 VSS Power Other A16 DSTBN3 Source Sync Input Output AB25 VSS Power Other A17 D56 Source Sync Input Output AB26 VSS Power Other A18 VSS Power Other AB27 VSS Power Other A19 D61 Source Sync Input Output AB28 VSS Power Other A2 VSS Power Other AB29 VSS Power Other A20 RESERVED AB3 MCERR Common Clk Input Output A21 VSS Power Other AB30 VSS Power Other A22 D62 Source Sync Input Output AB4 A26 Source Sync Input Output A23 RESERVED AB5 A24 Source Sync Input Output A24 VSS Power Other AB6 A174 Source Sync Input Output A25 VIT Power Other AB7 VSS Power Other A26 VTT Power Other AB8 VCC Power Other A3 RS2 Common Clk Input AC1 TMS TAP Input A4 D02 Source Sync Input Output AC2 DBR Power Other Output A5 DO4 Source Sync Input Output AC23 VCC Power Other A6 VSS Power Other AC24 VCC Power Other A7 DO7 Source Sync Input Output AC25 VCC Power Other A8 DBIO Source Sync Input Output AC26 VCC Power Other A9 VSS Power Other AC27 VCC Power Other AA1 VTT_OUT Power Other Output AC28 VCC Power Other AA2 LL_ID1 Power Other Output AC29 VCC Power Other AA23 VSS Power Other AC3 VSS Power Other AA24 VSS Power Other AC30 VCC Power Other AA25 VSS Power Other AC4 RESERVED AA26 VSS Power Other AC5 A25 Source Sync Input Output AA27 VSS Power Other AC6 VSS Power Other AA28 VSS Power Other AC7 VS
35. Power Other AE14 VCC Power Other AF23 VSS Power Other AE15 VCC Power Other AF24 VSS Power Other AE16 VSS Power Other AF25 VSS Power Other AE17 VSS Power Other AF26 VSS Power Other AE18 VCC Power Other AF27 VSS Power Other AE19 VCC Power Other AF28 VSS Power Other AE2 VSS Power Other AF29 VSS Power Other AE20 VSS Power Other AF3 VSS Power Other AE21 VCC Power Other AF30 VSS Power Other AE22 VCC Power Other AF4 A28 Source Sync Input Output AE23 VCC Power Other AF5 A27 Source Sync Input Output AE24 VSS Power Other AF6 VSS Power Other AE25 VSS Power Other AF7 VSS Power Other AE26 VSS Power Other AF8 VCC Power Other AE27 VSS Power Other AF9 VCC Power Other AE28 VSS Power Other AG1 TRST TAP Input AE29 VSS Power Other AG10 VSS Power Other AE3 RESERVED AG11 VCC Power Other AE30 VSS Power Other AG12 VCC Power Other AE4 RESERVED AG13 VSS Power Other AE5 VSS Power Other AG14 VCC Power Other AE6 RESERVED AG15 VCC Power Other AE7 VSS Power Other AG16 VSS Power Other 56 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 5 of 20 Sheet 6 of 20 Ne Pin Name De a Direction Ne Pin Name bce Lr Direction AG1
36. Power Other AH17 VSS Power Other AJ26 VCC Power Other AH18 VCC Power Other AJ27 VSS Power Other AH19 VCC Power Other AJ28 VSS Power Other AH2 RESERVED AJ29 VSS Power Other AH20 VSS Power Other AJ3 RESERVED AH21 VCC Power Other AJ30 VSS Power Other AH22 VCC Power Other AJ4 VSS Power Other AH23 VSS Power Other AJ 5 A34 Source Sync Input Output AH24 VSS Power Other AJ6 A35 Source Sync Input Output AH25 VCC Power Other AJ 7 VSS Power Other Dual Core Intel Xeon Processor 5100 Series Datasheet 57 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 7 of 20 Sheet 8 of 20 Pin Signal Pin 2 Signal y No Pin Name Buffer Type Direction No Pin Name Buffer Type Direction AJ8 VCC Power Other AL17 VSS Power Other AJ 9 VCC Power Other AL18 VCC Power Other AK1 RESERVED AL19 VCC Power Other AK10 VSS Power Other AL2 PROCHOT Open Drain Output Async AK11 VCC Power Other y AL20 VSS Power Other AK12 VCC Power Other AL21 VCC Power Other AK13 VSS Power Other AL22 VCC Power Other AK14 VCC Power Other AL23 VSS Power Other AK15 VCC Power Other AL24 VSS Power Other AK16 VSS Power Other AL25 VCC P
37. RS 2 0 the signals for which RSP provides parity protection It must connect to the appropriate pins of all processor FSB agents A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low While RS 2 0 000 RSP is also high since this indicates it is not being driven by any agent guaranteeing correct parity SKTOCC SKTOCC Socket occupied will be pulled to ground by the processor to indicate that the processor is present There is no connection to the processor silicon for this signal SMI SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt processors save the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tri state its outputs See Section 7 1 STPCLK STPCLK Stop Clock when asserted causes processors to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the FSB and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resu
38. Sync Input Output DBR AC2 Power Other Output D29 G14 Source Sync Input Output DBSY B2 Common Clk Input Output D30 F15 Source Sync Input Output DEFER G7 Common Clk Input D31 G15 Source Sync Input Output DPO J16 Common Clk Input Output D32 G16 Source Sync Input Output DP1 H15 Common Clk Input Output D33 E15 Source Sync Input Output DP2 H16 Common Clk Input Output D34 E16 Source Sync Input Output DP3 J17 Common Clk Input Output D35 G18 Source Sync Input Output DRDY CI Common Clk Input Output D36 G17 Source Sync Input Output DSTBNO C8 Source Sync Input Output D37 F17 Source Sync Input Output DSTBN1 G12 Source Sync Input Output D38 F18 Source Sync Input Output DSTBN2 G20 Source Sync Input Output 46 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 5 of 20 Sheet 6 of 20 Pin Signal Pin Signal Pin Name No Buffer Type Direction Pin Name No Buffer Type Direction DSTBN3 A16 Source Sync Input Output RESERVED AJ3 DSTBPO B9 Source Sync Input Output RESERVED AK1 DSTBP1 E12 Source Sync Input Output RESERVED AK3
39. Sync Input Output G3 TESTHI 08 Power Other Input F21 D43 Source Sync Input Output G30 BSEL2 Power Other Output F22 VSS Power Other G4 TESTHI 09 Power Other Input F23 RESERVED G5 PECI Power Other Input Output F24 TESTHIO7 Power Other Input G6 RESERVED F25 TESTHIO2 Power Other Input G7 DEFER Common Clk Input F26 TESTHIOO Power Other Input G8 BPRI Common Clk Input F27 VTT_SEL Power Other Output G9 D16 Source Sync Input Output F28 BCLKO Clk Input H1 GTLREF_DATA Power Other Input F29 RESERVED H10 vss Power Other F3 BRO Common Clk Input Output H11 VSS Power Other F30 VTT Power Other H12 VSS Power Other F4 VSS Power Other H13 VSS Power Other F5 RS1 Common Clk Input H14 VSS Power Other F6 RESERVED H15 DP1 Common Clk Input Output F7 VSS Power Other H16 DP2 Common Clk Input Output F8 D17 Source Sync Input Output H17 VSS Power Other F9 D18 Source Sync Input Output H18 VSS Power Other G1 VSS Power Other H19 VSS Power Other G10 RESERVED H2 GTLREF_ADD Power Other Input G11 DBI1 Source Sync Input Output H20 VSS Power Other G12 DSTBN1 Source Sync Input Output H21 VSS Power Other G13 D27 Source Sync Input Output H22 VSS Power Other G14 D29 Source Sync Input Output H23 VSS Power Other G15 D31 Source Sync Input Output H24 VSS Power Other G16 D32 Source Sync Input Output H25 VSS Power Other G17 D36 Source Sync Input Output H26 VSS Power Other G18 D35 Source Sync Input Output H27 VSS Power
40. both a lower operating frequency and voltage The lowest operating frequency is determined by the lowest supported bus ratio 1 6 for the Dual Core Intel Xeon Processor 5100 Series When the TCC is activated the processor automatically transitions to the new frequency This transition occurs rapidly on the order of 5 us During the frequency transition the processor is unable to service any bus requests and consequently all bus traffic is blocked Edge triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency Once the new operating frequency is engaged the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2 During the voltage change it will be necessary to transition through multiple VID codes to reach the target operating voltage Each step will be one VID table entry see Table 2 3 The processor continues to execute instructions during the voltage transition Operation at the lower voltage reduces the power consumption of the processor A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the operatin
41. ccc ccc en eee emen nennen 36 3 1 Processor Package Assembly Sketch cette eee mene 37 3 2 Processor Package Drawing Sheet 1 of 3 2 eee mene 38 3 3 Processor Package Drawing Sheet 2 of 3 ssssssssssssssseeee mmn 39 3 4 Processor Package Drawing Sheet 3 of 3 ssssssssssssssseee kk kaka 40 3 5 Processor Land Coordinates Top View khkKh kkh kE kk kk mmm eene 43 3 6 Processor Land Coordinates Bottom View ccc ccc kk nee e eee ee nnne sene nnns 44 6 1 Dual Core Intel Xeon Processor 5100 Series Thermal Profile E E 76 4 Dual Core Intel Xeon Processor 5100 Series Datasheet 6 2 Dual Core Intel Xeon Processor LV 5138 Nominal amp Short Term Thermal Profiles cccececeeeet esses eee eee ee n emm emen 77 6 3 Dual Core Intel Xeon Processor LV 5148 and Dual Core Intel Xeon Processor LV 5128 Thermal Profile Ah E Ee 79 6 4 Dual Core Intel Xeon Processor 5160 Thermal Profiles A and B kWCU 80 6 5 Case Temperature TCASE Measurement Location ssssssseeen nnn 82 6 6 Thermal Monitor 2 Frequency and Voltage Ordering Lh lk kk kk 84 0 4 PECI TOPOlOGY uude tote E en nk nea la n y benn de dan daa y b ma ka na E e E bete 87 6 8 Temperature Data Format Comparison Thermal Diode vs PECI Digital Thermal Sensor sobre tation serbe A aana KG kaa nut newt Hek a H herna deyan Kadin ms BADA 88 7 1 Stop
42. consists of a processor core mounted on a pinless substrate with 771 lands An integrated heat spreader IHS is attached to the package substrate and core and serves as the interface for processor component thermal solutions such as a heatsink Figure 3 1 shows a sketch of the processor package components and how they are assembled together Refer to the LGA771 Socket Design Guidelines for complete details on the LGA771 socket The package components shown in Figure 3 1 include the following e Integrated Heat Spreader IHS Thermal Interface Material TIM Processor Core die Package Substrate Landside capacitors Package Lands Figure 3 1 Processor Package Assembly Sketch ims Core die TM Substrate ____ Package Lands LS p MES Capacitors err LGA771 Socket System Board Note This drawing is not to scale and is for reference only 3 1 Package Mechanical Drawings The package mechanical drawings are shown in Figure 3 2 through Figure 3 4 The drawings include dimensions necessary to design a thermal solution for the processor including Package reference and tolerance dimensions total height length width and so forth e IHS parallelism and tilt Land dimensions Top side and back side component keepout dimensions Reference datums Note All drawing dimensions are in mm in Dual Core Intel Xeon Processor 5100 Series Datasheet 37 e n te Mechanical Specifications F
43. guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Figure 2 5 Dual Core Intel Xeon Processor 5100 Series Vcc Static and Transient Tolerance Load Line Icc A 0 10 20 30 40 50 60 70 80 90 VID 0 000 4 a d t E i VID 0 020 VID 0 040 4 Vec f Maximum VID 0 060 4 o VID 0 080 Vcc Minimum VID 0 100 Vcc Typical VID 0 120 4 VID 0 140 VID 0 160 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 13 1 for VCC overshoot specifications 2 Refer to Table 2 13 for processor VID information 3 Refer to Table 2 14 for VccStatic and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC DIE SENSE and VSS DIE SENSE lands and the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementations Dual Core Intel Xeon Processor 5100 Series Datasheet 33 e n tel Electrical Specifications Figure 2 6 Dual Core Inte
44. he 3e 3 D0 NT KALEDIANNE Al E D14326 ke t BNOMSSON CCLLECERLID PO OC D IAA ASSIS om 40 Dual Core Intel Xeon Processor 5100 Series Datasheet Mechanical Specifications 3 2 3 3 Table 3 1 intel Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements A thermal and mechanical solution design must not intrude into the required keepout zones Decoupling capacitors are typically mounted to either the topside or landside of the package substrate See Figure 3 4 for keepout zones Package Loading Specifications Table 3 1 provides dynamic and static load specifications for the processor package These mechanical load limits should not be exceeded during heatsink assembly mechanical stress testing or standard drop and shipping conditions The heatsink attach solutions must not include continuous stress onto the processor with the exception of a uniform load to maintain the heatsink to processor thermal interface Also any mechanical system or component testing should not exceed these limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal or mechanical solutions Package Loading Specifications Board i Parameter Thickness Min Max Unit Notes Static Compressive 1 57 mm 80 3
45. kak kaka k kaka kk kake 91 7 2 Clock Control and Low Power States ssssssssssse Ime aka kaka ene kaka kaka enn 91 7 2 1 Normal State MK K A xqkkhkkk kk Im eese enne kaka kaka kaka ka aa aka aka kaka kk kk kak ke 92 7 2 2 HALT or Extended HALT Stat Kh K A GKUK_llkk kk kk aka aka aka e kak k 92 7 2 3 Stop Grant State isses merino beans brace V HER OET EY AER ERU SA RRA 94 7 2 4 Extended HALT Snoop or HALT Snoop State Stop Grant Snoop State cioesscse kake ene I an REL iran n xan KDE sna law y W ban ante cine 95 7 3 Enhanced Intel SpeedStep Technology Lhkh llklhkkk kk kk kk kaka 95 8 Boxed Processor Specifications kh k lu kk kk kk kk kk kk kk kk rne nnn 97 8 1 Tan gojej la a ol a RIN D D Eon Fer HEE EN E a HIN MN taa aida dO aru Fa EE EEG ea bbs Rn Ead 97 8 2 Mechanical Specifications sy koc s ys i s ka eee nak kla dene ayi a Hie seem nen memes enn 99 8 2 1 Boxed Processor Heat Sink Dimensions CEK Lhk hWl llkkk kk kk 99 8 2 2 Boxed Processor Heat Sink Weight sss 107 8 2 3 Boxed Processor Retention Mechanism and Heat Sink Support EK israr ret era eee Ee Cer on bna nn DOO RA RARE RU RR ER PAR DAD EROR 107 8 3 Electrical Requirements ss i cudakar a bana ana a kd HA E d ka ba A Ml w b dina d z La T A ARD 107 8 3 1 Fan Power Supply Active CEK LkhK h l khk Kh lk kk kk kk kk kk kaka 107 8 3 2 Boxed Processor Cooling RequirementS LhL Lh
46. m hr at 45 3 Pa of flow impedance The duct should be carefully designed to minimize the airflow bypass around the heatsink The T 4 temperature of 40 C should be met This may require the use of superior design techniques to keep TRISE at or below 5 C based on an ambient external temperature of 35 C Boxed Processor Contents A direct chassis attach method must be used to avoid problems related to shock and vibration due to the weight of the thermal solution required to cool the processor The board must not bend beyond specification in order to avoid damage The boxed processor contains the components necessary to solve both issues The boxed processor will include the following items Dual Core Intel Xeon Processor 5100 Series Unattached heat sink solution Four screws four springs and four heat sink standoffs all captive to the heat sink Foam air bypass pad and skirt included with 1U passive 3U active solution Thermal interface material pre applied on heat sink Installation and warranty manual ntel Inside Logo Dual Core Intel Xeon Processor 5100 Series Datasheet 109 e n tel Boxed Processor Specifications The other items listed in Figure 8 3 that are required to compete this solution will be shipped with either the chassis or boards They are as follows CEK Spring supplied by baseboard vendors Heat sink standoffs supplied by chassis vendors 8 110 Dual Core Intel Xeon Proces
47. operating state for the processor HALT or Extended HALT State The Extended HALT state CIE is enabled via the BIOS The Extended HALT state must be enabled for the processor to remain within its specifications The Extended HALT state requires support for dynamic VID transitions in the platform HALT State HALT is a low power state entered when the processor have executed the HALT or MWAIT instruction When one of the processor cores execute the HALT or MWAIT instruction that processor core is halted however the other processor continues normal operation The processor will transition to the Normal state upon the occurrence of SMI BINIT INIT LINT 1 0 NMI INTR or an interrupt delivered over the front side bus RESET will cause the processor to immediately initialize itself The return from a System Management Interrupt SMI handler can be to either Normal Mode or the HALT state See the IA 32 Intel Architecture Software Developer s Manual Volume IIl System Programming Guide for more information The system can generate a STPCLK while the processor is in the HALT state When the system deasserts STPCLK the processor will return execution to the HALT state While in HALT state the processor will process front side bus snoops and interrupts Extended HALT State Extended HALT state is a low power state entered when both processor cores have executed the HALT or MWAIT instructions and Extended HALT state has been ena
48. other than Intel The debug port and J TAG signal chain must be designed into the processor board to utilize the XDP for debug purposes except for interposer solutions Target System Implementation System I mplementation Specific connectivity and layout guidelines for the Debug Port are provided in the Debug Port Design Guide for UP DP Systems and the appropriate platform design guidelines Logic Analyzer I nterface LAI Intel is working with two logic analyzer vendors to provide logic analyzer interfaces LAIs for use in debugging Dual Core Intel Xeon Processor 5100 Series systems Tektronix and Agilent should be contacted to obtain specific information about their logic analyzer interfaces The following information is general in nature Specific information must be obtained from the logic analyzer vendor Due to the complexity of Dual Core Intel Xeon Processor 5100 Series based multiprocessor systems the LAI is critical in providing the ability to probe and capture FSB signals There are two sets of considerations to keep in mind when designing a Dual Core Intel Xeon Processor 5100 Series based system that can make use of an LAI mechanical and electrical Dual Core Intel Xeon Processor 5100 Series Datasheet 111 e n tel Debug Tools Specifications 9 3 1 9 3 2 112 Mechanical Considerations The LAI is installed between the processor socket and the processor The LAI plugs into the socket while the
49. pin G5 PECI Host Controller Addr 0x30 Processor Socket 1 PECI pin G5 Addr 0x31 For Dual Core Intel Xeon Processor 5100 Series Key Difference with Legacy Diode Based Thermal Management Fan speed control solutions utilize a TControl value stored in the processor A32_TEMPERATURE_TARGET MSR Prior to Dual Core Intel Xeon Processor 5100 Series TControl represented a diode temperature With Dual Core Intel Xeon Processor 5100 Series TControl represents an offset from TCC activation temperature The DTS outputs temperature offsets over the PECI interface in response to a GetTemp0 command and these offsets are relative values vs an absolute values The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT Therefore as the temperature approaches TCC activation the value approaches zero degrees Celsius At zero degrees the TCC activates as described in Section 6 2 A data format comparison is shown below in Figure 6 8 While the Tcontrol value for PECI based digital temperature data is different than legacy it will use the same processor register and it will still be necessary for thermal management algorithms to use this new relative temperature format delivered over PECI to control fans or other temperature control methods Dual Core Intel Xeon Processor 5100 Series Datasheet 87 e
50. processor plugs into a socket on the LAI Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer The maximum volume occupied by the LAI known as the keepout volume as well as the cable egress restrictions should be obtained from the logic analyzer vendor System designers must make sure that the keepout volume remains unobstructed inside the system Note that it is possible that the keepout volume reserved for the LAI may include differerent requirements from the space normally occupied by the heatsink If this is the case the logic analyzer vendor will provide a cooling solution as part of the LAI Electrical Considerations The LAI will also affect the electrical performance of the FSB therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide Dual Core Intel Xeon Processor 5100 Series Datasheet
51. provides PREQ Probe Request functionality for the TAP port PREQ is used by debug tools to request debug operation of the processors BPM 5 4 must be bussed to all bus agents Please refer to the appropriate platform design guidelines for more detailed information BPRI l BPRI Bus Priority Request is used to arbitrate for ownership of the processor FSB 3 It must connect the appropriate pins of all processor FSB agents Observing BPRI active as asserted by the priority agent causes all other agents to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BR 1 0 4 1 0 The BR 1 0 signals are sampled on the active to inactive transition of RESET The 3 signal which the agent samples asserted determines its agent ID BRO drives the BREQO signal in the system and is used by the processor to request the bus These signals do not have on die termination and must be terminated BSEL 2 0 O The BCLK 1 0 frequency select signals BSEL 2 0 are used to select the processor input clock frequency Table 2 2 defines the possible combinations of the signals and the frequency associated with each combination The required frequency is determined by the processors chipset and clock synthesizer All FSB agents must operate at the same frequency For more information about thes
52. used for these products is called the Common Enabling Kit or CEK The CEK base is compatible with both thermal solutions and uses the same hole locations as the Intel Xeon processor with 800 MHz system bus The 1U passive 3U active combination solution will utilize a removable fan capable of 4 pin pulse width modulated PWM control Use of a 4 pin PWM controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the motherboards s ability to directly control the RPM of the processor heat sink fan See Section 8 3 for more details on fan speed control and see Section 6 3 for more on the PWM and PECI interface along with Digital Thermal Sensors DTS Figure 8 1 through Figure 8 3 are representations of the two heat sink solutions Boxed Dual Core Intel Xeon Processor 5100 Series 1U Passive 3U Active Combination Heat Sink With Removable Fan Dual Core Intel Xeon Processor 5100 Series Datasheet 97 m e n tel Boxed Processor Specifications Figure 8 2 Figure 8 3 98 Boxed Dual Core Intel Xeon Processor 5100 Series 2U Passive Heat Sink 2U Passive Dual Core Intel Xeon Processor 5100 Series Thermal Solution Exploded View Heat sink screw deeem springs m iil Heat sink Heat sink Screws i Heat sink standoffs Thermal Interface Material Motherboard ilie t and n processor Protective Tape emer CEK spring Chas
53. 11 N 1 2 3 9 Load 0 062 18 70 bf 2 16 mm 111 311 N 0 085 25 70 bf 2 54 mm 133 311 N 0 100 30 70 bf Dynamic Compressive NA NA 311 N max N 1 3 4 5 6 Load static compressive bf load 222 N dynamic loading 70 Ibf max static compressive load 4 50 Ibf dynamic loading Transient Bend Limits 1 57 mm NA 750 me 1 3 7 8 0 062 Notes 1 These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top surface 2 This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These specifications are based on limited testing for design characterization Loading limits are for the LGA771 socket 4 Dynamic compressive load applies to all board thickness 5 Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement 6 Test condition used a heatsink mass of 1 Ibm with 50 g acceleration measured at heatsink mass The dynamic portion of this specification in the product application can have flexibility in specific values but the ultimate product of mass times acceleration should not exceed this dynamic load 7 Transient bend is defined as the transient board deflection during manufacturing such as board assembly and system integration It is a relatively slow bending event compared to shock and vibration tests 8 For more information on the transient bend limits pl
54. 138 in Embedded Applications Thermal Mechanical Design Guideline for information on designing a thermal solution Enhanced Thermal Monitor TM2 The Dual Core Intel Xeon Processor 5100 Series adds supports for an Enhanced Thermal Monitor capability known as Thermal Monitor 2 TM2 This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor TM2 requires support for dynamic VID transitions in the platform When TM2 is enabled and a high temperature situation is detected the Thermal Control Circuit TCC will be activated for both processor cores The TCC causes the processor to adjust its operating frequency via the bus multiplier and input voltage via the VID signals This combination of reduced frequency and VID results in a reduction to the processor power consumption A processor enabled for TM2 includes two operating points each consisting of a specific operating frequency and voltage which is identical for both processor cores The first operating point represents the normal operating condition for the processor Under this condition the core frequency to system bus multiplier utilized by the processor is that contained in the CLOCK FLEX MAX MSR and the VID that is specified in Table 2 3 Dual Core Intel Xeon Processor 5100 Series Datasheet 83 e n tel Thermal Specifications Figure 6 6 6 2 2 84 The second operating point consists of
55. 2 1 AGTL Common Clock I O Synchronous to BCLK 1 0 ADS AP 1 0 BINIT 2 BNR 2 BPM5 BPM3 BPMO BR 1 0 DBSY DP 3 0 DRDY HIT HITM 2 LOCK MCERR AGTL Source Synchronous I Synchronous to assoc strobe Signals Associated Strobe REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 D 15 0 DBIO DSTBPO Z DSTBNO D 31 16 DBI1 DSTBP1 DSTBN1 D 47 32 DBI2 DSTBP2 DSTBN2 D 63 48 DBI3 DSTBP3 DSTBN3 AGTL Strobes I O Synchronous to BCLK 1 0 ADSTB 1 0 DSTBP 3 0 DSTBN 3 0 Open Drain Output Asynchronous FERR PBE ERR PROCHOT THERMTRIP CMOS Asynchronous Input Asynchronous A20M FORCEPR IGNNE INIT LINTO INTR LINT1 NMI PWRGOOD SMI STPCLK CMOS Asynchronous Output Asynchronous BSEL 2 0 VID 6 1 FSB Clock Clock BCLK 1 0 TAP Input Synchronous to TCK TCK TDI TMS TRST TAP Output Synchronous to TCK TDO Power Other Power Other GTLREF_ADD_MID GTLREF_ADD_END GTLREF_DATA_MID GTLREF_DATA_END LL ID 1 0 MS ID 1 0 PECI RESERVED SKTOCC TESTHI 11 0 TESTIN1 TESTIN2 VCC VCC DIE SENSE VCC DIE SENSE2 VCCPLL VID SELECT VSS DIE SENSE VSS DIE SENSE2 VSS VIT VIT OUT VIT SEL Dual Core Intel Xeon Processor 5100 Series Datasheet m Electrical Specifications n tel Table 2 8 Table 2 9 Table 2 10 2 8 2 9 Notes 1 Refer to Section 5 for signal descriptions
56. 2 3 25 VID 0 031 VID 0 046 VID 0 061 1 2 3 30 VID 0 038 VID 0 053 VID 0 068 1 2 3 35 VID 0 044 VID 0 059 VID 0 074 1 2 3 40 VID 0 050 VID 0 065 VID 0 080 1 2 3 45 VID 0 056 VID 0 071 VID 0 086 1 2 3 50 VID 0 063 VID 0 078 VID 0 093 1 2 3 55 VID 0 069 VID 0 084 VID 0 099 1 2 3 60 VID 0 075 VID 0 090 VID 0 115 1 2 3 65 VID 0 081 VID 0 096 VID 0 111 1 2 3 70 VID 0 088 VID 0 103 VID 0 118 1 2 3 75 VID 0 094 VID 0 109 VID 0 124 1 2 3 80 VID 0 100 VID 0 115 VID 0 130 1 2 3 85 VID 0 106 VID 0 121 VID 0 136 1 2 3 90 VID 0 113 VID 0 128 VID 0 143 1 2 3 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 13 1 for VCC overshoot specifications 2 Refer to Table 2 13 for processor VID information 3 Refer to Table 2 14 for VccStatic and Transient Tolerance 32 Dual Core Intel Xeon Processor 5100 Series Datasheet Bi Electrical Specifications n tel 4 The load lines specify voltage limits at the die measured at the VCC DIE SENSE and VSS DIE SENSE lands and the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line
57. 3 1211109 87 6 5 4 3 2 1 Data cooommorearzzvmx4c c z zo Address Common Clock Async Dual Core Intel Xeon Processor 5100 Series Datasheet 43 intel Mechanical Specifications Figure 3 6 Processor Land Coordinates Bottom View 44 Address Common Clock Async XP gt gt gt gt gt gt gt gt gt 3 222222 gt u O om m E amp X r amp Z0 J 4 C lt lt amp Vcc Vss 12345 t 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I gt gt gt gt gt gt gt amp 2 amp 282 Socket 771 Quadrants Bottom View vuoommorcarzzvomxaccz 2858 Pa s 1 23456 7 8 9 1011 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data Vir Clocks Dual Core Intel Xeon Processor 5100 Series Datasheet 4 1 Land Listing Dual Core Intel Xeon Processor 5100 Series Pin Assignments This section provides sorted land list in Table 4 1 and Table 4 2 Table 4 1 is a listing of all processor lands ordered alphabetically by land name Table 4 2 is a listing of all processor lands ordered by land number 4 1 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 1 of 20 Pin Name N BuU E Direction A03
58. 500 1C 0 0 1 1 1 0 1 4375 58 1 0 1 1 0 0 1 0625 1A 0 0 1 1 0 1 1 4500 56 1 0 1 0 1 1 1 0750 18 0 0 1 1 0 0 1 4625 54 1 0 1l 0 1 0 1 0875 16 0 0 1 0 1 1 1 4750 52 1 0 1 0 0 1l 1 1000 14 0 0 1 0 1 0 1 4875 50 1 0 1 0 0 0 1 1125 12 0 0 1 0 0 1 1 5000 4E 1 0 0 1 1 1 1 1250 10 0 0 1 0 0 0 1 5125 4C 1 0 0 1 1 0 1 1375 OE 0 0 0 1 1 1 1 5250 4A 1 0 0 1 0 il 1 1500 oc 0 0 0 1 1 0 1 5375 48 1 0 0 1 0 0 1 1625 0A 0 0 0 1 0 1 1 5500 46 1 0 0 0 1 1 1 1750 08 0 0 0 1 0 0 1 5625 44 1 0 0 0 1 0 1 1875 06 0 0 0 0 1 1 1 5750 42 1 0 0 0 0 1 1 2000 04 0 0 0 0 1 0 1 5875 40 1 0 0 0 0 0 1 2125 02 0 0 0 0 0 1 1 6000 3E 0 1 1 1 1 1 1 2250 00 0 0 0 0 0 0 OFF1 Notes 1 When the 111111 VID pattern is observed the voltage regulator output should be disabled 2 Shading denotes the expected VID range of the Dual Core Intel Xeon Processor 5100 Series 3 The VID range includes VID transitions that may be initiated by thermal events assertion of the FORCEPR signal see Section 6 2 1 2 Extended HALT state transitions see Section 7 2 2 or Enhanced Intel SpeedStep Technology transitions see Section 7 3 The Extended HALT state must be enabled for the processor to remain within its specifications 4 Once the VRM EVRD is operating after power up if either the Output Enable signal is de asserted or a specific VID off code is 22 received the VRM EVRD must turn off its output the output should go to high impedance within 500 ms and latch off until power is c
59. 6 3 for more on the PECI interface PROCHOT PROCHOT Processor Hot will go active when the processor s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the Thermal Control Circuit TCC has been activated if enabled The TCC will remain active until shortly after the processor deasserts PROCHOT See Section 6 2 3 for more details PWRGOOD PWRGOOD Power Good is an input The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD It must also meet the minimum pulse width specification in Table 2 18 and be followed by a 1 10 ms RESET pulse The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation Dual Core Intel Xeon Processor 5100 Series Datasheet 69 intel Table 5 1 Signal Definitions Signal Definitions Sheet 6 of
60. 7 Table 2 7 24 Front Side Bus Signal Groups The FSB signals have been combined into groups by buffer type AGTL input signals have differential input buffers which use GTLREF DATA and GTLREF ADD as reference levels In this document the term AGTL Input refers to the AGTL input group as well as the AGTL I O group when receiving Similarly AGTL Output refers to the AGTL output group as well as the AGTL I O group when driving AGTL asynchronous outputs can become active anytime and include an active PMOS pull up transistor to assist during the first clock of a low to high voltage transition With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters One set is for common clock signals whose timings are specified with respect to rising edge of BCLKO ADS HIT HITM and so forth and the second set is for the source synchronous signals which are relative to their respective strobe lines data and address as well as rising edge of BCLKO Asynchronous signals are still present A20M IGNNE Z and so forth and can become active at any time during the clock cycle Table 2 7 identifies which signals are common clock source synchronous and asynchronous FSB Signal Groups Signal Group Type Signals AGTL Common Clock Input Synchronous to BCLK 1 0 BPRI DEFER RESET RS 2 0 RSP TRDY AGTL Common Clock Output Synchronous to BCLK 1 0 BPM4 BPM
61. 7 VSS Power Other AH26 VCC Power Other AG18 VCC Power Other AH27 VCC Power Other AG19 VCC Power Other AH28 VCC Power Other AG2 BPM3 Common Clk Input Output AH29 VCC Power Other AG20 VSS Power Other AH3 VSS Power Other AG21 VCC Power Other AH30 VCC Power Other AG22 VCC Power Other AH4 A32 Source Sync Input Output AG23 VSS Power Other AH5 A33 Source Sync Input Output AG24 VSS Power Other AH6 VSS Power Other AG25 VCC Power Other AH7 VSS Power Other AG26 VCC Power Other AH8 VCC Power Other AG27 VCC Power Other AH9 VCC Power Other AG28 VCC Power Other AJ1 BPM1 Common Clk Output AG29 VCC Power Other AJ10 VSS Power Other AG3 BPM5 Common Clk Input Output AJ11 VCC Power Other AG30 VCC Power Other AJ12 VCC Power Other AG4 A30 Source Sync Input Output AJ13 VSS Power Other AG5 A31 Source Sync Input Output AJ14 VCC Power Other AG6 A29 Source Sync Input Output AJ15 VCC Power Other AG7 VSS Power Other AJ16 VSS Power Other AG8 VCC Power Other AJ17 VSS Power Other AG9 VCC Power Other AJ18 VCC Power Other AH1 VSS Power Other AJ19 VCC Power Other AH10 VSS Power Other AJ2 BPMO Common Clk Input Output AH11 VCC Power Other AJ20 VSS Power Other AH12 VCC Power Other AJ21 VCC Power Other AH13 VSS Power Other AJ22 VCC Power Other AH14 VCC Power Other AJ23 VSS Power Other AH15 VCC Power Other AJ24 VSS Power Other AH16 VSS Power Other AJ25 VCC
62. 7 Power Other VSS R27 Power Other VTT C28 Power Other VSS R28 Power Other VTT C29 Power Other VSS R29 Power Other VTT C30 Power Other VSS R30 Power Other VTT D25 Power Other VSS R5 Power Other VTT D26 Power Other VSS R7 Power Other VTT D27 Power Other VSS T3 Power Other VTT D28 Power Other VSS T6 Power Other VTT D29 Power Other VSS T7 Power Other VTT D30 Power Other VSS U1 Power Other VTT E30 Power Other VSS U7 Power Other VTT F30 Power Other VSS V23 Power Other VTT_OUT AA1 Power Other Output VSS V24 Power Other VTT OUT J1 Power Other Output VSS V25 Power Other VTT_SEL F27 Power Other Output 54 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing 4 1 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 1 of 20 Sheet 2 of 20 Pin Signal Pin Signal e s No Pin Name Buffer Type Direction No Pin Name Buffer Type Direction A10 DO8 Source Sync Input Output AAT VSS Power Other A11 D09 Source Sync Input Output AA8 VCC Power Other A12 VSS Power Other AB1 VSS Power Other A13 RESERVED AB2 ERR Open Drain Output Async A14 D50 Source Sync Input
63. C1E in addition to the HALT state and Stop Grant state to reduce power consumption by stopping the clock to internal sections of the processor depending on each particular state See Figure 7 1 for a visual representation of the processor low power states The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled via the BI OS for the processor to remain within its specifications Refer to the Conroe and Woodcrest Processor Family BIOS Writer s Guide For processors that are already running at the lowest bus to core frequency ratio for its nominal operating point the processor will transition to the HALT state instead of the Extended HALT state The Stop Grant state requires chipset and BIOS support on multiprocessor systems In a multiprocessor system all the STPCLK signals are bussed together thus all processors are affected in unison When the STPCLK signal is asserted the processor enters the Stop Grant state issuing a Stop Grant Special Bus Cycle SBC for each processor The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states Refer to the applicable chipset specification for more information Dual Core Intel Xeon Processor 5100 Series Datasheet 91 intel 7 2 2 1 7 2 2 2 92 Normal State This is the normal
64. D when running in HALT state 2 Processors running in the lowest bus ratio supported as shown in Table 2 1 will enter the HALT State when the processor has executed the HALT or MWAIT instruction since the processor is already operating in the lowest core frequency and voltage operating point Values represents SKUS with Extended HALT state 24 W and without Extended HALT state 27 W Extended HALT Maximum Power G step Symbol Parameter Min Typ Max Unit Notes PEXTENDED HALT Extended HALT State 6 Ww 1 Dual Core Intel Power Xeon Processor LV 5148 5138 5128 PEXTENDED HALT Extended HALT State 8 12 27 Ww 1 2 Dual Core Intel Power Xeon Processor 5100 Series Note 1 The specification is at Tcase 35 C and nominal Vcc The VID setting represents the maximum expected VID when running in HALT state 2 Processors running in the lowest bus ratio supported as shown in Table 2 1 will enter the HALT State when the processor has executed the HALT or MWAIT instruction since the processor is already operating in the lowest core frequency and voltage operating point Values represents SKUS with Extended HALT state 8 W 1333 FSB 12 W 1066FSB and without Extended HALT state 27 W The processor exits the Extended HALT state when a break event occurs When the processor exits the Extended HALT state it will first transition the VID to the original value and then change the bus to core frequency ratio back
65. DSTBP2 G19 Source Sync Input Output RESERVED AL1 DSTBP3 C17 Source Sync Input Output RESERVED AM2 FERR PBE R3 Open Drain Output RESERVED AM6 Async RESERVED AN5 FORCEPR AK6 CMOS Async Input RESERVED AN6 GTLREF_ADD H2 Power Other Input RESERVED B13 GTLREF_DATA H1 Power Other Input RESERVED B23 HIT D4 Common Clk Input Output RESERVED C23 HITM E4 Common Clk Input Output RESERVED C9 IERR AB2 Open Drain Output Async RESERVED D1 IGNNE N2 CMOS Async Input RESERVED D14 INIT P3 CMOS Async Input RESERVED D16 LINTO K1 CMOS Async Input RESERVED E1 LINT1 L1 CMOS Async Input RESERVED E23 LL IDO V2 Power Other Output RESERVED E24 LL ID1 AA2 Power Other Output RESERVED E5 LOCK C3 Common Clk Input Output RESERVED E6 MCERR AB3 Common Clk Input Output RESERVED E7 MS IDO w Power Other Output RESERVED F2 MS_ID1 v1 Power Other Output RESERVED F23 PECI G5 Power Other Input Output RESERVED F29 PROCHOT AL2 Open Drain Output RESERVED F6 Asyi RESERVED G10 PWRGOOD N1 CMOS Async Input RESERVED G2 REQO K4 Source Sync Input Output RESERVED G6 REQ1 J5 Source Sync Input Output RESERVED J2 REQ2 M6 Source Sync Input Output RESERVED J3 REQ3 K6 Source Sync Input Output RESERVED N4 REQ4 J6 Source Sync Input Output RESERVED N5 RESERVED A13 RESERVED P5 RESERVED A20 RESERVED R1 RESERVED A23 RESERVED Tl RESERVED ACA RESERVED T2 RESERVED AE3 RESERVED W2 RESERVED AE4 RESERVED Y1 RESERVED AE6 RESERVED Y3
66. Dual Core Intel Xeon Processor 5100 Series Datasheet August 2007 Reference Number 313355 003 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Dual Core Intel Xeon Processor 5100 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request 64 bit Intel Xeon processors with Intel EM64T requi
67. En b kina al a kaba 17 2 3 Decoupling Guidelines ascia er lak Klamen a ban n odan ne Dese ne KER Dade eR E a HE Ebe R 18 2 3 1 WGCODecouplings oxi rere hinen tren ente Ner x d an nn haaa gin tup ben EE aa a Ay 18 2 3 2 NTT Decoupling 2 city chee len b n eer ke re aUe Menan h b nin esc ga mp Ue nel bin w n 18 2 3 3 Front Side Bus AGTL Decoupling sssssssesem me 18 2 4 Front Side Bus Clock BCLK 1 0 and Processor Clocking hhkk kk kk 18 2 4 1 Front Side Bus Frequency Select Signals BSEL 2 0 necne 19 2 4 2 PbLLE Power S pply erroe eere Ere tecti e octo aa Eee eed Ure da eda 20 2 5 Voltage Identification VID 0 ce me eem 20 2 6 Reserved or Unused Siigal Ss a mur annanca nakan eee eee eee nennen 23 2 7 Front Side Bus Signal GroupS 0 d sya aka eee u e eminens 24 2 8 CMOS Asynchronous and Open Drain Asynchronous Si gnalS L k h kke EEE 25 2 9 Test Access Port TAP CONNection ccccccccccse kk kk HH aka ka kaka kaka kaka kak kaka 25 2 10 Platform Environmental Control Interface PECI DC SpecificationS k k EEEE 26 2 10 1 DC Characteristics use eredi te e repere Pert ch eni erred ecards 26 2 10 2 Input Device Hysteresis Mhk h Nwl kk kk e kk kak kaka k sine 27 2 11 Mixing Processors ioa r n d wann W nn be Ra h y be tri aa nanna na Kab elbek erbe Wana h bak a 27 2 12 Absolute Maximum and Minimum Ratings sss
68. IYM HOlNJ 3H LNOHLIM 03 J100N YO Q31Y12t 0 0350009438 039012912 30 LON LVH 51N31N09 SLI ONY 32N3014802 NI 038010810 I LI NOILVIHOJNI TY11N30I JN NOI1VBOdMOD TIANI SNIVINOD SNIMYNQ SIHI Dual Core Intel Xeon Processor 5100 Series Datasheet 106 Boxed Processor Specifications n tel 8 2 2 8 2 2 1 8 2 3 8 3 8 3 1 Boxed Processor Heat Sink Weight Thermal Solution Weight The 1U passive 3U active combination heat sink solution and the 2U passive heat sink solution will not exceed a mass of 1050 grams Note that this is per processor a dual processor system will have up to 2100 grams total mass in the heat sinks This large mass will require a minimum chassis stiffness to be met in order to withstand force during shock and vibration See Section 3 for details on the processor weight Boxed Processor Retention Mechanism and Heat Sink Support CEK Baseboards and chassis designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor Refer to the Server System Infrastructure Specification SSI EEB 3 6 TEB 2 1 or CEB 1 1 These specification can be found at http www ssiforum org Figure 8 3 illustrates the Common Enabling Kit CEK retention solution The CEK is designed to extend air cooling capability through the use of larger heat sinks with minimal airflow blockage and bypass CEK retention mechanisms can allow the use of mu
69. OODOOOOOOCOCOOOOQOOO A OQOOOOCCOOCOOOOOOODOOOOOOCOOOOOOOO Es E gl Q000000000000000000000000000000 T a E 1 QOOOOCOCOOOO000000OOOOOOCCOOOOCO FI H y OO oo pe OO EOF j E E T BH a E AEREE 8 lel I xu xeu _ i DEI CLL LT x da erga gt gt Peed alelels J z EIE gz alalgle a i i AB 3 EIEIE ziz s slala z 2 8 2 EH evpe ve5emeemems 5 EH E m cc f b i Hi 7 Lf ff E B gs 8 ES g8 2E Fh 3 8E x EH n lt gs Y i lt 2E Lr msg ae 1 N i E E n d N Sg LOS N i EHI L ape Lo o 28 T o E e o 8 g 2 a 43 2 E ES FE 8 m 88 ER FE 8 88 co ge ss ae ES cT vo uL ud a en lt Note Guidelines on potential I HS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal Mechanical Design Guidelines 38 Dual Core Intel Xeon Processor 5100 Series Datasheet Mechanical Specifications Figure 3 3 Processor Package Drawing Sheet 2 of 3 in te Di p te n ae Dee i Pe Bac BN ie E d L J THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION ITS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED REPRODUCED DISPLAYED OR MODIFIED WITHOUT THE PRIOR WRITTEN CONSENT OF
70. OdES 20 EEE EEE nnne kk nn kk ea 89 7 1 Power On Configuration Option Lands c cece eee eee te tenet kk ka kak 91 7 2 Extended HALT Maximum Power B step ccc cece e eee e eee e ee kk kk kk kak kak kak ka kek 93 7 3 Extended HALT Maximum Power G Step cece cece cere teen eect nee ee kk kaka k nena neta nnns 93 8 1 PWM Fan Frequency Specifications for 4 Pin Active CEK Thermal Solution 108 8 2 Fan Specifications for 4 Pin Active CEK Thermal Solution esses 108 8 3 Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution 108 Dual Core Intel Xeon Processor 5100 Series Datasheet Revision History Revision Description Date 001 Initial release June 2006 002 Updated Sections 2 3 and 6 with SKUs for 5148 5138 5128 November 2006 003 Updated Sections 2 3 and 6 with G step information August 2007 Dual Core Intel Xeon Processor 5100 Series Datasheet Dual Core Intel Xeon Processor 5100 Series Datasheet Features Features Dual Core Intel Xeon Processor 5100 Series Datasheet Dual Core processing with Intel Core microarchitecture FC LGA6 package with 771 Lands Available at up to 3 00 GHz processor speed 65 nm process technology Performance optimized version available Dual processing DP server support Includes 32 KB Level 1 instruction and 32 KB Level 1 data cache per core Inc
71. RS 2 0 RSP TRDY CMOS Asynchronous and Open Drain Asynchronous Signals Legacy input signals such as A20M IGNNE INIT SMI and STPCLK utilize CMOS input buffers Legacy output signals such as FERR PBE IERR PROCHOT and THERMTRIP utilize open drain output buffers All of the CMOS and Open Drain signals are required to be asserted deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state See Chapter 6 for additional timing requirements for entering and leaving the low power states Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic it is recommended that the processor s be first in the TAP chain and followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of Dual Core Intel Xeon Processor 5100 Series Datasheet 25 intel 2 10 1 Electrical Specifications accepting an input of the appropriate voltage Similar considerations must be made for TCK TMS TDO and TRST Two copies of each signal may be required with each driving a different voltage level Platform Environmental Control I nterface PECI DC Specifications The release of the Dual Core Intel Xeon Processor 5100 Series marks the transition from thermal diodes to digital thermal sensors for fan speed control D
72. S Power Other AA29 VSS Power Other AC8 VCC Power Other AA3 VSS Power Other AD1 TDI TAP Input AA30 VSS Power Other AD2 BPM2 Common Clk Output AA4 A21 Source Sync Input Output AD23 VCC Power Other AA5 A23 Source Sync Input Output AD24 VCC Power Other AA6 VSS Power Other Dual Core Intel Xeon Processor 5100 Series Datasheet 55 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 3 of 20 Sheet 4 of 20 us Pin Name Bul de Direction N Pin Name Sune 1 Ga Direction AD25 VCC Power Other AE8 SKTOCC Power Other Output AD26 VCC Power Other AE9 VCC Power Other AD27 VCC Power Other AF1 TDO TAP Output AD28 VCC Power Other AF10 VSS Power Other AD29 VCC Power Other AF11 VCC Power Other AD3 BINIT Common Clk Input Output AF12 VCC Power Other AD30 VCC Power Other AF13 VSS Power Other AD4 VSS Power Other AF14 VCC Power Other AD5 ADSTB1 Source Sync Input Output AF15 VCC Power Other AD6 A22 Source Sync Input Output AF16 VSS Power Other AD7 VSS Power Other AF17 VSS Power Other AD8 VCC Power Other AF18 VCC Power Other AE1 TCK TAP Input AF19 VCC Power Other AE10 VSS Power Other AF2 BPM4 Common Clk Output AE11 VCC Power Other AF20 VSS Power Other AE12 VCC Power Other AF21 VCC Power Other AE13 VSS Power Other AF22 VCC
73. Tcas_ calculated from the thermal profile is equal to 50 C Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP indicated in Table 6 linstead of the maximum processor power consumption The Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature refer to Section 6 2 To ensure maximum flexibility for future requirements systems should be designed to the Flexible Motherboard FMB guidelines even if a processor with lower power dissipation is currently planned The Thermal Monitor and Enhanced Thermal Monitor features must both be enabled in BIOS for the processor to be operating within specifications Dual Core I ntel amp Xeon Processor 5100 Series Thermal Specifications Care Maximum Thermal Minimum Maximum Freauen Power Design Power TCASE TCASE Notes ante W W CC C 5110 through 80 65 5 See Figure 6 1 1 2 3 4 5 6 5150 Table 6 2 5160 80 65 5 See Figure 6 1 1 2 3 4 5 6 Table 6 2 7 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherei
74. VSS Power Other J21 VCC Power Other L28 vss Power Other J22 VCC Power Other L29 VSS Power Other J23 VCC Power Other L3 VSS Power Other J24 VCC Power Other L30 VSS Power Other j25 VCC Power Other L4 A06 Source Sync Input Output J26 VCC Power Other L5 A05 Source Sync Input Output J27 VCC Power Other L6 VSS Power Other J28 VCC Power Other L7 VSS Power Other J29 VCC Power Other L8 VCC Power Other J3 RESERVED M1 VSS Power Other J30 VCC Power Other M2 THERMTRIP Open Drain Output Async J4 VSS Power Other M23 VCC Power Other J5 REQ1 Source Sync Input Output M24 VCC Power Other J6 REQ4 Source Sync Input Output M25 VCC Power Other J7 VSS Power Other M26 VCC Power Other J8 VCC Power Other M27 VCC Power Other J9 VCC Power Other M28 VCC Power Other K1 LI NTO CMOS Async Input M29 VCC Power Other K2 VSS Power Other M3 STPCLK CMOS Async Input 62 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 17 of 20 Sheet 18 of 20 Pin s Signal Pin Signal No Pin Name Buffer Type Direction No Pin Name Buffer Type Direction M30 VCC Power Other R23 VSS Power Other
75. WO S3S0dHNd 3A11Y81Sn0111 d AUYVONNOG f 134205 t ro 1 9 e92 o A TV Li ly ly SSS SV KANY N 32N303438 804 NMOHS QNYOSB 1531 cere LL E CL Z8 Be SS GS SS BR 5552 g e ge Boge E ss S ge Be st ge 52 1nod33 30S AUVINd CYVOEUSHLOW E 1650103 RT GOV T Y T S I 9 Boxed Processor Specifications Figure 8 5 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Figure 8 6 Bottom Side Board Keepout Zones Boxed Processor Specifications ABOVE PLATFORNS 00S 1 6 9 Is2L21 ees toss 21 irs 13 66 2 900 38 1 148 26 15500 N 1099 1021 12900 48 26 MOTHERBOARD BACKSIDE KEEPOUT SCALE 1 500 CONF IDEN E i i SPRING OUTLINE SH FOR ILLUSTRATION PURPOSES THIS DRAWING CONTAINS INTEL CORPORATION ONLY wo E a Z E a x 838 9 a es E zi 5 2 od 2 2 E 2 El o E 5 2 Gu zz B 3 2 s E ss 2 ss i 3 SOr 102 Dual Core Intel Xeon Processor 5100 Series Datasheet 5 rF D Boxed Processor Specifications Figure 8 7 Board Mounting Hole Keepout Zones
76. Y NOI1d182530 j i j y HG PIA ISNY 83d 9N12NY83101 ONY 9NINOISNOHIQ 0 AP67 JO ONIAVY ALITIGYWHYTS I WONTNIN Y 3AYH TIYHS LYYd OJHSINISSALITIGYANYTS T Y NON WIS 1 T 0T9 0I T k 310 03N19N02 2 0291 1S 0 XE 80 S 681 er Y Y NO1123S n Lu T n nam 8 81 8 Pi Sel Xb LM NO11N304302 131 JO INISNOJ M3LIINM NOlWd 3H LUONLIM 3I 09 NI 035019510 1 LI ONI 1 OON 0 Q31v14t10 0350003434 035012510 30 LOM LYW NOI 1304409 131NI SNIVINO ONIAVHO SIH Li Boxed Processor Specifications Figure 8 9 105 Dual Core Intel Xeon Processor 5100 Series Datasheet ntel Boxed Processor Specifications Figure 8 10 4 Pin Base Board Fan Header For Active CEK Heat Sink u3QV3HNI dr 3NDN ONIMYEO THSINIG 430v3H Nid F 6118 29096 Y VYYTD VINYS d4800 Ua j 61185 X08 0 4 San QAI 3911100 NOISSIN 0027 1N3NIHY430 o j NOILI9FOUd 319NV QYIHL 1 17 SLUVd 20 0 52 0 mo a PIA IMSY AL 398v83101 ONY SNOISI 431412345 35 AIR Y Tu ASSY 33d ALO y NOI 1d 182530 W38WTN LYVd ON WILI 401 Nid WG v1A ISNY 33d 9NIONVS3101 ONY 9NINOISN3WIQ P O APG IN dO ONILYY ALITIGVHAVT3 IN WAWINIW Y 3AVH TIWHS LuWd iiir eas E AYOAL a i 330V3HN dP nm NOTAN WIYJLVN I 310N5310N n s Xb XW sll OINI WO 8s 2 0F29 L v8 2 XE 62 NOL 1304403 13LNI JO 1N39N02 NJLI
77. a ka k y kaka ka 45 4 2 Land Listing by Land Number ssssssssssssseseememem memes sese eem eene 55 541 Signal Definitio NS reris eara tat b tee san Mehla a Es fad k Ea Cea ua wa e Rs Madey 65 Dual Core Intel Xeon Processor 5100 Series Datasheet intel 6 1 Dual Core Intel Xeon Processor 5100 Series Thermal Specifications 75 6 2 Dual Core Intel Xeon Processor 5100 Series Thermal Profile Table 76 6 3 Dual Core Intel Xeon Processor LV 5138 Thermal Specifications 77 6 4 Dual Core Intel Xeon Processor LV 5138 Nominal Thermal Profile Table 78 6 5 Dual Core Intel Xeon Processor LV 5138 Short Term Thermal Profile Table 78 6 6 Dual Core Intel Xeon Processor LV 5148 and Dual Core Intel Xeon Processor LV 5128 Thermal Specifications 78 6 7 Dual Core Intel Xeon Processor LV 5148 and Dual Core Intel Xeon Processor LV 5128 Thermal Profile Table sues 79 6 8 Dual Core Intel Xeon Processor 5160 Thermal Specifications sususs 79 6 9 Dual Core Intel Xeon Processor 5160 Thermal Profile A Table jE 80 6 10 Dual Core Intel Xeon Processor 5160 Thermal Profile B Table jjjEjj 81 6 11 Supported PEC Command Functions and Codes cccceccceeeeee eee eeeee senses kk kaka 89 6 12 GetTempO0 Error C
78. age Regulator thermal protection circuitry should not trip for load currents greater then Icc_TDC 2 Not 100 tested Specified by design characterization Figure 2 3 Dual Core Intel Xeon Processor 5100 Series Load Current versus Time 66 65 64 63 62 61 Sustained Current A 60 59 0 01 0 1 1 0 100 1000 Time Duration s Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc Tpc Dual Core Intel Xeon Processor 5100 Series Datasheet 31 e n tel Electrical Specifications 2 Not 100 tested Specified by design characterization Figure 2 4 Dual Core Intel Xeon Processor 5160 Load Current versus Time 95 Sustained Current A 8 75 70 65 0 01 0 1 1 LU 100 1000 Time Duration s Notes 1 Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than Icc TDC M A 2 Not 10096 tested Specified by design characterization Table 2 14 Vcc Static and Transient Tolerance Icc A Vcc Max V Vcc ryp V Vcc Min V Notes 0 VID 0 000 VID 0 015 VID 0 030 1 2 3 5 VID 0 006 VID 0 021 VID 0 036 1 2 3 10 VID 0 013 VID 0 028 VID 0 043 1 2 3 15 VID 0 019 VID 0 034 VID 0 049 1 23 20 VID 0 025 VID 0 040 VID 0 055 1
79. al integrity models which includes buffer and package models Power and Ground Lands For clean on chip processor core power distribution the processor has 223 Vcc power and 273 Vss ground inputs All Vcc lands must be connected to the processor power plane while all Vss lands must be connected to the system ground plane The processor Vcc lands must be supplied with the voltage determined by the processor Voltage I Dentification VID signals See Table 2 3 for VID definitions Twenty two lands are specified as Vz which provide termination for the FSB and provides power to the I O buffers The platform must implement a separate supply for these lands which meets the V specifications outlined in Table 2 13 Dual Core Intel Xeon Processor 5100 Series Datasheet 17 e n tel Electrical Specifications 2 3 1 2 3 2 2 3 3 2 4 18 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds the Dual Core Intel Xeon Processor 5100 Series are capable of generating large average current swings between low and full power states This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate Larger bulk storage Cauik such as electrolytic capacitors supply current during longer lasting changes in current demand by the component such as coming out of an idle condition Similarly they act as a storage well for current when entering an idle cond
80. bled via the BIOS When one of the processor cores executes the HALT instruction that processor core is halted however the other processor core continues normal operation The Extended HALT state is a lower power state than the HALT state or Stop Grant state The Extended HALT state must be enabled for the processor to remain within its specifications The processor will automatically transition to a lower core frequency and voltage operating point before entering the Extended HALT state Note that the processor FSB frequency is not altered only the internal core frequency is changed When entering the low power state the processor will first switch to the lower bus to core frequency ratio and then transition to the lower voltage VID While in the Extended HALT state the processor will process bus snoops Dual Core Intel Xeon Processor 5100 Series Datasheet Features Table 7 2 Table 7 3 Note Extended HALT Maximum Power B step Symbol Parameter Min Typ Max Unit Notes PEXTENDED HALT Extended HALT State 14 Ww 1 Dual Core Intel Power Xeon Processor LV 5148 PEXTEN DED_HALT Extended HALT State 24 27 Ww 12 Dual Core Intel Power Xeon Processor 5100 Series PEXTENDED HALT Extended HALT State 24 Ww 1 Dual Core Intel amp Power Xeon Processor 5160 Note 1 The specification is at Tcase 50 C and nominal Vcc The VID setting represents the maximum expected VI
81. ch heavier heat sink masses compared to legacy limits by using a load path directly attached to the chassis pan The CEK spring on the secondary side of the baseboard provides the necessary compressive load for the thermal interface material The baseboard is intended to be isolated such that the dynamic loads from the heat sink are transferred to the chassis pan via the stiff screws and standoffs The retention scheme reduces the risk of package pullout and solder joint failures All components of the CEK heat sink solution will be captive to the heat sink and will only require a Phillips screwdriver to attach to the chassis pan When installing the CEK the CEK screws should be tightened until they will no longer turn easily This should represent approximately 6 8 inch pounds of torque More than that may damage the retention mechanism components Electrical Requirements Fan Power Supply Active CEK The 4 pin PWM controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics This is achieved though more accurate measurement of processor die temperature through the processor s Digital Thermal Sensors Fan RPM is modulated through the use of an ASIC located on the baseboard that sends out a PWM control signal to the 4th pin of the connector labeled as Control This thermal solution requires a constant 12 V supplied to pin 2 of the active thermal solution and does not support variable voltage contro
82. converter integrated onto the system board that provides the correct voltage and current to the processor based on the logic state of the processor VID bits Vcc The processor core power supply Vss The processor ground V41 FSB termination voltage Note In some Intel processor EMTS documents V is instead called Vccp 1 2 State of Data The data contained within this document is the most accurate information available by the publication date of this document Values are subject to change prior to production 1 3 References Material and concepts available in the following documents may be beneficial when reading this document 14 Dual Core Intel Xeon Processor 5100 Series Datasheet Introduction intel Document I ntel Order Number AP 485 Intel Processor Identification and the CPUID Instruction 241618 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 1 Basic Architecture 253665 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2A 253000 Instruction Set Reference Manual A M 253667 253668 253669 Intel 64 and IA 32 Architectures Software Developer s Manual Volume 2B Instruction Set Reference Manual N Z Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A System Programming Guide Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B System Programming Guide Intel 64 and IA 32 Intel Architecture Optimizat
83. d signals are low This allows parity to be high when all the covered signals are high AP 1 0 must be connected to the appropriate pins of all Dual Core Intel Xeon Processor 5100 Series FSB agents The following table defines the coverage model of these signals Request Signals Subphase 1 Subphase 2 A 35 24 APO AP1 A 23 3 AP1 APO REQ 4 0 AP1 APO BCLK 1 0 The differential bus clock pair BCLK 1 0 Bus Clock determines the FSB frequency All processor FSB agents must receive these signals to drive their outputs and latch their inputs All external timing parameters are specified with respect to the rising edge of BCLKO crossing Vcnoss Dual Core Intel Xeon Processor 5100 Series Datasheet 65 Bi intel Table 5 1 Signal Definitions Sheet 2 of 7 Name Type Description Notes BINIT 1 0 BINIT Bus Initialization may be observed and driven by all processor FSB agents 3 and if used must connect the appropriate pins of all such agents If the BINIT driver is enabled during power on configuration BINIT is asserted to signal any bus condition that prevents reliable future operation If BINIT observation is enabled during power on configuration see Section 7 1 and BINIT is sampled asserted symmetric agents reset their bus LOCK activity and bus request arbitration state machines The bus agents do not reset their O Queue 10Q and transact
84. e Sync Input Output APO U2 Common Clk Input Output AP1 U3 Common Clk Input Output BCLKO F28 Clk Input BCLK1 G28 Clk Input BINIT AD3 Common Clk Input Output BNR C2 Common Clk Input Output BPMO AJ2 Common Clk Input Output BPM1 AJ1 Common Clk Output BPM2 AD2 Common Clk Output BPM3 AG2 Common Clk Input Output BPM4 AF2 Common Clk Output BPM5 AG3 Common Clk Input Output BPRI G8 Common Clk Input BRO F3 Common Clk Input Output BR1 H5 Common Clk Input BSELO G29 Power Other Output BSEL1 H30 Power Other Output 45 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 3 of 20 Sheet 4 of 20 Pin Name a te R Direction Pin Name un PEL as Direction BSEL2 G30 Power Other Output D39 E18 Source Sync Input Output DOO B4 Source Sync Input Output D40 E19 Source Sync Input Output DO1 C5 Source Sync Input Output D41 F20 Source Sync Input Output DO2 A4 Source Sync Input Output D42 E21 Source Sync Input Output DO3 C6 Source Sync Input Output D43 F21 Source Sync Input Output DO4 A5 Source Sync Input Output D44 G21 Source Sync Input Output DO5 B6 Source Sync Input Output D45 E22 Source Sync Input Output D06 B7 Source Sync Input Output D46 D22 Source Sync Input Output DO7 A7 Source Sync Input Output D47 G22 So
85. e VCC DIE SENSE2 and VSS DIE SENSE2 lands Table 2 18 Vcc Overshoot Specifications Symbol Parameter Min Max Units Figure Notes Vos MAX Magnitude of Vcc overshoot above VID 50 mV 2 7 Tos MAX Time duration of Vcc overshoot above VID 25 us 2 7 Dual Core Intel Xeon Processor 5100 Series Datasheet 35 e n tel Electrical Specifications Figure 2 7 Vcc Overshoot Example Waveform 2 13 2 36 Example Overshoot Waveform VID 0 050 Vos o o S o gt VID 0 000 Tos 0 5 10 15 20 25 Time us Tos Overshoot time above VID Vos Overshoot above VID Notes 1 VOS is the measured overshoot voltage 2 TOS is the measured time duration above VID Die Voltage Validation Core voltage VCC overshoot events at the processor must meet the specifications in Table 2 18 when measured across the VCC DIE SENSE and VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands Overshoot events that are 10 ns in duration may be ignored These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope 8 Dual Core Intel Xeon Processor 5100 Series Datasheet Mechanical Specifications n tel 3 Mechanical Specifications The Dual Core Intel Xeon Processor 5100 Series is packaged in a Flip Chip Land Grid Array FC LGA6 package that interfaces to the baseboard via a LGA771 socket The package
86. e signals including termination recommendations refer to the appropriate platform design guideline 66 Dual Core Intel Xeon Processor 5100 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 3 of 7 intel Name D 63 0 Type 1 0 Description D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor FSB agents and must connect the appropriate pins on all such agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to strobes and DBI DSTBN DSTBP Daly Data Group D 15 0 0 D 31 16 1 D 47 32 2 D 63 48 3 WIN ejo Furthermore the DBI signals determine the polarity of the data signals Each group of 16 data signals corresponds to one DBI signal When the DBI signal is active the corresponding data group is inverted and therefore sampled active high Notes DBI 3 0 1 0 DBI 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DBI 3 0 signals are activated when the data on the data bus is inverted
87. ease refer to the MAS document entitled Manufacturing with Intel components using 771 land LGA package that interfaces with the motherboard via a LGA771 socket Dual Core Intel Xeon Processor 5100 Series Datasheet 41 Table 3 2 3 5 3 6 42 9 Mechanical Specifications Refer to the Dual Core Intel Xeon Processor 5100 SeriesThermal Mechanical Design Guidelines or Dual Core Intel Xeon Processor LV 5138 in Embedded Applications Thermal Mechanical Design Guidelines for information on heatsink clip load metrology Package Handling Guidelines Table 3 2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Package Handling Guidelines Parameter Maximum Recommended Units Notes Shear 311 N 70 Ibf is Tensile 111 N 25 Ibf 2 4 5 Torque 3 95 N m 3 4 5 35 LBF in Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 Atorque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization and incidental applications one time only 5 Handling guideline
88. ed however this may interfere with some TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bidirectional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Resistor values should be within 2096 of the impedance of the baseboard trace for FSB signals unless otherwise noticed in the appropriate platform design guidelines For unused AGTL input or I O signals use pull up resistors of the same value as the on die termination resistors Rrr Some TAP CMOS Asynchronous inputs and CMOS Asynchronous outputs do not include on die termination Inputs and utilized outputs must be terminated on the baseboard Unused outputs may be terminated on the baseboard or left unconnected Note that leaving unused outputs unterminated may interfere with some TAP functions complicate debug probing and prevent boundary scan testing Signal termination for these signal types is discussed in the appropriate platform design guidelines Each of the TESTHI signals must be tied to the processor Vr individually using a matched resistor where a matched resistor has a resistance value within 20 of the impedance of the board transmission line traces For example if the trace impedance is 50 Q then a value between 40 Q and 60 Q is required Dual Core Intel Xeon Processor 5100 Series Datasheet 23 e n tel Electrical Specifications 2
89. eet m Electrical Specifications n tel 14 Icc tpc is the sustained DC equivalent current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment The voltage regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the processor of a thermal excursion Please see the applicable design guidelines for further details The processor is capable of drawing Icc tpc indefinitely Refer to Figure 2 1 for further details on the average processor current draw over various time durations This parameter is based on design characterization and is not tested 15 This is the maximum total current drawn from the Vr plane by only one processor with R r enabled This specification does not include the current coming from on board termination Rr through the signal line Refer to the appropriate platform design guide and the Voltage Regulator Design Guidelines to determine the total l r drawn by the system This parameter is based on design characterization and is not tested 16 lec vm our iS Specified at 1 2 V Figure 2 2 Dual Core Intel Xeon Processor LV 5148 5138 5128 Processor Load Current versus Time 46 45 44 43 42 41 40 39 38 Sustained Current A 37 36 35 34 r r r 0 01 0 1 1 10 100 1000 Time Duration s Notes 1 Processor or Volt
90. ent a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Platform Environment Control Interface PECI bus as described in Section 6 3 The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Section 6 2 Processor Thermal Features Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications The Dual Core Intel Xeon Processor 5100 Series Dual Core Intel Xeon Processor LV 5148 and Dual Core Intel Xeon Processor LV 5128 support a single Thermal Profile see Figure 6 1 Table 6 2 Figure 6 3 and Table 6 7 With these Thermal Profiles it s expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive Dual Core Intel Xeon Processor 5100 Series Datasheet 73 n tel Thermal Specifications applications Refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines for details on system thermal solution design thermal profiles and environmen
91. eon Processor 5100 Series Datasheet 53 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 19 of 20 Sheet 20 of 20 Pin Name um gel r au Direction Pin Name N El an Direction VSS L28 Power Other VSS V26 Power Other VSS L29 Power Other VSS V27 Power Other VSS L3 Power Other VSS V28 Power Other VSS L30 Power Other VSS V29 Power Other VSS L6 Power Other VSS v3 Power Other VSS L7 Power Other VSS v30 Power Other VSS M1 Power Other VSS V6 Power Other VSS M7 Power Other VSS V7 Power Other VSS N3 Power Other VSS wa Power Other VSS N6 Power Other VSS W7 Power Other VSS N7 Power Other VSS Y2 Power Other VSS P23 Power Other VSS Y5 Power Other VSS P24 Power Other VSS Y7 Power Other VSS P25 Power Other VSS_DIE_SENSE AN4 Power Other Output VSS P26 Power Other VSS_DIE_SENSE2 AL7 Power Other Output VSS P27 Power Other VTT A25 Power Other VSS P28 Power Other VTT A26 Power Other VSS P29 Power Other VTT B25 Power Other VSS P30 Power Other VTT B26 Power Other VSS P4 Power Other VTT B27 Power Other VSS P7 Power Other VTT B28 Power Other VSS R2 Power Other VTT B29 Power Other VSS R23 Power Other VTT B30 Power Other VSS R24 Power Other VTT C25 Power Other VSS R25 Power Other VTT C26 Power Other VSS R26 Power Other VTT C2
92. er AN19 VCC Power Other B4 DOO Source Sync Input Output AN2 VSS Power Other B5 VSS Power Other AN20 VSS Power Other B6 DO5 Source Sync Input Output AN21 VCC Power Other B7 D06 Source Sync Input Output AN22 VCC Power Other B8 VSS Power Other AN23 VSS Power Other B9 DSTBPO Source Sync Input Output AN24 VSS Power Other C1 DRDY Common Clk Input Output AN25 VCC Power Other C10 VSS Power Other AN26 VCC Power Other C11 D11 Source Sync Input Output AN3 VCC DIE SENSE Power Other Output C12 D14 Source Sync Input Output AN4 VSS_DIE_SENSE Power Other Output C13 VSS Power Other AN5 RESERVED C14 D52 Source Sync Input Output AN6 RESERVED C15 D51 Source Sync Input Output AN7 VID_SELECT Power Other Output C16 VSS Power Other AN8 VCC Power Other C17 DSTBP3 Source Sync Input Output AN9 VCC Power Other C18 D54 Source Sync Input Output B1 VSS Power Other C19 VSS Power Other B10 D10 Source Sync Input Output C2 BNR Common Clk Input Output Dual Core Intel Xeon Processor 5100 Series Datasheet 59 intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 11 of 20 Sheet 12 of 20 us Pin Name Sue aod Direction us Pin Name Bue Pu Direction C20 DBI3 Source Sync Input Output D3 vss Power Other C21 D58 Source Sync Input Output D30 VIT Powe
93. ermal and power management capabilities are implemented including Thermal Monitor TM1 Thermal Monitor 2 TM2 and Enhanced Intel SpeedStep Technology These technologies are targeted for dual processor in enterprise environments TM1 and TM2 provide efficient and effective cooling in high temperature situations Enhanced Intel SpeedStep Technology provides power management capabilities to servers and workstations Dual Core Intel Xeon Processor 5100 Series features include Advanced Dynamic Execution enhanced floating point and multi media units Streaming SIMD Extensions 2 SSE2 and Streaming SIMD Extensions 3 SSE3 Advanced Dynamic Execution improves speculative execution and branch prediction internal to the processor The floating point and multi media units include 128 bit wide registers and a separate register for data movement SSE3 instructions provide highly efficient double precision floating point SI MD integer and memory management operations The Dual Core Intel Xeon Processor 5100 Series support Intel Extended Memory 64 Technology Intel EM64T as an enhancement to Intel s A 32 architecture This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on Intel Extended Memory 64 Technology and its programming model can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel co
94. g frequency and voltage transition back to the normal system operating point Transition of the VID code will occur first in order to insure proper operation once the processor reaches its normal operating frequency Refer to Figure 6 6 for an illustration of this ordering Thermal Monitor 2 Frequency and Voltage Ordering Tiv Temperature Frequency Vcc Time T hysterisis The PROCHOT signal is asserted when a high temperature situation is detected regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled On Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption This mechanism is referred to as On Demand mode and is distinct from the Thermal Monitor and Thermal Monitor 2 features On Demand mode is intended as a means to reduce system level power consumption Systems utilizing the Dual Core Intel Xeon Processor 5100 Series must not rely on software usage of this mechanism to limit the processor temperature Dual Core Intel Xeon Processor 5100 Series Datasheet m Thermal Specifications n tel 6 2 3 6 2 4 If bit 4 of the 1A32_CLOCK_MODULATION MSR is set to a 1 the processor will immediately reduce its power consumption via modulation starting and stopping of the internal core clock independent of the processor temperature
95. hk k khk Kh h l lkk kk kk me 108 8 4 Boxed Processor CoOontentS Mk hk N WQhshkkkkkkk kk e ehem ease eae enean nean nnn nnn 109 9 Debug Tools Specifications i i etn DDR ERE TERRAE a A VER RR MARRE EAR EE War n nik eka 111 9 1 Debug Port System Requirements sss nemen 111 9 2 Target System Implementation ssssssssssese mnes enn 111 9 2 1 System Implementation sss nme memes aa ka 111 9 3 Logic Analyzer Interface LAI MHKMh K l l K K k kk kk kk kk kk kk kk nme nnn nnn 111 9 3 1 Mechanical Considerations h khhWlllk kk k klkkkklk kk kk aka nennen kak ke 112 9 3 2 Electrical Considerations csse eee meme nn 112 Figures 2 l Input Device Hysteresis eicit eene o ER REY E ERR X LER IR i ER RR RR ERG wake wa eed 27 2 2 Dual Core Intel Xeon Processor LV 5148 5138 5128 Processor Load Current versus Time essssssssssssssssen nehmen kk k k kk kk kk kk ka 31 2 3 Dual Core Intel Xeon Processor 5100 Series Load Current versus Time 31 2 4 Dual Core Intel Xeon Processor 5160 Load Current versus Time 32 2 5 Dual Core Intel Xeon Processor 5100 Series VCC Static and Transient Tolerance Load Line sessese HH hme meme hehe nnn nnn 33 2 6 Dual Core Intel Xeon Processor LV 5148 5138 5128 VCC Static and Transient Tolerance Load Lines cssssses meme nen 34 2 7 VCC Overshoot Example Waveform
96. however this does not apply to frequency transitions initiated due to thermal events Extended HALT Enhanced Intel SpeedStep Technology transitions or assertion of the FORCEPR signal See Chapter 6 Not all operating systems can support dual processors with mixed frequencies Mixing processors of different steppings but the same model as per CPUID instruction is supported Details regarding the CPUID instruction are provided in the Intel Processor Identification and the CPUID Instruction application note Absolute Maximum and Minimum Ratings Table 2 12 specifies absolute maximum and minimum ratings only which lie outside the functional limits of the processor Only within specified operation limits can functionality and long term reliability be expected At conditions outside functional operation condition limits but within absolute maximum and minimum ratings neither functionality nor long term reliability can be expected If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits but within the absolute maximum and minimum ratings the device may be functional but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits Dual Core Intel Xeon Processor 5100 Series Datasheet 27 Table 2 12 28 Electrical Specifications At conditions exceeding absolute maximum and minimum ratings neither fu
97. igital Thermal Sensors DTS are on die analog to digital temperature converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature Data from the DTS are processed and stored in a processor register which is queried through the Platform Environment Control Interface PECI PECI is a proprietary one wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal monitoring devices More detailed information may be found in Section 6 3 DC Characteristics A PECI device interface operates at a nominal voltage set by Vy The set of DC electrical specifications shown in Table 2 11 is used with devices normally operating from a Vy interface supply Vrr nominal levels will vary between processor families All PECI devices will operate at the V level determined by the processor installed in the system For specific nominal V m levels refer to the appropriate processor EMTS Table 2 11 PECI DC Electrical Limits 26 Symbol Definition and Conditions Min Max Units Notes Vin Input Voltage Range 0 150 Vr 0 150 V Vhysteresis Hysteresis 0 1 Vir N A V Negative edge threshold Vn voltage 0 275 Vr 0 500 Vr V Positive edge threshold Vp voltage 0 550 Vz 0 725 Vr V High level output source l 6 0 N A mA source Voy 0 75 Vm Low level output sink lsi 0 5 1 0 mA sink V
98. ign Guideline for system and environmental implementation details Dual Core Intel Xeon Processor 5100 Series Datasheet 71 e n tel Thermal Specifications Table 6 4 Dual Core Intel Xeon Processor LV 5138 Nominal Thermal Profile Table Power W Tcase Max C P PROFILE MIN NOMINAL 6 8 50 0 10 52 4 15 56 1 20 59 7 25 63 4 30 67 1 35 70 8 Table 6 5 Dual Core Intel Xeon Processor LV 5138 Short Term Thermal Profile Table Power W Tcase Max C P PROFILE MIN SHORT TERM 60 0 5 63 7 10 67 4 15 71 1 20 74 7 25 78 4 30 82 1 35 85 8 Table 6 6 Dual Core Intel Xeon Processor LV 5148 and Dual Core Intel Xeon Processor LV 5128 Thermal Specifications Thermal Minimum Maximum Processor Design Power TCASE TCASE Notes w C C 5148 40 5 See Figure 6 3 1 2 3 4 5 Table 6 7 5128 40 5 See Figure 6 3 1 2 3 4 5 Table 6 7 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and I cc combination wherein Vcc exceeds Vcc max at specified Icc Please refer to the loadline specifications in Section 2 i 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3
99. igure 3 2 Processor Package Drawing Sheet 1 of 3 x 2 m m a o E i i 2 La a SR og e xt is e FEE i 4 E AE 2 g q eo H O0000000000000000000060000000 O00000000000000000000000CC00C0000 E OOO0O0CCOOOOOODOOQOOOOOOOCCOOOOOOOD E QOOOCcOOOOOO000OQOOOOOOCOOOOOOOO ly ze 0000000000000000000000C000000009 bea E i oOOOOCcOOOO0000D00QOOOOOOCOOOOOO0O00Q OOO0O00OcOo000000000005000000COOO000000 000006600000000000000000000000000 xa 000006600 X 4 9006060000 000000000 600000000 s 900000000 ocooooooobo zu FEI als Pi 900000000 90000005 Bg EREKE E 065006066 96000000 065006606 96666000 M 666056606 j m D 66606009 H B ERN 000000000 I 6600600006 PE 900000000 00000000 a HEI FEI t FI 000006000 06000060 EEE BR B 066066666 66600000 sla LE 000000600 6660060009 000000000 gi 1 6006060085 o0000CCCO o0000000 Iz 66600666600000000000000066006009 06005666606665650660066660666669 OOoOOO0O0600000005000000000606000000009 A B OOOOOCCOOOOOOD
100. included in Table 2 13 and Table 2 14 Dual Core Intel Xeon Processor 5100 Series Datasheet Electrical Specifications intel Power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable Table 2 3 Voltage Identification Definition pe Mag Ma yos wez aa ve URE Re MR es xez 2 u ma 1 1 1 1 0 1 0 8500 0 1 1 1 1 0 1 2375 1 1 1 1 0 0 0 8625 0 1 1 1 0 1 1 2500 1 1 1 0 1 1 0 8750 0 1 1 1 0 0 1 2625 1 1 1 0 1 0 0 8875 0 1 1 0 1 1 1 2750 1 1 1 0 0 1 0 9000 0 1 1 0 1 0 1 2875 1 1 1 0 0 0 0 9125 0 1 1 0 0 1 1 3000 1 1 0 1 1 1 0 9250 0 1 1 0 0 0 1 3125 1 1 0 1 1 0 0 9375 0 1 0 1 1 1 1 3250 1 1 0 1 0 1 0 9500 0 1 0 1 1 0 1 3375 1 1 0 1 0 0 0 9625 0 1 0 1 0 1 1 3500 1 1 0 0 1 1 0 9750 0 1 0 1 0 0 1 3625 1 1 0 0 1 0 0 9875 0 1 0 0 1 1 1 3750 1 1 0 0 0 1 1 0000 0 1 0 0 1 0 1 3875 1 1 0 0 0 0 1 0125 0 1 0 0 0 1 1 4000 1 0 1 1 1 1 1 0250 0 1 0 0 0 0 1 4125 1 0 1 1 1 0 1 0375 0 0 1 1 1 1 1 4250 1 0 1 1 0 1 1 0500 0 0 1 1 1 0 1 4375 1 0 1 1 0 0 1 0625 0 0 1 1 0 1 1 4500 1 0 1 0 1 1 1 0750 0 0 1 1 0 0 1 4625 1 0 1 0 1 0 1 0875 0 0 1 0 1 1 1 4750 1 0 1 0 0 1 1 1000 0 0 1 0 1 0 1 4875 1 0 1 0 0 0 1 1125 0 0 il 0 0 1 1 5000 i 0 0 1 1 1 1 1250 0 0 1 0 0 0 1 5125 1 0 0 1 1 0 1 1375 0 0 0 1 1 1 1 5250 1 0 0 1 0 1 1 1500 0 0 0 1 1 0 1 5375 1 0 0 1 0 0 1 1625 0 0 0 1 0 1 1 5500 1 0 0 0 1
101. ion Reference Manual Intel 64 and IA 32 Architectures Software Developer s Manual 248966 Documentation Changes 1A 32 Intel Architecture and Intel Extended Memory 64 Software 252046 Developer s Manual Documentation Changes Inte Extended Memory 64 Technology Volume 300834 Volume 2 300835 Intel virtualization Technology Specification for 1A 32 Intel Architecture C97063 002 Dual Core Intel Xeon Processor 5100 Series Specification Update 313356 Debug Port Design Guide for UP DP Systems 313373 Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines EPS12V Power Supply Design Guide A Server system Infrastructure SSI Specification for Entry Chassis Power Supplies www ssiforum org Entry Level Electronics Bay Specifications A Server System Infrastructure SSI Specification for Entry Pedestal Servers and Workstations www ssiforum org Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design 313357 Guidelines Dual Core Intel Xeon Processor LV 5138 in Embedded Applicataions 315225 Thermal Mechanical Design Guidelines Dual Core Intel Xeon Processor 5100 Series Boundary Scan Descriptive Language BSDL Model www intel com design Xeon documentation htm NEBS TM Requirements Physical Protection GR 63 CORE http telecom info telcordia com Electromagnetic Compatibility and Electrical Safety Generic Criteria fo
102. ion tracking state machines upon observation of BINIT assertion Once the BINIT assertion has been observed the bus agents will re arbitrate for the FSB and attempt completion of their bus queue and IOQ entries If BINIT observation is disabled during power on configuration a priority agent may handle an assertion of BINIT as appropriate to the error handling architecture of the system BNR 1 0 BNR Block Next Request is used to assert a bus stall by any bus agent who is 3 unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions Since multiple agents might need to request a bus stall at the same time BNR is a wired OR signal which must connect the appropriate pins of all processor FSB agents In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is activated on specific clock edges and sampled on specific clock edges BPM5 1 0 BPM 5 0 Breakpoint Monitor are breakpoint and performance monitor signals 2 BPM4 They are outputs from the processor which indicate the status of breakpoints and O MO BPM3 programmable counters used for monitoring processor performance BPM 5 0 1 0 should connect the appropriate pins of all FSB agents BPM 2 11 O BPM4 provides PRDY Probe Ready functionality for the TAP port PRDY is a BPMO I O processor output used by debug tools to determine processor debug readiness BPM5
103. ition from a running condition Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2 13 Failure to do so can result in timing violations or reduced lifetime of the component For further information and guidelines refer to the appropriate platform design guidelines Vcc Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance ESR and the baseboard designer must assure a low interconnect resistance from the regulator EVRD or VRM pins to the LGA771 socket Bulk decoupling must be provided on the baseboard to handle large current swings The power delivery solution must insure the voltage and current specifications are met as defined in Table 2 13 For further information regarding power delivery decoupling and layout guidelines refer to the appropriate platform design guidelines Vr Decoupling Bulk decoupling must be provided on the baseboard Decoupling solutions must be sized to meet the expected load To insure optimal performance various factors associated with the power delivery solution must be considered including regulator type power plane and trace sizing and component placement A conservative decoupling solution consists of a combination of low ESR bulk capacitors and high frequency ceramic capacitors For further information regarding power delivery decoupling and layout guidelines
104. l Xeon Processor LV 5148 5138 5128 Vcc Static and Transient Tolerance Load Lines Icc A Vcc m di Maximum Vcc d Minimum Vcc Typical MD 0 100 Notes 1 The Vcc min and Vcc max loadlines represent static and transient limits Please see Section 2 13 1 for VCC overshoot specifications 2 Refer to Table 2 13 for processor VID information 3 Refer to Table 2 14 for VccStatic and Transient Tolerance 4 The load lines specify voltage limits at the die measured at the VCC DIE SENSE and VSS DIE SENSE lands and the VCC DIE SENSE2 and VSS DIE SENSE2 lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC DIE SENSE and VSS DIE SENSE lands and VCC DIE SENSE2 and VSS DIE SENSE2 lands Refer to the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for socket load line guidelines and VR implementation Please refer to the appropriate platform design guide for details on VR implementation Table 2 15 AGTL Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes Vu Input Low Voltage 0 10 0 GTLREF 0 10 V 2 4 6 Vin Input High Voltage GTLREF 0 10 Vr V r 0 10 V 3 6 Vou Output High Voltage Vrr 0 10 N A Vr V 4 6 Ron Buffer On Resistance 10 00 11 50 13 00 Q 5 lu Input Leakage Current N A N A 100 HA 7 Notes Unless otherwise noted all specifications in this table app
105. l or 3 pin PWM control See Table 8 2 for details on the 4 pin active heat sink solution connectors If the 4 pin active fan heat sink solution is connected to an older 3 pin baseboard CPU fan header it will default back to a thermistor controlled mode allowing compatibility with legacy 3 wire designs When operating in thermistor controlled mode fan RPM is automatically varied based on the TINLET temperature measured by a thermistor located at the fan inlet of the heat sink solution Dual Core Intel Xeon Processor 5100 Series Datasheet 107 intel Table 8 1 Table 8 2 Figure 8 11 Table 8 3 8 3 2 108 Boxed Processor Specifications The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it The fan power header identification and location must be documented in the suppliers platform documentation or on the baseboard itself The baseboard fan power header should be positioned within 177 8 mm 7 in from the center of the processor socket PWM Fan Frequency Specifications for 4 Pin Active CEK Thermal Solution Description Min Frequency Nominal Frequency Max Frequency Unit PWM Control Frequency Range 21 000 25 000 28 000 Hz Fan Specifications for 4 Pin Active CEK Thermal Solution de Typ Max Max Description Min Steady Steady Startup Unit 12 V 12 volt fan power supply 10 8 12 12 13 2 V IC Fan Cur
106. locks are on while the TCC is active Dual Core Intel Xeon Processor 5100 Series Datasheet m Thermal Specifications n tel 6 2 1 2 When the Thermal Monitor is enabled and a high temperature situation exists that is TCC is active the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor typically 30 50 Cycle times are processor speed dependent and will decrease as processor core frequencies increase A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases With a thermal solution designed to meet Thermal Profile A it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable A thermal solution that is designed to Thermal Profile B may cause a noticeable performance loss due to increased TCC activation Thermal Solutions that exceed Thermal Profile B will exceed the maximum temperature specification and affect the long term reliability of the processor In addition a thermal solutio
107. ludes 4 MB L2 Cache shared between the cores Intel Advanced Smart Cache 1066 1333 MHz system bus with Dual Independent Bus architecture Intel 64 Technology Intel amp 64 Intel virtualization Technology Intel Wide Dynamic Execution Intel Advanced Digital Media Boost Intel Smart Memory Access Demand Based Switching DBS with Enhanced Intel SpeedStep Technology Enhanced thermal and power management capabilities Thermal Monitor TM1 e Thermal Monitor 2 TM2 Platform Environment Control Interface PECI to monitor Digital Thermal Sensors The Dual Core Intel Xeon Processor 5100 series is designed for high performance dual processor server workstation and embedded applications Based on the Intel Core micro architecture it is binary compatible with previous Intel Architecture 1A 32 processors The Dual Core Intel Xeon Processor 5100 series are scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP Windows Server 2003 Linux and UNI X The Dual Core Intel Xeon Processor 5100 series delivers compute power at unparalleled value and flexibility for powerful servers internet infrastructure and departmental server applications The Intel Core microarchitecture and Intel Virtualization Technology deliver outstanding performance and headroom for peak internet server workloads resulting in faster re
108. lways respond to requests and the protocol itself can be relied upon to detect any transmission failures There are however certain scenarios where the PECI is know to be unresponsive Prior to a power on RESET and during RESET assertion PECI is not guaranteed to provide reliable thermal data System designs should implement a default power on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI To protect platforms from potential operational or safety issues due to an abnormal condition on PECI the Host controller should take action to protect the system from possible damaging states If the Host controller cannot complete a valid PECI transactions of GetTempO with a given PECI device over 3 consecutive failed transactions or a one second max specified interval then it should take appropriate actions to protect the corresponding device and or other system components from overheating The host controller may also implement an alert to software in the event of a critical or continuous fault condition PECI GetTempO Error Code Support The error codes supported for the processor GetTemp0 command are listed in Table 6 12 below Table 6 12 GetTempO Error Codes Error Code Description 0x8000 General sensor error 0x8002 Sensor is operational but has detected a temperature below its operational range underflow currently 309C absolute temperature
109. ly to all processor frequencies Vi is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low Viris defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above Vrr However input signal drivers must comply with the signal quality specifications This is the pull down driver resistance Refer to processor O Buffer Models for I V characteristics Measured at 0 31 V Roy min 0 225 R Ron typ 0 250 Rz Ron max 0 275 Rar GTLREF should be generated from V with a 1 tolerance resistor divider The Vr referred to in these specifications is the instantaneous Vy Specified when on die R r and Roy are turned off Viy between 0 and V Diss Qv WN Table 2 16 CMOS Signal Group and TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes VIL Input Low Voltage 0 10 0 00 0 3 V V 2 3 Vin Input High Voltage 0 7 Vir Vit Vy 0 1 V 2 VoL Output Low Voltage 0 10 0 0 1 V V 2 34 Dual Core Intel Xeon Processor 5100 Series Datasheet Electrical Specifications n tel Table 2 16 CMOS Signal Group and TAP Signal Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 Vou Output High Voltage 0 9 Vrr Vit Vtr 0 1 V 2 lot Output Low Current 1 70 N A 4 70 mA 4 lou Output High Current
110. m technology 64bitextensions In addition the Dual Core Intel Xeon Processor 5100 Series support the Execute Disable Bit functionality When used in conjunction with a supporting operating system Execute Disable allows memory to be marked as executable or non executable This feature can prevent some classes of viruses that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system Further details on Execute Disable can be found at http www intel com cd ids developer asmo na eng 149308 htm The Dual Core Intel Xeon Processor 5100 Series support Intel Virtualization Technology for hardware assisted virtualization within the processor Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions Intel Virtualization Technology is used in conjunction with Virtual Machine Dual Core Intel Xeon Processor 5100 Series Datasheet 11 intel Table 1 1 1 1 12 Introduction Monitor software enabling multiple independent software environments inside a single platform Further details on Intel Virtualization Technology can be found at http developer intel com technology vt The Dual Core Intel Xeon Processor 5100 Series are intended for high performance server and workstation systems The Dual Core Intel Xeon Processor 5100 Series support a Dual Independent Bus DIB architecture with one processor on each bus up to two process
111. m Thermal Profiles 90 Short term Thermal Profile may only be used for short term excursions to higher ambient temperatures not to exceed 360 hours per year 80 y ce n we Tc 0 741 P 60 we Tease C e ce Tc 0 741 P 45 50 Nominal Short Term 40 0 5 10 15 20 Power W 25 30 35 Notes 1 The Nominal Thermal Profile must be used for all normal operating conditions or for products that do not require NEBS Level 3 compliance Please refer to Table 6 4 for discrete points that constitute the thermal profile 2 The Short Term Thermal Profile may only be used for short term excursions to higher ambient operating temperatures not to exceed 96 hours per instance 360 hours per year and a maximum of 15 instances per year as compliant with NEBS Level 3 Please refer to Table for discrete points that constitute the thermal profile 3 Implementation of either thermal profile should result in virtually no TCC activation See Section 6 2 for details on TCC activation 4 Utilization of a thermal solution that exceeds the Short Term Thermal Profile or which operates at the Short Term Thermal Profile for a duration longer than the limits specified in Note 2 above do not meet the processor s thermal specifications and may result in permanent damage to the processor 5 Refer to the Dual Core Intel Xeon Processor LV 5138 in Embedded Applications Thermal Mechanical Des
112. m and targeted response rate The key items to take into account when settling on a fan control algorithm are the DTS sample rate whether the temperature filter is enabled how often the PECI host will poll the processor for temperature data and the rate at which fan speed is changed Depending on the designer s specific requirements the DTS sample rate and alpha beta filter may have no effect on the fan control algorithm PECI Specifications PECI Device Address The socket 0 PECI register resides at address 0x30 and socket 1 resides at 0x31 PECI Command Support The Dual Core Intel Xeon Processor 5100 Series supports the PECI commands listed in Table 6 11 Dual Core Intel Xeon Processor 5100 Series Datasheet Thermal Specifications n tel Table 6 11 Supported PECI Command Functions and Codes 6 3 2 3 6 3 2 4 Command Code Comments Function This command targets a valid PECI device address followed by zero Write Length Ping n a and zero Read Length Write Length 1 GetTemp0 0x01 Read Length 2 Returns the temperature of the processor in Domain 0 PECI Fault Handling Requirements PECI is largely a fault tolerant interface including noise immunity and error checking improvements over other comparable industry standard interfaces The PECI client is as reliable as the device that it is embedded in and thus given operating conditions that fall under the specification the PECI will a
113. mal Profile B see Figure 6 4 Table 6 10 is indicative of a constrained thermal environment that is 1U form factor Because of the reduced cooling capability represented by this thermal solution the probability of TCC activation and performance loss is increased Additionally utilization of a thermal solution that does not meet Thermal Profile B will violate the thermal specifications and may result in permanent damage to the processor Intel has developed these thermal profiles to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation Refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines for details on system thermal solution design thermal profiles and environmental considerations Dual Core Intel Xeon Processor 5100 Series Datasheet Thermal Specifications Table 6 1 intel The upper point of the thermal profile consists of the Thermal Design Power TDP defined in Table 6 8 and the associated TcAse value It should be noted that the upper point associated with Thermal Profile B x TDP and y Tcase max P TDP represents a thermal solution design point In actuality the processor case temperature will not reach this value due to TCC activation see Figure 6 4 The lower point of the thermal profile consists of x 2 P PROFILE MIN and y TCASE MAX P PROFILE MIN P pRoFILeE MIN S defined as the processor power at which
114. mal Profile apply to the B step of the Dual Core Intel Xeon Processor 5160 only Table 6 9 Dual Core Intel Xeon Processor 5160 Thermal Profile A Table Sheet 1 of 2 Power W TcasE Max C C P PRoriLE MIN A736 8 50 0 40 50 7 45 51 9 50 53 1 55 54 2 60 55 4 65 56 5 80 Dual Core Intel Xeon Processor 5100 Series Datasheet Bi Thermal Specifications n tel Table 6 9 Dual Core Intel Xeon Processor 5160 Thermal Profile A Table Sheet 2 of 2 Power W Tcase_max C 70 57 7 75 58 8 80 60 0 Table 6 10 Dual Core Intel Xeon Processor 5160 Thermal Profile B Table Power W TcasE Max C C P PRoriLE MIN B727 50 35 52 3 40 53 7 45 55 1 50 56 5 55 57 9 60 59 3 65 60 7 70 62 1 75 63 6 80 65 6 1 2 Thermal Metrology The minimum and maximum case temperatures TcAsg are specified in Table 6 2 Table 6 4 Table Table 6 7 Table 6 9 and Table 6 10 and are measured at the geometric top center of the processor integrated heat spreader IHS Figure 6 5 illustrates the location where Tcase temperature measurements should be made For detailed guidelines on temperature measurement methodology refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines and Dual Core Intel Xeon Processor LV 5138 in Embedded Applications Thermal Mechanical Design Guidelines
115. mes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input TCK TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI TDI Test Data In transfers serial test data into the processor TDI provides the serial input needed for J TAG specification support TDO TDO Test Data Out transfers serial test data out of the processor TDO provides the serial output needed for J TAG specification support TESTHI 11 0 TESTHI 11 0 must be connected to a V power source through a resistor for proper processor operation Refer to Section 2 6 for TESTHI restrictions THERMTRI P Assertion of THERMTRI P Thermal Trip indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur Measurement of the temperature is accomplished through an internal thermal sensor Upon assertion of THERMTRIP the processor will shut off its internal clocks thus halting program execution in an attempt to reduce the processor junction temperature To protect the processor its core voltage Vcc must be removed following the assertion of THERMTRIP Intel also recommends the removal of V when THERMTRIP is asserted Driving of the THERMTRIP signals is enabled within 10 us of the assertion of PWRGOOD and is disabled on de assertion of PWRGOOD Once activated THERMTRI P remains la
116. n Vcc exceeds Vcc max at specified Icc Please refer to the loadline specifications in Section 2 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VIDs found in Table 2 3 5 FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirement 6 This applies to the Dual Core Intel Xeon Processor 5160 beginning with the G step The B step specifications can be found in Table 6 8 Dual Core Intel Xeon Processor 5100 Series Datasheet 15 e n tel Thermal Specifications Figure 6 1 Dual Core Intel Xeon Processor 5100 Series Thermal Profile 70 TCASE_MAX TDP 65 o eo Y 0 385 x 440 0 Temperature C c c 50 45 20 25 30 35 40 45 50 55 60 65 Power W Notes 1 Please refer to Table 6 2 for discrete points that constitute the thermal profile 2 Refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines for system and environmental implementation details Table 6 2 Dual Core Intel Xeon Processor 5100 Series Thermal Profile Table
117. n that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines or information on designing a thermal solution For the Dual Core Intel Xeon Processor LV 5138 it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable Utilization of a thermal solution that exceeds the Short Term Thermal Profile or which operates at the Short Term Thermal Profile for a duration longer than the specified limits do not meet the processor s thermal specifications and may result in permanent damage to the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously Refer to the Dual Core Intel Xeon Processor LV 5138 in Embedded Applications Thermal Mechanical Design Guideline for information on designing a thermal solution The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines Refer to the Dual Core Intel Xeon Processor LV 5
118. nctionality nor long term reliability can be expected Moreover if a device is subjected to these conditions for any length of time then when returned to conditions within the functional operating condition limits it will either not function or its reliability will be severely degraded Although the processor contains protective circuitry to resist damage from static electric discharge precautions should always be taken to avoid high static voltages or electric fields Processor Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes 2 Vec Core voltage with respect to VSS 0 30 1 55 V Vr FSB termination voltage with respect to Vss 0 30 1 55 V TcASE Processor case temperature See See IG Chapter 6 Chapter 6 TsTORAGE Storage temperature 40 85 C 3 4 5 Notes 1 For functional operation all processor electrical signal quality mechanical and thermal specifications must be satisfied 2 Overshoot and undershoot voltage guidelines for input output and I O signals are outlined in Section 3 Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor 3 Storage temperature is applicable to storage conditions only In this scenario the processor must not receive a clock and no lands can be connected to a voltage bias Storage within these limits will not affect the long term reliability of the device For functional operation please refer to
119. nd VSS DIE SENSE lands and across the VCC DIE SENSE2 and VSS DIE SENSE2 lands with an oscilloscope set to 100 MHz bandwidth 1 5 pF maximum probe capacitance and 1 MO minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled in the scope probe 4 The processor must not be subjected to any static Vcc level that exceeds the Vcc max associated with any particular current Failure to adhere to this specification can shorten processor lifetime 5 lcc max Specification is based on maximum Vcc loadline The processor is capable of drawing Icc max for up to IO ms i 6 Icc reset iS specified while PWRGOOD and RESET are asserted 7 This specification represents the total current for GTLREF DATA and GTLREF ADD 8 V must be provided via a separate voltage source and must not be connected to Vcc This specification is measured at the land 9 Minimum VCC and maximum ICC are specified at the maximum processor case temperature TCASE shown in Figure 6 1 10 This specification refers to the total reduction of the load line due to VID transitions below the specified VID 11 Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings 12 This specification applies to the VCCPLL land 13 Baseboard bandwidth is limited to 20 MHz Dual Core Intel Xeon Processor 5100 Series Datash
120. ng MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state For additional information on the pending break event functionality including the identification of support of the feature and enable disable information refer to Vol 3 of the Intel Architecture Software Developer s Manual and the Intel Processor Identification and the CPUID Instruction application note FORCEPR The FORCEPR force power reduction input can be used by the platform to cause the Dual Core Intel Xeon Processor 5100 Series to activate the Thermal Control Circuit TCC GTLREF ADD GTLREF ADD determines the signal reference level for AGTL address and common clock input lands GTLREF ADD is used by the AGTL receivers to determine if a signal is a logical O or a logical 1 GTLREF DATA GTLREF DATA determines the signal reference level for AGTL data input lands GTLREF DATA is used by the AGTL receivers to determine if a signal is a logical 0 or a logical 1 HIT HITM 1 0 1 0 HIT Snoop Hit and HITM Hit Modified convey transaction snoop operation results Any FSB agent may assert both HIT and HITM together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR
121. nimum Maximum Frequency Power Design Power TCASE TCASE Notes w w C C Launch to FMB 90 65 5 See Figure 6 4 1 2 3 4 5 6 Table 6 9 7 Table 6 10 Notes 1 These values are specified at Vcc max for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and Icc combination wherein Vcc exceeds Vcc max at specified Icc Please refer to the loadline specifications in Section 2 2 Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at maximum Tease 3 These specifications are based pre silicon estimates and simulations These specifications will be updated with characterized data from silicon measurements in a future release of this document 4 Power specifications are defined at all VI Ds found in Table 2 3 The processor may be shipped under multiple VI Ds for each frequency Dual Core Intel Xeon Processor 5100 Series Datasheet 79 intel 5 6 Thermal Specifications FMB or Flexible Motherboard guidelines provide a design target for meeting all planned processor frequency requirements These values only apply to the B step of the Dual Core Intel Xeon Processor 5160 For the G step specifications please refer to Table 6 1 Figure 6 4 Dual Core I ntel 8 Xeon Processor 5160 Thermal Profiles A and B Tem
122. oL 0 25 V4 High impedance state liai leakage to Vy N A 50 HA 2 Vieak Vor High impedance leakage leak to GND N A 10 HA 2 Vieak Vou Cpus Bus capacitance N A 10 pF Signal noise immunit Vnoise Sabe 300 MHz i 0 1 Myr N A Vp p Note 1 V supplies the PECI interface PECI behavior does not affect V min max specifications 2 The leakage specification applies to powered devices on the PECI bus Dual Core Intel Xeon Processor 5100 Series Datasheet 2 10 2 Figure 2 1 2 11 Note 2 12 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use Figure 2 1 as a guide for input buffer design Input Device Hysteresis Aie Maximum Vp Minimum Vp Minimum Valid Input Hysteresis Signal Range Maximum Vy Minimum VN PECI Ground Mixing Processors Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency core frequency power segments and have the same internal cache sizes Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel Combining processors from different power segments is also not supported Processors within a system must operate at the same frequency per bits 12 8 of the CLOCK FLEX MAX MSR
123. ocessor Package Drawing Sheet 3 of 3 Mechanical Specifications THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION TIS DISCLOSED IN CONFIDENCE ANDITS CONTENTS MAY NOT BE DISCLOSED REPRODUCED DISPLAYED OR MODIFED WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION mur 000000000000000 00000000d0000000 900000000000000 00000000Q0000000 oooooooooQgoooooo Oooooocoooodoooooo OoooooOoOoOOQgOooOOooOo 9900000000000000 9699 ach OOOOODOOOOOOOOO OOOOODOOOOOOOOOQ OOOOODOOOOOOcOOO OOOOODOOOOOOOOOQ 90000DO0000000000 OcOOOOCOOOOOOcOOCO 90900D0000000000 000000000000000 000000000 9009000909 060060000 OO00090000 000000000 a LoooogoooQ 909000000 9 000000000 900000000 969000000 ooooo0000 660000000 909990000 000000000 900000000 o00000000 QOOOCOOOO oooep200000 i ens OO00000000 000090000 000000095 o OOoOooCcOOOO OOoOoOOcOOOOOOOOOOO og00090000000000090 OOoooOcOoOoOOOOOOOOO 0000000000000000 9 9999990990099 0000000000000000 o 000000000000000000000000000800000 OOOOCOOOOOOOCOOCOOQOOOOCOCOOOCOOOOOO 900000 OOOO0O0CODOOOOOOSO 00000000000000 9Q0999999990900909 0000000000000000 A r us 15 MAXNIONMME COMPONENT HEGET spe Tow
124. ocessor is in Stop Grant state PBE will be asserted if there is any pending interrupt latched within the processor Pending interrupts that are blocked by the EFLAGS IF bit being clear will still cause assertion of PBE Assertion of PBE indicates to system logic that it should return the processor to the Normal state Extended HALT Snoop or HALT Snoop State Stop Grant Snoop State The Extended HALT Snoop state is used in conjunction with the Extended HALT state If the Extended HALT state is not enabled in the BIOS the default Snoop state entered will be the HALT Snoop state Refer to the sections below for details on HALT Snoop state Stop Grant Snoop state and Extended HALT Snoop state HALT Snoop State Stop Grant Snoop State The processor will respond to snoop or interrupt transactions on the front side bus while in Stop Grant state or in HALT state During a snoop or interrupt transaction the processor enters the HALT Grant Snoop state The processor will stay in this state until the snoop on the front side bus has been serviced whether by the processor or another agent on the front side bus or the interrupt has been latched After the snoop is serviced or the interrupt is latched the processor will return to the Stop Grant state or HALT state as appropriate Extended HALT Snoop State The Extended HALT Snoop state is the default Snoop state when the Extended HALT state is enabled via the BIOS The processor will remain in the lo
125. of the processor by changing the bus to core frequency ratio and voltage This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system The Dual Core Intel Xeon Processor 5100 Series has hardware logic that coordinates the requested voltage VID between the processor cores The highest voltage that is requested for either of the processor cores is selected for that processor package Note that the front side bus is not altered only the internal core frequency is changed In order to run at reduced power consumption the voltage is altered in step with the bus ratio The following are key features of Enhanced Intel SpeedStep Technology Multiple voltage frequency operating points provide optimal performance at reduced power consumption Voltage frequency selection is software controlled by writing to processor MSR s Model Specific Registers thus eliminating chipset dependency f the target frequency is higher than the current frequency Vcc is incremented in steps 12 5 mV by placing a new value on the VID signals and the processor shifts to the new frequency Note that the top frequency for the processor can not be exceeded If the target frequency is lower than the current frequency the processor shifts to the new frequency and Vcc is then decremented in steps 12 5 mV by changing the target VID through the VID signals D
126. ommon Clk Input D21 VSS Power Other E30 VIT Power Other D22 D46 Source Sync Input Output E4 HITM Common Clk Input Output D23 VCCPLL Power Other Input E5 RESERVED D24 vss Power Other E6 RESERVED D25 VTT Power Other E7 RESERVED D26 VTT Power Other E8 VSS Power Other D27 VTT Power Other E9 D19 Source Sync Input Output D28 VTT Power Other F1 VSS Power Other D29 VTT Power Other F10 VSS Power Other 60 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 2 Land Listing by Land Number Table 4 2 Land Listing by Land Number Sheet 13 of 20 Sheet 14 of 20 uc Pin Name N a Direction Ne Pin Name Baker Direction F11 D23 Source Sync Input Output G20 DSTBN2 Source Sync Input Output F12 D24 Source Sync Input Output G21 D44 Source Sync Input Output F13 VSS Power Other G22 D47 Source Sync Input Output F14 D28 Source Sync Input Output G23 RESET Common Clk Input F15 D30 Source Sync Input Output G24 TESTHI06 Power Other Input F16 VSS Power Other G25 TESTHI03 Power Other Input F17 D37 Source Sync Input Output G26 TESTHIO5 Power Other Input F18 D38 Source Sync Input Output G27 TESTHI04 Power Other Input F19 VSS Power Other G28 BCLK1 Clk Input F2 RESERVED G29 BSELO Power Other Output F20 D41 Source
127. on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal and must connect the appropriate pins of all processor FSB agents Notes LINT 1 0 LL_ID 1 0 LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all FSB agents When the APIC functionality is disabled the LINTO INTR signal becomes INTR a maskable interrupt request signal and LINT1 NMI becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous These signals must be software configured via BIOS programming of the APIC register space to be used either as NMI INTR or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration The LL ID 1 0 signals are used to select the correct loadline slope for the processor These signals are not connected to the processor die A logic 0 is pulled to ground and a logic 1 is a no connect on the Dual Core Intel Xeon Processor 5100 Series package LOCK 1 0 LOCK indicates to the system that a transaction must occur atomically This signal must connect the appropriate pins of all processor FSB agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbi
128. onally both processor cores must be in the Stop Grant state before the deassertion of STPCLK Since the AGTL signal pins receive power from the front side bus these pins should not be driven allowing the level to return to Vrr for minimum power drawn by the termination resistors in this state In addition all other input pins on the front side bus should be driven to the inactive state BINIT will not be serviced while the processor is in Stop Grant state The event will be latched and can be serviced by software upon exit from the Stop Grant state RESET will cause the processor to immediately initialize itself but the processor will stay in Stop Grant state A transition back to the Normal state will occur with the de assertion of the STPCLK signal A transition to the Grant Snoop state will occur when the processor detects a snoop on the front side bus see Section 7 2 4 1 Dual Core Intel Xeon Processor 5100 Series Datasheet Features 7 2 4 7 2 4 1 7 2 4 2 7 3 Note intel While in the Stop Grant state SMI INIT BINIT and LINT 1 0 will be latched by the processor and only serviced when the processor returns to the Normal state Only one occurrence of each event will be recognized upon return to the Normal state While in Stop Grant state the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus The PBE signal can be driven when the pr
129. onitoring devices A topology diagram is given in Figure 6 7 The PECI bus offers A wide speed range from 2 Kbps to 2 Mbps CRC check byte used to efficiently and automatically confirm accurate data delivery Synchronization at the beginning of every message minimizes device timing accuracy requirements The Platform Environment Control Interface PECI bus uses a single wire for self clocking and data transfer and requires no additional control lines The physical layer is a self clocked one wire bus that begins each bit with a driven rising edge from an idle level near zero volts The duration of the signal driven high depends on whether the bit value is a logic 0 or logic 1 PECI also includes variable data transfer rate established with every message The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components Bus speed error checking and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information The PECI interface is disabled by default and must be enabled through BIOS by setting PECI EN bit 0 of Model Specific Register PECI_CTL at address 05AO0h to 1 Dual Core Intel Xeon Processor 5100 Series Datasheet Thermal Specifications Figure 6 7 6 3 1 1 PECI Topology Processor Socket 0 PECI
130. or sockets in a system The DIB architecture provides improved performance by allowing increased FSB speeds and bandwidth The Dual Core Intel9 Xeon Processor 5100 Series are packaged in an FC LGA6 Land Grid Array package with 771 lands for improved power delivery It utilizes a surface mount LGA771 socket that supports Direct Socket Loading DSL Dual Core I ntel Xeon Processor 5100 Series of Processor L1 Cache L2 Advanced Front Side Bus Package Cores Transfer Cache Frequencies 9 32 KB instruction 1333 MHz FC LGA6 2 4 MB shared 32 KB data 1066 MHz 771 Lands The Dual Core Intel Xeon Processor 5100 Series based platforms implement independent core voltage Vcc power planes for each processor FSB termination voltage Vr is shared and must connect to all FSB agents The processor core voltage utilizes power delivery guidelines specified by VRM EVRD 11 0 and its associated load line see Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines for further details VRM EVRD 11 0 will support the power requirements of all frequencies of the Dual Core Intel Xeon Processor 5100 Series Refer to the appropriate platform design guidelines for implementation details The Dual Core Intel Xeon Processor 5100 Series support 1333 MHz Front Side Bus operation The Dual Core Intel Xeon Processor LV 5138 and Dual Core Intel Xeon Processor LV 5128 support 1066MHz Front Side Bu
131. oth component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS Typical system level thermal solutions may consist of system fans combined with ducting and venting This section provides data necessary for developing a complete thermal solution For more information on designing a component level thermal solution refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines and Dual Core Intel Xeon Processor LV 5138 in Embedded Applications Thermal Mechanical Design Guidelines The boxed processor will ship with a component thermal solution Refer to Section 8 for details on the boxed processor For the Dual Core Intel Xeon Processor LV 5128 follow the Dual Core Intel Xeon Processor LV 5148 Thermal Profile Thermal Specifications To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature TcAsg specifications as defined by the applicable thermal profile Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system For more details on thermal solution design please refer to the processor thermal mechanical design guidelines The Dual Core Intel Xeon Processor LV 5148 5138 5128 implem
132. ower Other AK17 VSS Power Other AL26 VCC Power Other AK18 VCC Power Other AL27 VSS Power Other AK19 VCC Power Other AL28 VSS Power Other AK2 VSS Power Other AL29 VCC Power Other AK20 VSS Power Other AL3 VSS Power Other AK21 VCC Power Other AL30 VCC Power Other AK22 VCC Power Other AL4 VID5 Power Other Output AK23 VSS Power Other AL5 VID1 Power Other Output AK24 VSS Power Other AL6 VID3 Power Other Output AK25 VCC Power Other AL7 VSS DIE SENSE2 Power Other AK26 VCC Power Other AL8 VCC DIE SENSE2 Power Other AK27 VSS Power Other E ALY VCC Power Other AK28 VSS Power Other AM1 VSS Power Other AK29 VSS Power Other AM10 VSS Power Other AK3 RESERVED AM11 VCC Power Other AK30 VSS Power Other AM12 VCC Power Other AK4 VIDA Power Other Output AM13 VSS Power Other AK5 VSS Power Other AM14 VCC Power Other AK6 FORCEPR CMOS Async Input AM15 VCC Power Other AK7 VSS Power Other AM16 VSS Power Other AK8 VCC Power Other AM17 VSS Power Other AK9 VCC Power Other AM18 VCC Power Other AL1 RESERVED AM19 VCC Power Other AL10 VSS Power Other AM2 RESERVED AL11 VCC Power Other AM20 VSS Power Other AL12 VCC Power Other AM21 VCC Power Other AL13 VSS Power Other AM22 VCC Power Other AL14 VCC Power Other AM23 VSS Power Other AL15 VCC Power Other AM24 VSS Power Other AL16 VSS Power Other AM25 VCC Power Other 58
133. ower Other VCC AG8 Power Other VCC AK8 Power Other VCC AG9 Power Other VCC AK9 Power Other VCC AH11 Power Other VCC AL11 Power Other VCC AH12 Power Other VCC AL12 Power Other VCC AH14 Power Other VCC AL14 Power Other VCC AH15 Power Other VCC AL15 Power Other VCC AH18 Power Other VCC AL18 Power Other VCC AH19 Power Other VCC AL19 Power Other VCC AH21 Power Other VCC AL21 Power Other VCC AH22 Power Other VCC AL22 Power Other VCC AH25 Power Other VCC AL25 Power Other VCC AH26 Power Other VCC AL26 Power Other VCC AH27 Power Other VCC AL29 Power Other VCC AH28 Power Other VCC AL30 Power Other VCC AH29 Power Other VCC AL9 Power Other VCC AH30 Power Other VCC AM11 Power Other VCC AH8 Power Other VCC AM12 Power Other VCC AH9 Power Other VCC AM14 Power Other VCC AJ11 Power Other VCC AM15 Power Other VCC AJ12 Power Other VCC AM18 Power Other VCC AJ14 Power Other VCC AM19 Power Other VCC AJ15 Power Other VCC AM21 Power Other VCC AJ18 Power Other VCC AM22 Power Other VCC AJ19 Power Other VCC AM25 Power Other VCC AJ21 Power Other VCC AM26 Power Other VCC AJ22 Power Other VCC AM29 Power Other VCC AJ25 Power Other VCC AM30 Power Other VCC AJ26 Power Other VCC AM8 Power Other VCC AJ8 Power Other VCC AM9 Power Other VCC AJ9 Power Other VCC AN11 Power Other VCC AK11 Power Other VCC AN12 Power Other VCC AK12 Power Other VCC AN14 Power Other VCC AK14 Powe
134. ower Other VSS AA30 Power Other VSS AF25 Power Other VSS AA6 Power Other VSS AF26 Power Other VSS AA7 Power Other VSS AF27 Power Other VSS AB1 Power Other VSS AF28 Power Other Dual Core Intel Xeon Processor 5100 Series Datasheet 51 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 15 of 20 Sheet 16 of 20 Pin Name Ne eco au Direction Pin Name n PE 1 NE Direction VSS AF29 Power Other VSS AK17 Power Other VSS AF3 Power Other VSS AK2 Power Other VSS AF30 Power Other VSS AK20 Power Other VSS AF6 Power Other VSS AK23 Power Other VSS AF7 Power Other VSS AK24 Power Other VSS AG10 Power Other VSS AK27 Power Other VSS AG13 Power Other VSS AK28 Power Other VSS AG16 Power Other VSS AK29 Power Other VSS AG17 Power Other VSS AK30 Power Other VSS AG20 Power Other VSS AK5 Power Other VSS AG23 Power Other VSS AK7 Power Other VSS AG24 Power Other VSS AL10 Power Other VSS AG7 Power Other VSS AL13 Power Other VSS AH1 Power Other VSS AL16 Power Other VSS AH10 Power Other VSS AL17 Power Other VSS AH13 Power Other VSS AL20 Power Other VSS AH16 Power Other VSS AL23 Power Other VSS AH17 Power Other VSS AL24 Power Other VSS AH20 Power Other VSS AL27 Power Other VSS AH23 Power Other VSS AL28 Power Othe
135. perature C TCASE_MAX_B TDP is a thermal solution design point In actuality units will not significantly exceed TCASE MAX A due to TCC activation TCASE MAX BQTDP TCASE MAX AQTDP Thermal Profile B Y 0 282 x 442 4 Thermal Profile A Y 0 231 x 441 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Power W Notes 1 Thermal Profile A is representative of a volumetrically unconstrained platform Please refer to Table 6 9 for discrete points that constitute the thermal profile 2 Implementation of Thermal Profile A should result in virtually no TCC activation Furthermore utilization of thermal solutions that do not meet processor Thermal Profile A will result in increased probability of TCC activation and may incur measurable performance loss See Section 6 2 for details on TCC activation 3 Thermal Profile B is representative of a volumetrically constrained platform Please refer to Table 6 10 for discrete points that constitute the thermal profile 4 Implementation of Thermal Profile B will result in increased probability of TCC activation and measurable performance loss Furthermore utilization of thermal solutions that do not meet Thermal Profile B do not meet the processor s thermal specifications and may result in permanent damage to the processor 5 Refer to the Dual Core Intel Xeon Processor 5100 Series Thermal Mechanical Design Guidelines for system and environmental implementation details 6 This Ther
136. perature of 35 C Following these guidelines will allow the designer to meet Dual Core Intel Xeon Processor 5100 Series Thermal Profile and conform to the thermal requirements of the processor 1U Passive 3U Active Combination Heat Sink Solution Pedestal Active The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting It may be still be necessary to implement some form of chassis air guide or air duct to meet the TLA temperature of 40 C depending on the pedestal chassis layout Also while the active thermal solution design will mechanically fit into a 2U volumetric it may not provide adequate airflow This is due to the requirement of additional space at the top of the thermal solution to allow sufficient airflow into the heat sink fan Use of the active configuration in a 2U rackmount chassis is not recommended It is recommended that the ambient air temperature outside of the chassis be kept at or below 35 C The air passing directly over the processor thermal solution should not be preheated by other system components Meeting the processor s temperature specification is the responsibility of the system integrator 2U Passive Heat Sink Solution 2U Rack or Pedestal In the 2U passive configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 27 cfm at 0 182 in H20 45 9
137. pins are used to support automatic selection of power supply voltages Vcc These are CMOS signals that are driven by the processor and must be pulled up through a resistor Conversely the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid The VID pins are needed to support processor voltage specification variations See Table 2 3 for definitions of these pins The VR must supply the voltage that is requested by these pins or disable itself VID SELECT VID SELECT is an output from the processor which selects the appropriate VID table for the Voltage Regulator This signal is not connected to the processor die This signal is a no connect on the Dual Core Intel Xeon Processor 5100 Series package VSS DIE SENSE VSS DIE SENSE2 VSS DIE SENSE and VSS DIE SENSE2 provides an isolated low impedance connection to the processor core power and ground This signal should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details The FSB termination voltage input pins Refer to Table 2 13 for further details VIT OUT The VTT OUT signals are included in order to provide a local V for some signals that require termination to V on the motherboard VIT SEL The VTT SEL signal is used to select the correct V4
138. r Network Telecomminications Equipment GR 1089 CORE http telecom info telcordia com Note Dual Core Intel Xeon Processor 5100 Series Datasheet Contact your Intel representative for the latest revision of these documents 15 16 Introduction Dual Core Intel Xeon Processor 5100 Series Datasheet Bi Electrical Specifications n tel 2 2 1 2 2 Electrical Specifications Front Side Bus and GTLREF Most Dual Core Intel Xeon Processor 5100 Series FSB signals uses Assisted Gunning Transceiver Logic AGTL signaling technology This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates AGTL buffers are open drain and require pull up resistors to provide the high logic level and termination AGTL output buffers differ from GTL buffers with the addition of an active PMOS pull up transistor to assist the pull up resistors during the first clock of a low to high voltage transition Platforms implement a termination voltage level for AGTL signals defined as V m Because platforms implement separate power planes for each processor and chipset separate Vcc and Vy supplies are necessary This configuration allows for improved noise tolerance as processor frequency increases Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with pre
139. r VSS AH24 Power Other VSS AL3 Power Other VSS AH3 Power Other VSS AM1 Power Other VSS AH6 Power Other VSS AM10 Power Other VSS AH7 Power Other VSS AM13 Power Other VSS AJ10 Power Other VSS AM16 Power Other VSS AJ13 Power Other VSS AM17 Power Other VSS AJ16 Power Other VSS AM20 Power Other VSS AJ17 Power Other VSS AM23 Power Other VSS AJ20 Power Other VSS AM24 Power Other VSS AJ23 Power Other VSS AM27 Power Other VSS AJ24 Power Other VSS AM28 Power Other VSS AJ27 Power Other VSS AM4 Power Other VSS AJ28 Power Other vss AM7 Power Other VSS AJ29 Power Other VSS AN1 Power Other VSS AJ30 Power Other VSS AN10 Power Other VSS AJ4 Power Other VSS AN13 Power Other VSS AJ7 Power Other VSS AN16 Power Other VSS AK10 Power Other VSS AN17 Power Other VSS AK13 Power Other VSS AN2 Power Other VSS AK16 Power Other VSS AN20 Power Other 52 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 17 of 20 Sheet 18 of 20 Pin Name Ne M ou m Direction Pin Name Ne lu Direction VSS AN23 Power Other VSS F13 Power Other VSS AN24 Power Other VSS F16 Power Other VSS B1 Power Other VSS F19 Power Other VSS B11 Power Othe
140. r Other C22 VSS Power Other D4 HIT Common Clk Input Output C23 RESERVED D5 vss Power Other C24 VSS Power Other D6 VSS Power Other C25 VTT Power Other D7 D20 Source Sync Input Output C26 VTT Power Other D8 D12 Source Sync Input Output C27 VTT Power Other D9 VSS Power Other C28 VTT Power Other E1 RESERVED Power Other C29 VTT Power Other E10 D21 Source Sync Input Output C3 LOCK Common Clk Input Output E11 VSS Power Other C30 VIT Power Other E12 DSTBP1 Source Sync Input Output C4 VSS Power Other E13 D263 Source Sync Input Output C5 DO1 Source Sync Input Output E14 VSS Power Other C6 DO3 Source Sync Input Output E15 D33 Source Sync Input Output C7 VSS Power Other E16 D34 Source Sync Input Output C8 DSTBNO Source Sync Input Output E17 vss Power Other C9 RESERVED E18 D39 Source Sync Input Output D1 RESERVED E19 D40 Source Sync Input Output D10 D22 Source Sync Input Output E2 VSS Power Other D11 D15 Source Sync Input Output E20 VSS Power Other D12 VSS Power Other E21 D42 Source Sync Input Output D13 D25 Source Sync Input Output E22 D45 Source Sync Input Output D14 RESERVED E23 RESERVED D15 vss Power Other E24 RESERVED D16 RESERVED E25 VSS Power Other D17 D49 Source Sync Input Output E26 VSS Power Other D18 VSS Power Other E27 VSS Power Other D19 DBI 2 Source Sync Input Output E28 VSS Power Other D2 ADS Common Clk Input Output E29 VSS Power Other D20 D48 Source Sync Input Output E3 TRDY C
141. r Other VCC AN15 Power Other VCC AK15 Power Other VCC AN18 Power Other VCC AK18 Power Other VCC AN19 Power Other VCC AK19 Power Other VCC AN21 Power Other VCC AK21 Power Other VCC AN22 Power Other VCC AK22 Power Other VCC AN25 Power Other VCC AK25 Power Other VCC AN26 Power Other Dual Core Intel Xeon Processor 5100 Series Datasheet 49 intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 11 of 20 Sheet 12 of 20 Pin Name um due AM Direction Pin Name ipa ieee 1 NE Direction VCC AN8 Power Other VCC M30 Power Other VCC AN9 Power Other VCC M8 Power Other VCC J10 Power Other VCC N23 Power Other VCC J11 Power Other VCC N24 Power Other VCC J12 Power Other VCC N25 Power Other VCC J13 Power Other VCC N26 Power Other VCC J14 Power Other VCC N27 Power Other VCC J15 Power Other VCC N28 Power Other VCC J18 Power Other VCC N29 Power Other VCC J19 Power Other VCC N30 Power Other VCC J20 Power Other VCC N8 Power Other VCC J21 Power Other VCC P8 Power Other VCC J22 Power Other VCC R8 Power Other VCC J23 Power Other VCC T23 Power Other VCC J24 Power Other VCC T24 Power Other VCC J25 Power Other VCC T25 Power Other VCC J26 Power Other VCC T26 Power Other VCC J27 Power Other VCC T27 Power Other VCC J28 Power Other VCC T28 Power Other VCC J29 Power O
142. r VSS F22 Power Other VSS B14 Power Other VSS F4 Power Other VSS B17 Power Other VSS F7 Power Other VSS B20 Power Other VSS G1 Power Other VSS B24 Power Other VSS H10 Power Other VSS B5 Power Other vss H11 Power Other VSS B8 Power Other VSS H12 Power Other VSS C10 Power Other VSS H13 Power Other VSS C13 Power Other VSS H14 Power Other VSS C16 Power Other VSS H17 Power Other VSS C19 Power Other VSS H18 Power Other VSS C22 Power Other VSS H19 Power Other VSS C24 Power Other VSS H20 Power Other VSS C4 Power Other vss H21 Power Other VSS C7 Power Other VSS H22 Power Other VSS D12 Power Other VSS H23 Power Other VSS D15 Power Other VSS H24 Power Other VSS D18 Power Other VSS H25 Power Other VSS D21 Power Other VSS H26 Power Other VSS D24 Power Other VSS H27 Power Other VSS D3 Power Other VSS H28 Power Other VSS D5 Power Other VSS H29 Power Other VSS D6 Power Other VSS H3 Power Other VSS D9 Power Other VSS H6 Power Other VSS E11 Power Other VSS H7 Power Other VSS E14 Power Other VSS H8 Power Other VSS E17 Power Other VSS H9 Power Other vss E2 Power Other VSS J4 Power Other VSS E20 Power Other VSS J7 Power Other VSS E25 Power Other VSS K2 Power Other VSS E26 Power Other VSS K5 Power Other VSS E27 Power Other VSS K7 Power Other VSS E28 Power Other VSS L23 Power Other VSS E29 Power Other VSS L24 Power Other VSS E8 Power Other VSS L25 Power Other VSS F1 Power Other VSS L26 Power Other VSS F10 Power Other VSS L27 Power Other Dual Core Intel X
143. rent Draw N A 1 1 25 1 5 A SENSE SENSE frequency 2 2 2 2 Pulses per fan revolution Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution PIN 3 PIN4 PIN 2 oe Fan Cable Connector Pin Out for 4 Pin Active CEK Thermal Solution Pin Number Signal Color 1 Ground Black 2 Power 12 V Yellow 3 Sense 2 pulses per revolution Green 4 Control 21 KHz 28 KHz Blue Boxed Processor Cooling Requirements As previously stated the boxed processor will be available in two product configurations Each configuration will require unique design considerations Meeting the processor s temperature specifications is also the function of the thermal design of the entire system and ultimately the responsibility of the system integrator The processor temperature specifications are found in Section 6 of this document Dual Core Intel Xeon Processor 5100 Series Datasheet Boxed Processor Specifications n tel 8 3 2 1 8 3 2 2 8 3 2 3 8 4 1U Passive 3U Active Combination Heat Sink Solution 1U Rack Passive In the 1U configuration it is assumed that a chassis duct will be implemented to provide a minimum airflow of 15 cfm at 0 38 in H20 25 5 m 3 hr at 94 6 Pa of flow impedance The duct should be carefully designed to minimize the airflow bypass around the heatsink It is assumed that a 40 C TLA is met This requires a superior chassis design to limit the TRISE at or below 5 C with an external ambient tem
144. res a computer system with a processor chipset BIOS OS device drivers and applications enabled for Intel EM64T Processor will not operate including 32 bit operation without an Intel EM64T enabled BIOS Performance will vary depending on your hardware and software configurations Intel EM64T enabled OS BIOS device drivers and applications may not be available Check with your vendor for more information Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order Intel Pentium Intel Xeon Intel SpeedStep Intel Extended Memory 64 Technology Intel Virtualization Technology and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries Other names and brands may be claimed as the property of others Copyright 2007 Intel Corporation 2 Dual Core Intel Xeon Processor 5100 Series Datasheet Contents qz H MTETLTET 9 1 ln tP O di Cti Ol cc Lm 11 LI I dh 12 al aba v gt o gt _ _ _ rr_eeaeennnt 14 1 3 References esee re ere EE recorder du i Abest emb iege br n bese a iat Ri e Lg 14 2 Electrical Speciflca tO cm P bia nian kan Mak na AASE na india dran cak nan 17 2 1 Front Side B s a d GTUREP ici uc yin naa view Y NERR TRE RR kd newa W WU WER WA kra 17 2 2 Power and Ground Land Ss a xx kanan ln ay ir erm entm xr baley dx ERR xn
145. rocessor 5100 Series Datasheet Introduction intel Dual Core I ntel Xeon Processor 5100 Series Intel 64 bit microprocessor intended for dual processor servers and workstations The Dual Core Intel Xeon Processor 5100 Series are based on Intel s 65 nanometer process in the FC LGA6 package with two processor cores For this document processor is used as the generic term for the Dual Core Intel Xeon Processor 5100 Series Dual Core I ntel amp Xeon Processor LV 5148 Dual Core Intel Xeon Processor LV 5138 and Dual Core Intel Xeon Processor LV 5128 Intel 64 bit microprocessor intended for dual processor server blades and embedded servers requiring higher case temperatures The Dual Core Intel Xeon Processor LV 5148 Dual Core Intel Xeon Processor LV 5138 and Dual Core Intel Xeon Processor LV 5128 are lower voltage lower power version of the Dual Core Intel Xeon Processor 5100 Series For this document Dual Core Intel Xeon Processor LV 5148 5138 5128 is used to call out specifications that are unique to the Dual Core Intel Xeon Processor LV 5148 5138 5128 SKU Dual Core I ntel Xeon Processor 5160 A performance optimized version of the Dual Core Intel Xeon Processor 5100 Series For this document Dual Core Intel Xeon Processor 5160 is used to call out specifications that are unique to the Dual Core Intel Xeon Processor 5160 SKU FC LGA6 Flip Chip Land Grid Array Package
146. ropriate platform design guidelines for details on implementing the FORCEPR signal feature Dual Core Intel Xeon Processor 5100 Series Datasheet 85 e n tel Thermal Specifications 6 3 6 3 1 Note 86 THERMTRI P Signal Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRI P definition in Table 5 1 At this point the FSB signal THERMTRIP will go active and stay active as described in Table 5 1 THERMTRIP activation is independent of processor activity and does not generate any bus cycles Intel also recommends the removal of Vmr Platform Environment Control I nterface PECI I ntroduction The introduction of the Dual Core Intel Xeon Processor 5100 Series marks the transition from thermal diodes to digital thermal sensors for fan speed control Digital Thermal Sensors DTS are on die analog to digital temperature converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature Data from the DTS are processed and stored in a processor register which is queried through the Platform Environment Control Interface PECI PECI is a proprietary one wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal m
147. s are for the package only and do not include the limits of the processor socket Package I nsertion Specifications The Dual Core Intel Xeon Processor 5100 Series can be inserted and removed 15 times from an LGA771 socket Processor Mass Specifications The typical mass of the Dual Core Intel Xeon Processor 5100 Series is 21 5 grams 0 76 oz This includes all components which make up the entire processor product Dual Core Intel Xeon Processor 5100 Series Datasheet Mechanical Specifications 3 7 Processor Materials The Dual Core Intel Xeon Processor 5100 Series is assembled from several components The basic material properties are described in Table 3 3 Table 3 3 Processor Materials Component Material Integrated Heat Spreader IHS Nickel over copper Substrate Fiber reinforced resin Substrate Lands Gold over nickel 3 8 Processor Land Coordinates Figure 3 5 and Figure 3 6 show the top and bottom view of the processor land coordinates respectively The coordinates are referred to throughout the document to identify processor lands Figure 3 5 Processor Land Coordinates Top View intel Voc Vss 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 LAE 54321 poge uoommorczarzzumac sz Socket 771 Quadrants Top View Li V4 Clocks 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1
148. s operation The FSB utilizes a split transaction deferred reply protocol and Source Synchronous Transfer SST of address and data to improve performance The processor transfers data four times per bus clock 4X data transfer rate as in AGP 4X Along with the 4X data bus the address bus can deliver addresses two times per bus clock and is referred to as a double clocked or a 2X address bus In addition the Request Phase completes in one clock cycle The FSB is also used to deliver interrupts Signals on the FSB use Assisted Gunning Transceiver Logic AGTL level voltages Section 2 1 contains the electrical specifications of the FSB while implementation details are fully described in the appropriate platform design guidelines refer to Section 1 3 Terminology A 3t symbol after a signal name refers to an active low signal indicating a signal is in the asserted state when driven to a low level For example when RESET is low a reset has been requested Conversely when NMI is high a nonmaskable interrupt has occurred In the case of signals where the name does not imply an active state but describes part of a binary sequence such as address or data the symbol implies that the signal is inverted For example D 3 0 HLHL refers to a hex A and D 3 0 LHLH also refers to a hex A H High logic level L Low logic level Commonly used terms are explained here for clarification Dual Core Intel Xeon P
149. sis pan Notes 1 The heat sinks represented in these images are for reference only and may not represent the final boxed processor heat sinks 2 The screws springs and standoffs will be captive to the heat sink This image shows all of the components in an exploded view 3 Itis intended that the CEK spring will ship with the base board and be pre attached prior to shipping Dual Core Intel Xeon Processor 5100 Series Datasheet m Boxed Processor Specifications n te 8 2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor 8 2 1 Boxed Processor Heat Sink Dimensions CEK The boxed processor will be shipped with an unattached thermal solution Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling The physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 8 4 through Figure 8 8 Figure 8 9 through Figure 8 10 are the mechanical drawings for the 4 pin board fan header and 4 pin connector used for the active CEK fan heat sink solution Dual Core Intel Xeon Processor 5100 Series Datasheet 99 Boxed Processor Specifications 3 L l 8 7Q3MOT1V SIN3NOdMO GUYOGH3HION ON 100d33W YIONI4 QBVOH 9NIUJS X32 o WO 12141538 1H9 3H 1N3NOdNOO QUYOQN3HLON XVW WNIT JRO Q S118 25056 vo vis uw armo dieti set Pul 03N011Y 1303214 LN3NOdNOD QNYOGNJHLON
150. sor 5100 Series Datasheet Debug Tools Specifications n tel 9 9 1 Note 9 2 9 2 1 9 3 Debug Tools Specifications Please refer to the Debug Port Design Guide for UP DP Systems and the appropriate platform design guidelines for information regarding debug tool specifications Section 1 3 provides collateral details Debug Port System Requirements The Dual Core Intel Xeon Processor 5100 Series debug port is the command and control interface for the In Target Probe ITP debugger The ITP enables run time control of the processors for system debug The debug port which is connected to the FSB is a combination of the system J TAG and execution signals There are several mechanical electrical and functional constraints on the debug port that must be followed The mechanical constraint requires the debug port connector to be installed in the system with adequate physical clearance Electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor While the J TAG signals operate at a maximum of 75 MHz the execution signals operate at the common clock FSB frequency The functional constraint requires the debug port to use the J TAG system via a handshake and multiplexing scheme In general the information in this chapter may be used as a basis for including all run control tools in Dual Core Intel Xeon Processor 5100 Series based system designs including tools from vendors
151. sponse times support for more users and improved scalability 10 Features Dual Core Intel Xeon Processor 5100 Series Datasheet intel l Introduction The Dual Core Intel Xeon Processor 5100 Series are 64 bit server workstation processors utilizing two Intel microarchitecture cores These processors are based on Intel s 65 nanometer process technology combining high performance with the power efficiencies of a low power microarchitecture The Dual Core Intel Xeon Processor 5100 Series maintain the tradition of compatibility with A 32 software Some key features include on die 32 KB Level 1 instruction and data caches and 4 MB Level 2 cache with Advanced Transfer Cache Architecture The processors Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache requests occurs resulting in reduced bus cycle penalties and improved performance The 1333 MHz Front Side Bus FSB is a quad pumped bus running off a 333 MHz system clock making 10 66 GBytes per second data transfer rates possible Some lower speed SKU s are available which support a 1066 MHz Front Side Bus FSB This is a quad pumped bus running off a 266 MHz system clock making 8 5 GBytes per second data transfer rates possible The Dual Core Intel Xeon Processor 5160 offers higher clock frequencies than the Dual Core Intel Xeon Processor 5100 Series for platforms that are targeted for the performance optimized segment Enhanced th
152. ssssssmemem s 27 2 13 Processor DC Specifications cessisse ees DEEDEE na segue n e ad n Re da ad e E e een E 29 2 13 1 VCC Overshoot Specification eee emen 35 2 13 2 Die Voltage Validatlon oreet Rt eher RES ken k n Qa ak A S r An n wa xa ERE Na n 36 3 Mechanical Specificablons si sin sien aa nina a nin k aia bin bh aya anka nin k i 37 3 1 Package Mechanical Drawings kKhK hKk h lklk kk ene teeta eens 37 3 2 Processor Component Keepout ZONES cece cece eee ne eee eet een 41 3 3 Package Loading Specifications sxa s kaldin nk kasi babe na bna a naka an nae Kalp bara b d ena a nens 41 3 4 Package Handling Guidelines kk menn 42 3 5 Package Insertion SpecificationS 0 nme kak aka 42 3 6 Processor Mass Specifications sssssssssssssss memes eem nnns 42 3 7 Processor MaterlalS to Za ooo kanan sakin nan ne h waza o Sal a PNE tiene hemi BER E b an a k nin UE 43 3 8 Processor Land Coordinates hk kh h v k kk kk mmm emen ak nnns 43 4 Land BRI ME 45 4 1 Dual Core Intel Xeon Processor 5100 Series Pin Assignments 45 4 3 1 band Listing by Land Name ns ener ere kalak b da na kl W pa nw kw na Area WAR wa dika n 45 4 1 2 Land Listing by Land NUM ber sssssssrsssessrrererserarsrrerntsrrerrrnernerererrenerserens 55 5 Signal DefiniblOnis crecer retur rm yy mr rm 65 5L Signal Definitions
153. t Output V5 Al4 Source Sync Input Output V6 VSS Power Other V7 VSS Power Other V8 VCC Power Other w MS IDO Power Other Output w2 RESERVED W23 VCC Power Other w24 VCC Power Other W25 VCC Power Other w26 VCC Power Other W27 VCC Power Other w28 VCC Power Other w29 VCC Power Other W3 TESTHIO1 Power Other Input w30 VCC Power Other wa VSS Power Other W5 Al6 Source Sync Input Output W6 A18 Source Sync Input Output W7 VSS Power Other ws VCC Power Other 64 Dual Core Intel Xeon Processor 5100 Series Datasheet Signal Definitions 5 Signal Definitions 5 1 Table 5 1 Signal Definitions Signal Definitions Sheet 1 of 7 Name Type Description Notes A 35 3 1 0 A 35 3 Address define a 239 byte physical memory address space In sub phase 1 of the address phase these signals transmit the address of a transaction In sub phase 2 these signals transmit transaction type information These signals must connect the appropriate pins of all agents on the FSB A 35 3 are protected by parity signals AP 1 0 A 35 3 are source synchronous signals and are latched into the receiving buffers by ADSTB 1 0 On the active to inactive transition of RESET the processors sample a subset of the A 35 3 lands to determine their power on configuration See Section 7 1 A20M If A20M Address 20 Mask is asserted the processor masks ph
154. t which the particular processor can operate If lower speeds are desired the appropriate ratio can be configured via the CLOCK FLEX MAX MSR For details of operation at core frequencies lower than the maximum rated processor speed refer to the Conroe and Woodcrest Processor Family BIOS Writer s Guide Clock multiplying within the processor is provided by the internal phase locked loop PLL which requires a constant frequency BCLK 1 0 input with exceptions for spread spectrum clocking The Dual Core Intel Xeon Processor 5100 Series utilizes differential clocks Details regarding BCLK 1 0 driver specifications are provided in the CK410B Clock Synthesizer Driver Design Guidelines Table 2 1 contains processor core frequency to FSB multipliers and their corresponding core frequencies Table 2 1 Core Frequency to FSB Multiplier Configuration Core Frequency to Core Frequency with FSB Multiplier 266 MHz FSB Clock Processor Notes 1 6 1 60 GHz 5110 1 2 3 4 1 7 1 86 GHz 5120 5128 1 2 3 1 8 2 13 GHz 5138 1 2 3 Core Frequency to Core Frequency with FSB Multiplier 333 MHz FSB Clock Processor Notes 1 6 2 0 GHz 5130 1 2 3 4 1 7 2 33 GHz 5140 5148 1 2 3 1 8 2 66 GHz 5150 1 2 3 1 9 3 0 GHz 5160 1 2 3 Notes 1 Listed frequencies illustrate clock frequency multipliers and are not necessarily committed production frequencies for 40 W 65 W or 80 W versions of Dual Core Intel Xeon
155. tal considerations Intel has developed thermal profiles specific to enable the Dual Core Intel Xeon Processor LV 5138 to be used in environments compliant with NEBS Level 3 ambient operating temperature requirements At a minimum NEBS Level 3 requires a nominal ambient operating temperature of 40 C with short term excursions to 55 C Short term is defined as a maximum of 96 hours per instance for a total maximum of 360 hours per year and a maximum of 15 instances per year To comply with these ambient operating temperature requirements Intel has developed a corresponding Nominal Thermal Profile and Short Term Thermal Profile For normal operation the processor must remain within the minimum and maximum case temperature Tcase specifications as defined by the Nominal Thermal Profile For short term operating conditions maximum 96 hours per instance maximum 360 hours per year maximum of 15 instances per year the processor may remain within the minimum and maximum Tease as defined by the Short Term Thermal Profile For environments that do not require NEBS Level 3 compliance the processor must always remain within the minimum and maximum case temperature Tease specifications as defined by the Nominal Thermal Profile To provide greater flexibility in environmental conditions and thermal solution design the Nominal Thermal Profile and the Short Term Thermal Profile are each specified 5 C above the NEBS Level 3 ambient opera
156. tched until PWRGOOD is de asserted While the de assertion of the PWRGOOD signal will de assert THERMTRIP if the processor s junction temperature remains at or above the trip level THERMTRIP will again be asserted within 10 us of the assertion of PWRGOOD 70 Dual Core Intel Xeon Processor 5100 Series Datasheet Signal Definitions Table 5 1 Signal Definitions Sheet 7 of 7 intel Name TMS Type l Description TMS Test Mode Select is a J TAG specification support signal used by debug tools Notes TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of all FSB agents TRST TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset VccPLL The Dual Core Intel Xeon Processor 5100 Series implements an on die PLL filter solution The Vccp input is used as a PLL supply voltage VCC_DIE_SENSE VCC_DIE_SENSE2 VCC_DIE_SENSE and VCC_DIE_SENSE2 provides an isolated low impedance connection to the processor core power and ground This signal should be connected to the voltage regulator feedback signal which insures the output voltage that is processor voltage remains within specification Please see the applicable platform design guide for implementation details VID 6 1 VID 6 1 Voltage I D
157. ter solution is implemented on the Dual Core Intel Xeon Processor 5100 Series The Vecp input is used for this configuration in Dual Core Intel Xeon Processor 5100 Series based platforms Please refer to Table 2 13 for DC specifications Refer to the appropriate platform design guidelines for decoupling and routing guidelines Voltage Identification VI D The Voltage Identification VID specification for the Dual Core Intel Xeon Processor 5100 Series is defined by the Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor Vcc pins VID signals are open drain outputs which must be pulled up to V Please refer to Table 2 16 for the DC specifications for these signals A voltage range is provided in Table 2 13 and changes with frequency The specifications have been set such that one voltage regulator can operate with all supported frequencies Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings This is reflected by the VID range values provided in Table 2 3 The Dual Core Intel Xeon Processor 5100 Series uses six voltage identification signals VID 6 1 to support automatic selection of power supply voltages Table 2 3 specifies the voltage level corresponding to the state of VID 6
158. the processor case temperature specifications This rating applies to the processor and does not include any tray or packaging 5 Failure to adhere to this specification can affect the long term reliability of the processor Dual Core Intel Xeon Processor 5100 Series Datasheet m Electrical Specifications n tel 2 13 Processor DC Specifications The processor DC specifications in this section are defined at the processor core pads unless noted otherwise See Section 4 1 for the Dual Core Intel Xeon Processor 5100 Series land listings and Section 5 1 for signal definitions Voltage and current specifications are detailed in Table 2 13 For platform planning refer to Table 2 14 which provides VCC static and transient tolerances This same information is presented graphically in Figure 2 4 The DC specifications for the AGTL signals are listed in Table 2 15 Legacy signals and Test Access Port TAP signals follow DC specifications similar to CMOS The DC specifications for the PWRGOOD input and TAP signal group are listed in Table 2 16 Table 2 13 through Table 2 18 list the DC specifications for the processor and are valid only while meeting specifications for case temperature TcAse as specified in Chapter 6 Thermal Specifications clock frequency and input voltages Care should be taken to read all notes associated with each parameter Table 2 13 Voltage and Current Specifications Sheet 1 of 2
159. ther VCC T29 Power Other VCC J30 Power Other VCC T30 Power Other VCC J8 Power Other VCC T8 Power Other VCC J9 Power Other VCC U23 Power Other VCC K23 Power Other VCC U24 Power Other VCC K24 Power Other VCC U25 Power Other VCC K25 Power Other VCC U26 Power Other VCC K26 Power Other VCC U27 Power Other VCC K27 Power Other VCC U28 Power Other VCC K28 Power Other VCC U29 Power Other VCC K29 Power Other VCC U30 Power Other VCC K30 Power Other VCC u8 Power Other VCC K8 Power Other VCC v8 Power Other VCC L8 Power Other VCC w23 Power Other VCC M23 Power Other VCC W24 Power Other VCC M24 Power Other VCC w25 Power Other VCC M25 Power Other VCC W26 Power Other VCC M26 Power Other VCC W27 Power Other VCC M27 Power Other VCC w28 Power Other VCC M28 Power Other VCC w29 Power Other VCC M29 Power Other VCC w30 Power Other 50 Dual Core Intel Xeon Processor 5100 Series Datasheet intel Land Listing Table 4 1 Land Listing by Land Name Table 4 1 Land Listing by Land Name Sheet 13 of 20 Sheet 14 of 20 Pin Name Ne M o m Direction Pin Name N Bu we Direction VCC ws Power Other VSS AB23 Power Other VCC Y23 Power Other VSS AB24 Power Other VCC Y24 Power Other VSS AB25 Power Other VCC Y25 Power Other VSS AB26 Power Other VCC Y26 Power
160. ting conditions in which all processor specifications including DC AC FSB signal quality mechanical and thermal are satisfied Storage Conditions Refers to a non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor lands should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material Dual Core Intel Xeon Processor 5100 Series Datasheet 13 Introduction Priority Agent The priority agent is the host bridge to the processor and is typically known as the chipset Symmetric Agent A symmetric agent is a processor which shares the same I O subsystem and memory array and runs the same operating system as another processor in a system Systems using symmetric agents are known as Symmetric Multiprocessing SMP systems Integrated Heat Spreader I HS A component of the processor package used to enhance the thermal performance of the package Component thermal solutions interface with the processor at the IHS surface Thermal Design Power Processor thermal solutions should be designed to meet this target It is the highest expected sustainable power while r
161. ting temperature requirements of 40 C nominal and 55 C short term The Nominal Thermal Profile is defined at an ambient operating temperature of 45 C and the Short Term Thermal Profile is defined at an ambient operating temperature of 60 C Both of these thermal profiles ensure adherence to Intel reliability requirements It is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Utilization of a thermal solution that exceeds the Short Term Thermal Profile or which operates at the Short Term Thermal Profile for a duration longer than the specified limits will violate the thermal specifications and may result in permanent damage to the processor Refer to the Dual Core Intel Xeon Processor LV 5138 in Embedded Applications Thermal Mechanical Design Guidelines for details on system thermal solution design thermal profiles and environmental considerations The Dual Core Intel Xeon Processor 5160 has two thermal profiles either of which can be implemented Both ensure adherence to Intel reliability requirements Thermal Profile A see Figure 6 4 Table 6 9 is representative of a volumetrically unconstrained thermal solution that is industry enabled 2U heatsink In this scenario it is expected that the Thermal Control Circuit TCC would only be activated for very brief periods of time when running the most power intensive applications Ther
162. to the original value Processors running in the lowest bus ratio supported as shown in Table 2 1 will enter the HALT State when the processor has executed the HALT or MWAIT instruction since the processor is already operating in the lowest core frequency and voltage operating point Dual Core Intel Xeon Processor 5100 Series Datasheet 93 intel Figure 7 1 7 2 3 94 Stop Clock State Machine HALT or MWAIT Instruction and HALT Bus Cycle Generated Normal Stat Extended HALT or HALT State jos ai INIT BINIT INTR NMI SMI BCLK running iE RESET FSB interrupts Snoops and interrupts allowed A x lt C Snoop Snoop STPCLK STPCLK amp Event _ Event Asserted De asserted Occurs Serviced Y Extended HALT Snoop or HALT Snoop State BCLK running Service snoops to caches Y Stop Grant State e or Stop Grant Snoop State BCLK running BCLK running Snoops and interrupts allowed Snoop Event Serviced Service snoops to caches Stop Grant State When the STPCLK pin is asserted the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor issued Stop Grant Acknowledge special bus cycle Once the STPCLK pin has been asserted it may only be deasserted once the processor is in the Stop Grant state Both processor cores will enter the Stop Grant state once the STPCLK pin is asserted Additi
163. trate for ownership of the processor FSB it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor FSB throughout the bus locked operation and ensure the atomicity of lock MCERR MS ID 1 0 1 0 MCERR Machine Check Error is asserted to indicate an unrecoverable error without a bus protocol violation It may be driven by all processor FSB agents MCERR assertion conditions are configurable at a system level Assertion options are defined by the following options Enabled or disabled e Asserted if configured for internal errors along with IERR Asserted if configured by the request initiator of a bus transaction after it observes an error Asserted by any bus agent when it observes an error in a bus transaction For more details regarding machine check architecture refer to the A 32 Software Developer s Manual Volume 3 System Programming Guide These signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying These signals are not connected to the processor die A logic 0 is pulled to ground and a logic 1 is a no connect on the Dual Core Intel Xeon Processor 5100 Series package PECI 1 0 PECI is a proprietary one wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal monitoring devices See Section
164. ttempts to ensure the Thermal Control Circuit is not activated below maximum TcAse when dissipating TDP power There is no defined or fixed correlation between the PROCHOT trip temperature or the case temperature Thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of Tcase or PROCHOT FORCEPR Signal The FORCEPR force power reduction input can be used by the platform to cause the Dual Core Intel Xeon Processor 5100 Series to activate the TCC If the Thermal Monitor is enabled the TCC will be activated upon the assertion of the FORCEPR signal Assertion of the FORCEPR signal will activate TCC for both processor cores The TCC will remain active until the system deasserts FORCEPR FORCEPR is an asynchronous input FORCEPR can be used to thermally protect other system components To use the VR as an example when FORCEPR is asserted the TCC circuit in the processor will activate reducing the current consumption of the processor and the corresponding temperature of the VR It should be noted that assertion of FORCEPR does not automatically assert PROCHOT As mentioned previously the PROCHOT signal is asserted when a high temperature situation is detected A minimum pulse width of 500 us is recommended when FORCEPR is asserted by the system Sustained activation of the FORCEPR signal may cause noticeable platform performance degradation Refer to the app
165. ual Core Intel Xeon Processor 5100 Series Datasheet Boxed Processor Specifications n tel 8 8 1 Figure 8 1 Boxed Processor Specifications Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels The Dual Core Intel Xeon Processor 5100 Series will be offered as an Intel boxed processor Intel will offer the Dual Core Intel Xeon Processor 5100 Series with two heat sink configurations available for each processor frequency 1U passive 3U active combination solution and a 2U passive only solution The 1U passive 3U active combination solution is based on a 1U passive heat sink with a removable fan that will be pre attached at shipping This heat sink solution is intended to be used as either a 1U passive heat sink or a 3U active heat sink Although the active combination solution with removable fan mechanically fits into a 2U keepout its use is not recommended in that configuration The 1U passive 3U active combination solution in the active fan configuration is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and strong side directional airflow is not an issue The 1U passive 3U active combination solution with the fan removed and the 2U passive thermal solution require the use of chassis ducting and are targeted for use in rack mount or pedestal servers The retention solution
166. uenerit sanika ak kaliy a nb haa AUR TX Redit dad da d Ra RE ERA rk d RENE NR 65 6 Thermal SpeciflCatlofis 1 sdelkkelalnlhiky na chen ere Decr enl eie in nala Win ya n hak ban n n n b Tree bebe dal 73 6 1 Package Thermal Specifi Cat OnS ML l kk kk kk kk kk kk kak renes 73 6 1 1 Thermal Specifications cr d sen lek Wenn ah n temer dn e Pocos Ear LR eet b y 73 6 1 2 Thermal Metrology L hkhk lkk kk kk kk kk Iesse kk emen nnn 81 6 2 Processor Thermal FeatU S s isa si klkan kulan na Haaa karn bana k nan a a kala aa aa aa bai a kad na lal a ara 82 6 2 1 Thermal Monitor FeatUreS LM k hC kk kkk kk eee nnne 82 Dual Core Intel Xeon Processor 5100 Series Datasheet 6 2 2 O Demand Mode ica han php LA AW CERCA RED A W b wak bA D YA E d r 84 6 2 3 PROCHOT Signal s ass ku trn REA neni enun tener is hb dadan A bl an n anan ka dika 85 6 2 4 FORCEPR Signal cna aber a KEY day w D k Ya WAD W haka Wadan ears 85 6 2 5 THERMTRIP SIQA niina i salkl kina laten bia a Hal ayn alc M bkay ba f c aya nennen nnn 86 6 3 Platform Environment Control Interface PECI c sss Hee 86 6 3 1 Introduction ee mm e meee e C DR Redon 86 6 3 2 PECISPEGCIICALIONS eire ted retener bala ren War alla ce Fh yana nan ba var da D Df 88 7 Feature SN N eas DN DD rr rg dg 91 7 1 Power On Configuration Options kh h kkL kkkkk kk kk
167. unning known power intensive real applications TDP is not the maximum power that the processor can dissipate I ntel Extended Memory 64 Technology Intel EM64T An enhancement to Intel s IA 32 architecture that allows the processor to execute operating systems and applications written to take advantage of the 64 bit extension technology Further details on can be found in the 64 bit Extension Technology Software Developer s Guide at http developer intel com Enhanced Intel SpeedStep Technology EIST Technology that provides power management capabilities to servers and workstations Platform Environment Control I nterface PECI A proprietary one wire bus interface that provides a communication channel between Intel processor and chipset components to external thermal monitoring devices for use in fan speed control PECI communicates readings from the processor s digital thermal sensor PECI replaces the thermal diode available in previous processors I ntel virtualization Technology Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple robust independent software environments inside a single platform VRM Voltage Regulator Module DC DC converter built onto a module that interfaces with a card edge socket and supplies the correct voltage and current to the processor based on the logic state of the processor VID bits EVRD Enterprise Voltage Regulator Down DC DC
168. urce Sync Input Output DO8 A10 Source Sync Input Output D48 D20 Source Sync Input Output D09 All Source Sync Input Output D49 D17 Source Sync Input Output D10 B10 Source Sync Input Output D50 Al4 Source Sync Input Output D11 C11 Source Sync Input Output D51 C15 Source Sync Input Output D12 D8 Source Sync Input Output D52 C14 Source Sync Input Output D13 B12 Source Sync Input Output D53 B15 Source Sync Input Output D14 C12 Source Sync Input Output D54 C18 Source Sync Input Output D15 D11 Source Sync Input Output D55 B16 Source Sync Input Output D16 G9 Source Sync Input Output D56 A17 Source Sync Input Output D17 F8 Source Sync Input Output D57 B18 Source Sync Input Output D18 F9 Source Sync Input Output D58 C21 Source Sync Input Output D19 E9 Source Sync Input Output D59 B21 Source Sync Input Output D20 D7 Source Sync Input Output D60 B19 Source Sync Input Output D21 E10 Source Sync Input Output D61 A19 Source Sync Input Output D22 D10 Source Sync Input Output D62 A22 Source Sync Input Output D23 F11 Source Sync Input Output D63 B22 Source Sync Input Output D24 F12 Source Sync Input Output DBI0 A8 Source Sync Input Output D25 D13 Source Sync Input Output DBI1 G11 Source Sync Input Output D26 E13 Source Sync Input Output DBI2 D19 Source Sync Input Output D27 G13 Source Sync Input Output DBI3 C20 Source Sync Input Output D28 F14 Source
169. vious processor families Design guidelines for the processor FSB are detailed in the appropriate platform design guidelines refer to Section 1 3 The AGTL inputs require reference voltages GTLREF_DATA and GTLREF_ADD which are used by the receivers to determine if a signal is a logical 0 or a logical 1 GTLREF_DATA is used for the 4X front side bus signaling group and GTLREF_ADD is used for the 2X and common clock front side bus signaling groups Both GTLREF_DATA and GTLREF_ADD must be generated on the baseboard Refer to the applicable platform design guidelines for details Termination resistors R77 for AGTL signals are provided on the processor silicon and are terminated to VTE The on die termination resistors are always enabled on the Dual Core Intel Xeon Processor 5100 Series to control reflections on the transmission line Intel chipsets also provide on die termination thus eliminating the need to terminate the bus on the baseboard for most AGTL signals Some FSB signals do not include on die termination R77 and must be terminated on the baseboard See Table 2 9 for details regarding these signals The AGTL bus depends on incident wave switching Therefore timing calculations for AGTL signals are based on flight time as opposed to capacitive deratings Analog signal simulation of the FSB including trace lengths is highly recommended when designing a system Contact your Intel Field Representative to obtain the processor sign
170. wer bus to core frequency ratio and VID operating point of the Extended HALT state While in the Extended HALT Snoop state snoops and interrupt transactions are handled the same way as in the HALT Snoop state After the snoop is serviced or the interrupt is latched the processor will return to the Extended HALT state Enhanced Intel SpeedStep Technology Dual Core Intel Xeon Processor 5100 Series supports Enhanced Intel SpeedStep Technology This technology enables the processor to switch between multiple frequency and voltage points which results in platform power savings Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform Switching between voltage frequency states is software controlled Not all Dual Core Intel Xeon Processor 5100 Series are capable of supporting Enhanced Intel SpeedStep Technology More details on which processor frequencies will support this feature is provided in the Dual Core Intel Xeon Processor 5100 Series Specification Update Dual Core Intel Xeon Processor 5100 Series Datasheet 95 96 ntel Enhanced Intel SpeedStep Technology creates processor performance states P states or voltage frequency operating points P states are lower power capability states within the Normal state as shown in Figure 7 1 Enhanced Intel SpeedStep Technology enables real time dynamic switching between frequency and voltage points It alters the performance
171. ycled Refer to Voltage Regulator Module VRM and Enterprise Voltage Regulator Down EVRD 11 0 Design Guidelines Dual Core Intel Xeon Processor 5100 Series Datasheet m Electrical Specifications n tel Table 2 5 Table 2 6 2 6 Loadline Selection Truth Table for LL 1D 1 0 LL_ID1 LL_IDO Description 0 0 Reserved 0 1 Dual Core Intel Xeon Processor 5100 Series 1 0 Reserved 1 1 Reserved Note The LL_ID 1 0 signals are used to select the correct loadline slope for the processor Market Segment Selection Truth Table for MS_1D 1 0 MS_ID1 MS lI DO Description 0 0 Reserved 0 1 Dual Core Intel Xeon Processor 5100 Series 1 0 Reserved 1 1 Reserved Note The MS ID 1 0 signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying Reserved or Unused Signals All Reserved signals must remain unconnected Connection of these signals to Vec Vme Vss or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 for a land listing of the processor and the location of all Reserved signals For reliable operation always connect unused inputs or bidirectional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground Vss Unused outputs can be left unconnect
172. ysical address bit 20 A20 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting A20M emulates the 8086 processor s address wrap around at the 1 MB boundary Assertion of A20M is only supported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an I O write instruction it must be valid along with the TRDY assertion of the corresponding I O write bus transaction ADS 1 0 ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 35 3 lands All bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction This signal must be connected to the appropriate pins on all Dual Core Intel Xeon Processor 5100 Series FSB agents ADSTB 1 0 1 0 Address strobes are used to latch A 35 3 and REQ 4 0 on their rising and falling edge Strobes are associated with signals as shown below Signals Associated Strobes REQ 4 0 A 16 3 ADSTBO A 35 17 ADSTB1 AP 1 0 1 0 AP 1 0 Address Parity are driven by the request initiator along with ADS A 35 3 and the transaction type on the REQ 4 0 signals A correct parity signal is high if an even number of covered signals are low and low if an odd number of covere

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