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Application Note - Atmel Corporation
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1. Technical Reference Manual RN ARM926EJ S Technical Reference Manual Embedded in circuit emulator Evaluation Kit User Guide AT91SAM9263 EK Evaluation Board User Guide Using SDRAM on AT91SAMSO Microcontrollers Using SDRAM on AT91SAM9 Microcontrollers NANDFlash Support in AT91SAM9 Microcontrollers NAND Flash Support in AT91SAMO Microcontrollers 2 Application Note memm 6305C ATARM 07 May 09 Application Note 3 Schematic Check List CAUTION The AT91SAMO board design must comply with the power up and power down sequence guidelines provided in the Electrical Characteristics section in the datasheet to guarantee reliable operation of the device 1 2V and 3 3V Dual Power Supply Schematic Example 100nF Roa VDDPLL GNDPLL 100nF rel VDDOSC GND 100nF Ti VDDIOP1 eno t TJ VDDIOPO 10 F 100nF GND T t TJ VDDIOMO 1OuF 100nF DC DC Converter GND e 1 VDDIOM1 10pF 100nF l T F GND 100nF DC DC Converter GNDBU L ee VDDCORE i0uF 100nF AG a GND 1 2V and 3 3V Dual Power Supply Schematic Example 3 3V external memories VDDIOMO amp VDDIOM1 3 3V Image Sensor VDDIOP1 are used AMEL 3 6305C ATARM 07 May 09 Signal Name AMEL Recommended Pin Connection 1 08V to 1 32V Description Powers the device VDDCORE Decoupling Filtering capacitors m f 102 Decoupling Fi
2. allowing calculation of the best R C1 C2 component values for the PLL Loop Back Filter Second order filter PLLRCA L SEC PLL PLLRCB E Can be left unconnected if PLL not used R C2 AT91SAM9263 C1 tx GNDPLL R C1 and C2 must be placed as close as possible to the pins AMEL 7 6305C ATARM 07 May 09 ATMEL Signal Name Recommended Pin Connection Description ICE and JTAG TCK Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TMS Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDI Pull up 100 kOhm This pin is a Schmitt trigger input No internal pull up resistor TDO Floating Output driven at up to Vyppiopo RTCK Floating Output driven at up to Vyppiopo Please refer to the I O line considerations NTRST and the errata sections of AT91SAM9263 Internal pull up resistor to Vyppiopo 100 kOhm datasheet H 6 In harsh environments It is strongly Must be tied to Vypppy to enter JTAG Boundary Scan recommended to tie this pin to GNDBU JTAGSEL if not used or to add an external low value resistor such as 1 kOhm Internal pull down resistor to GNDBU 15 kOhm Reset Test NRST is configured as an output at power up Application dependent NRST Can be connected to a push button for NRST is controlled by the Reset Controller RSTC hardware reset An in
3. 9 Notes NWR 1 enables upper byte writes NWRO enables lower byte writes 1 2 NWRx enables corresponding byte x writes x 0 1 2 or 3 3 NBSO and NBS1 enable respectively lower and upper bytes of the lower 16 bit word 4 NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16 bit word 5 EBIO signals only 6 BEx Byte x Enable x 0 1 2 or 3 7 EBI1 signals only AMEL 6305C ATARM 07 May 09 AMEL Table 4 2 EBI Pins and External Devices Connections Pins of the Interfaced Device CompactFlash Signals SDRAM esas FA ipd NANDFlash EBIO_ EBI1_ EBIO only Controller SDRAMC SMC DO D7 DO D7 DO D7 DO D7 I O0 I O7 D8 D15 D8 D15 D8 15 D8 15 I O8 I O15 9 D16 D31 D16 D31 AO NBSO DQMO AO AO A1 NWR2 NBS2 DQM2 A1 A1 A2 A10 A 0 8 A 2 10 A 2 10 A11 A9 SDA10 A10 A12 A13 A14 A 11 12 E A15 A16 BAO BAO A17 BA1 BA1 A18 A20 A21 NANDALE ALE A22 NANDCLE s REG REG CLE A23 A249 A25 CFRNW CFRNW NCSO NCS1 SDCS CS NCS2 NCS2 NANDCS NCS3 NANDCS CE NCS4 CFCSO CFcso CFcso NCS5 CFCS1 cFcs1 cFcs1 NANDOE OE NANDWE WE NRD CFOE OE 7 NWRO NWE CFWE WE WE NWR1 NBS1 CFIOR DQMI1 IOR IOR NWR3 NBS
4. for use as components in applications intended to support or sustain life 2007 Atmel Corporation All rights reserved Atmel logo and combinations thereof and others are registered trademarks or trademarks of Atmel Europe Le Krebs 8 Rue Jean Pierre Timbaud BP 309 78054 Saint Quentin en Yvelines Cedex France Tel 33 1 30 60 70 00 Fax 33 1 30 60 71 11 Technical Support AT91SAM Support Atmel techincal support Atmel Corporation or its subsidiaries Other terms and product names may be trademarks of others Atmel Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 Sales Contacts www atmel com contacts 6305C ATARM 07 May 09
5. 3 CFIOW DQM3 IOW IOW z CFCE1 CE1 cso CFCE2 CE2 CS1 14 Application Note memm 6305C ATARM 07 May 09 Application Note Table 4 2 EBI Pins and External Devices Connections Continued Pins of the Interfaced Device mpactFlash Signals SDRAM popalo iA Me NANDFlash EBIO_ EBI1_ REIU DAIN EBIO only Controller SDRAMC SMC SDCK CLK SDCKE CKE RAS RAS CAS CAS SDWE WE NwAIT WAIT WAIT Pxx B CD1 or CD2 CD1 or CD2 Pxx CE Pxx RDY Notes 1 Notdirectly connected to the CompactFlash slot Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot Any PIO line EBIO signals only EBI1 signals only 1 08 1 015 bits used only for 16 bit NANDFlash CE connection depends on the NANDFlash For standard NANDFlash devices it must be connected to any free PIO line For CE don t care NANDFlash devices it can be connected either to NCS3 NANDCS or to any free PIO line EBIO_NWAIT signal is multiplexed with PD5 EBI1_NWAIT signal is multiplexed with PE20 8 For SDRAM connection examples see Using SDRAM on AT91SAM9 Microcontrollers application note 9 For NANDFlash connection examples see NAND Flash Support in AT91SAM Microcontrollers application note oa bo N N AMEL 6305C ATARM 07 May 09 AMEL 5 AT91SAM Boot Program Hardwa
6. AT91SAM9263 Microcontroller Schematic Check List 1 Introduction This application note is a schematic review check list for systems embedding the Atmel ARM Thumb based AT91SAM9263 microcontroller It gives requirements concerning the different pin connections that must be consid ered before starting any new board design and describes the minimum hardware resources required to quickly develop an application with the AT91SAM9263 It does not consider PCB layout constraints It also gives advice regarding low power design constraints to minimize power consumption This application note is not intended to be exhaustive Its objective is to cover as many configurations of use as possible The Check List table has a column reserved for reviewing designers to verify the line item has been checked AMEL T O AT91 ARM Thumb based Microcontrollers Application Note 6305C ATARM 07 May 09 AMEL 2 Associated Documentation Before going further into this application note it is strongly recommended to check the latest documents for the AT91SAM9263 Microcontroller on Atmel s Web site Table 2 1 gives the associated documentation needed to support full understanding of this appli cation note Table 2 1 Associated Documentation Information Document Title User Manual Electrical Mechanical Characteristi d a ancas aas RS AT91SAM9263 Product Datasheet Ordering Information Errata E alain ENIM ARM9EJ S
7. ET FORTH IN ATMEL S TERMS AND CONDI TIONS OF SALE LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifica tions and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Unless specifically pro vided otherwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted International Atmel Asia Unit 1 5 amp 16 19 F BEA Tower Millennium City 5 418 Kwun Tong Road Kwun Tong Kowloon Hong Kong Tel 852 2245 6100 Fax 852 2722 1369 Product Contact Web Site www atmel com www atmel com AT91SAM Literature Requests www atmel com literature
8. MC SDRAM Controller CompactFlash Support NANDFlash Support See External Bus Interface EBI Hardware Interface on page 13 10 Application Note memm 6305C ATARM 07 May 09 m Application Note ral Signal Name Recommended Pin Connection Description USB Host UHP No internal pull down resistors HDPA Application dependent HDPB Typically 15 kOhm resistor to GND To reduce power consumption if USB Host is not used connect HDPA HDPB to GND No internal pull down resistors HDMA Application dependent HDMB Typically 15 kOhm resistor to GND To reduce power consumption if USB Host is not used connect HDMA HDMB to GND USB Device UDP To reduce power consumption USB Device Built in Transceivers can be disabled enabled by default Integrated programmable pull up resistor UDP TXVC No internal pull down resistor DDP Application dependent To reduce power consumption if USB Device is not used connect DDP to Vyppiopo No internal pull down resistor DDM Application dependent To reduce power consumption if USB Device is not used connect DDM to GND Notes 1 These values are given only as a typical example 2 Decoupling capacitors must be connected as close as possible to the microcontroller and on each concerned pin 100nF Hn VDDCORE 100nF i i VDDCORE 100nF l Hi VDDCORE GND 3 The double
9. commended resistor value is defined in the electrical specifications of the AT91SAM9263 datasheet itori 27K PIO 5V Bus Monitoring d 3 TypeB 4 Connector 330 K 330 K 12 Application Note mem 6305C ATARM 07 May 09 m Application Note 4 External Bus Interface EBI Hardware Interface Table 4 1 and Table 4 2 detail the connections to be applied between the EBI pins and the external devices for each Mem ory Controller Table 4 1 EBI Pins and External Static Devices Connections Pins of the Interfaced Device Signa esse Rae Mire qae mee time EBIO EBH Devices Devices Devices Controller MC DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 DO D7 D8 D15 D8 D15 D8 D15 D8 D15 D8 15 D8 15 D16 D23 D16 D23 D16 D23 D16 D23 D24 D31 D24 D31 D24 D31 D24 D31 AO NBSO AO NLB NLB BEO A1 NWR2 NBS2 A1 AO AO WEO NLB BE2 9 A2 A22 A 2 22 A 1 21 A 1 21 A 0 20 A 0 20 A 0 20 A23 A259 A 23 25 A 22 24 A 22 24 A 21 23 A 21 23 A 21 23 NCSO CS CS CS CS CS CS NCS1 SDCS CS CS CS CS CS CS NCS209 CS CS CS CS CS CS NCS2 NANDCS CS CS CS CS CS CS NCS3 NANDCS CS CS CS CS CS CS NCS4 CFCSso CS CS CS CS CS CS NCS5 CFCS1 CS CS CS CS CS CS NRD CFOE OE OE OE OE OE OE NWRO NWE WE WE WE WEO WE WE NWR1 NBS1 WE NUB WEO NUBO BE1 9 NWR3 NBS3 WE NUB BE3
10. ith frequencies above 8 MHz Crystal load capacitance to check Ccrysta AT91SAM9263 1 1K i ConvsrAL 1 i x Crex Ciexr T Example for an 18 432 MHz crystal with a load capacitance of Ccorysta 15 pF external capacitors are required C gxr 18pF Refer to the electrical specifications of the AT91SAM9263 datasheet XIN XOUT Main Oscillator in Bypass Mode XIN external clock source XOUT can be left unconnected 3 3V VDDPLL square wave signal External clock source up to 50 MHz Duty Cycle 40 to 6096 Refer to the electrical specifications of the AT91SAM9263 datasheet XIN32 XOUT32 Slow Clock Oscillator 32 768 kHz Crystal Capacitors on XIN32 and XOUT32 crystal load capacitance dependent Crystal load capacitance to check Ccrystatge AT91SAM9263 XIN32 XOUT32 GNDBU ConvsrAL32 CLEXT32 Cigxra2 Example for an 32 768 kHz crystal with a load capacitance of Copystar 357 12 5 pF external capacitors are required C gxra2 17 pF Refer to the electrical specifications of the AT91SAM9263 datasheet rta Application Note 6305C ATARM 07 May 09 w Application Note ral Signal Name Recommended Pin Connection Description See the Excel spreadsheet ATMEL PLL LFT Filter CALCULATOR AT91 oo zip available in the software files on the Atmel Web site
11. ltering capacitors must be added to improve 100 nF and 10pF M startup stability and reduce source voltage drop VDDBU 1 08V to 1 32V Powers the Backup I O lines Decoupling capacitor 100 nF Slow Clock Oscillator and a part of the System Controller Powers first External Bus Interface EBIO I O lines 1 65V to 1 95V Dual voltage range supported or The voltage ranges are selected by programming the VDDIOMO9 3 0V to 3 6V VDDIOMSEL bit in the EBIO CSA register re P At power up the selected voltage is 3 3V nominal and Decoupling Filtering capacitors i power supply pins can accept either 1 8V or 3 3V 100 nF and 1OoyF 9 Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop Powers second External Bus Interface EBI1 I O lines Dual voltage range supported 1 65V to 1 95V The voltage ranges are selected by programming the or VDDIOMSEL bit in the EBI1_CSA register VDDIOM1 3 0V to 3 6V At power up the selected voltage is 3 3V nominal and Decoupling Filtering capacitors power supply pins can accept either 1 8V or 3 3V 100 nF and 1O0yF 9 Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop 27N to 3 6V Powers Peripheral I O lines and USB transceivers VDDIOPO 4 Decoupling Filtering capacitors BM 10 Decoupling Filtering capacitors must be added to improve 100 nF and 10pF m startup stability and reduce source voltage drop P
12. nection Description PIO All PIOs are pulled up inputs at reset except those which PAx are multiplexed with the Address Bus signals that require to be enabled as peripherals ka Application d d PD12 EBIO A23 PD13 EBIO A24 PD14 EBIO A25 dug pplication dependent Fipillig Ep 100K hes x To reduce power consumption if not used the concerned PEX PIO can be configured as an output driven at 0 with internal pull up disabled EBIO 9263 system boots only on EBIO with dedicated Chip Select Data Bus DO to D31 Data bus lines DO to D15 are pulled up inputs to Vyppiomo D0 D15 o at reset D16 D31 Application dependent Note Data bus lines D16 to D31 are multiplexed with the PIOD controller Their I O line reset state is input with pull up enabled too Address Bus A0 to A25 All address lines are driven to O at reset A0 A22 Application dependent A23 A25 Note X EBIO A23 PD12 EBIO A24 PD13 EBIO A25 PD14 are enabled by default at reset through the PIO controllers EBI1 Data Bus DO to D31 Data bus lines DO to D15 are pulled up inputs to Vyppiom1 at reset DO D15 D16 D31 Application dependent Note Data bus lines D16 to D31 are multiplexed with the PIOA controller Their I O line reset state is input with pull up enabled too Address Bus A0 to A22 A0 A22 Application dependent All address lines are driven to 0 at reset S
13. nent version Refer to the AT91SAM9263 datasheet 5 5 NANDFlash Boot The NANDFlash Boot program searches for a valid application in the NANDFlash memory Table 5 4 Pins Driven during NANDFlash Boot Program Execution Peripheral Pin PIO Line PIOD PIO for NAND Chip Select PD15 PIOA PIO for NAND Ready Busy PA22 Address Bus NANDCLE A22 Address Bus NANDALE A21 NANDFlash Boot support depends on component revision Refer to the AT91SAM9263 datasheet AMEL 6305C ATARM 07 May 09 AMEL 6 Revision History Change Request Doc Rev Comments Ref Add a line to XIN and XOUT pins in Schematic Check List table 6327 6305C Add a Caution paragraph before Schematic Check List table 6124 Edit SHDN line in Schematic Check List table 6149 6305B EBIO EBI1 specified for signals NCS2 and NCS2 NANDCS Table 4 1 on page 13 4588 Updated Recommended Pin Connection for JTAGSEL and TST 5076 6305A First issue 18 Application Note memm 6305C ATARM 07 May 09 AIMEL T Headquarters Atmel Corporation 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS S
14. owers Peripheral I O lines involving Image Sensor 1 65V to 3 6V Interface ISI VDDIOP10 Decoupling Filtering capacitors 100 nF and 1O0yF 9 Decoupling Filtering capacitors must be added to improve startup stability and reduce source voltage drop 3 0V to 3 6V VDDOSC P the Mai illator Decoupling capacitor 100 nF 9 ene ee 3 0V to 3 6V VDDPLL B Powers the PLL cells Decoupling capacitor 100 nF Application Note m 6305C ATARM 07 May 09 Application Note al Signal Name Recommended Pin Connection Description GND pins are common to VDDCORE VDDIOM VDDOSC and VDDIOP pins GND pins should be connected as shortly as possible to the system ground plane GNDBU pin is provided for VDDBU pin GNDBU Backup Ground GNDBU pin should be connected as shortly as possible to the system ground plane GNDPLL pin is provided for VDDPLL pin GNDPLL PLL Ground GNDPLL pin should be connected as shortly as possible to the system ground plane GND Ground AMEL s 6305C ATARM 07 May 09 Signal Name AMEL Recommended Pin Connection Description Clock Oscillator and PLL XIN XOUT Main Oscillator in Normal Mode Crystals between 3 and 20 MHz Capacitors on XIN and XOUT crystal load capacitance dependent 1 kOhm resistor on XOUT only required for crystals with frequencies lower than 8 MHz 470 Ohm resistor on XOUT is mandatory for crystals w
15. power supplies VDDIOMO VDDIOM1 VDDIOPO and VDDIOP1 power the device differently when interfacing with memories or with peripherals 4 Some I O lines of PIO Controller A and PIO Controller E are powered by VDDIOM1 See the sections Multiplexing on PIO Controller A and Multiplexing on PIO Controller E in the AT91SAM9263 datasheet Some 1 0 lines of PIO Controller D are powered by VDDIOMO See the section Multiplexing on PIO Controller D in the AT91SAM9263 datasheet 5 It is recommended to establish accessibility to a JTAG connector for debug in any case 6 In a well shielded environment subject to low magnetic and electric field interference the pin may be left unconnected In noisy environments a connection to ground is recommended AMEL n 6305C ATARM 07 May 09 AMEL 7 Example of USB Host connection A termination serial resistor Rez must be connected to HDPA HDPB and HDMA HDMB A recommended resistor value is defined in the electrical specifications of the AT91SAM9263 datasheet 5V 0 50A 10uF 100nF 10nF Rext Type A Connector HDMA or HDMB HDPA or HDPB 8 Example of USB Device connection As there is an embedded pull up no external circuitry is necessary to enable and disable the 1 5 kOhm pull up To prevent over consumption when the host is disconnected an external pull down can be added to DDP and DDM A termination serial resistor Rex must be connected to DDP and DDM A re
16. re Constraints See the AT91SAM Boot Program section of the AT91SAM9263 datasheet for more details on the boot program 5 1 AT91SAM Boot Program Supported Crystals MHz 3 0 3 2768 3 6864 3 84 4 0 4 433619 4 608 4 9152 5 0 5 24288 6 0 6 144 6 4 6 5536 7 159090 7 3728 7 864320 8 0 9 8304 10 0 11 05920 12 0 12 288 13 56 14 31818 14 7456 16 0 17 734470 18 432 20 0 5 2 SAM BA Boot The SAM BA Boot Assistant supports serial communication via the DBGU or the USB Device Port Table 5 1 Pins Driven during SAM BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PC30 DBGU DTXD PC31 5 3 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory The DataFlash must be connected to NPCSO of the SPIO 16 Table 5 2 Pins Driven during DataFlash Boot Program Execution Peripheral Pin PIO Line SPIO MOSI PA1 SPIO MISO PAO SPIO SPCK PA2 SPIO NPCSO PA5 Application Note memm 6305C ATARM 07 May 09 Application Note 5 4 SD Card Boot The SD Card Boot program searches for a valid application in the SD Card memory Table 5 3 Pins Driven during SD Card Boot Program Execution Peripheral Pin PIO Line MCI1 MCCK PA6 MCI1 MCCDA PA7 MCI1 MCDAO PA8 MCI1 MCDA1 PA9 MCI1 MCDA2 PA10 MCI1 MCDA3 PA11 SD Card Boot support depends on compo
17. ternal pull up resistor to Vyppiopo 100 kOhm is available for User Reset and External Reset control In harsh environments It is strongly TST recommended to tie this pin t GNDBU Internal pull down resistor to GNDBU 15 kOhm if not used or to add an external low value resistor such as 1 kOhm Application dependent Internal pull up resistor to Vyppiopo 100 kOhm Must be tied to Vyppiopo to boot on BMS Embedded ROM Must be tied to GND to boot on external memory EBIO Chip Need to isolate PB3 BMS during reset sequence if an Select 0 external AC97 component is used No access has to be Must be stable during boot process done EROS nigh reset Shutdown Wakeup Logic Application dependent A typical application connects the pin SHDN to the shutdown input of the DC DC The SHDN pin is a tri state output Converter ja MARONI No internal pull up resistor SHDN An external pull up to VDDBU is needed An external pull up to VDDBU is needed and its value is to be higher than 1 MOhm The resistor value is calculated according to the regulator enable implementation and the SHDN level SHDN pin is driven low to GNDBU by the Shutdown Controller SHDWC Application Note mem 6305C ATARM 07 May 09 Application Note This pin is an input only WKUP OV to Vyppau WKUP behavior can be configured through the Shutdown Controller SHDWC AMEL 6305C ATARM 07 May 09 AMEL Signal Name Recommended Pin Con
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