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N-series Intel® Pentium® Processors and Intel® Celeron

1. Datasheet Volume 1 of 3 VID7 VID6 VID5 VIDA VID2 VIDO 8 0 0 0 0 0 0 0 0 0 0 0 00000 0 0 0 0 0 0 0 1 0 1 0 25000 0 0 0 0 0 0 1 0 0 2 0 25500 0 0 0 0 0 0 1 1 0 3 0 26000 0 0 0 0 0 1 0 0 0 4 0 26500 0 0 0 0 0 1 0 1 0 5 0 27000 0 0 0 0 0 1 1 0 0 6 0 27500 0 0 0 0 0 1 1 1 0 7 0 28000 0 0 0 0 1 0 0 0 0 8 0 28500 0 0 0 0 1 0 0 1 0 9 0 29000 0 0 0 0 1 0 1 0 0 A 0 29500 0 0 0 0 1 0 1 1 0 B 0 30000 0 0 0 0 1 1 0 0 0 0 30500 0 0 0 0 1 1 0 1 0 D 0 31000 0 0 0 0 1 1 1 0 0 E 0 31500 0 0 0 0 1 1 1 1 0 F 0 32000 0 0 0 1 0 0 0 0 1 0 0 32500 0 0 0 1 0 0 0 1 1 1 0 33000 0 0 0 1 0 0 1 0 1 2 0 33500 0 0 0 1 0 0 1 1 1 3 0 34000 0 0 0 1 0 1 0 0 1 4 0 34500 0 0 0 1 0 1 0 1 1 5 0 35000 0 0 0 1 0 1 1 0 1 6 0 35500 0 0 0 1 0 1 1 1 1 7 0 36000 0 0 0 1 1 0 0 0 1 8 0 36500 0 0 0 1 1 0 0 1 1 9 0 37000 0 0 0 1 1 0 1 0 1 A 0 37500 0 0 0 1 1 0 1 1 1 B 0 38000 0 0 0 1 1 1 0 0 1 0 38500 0 0 0 1 1 1 0 1 1 D 0 39000 0 0 0 1 1 1 1 0 1 E 0 39500 0 0 0 1 1 1 1 1 1 F 0 40000 0 0 1 0 0 0 0 0 2 0 0 40500 219 m e n Electrical Specifications Table 21 6 IMVP7 0 Voltage Identification Reference Sheet 2 of 7 VID7 VID6 VID5 VID2 BS BE V 0 0 1 0 0 0 0 1 2 1 0 41000 0 0 1 0 0 0 1 0 2 2 0 41500 0 0 1 0 0 0 1 1 2 3 0 42000 0 0 1 0 0
2. Symbol Parameter Min Typ Max Units Notes Single Ended Standby Voff off output voltage 10 10 mV 6 AVcc Vswing 1 output swing 400 600 mV Single Ended high level _ lt 165 MHz output voltage 10 10 mv 6 AVcc gt 165 MHz 1 ivel 200 d 10 mV 6 lt 165 MHz pira 600 400 mV 6 VoL 7165 MHz BH ea level 700 400 mV 6 AVcc Note 1 Analog Voltage level 21 6 1 3 embedded DisplayPort DC Specification Table 21 11 embedded Display Port DC Specification Symbol Parameter Min Units Notes VTX DIFFp p Differential Peak to peak LevelO Output Voltage Level 0 0 18 0 2 0 22 Y L2 VTX DIFFp p Differential Peak to peak Leveli Output Voltage Level 1 0 2 0 0 275 V 1 2 VIX DIFFp p Differential Peak to peak Level2 Be Output Voltage Level 2 0 27 0 3 0 33 1 2 VTx DIFFp p Differential Peak to peak Level3 Output Voltage Level 3 0 315 0 35 0 385 1 2 VTx DIFFp p Differential Peak to peak Level4 zi Output Voltage Level 4 0 36 0 4 ee v 1 2 VTx DIFFp p Differential Peak to peak Level5 Output Voltage Level 5 0 405 0 45 0 495 12 Maximum Allowed VTx piFFp p MAx Differential Peak to peak 1 380 V 3 Output Voltage Tx DC Common Mode No Pre emphasis 0 0 0 0 0 0 dB 1 3 5 Pre emphasis 2 8 3 5 4 2 dB 1 RATIO 6 0 dB Pre emphasis 4 8 6 0 7 2 dB 1 9 5 dB Pre
3. 82 9 1 2 Simultaneous PAR ERR RR 82 9 1 3 Primary Camera Still Image 2 02 222 222 83 9 1 4 Burst Mode S pport d n un died Males dad Ta RA ER 83 9 1 5 Continuous Mode 22 2 2 lt lt 5 kenn ca na RES ARR REA XR 83 9 1 6 Secondary Camera Still Image 83 9 1 7 Primary Camera Video 1 3 83 9 1 8 Secondary Camera Video Resolution 4 4 1 1 83 9 1 9 e Pc 83 9 2 Imaging Subsystem 2 4 4 4 4 2 4 6 nen 84 9 2 1 Processor Cope 84 9 2 2 Imaging Signal Processor ISP 84 9 2 2 1 MIPT CSI 2 GN MD NND 84 9 2 2 2 DC for Camera 85 9 2 2 3 Camera Sideband for Camera 22 2 1 85 9 3 Functional Description ient xen Fete xu YER 86 9 3 1 Preview Mode eet beaten Ta 86 9 3 2 Image Captures dele Paes
4. 119130 33 1H513H 1 4 EMOTY P y13C 335 719130 335 a 335 ke 182138 310 YNY We 1H5138 1178 145 31 3181183 18913 03578 vy 53171153 C SIMI NI NIHL 38 01 35v 3 101 11 7 HS a 1N 3193 310 HL 3 S SN ww NE T 9000 59590005959590050 00001 99825429 900000000090900000909090000000000 09209900 0 0 0 0 090 0 0 090 0 0 0 0 07 60 999 oc 0 0 090 9 8000080000800 0800000 0499900000099 00000 0 099909 ojo o o ojo 0 0 0000000 j ofo 6009000000 5 006 9 9 989 9 9 opo o 2000000020 0099000000 o 0 o o o 0000000000 0000000000 000000000000000 0000000000 OXoodododdoo000000060000000 00000000007 900000000 9990000000000000 0000000000 000000090000000 oo 0000000000 000000000000000 9900000000 0009000000
5. 165 16 10 2 3Counter 2 Speaker 2 nara sani 165 16 10 3 165 16 10 3 t Timer Prograrmmirng eden nro a exe nines Re 165 16 10 3 2Reading From the Interval 2 1222 166 PCU iLB High Precision Event Timer 168 16 11 1 Features reta rh 168 16 11 1 1Non Periodic Mode All 168 16 11 1 2 Mode Timer 0 168 16 11 2 O dS RADI 170 16 11 3 Memory Mapped Registers 170 PCUSILB GPIO 170 16 12 1 Signal DescriptiOnz is eese eerte nez a 172 16 12 2 GPIO Controller ite eite ine deretur tu Da Rd 172 16 12 172 16 12 4 GPIO REGISTERS eres eae al 173 16 12 4 1Memory Space Address Mapping 173 16 12 5 Register Address 173 16 12 6 Hard Strap
6. Pin Pin Name Pin Pin Name Pin Name 45 VSS AD29 CORE VCC1 SENSE DDR3 M1 DQ AT51 VSS AJ32 CORE VSSO SENSE DDR3 M1 DQ VSS AG32 CORE VCCO SENSE DDR3 M1 DQ 01 55 C35 USB3 TXP3 DDR3 M1 DQ VSS C34 USB3_TXP2 DDR3 M1 DQ AU51 VSS USB3 TXP1 DDR3 M1 DQ AU53 VSS B32 USB3 TXPO DDR3 M1 DQ 14 VSS A35 USB3 TXN3 DDR3 M1 DQ 19 VSS B34 USB3 TXN2 DDR3 M1 DQ AV24 VSS C33 USB3 TXN1 DDR3 M1 DQ AV27 VSS C32 USB3_TXNO DDR3 M1 DQ AV30 VSS G34 USB3 RXP3 DDR3 M1 DQ AV35 VSS G32 USB3 RXP2 DDR3 M1 DQ AV40 VSS F30 USB3 RXP1 DDR3 M1 DQ AW13 VSS F28 USB3_RXPO DDR3 DQ AW19 VSS 234 9583 RXN3 DDR3 M1 AW27 VSS 132 USB3 RXN2 DDR3 M1 DQ AW35 VSS D30 USB3 RXN1 DDR3 M1 DQ AW41 VSS D28 USB3_RXNO DDR3 DQ AY20 VSS D34 USB3 RCOMP P DDR3 M1 DQ 22 VSS F34 USB3_RCOMP_N DDR3_M1_DQ AY24 VSS B47 USB_VBUSSNS DDR3 M1 DQ AY26 VSS C37 RSVD DDR3 M1 DQ AY28 55 7 RSVD DDR3 M1 DQ AY3 VSS F36 RSVD DDR3 M1 DQ AY30 VSS D36 RSVD DDR3 M1 DQ AY32 VSS M34 RSVD DDR3 M1 DQ AY34 VSS M32 RSVD DDR3 M1 DQ 45 55 34 RSVD DDR3 M1 DQ AY47 VSS P34 RSVD DDR3 M1 DQ AY51 VSS A48 USB_RCOMP DDR3 M1 DQ VSS B48 USB_OTG_ID DDR3 DQ 9 vss P16 USB_OC1_N DDR3 M1 DQ 828 VSS 14 USB N DDR3 M1 DQ B36 VSS B46 RSVD DDR3 M1 DQ BA19 VSS N38 USB HSIC RCOMP DDR3 DQ 24 55 K38 USB
7. 0 4 44 411 1 emen ns 235 21 2405 2 0 Host DC Specification e corriere Een root Ro winged OX 235 21 25USB HSIC DC Electrical 5 4 4 2 4 44 41 237 21 26USB 3 0 DC Specification iier rie e 238 21 27LPC 1 8V Signal Group DC Specification 1 1 1 emen 238 21 28LPC 3 3V Signal Group DC Specification emnes 239 21 29 PCU SPI DC 2 een n tu enses gre 239 21 30Power Management 1 8V Suspend Well Signal Group DC Specification 239 21 31PMC_RSTBTN 1 8V Core Well Signal Group DC Specification 240 21 32Power Management RTC Well Signal Group DC 240 21 33RTC Well DG SpecifiCatiOn i iiie arte doe RR RA 240 21 34PROCHOT Signal Group DC 5 241 21 35SVID Signal Group DC Specification 5 DATA 5 SVID ALERT 241 21 36GPIO 1 8V Core Well Signal Group DC 242 21 37510 SPI DC Specifications 22 22 242 21 3917C Signal Electrical Specifications
8. use ome 58 RCOMP use 2 DDIO OBS N DDIO oss P RSVD Datasheet Volume 1 of 3 Ball Ball Out and SoC Pin Locations Figure 19 5 Map DDR3L Bottom Right View Columns 28 4 MM RTS UARTi UARTS_RX ARTI 58 D D Do RD RD PCIE COREPWR i E 7 PCIE RXN RSMRST_ _ AU PLTR 1 Bman _ SRTCRST _ 1 DIFF DIFF DIFF DIFF Pit P 2 Pla m RSV Nia cix _DIFF_ cx pit Plo NBI Datasheet Volume 1 of 3 _ _ DOCKENB 3 SLM SIMO RT UARTZ CT si 58 58 MMCiD D zd 7 5 1 Use Oct US amp 5 RCOMP _RCOMP pz 2 7 7 E 7 RVD SDMMC2 5 2 7 7 PCIE RXN MF HDA MF_HDA_ spo 501 _ _ DOCKRST UART2 RX UART2 TX D D FSI PL C FST SP sis MMCiD 5 450 5 0 SOMMCi po 2 22 197
9. 4 4 1 nann nnns 181 16 351 0 Registers Alias Locations iiid irte 186 17 1Signals Description osx 187 17 25 Feature ak See 188 18 15 Interrupts Generated From Events Packets 190 18 2Interrupt Generated for INT A D mnes 191 T9 1SOC Pit LOCATIONS siiis perdue 199 21 1SoC Base Frequencies and Thermal Specifications 216 21 2Storage Conditions Prior to Board 216 21 3SoC Power Rail DC Specifications and Maximum 5112 217 21 4VCC and DC Voltage 5 0 218 21 5VSDIO Voltage Setting ciere eoe eek nn iln daa de Rr n RR amd En n RT AIRE RE 218 21 6IMVP7 0 Voltage Identification Reference 1 eene nene 219 21 7ILB RIC Crystal Specification rein nena nna adn na a RENE 225 21 8Integrated Clock Crystal 5 226 21 9DisplayPort DC
10. 57 5 5 MER 57 5 5 1 c 57 5 5 2 E 57 5 5 3 58 5 6 Dynamic Platform Thermal Framework 1 1122 58 5 7 Thermal Status is stax P MEE 58 6 Power 2 444 4441 59 6 1 Power Management 59 6 2 Power Management States 22 12 2 59 6 2 1 EA cupi 59 6 2 2 Integrated Memory Controller 54 1111222 61 6 3 Processor Core Power 61 6 3 1 Enhanced Intel SpeedStep Technology 61 6 3 2 Dynamic Cache Sizing 61 6 3 3 Low Power Idle 54 lt nnn 62 6 3 3 1 Clock Control Low Power 62 6 3 4 Processor Core C States n 63 6 341 Core CO ea eene Cual uk adag 63 6 3 4
11. Platform Controller Unit PCU Overview Table 16 3 Transitions Due to Power Failure 16 2 2 2 16 2 2 2 1 Note Note Note Table 128 16 4 State at Power Failure 1 Bit Transition When Power Returns 50 i 50 54 5 50 55 5 50 Event Input Signals and Their Usage The SoC has various input signals that trigger specific events This section describes those signals and how they should be used PWRBTNZ Power Button The PMU_PWRBTN signal operates as a Fixed Power Button as described the Advanced Configuration and Power Interface specification The signal has a 16 ms debounce on the input The state transition descriptions are included in Table 16 4 The transitions start as soon as the PMU_PWRBTN is pressed but after the debounce logic and does not depend on when the power button is released During the time that the PMU SLP 54 signal is stretched for the minimum assertion width if enabled the power button is not a wake event See below for more details Transitions Due to Power Button Present 5 State Event Transition Action Comment PMU_PWRBTN goes SMI or SCI generated depending Software typically initiates 0 low on PM1 CNT SCI EN Sleep state 1 STS EN PWRBTN EN and SMI EN GBL SMI EN 54 55 PMU_PWRBTN goes Wake Event Transitions to SO Standard wakeup low state G3 PWRBTN None No e
12. RSTB SYNC 194 Datasheet Volume 1 of 3 Ball Ball Out and SoC Pin Locations n te Figure 19 3 Ball Map DDR3L Top Right View Columns 3 1 Nt pareti DDR3 NH Datasheet Volume 1 of 3 195 intel Ball Map Ball Out and SoC Pin Locations Figure 19 4 Ball Map DDR3L Bottom Left View Columns 53 29 196 SPIO 50510 Z GP C AMER ASBO3 DDEN TXP DDIO DDIO_TxP GPIO_ SUS1 GP CA MERAS 805 PANEL 0 BKL TEN DOC SDA B PANEL B _2 xucn 450 SEC GPIO_ 80811 _ AMER 5 04 PANEL 0 BKL TCTL eb DD SCL 0011 TXN TXN TXN TXN 2 p DDIO TXN 1 1 0 RVD PL OBS P DDIO AUX DDIO AUX mesiac 1 LKN 2 TX DOI2 GP 0011 P N oia TXN biz TxN 5 bi _
13. register There is no STOP condition before the repeated START condition and that a NACK signifies the end of the read transfer The Mem AUXC E32B bit in the Auxiliary Control register must set when using this protocol See section 5 5 8 of the System Management Bus SMBus Specification Version 2 0 for the format of the protocol Datasheet Volume 1 of 3 Platform Controller Unit Overview Note I C Read intel This command allows the SoC to perform block reads to certain 12 devices such as serial EEPROMs The SMBus Block Read supports the 7 bit addressing mode only However this does not allow access to devices using the I2C Combined Format that has data bytes after the address Typically these data bytes correspond to an offset address within the serial memory chips This command is supported independent of the setting of the SMB Config HCFG I2C EN bit The 12 Read command with the SMB Config HCTL PECEN bit set produces undefined results Software must force both the SMB Config HCTL PECEN and SMB Mem AUXC AAC bit to Ob when running this command For IC Read command the value written into SMB Mem TSA RW needs to be 1b The format that is used for the command is shown in the following table Table 16 13 12 Block Read Bit Description 1 Start 8 2 Slave Address 7 bits 9 Write 10 Acknowledge from slave
14. 1 000 185 Serial irren exe 187 17 1 Functional Feature Descriptions nne reri etai canes cates aca er ren 187 17 2 Signal Descriptions ntt ders itk ree 187 17 3 Iure ES 188 17 3 1 Supported Features peer nexa kane ER 188 17 3 2 Features Not Supported 1 188 17 4 SURE 188 PCI 2 0 Teide er Ex UPS Pees ee 189 18 1 Signal Descriptions crine 189 18 2 189 18 2 1 Root Port Corifig ratiOns 190 18 2 2 Interrupts and Events nn nnn 190 18 2 2 1 Express Card Hot Plug 1 1222 191 18 2 2 2 System Error isse ctn Ber nk hun nnm n 191 18 2 3 Power nine reina 191 18 3 References ies ga trea Lagu 192 Ball Map Bal
15. 86 9 3 3 Video iba 86 9 3 4 Ie EET 86 9 4 MIPI CSI 2 2 kk DENS AR MR QUARE ERR AERA USER 87 9 4 1 MIPI CSI 2 Receiver FeatUres an kann nnn 88 10 SoCStorage esce 91 1014 SoC Storage cere 91 10 1 1 Storage Control Cluster SDIO 0 91 10 2 Signal Descriptions eri TA 91 10 3 References Lamia Ua DRE 92 11 USB Controller Interfaces tu opea saxa 93 111 SOC SUPPOMS e 93 11 2 Signal Descriptioris RE 94 11 3 USB 3 0 xHCI Extensible Host Controller 95 11 3 1 Features of USB 3 0 ET 95 11 3 1 1 USB 3 0 5 tee codes 95 Datasheet Volume 1 of 3 5 13 14 15 11 3 2 Features of USB 95 11 4 asta d RR Rb art Uu SUR On E E 95 Low Power Engine LPE for Audio 126 22 97 12
16. Datasheet Volume 1 of 3 N3000 N3050 N3700 N3150 TDP 4W TDP 6W TDP 6W TDP 6W s3 s4 55 Power Rail SDP 3W 5 4 SDP 4W SDP 4W psu DC DC QC QC mA mA mA SO Imax SO Imax SO Imax Imax mA mA mA mA VCCO VCC1 merged 3600 3600 7700 7700 0 0 0 VGG 11000 11000 11000 11000 0 0 0 VNN 3500 3500 3500 3500 100 100 100 1 1900 2000 2000 2000 15 15 15 1 155 500 500 500 500 0 0 0 1 24 500 500 500 500 5 5 5 1 55 1 85 19 836 19 836 19 836 19 836 1 0 0 1 550 550 550 550 5 5 5 V3P3A PRIME 200 200 200 200 1 1 1 LPC IO 3 3V 147 59 147 59 147 59 147 59 1 1 1 VSDIO 3 3V 141 141 141 141 1 0 0 VSDIO 1 8V 93 93 93 93 1 0 0 VDDQ 1 35V 2400 2400 2400 2400 1 0 0 VCC RTC 100 100 100 100 10 10 10 Notes 1 VDDQ current is based on 1867 MT s 2 Iccmax for V1P15 in Sx state is lt 1 if it is configured as a always rail 217 intel Electrical Specifications 21 4 1 VCC VGG and VNN Voltage Specifications Table 21 4 and Table 21 18 list the DC specifications for the SoC power rails They are valid only while meeting specifications for junction temperature clock frequency and input voltages Care should be taken to read all notes associated with each parameter Table 21 4 VCC VGG and VNN DC Voltage Specifications Symbol Parameter Min Unit Notes CORE VCC VID
17. 5 DATA CMOS1 8 External pull up resistor is required This signal is multiplexed and may be used by other functions Datasheet Volume 1 of 3 m Platform Controller Unit Overview n tel 16 6 2 16 6 2 1 16 6 2 1 1 Features Host Controller The SMBus host controller is used to send commands to other SMBus slave devices Software sets up the host controller with an address command and for writes data and optional PEC and then tells the controller to start When the controller has finished transmitting data on writes or receiving data on reads it generates an SMI or interrupt if enabled The host controller supports 8 command protocols of the SMBus interface see System Management Bus SMBus Specification Version 2 0 Quick Command Send Byte Receive Byte Write Byte Word Read Byte Word Process Call Block Read Write and Block Write Block Read Process Call Additionally it supports 1 command protocol for 12 devices I C Read The SMBus host controller requires that the various data and command fields be setup for the type of command to be sent When software sets the START bit the SMBus Host controller performs the requested transaction and interrupts the processor or generates an SMI when the transaction is completed Once START command has been issued the values of the active registers Host Control SMB HCTL Host Command SMB HCM
18. 55 1 125 RXD GP 55 1 125 TXD 55 0 125 55 1 125 GP SSP 1 125 FS GP SSP 0 I2S RXD GP SSP 0 125 FS UARTi CTS UART1_RTS_N UART1_RXD UART1_TXD UART2_CTS_N UART2_RTS_N UART2_RXD UART2_TXD GPIO_ALERT 12 0 SCL I2CO SDA 2 SCL GPIO SoC Power Rail 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Vi 1 1 1 1 1 1 1 VI P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P5A P8A P5A P8A P5A P8A P5A P8A P5A P8A P5A P8A P5A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A P8A Pwrgood Assert State Input 20k PU Input 20k PU Input 20k PU Input 20k PD Input 20k PD Input 20k PU Input 20k PD Input 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PD Input 20k PD 0 20k PD 0 20k PD Input 20k PD 0 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PU 1 20k PU Input 20k PU 1 20k PU Input 20k PU 1 20k PU Input 20k PU 1 20k PU 0 20k PU Z 1k PU OD input Z 1k PU OD input Input 20k PU Resetout De assert State Input 20 Input 20 Input 20 Input 20 I
19. DDIO DATA Sus multiplexed with 1 0 V1P8A Input 20k PU Input 20k PU DDI1_DDC_DATA DDIO_HPD 1 0 V1P8A GPIDMV Input 20k PD Input 20k PD DDIO_VDDEN 0 0 DDIO BKLTCTL 1 0 V1P8A GPIONN 7 Output BKLTEN ene 7 Output DDIi TXP 3 0 V1P35 MODPHY 7 Output DDI1_TXN 3 0 V1P35 MODPHY 7 Output DDI1_AUXP 1 0 V1P35 MODPHY 7 Output DDI1_AUXN 1 0 V1P35 MODPHY 7 Output DDIi RCOMP 1 0 V1P35 MODPHY 7 Output DDIi RCOMP P 10 V1P35 MODPHY 7 Output BKLTCTL 1 0 V1P8A 7 Output DDI1_BKLTEN 1 0 V1P8A ii ud 7 Output DDI1_DDC_CLK V1P8A Input 20kPU Input 20k PU DATA 1 0 V1P8A GPIDMV Input 20k PU Input 20k PU DDI1_HPD 1 0 V1P8A GPIDMV Input 20k PD Input 20k PD DDIi VDDEN SEEN 0 0 DDI2 TXP 3 0 V1P35 MODPHY 7 Output DDI2_TXN 3 0 V1P35 MODPHY 7 Output AUXP 1 0 V1P35 MODPHY 7 Output 0012 AUXN 1 0 V1P35 MODPHY 7 Output 32 Datasheet Volume 1 of 3 Physical Interfaces intel Table 2 9 Digital Display Interface Signals Sheet 2 of 2 Default Buffer State Platform Pwrgood Assert Resetout Signal Name Dir Power Type State De assert State DDI2_DDC_CLK 1 0 V1P8A MS cle Input 20k PU Input 20k PU DDI2_DDC_DATA 1 0 V1P8A GPIOMV Input 20k PU Input 20k PU DDI2_HPD yo GPIOMV Input 20kPD Input 20k PD 2
20. 1 1 1 1 1 1 Pwrgood Assert State Input 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PU nput 20k PU nput 20k PU Input 20k PU nput 20k PU nput 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PU Input 20k PU Input 20k PU Input 20k PU Z 5k PU OD Input 5k PU OD Input 5k PD Input 5k PU 2 Input 5k PU Input 5k PU Input 20k PU 0 20k PD Input 20k PD Input 20k PU Resetout De assert State 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k 20k Z PU OD 2 PU OD Z PU OD 2 PU OD Z PU OD 2 PU OD 2 PU OD 2 PU OD 2 PU OD 2 PU OD 2 PU OD Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU 2 20 2 20 2 20 7 20k PU OD Output 5k PU OD Input 5k PU OD Input 5k PD Input 5k PU 2 Input 5k Input 5k PU Input 20k PU SLP Input Input 20k PU intel Optional Modes Direction Mode2 DDIO DDC SCL O Mode3 DDI2 DDC SCL O Mode2 HV DDIO DDC SDA IO Mode3 HV 0012 SDA IO M
21. And the platform requests a higher power C State the memory access or snoop request is serviced and the package remains in the higher power C State 64 Datasheet Volume 1 of 3 intel Table 6 6 6 3 5 1 6 3 5 2 6 3 5 3 Coordination of Core Module Power States at the Package Level Core Module 1 Package C State co 6 5 C6FS C7 CO CO CO CO CO o z CO Git Cii Cii cii 79 S C6NS CO Cii C6 C6 M 5 C6FS CO C6C C6 C6 7 Cii C6 C7 Notes 1 If enabled the package C State will be if all actives cores have resolved core Ci state or higher 2 C6NS implies only the core should be powergated but the L2 cache contents should be retained 3 C6FS implies the core should be powergated and the L2 cache can be fully flushed to get even more power savings 4 C6Cis C6 Conditional where the L2 cache is still powered 5 Two cores of the SoC will make up one module Package CO State The normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO State or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO State Package C1 C1E State No additional power reduction actions are taken in the package C1 State However if the sub state is enab
22. 140 16 4 3 1 Base 21 2 ne A Dean os 140 16 4 3 2 Legacy 2 2 2 ces ceeds race 140 16 4 4 UART Enable Disable seite gea DR A NAR IAN 141 16 4 5 I O Mapped Registers sank nnn 141 16 5 Register edited 141 16 6 X PCU System Management Bus SMBUS 142 16 6 1 Signal Descriptions n taeda 142 16 6 2 Bzjdisnge LIAE 143 16 6 2 1 Host Controller ia gies 143 16 6 2 2 BUS APDItratiOn smem soeren DU E 148 16 6 2 3 BUS TIMIN pr e E NR ERE 148 16 6 2 4 Interr pts SMLI 148 16 6 2 5 5 iioii inia Dre adi sa nen EE RR RIA 150 16 6 2 6 SMBus CRC Generation and Checking 150 16 6 2 7 SMBUS Slave na 150 16 6 2 8 Function lt ninh 151 Datasheet Volume 1 of 3 7 16 7 16 9 16 10 16 11 16 12 16 13 16 6
23. 4 xis 2 x2 s 1 x2 plus 2 xis 1 Interrupts and Events Legacy MSI Interrupts General Purpose Events Express Card Hot plug Events System Error Events Power Management Link State support for LOs L1 and L2 Powered down in ACPI S3 state L3 Datasheet Volume 1 of 3 189 18 2 1 Root Port Configurations Depending on SKU there are up to four possible lane assignments for root ports 1 4 Figure 18 2 Root Port Configuration Options Note Note 18 2 2 Table 18 1 190 4 x1 1 x2 2 x1 2 0 2 0 1 x4 2 x2 2 0 2 0 Root Port 1 Root Port 1 Root Port 2 Root port configurations are set by SoftStraps stored in SPI flash and the default option is 4 x1 Links for each root port will train automatically to the maximum possible for each port x2 link widths are not common Most devices will only train to x1 or x4 PCI functions in PCI configuration space are disabled for root ports not available Interrupts and Events A root port is capable of handling interrupts and events from an end point device A root port can also generate its own interrupts for some events including power management and hot plug events but also including error events There are two interrupt types a root port will receive from an end point device legacy and MS
24. Input Low Voltage 0 3 Vner V 1 Input High Voltage 0 65 V 21 6 23 Serial ATA SATA DC Specification Refer to the SATA Revision 3 2 for the latest specification 88 244 Datasheet Volume 1 of 3
25. t acide sa ERR QR P 126 16 3Transitions Due to Power an sani unn 128 16 4Transitions Due to Power Button senes nennen nnn nn nnn 128 16 5System enitn caa saa Fa Eur 130 16 6Causes of SML arid SCI dtu seh nne rn bd a mea ERR REOR DEOR EATUR E a RR A 131 16 7INIT Assertiori CAUSES 133 16 8SPLSignals Uta a qae LR RA a 134 16 9UART SignalS MEM Ida I AELIAN piat 138 16 10Baud Rate Examples reri oae arn o E RR acu NOR RR C A 139 lo liRegister Access a ARI UA 141 16 12SMBus Signal scr eet pennae a 142 16 131C Block tob 147 16 14Enable for PCU SMB ALERT pedea a ska Ce DER Rus 149 16 15Enables for SMBUS Host 22 2 22 2 ceeds da aca se reas 149 16 16Enables for the Host Notify Command 111 eene eee nnns 149 16 17 5 Notify F rMaAT PET 150 T6 I8IDB Sigrials uses eR aat e
26. 92 10 355 SIGNAIS 92 IB ESREISISESIIIIr EC 94 I11 2HSIC SignalS dese niat 94 T231 LPE Signals terere e e LEUTE 97 12 2Clock Erequencies iore obest dex ane 102 12 3M N Values Exatrples i erue ciere enia nnd sean ON UE I ERR E EAR RR ZUR aa RIA 105 12 4M N Configurable Fields 105 12 5Programmable Protocol 44 44 4 110 14 1510 5 Descriptio a 114 15 1SPI Interface Signals niea nas FRE bene 115 15 212C 6 0 Signals ta rene Tu eeu te Qu awed Dr 116 Datasheet Volume 1 of 3 15 3UART 1 Interface Signals 119 15 4UART 2 Interface Signals ERR Ca eor Ex Ra 120 15 5Baud Rates Achievable with Different DLAB 665 1 121 16 1BBS Configurations 126 16 2PMC Sighals erani
27. PWRBTN S4 SUS STAT SUSCLK 3 0 SUSPWRDNACK 2 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value 3 Vy is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value Table 21 31 PMC_RSTBTN 1 8V Core Well Signal Group DC Specification value value Symbol Parameter Min Typ Max Units Notes VREF Voltage UNCORE_V1P8_G3 V Input High Voltage 0 65 VREF 1 Vit Input Low Voltage 0 35 VREF V 2 Notes 1 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low Table 21 32 Power Management and RTC Well Signal Group DC Specification Symbol Parameter Min Units Notes VREF I O Voltage RTC V3P3RTC G5 Input High Voltage 2 0 1 Input Low Voltage 0 78 2 Notes 1 defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 Vi is definea as the minimum voltage level at a receiving agent that will be interpreted as a logical low value Table 21 33 RTC Well DC Specification Symbo
28. capitan rate calce ni ra e bab de 242 21 39HD Audio DC Specifications for 1 5 tren hr da aha 243 21 40HD Audio Specification for 1 8 243 21 41SMBus DC Specification chee 244 21 42 PCI Express DC Receiver Signal 10212 122 244 21 43 PCI Express DC Transmit Signal Characteristics 001 12122 244 21 44 PCI Express DC Clock Request Input Signal 244 Datasheet Volume 1 of 3 intel Revision History Revision Number 001 Initial release Description Revision Date April 2015 Datasheet Volume 1 of 3 88 15 em G 16 Datasheet Volume 1 of 3 Introduction 1 Introduction The N series Intel Pentium processor and Intel Celeron processor families are the Intel Architecture IA SoC that integrates the next generation Intel processor core Graphics Memory Controller and I O interfaces into a single system on chip solution The following figure shows the system level block diagram of the SoC Refer to the subsequent chapters for detailed information on the functionality of the different interface blocks This document is distributed as a part of the complete Datasheet document consisting of three volume
29. defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 as the minimum voltage level at a receiving agent that will be interpreted as logical low Mesures G3 4 Rwpu 20k and _40 only used for JTAG_TRST Table 21 21 JTAG Signal Group DC Specification JTAG TDO Symbol Parameter Min Units Notes VREF I O Voltage GPIO 1 Input High Voltage 0 75 VREF V 1 Vu Input Low Voltage 0 45 VREF V 2 Zpd Pull down Impedance 17 5 35 Q 3 Notes 1 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 vce as the minimum voltage level at a receiving agent that will be interpreted as a logical low 35 GPIO G3 Table 21 22 JTAG Signal Group DC Specification PRDYZ JTAG PREQZ Symbol Parameter Min Typ Max Units Notes VREF I O Voltage GPIO 1 Input High Voltage 0 75 VREF V 1 Input Low Voltage 0 45 VREF V 2 Zpd Pull down Impedance 17 5 35 3 Notes 1 defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 Vi ls define as the minimum voltage level at a receiving agent that will be interpreted as a logical low value 3 Measured at GPI
30. 1 20k PD 0 20k PD Input 20k PU Resetout De assert State Input 20 Input 20 Input 20 Input 20 1 Input 20 20 Input 20 0 20 Input 20 Input 20 Input 20 Input 20 Clock 20 Clock 20 Clock 20 Clock 20 Clock 20 Clock 20 Input 20 Input 20 1 Input 20 Input 20 k PU k PU k PU k PU k PD k PD k PD PD k PU k PU k PU k PU k PD k PD k PD k PD k PD k PD k PD k PU k PU k PU 32KHz Clock Input 20 Input 20 1 0 20k 0 0 Input 20 Input 20 0 20k 0 20k PRG 0 Input 20 k PU k PU PD PD PD PD PD k PU Physical Interfaces Optional Modes Direction Mode2 UARTO TXD O Mode2 UARTO RXD I Mode2 SDMMC3 WP I Mode2 MMC1 RESET Mode2 UARTO_RXD I Datasheet Volume 1 of 3 Physical Interfaces Table 2 27 GPIO Multiplexing and Modes Sheet 6 of 6 Count 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 SoC Pin No F2 D2 Ji 13 H3 G2 L3 K10 K9 M12 M10 K7 K6 AM9 AM6 AM7 H4 14 Y13 Yi2 V13 12 40 42 41 AD50 P14 P16 CFIO Name SDMMC3 SDMMC3 CMD SDMMC3 DO SDMMC3 Di SDMMC3 D2 SDMMC3_D3 SDMMC3_PWR_EN_N SDMMC2_CLK SDMMC2_CMD SDMMC2 DO SDMMC2 Di SDMMC2 D2
31. Display Datasheet Volume 1 of 3 MIPI CSI Camera Serial Interface and ISP tel 9 MIPI CSI Camera Serial Interface and ISP 9 1 Signal Descriptions Table 9 1 CSI Signals Signal Name Direction Description MCSI1 CLKP N I Clock Lane MIPI CSI input clock lane 0 for port 1 Data Lanes Four MIPI CSI Data Lanes 0 3 for port 1 Lanes 2 511 DP N 3 0 and 3 can optionally used as data lanes for port 3 MCSI2 CLKP N I Clock Lane MIPI CSI input clock lane 0 for port 2 MCSI2 DP N 1 0 I Data Lane MIPI CSI Data Lanes for port 2 MCSI3 CLKP N I Clock Lane MIPI CSI input clock lane 0 for port 3 MCSI RCOMP Resistor Compensation This is pre driver slew rate compensation for the MIPI CSI Interface Table 9 2 Signals Signal Name Direction Description Type Output from shutter switch when its pressed halfway This switch GP_CAMERASBOO I O state is used to trigger the Auto focus LED for Xenon Flash or Torch mode for LED Flash Output from shutter switch when its pressed full way This switch Hn state is used to trigger Xenon flash or LED Flash Active high control signal to Xenon Flash to start charging the CAMERASBO2 I O Capacitor Active low output from Xenon Flash to indicate that the capacitor is GP CAMERASBO3 1 9 fully charged and is ready to be triggered GP 5 04 I O Activ
32. aid 174 PCU iLB Interrupt Decoding and eem 174 Datasheet Volume 1 of 3 17 18 19 20 21 16 13 Features 175 16 13 1 1Interrupt 4 175 16 13 1 21 iR RAD PER 175 16 14 PCU ILB I O UK D 175 16 14 1 I II 176 16 14 2 178 16 14 3 Indirect I O Registers etn ehe n da tarnen 178 16 15 PCU iLB 8259 Programmable Interrupt Controllers PIC 179 16 15 l Features sce 179 16 15 1 1Interrupt Handling 180 16 15 1 2Initialization Command Words ICWX 181 16 15 1 30peration Command Words OCW 182 16 15 1 4Modes of Operation ka terea sede sa 183 16 15 1 5End of Interrupt EOI 184 16 15 1 6Maskirig Interrupts ede ehe rene dpa gen aed ge 185 16 15 2 I O Mapped Registers
33. bee aa 4KB CCM 160KB 96KB Instruction Closely Coupled Memory CCM Instruction CCM for the core is used for loading commonly used routines as well as time critical processing Examples of time critical processing are acoustic echo cancellation and noise cancellation during voice calls Instruction CCM is initialized after reset by an external DMA controller Runtime update of instruction CCM can be done either using explicit instructions or using an external DMA controller with inbound access Data Closely Coupled Memory CCM Data CCM can be initialized after reset by an external DMA controller using inbound access Runtime update of data CCM can be done either using stores to Data CCM or using an external DMA controller with inbound access Mailbox Memory and Data Exchange The mailbox memory is a shared memory region in LPE address space that is accessible by the SoC Processor Core PMC and LPE It is used when Doorbell registers cannot hold all the information that one processor wishes to communicate to the other A typical example of such data blocks are audio stream related parameters when starting a new stream The structures of data communicated through the mailbox are not defined in hardware so that software may partition the mailbox memory in any desired way and create any meaningful structures required Datasheet Volume 1 of 3 Low Power Engine LPE for Audio 125 n tel 12 4 12 4 1 1
34. display registers be accessed by HD Audio N A Yes Yes LPE Audio N A No No Compressed Audio N A Yes Yes SoC Display supported Resolutions 1 Display only 2 Displays 2 Displays 3 Displays 1 Internal 1 Internal 1 Internal 1 Internal 1 External 1 External 1 WIDI 2 Externals 2 Externals Int eDP eDP eDP eDP zs 2560x1440 N A 2560x1440 2560x1440 N A 2560x1440 60Hz 60Hz 60Hz 60Hz HDMI DP HDMI DP HDMI DP HDMI DP Ext 3840 2160 3840 2160 WIDI 3840x2160 3840x2160 HW N A 30Hz 30Hz 1920x1080 30Hz 30Hz 2560x1600 2560x1600 30Hz 2560x1600 2560x1600 60Hz 60Hz 60Hz 60Hz HDMI DP HDMI DP Ext 3840 2160 3840 2160 2 a N A N A N A N A 30Hz 30Hz 2560x1600 2560x1600 60Hz 60Hz Notes 1 SoC supported maximum of 3 simultaneous displays External display in both clone and extended modes 2 WiDi resolution dependent on antenna configuration 1080p assumes 2 2 and expect 720p for 1x1 3 Experience may differ based on configuration resolution and work loads High Definition Multi media Interface HDMI The High Definition Multi media Interface HDMI is provided for transmitting digital audio and video signals from DVD players set top boxes and other audiovisual sources to television sets projectors and other video displays It can carry high quality multi channel audio data and all standard and high definition consumer electronics video formats HDMI display interface conn
35. 0 45 V 1 Output High Current 2 1 Output Low Current 2 mA 1 Notes 1 Applies to SPI1 CS 1 0 SPI1 SPI1 MOSI 2 Applies to SPI1 MISO and SPI1 3 I O buffer supply voltage is measured at the SoC package pins The tolerances shown are inclusive of all noise from DC up to 20 MHz In testing the voltage rails should be measured with a bandwidth limited oscilloscope that has a rolloff of 3 dB decade above 20 MHz 21 6 17 SIO I C DC Specification Table 21 38 I C Signal Electrical Specifications Symbol Parameter Min Units Notes VREF T O Voltage V1P8_G3 Input High Voltage 0 7 VREF V Input Low Voltage 0 3 VREF V VoL Output Low Voltage 0 2 VREF V Vuys Input Hysteresis 0 1 V Pin Capacitance 2 5 pF 242 Datasheet Volume 1 of 3 Electrical Specifications n tel 21 6 18 SIO UART DC Specification Refer to the GPIO Buffer 1 8V DC Specification that is mentioned in Section 21 6 15 GPIO DC Specification on page 242 21 6 19 12 Audio DC Specification Refer to the GPIO Buffer 1 8V DC Specification that is mentioned in Section 21 6 15 GPIO DC Specification on page 242 21 6 20 High Definition Audio DC Specifications Table 21 39 HD Audio DC Specifications for 1 5V Symbol Parameter Min Typ Max Units Notes Vec Suppl
36. 000000000 20050590000 0000 00000000000000000 500000000 900000090000000 0000000000 90290000000 220000000000000 1 os 000009 ggg 000000000000 999000 tro 09000000009 000000090000000 99009902999 coo 00000000 00000000 dio 900000000 2 808 5 9 90 E 059 9 0000980009 lt 500 o 2 0 9904000000 0090000 0 o 000 0000000 000000000 0000000 o 9998 0 o odo o o 0000 o o 0909990 9 0 0 0 050 o o Of9 o o opo o 0 o 0 00 9909 99 559205 52 955205 95 9 99 0540 9 9002000 0 0 99 00000 0 00009 08096 950 000 9090 5909090959099909595909090959090 eee t ali as 195689 ET Datasheet Volume 1 of 3 212 Package Information Figure 20 2 Package Mechanical Drawing Part 2 of aan 4 2 88 Datasheet Volume 1 of 3 213 n Package Information 214 Datasheet Volume 1 of 3 m e Electrical Specifications n tel 21 21 1 21 2 Caution Note Electrical Specifications Absolute Maximum and Minimum Specifications The absolute maximum and minimum specifications are used to specify conditions allowable outside of the functional limits of the SoC but with possible reduc
37. 168 Platform Controller Unit PCU Overview PCU iLB High Precision Event Timer This function provides a set of timers that to be used by the operating system for timing events One timer block is implemented containing one counter and three timers HPET operation is not guaranteed when LPC clock is running at 25MHz Designs needing LPC to be at 25 MHz should use an alternate timer like TIMER LAPIC timer for their application Platform Control Unit High Precision Event Timer HPET Platform Control Unit iLB Features Non Periodic Timers This mode can be thought of as creating a one shot When a timer is set up for non periodic mode it generates an interrupt when the value in the main counter matches the value in the timer s comparator register As timers 1 and 2 are 32 bit they will generate another interrupt when the main counter wraps TOCV cannot be programmed reliably by a single 64 bit write in a 32 bit environment unless only the periodic rate is being changed If TOCV needs to be re initialized the following algorithm is performed 1 Set TOC TVS 2 Set TOCV 31 0 3 Set TOC TVS 4 Set TOCV 63 32 Every timer is required to support the non periodic mode of operation Periodic Mode Timer 0 Only When set up for periodic mode when the main counter value matches the value in TOCV an interrupt is generated if enabled Ha
38. Figure 8 4 3 D Graphics Block Diagram 8 3 1 8 3 2 8 3 3 8 3 3 1 76 Command Multi Format Streamers Media Processing Codec Display Media Sampler Sampler Pixel Ops Features The 3 D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3 D Engine The Gen 8 0 LP 3 D engine provides the following performance and power management enhancements e Hierarchal Z Video quality enhancements 3 D Engine Execution Units The EUs perform 128 bit wide execution per clock Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing 3 D Pipeline Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL Datasheet Volume 1 of 3 m e Graphics Video and Display n tel 8 3 3 2 8 3 3 3 8 3 3 4 8 3 3 5 8 3 3 6 8 4 Vertex Shader VS Stage The VS stage performs shading of vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorith
39. Nominator Target_clock Denominator Source clock Example To generate 17 64 MHz 400 x 44 1 KHz output clock out of 25 MHz clock you need to program NOM 441 and DENOM 625 17 64 MHz 441 625 x 25 MHz In general the M over N can generate fractional devisor that could be used for generating the required clocks for audio codec Table 12 3 describes some configuration options of this generic divider Datasheet Volume 1 of 3 m Low Power Engine LPE for Audio 126 tel Table 12 3 12 5 6 2 12 5 6 3 Table 12 4 12 6 12 6 1 M N Values Examples Clock Requested Clock M N Value requency 48 KHz 6 3125 48K x 24 1 152 MHz 1152 25000 48K x 32 1 536 MHz 1536 25000 25 MHz 48K x 64 3 072 MHz 3072 25000 44 1 KHz 441 250000 48K x 400 19 2 MHz 96 125 44 1K x 400 17 64 MHz 441 625 Accuracy and Jitter The output of the M N is equal to the desired clock in average with Jitter of 20nTXE for 25 MHz input clock Configuration The following configurable fields per M N divider SSP are in LPE shim registers M N Configurable Fields Field Width Description Bypass 1 bit When set M N divider is bypass Clock from CCU is connected directly to SSP CCLK Update 1 bit Update divider parameters M Value 20 bits Nominator value N Value 20 bits Denominator value SSP I S The SoC audio subsystem consist
40. m Platform Controller Unit PCU Overview 16 4 1 Signal Descriptions Table 16 9 UART Signals Direction Type Description Signal Name COM1 Receive Serial data input from device to the receive port I This signal is multiplexed and may be used by other GPIO UART functions Note Refer to Section 2 4 Hardware Straps on page 40 to get more details UARTO_RXD 1 Transmit Serial data output from transmit port to the device pin This signal is multiplexed and may be used by other GPIO UART functions Note Refer to Section 2 4 Hardware Straps on page 40 to get more details UARTO Notes 1 These signals are part of PCU Logic 2 Among others these signals are multiplexed with LPC CLKRUN and LPC FRAME Enabled in Mode2 16 4 2 Features The serial port consists of a UART which supports a subset of the functions of the 16550 industry standard The UART performs serial to parallel conversion on data characters received from a peripheral device and parallel to serial conversion on data characters received from the processor The processor may read the complete status of the UART at any time during the functional operation Available status information includes the type and condition of the transfer operations being performed by the UART and any error conditions The serial port may operate in either FIFO or non FIFO mode In FIFO mode a 16 byte t
41. m e n tel Ball Map Ball Out and SoC Pin Locations Figure 19 6 Ball Map DDR3L Bottom Right View Columns 3 1 SUSPWRD NACK 5 12 lt _ 2 125 5 sciL SDA 12cs sci imm Sci sce gt 198 Datasheet Volume 1 of 3 Ball Ball Out SoC Pin Locations 19 1 SoC Pin List Locations Table 19 1 SoC Pin List Locations Sheet 1 of 11 Pin Pin Name Pin Pin Name Pin Pin Name M24 VSSA Y30 VCCSRAMSOCIUN 1P05 T44 MCSI 1 CLKP A5 VSS Y32 VCCSRAMSOCIUN 1 05 T45 51 1 VSS Y33 VCCSRAMSOCIUN 1 05 B2 VSS NCTF Y35 VCCSRAMSOCIUN 1 05 B52 VSS_NCTF AK21 VCCSRAMGEN 1P15 BG1 VSS_NCTF AM19 VCCSRAMGEN_1P15 RSVD BG53 VSS_NCTF AA18 UNCORE_VNN_S4 LPC_HVT_RCOMP BH1 VSS_NCTF 19 UNCORE_VNN_S4 FRAME BH2 VSS 21 UNCORE VNN 54 LPC_CLKRUN_N BH52 VSS_NCTF 22 UNCORE_VNN_S4 RSVD_VSS BH53 VSS_NCTF 24 UNCORE_VNN_S4 ILB_SERIRQ VSS_NCTF 25 UNCORE_VNN_S4 ICLKRCOMP F1 VSS_NCTF AC18 UNCORE_VNN_S4 ICLKICOMP 11 VSS AC19 UNCORE_VNN_S4 2 6 SDA 15 VSS 21 UNCORE 54 2 6 SCL 19 VSS 22 UNCORE 54 I2C5 SDA A23 VSS AC24 UNCORE_VNN_S4 I2C5 SCL A31 VSS 25 UNCORE 54 I2C4 SDA A39 VSS AD25
42. 10 DDR3_M1_CKE 0 BF22 VSS AD13 UART1_CTS_N 16 DDR3_M1_CKB 1 BF26 VSS 48 TRST_N 14 DDR3_M1_CKB 0 BF27 VSS AD48 TMS BDi6 DDR3 CK 1 BF28 VSS P30 RSVD BD14 DDR3 CK 0 BF32 VSS 28 RSVD BG9 DDR3 1 CAS BF4 VSS AF40 TDO BF2 DDR3 M1 BS 2 BF42 VSS AD47 TDI AY14 DDR3_M1_BS 1 BF50 VSS AF42 TCK DDR3 BS 0 BG14 VSS AD41 SVIDO DATA BH44 WE BG16 VSS AD42 SVIDO_CLK BA28 DDR3 MO RCOMP BG18 VSS AD40 SVIDO_ALERT_N BA40 DDR3 MO RAS N BG19 VSS AE3 SUSPWRDNACK BA38 DDR3 MO ODT 1 BG20 VSS 014 505 5 AV36 DDR3 MO ODT 0 BG24 VSS D18 SRTCRST N AU28 DDR3 MO ODQVREF BG27 VSS H4 SPKR AT28 DDR3 MO OCAVREF BG30 VSS V12 SPI1 MOSI AT30 RSVD 204 Datasheet Volume 1 of 3 Ball Ball Out SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 7 of 11 Pin Pin Name Pin Pin Name BG34 VSS V13 SPI1 MISO RSVD BG35 VSS Y12 SPI1 CS1 N DDR3 MO MA BG36 VSS Y13 SPI1 CSO N DDR3 MO MA BG38 55 14 SPI1 DDR3 BG40 VSS 226 RSVD DDR3 MO MA BG47 VSS K26 RSVD DDR3 MO MA BG49 VSS N26 RSVD DDR3 MO MA BG5 VSS AF52 SEC 5059 DDR3 MO MA BG7 VSS AF51 SEC 5058 MO 11 VSS 5
43. 16 4 2 1 2 16 4 3 16 4 3 1 16 4 3 1 1 16 4 3 2 16 4 3 2 1 140 The maximum time between a received character and a timeout interrupt is 160 ms at 300 baud with a 12 bit receive character that is 1 start 8 data 1 parity and 2 stop bits When a time out interrupt occurs it is cleared and the timer is reset when the processor reads one character from the receiver FIFO If a time out interrupt has not occurred the time out timer is reset after a new character is received or after the processor reads the receiver FIFO Transmit Interrupt When the transmitter FIFO and transmitter interrupt are enabled FIFO Control Register bit 0 1b and Interrupt Enable Register bit 0 1b transmit interrupts occur as follows The Transmit Data Request interrupt occurs when the transmit FIFO is half empty or more than half empty The interrupt is cleared as soon as the Transmit Holding Register is written 1 to 16 characters may be written to the transmit FIFO while servicing the interrupt or the Interrupt Identification Register is read FIFO Polled Mode Operation With the FIFOs enabled FIFO Control register bit 0 1b setting Interrupt Enable register IER bits 3 0 000b puts the serial port in the FIFO polled mode of operation Since the receiver and the transmitter are controlled separately either one or both may be in the polled mode of operation In this mode software checks receiver and transmitter status through
44. 193 19 2Ball Map DDR3L Top Right View Columns 28 4 sese 194 19 3Ball Map DDR3L Top Right View Columns 3 1 sessssssssesn memes 195 19 4Ball Map DDR3L Bottom Left View Columns 53 29 196 19 5Ball Map DDR3L Bottom Right View Columns 28 4 197 19 6Ball Map DDR3L Bottom Right View Columns 3 1 198 20 1Package Mechanical Drawing Part 1 3 sss eene 212 20 2Package Mechanical Drawing Part 2 000 emen eene 213 21 1Definition of Differential Voltage and Differential Voltage 231 21 2Definition of Pre Emphiasis croce nenne an rH REN d a E RR E E A 231 21 34 51 DC Bus Signal chalet d ad a 233 21 4Definition of VHYS in the DDR L Interface Timing 5 2 241 Tables 1 1 Structure of the Processor Datasheet sss seen nene een 19 1 2 Related Documents 2 E 26 2 1 Platform Power Well 5 nen eene sees 27 2 2 Buffer Type Definitions dee a ax ARR 28 2 3 Default Memory Controller Interface meme 28 2 4 DDR3L
45. 2 2 1 Table 2 4 Default Memory Controller Interface Signals Sheet 2 of 2 intel Buffer State Description Off The power plane for this signal is powered down The processor does not drive outputs and inputs should not be driven to the processor VSS on output 1 Buffer drives 0 Buffer driver VoL H Buffer Hi Z weak PU default to 20k unless explicitly specified otherwise L Buffer Hi Z weak PD default to 20k unless explicitly specified otherwise Input H Input enable weak PU Output L Output enable weak PU Pgm Programmable Retrain Retrain configuration data prior to standby SoC Physical Signal Per Interface This section lists signals groups of each interface and describes the states of each signal during supported buffer states System Memory Controller Interface Signals DDR3L DDR3L System Memory Signals Sheet 1 of 2 Default Buffer State Signal Name Dir Platform Type Pwrgood Assert Resetout Power State De assert State DDR3 MA 15 0 VDDQ V1P35 DDR3 2 2 DDR3 MO CK 1 0 P VDDQ V1P35 DDR3 2 2 DDR3 MO CK 1 0 VDDQ V1P35 DDR3 2 2 DDR3_MO_CKE 1 0 VDDQ V1P35 DDR3 Weak 0 0 DDR3 MO CS 1 0 N VDDQ V1P35 DDR3 2 2 DDR3 CAS VDDQ V1P35 DDR3 2 2 DDR3 MO RAS VDDQ V1P35 DDR3 2 2 DDR3 MO WE VDDQ V1P35 DDR3 2 2 DDR3 BS 2 0 VDDQ V
46. Fi 113 114 AD45 41 AF42 AD47 AF40 AD48 AB48 T2 P2 R3 M3 CFIO Name 2 SDA 2C2 SCL I2C2 SDA 2C3 SCL 2C3 SDA 2C4 SCL I2C4 SDA I2C5 SCL I2C5 SDA I2C6 SCL I2C6 SDA MF ISH GPIO 0 MF ISH GPIO 1 MF ISH GPIO 2 MF ISH GPIO 3 MF ISH GPIO 4 MF ISH GPIO 5 MF ISH GPIO 6 MF ISH GPIO 7 MF 5 8 5 9 ISH 2 SDA ISH 2 SCL CX PRDY CX PREQ N TCK TDI TDO TMS TRST N ILB SERIRQ MF LPC CLKOUTO MF LPC CLKOUT1 MF LPC ADO Datasheet Volume 1 of 3 Default Mode Brel el ele el eye Default Function 2 1 SDA I2C2 SCL 2C2 SDA I2C3 SCL 2C3 SDA I2C4 SCL I2C4 SDA I2C5 SCL I2C5 SDA I2C6 SCL I2C6 SDA ISH GPIO 0 ISH GPIO 1 ISH GPIO 2 ISH GPIO 3 5 GPIO 4 5 GPIO 5 5 GPIO 6 5 7 5 GPIO 8 5 GPIO 9 ISH 12 1 SDA ISH 2 SCL PRDY N PREQ N TCK TDI TDO TMS TRST N ILB SERIRQ LPC CLKOUTO LPC CLKOUT1 LPC ADO GPIO SoC Power Rail V1P8A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
47. INTD Root Port 2 INTD INTA INTB INTC Root Port 3 INTC INTD INTA INTB Root Port 4 INTB INTC INTD INTA Interrupts generated from events within the root port are not swizzled Express Card Hot Plug Events Express Card Hot plug is available based on Presence Detection for each root port A full Hot plug Controller is not implemented Presence detection occurs when a PCI Express device is plugged in and power is supplied The physical layer will detect the presence of the device and the root port will set the SLSTS PDS and SLSTS PDC bits When a device is removed and detected by the physical layer the root port will clear the SLSTS PDS bit and set the SLSTS PDC bit Interrupts can be generated by the root port when a hot plug event occurs A hot plug event is defined as the transition of the SLSTS PDC bit from 0 to 1 Software can set the SLCTL PDE and SLTCTL HPE bits to allow hot plug events to generate an interrupt If SLCTL PDE and SLTCTL HPE are both set and STSTS PDC transitions from 0 to 1 an interrupt will be generated System Error SERR System Error events are support by both internal and external sources See the PCI Express Base Specification Rev 2 0 for details Power Management Each root port s link supports LOs Li and L2 3 link states per PCI Express Base Specification Rev 2 0 L2 3 is entered on entry to S3 Datasheet Volume 1 of 3 191 intel PCI Express 20
48. S5 DIS 15 Ob PMCON1 WOL OVRD 13 Ob GEN_PMCON1 DIS_SLP_X_STRCH_SUS_UP 12 Ob GEN_PMCON1 RTC Reserved 8 Ob GEN_PMCON1 SWSMI_RATESEL 7 6 00b GEN_PMCON1 S4MAW 5 4 00b GEN_PMCON1 S4ASE 3 Ob GEN_PMCON1 AG3E 0 Ob 1 575 26 Ob PM1_STS_EN PWRBTNOR_STS 1i Ob 1 CNT SLP 12 10 Ob GPEOa EN PME BO EN 13 Ob GPEOa EN BATLOW EN 10 Ob Note RST will not set PMCONI RPS This bit is only set when R_TEST is asserted low When the system is rebooted 1 5 bit can be detected in the set state Using a GPI to Clear CMOS A jumper on a GPI can also be used to clear CMOS values BIOS should detect the setting of this GPI on system boot up and manually clear the CMOS array The GPI strap technique to clear CMOS requires multiple steps to implement The system is booted with the jumper in new position then powered back down The jumper is replaced back to the normal position then the system is rebooted again Do not implement a jumper on RTC VCC to clear CMOS References Accessing the Real Time Clock Registers and the NMI Enable Bit http download intel com design intarch PAPERS 321088 pdf I O Mapped Registers The RTC internal registers and RAM is organized as two banks of 128 bytes each called the standard and extended banks It is not possible to disable the extended bank The first 14 bytes of the standard bank contain the RTC time and date information
49. U43 VSS F7 RSVD F40 DDI2 TXP 0 045 VSS 112 RSVD F44 DDI2 TXN 3 046 VSS D6 RSVD G42 DDI2 TXN 2 048 VSS C7 RSVD K40 DDI2_TXN 1 U49 VSS E8 RSVD G40 DDI2_TXN 0 U5 VSS D12 RSVD 248 DDI2 AUXP U53 VSS F10 RSVD C49 0012 AUXN U6 VSS F12 RSVD M52 0011 TXP 3 U8 VSS B10 RSVD L53 DDI1 TXP 2 U9 VSS C11 RSVD K51 DDI1 TXP 1 V16 VSS AF12 HDA SYNC J51 DDI1_TXP 0 21 VSS AF14 MF_HDA_SDO M51 DDI1_TXN 3 V25 VSS AD6 MF_HDA_SDI1 L51 DDI1 TXN 2 V32 VSS AD7 MF HDA SDIO 52 DDI1_TXN 1 V38 VSS 1 MF_HDA_RST_N H51 DDI1_TXN 0 V41 VSS AB7 MF_HDA_DOCKRST_N F47 DDI1_PLLOBS_P V42 VSS 9 HDA DOCKEN 49 DDI1 PLLOBS 44 VSS AD9 MF HDA CLK M42 DDI1_AUXP wi VSS G44 RSVD K42 DDI1 AUXN 10 VSS A49 RSVD G53 DDIO TXP 3 14 VSS 51 RSVD F53 TXP 2 16 VSS C53 RSVD H49 DDIO_TXP 1 19 VSS E53 RSVD 250 DDIO_TXP 0 Y21 VSS B49 RSVD G52 DDIO TXN 3 Y22 VSS B50 RSVD F52 DDIO_TXN 2 Y24 55 D52 RSVD H50 DDIO TXN 1 Y29 55 52 RSVD C51 DDIO_TXN 0 Y38 VSS B53 RSVD F38 DDIO_PLLOBS_P Y4 VSS A52 RSVD G38 DDIO_PLLOBS_N 40 VSS P44 MCSI COMP H47 DDIO AUXP Y45 VSS T50 MCSI_3_CLKP H46 DDIO_AUXN 208 Datasheet Volume 1 of 3 Ball Ball Out SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 11 of 11 Pin Pin Name Pin Pin Name P
50. While executing code Enhanced Intel SpeedStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P State When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C State In general lower power C States have longer entry and exit latencies 6 3 1 Enhanced Intel SpeedStep Technology The following are the key features of Enhanced Intel SpeedStep Technology e Applicable to Processor Core Voltage and Graphic Core Voltage Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P States Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency If the target frequency is higher than the current frequency Core is ramped up slowly to an optimized voltage This voltage is signaled by the SVID signals to the voltage regulator Once the voltage is established the PLL locks on to the target frequency If the target frequency is lower than the current frequency the PLL locks to the target frequency then transitions to a lower voltage by signaling the target voltage on the SVID signals e The processor controls voltage ramp rates by requesting appropriate ramp rates from an external SVID controller Because there is low transition latency b
51. because the counting process is asynchronous to read operations However in the case of Counter 2 the count can be stopped by writing Ob to the NSC TC2E register bit Counter Latch Command The Counter Latch command written to Port 43h latches the count of a specific counter at the time the command is received This command is used to ensure that the count read from the counter is accurate particularly when reading a two byte count The count value is then read from each counter s Count register as was programmed by the Control register The count is held in the latch until it is read or the counter is reprogrammed The count is then unlatched This allows reading the contents of the counters on the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one counter Counter Latch commands do not affect the programmed mode of the counter in any way If a counter is latched and then some time later latched again before the count is read the second Counter Latch command is ignored The count read is the count at the time the first Counter Latch command was issued Read Back Command The Read Back command written to Port 43h latches the count value programmed mode and current states of the OUT pin and Null Count flag of the selected counter or counters The value of the counter and its status may then be read by I O access to the counter address The Read Back command may be used t
52. 0 5USI2 override 20k PU 1 Normal Operation 0 DSI Port not detected 1 DSI Port detected Weak int 5095131 Display Dor 20k PD Note DSI is not supported for the processor This strap will not enable DSI on the processor Leave the pin floating if GPIO functionality is not used Boot BIOS Weak interna 0 No SPI Default GPIO_SUS 4 Strap BBS 20k PU 1 SPI Flash Descriptor Weak interna 0 Override SUS 5 Security 20k PU 1 Normal Operation 1 Normal Operation SUS 6 Halt Boot Strap Note This strap MUST be High at RSMRST de assert to ensure proper platform operation and use of GPIO DFX 8 0 PLLs ICLK 0 Supply is 1 25V GPIO SUS 8 usB2 SER 1 supply is 1 35V Supply Select GPIO_SUS 9 ICLK USB2 Weak interna No bypass 20k PD Weak interna 20k PD Bypass with 1 05V No Bypass Default Bypass 0 1 0 1 Datasheet Volume 1 of 3 Physical Interfaces Table 2 26 Hard Strap Description and Functionality Sheet 2 of 2 ntel 1 Pull Up Pull Uu Signal Name Purpose Down Strap Description CCU SUS RO Weak internal 0 No Bypass Default CAMERASB09 0 Bypass 20k PD 1 Bypass RTC OSC Weak internal 0 No Bypass Default GPIO_CAMERASB11 Bypass 20k PD 1 Bypass Notes 1 straps are sampled on the rising edge de assertion of PMU_RSMRST_N 2 For proper operation of GPIO fun
53. 25 1 4 Table 1 2 26 intel Introduction Interface Category SoC Features Platform Controller Unit PCU UART Max Baud Rate 115 200 bps thus recommended for debug only 16550 controller compliant Reduced Signal Count TX and RX only COMI interface FAST SPI For SPI Flash only of up to 16MB size each No other SPI peripherals are supported Stores boot firmware and system configuration data Supports frequencies of 20 MHz 33 MHz and 50 MHz Note Fast SPI signals do not get tri stated during RSMRST assertion Note Flash Sharing is not supported for the processor Platforms PMC Controls many of the power management features present in the SoC iLB Supports legacy PC platform features Sub blocks include LPC GPIO 8259 PIC I O APIC 8254 timers HPET timers and the RTC Related Documents Related Documents Document Title Number Location N series Intel Pentium Processors and Intel Celeron Processors Datasheet Volume 332093 2 of 3 N series Intel Pentium Processors and Intel Celeron Processors Datasheet Volume 332094 3 of 3 N series Intel Pentium Processors and Intel Celeron Processors Specification 33209 Update 5 Datasheet Volume 1 of 3 Physical Interfaces 2 Physical Interfaces 2 1 Platform Power Rails Table 2 1 Platform Power Well Definitio
54. CPU cache per core On die 1MB 16 way L2 cache shared per two cores module One thread per core Note Intel Hyper Threading Technology is not supported Address size Support 36 bit physical address 48 bit linear address size Core State C1 C6C C6 and C7 states Type Type 3 BGA FCBGA15 Processor Core 14 nm Process Package X Y Dimension 25 mm x 27 mm Post SMT Height 1mm Ball Pitch 0 593 mm Pin Ball Count 1170 DDR3L 1 35V DRAM interface I Os Interface Dual Channel Up to two ranks per channel 4 ranks in total Transfer Data rate Up to 1600MT s Device Data Width x8 x16 12 8GB s for 1600 5 single channel Memory Bandwidth 25 658 for 1600MT s dual channel Data bus 64 bit only per channel Standard 1Gb 2Gb 4Gb and 8Gb Memory DRAM Device Read latency 5 6 7 8 9 10 11 12 13 Technologies Write latency 3 4 5 6 7 8 Support Truck Clock Gating Support early SR exit Support slow power down Support command signal tri state not driving a valid command Other Support different physical mappings of bank address to optimize performance Support Dynamic Voltage and Frequency Scaling Aggressive power management to reduce power consumption Proactive page closing policies to close unused pages Generation Gen 8 LP Intel graphics core Units 16 Execution Units 05 3 D DirectX 11 1 OpenGL 4 2 OpenGL ES 3 0 OpenCL 1 2 HW Accelerat Graphics 2 0 HEVC 264 MPEG2 VC 1 WMV9 Support content p
55. Full autoflow automating both nCTS and nRTS and half autoflow automating only nCTS Full Autoflow is enabled by writing a 1 to bits 1 and 5 of the Modem Control Register MCR Auto nCTS Only mode is enabled by writing a 1 to bit 5 and a 0 to bit 1 of the MCR register RTS UART Output When in full autoflow mode nRTS is asserted when the UART FIFO is ready to receive data from the remote transmitter This occurs when the amount of data in the Receive FIFO is below the programmable threshold value When the amount of data in the Receive FIFO reaches the programmable threshold nRTS is de asserted It will be asserted once again when enough bytes are removed from the FIFO to lower the data level below the threshold CTS UART Input When in Full or Half Autoflow mode nCTS is asserted by the remote receiver when the receiver is ready to receive data from the UART The UART checks nCTS before sending the next byte of data and will not transmit the byte until nCTS is low If nCTS goes high while the transfer of a byte is in progress the transmitter will complete this byte 88 Datasheet Volume 1 of 123 tel Serial I O SIO Overview 124 Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview tel 16 16 1 16 1 1 16 1 1 1 Note Platform Controller Unit PCU Overview The Platform Controller Unit PCU is a collection of hardware blocks that are critical for implementing a Windows
56. Integrated Clock Usage Description Differential clock for HDMI devices HDMI DDC MIPI CSI DDI 2 0 _DDC_CLK MCSI1_CLKP MCSI1_CLKN MCSI2_CLKP MCSI2_CLKN MCSI3_CLKP MCSI3_CLKN 100 KHz 200 400 MHz Clock for HDMI DDC devices Clocks for front and rear cameras SVID Platform Clocks SVIDO_CLK PLT_CLK 5 0 20 MHz 19 2 MHz Clock used by voltage regulator Platform clocks I2C 6 0 CLK 1 7 MHz 12 clocks 54 88 Datasheet Volume 1 of 3 m e Thermal Management n tel 5 5 1 5 2 Table 5 1 Thermal Management Overview The thermal management system for the SoC helps in managing the overall thermal profile of the system to prevent overheating and system breakdown The architecture implements various proven methods of maintaining maximum performance while remaining within the thermal specification Throttling mechanisms are used to reduce power consumption when thermal limits of the device are exceeded and the system is notified of critical conditions by means of interrupts or thermal signalling pins SoC thermal management differs from legacy implementations primarily by replacing dedicated thermal management hardware with firmware The thermal management system Eight digital thermal sensors DTS e Supports a hardware trip point and four programmable trip points based on the temperature indicated by thermal sensors e Supports differe
57. SMC System Management Controller or External Controller refers to a separate system management controller that handles reset sequences sleep state transitions and other system management tasks SMI System Management Interrupt is used to indicate any of several system conditions such as thermal sensor events throttling activated access to System Management RAM chassis open or other system state related activity SIO Serial I O SPI Serial Peripheral Interface SSP Synchronous Serial Protocol TDP Thermal Design Power TMDS Transition Minimized Differential Signaling TMDS is a serial signaling interface used in DVI and HDMI to send visual data to a display TMDS is based on low voltage differential signaling with 8 10b encoding for DC balancing UART Universal Asynchronous Receiver Transmitter VCO Voltage Controlled Oscillator Warm Reset Warm reset is when both PMC_PLTRST and PMC_CORE_PWROK are asserted Datasheet Volume 1 of 3 21 1 22 intel 3 Feature Overview Introduction Interface Category SoC Features Up to 4 IA low power Intel processor cores No Cores Quad Out of Order Execution OOE processor cores Based on 14nm processor technology Cores are grouped into Dual Core modules Modules Cashes On die 32KB 8 way 11 instruction cache and 24KB 6 way L1 data
58. Table 19 1 SoC Pin List Locations Sheet 3 of 11 Pin Pin Name Pin Pin Name Pin Name AH13 VSS P40 MIPI_V1P2A_G3 5 02 14 55 40 V1P2A G3 GP CAMERASBO1 41 VSS V18 ICLK GND OFF GP 5 00 42 VSS 19 GND OFF RSVD 44 55 1 DDR VDDQ G 54 RSVD 47 VSS BE53 DDR VDDQ G S4 RSVD AH9 VSS BJ2 DDR VDDQ G S4 FST SPI D3 1 VSS BJ3 DDR VDDQ G S4 FST SPI D2 AJi6 VSS BJ49 DDR VDDQ G S4 FST SPI D1 218 VSS BJ5 DDR VDDQ G S4 FST SPI DO AJ25 55 BJ51 DDR VDDQ G 54 FST SPI CS2 N AJ3 VSS BJ52 DDR VDDQ G S4 FST SPI CS1 N AJ51 VSS 18 DDR VDDQ 54 FST SPI CSO N AJ53 VSS AM36 DDR VDDQ G 54 FST SPI CLK 16 55 18 DDR VDDQ G 54 RSVD AK22 VSS 19 DDR VDDQ 54 RSVD AK25 VSS AN35 DDR VDDQ G S4 DDR3 VCCA PWROK AK27 VSS AN36 DDR VDDQ G S4 DDR3 M1 WE N AK29 VSS AU18 DDR VDDQ 54 DDR3 M1 RCOMP AK32 VSS AU36 DDR VDDQ G S4 DDR3 M1 RAS N AK38 VSS 10 VDDQ 54 DDR3 M1 ODT 1 AK4 VSS 16 DDR_VDDQ_G_S4 DDR3 M1 ODT O0 40 VSS AV38 DDR VDDQ G 54 DDR3 M1 ODQVREF 44 VSS AV44 DDR VDDQ G 54 DDR3 1 OCAVREF 45 VSS 10 DDR VDDQ G S4 RSVD 47 VSS AY44 DDR VDDQ G S4 RSVD 50 VSS BE3 DDR VDDQ G S4 DDR3 M1 AK7 VSS BE51 DDR_VDDQ_
59. UNCORE S4 12 4 SCL A43 VSS AD27 UNCORE VNN S4 I2C3 SDA A47 VSS H44 USB VDDQ G3 I2C3 SCL A7 VSS AN27 DDRSFR_VDDQ_G_S4 2 2 SDA 16 55 Y25 VSFR 2 2 SCL 27 VSS Y27 ICLK VSFR G3 2 SDA AA38 VSS D4 V3P3A G5 2 SCL 5 VSS E3 RTC V3P3A G5 2 0 SDA AB10 VSS B6 V3P3RTC G5 2 0 SCL 12 55 C5 V3P3RTC G5 RSVD AB13 VSS AK30 CORE 1 15 RSVD 14 VSS AK35 CORE 1 15 HV DDI2 HPD AB4 VSS AK36 CORE 1 15 HV 0012 SDA 42 VSS AM29 CORE V1P15 HV 0012 DDC SCL 47 VSS AC30 VSFR R51 HV 50 VSS P38 CORE VSFR W51 DDIO HPD Datasheet Volume 1 of 3 199 m e n tel Ball Map Ball Out and SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 2 of 11 Pin Pin Name Pin Pin Name Pin Pin Name AB6 VSS CORE VSFR G3 Y52 HV 0010 SDA AC16 VSS P41 USBSSIC V1P2A G3 Y51 HV DDIO DDC SCL AC29 VSS V29 USBSSIC_V1P05A_G3 AH45 RSVD AC33 VSS M41 USBHSIC_V1P2A_G3 P26 RSVD AC35 VSS E1 SDIO V3P3A V1P8A G3 40 GPIOO_RCOMP AC38 VSS E2 SDIO V3P3A 1 AG53 5057 AD21 VSS Y18 GPIO 1 51 5056 AD30 55 AD33 GPIO V1P8A G3 AH52 GPIO SUS5 AD32 VSS AF33 GPIO
60. axe aia 227 21 10HDMI DC Specification 22 rite bea a 228 21 11embedded Display Port DC Specification 1 1 enne 228 21 12DDI AUX Channel DC 5 nau 229 Datasheet Volume 1 of 3 13 14 21 13embedded Display Port AUX Channel DC 5 1 111 229 21 14DDC Signal DC Specification DCC DATA DDC CLK sss mme 230 21 15DDC Miscellaneous Signal DC Specification HPD BKLTCTL BKLTEN 230 21 16MIPI HS RX MIPI LP RX Minimum Nominal and Maximum Voltage Parameters 232 21 17SDIO DC SpecificatilOh occi eee tette te thea tenga te DR xl Fa a Dd 232 21 18SD Card DC Specification snanar ei orna aka tu tae 232 21 19eMMC 4 51 DC Electrical nsn nana anni 233 21 20JTAG Signal Group DC Specification JTAG_TMS 2 TDI JTAG_TRST_N 234 21 21JTAG Signal Group DC Specification JTAG 234 21 22JTAG Signal Group DC Specification JTAG_PREQ 234 21 23DDR3L Signal Group DC 5
61. bit rate of 48Mb s Intel HD Audio Serial Data In 1 0 Serial TDM data input from HDA SDI 1 0 I the codec s The serial input is single pumped for a bit rate of 24Mb second HDA DOCKEN ae HD Audio Docking Enable Enable audio docking isolation HDA_DOCKRST Intel HD Audio Docking Reset Audio docking station reset The signals in the table above are all multiplexed and maybe used by other functions 14 2 Features The Intel HD Audio Controller supports the following features e Supports MSI and legacy interrupt delivery e Support for ACPI D3 and DO Device States e Supports up to 6 streams three input three output 16 channels per stream 32 bits sample 192 KHz sample rate 24 MHz HDA CLK supports SDO double pumped at 48Mb s SDI single pumped at 24Mb s e Supports 1 5V and 1 8V mode e Supports optional Immediate Command Response mechanism 14 3 References High Definition Audio Specification Revision 1 0a e http www intel com content dam www public us en documents product specifications high definition audio specification pdf 88 114 Datasheet Volume 1 of Serial 510 Overview te 15 Serial SIO Overview The Serial I O SIO is a collection of hardware blocks that implement simple but key serial I O interfaces for platform usage These hardware blocks include SIO Serial Peripheral SPI SIO I C Interface SIO High Speed UART
62. embedded Display Port AUX Channel DC Specification on page 229 e Section 21 6 1 6 DDC Signal DC Specification on page 230 21 6 1 1 DisplayPort DC Specification Table 21 9 DisplayPort DC specification Symbol Parameter Min Units Notes VzTX DIFFp p Differential Peak to peak Levelo es Output Voltage Level 0 0 34 0 4 0 46 VzTX DIFFp p Differential Peak to peak Leveli Output Voltage Level 1 0 51 0 6 0 68 VzX DIFFp p Differential Peak to peak Level2 xs Output Voltage Level 2 0 69 0 8 0 92 VTx prFFp p Differential Peak to peak Level3 ee Output Voltage Level 3 0 85 Bs 1 38 Pre emphasis 0 0 0 0 0 0 V 3 5 dB Pre emphasis 2 8 3 5 4 2 dB TX PREEMP RATIO 6 0 dB Pre emphasis 4 8 6 0 7 2 dB 9 5 dB Pre emphasis 7 5 9 5 11 4 dB Tx DC Common Mode 0 2 0 V Voltage Differential Return Loss at 12 0 675GHz at Tx Package pins RLyx DIFF Differential Return Loss at 9 _ dB 1 1 35 GHz at Tx Package pins TX Output Capacitance 1 5 pF 2 Notes 1 Straight loss line between 0 675 GHz and 1 35 GHz 2 Represents only the effective lump capacitance seen at the SoC interface that shunts the TX termination Datasheet Volume 1 of 3 227 intel 21 6 1 2 HDMI DC Specification Table 21 10 HDMI DC Specification Electrical Specifications
63. once all LPC devices have been initialized The Clock Run protocol is enabled by setting the LPCC CLKRUN_EN register bit SERIRQ Disable Serialized IRQ support may be disabled by setting the OIC SIRQEN bit to Ob References Low Pin Count Interface Specification Revision 1 1 LPC http www intel com design chipsets industry Ipc htm e Serialized IRQ Support for PCI Systems Revision 6 0 http www smsc com media Downloads_Public papers serirq60 doc Implementing Industry Standard Architecture ISA with Intel Express Chipsets 318244 http www intel com assets pdf whitepaper 318244 pdf PCU iLB Real Time Clock RTC The SoC contains a real time clock with 242 bytes of battery backed RAM The real time clock performs two key functions keeping track of the time of day and storing system data even when the system is powered down The RTC operates on a 32 768 KHz crystal and a 3 3V battery The RTC supports two lockable memory ranges By setting bits in the configuration space two 8 byte ranges can be locked to read and write accesses This prevents unauthorized reading of passwords or other system security information The RTC supports a date alarm that allows for scheduling a wake up event up to 30 days in advance Signal Descriptions See Chapter 2 Physical Interfaces for additional details Table 16 23 RTC Signals Sheet 1 of 2 160 Direction Type Signal Name Description I Crys
64. 0 0 0 1 1 3 1 22000 1 1 0 0 0 1 0 0 C 4 1 22500 1 1 0 0 0 1 0 1 C 5 1 23000 1 1 0 0 0 1 0 6 1 23500 1 1 0 0 0 1 1 1 C 7 1 24000 1 1 0 0 1 1 0 0 C 8 1 24500 1 1 0 0 1 0 0 1 9 1 25000 1 1 0 0 1 0 1 0 1 25500 1 1 0 0 1 0 1 1 1 26000 1 1 0 0 1 0 0 0 1 26500 1 1 0 0 1 1 0 1 D 1 27000 1 1 0 0 1 1 1 0 C E 1 27500 1 1 0 0 1 1 1 1 C F 1 28000 1 1 0 1 0 1 0 0 D 0 1 28500 1 1 0 1 0 1 0 1 D 1 1 29000 1 1 0 1 0 0 1 0 D 2 1 29500 1 1 0 1 0 0 1 1 D 3 1 30000 1 1 0 1 0 1 0 0 D 4 1 30500 1 1 0 1 0 1 0 1 D 5 1 31000 1 1 0 1 0 1 1 0 D 6 1 31500 1 1 0 1 0 1 1 1 D 7 1 32000 1 1 0 1 1 0 0 0 D 8 1 32500 1 1 0 1 1 0 0 1 D 9 1 33000 1 1 0 1 1 0 1 0 D A 1 33500 1 1 0 1 1 0 1 1 D B 1 34000 1 1 0 1 1 1 0 0 D 1 34500 1 1 0 1 1 1 0 1 D D 1 35000 1 1 0 1 1 1 1 0 D E 1 35500 1 1 0 1 1 1 1 1 D F 1 36000 1 1 1 0 0 0 0 0 E 0 1 36500 1 1 1 0 0 0 0 1 E 1 1 37000 1 1 1 0 0 0 1 0 E 2 1 37500 1 1 1 0 0 0 1 1 E 3 1 38000 1 1 1 0 0 1 0 0 E 4 1 38500 1 1 1 0 0 1 0 1 E 5 1 39000 1 1 1 0 0 1 1 0 E 6 1 39500 1 1 1 0 0 1 1 1 E 7 1 40000 1 1 1 0 1 0 0 0 E 8 1 40500 224 Datasheet Volume 1 of 3 Electrical Specifications Table 21 6 7 0 Voltage Identification Reference Sheet 7 of 7 intel 21 5 Crystal Specifications VID7 VID6 VID5 VIDA VID2 vID1 VIDO e 1 1 1 0 1 0 0 1
65. 0 82000 0 1 1 1 0 1 0 0 7 4 0 82500 0 1 1 1 0 1 0 1 7 5 0 83000 0 1 1 0 1 1 0 7 6 0 83500 0 1 1 1 0 1 1 1 7 7 0 84000 0 1 1 1 1 0 0 0 7 8 0 84500 0 1 1 1 1 0 0 1 7 9 0 85000 0 1 1 1 1 0 1 0 7 A 0 85500 0 1 1 1 1 0 1 1 7 B 0 86000 0 1 1 1 1 1 0 0 7 C 0 86500 0 1 1 1 1 1 0 1 7 D 0 87000 0 1 1 1 1 1 1 0 7 E 0 87500 0 1 1 1 1 1 1 1 7 F 0 88000 1 0 0 1 0 0 0 0 8 0 0 88500 1 0 0 1 0 0 0 1 8 1 0 89000 1 0 0 1 0 0 1 0 8 2 0 89500 1 0 0 0 0 0 1 1 8 3 0 90000 1 0 0 0 0 1 0 0 8 4 0 90500 1 0 0 0 0 1 0 1 8 5 0 91000 1 0 0 0 0 1 1 0 8 6 0 91500 1 0 0 0 0 1 1 1 8 7 0 92000 1 0 0 0 1 0 0 0 8 8 0 92500 1 0 0 0 1 0 0 1 8 9 0 93000 1 0 0 0 1 0 1 0 8 A 0 93500 1 0 0 0 1 0 1 1 8 B 0 94000 1 0 0 0 1 1 0 0 8 C 0 94500 1 0 0 0 1 1 0 1 8 D 0 95000 1 0 0 0 1 1 1 0 8 E 0 95500 1 0 0 0 1 1 1 1 8 F 0 96000 1 0 0 0 0 0 0 0 9 0 0 96500 1 0 0 0 0 0 0 1 9 1 0 97000 1 0 0 0 0 0 1 0 9 2 0 97500 1 0 0 1 0 0 1 1 9 3 0 98000 1 0 0 1 0 1 0 0 9 4 0 98500 1 0 0 1 0 1 0 1 9 5 0 99000 1 0 0 1 0 1 1 0 9 6 0 99500 1 0 0 1 0 1 1 1 9 7 1 00000 1 0 0 1 1 0 0 0 9 8 1 00500 222 Datasheet Volume 1 of 3 Electrical Specifications Table 21 6 7 0 Voltage Identification Reference Sheet 5 of 7 intel VID7 VID6 VID5 VIDA VID2 VIDO 4 1 0 0 1 1 0 0 1 9 1 01000 1 0 0
66. 1 0 0 2 4 0 42500 0 0 1 0 0 1 0 1 2 5 0 43000 0 0 1 0 0 1 1 0 2 6 0 43500 0 0 1 0 0 1 1 1 2 7 0 44000 0 0 1 0 1 0 0 0 2 8 0 44500 0 0 1 0 1 0 0 1 2 9 0 45000 0 0 1 0 1 0 1 0 2 A 0 45500 0 0 1 0 1 0 1 1 2 B 0 46000 0 0 1 0 1 1 0 0 2 C 0 46500 0 0 1 0 1 1 0 1 2 D 0 47000 0 0 1 0 1 1 1 0 2 E 0 47500 0 0 1 0 1 1 1 1 2 F 0 48000 0 0 1 1 0 0 0 0 3 0 0 48500 0 0 1 1 0 0 0 1 3 1 0 49000 0 0 1 1 0 0 1 0 3 2 0 49500 0 0 1 1 0 0 1 1 3 3 0 50000 0 0 1 1 0 1 0 0 3 4 0 50500 0 0 1 1 0 1 0 1 3 5 0 51000 0 0 1 1 0 1 1 0 3 6 0 51500 0 0 1 1 0 1 1 1 3 7 0 52000 0 0 1 1 1 0 0 0 3 8 0 52500 0 0 1 1 1 0 0 1 3 9 0 53000 0 0 1 1 1 0 1 0 3 A 0 53500 0 0 1 1 1 0 1 1 3 B 0 54000 0 0 1 1 1 1 0 0 3 0 54500 0 0 1 1 1 1 0 1 3 D 0 55000 0 0 1 1 1 1 1 0 3 E 0 55500 0 0 1 1 1 1 1 1 3 F 0 56000 0 1 0 0 0 0 0 0 4 0 0 56500 0 1 0 0 0 0 0 1 4 1 0 57000 0 1 0 0 0 0 1 0 4 2 0 57500 0 1 0 0 0 0 1 1 4 3 0 58000 0 1 0 0 0 1 0 0 4 4 0 58500 0 1 0 0 0 1 0 1 4 5 0 59000 0 1 0 0 0 1 1 0 4 6 0 59500 0 1 0 0 0 1 1 1 4 7 0 60000 0 1 0 0 1 0 0 0 4 8 0 60500 220 Datasheet Volume 1 of 3 Electrical Specifications Table 21 6 7 0 Voltage Identification Reference Sheet 3 of 7 intel Datasheet Volume 1 of 3 VID7 VID6 VID5 VIDA VID2 VIDO 41 0 1 0 0 1 0 0 1 4 0 6
67. 1 1 0 1 0 9 1 01500 1 0 0 1 1 0 1 1 9 B 1 02000 1 0 0 1 1 1 0 0 9 1 02500 1 0 0 1 1 1 0 1 9 D 1 03000 0 0 1 1 1 1 0 9 E 1 03500 1 0 0 1 1 1 1 1 9 F 1 04000 1 0 1 1 0 0 0 0 A 0 1 04500 1 0 1 1 0 0 0 1 A 1 1 05000 1 0 1 1 0 0 1 0 A 2 1 05500 1 0 1 0 0 0 1 1 A 3 1 06000 0 1 0 0 1 0 0 A 4 1 06500 1 0 1 0 0 1 0 1 A 5 1 07000 1 0 1 0 0 1 1 0 A 6 1 07500 1 0 1 0 0 1 1 1 A 7 1 08000 1 0 1 0 1 0 0 0 A 8 1 08500 1 0 1 0 1 0 0 1 A 9 1 09000 0 1 0 1 0 1 0 A A 1 09500 1 0 1 0 1 0 1 1 A B 1 10000 1 0 1 0 1 1 0 0 A 1 10500 1 0 1 0 1 1 0 1 A D 1 11000 1 0 1 0 1 1 1 0 A E 1 11500 1 0 1 0 1 1 1 1 A F 1 12000 0 0 0 0 0 0 B 0 1 12500 1 0 1 0 0 0 0 1 B 1 1 13000 1 0 1 0 0 0 1 0 B 2 1 13500 1 0 1 1 0 0 1 1 B 3 1 14000 1 0 1 1 0 1 0 0 4 1 14500 1 0 1 1 0 1 0 1 5 1 15000 0 1 0 1 1 0 6 1 15500 1 0 1 1 0 1 1 1 7 1 16000 1 0 1 1 1 0 0 0 8 1 16500 1 0 1 1 1 0 0 1 9 1 17000 1 0 1 1 1 0 1 0 1 17500 1 0 1 1 1 0 1 1 B 1 18000 0 1 1 1 1 0 0 B C 1 18500 1 0 1 1 1 1 0 1 B D 1 19000 1 0 1 1 1 1 1 0 B E 1 19500 1 0 1 1 1 1 1 1 B F 1 20000 1 1 0 0 0 0 0 0 0 1 20500 Datasheet Volume 1 of 3 223 m e n Electrical Specifications Table 21 6 IMVP7 0 Voltage Identification Reference Sheet 6 of 7 VID7 VID6 VID5 VID2 VID1 B BE V 1 1 0 0 0 0 0 1 C 1 1 21000 1 1 0 0 0 0 1 0 C 2 1 21500 1 1 0
68. 1 8 Voltage Identification VID Table 21 6 specifies the voltage level corresponding to the eight bit VID value transmitted over serial VID SVID interface per IMVP7 specification A 1 in this table refers to a high voltage level and 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself The SVID signals are CMOS push pull drivers Refer to Table 21 35 for the DC specifications for these signals The VID codes will change due to performance temperature and or current load changes in order to minimize the power of the part A voltage range is provided in Table 21 4 The specifications are set so that one voltage regulator can operate with all supported frequencies Datasheet Volume 1 of 3 Electrical Specifications intel Individual SoC VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in Table 21 4 The SoC provides the ability to operate while transitioning to an adjacent VID and its associated voltage This will represent a DC shift in the loadline Note The following table lists all voltages possible per IMVP7 specification Not all voltages are valid on actual SKUs Table 21 6 7 0 Voltage Identification Reference Sheet 1 of 7
69. 126 16 2 Management Controller 126 16 2 1 Signal Descriptions cnin acre cnn mnnera n ER d e nn OC A EON ced 126 16 2 2 1 15 148 127 16 2 2 1 Sx G3 Sx Handling Power 127 16 2 2 2 Event Input Signals and Their Usage 128 16 2 2 3 System Power Planes damen a 129 16 2 2 4 SMIZ SCI Generation 0 0 0 0 0 0 0 402 131 16 2 2 5 Platform Clock SuppOoFt 133 16 2 2 6 INIT Initialization Generation 2 2221 133 16 2 3 REFERENCES kets E M 134 16 3 PCU Serial Peripheral Interface 134 16 3 1 Signal Descriptions oid eere 134 16 3 2 Rig T 135 16 4 PCU Universal Asynchronous Receiver Transmitter UART 137 16 4 1 Signal Descriptions iore rci eer Ea eee ai 138 16 4 2 Feature S Ra n Ced T d ra rd iR VA Qe Liu aoa 138 16 4 2 1 FIFO a T 139 16 4 3 USE
70. 16 15 1 6 1 16 15 1 6 2 16 15 2 Note Automatic End of Interrupt Mode In this mode the PIC automatically performs a Non Specific EOI operation at the trailing edge of the last interrupt acknowledge pulse From a system standpoint this mode should be used only when a nested multi level interrupt structure is not required within a single PIC The AEOI mode can only be used in the master controller and not the slave controller Both the master and slave PICs have an AEOI bit MICW4 AEOI SICW4 AEOI respectively Only the MICW4 AEOI bit should be set by software The SICW4 AEOI bit should not be set by software Masking Interrupts Masking on an Individual Interrupt Request Each interrupt request can be masked individually by the Interrupt Mask Register IMR This register is programmed through OCW1 Each bit in the IMR masks one interrupt channel Masking IRQ2 on the master controller masks all requests for service from the slave controller Special Mask Mode Some applications may require an interrupt service routine to dynamically alter the system priority structure during its execution under software control For example the routine may wish to inhibit lower priority requests for a portion of its execution but enable some of them for another portion The special mask mode enables all interrupts not masked by a bit set in the Mask register Normally when an interrupt service routine acknowledges an interrupt without i
71. 18 3 References PCI Express Base Specification Rev 2 0 88 192 Datasheet Volume 1 of 3 Ball Ball Out and SoC Pin Locations n te 19 Ball Map Ball Out and SoC Pin Locations Figure 19 1 Ball Top Left View Columns 53 29 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 0 29 2083 DDR3 MO DDR3 MO DDR3 MO majo par7 DABS DDR3 MO DOFO _ _ DORMO _ _ _ bi v 1 24 1P3 eso WEB _ pasis _ Pa ss 0087 _ DDR3 DDR3 DDR3 DDR3 DDR3 _ 2 pasas 2984 _0 5 095871 BG DORMO _ _ _ _ DORMO _ _ 4 Ma 12 8 j _ _ DORMO _ _ _ m _ mam DDR3 MO DDR3 MO MO BD mug T T ma T DDR3 MO DDFG MO _ MO _ ka pops m DDR3 MO DDR3 MO DOR3 MO _ _ _ _ go DOR3 MO DRAMRS lt FASB oofa DOR3_MO DOR3_MO 7 0 exu DDR3 MO DDR3 MO Aw OBA _ MO 0083 295 003 _ 0
72. 2 Core State 63 6 3 4 3 Core State tanec 63 6 3 4 4 Core C7 eere veru 63 6 3 4 5 C State nane xk Y REA Sra EROR envied 64 6 3 5 Package C Stat65 REA 64 6 3 5 1 Package State cese eee ec erre nk n te 65 6 3 5 2 Package C1 CIE ici eene tete Teka ten dba seda ERR 65 6 3 5 3 Package CO State rcino ciii rne ir ka tussis neces 65 6 3 5 4 Package C7 State csse eee ene cates 66 6 3 6 Graphics and Video Decoder C State 66 6 3 7 Intel Display Power Saving Technology Intel 5 66 6 3 8 Intel Automatic Display Brightness eene nnn 66 6 3 9 Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology Rx REEF EAR CREER KE A LAE NIE RA 67 6 4 Memory Power 4 67 6 4 1 Disabling Unused System Memory 312222222222 67 6 4 2 DRAM Power Management and Initialization 67 6 4 2 1 Initialization Role of nnn ns 67
73. 2 6 MIPI CSI Camera Serial Interface and ISP Interface Signals Table 2 10 MIPI CSI Interface Signals Default Buffer State Signal Name Dir Platform Type Pwrgood Assert Resetout Power State De assert State MCSI 1 CLKN I V1P24A MIPI DPHY Input Input MCSI 1 CLKP I V1P24A MIPI DPHY Input Input MCSI 1 DN 0 3 I V1P24A MIPI DPHY Input Input MCSI 1 DP 0 3 I V1P24A MIPI DPHY Input Input MCSI 2 CLKN I V1P24A MIPI DPHY Input Input MCSI 2 CLKP I V1P24A MIPI DPHY Input Input MCSI 2 DN 0 1 I V1P24A MIPI DPHY Input Input MCSI 2 DP 0 1 I V1P24A MIPI DPHY Input Input MCSI 3 CLKN I V1P24A MIPI DPHY Input Input MCSI 3 CLKP I V1P24A MIPI DPHY Input Input MCSI RCOMP I O V1P24A MIPI DPHY 2 2 CAMERASB 00 11 GPIOMV HS Input 20k PD Input 20k PD 2 2 7 Storage Controller Interface Signals Table 2 11 Storage Controller e MMC SDIO SD Interface Signals Sheet 1 of 2 Default Buffer State Signal Name Dir Platform Pwrgood Assert Resetout 9 Power State De assert State SDMMC1_D 7 0 V1P8A GPIOMV HS Z 20K PU Z 20K PU SDMMC1_CMD V1P8A GPIOMV HS Z 20K PU Z 20K PU SDMMC1_CLK 1 0 V1P8A GPIOMV HS 0 20K PD 0 20K PD SDMMC1_RCLK I O V1P8A GPIOMV HS Z 20K PD 2 Datasheet Volume 1 of 3 33 intel Physical Interfaces Table 2 11 Storage Controller e MMC SDIO SD Interface Si
74. 20 in the bit sequence are not sent as a result the slave will not acknowledge bit 28 in the sequence Block Write Block Read Process Call The block write block read process call is a two part message The call begins with a slave address and a write condition After the command code the host issues a write byte count M that describes how many more bytes will be written in the first part of the message If a master has 6 bytes to send the byte count field will have the value 6 0000 0110b followed by the 6 bytes of data The write byte count M cannot be 0 The second part of the message is a block of read data beginning with a repeated start condition followed by the slave address and a Read bit The next byte is the read byte count N which may differ from the write byte count M The read byte count N cannot be 0 The combined data payload must not exceed 32 bytes The byte length restrictions of this process call are summarized as follows e gt 1 gt 1 byte M N 32 bytes The read byte count does not include the byte is computed on total message beginning with the first slave address and using the normal PEC computational rules It is highly recommended that a PEC byte be used with the Block Write Block Read Process Call Software must do a read to the Host Command SMB Mem HCMD register to reset the 32 byte buffer pointer prior to reading the Host Block Data SMB
75. 2010 SD Specification Part A2 SD Host Controller Standard Specification version 3 00 February 18 2010 SD Specification Part 03 security Specification version 1 01 April 15 2001 embedded Multi Media Card e MMC Product Standard v4 5 JESD84 A5 88 Datasheet Volume 1 of 3 m USB Controller Interfaces n tel 11 11 1 Note Note Note USB Controller Interfaces SoC Supports e Four 4 Super Speed SS ports e Five 5 High Speed HS ports Two 2 High Speed Inter Chip HSIC ports There is one dedicated HS port USB 2 0 while the other 4 HS ports are multiplexed with SS ports and can be used either by USB 2 0 or USB 3 0 It is recommended to disable USB OTG through BIOS The Disable OTG Soft Strap is not functional Global Valid Bit is used to enable disable debug features It is recommended that users set the Global Valid Bit 21 on production ready systems for lower SoC power Datasheet Volume 1 of 3 93 m e n te USB Controller Interfaces 11 2 Signal Descriptions Table 11 1 USB Signals Signal Name um cu Description Transmitter serial data outputs High Speed Serialized data USB3 TXP N O0 3 USB 3 0 PHY outputs Receiver serial data inputs High speed serialized data inputs USB3 RXP N O0 3 USB 3 0 PHY I Resistor Compensation An external resistor must be connected USB3 RCOMP P N USB 3 0 PHY I O USB2 Data High speed serialized data I O USB_D
76. 20k PU Z 20k PU Z 20k PU Z 20k PU 1 0 Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Input 20k PU Input 20k PU Input 20k PU PRG 0 1 1 Input 20k PD 0 Input lorZ 0 2 Input 20k PU Input 20k PU intel Optional Modes Direction Mode3 UARTO TXD O 47 48 Physical Interfaces Datasheet Volume 1 of 3 Processor Core 3 3 1 3 2 3 2 1 intel Processor Core SoC Transaction Router The SoC Transaction Router is a central hub that routes transactions between the CPU cores graphics controller I O and the memory controller In general it handles CPU Core Interface Requests for CPU Core initiated memory and I O read and write operations and processor initiated message signaled interrupt transactions Device MMIO and PCI configuration routing Buffering and memory arbitration PCI Configuration and MMIO accesses to host device 0 0 0 For more information on SoC Transaction Router Registers refer to the SoC Datasheet Volume 2 and Volume 3 See Related Documents section Intel Virtualization Technology Intel VT Intel virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a single system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture micropro
77. 28 Reserved 27 20 Extended Family value 19 16 Extended Model value 15 13 Reserved 12 Processor Type Bit 11 8 Family value 7 4 Model value 3 0 Stepping ID Value References For further details of Intel 64 and IA 32 architectures refer to Intel 64 and IA 32 Architectures Software Developer s Manual Combined Volumes 1 2A 2B 2C 3A 3B and 3C e http www intel com content www us en processors architectures software developer manuals html Datasheet Volume 1 of 3 51 m n te Processor Core For more details on Intel Performance Primitives refer to Intel Performance Primitives web page http software intel com en us intel ipp For more details on using the RDRAND instruction refer to Intel Advanced Vector Extensions Intel AVX Programming Reference 88 52 Datasheet Volume 1 of 3 Integrated Clock 4 Table 4 1 Table 4 2 Integrated Clock Clocks are integrated consisting of multiple variable frequency clock domains across different voltage domains This architecture achieves a low power clocking solution that supports the various clocking requirements of the many SoC interfaces Platform clocking is provided internally by the iClock block and does not require external devices for clocking the required platform clocks are provided by only two inputs a 19 2 MHz primary reference for the integrated clock block and a 32 768 KHz reference for the Real Time Clock
78. 3 Referee Sonn er 151 PCU Intel Legacy Block 152 16 7 1 Signal Descriptions sad otra dex este ct Rae aua a oid dada DE ax TERR cian 152 16 7 2 eiu dw nod Vae EY 152 16 7 2 1 Key ioci eoe unie Ebo da end 152 16 7 2 2 Non Maskable Interrupt eem 153 PCU iLB Low Pin Count LPC Bridge 4 154 16 8 1 Signal e RR RA XR REY AE 154 16 8 2 az 154 16 8 2 1 Memory Cycle 155 16 8 2 2 Trusted Platform Module TPM 1 2 2 2 4 155 16 8 2 3 FWA Cycle gt tree na adt tta ma Son DR Ir rk ns 155 16 8 2 4 Subtractive Decode eh c enin ERR 156 16 8 2 5 POST Code Redirection eee inert e enn cane 156 16 8 2 6 Power 156 16 8 2 7 Serialized IRQ 5 156 16 8 3 159 16 8 3 1 LPC Clock Delay 1
79. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SoC Pin No V51 v52 w53 R51 P52 51 R53 U51 T51 T52 M7 P6 M6 M4 P9 P7 T6 T7 T10 T12 T13 v4 V6 V7 v2 01 40 41 44 45 47 AK48 CFIO Name PANELO_BKLTCTL PANELO_BKLTEN PANELO_VDDEN HV_DDI1_HPD PANEL1_BKLTCTL PANEL1_BKLTEN PANEL1_VDDEN HV_DDI2_HPD HV_DDI2_DDC_SCL HV_DDI2_DDC_SDA SDMMC1_CLK SDMMCi CMD SDMMC1 DO SDMMC1 Di SDMMC1 D2 SDMMCi 03 CD MMCi 04 SD WE SDMMC1 05 SDMMC1 06 SDMMC1 07 SDMMC1_RCLK FST_SPI_CLK FST_SPI_CSO_N FST SPI 51 FST SPI 52 FST SPI DO FST SPI 01 FST SPI D2 FST SPI D3 GPIO GPIO DFX1 GPIO DFX2 GPIO DFX3 GPIO DFX4 DFX5 Datasheet Volume 1 of 3 Default Mode Default Function PANELO BKLTCTL BKLTEN PANELO_VDDEN HV_DDI1_HPD PANEL1_BKLTCTL PANEL1_BKLTEN PANEL1_VDDEN HV_DDI2_HPD HV_DDI2_DDC_SCL HV_DDI2_DDC_SDA SDMMC1_CLK SDMMC1 CMD SDMMCi DO SDMMCi Di SDMMCi D2 SDMMCi1 D3 CD 1 04 SD WE SDMMCi D5 SDMMCi 06 SDMMCi 07 SDMMC1_RCLK FST_SPI_CLK FST_SPI_CSO_N FST SPI CS1 N FST SPI 52 FST SPI DO FST SPI D1 FST SPI D2 FST SPI D3 RSVD Inputs RSVD Inputs RSVD Inputs RSVD Inputs RSVD Inputs RSVD Inputs GPIO SoC Power Rail V1P8A V1P8A V1P8A V1P8
80. 4Gb x8 8KB 1KB 8 chips 8GB 8 8Gb x8 16KB 2KB 8 chips 512MB 4 1Gb x16 8KB 2KB 4 chips 1GB 4 2Gb x16 8KB 2KB 4 chips 2GB 4 4Gb x16 8KB 2KB 4 chips 4GB 4 8Gb x16 8KB 2KB 4 chips 88 70 Datasheet Volume 1 of 3 Graphics Video and Display n tel 8 8 1 Figure 8 1 8 1 1 8 1 1 1 Graphics Video and Display SoC Graphics Display SoC Graphics Display Diagram Display Controller Display N Planes S lt gt st n e Port D DDI2 The Processor Graphics controller display pipe can be divided into four components that are all incorporated into the Display Controller Display Planes Display Pipes Display Physical Interfaces Four planes available per pipe 1x Primary 2x Video Sprite and 1x Cursor A display plane is a single displayed surface in memory and contains one image desktop cursor overlay It is the portion of the display hardware logic that defines the format and location of a rectangular region of memory that can be displayed on a display output device and delivers that data to a display pipe This is clocked by the Core Display Clock Primary Display Planes A B and C Planes A B and C are the main display planes and are associated with Pipes A B and C respectively Each plane supports per pixel alpha blending Video Sprite Planes A B C D E and F Video Sprite Planes A B
81. AD38 CORE_VSFR_G3 24 DDR3_M1_DQS 6 4 VSS AF35 VSFR AT22 DDR3 M1 DQS 5 45 VSS AM25 DDR VDDQ G S4 BH14 DDR3 M1 DQS 4 46 VSS VCCCFIOAZA 1 80 2 DDR3 1 DQS 3 48 VSS 4 VCCCFIOAZA 1 80 12 DDR3 M1 DQS 2 49 VSS U27 USB3 V1P05A AV7 DDR3 M1 DQS 1 5 VSS V27 USB3_V1P05A_G3 AM2 DDR3_M1_DQS 0 AN51 VSS U22 SATA V1P05A AT7 DDR3 M1 DQ 9 AN53 VSS U24 SATA 1 G3 AP6 DDR3 1 DQ 8 6 VSS V22 PCIE V1P05A G3 AP3 DDR3 M1 DQ 7 AN8 VSS 24 1 BG21 DDR3 1 001631 9 VSS AM21 DDR V1P05A BH26 DDR3 1 DQ 62 VSS 22 DDR V1P05A BJ25 DDR3 M1 DQ 61 AP45 VSS AM32 DDR V1P05A BG26 DDR3 1 DQ 60 AP50 VSS AM33 DDR V1P05A AR1 DDR3 M1 DQ 6 AP9 VSS 22 DDR V1P05A BG22 DDR3 1 DQ 59 18 VSS AN32 DDR V1P05A BH20 DDR3 M1 DQ 58 AT19 VSS V36 DDI_VDDQ_G3 BG25 DDR3_M1_DQ 57 AT27 VSS Y36 DDI_VDDQ_G3 BJ21 DDR3_M1_DQ 56 VSS U16 FUSE 1 G3 BD26 DDR3 M1 DQ 55 AT35 VSS U19 FUSE V1P05A G3 BF24 DDR3 1 DQ 54 AT36 VSS AF27 CORE VSS1 SENSE BA20 DDR3 M1 DQ 53 202 Datasheet Volume 1 of 3 Ball Ball Out SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 5 of 11
82. C D E and F are planes optimized for video decode Pipe A Primary planeA VSpriteA VSpriteB CusrorA Pipe Primary planeB VSpriteC VSpriteD CursorB e Pipe C Primary planeC VSpriteE VSpriteF CursorC Datasheet Volume 1 of 3 71 intel 8 1 1 2 8 1 3 8 2 Table 8 1 Table 8 2 72 Cursors and Graphics Video Display Cursors A B and C are small fixed sized planes dedicated for mouse cursor acceleration and are associated with Planes A B and C respectively Display Pipes The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed The display pipes A B and C operate independently of each other at the rate of one pixel per clock They can be attached to any of the display interfaces Display Physical Interfaces The display physical interfaces consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device These interfaces are digital DisplayPort embedded DisplayPort DVI and HDMI interfaces Digital Display Interfaces Display Technologies Support 1 4 wired 2 2 wireless Technology Standard eDP 1 4 VESA embedded DisplayPort Standard Version 1 4 DP 1 1a VESA DisplayPort Standard Version 1 1a HDMI 1 4b High Definition Multi media Interface Specificat
83. Core VID Target Range 0 5 1 3 V CORE VCCO for SoC Core 0 See VCC VID V 2 CORE 1 for SoC Core 1 See VCC VID V 5 UNCORE VNN VID Uncore VID Target Range 0 5 1 05 V UNCORE VNN G3 for SoC Uncore See VNN VID V 2 5 VGG for SoC Display 0 5 1 2 V CORE VCC Default target Vcc Vyw voltage for UNCORE VNN initial power up 1 0 V 4 VCCO0 1 Tolerance Tolerance of 1 voltage at VID 50 50 target Tolerance of VNN voltage at VID _ Tolerance target 50 50 VGG Tolerance Perange of VGG voltage at VID 60 _ 60 6 arget Notes 1 Each SoC is programmed with voltage identification value VID which is set at manufacturing and cannot be altered Individual VID values are calibrated during manufacturing such that two SoCs at the same frequency may have different settings within the VID range This differs from the VID employed by the SoC during a power management event 2 N A 3 and are merged into single SVID 4 Depending on configuration chosen VNN SVID can be either variable VID or fixed VID to a voltage such as 1 05V 5 The processor SVID is based on VR12 1 requirement VID DAC is similar to IMPV7 VID DAC 6 Maximum threshold allowed can be 90mV as long as it returns to 60mV within 20 us Table 21 5 VSDIO Voltage Setting 21 4 2 218 SDMMC3 PWR EN B SDMMC3 1P8 EN VSDIO V 1 0 0 1 1 0 0 0 3 3 0 1
84. I2C GPIOHV HS GPIO Buffer type High Voltage 1 8V 3 3V High Speed FMAX 208 MHz GPIOHV HS RCOMP GPIO Buffer type High Voltage 1 8V 3 3V High Speed FMAX 208 MHz RCOMP Note GPIO mode where register controlled will not hit MAX speeds they only matter when functionally used Table 2 3 Default Memory Controller Interface Signals Sheet 1 of 2 Buffer State Description Z The SoC places this output in a high impedance state For inputs external drivers are not expected Do Not Care The state of the input driven or tristated does not affect the processor For outputs it is assumed that the output buffer is in a high impedance state Vou The SoC drives this signal high with a termination of 50 9 VoL The SoC drives this signal low with a termination of 50 Q Unknown The processor drives or expects an indeterminate value Vin The SoC expects requires the signal to be driven high Vit The SoC expects requires the signal to be driven low P 1 1V USB low speed single ended 1 This signal is pulled high by a pull up resistor internal or external internal value Pull up Mind tia specified in Term column Pull down This signal is pulled low by a pull down resistor internal or external internal value specified in Term column Running The clock is toggling or the signal is transitioning 28 Datasheet Volume 1 of 3 Physical Interfaces Table 2 3 2 2
85. In STR the CKE signals remain LOW so the SDRAM devices perform self refresh The target behavior is to enter self refresh for the package low power states as long as there are no memory requests to service Dynamic Power Down Operation Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or precharge power down CKE de assertion with all pages closed Precharge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM I O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks can be controlled on a per SO DIMM basis Exceptions are made for per SO DIMM control signals such as CS CKE and ODT for unpopulated SO DIMM slots The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should be disabled
86. Management Bus SMBus Specification Version 2 0 for the format of the protocol Send Byte Receive Byte For the Send Byte command the Transmit Slave Address SMB TSA and Host Command SMB HCMD registers are sent the Receive Byte command the Transmit Slave Address SMB Mem TSA register is sent The data received is stored in the Data 0 SMB Mem register Software must force the SMB Config HCFG I2C EN bit to Ob when running this command The Receive Byte is similar to a Send Byte the only difference is the direction of data transfer See sections 5 5 2 and 5 5 3 of the System Management Bus SMBus Specification Version 2 0 for the format of the protocol Write Byte Word The first byte of a Write Byte Word access is the command code The next 1 or 2 bytes are the data to be written When programmed for a Write Byte Word command the Transmit Slave Address SMB TSA Host Command SMB Mem HCMD Data 0 SMB Mem registers are sent In addition the Data 1 Mem HD1 register is sent on a Write Word command Software must force the SMB Config HCFG I2C EN bit to 0 when running this command See section 5 5 4 of the System Management Bus SMBus Specification Version 2 0 for the format of the protocol Read Byte Word Reading data is slightly more complicated than writing data First the SoC must write a command to the slave device Then it must follow that command with a repeate
87. Note SIO Serial Peripheral Interface SPI is supported for a platform supporting non Windows operating systems only 15 1 Register Map For more information on SIO registers refer to the Processor Datasheet Volume 2 and Volume 3 See Related Documents section 15 2 SIO Serial Peripheral Interface SPI The Serial I O implements one SPI controller that supports master mode Note SIO SPI can operate up to 20 MHz 15 2 1 Signal Descriptions Table 15 1 SPI Interface Signals Signal Name Direction Type Description SPI1 a SPI Serial Clock Sus 2 active low a 15 2 1 1 Clock Phase and Polarity SPI clock phase and clock polarity overview The SSCR1 SPO polarity setting bit determines whether the serial transfer occurs on the rising edge of the clock or the falling edge of the clock When SSCR1 SPO 0 the inactive or idle state of SIO SPI CLK is low When SSCR1 SPO 1 the inactive or idle state of SIO SPI is high The SSCR1 SPH phase setting bit selects the relationship of the serial clock with the slave select signal When SSCR1 SPH 0 SIO SPI CLK is inactive until one cycle after the start of a frame and active until 1 2 cycle after the end of a frame Datasheet Volume 1 of 3 115 tel Serial 510 Overview When SSCR1 SPH 0 SIO SPI CLK is inactive until 1 2 cycle after the start
88. Output goes to 0 for one clock time then back to 1 and counter is reloaded Square wave output Output is 1 Output goes to 0 when counter rolls over and 3 counter is reloaded Output goes to 1 when counter rolls over and counter is reloaded and so forth 4 Software triggered strobe Output is 1 Output goes to 0 when count expires for one clock time 5 Hardware triggered strobe Output is 1 Output goes to 0 when count expires for one clock time Reading From the Interval Timer It is often desirable to read the value of a counter without disturbing the count in progress There are three methods for reading the counters a simple read operation counter Latch command and the Read Back command Each is explained below With the simple read and counter latch command methods the count must be read according to the programmed format specifically if the counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other Read write or programming operations for other counters may be inserted between them Simple Read The first method is to perform a simple read operation The counter is selected through Port 40h Counter 0 41h Counter 1 or 42h Counter 2 Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel Note 16 10 3 2 2 16 10 3 2 3 Performing a direct read from the counter does not return a determinate value
89. Pad Broadcast Write Registers Group7 0x4400 FamilyO Pad Registers Group8 0x4800 Family1 Pad Registers Group9 16 12 5 Register Address Mapping The following table describes registers description and number and its CFIO controller Table 16 31 Register Address Mapping Sheet 1 of 2 address offset according to pad Address Default Name Description 0x0000 OxFFFF_FFFF gpio_read_access_policy_access_reg GPIO Read Access Control 0x0100 OxFFFF_FFFF gpio_write_access_policy_access_reg GPIO Write Access Control 0x0200 0x0000_0000 gpio wake status reg O GPIO WAKE STATUS REG 0 0x0280 0x0000 0000 gpio wake mask reg 0 GPIO WAKE MASK REG 0 0x0300 0x0000 0000 gpio interrupt status GPIO Interrupt Status 0x0380 0x0000 0000 gpio interrupt mask GPIO Interrupt Status 0x1000 0x0000 0000 gpio family bw mask 31 0 GPIO Broadcast Data Mask bit Register 0x1004 0x0000 0000 gpio family bw data 31 0 GPIO Broadcast Data Register 0x1008 0x0000 0000 gpio family broadcast reg mask 0 gpio family broadcast reg mask 0 0x1080 Varies family name family rcomp control reg RCOMP Control Register 0x20 family Datasheet Volume 1 of 3 173 t el Platform Controller Unit PCU Overview Table 16 31 Register Address Mapping Sheet 2 of 2 Address Default Name Description 0x1084 Varies family name family rcomp offset
90. RTC block Both of these would likely be implemented as crystal references The different inputs and outputs are listed in the following tables SoC Clock Inputs Clock Domain Signal Name Frequency Usage Description OSCIN Reference crystal for the iCLK PLL Main OSCOUT 19 2 MHz RTC X1 RTC crystal I O for RTC block RTC X2 32 768 KHz Can be configured as an input to LPC LPC CLK S MULT 9r compensate for board routing delays through Soft Strap SoC Clock Outputs Sheet 1 of 2 Clock Domain Signal Name Frequency Usage Description DDR3 MO CKP 1 0 Drives the Memory ranks 0 1 Data rate MT s is 2x the clock rate DDR DDR3 MO CKN 1 0 800 MHz DDR3 1 CKP 1 0 DDR3 Mi CKN 1 0 MMC1 Clock for Storage Devices SDHC SD2 CLK 200 MHz SD3 CLK 20 MHz Clock for SPI flash 20 MHz by default SPI FST SPI CLK 33 MHz 50 MHz COMMS PMC_SUSCLK 0 32 768 KHz Pass through clock from RTC oscillator LPC LPC CLK 0 1 5 Provided to devices requiring LPC clock DisplayPort DDIO TXP 3 0 DDIO_TXN 3 0 DDI1_TXP 3 0 DDI1_TXN 3 0 DDI2_TXP 3 0 DDI2_TXN 3 0 162 or 270 MHz Differential clock for DP devices Datasheet Volume 1 of 3 53 intel Table 4 2 SoC Clock Outputs Sheet 2 of 2 Clock Domain HDMI Signal Name DDIO TXP 3 0 DDIO_TXN 3 0 DDI1_TXP 3 0 DDI1_TXN 3 0 DDI2_TXP 3 0 DDI2_TXN 3 0 Frequency 25 297 MHz
91. SDMMC2 D3 CD N MF SMB ALERT N MF SMB CLK MF SMB DATA SPKR 5 1 SPI1 50 SPI1 51 SPI1_MISO SPI1_MOSI SVIDO_ALERT_N SVIDO_CLK SVIDO_DATA PROCHOT_N USB_OCO_N USB_OC1_N Datasheet Volume 1 of 3 Default Mode Default Function SDMMC3_CLK SDMMC3_CMD SDMMC3 DO SDMMC3 Di SDMMC3 D2 SDMMC3 D3 SDMMC3 PWR SDMMC2 CLK SDMMC2 CMD SDMMC2 DO SDMMC2 Di SDMMC2 D2 SDMMC2 D3 CD N SMB ALERT N SMB CLK SMB DATA SPKR SPIi SPI1 CSO SPI1 51 SPI1 MISO SPI1 MOSI SVIDO ALERT SVIDO SVIDO DATA PROCHOT N USB OCO N USB 5 V3P3A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 88 Pwrgood Assert State 0 20k PD Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU 1 20k PD 0 20k PD Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Input 20k PU Input 20k PU Input 20k PU 0 20k PU 0 20k PU 1 20k PU 1 20k PU Input 20k PU 0 20k PU Input 0 0 2 Input 20k PU Input 20k PU Resetout De assert State 0 Z 20k PU Z
92. SERIRQ are also ANDed with the corresponding internal interrupts For example if IRQ10 is set to be used as the SCI then it is ANDed with the decoded value for IRQ10 from the SERIRQ stream Table 16 22 SERIRQ Interrupt Mapping Sheet 1 of 2 158 Frame Interrupt 2 Comment 1 IRQO 2 Ignored Can only be generated by means of the internal 8524 2 IRQ1 5 Before port 60h latch 3 SMI 8 Causes SMI if low Sets SMI STS ILB SMI STS register bit 4 IRQ3 11 5 1804 14 6 IRQ5 17 7 IRQ6 20 8 IRQ7 23 9 IRQ8 26 Ignored IRQ8 can only be generated internally 10 1809 29 11 180910 32 12 IRQ11 35 13 IRQ12 38 Before port 60h latch 14 IRQ13 41 Ignored 15 IRQ14 44 Ignored 16 IRQ15 47 17 IOCHCK 50 Same as ISA IOCHCK going active Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel Table 16 22 SERIRQ Interrupt Mapping Sheet 2 of 2 16 8 3 16 8 3 1 Data Interrupt 2 Comment 18 PCI INTA 53 19 PCI INTB 56 20 PCI INTC 59 21 PCI INTD 62 Use LPC Clock Delay Compensation In order to meet LPC interface AC timing requirements a LPC clock loop back is required The operation of this loop back can be configured in two ways 1 the SoC In this configuration LPC CLK 0 is looped back on itself on the SoC pad a Benefit LPC CLK 0 and LPC CLK 1 are both available for system clocking b Dra
93. Table 2 23 Power Management Unit PMU Signals and Clocks 2 3 10 Sheet 2 of 2 Default Buffer State Signal Name Dir podia Type Pwrgood Assert Resetout ower State De assert State SDI 0 1 yo GPIOMV MS Input 20K PD Input 20K PD MF 500 MS Input 20K PD Input 20K PD MF HDA SYNC yo GPIOMV MS Input 20K PD Input 20K PD Notes The processor HD Audio logic buffers can support 1 8V However functionality with 1 8V has not been validated Power Management Unit PMU Signals Default Buffer State Signal Name Dir Platform Type Pwrgood Assert Resetout Power State De assert State PRESENT V1P8A GPIOMV MS Input 20K PD Input 20K PD PMU BATLOW GPIOMV MS Input 20K PU Input 20K PU PMU PLTRST N I O V1P8A GPIOMV MS 0 20K PU 1 PWRBTN I GPIOMV MS Input 20K PU Input 20K PU PMU RESETBUTTON GPIOMV MS Input 20K PU Input 20K PU PMU SLP LAN N I O V1P8A GPIOMV MS 0 20K PU 0 LAN I GPIOMV MS Input 20K PU Input 20K PU PMU SLP S3 N I O V1P8A GPIOMV MS 0 20K PU 1 PMU SLP S4 N V1P8A GPIOMV MS 0 20K PU 1 PMU WAKE N GPIOMV MS Input 20K PU Input 20K PU PMU_SUSCLK I O V1P8A GPIOMV MS 0 20K P
94. Top Swap indicator BIOS EFI Controlled BIOS EFI can use the GCS TS register bit to set the Top Swap indicator The GCS TS bit is stored in the RTC well and therefore keeps its value even when the system is powered down Writes to GCS TS will be unsuccessful if the GCS BILD bit has been set Datasheet Volume 1 of 3 125 Platform Controller Unit PCU Overview 16 1 1 2 Note Note 16 1 2 Note Table 16 1 16 2 16 2 1 Note Table 16 2 126 Hardware Controlled System hardware external to the SoC can be used to assert or de assert the Top Swap strapping input signal If the signal is sampled as being asserted during power up then Top Swap is active The Top Swap strap is an active low signal and is multiplexed with the GPIO SUS2 signal The Top Swap strap when asserted at power up forces Top Swap to be active even if GCS TS bit is cleared but does not change the GCS TS bit itself The GCS TS bit can not be changed if Top Swap pin strap was sampled as being asserted until the next power up when Top Swap is sampled as being de asserted BIOS EFI Boot Strap BIOS EFI may be booted from the PCU SPI interface or the iLB LPC interface The choice of SPI or LPC is configured by the BIOS EFI Boot Strap BBS The possible configurations of the BBS are indicated in Table 16 1 1 BBS is multiplexed with the 5054 signal 2 BIOS EFI boot from the LPC interface is not
95. V1P8A G3 51 SUSA AD36 VSS 18 GPIO V1P8A 48 GPIO 5053 VSS 19 GPIO V1P8A 50 5052 AD44 VSS G1 SDIO V3P3A 1 AD52 5051 AE1 VSS AD16 DDI_VGG AD51 GPIO_SUSO AE11 VSS AD18 DDI_VGG AK42 GPIO_DFX8 AE12 VSS AD19 DDI_VGG AK41 GPIO_DFX7 AE14 VSS 16 DDI_VGG AM48 GPIO_DFX6 AE40 VSS 18 DDI_VGG AK48 GPIO_DFX5 AE42 VSS AF19 47 GPIO_DFX4 AE43 VSS AF21 AM45 GPIO DFX3 AE45 VSS AF22 DDI VGG AM44 GPIO DFX2 AE46 VSS AG16 AM41 GPIO DFX1 48 VSS 18 DDI_VGG AM40 GPIO_DFXO AE50 VSS AG19 DDI_VGG GPIO_ALERT AE53 VSS AG21 DDI_VGG AK12 GP_SSP_2_TXD AE6 VSS AG22 DDI_VGG AK13 GP_SSP_2_RXD AE8 VSS AG24 DDI_VGG AK10 GP_SSP_2_FS VSS AJ19 DDI VGG AK9 GP SSP 2 CLK AF10 VSS 121 DDI VGG V40 GP CAMERASB11 24 VSS 122 DDI VGG Y41 GP_CAMERASB10 AF25 VSS AJ24 DDI VGG 42 _ 9 AF32 VSS AK24 DDI_VGG Y44 5 08 AF38 55 135 FUSE V1P15 AB40 CAMERASBO7 AF47 VSS AK33 FUSE 5 AA51 GP CAMERASBO6 AG25 VSS G10 FUSEO V1P05A G3 AB52 5 5 AH10 VSS H10 FUSE1 V1P05A AB51 GP CAMERASBO04 AH12 VSS N18 FUSE3 1 G5 AC53 GP 5 200 Datasheet Volume 1 of 3 Ball Ball Out SoC Pin Locations
96. along with four registers A D that are used for configuration of the RTC The extended bank contains a full 128 bytes of battery backed SRAM All data movement between the host processor and the RTC is done through registers mapped to the standard I O space Datasheet Volume 1 of 3 163 m Platform Controller Unit PCU Overview Note Registers reg IR type and reg TR type are used for data movement to and from the standard bank Registers reg type and reg RTR type are used for data movement to and from the extended bank All of these registers have alias I O locations as indicated in Table 16 25 Table 16 25 Registers Alias Locations Register Original I O Location Alias I O Location reg IR type 70h 74h reg RTC TR type 71h 75h reg RTC RIR type 72h 76h reg RTC RTR type 73h 77h 16 9 6 Indexed Registers The RTC contains indexed registers that are accessed by means of the reg RTC IR type and reg RTC TR type registers Table 16 26 RTC Indexed Registers Start End Name 00h 00h Seconds 01 Oih Seconds Alarm 02h 02h Minutes 03h 03h Minutes Alarm 04h 04h Hours 05h 05h Hours Alarm 06h 06h Day of Week 07h 07h Day of Month 08h 08h Month 09h 09h Year OAh OAh Register A OBh OBh Register B OCh OCh Register C ODh ODh Register D OEh 7Fh 114 Bytes of User RAM 16 10 PCU
97. and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled 88 Datasheet Volume 1 of 3 System Memory Controller n tel 7 System Memory Controller 7 1 DDR3L Interface Signals Table 7 1 Memory Channel 0 DDR3L Signals Sheet 1 of 2 Signal Name cw Description DDR3 MO CK 1 0 P Clock PAD 1 pair per Rank Driven to DRAM DDR3 MO CK 1 0 N DDR3 Chip Select 1 Rank Driven by to DRAM DDR3 MO CS 1 0 DDR3 Clock Enable power management Driven by PHY to DDR3 MO CKE 1 0 DDR3 DRAM Memory Address Driven by to DRAM DDR3 MO MA 15 0 DDR3 Bank Select Driven to DRAM DDR3 MO BS 2 0 DDR3 Row Address Select Used with 5 DDR3 MO RAS DDR3 DDR3 MO WEZ along with DDR3 MO 5 to define the DRAM Commands Column Address Select Used with DDR3 RAS DDR3 MO CAS N DDR3 and DDR3 MO along with DDR3 5 to define the SRAM Commands Write Enable Control Signal Used with DDR3 MO WE DDR3 WE DDR3 MO 5 along with control signal DDR3 MO 5 to define the DRAM Commands 3 I O Data Lines Bidirectional signals between DRAM PHY DDR3 MO DQ 63 0 DDR3 Data Mask DM is an ou
98. available when Secure Boot is enabled BBS Configurations BBS Level Description Low 0b Boot from LPC High 1b Boot from SPI PMU Power Management Controller PMC The Power Management Controller PMC controls many of the power management features present in the SoC Signal Descriptions These signals are part of CFIO GPIO and may be used by other functions PMC Signals Sheet 1 of 2 4 Direction Signal Name Type Description PMU AC PRESENT I AC Present This input pin indicates when the platform is CMOS 1 8 plugged into AC power Battery Low An input from the battery to indicate that there is insufficient power to boot the system Assertion will prevent I wake from the S4 S5 state This signal can also be enabled to CMOS V1P8 cause an SMI when asserted In desktop configurations without a battery this signal should be tied high to 1 S5 PMU_BATLOW Platform Reset The SoC asserts this signal to reset devices on the platform The SoC asserts the signal during power up CMOS 8 when software initiates hard reset sequence through the Reset Control 5 register Datasheet Volume 1 of 3 Platform Controller Unit Overview Table 16 2 PMC Signals Sheet 2 of 2 Signal Name Description ype Power Button The signal will cause SMI or SCI to indicate a system request to
99. battery voltage is valid The RC time delay should be in the 10 20 ms range Contact your Intel representative for details If the battery is missing weak this signal appears low asserted at boot just after the suspend power rail V3P3A is up since it will not have time to meet when is high The weak missing battery condition is reported in the 1 5 Power Status register When asserted BIOS may clear the RTC CMOS RAM Note RSM_RST signal needs to toggle in order for bit status to propagate and reflect in the GEN PMCON registers Notes Unless CMOS is being cleared only to be done in the G3 power state or the battery is low the signal input must always be high when all other RTC power planes are on Notes This signal may also be used for debug purposes as part of a XDP port Contact your Intel representative for details COREPOWER I CMOS V3P3 Core Power OK When asserted this signal is an indication to the SoC that all of its core power rails have been stable for 10 ms It can be driven asynchronously When it is negated the SoC asserts PMC_PLTRST Note It is required that the power rails associated with PCI Express typically the 3 3V 5V and 12V core well rails have been valid for 99 ms prior to PMC CORE PWROK assertion in order to comply with the 100 ms TPVPERL PCI Express 2 0 specification on PMC_PLTRST de assertion Note PMC CORE PWROK must not glitch even i
100. be assumed to be populated DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals which the SDRAM controller supports The processor drives four CKE pins to perform these operations Initialization Role of CKE During power up CKE is the only input to the SDRAM that is recognized other than the DDR3 reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up Datasheet Volume 1 of 3 67 tel Power Management 6 4 2 2 6 4 2 3 6 4 2 4 68 CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is guaranteed to remain inactive for much longer than the specified 200 micro seconds after power and clocks to SDRAM devices are stable Conditional Self Refresh Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh the package low power states Intel RMPM functionality depends on graphics display state relevant only when internal graphics is being used as well as memory traffic patterns generated by other connected I O devices When entering the Suspend to RAM STR state the processor core flushes pending cycles and then places all SDRAM ranks into self refresh
101. compatible platform These hardware blocks include e PMU Power Management Controller PMC e PCU Serial Peripheral Interface SPI For boot FW and system configuration data Flash storage Note Flash Sharing is not supported for the processor Platforms Note Fast SPI signals do not get tri stated during RSMRST assertion e PCU Universal Asynchronous Receiver Transmitter UART e PCU Intel Legacy Block iLB Overview The PCU also implements some high level configuration features for BIOS EFI boot PCU Configuration Features for BIOS EFI Boot Overview BIOS EFI Top Swap While updating the BIOS EFI boot sector in flash unexpected system power loss can cause an incomplete write resulting in a corrupt boot sector For this reason two boot sectors are stored in the flash The location of the secondary boot sector is defined by inverting one of the bits of the address A16 A17 or A18 that the processor core will attempt to fetch code from This address bit will vary depending on the size of the boot block BBSize register bit definition for further details Prior to starting writes to the primary BIOS EFI boot sector the Top Swap indicator is set From this point onwards the secondary boot sector will be used Only after successful completion of the primary boot sector write should the Top Swap indicator be cleared and the primary boot sector be used again There are two methods that can be used to implement the
102. data structures and prevent them from being tampered by malicious software e VM Functions VM function is an operation provided by the processor that can be invoked using the VMFUNC instruction from guest VM without a VM exit function to perform EPTP switching is supported and allows guest VM to load a new value for the EPT pointer thereby establishing a different EPT paging structure hierarchy 3 3 Security and Cryptography Technologies 3 3 1 PCLMULQDQ Instruction The processor supports the carry less multiplication instruction PCLMULQDQ PCLMULQDO is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication 50 Datasheet Volume 1 of 3 Processor Core 3 3 2 3 3 3 3 4 3 5 intel Digital Random Number Generator The processor introduces a software visible digital random number generation mechanism supported by a high quality entropy source This capability is available to programmers through the new RDRAND instruction The resultant random number generation capability is designed to comply with existing industry standards ANSI X9 82 and NIST SP 800 9
103. diode drop 50 G3 HD Audio VCCCFIOAZA 1P80 1 5V or 1 8V fixed voltage _ 15 18 for HD Audio 5 50 55 Notes 1 The voltage supply for SDIO can be 1 8V or 3 3V Datasheet Volume 1 of 3 27 m e n e Physical Interfaces Table 2 2 Buffer Type Definitions Buffer Type Buffer Description MIPI DPHY 1 24V tolerant MIPI DPHY buffer type USB3 PHY 1 0V tolerant USB3 PHY buffer type USB2 PHY 1 8V tolerant USB3 PHY buffer type HSIC PHY 1 2V tolerant HSIC PHY buffer type SATA PHY 1 0V tolerant SATA PHY buffer type PCIe PHY 1 0V tolerant PCIe PHY buffer type RTC PHY 3 3V tolerant RTC PHY buffer type GPIO GPIO buffer type This can be of the following types 1 8 3 3V MODPHY 1 0V tolerant MODPHY buffer type DDR3 1 5V tolerant DDR3 buffer type Analog Analog pins that do not have specific digital requirements Often used for circuit calibration or monitoring GPIOMV HS GPIO Buffer type Medium Voltage 1 8V High Speed FMAX 208 MHz GPIOMV MS GPIO Buffer type Medium Voltage 1 8V Medium Speed FMAX 60 MHz GPIOMV MS CLK GPIO Buffer type Medium Voltage 1 8V Medium Speed FMAX 60 MHz Clock GPIOMV HS GPIO Buffer type Medium Voltage 1 8V High Speed FMAX 208 MHz Clock GPIOMV HS RCOMP GPIO Buffer type Medium Voltage 1 8V High Speed FMAX 208 MHz RCOMP GPIOMV MS I2C GPIO Buffer type Medium Voltage 1 8V Medium Speed FMAX 60 MHz
104. do not result in any LPC transactions Power Management LPCPD Protocol Same timings as for 505 After driving 505 STAT active the SoC drives low and tri states or drives low AD 3 0 The Low Pin Count Interface Specification Revision 1 1 defines the LPCPD protocol where there is at least 30 us from LPCPD assertion to LRST assertion This specification explicitly states that this protocol only applies to entry exit of low power states which does not include asynchronous reset events The SoC asserts both 505 STAT connects to LPCPD and PLTRST connects to LRST at the same time during a global reset This is not inconsistent with the LPC LPCPD protocol Clock Run CLKRUN When there are no pending LPC cycles and SERIRQ is in quiet mode the SoC can shut down the LPC clock The SoC indicates that the LPC clock is going to shut down by de asserting the CLKRUNZ signal LPC devices that require the clock to stay running should drive CLKRUNZ low within 4 clocks of its de assertion If no device drives the signal low within 4 clocks the LPC clock will stop If a device asserts LPC CLKRUNZ the SoC will start the LPC clock and assert CLKRUNZ The CLKRUN protocol is disabled by default See Section 16 8 3 2 2 Clock Run Enable on page 160 for further details Serialized IRQ SERIRQ Overview The interrupt control
105. example 225 intel Table 21 8 Integrated Clock Crystal Specification 21 6 Note 226 Electrical Specifications Symbol Parameter Min Units Notes 19 2 MHz 1 Toon ed PNE T tolerance 30 30 1 PpRIVE Crystal drive load 100 uW 1 Resr ESR 80 Ohm 1 Ci oAD Crystal load capacitance 12 pF Crystal shunt capacitance 2 pF 1 Ci C2 Load Capacitance tolerance 10 10 1 Note 1 These are the specifications needed to select a crystal oscillator for the Integrated Clock circuit Crystal must be AT cut fundamental parallel resonance DC Specifications Platform reference voltages are specified at DC only measurements should be made with respect to the supply voltages specified in Section 21 4 Voltage and Current Specifications on page 217 Maximum and Minimum values are bounded by reference voltages See the following DC Specifications in this section Section 21 6 1 Display DC Specification on page 227 Section 21 6 2 MIPI Camera Serial Interface CSI DC Specification on page 232 Section 21 6 3 SCC SDIO DC Specification on page 232 Section 21 6 4 SCC SD DC Specification on page 232 Section 21 6 5 eMMC 4 51 DC Electrical Specification on page 233 Section 21 6 6 JTAG DC Specification on page 234 Section 21 6 7 DDR3L Memor
106. iLB 8254 Timers The 8254 contains three counters which have fixed uses including system timer and speaker tone All registers are clocked by a 14 31818 MHz clock 16 10 1 Signal Descriptions See Chapter 2 Physical Interfaces for additional details 164 Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview tel Table 16 27 8254 Signals Direction Type Signal Name Description Speaker The signal drives an external speaker driver device which in turn drives the system speaker Upon PMC_PLTRST its output state is 0 This signal is multiplexed and may be used by other functions ILB 8254 SPKR 16 10 2 Features 16 10 2 1 Counter 0 System Timer This counter functions as the system timer by controlling the state of IRQO and is programmed for Mode 3 operation The counter produces a square wave with a period equal to the product of the counter period 838 ns and the initial count value The counter loads the initial count value one counter period after software writes the count value to the counter I O address The counter initially asserts IRQO and decrements the count value by two each counter period The counter negates IRQO when the count value reaches 0 It then reloads the initial count value and again decrements the initial count value by two each counter period The counter then asserts IRQO when the count value reaches 0 reloads the initial count value and repeats the
107. impedance requirement when an off receiver s input goes below output 4 All transmitters shall be AC coupled The AC coupling is required either within the media or within the transmitting component itself 21 6 11 LPC DC Specification Table 21 27 LPC 1 8V Signal Group DC Specification Symbol Parameter Min Input High Voltage 1 5 Input Low Voltage 0 5 Output High Voltage 0 9 x 1 8 VoL Output Low Voltage Output High Current Output Low Current ILEAK Input Leakage Current 10 Input Capacitance 238 Datasheet Volume 1 of 3 Electrical Specifications Table 21 28 LPC 3 3V Signal Group DC Specification Parameter Typ Max Units Notes Input High Voltage 3 3 3 3 0 5 V 1 Input Low Voltage 0 0 8 V 2 Output High Voltage V 3 Output Low Voltage 0 4 V 3 Output High Current 0 5 mA 3 Output Low Current 1 5 x mA 3 Input Leakage Current 10 10 Input Capacitance 10 Notes 1 defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value Applies to LPC AD 3 0 LPC CLKRUN N is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value Applies to LPC AD 3 0 CLKRUN is tested with Iout 500uA Vo is tested with Iout21500uA A
108. its internal caches or floating point registers The cores then begin execution at the power on Reset vector configured during power on configuration Table 16 7 INIT Assertion Causes Datasheet Volume 1 of 3 Cause PORT92 INIT NOW transitions from Ob toib RST CNT SYS RST Ob and RST CNT RST CPU transitions from Ob to 1b 133 intel 16 2 3 16 3 Note Note Note 16 3 1 Table 16 8 134 References Platform Controller Unit PCU Overview Advanced Configuration and Power Interface Specification Revision 3 0 http www acpi info PCU Serial Peripheral Interface SPI The SoC implements a SPI controller as the interface for BIOS Flash storage This SPI Flash device is also required to support configuration storage for the firmware for the Trusted Execution Engine The controller supports a maximum of two SPI Flash devices using two chip select signals with speeds of 20 MHz 33 MHz or 50 MHz Dual and Quad I O Flash devices are supported in addition to standard flash devices The default interface speed is 20 MHz Frequency capability of the Flash Component should be higher than the maximum set frequency of SPI bus Flash Sharing is not supported for the processor platforms Fast SPI signals do not get tri stated during RSMRST assertion Signal Descriptions SPI Signals Signal Name Description ype FST SPI CLK ER Tin Clock When the bus is id
109. level Intel branded products are specified and certified to meet the following temperature and humidity limits Non Operating Temperature Limit 40 C to 70 C Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C 216 Datasheet Volume 1 of 3 Electrical Specifications 21 4 Note Note intel Voltage and Current Specifications The I O buffer supply voltages are specified at the SoC package balls The tolerances shown in Table 21 3 are inclusive of all noise from DC up to 20 MHz The voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of 3 dB decade above 20 MHz under all operating conditions Table 21 4 indicates which supplies are connected directly to a voltage regulator or to a filtered voltage rail For voltage rails that are connected to a filter they should be measured at the input of the filter If the recommended platform decoupling guidelines cannot be met the system designer will have to make trade offs between the voltage regulator out DC tolerance and the decoupling performances of the capacitor network to stay within the voltage tolerances listed below The SoC is a pre launch product Voltage and current specifications are subject to change average current draw G5 is specified at 27 under battery conditions Table 21 3 SoC Power Rail DC Specifications and Maximum Current
110. of the signal pin Direction The buffer direction can be either input output or I O bidirectional Type The buffer type is in Chapter 21 Electrical Specifications Description A brief explanation of the signal function The processor SoC has a maximum of 198 GPIOs and these GPIOs are divided into 4 communities GPIOs are multiplexed with other alternate modes GPIO Controller The GPIO controllers handle all GPIO CFIO interface to the processor SoC GPIO NORTH used for Camera sensors DFX SVID and as Display Pins GPIO SOUTHEAST Defines the Pads Pins for MMC Storage SD host controllers for storage and COMMS LPC Pins Fast SPI Pins and Platform clock GPIO SOUTHWEST Defines the Pads Pins for HS UART I2C HS PCIe SMBus and SPI Pins GPIO EAST Defines the Pads SoC power state related signals of PMU and ISH Pins ISH Integrated Sensor Hub is not supported for the processor however the GPIOs can be used for other functionality Use Each GPIO has six registers that control how it is used or report its status Use Select Select e GPIO Level e Trigger Positive Edge Trigger Negative Edge e Trigger Status The Use Select register selects a GPIO pin as a GPIO or leaves it as its programmed function This register must be set for all other registers to affect the GPIO The I O Select register determines the direction of the GPIO The Trigger Positive Edge and Trigger Negati
111. provided with the component data sheet Datasheet Volume 1 of 3 243 m e n Electrical Specifications 21 6 21 SMBus System Management DC Specification Table 21 41 SMBus DC Specification Symbol Parameter Min Units Notes Supply voltage 1 89 Input High Voltage 2 1 5 5 V Vit Input Low Voltage 0 8 V Output High Voltage V VoL Output Low Voltage 0 4 V 1 Input Leakage Current 5 5 Ipullup Pull Up current 100 350 Note 1 AtIout 350 uA 21 6 22 PCI Express DC Specification Table 21 42 PCI Express DC Receiver Signal Characteristics Symbol Parameter Min Units Notes VnxIDFF Differential RX Peak to Peak 175 _ 1200 1 Gen1 VnxipFF Differential RX Peak to Peak 100 _ 1200 1 Gen1 Note 1 PCI Express peak to peak 2 RXp x RXn x Table 21 43 PCI Express DC Transmit Signal Characteristics Symbol Parameter Min Units Notes VIXDIFF Differential TX Peak to Peak 800 1200 1 Differential TX Peak to Peak VIXDIFF LP Low power mode 400 7 1299 my z Note 1 PCI Express peak to peak 2 RXp x RXn x Table 21 44 PCI Express DC Clock Request Input Signal Characteristics Symbol Parameter Min Typ Max Units Notes VREF Voltage UNCORE_V1P8_S4 V
112. provides a mechanism for the processor to initiate communications with SMBus peripherals slaves The SoC is also capable of operating in a mode in which it can communicate with 12 compatible devices The SoC can perform SMBus messages with packet error checking PEC enabled or disabled The actual PEC calculation and checking can be performed in either hardware or software The SMBus Address Resolution Protocol ARP is supported by using the existing host controller commands through software except for the Host Notify command which is actually a received message The programming model of the host controller is combined into two portions a PCI configuration portion and a system I O mapped portion static configurations such as the I O base address is done using the PCI configuration space Real time programming of the Host interface is done in system I O space Figure 16 1 Platform Control Unit System Management Bus 16 6 1 Signal Descriptions See Chapter 2 Physical Interfaces for additional details Table 16 12 SMBus Signal Names 142 Direction Signal Name Type Description SMBus Alert SMB ALERT Z 8 This signal is used to generate internal SMI This signal is multiplexed and may be used by other functions SMBus Clock PCU SMB CLK CMOS1 8 External pull up resistor is required This signal is multiplexed and may be used by other functions
113. receiver interrupts occur as follows The receive data available interrupt is invoked when the FIFO has reached its programmed trigger level The interrupt is cleared when the FIFO drops below the programmed trigger level The IIR receive data available indication also occurs when the FIFO trigger level is reached and like the interrupt the bits are cleared when the FIFO drops below the trigger level e The receiver line status interrupt IIR C6h as before has the highest priority The receiver data available interrupt IIR C4h is lower The line status interrupt occurs only when the character at the top of the FIFO has errors The COM1_LSR DR bit is set to 1b as soon as a character is transferred from the shift register to the Receive FIFO This bit is reset to Ob when the FIFO is empty Character Timeout Interrupt When the receiver FIFO and receiver time out interrupt are enabled a character time out interrupt occurs when all of the following conditions exist e At least one character is in the FIFO e The last received character was longer than four continuous character times ago if two stop bits are programmed the second one is included in this time delay The most recent processor read of the FIFO was longer than four continuous character times ago e The receiver FIFO trigger level is greater than one Datasheet Volume 1 of 3 139 m Platform Controller Unit PCU Overview
114. register an interrupt is generated to the LPE The LPE firmware sees there is a message waiting from the SoC Processor Core and reads the IPCX register for the data This data is a pre configured message where the message structure has been decided beforehand between the SoC Processor Core and the LPE Similarly we have the IPCD register for the communication between the LPE and SoC Processor Core Once the LPE writes to the IPCD register an interrupt should be generated for the SoC Processor Core and the SoC Processor Core should read the message from the IPCD register and act accordingly From a software viewpoint the mechanism remains the same as before From a hardware view point the interrupt to IA 32 gets routed by means of the IOAPIC block The IPC from Audio to IA 32 gets a dedicated interrupt line to the IOAPIC Interrupts Between PMC and LPE The interrupts between PMC and LPE are also handled using Inter Process Communication registers Datasheet Volume 1 of 3 101 m n tel Low Power Engine LPE for Audio 12 12 4 3 Note 12 4 4 12 5 12 5 1 Table 12 2 102 Power Management Options for the LPE Core WAITI Allows the LPE core to suspend operation until an interrupt occurs by executing the optional WAITI instruction External Run Stall Control Signal This processor input allows external logic to stall large portions of the LPE pipeline by shutting off the clock to much of the process
115. sensors and the camera peripherals such as flash LED and lens motor Camera Sideband for Camera Interface Twelve 12 GPIO signals GP_CAMERASB 11 00 are allocated for camera functions refer to Table 9 2 for signal names These GPIOs are multiplexed and are available for other usages without powering on the ISP The ISP provides a timing control block through which the GPIOs can be controlled to support assertion de assertion pulse widths and delay The configuration of camera GPIOs listed below is just an example of how the GPIOs can be used Several of these functions could be implemented using 12 depending on the sensor implementation for the platform e Sensor Reset signals Force hardware reset on one or more of the sensors Sensor Single Shot Trigger signal Indicate that the target sensor needs to send a full frame in a single shot mode or to capture the full frame for flash synchronization PreLight Trigger signal Light up a pilot lamp prior to firing the flash for preventing red eye Flash Trigger signal Indicate that a full frame is about to be captured The Flash fires when it detects an assertion of the signal Sensor Strobe Trigger signal Asserted by the target sensor to indicate the start of a full frame when it is configured in the single shot mode or to indicate a flash exposed frame for flash synchronization Datasheet Volume 1 of 3 85 m e n MIPI CSI Camera Serial Int
116. supports accessing Trusted Platform Module TPM 1 2 devices by means of the LPC TPM START encoding Memory addresses within the range 00000 to FEDAOFFFh will be accepted by the LPC Bridge and sent on LPC as TPM special cycles No additional checking of the memory cycle is performed This is different to the FEDO0O000h to FED4BFFFh range implemented on some other Intel components since no Intel Trusted Execution Technology Intel TXT transactions are supported FWH Cycle Notes If the LPC controller receives any SYNC returned from the device other than short 0101 long wait 0110 or ready 0000 when running a FWH cycle indeterminate results may occur A FWH device is not allowed to assert an Error SYNC BIOS EFI boot from LPC is not supported when Secure Boot is enabled No validation has been done with BIOS on LPC Reference design uses SPI Datasheet Volume 1 of 3 155 m Platform Controller Unit PCU Overview 16 8 2 4 16 8 2 5 Note 16 8 2 6 16 8 2 6 1 Note 16 8 2 6 2 Note 16 8 2 7 16 8 2 7 1 156 Subtractive Decode cycles that are not decoded internally and are not targeted for LPC that is configuration cycles I O cycles above 64KB and memory cycles above 16MB will be sent to LPC with FRAME Z not asserted POST Code Redirection Writes to addresses 80h 8Fh in I O register space will also be passed to the LPC bus Reads of these addresses
117. the trailing edge of the second INTA While the ISR bit is set all further interrupts of the same or lower priority are inhibited while higher levels generate another interrupt Interrupt priorities can be changed in the rotating priority mode Special Fully Nested Mode This mode is used in the case of a system where cascading is used and the priority has to be conserved within each slave In this case the special fully nested mode is programmed to the master controller This mode is similar to the fully nested mode with the following exceptions When an interrupt request from a certain slave is in service this slave is not locked out from the master s priority logic and further interrupt requests from higher priority interrupts within the slave are recognized by the master and initiate interrupts to the processor In the normal nested mode a slave is masked out when its request is in service When exiting the Interrupt Service routine software has to check whether the interrupt serviced was the only one from that slave This is done by sending a Non Specific EOI command to the slave and then reading its ISR If it is 0 a non specific EOI can also be sent to the master Automatic Rotation Mode Equal Priority Devices In some applications there are a number of interrupting devices of equal priority Automatic rotation mode provides for a sequential 8 way rotation In this mode a device receives the lowest priority after b
118. this clock can be sourced from XTAL clock 24 MHz or PLL 25 MHz These clocks are then divided down within the serial interface IP to generate the final bit clock for the interface After power on if the SSP input I O clock is in high state first transition of the clock from high to low may be missing due to the SoC clock gating logic M N Divider LPE SSP in master mode uses the SSP CCLK to drive the serial clock It has very limited option to divide CCLK An M N divider is added between the 24 MHz clock XOSC from CCU to each SSP CCLK input as shown in following diagram Datasheet Volume 1 of 3 103 m n tel Low Power Engine LPE for Audio 12 Figure 12 3 SSP CCLK Structure 12 5 6 1 104 XOSC 192 MHz 25 MHz CFG REG MN 55 Is wwj 7 91 CFG REG N 5922 Note The M N divider has a bypass option so VLV could be configured to act same as TNG The LPE M N divider is designed to produce a clock signal for the SSP block used in master mode The divider is based on a generic NOM DENOM divider The supplied Master clock is 24 MHz XTAL or 25 MHz LPPLL but usually be used by the 25 MHz clock This mechanism is good for a wide spectrum of generated clocks Two registers must be configured to get the target SSP clock The values for the Nominator and Denominator registers are the smallest divider of
119. to 1 8V set V1P8 mode in family configuration trigger RCOMP cycle using family RCOMP registers lastly copy RCOMP value to family p and n strength values LPC Clock 0 Out 25 MHz PCI like clock driven to LPC peripherals LPC CLK O HSHV These signals are multiplexed and may be used by other functions 3 3 1 8 LPC Clock 1 Out 25 MHz PCI like clock driven to LPC peripherals Can be LPC CLK 1 HSHV configured as an input to compensate for board routing delays through SoftStrap 3 3 1 8 These signals are multiplexed and may be used by other functions LPC Clock Run Input to determine the status of LPC and an open drain output used to request starting or speeding up ILB LPC CLK This is a sustained tri yo state signal used by the central resource to request permission to stop or slow LPC CLKRUN N ng ILB LPC CLK The central resource is responsible for maintaining the signal in the 3 3 1 8 asserted state when ILB is running and de asserts the signal to request permission to stop or slow ILB LPC CLK An internal pull up is provided for this signal This signal is multiplexed and may be used by other functions LPC Frame This signal indicates the start of LPC cycle or abort LPC FRAME N HSHV This signal is multiplexed and may be used by other functions 3 3 1 8 IO Serial Interrupt Request This signal implements the serial interrupt protocol LPC SERIRQ MSMV This signal is multiplex
120. visit http www intel com go virtualization The original equipment manufacturer must provide TPM functionality which requires a TPM supported BIOS TPM functionality must be initialized andmay not be available in all countries For Enhanced Intel SpeedStep amp Technology see the Processor Spec Finder at http ark intel com or contact your Intel representative for moreinformation Intel AES NI requires a computer system with an AES NI enabled processor as well as non Intel software to execute the instructions in the correctsequence AES NI is available on select Intel processors For availability consult your reseller or system manufacturer For more information see http software intel com en us articles intel advanced encryption standard instructions aes ni Intel Celeron Pentium Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology Intel Display Power Saving Technology Intel DPST Intel Trusted Execution Engine Intel TXE Intel virtualization Technology Intel VT Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x Enhanced Intel SpeedStep Technology Intel Display Power Saving Technology Intel DPST Intel Automatic Display Brightness Intel High Definition Audio Intel HD Audio Intel Performance Primitives Intel Advanced Vector Extensions Intel AVX Intel Rapid Memory Power Management Intel RMPM and the I
121. 0 Some possible uses of the new RDRAND instruction include cryptographic key generation as used in a variety of applications including communication digital signatures secure storage and so forth Power Aware Interrupt Routing PAIR is an improvement in H W routing of redirectable interrupts Each core power state is considered in the routing selection to reduce the power or performance impact of interrupts System BIOS configures the routing algorithm for example fixed priority rotating hash or PAIR during setup by means of non architectural register The PAIR algorithm can be biased to optimize for power or performance and the largest gains will be seen in systems with high interrupt rates Platform Identification and CPUID In addition to verifying the processor signature the intended processor platform type must be determined to properly target the microcode update The intended processor platform type is determined by reading bits 52 50 of the IA32 PLATFORM ID register MSR 17h within the processor This is a 64 bit register that must be read using the RDMSR instruction The 3 Platform ID bits when read as a binary coded decimal BCD number indicate the bit position in the microcode update header s Processor Flags field that is associated with the installed processor Executing the CPUID instruction with 1 will provide the following information EAX Field Description 31
122. 083 _ DDR3 DDR3 MO DDR3 MO AM 050 DDRGMO _ DDR3MO AL paj _ DORB_MO DDR3 Dals 8 GPIO 505 GPIO 505 GPIO 505 5 4 2 sus sus 7 7 SEC GPIO SEC AF SUS9 5158 Datasheet Volume 1 of 3 193 te Ball Map Ball Out and SoC Pin Locations Figure 19 2 Ball Map DDR3L Top Right View Columns 28 4 28 26 25 24 22 21 20 19 18 13 12 11 10 9 8 DOR3 1 DOR3 1 DDR3 M1 DOR3 Mi 7 parz malig DDR3 DDR3 M1 DORZ DDR3 Mi E DDR3 1 02083 Mi DDR3 Mi EX DOR3 Mi DDR3 Mi DOR3 1 DDR3 1 paje2 _ 62 58 Pape DDR3 DDR3 DOR3 DDR3 1 DDR3 1 DOR3 1 Da s7 DDR3 Mi 1 DDR3 DOR3 Mi Doiss _ _ 2 papi T ASB E _ _ eM _ E _ 13 Mi DOR3 DOR3 Maa a Z A MANO m m _ _ DDR3MIDOR3MI _ MAS _ DDR3 Mi DOR Mi DDR3 Mi 99119 poizz 0 50 121 50 5 me 12230 1202 50
123. 1 SEC GPIO 50511 DDR3 MO MA BJ15 VSS AE51 SEC GPIO SUS10 DDR3 MO MA BJ19 VSS P12 SDMMC3_RCOMP DDR3 MO MA BJ23 VSS L3 SDMMC3 PWR EN N DDR3 MO MA BJ27 VSS G2 SDMMC3_D3 DDR3 MO MA BJ31 55 SDMMC3 D2 DDR3 MO MA BJ35 VSS 13 SDMMC3 D1 DDR3 MO MA BJ39 VSS 21 SDMMC3 DO DDR3 MO MA BJ43 VSS D2 SDMMC3 CMD DDR3 MO DRAMRST N 247 VSS F2 SDMMC3 CLK DDR3 MO 0058171 27 VSS K3 SDMMC3 CD N DDR3 0058161 20 55 K2 SDMMC3 1P8 EN DDR3 MO 0058151 C22 VSS K6 SDMMC2_D3_CD_N DDR3 MO DQSB 4 C28 VSS K7 SDMMC2 D2 DDR3 MO 0058131 C3 VSS M10 SDMMC2 D1 DDR3 MO DQSB VSS M12 SDMMC2 DO DDR3 MO DQSB C36 VSS K9 SDMMC2 CMD DDR3 MO DQSB C39 VSS K10 SDMMC2 CLK DDR3 MO 005171 C47 VSS P13 SDMMC1_RCOMP DDR3 MO DGS 6 D10 VSS P7 SDMMC1 03 CD DDR3 MO DQGS 5 016 VSS P9 SDMMC1 02 DDR3 MO DGS 4 024 VSS M4 SDMMC1_D1 DDR3 MO DQGS 3 027 VSS 6 SDMMC1 DO DDR3 MO 005121 032 VSS P6 SDMMC1_CMD DDR3 MO DGS 1 038 VSS 7 5 DDR3 MO DGS 0 D40 VSS C29 SATA TXP1 DDR3 MO DQ 9 042 VSS C31 SATA TXPO DDR3 MO 00181 Datasheet Volume 1 of 3 205 m e n tel Ball Map Ball Out and SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 8 of 11 Pin Pin Name Pin Pin Name Pin Pin Name E19 VSS A29 SATA TXN1 51 DDR3 MO 0071 E35 VSS B30 SATA TXNO BG3
124. 1 Signal Descriptions csici ines even bein a a xin kan bie ndn adn 97 12 2 3 F eatufes uctor i 97 12 2 1 Audio Capabilities cerei ocu n tk Rn xh enin a 98 12 2 1 1 Audio Decode CEU RE REA dE 98 12 2 1 2 Audio Encode esee tease FRENCH ERE 98 12 3 Detailed Block Level ade kx 99 12 3 1 CONS 99 12 3 2 Memory 99 12 3 3 Instruction Closely Coupled Memory 100 12 3 4 Data Closely Coupled Memory 100 12 3 5 Mailbox Memory and Data Exchange 100 12 4 Software Implementation Considerations 101 12 4 1 SoC Processor Core Cache 101 12 4 2 101 12 4 2 1 LPE Peripheral 101 12 4 2 2 Interrupts Between SoC Processor Core and the LPE 101 12 4 2 3 Interr
125. 1 Like DisplayPort embedded DisplayPort also consists of a Main Link Auxiliary channel and a optional Hot Plug Detect signal Each eDP port can be configured for up to 4 lanes DisplayPort Auxiliary Channel A bi directional AC coupled AUX channel interface replaces the 12 for EDID read link management and device control I2C to Aux bridges are required to connect legacy display devices Hot Plug Detect HPD The SoC supports HPD for hot plug sink events on the HDMI and DisplayPort interfaces Integrated Audio Over HDMI and DisplayPort The SoC can support each audio streams on DP HDMI ports Each stream can be programmed to each DDI port High Bandwidth Digital Content Protection HDCP HDCP is the technology for protecting high definition content against unauthorized copy or unreceptive between a source computer digital set top boxes and so forth and the sink panels monitor and TV The SoC supports HDCP 1 4 wired 2 2 wireless for content protection over wired displays HDMI DisplayPort and embedded DisplayPort 3 D Graphics and Video The SoC implements a derivative of the Generation 8 LP graphics engine which consists of rendering engine and bit stream encoder decoder engine The rendering engine is used for 3 D rendering media compositing and video encoding The Graphics engine is built around sixteen execution units EUs Datasheet Volume 1 of 3 75 m n tel Graphics Video and Display
126. 1 41000 1 1 1 0 1 0 1 0 1 41500 1 1 1 0 1 0 1 1 B 1 42000 1 1 1 0 1 1 0 0 1 42500 1 1 1 0 1 1 0 1 E D 1 43000 1 1 0 1 1 1 0 E E 1 43500 1 1 1 0 1 1 1 1 E F 1 44000 1 1 1 1 0 0 0 0 F 0 1 44500 1 1 1 1 0 0 0 1 F 1 1 45000 1 1 1 1 0 0 1 0 F 2 1 45500 1 1 1 1 0 0 1 1 F 3 1 46000 1 1 1 0 1 0 0 F 4 1 46500 1 1 1 1 0 1 0 1 F 5 1 47000 1 1 1 1 0 1 1 0 F 6 1 47500 1 1 1 1 0 1 1 1 F 7 1 48000 1 1 1 1 1 0 0 0 F 8 1 48500 1 1 1 1 1 0 0 1 F 9 1 49000 1 1 1 1 0 1 0 F 1 49500 1 1 1 1 1 0 1 1 B 1 50000 1 1 1 1 1 1 0 0 F 1 49500 1 1 1 1 1 1 0 1 F D 1 50000 1 1 1 1 1 1 1 0 F E 1 49500 1 1 1 1 1 1 1 1 F F 1 50000 There are two crystal oscillators One for RTC which maintains time and provides initial timing reference for power sequencing The other is for the Integrated Clock which covers clocking for the entire processor Table 21 7 ILB RTC Crystal Specification Datasheet Volume 1 of 3 Symbol Parameter Min Units Notes 32 768 KHz 1 Crystal frequency tolerance B see notes 20 ppm 1 RESR ESR 50 KOhm 1 Capacitance of X1 X2 pins 15 1 Notes 1 These are the specifications needed to select a crystal oscillator for the RTC circuit 2 Crystal tolerance impacts RTC time A 10 ppm crystal is recommended for 1 7 second tolerance per day RTC circuit itself contributes addition 10 ppm for a total of 20 ppm in this
127. 1 8 Output Low Voltage 1 8 Input High Voltage 1 8V 1 8 Input Low Voltage 1 8V Iou lor Current at VoL Voh 2 2 mA total Load Capacitance 40 pF 21 6 5 eMMC 4 51 DC Electrical Specification Table 21 19 eMMC 4 51 DC Electrical Specifications Symbol Parameter Min Max Units VREF T O Voltage GPIO_V1P8A_G3 VoH Output HIGH voltage 0 45 V Voi Output LOW voltage 0 45 V Input HIGH voltage 0 65 VREF Vref 0 3 V Vit Input LOW voltage 0 3 0 35 VREF V Bus Signal Line capacitance 30 Input Leakage Current 52 2 Output Leakage Current 2 2 Figure 21 3 4 51 DC Bus Signal Level 4 V Vpp output high level input Von high undefined input low level output Is low level Datasheet Volume 1 of 3 233 m e n Electrical Specifications 21 6 6 JTAG DC Specification Table 21 20 JTAG Signal Group DC Specification JTAG TMS 2 TDI JTAG TRST Symbol Parameter Min Typ Max Units Notes VREF Voltage GPIO_V1P8A_G3 Input High Voltage 0 75 VREF 1 Ve ImpttowVotagg V 2 Rwpu Weak pull up Impedance 2 5 5 7 5 KQ 3 Rwpd Weak pull down Impedance 2 5 5 7 5 3 4 Weak pull down Impedance 40K 20 70 KQ 4 Notes 1
128. 1000 0 1 0 0 1 0 1 0 4 0 61500 0 1 0 0 1 0 1 1 4 B 0 62000 0 1 0 0 1 1 0 0 4 0 62500 0 1 0 0 1 1 0 1 4 D 0 63000 0 1 0 0 1 1 1 0 4 E 0 63500 0 1 0 0 1 1 1 1 4 F 0 64000 0 1 0 1 0 0 0 0 5 0 0 64500 0 1 0 1 0 0 0 1 5 1 0 65000 0 1 0 1 0 0 1 0 5 2 0 65500 0 1 0 1 0 0 1 1 5 3 0 66000 0 1 0 1 0 1 0 0 5 4 0 66500 0 1 0 1 0 1 0 1 5 5 0 67000 0 1 0 1 0 1 1 0 5 6 0 67500 0 1 0 1 0 1 1 1 5 7 0 68000 0 1 0 1 1 0 0 0 5 8 0 68500 0 1 0 1 1 0 0 1 5 9 0 69000 0 1 0 1 1 0 1 0 5 0 69500 0 1 0 1 1 0 1 1 5 B 0 70000 0 1 0 1 1 1 0 0 5 0 70500 0 1 0 1 1 1 0 1 5 D 0 71000 0 1 0 1 1 1 1 0 5 E 0 71500 0 1 0 1 1 1 1 1 5 F 0 72000 0 1 1 0 0 0 0 0 6 0 0 72500 0 1 1 0 0 0 0 1 6 1 0 73000 0 1 1 0 0 0 1 0 6 2 0 73500 0 1 1 0 0 0 1 1 6 3 0 74000 0 1 1 0 0 i 0 0 6 4 0 74500 0 1 1 0 0 1 0 1 6 5 0 75000 0 1 0 0 1 1 0 6 6 0 75500 0 1 1 0 0 1 1 1 6 7 0 76000 0 1 1 0 1 0 0 0 6 8 0 76500 0 1 1 0 1 0 0 1 6 9 0 77000 0 1 1 0 1 0 1 0 6 0 77500 0 1 1 0 1 0 1 1 6 B 0 78000 0 1 1 0 1 1 0 0 6 C 0 78500 0 1 1 0 1 1 0 1 6 D 0 79000 0 1 1 0 1 1 1 0 6 E 0 79500 0 1 1 0 1 1 1 1 6 F 0 80000 0 1 1 1 0 0 0 0 7 0 0 80500 221 m e n Electrical Specifications Table 21 6 IMVP7 0 Voltage Identification Reference Sheet 4 of 7 VID7 VID6 VID5 VID2 ES BE V 0 1 1 1 0 0 0 1 7 1 0 81000 0 1 1 1 0 0 1 0 7 2 0 81500 0 1 1 1 0 0 1 1 7 3
129. 18 11 Send Data 1 SMB Mem HD1 register 19 Acknowledge from slave 20 Repeated Start 27 21 Slave Address 7 bits 28 Read 29 Acknowledge from slave 37 30 Data byte 1 from slave 8 bits 38 Acknowledge 46 39 Data byte 2 from slave 8 bits 47 Acknowledge Data bytes from slave Acknowledge Data byte from slave 8 bits Acknowledge Stop The SoC will continue reading data from the peripheral until the NAK is received Datasheet Volume 1 of 3 147 Platform Controller Unit PCU Overview 16 6 2 2 16 6 2 3 16 6 2 3 1 16 6 2 3 2 16 6 2 4 148 Bus Arbitration Several masters may attempt to get on the bus at the same time by driving the SMB DATA line low to signal a start condition The SoC continuously monitors the PCU SMB DATA line When the SoC is attempting to drive the bus to a 1 by letting go of the PCU SMB DATA line and it samples SMB DATA low then some other master is driving the bus and the SoC will stop transferring data If the SoC sees that it has lost arbitration the condition is called a collision The SoC will set 5 Mem HSTS BERR if enabled generate an interrupt or SMI The processor is responsible for restarting the transaction The SoC as a SMBus master drives the clock When the SoC is sending address or command or data bytes on writes it drives data relative to the clock it is also driving It will not start toggling the clock u
130. 1P35 DDR3 2 2 DDR3 MO DRAMRST VDDQ V1P35 DDR3 Weak 0 0 DDR3 MO ODT 1 0 VDDQ V1P35 DDR3 2 2 DDR3 MO DQ 63 0 I O VDDQ V1P35 DDR3 2 2 DDR3 DM 7 0 O VDDQ V1P35 DDR3 2 2 DDR3 DQSP 7 0 I O VDDQ V1P35 DDR3 2 2 DDR3 DQSN 7 0 I O VDDQ V1P35 DDR3 2 2 DDR3 MO OCAVREF I 0 5 VDDQ DDR3 2 2 DDR3 MO ODQVREF I 0 5 VDDQ DDR3 2 2 DDR3 MO RCOMP I VDDQ V1P35 DDR3 2 2 DDR3 MA 15 0 VDDQ V1P35 DDR3 2 2 Datasheet Volume 1 of 3 29 intel Physical Interfaces Table 2 4 DDR3L System Memory Signals Sheet 2 of 2 Default Buffer State Signal bir ior PrragedAssert DDR3 CK 1 0 P VDDQ V1P35 DDR3 2 2 DDR3 Mi CK 1 0 N VDDQ V1P35 DDR3 7 7 DDR3 CKE 1 0 VDDQ V1P35 DDR3 Weak 0 0 DDR3 Mi CS 1 0 N VDDQ V1P35 DDR3 7 7 DDR3 Mi CAS VDDQ V1P35 DDR3 2 2 DDR3 Mi RAS VDDQ V1P35 DDR3 2 2 DDR3 Mi WE N 0 VDDQ V1P35 DDR3 Z 2 DDR3 Mi BS 2 0 VDDQ V1P35 DDR3 2 2 DDR3 M1 DRAMRST N VDDQ V1P35 DDR3 Weak 0 0 DDR3 Mi ODT 1 0 VDDQ V1P35 DDR3 7 7 DDR3 Mi DQ 63 0 I O VDDQ V1P35 DDR3 2 2 DDR3 M1 DM 7 0 0 VDDQ V1P35 DDR3 Z Z DDR3_M1_DQS 7 0 _P VDDQ V1P35 DDR3 2 2 DDR3 Mi DQS 7 0 N I O VDDQ V1P35 DDR3 7 7 DDR3 Mi OCAVREF I 0 5 VDDQ DDR3 Z 2 DDR3 Mi ODQVREF I 0 5 VDDQ DDR3 2 DDR
131. 2 4 2 12 4 2 1 12 4 2 2 12 4 2 3 Software Implementation Considerations SoC Processor Core Cache Coherence Traffic generated by the LPE core is considered non cacheable and non coherent with respect to the SoC Processor Core cache DMA traffic is considered cacheable and checked for coherency with the SoC Processor Core cache Implications of this implementation are as follows e All code and tables for the LPE core need to be explicitly flushed from the SoC Processor Core cache if they are ever accessed e If the LPE core directly accesses data buffers in system DDR the driver must explicitly flush the buffer from the SoC Processor Core cache If DMA accesses data buffers from system DRAM the driver need not flush the data buffer from the SoC Processor Core cache Interrupts LPE Peripheral Interrupts Each of the LPE peripherals generates its own interrupts SSPO SSP1 and SSP2 have one interrupt each Each of the DMA channels have individual interrupt lines These interrupts are connected to the LPE core through the PISR register The same interrupts are routed to IOAPIC through the ISRX register The LPE core and SoC Processor Core have individual masks to enable these interrupts Interrupts Between SoC Processor Core and the LPE The interrupts between the SoC Processor Core and the LPE are handled through the inter processor communication registers Whenever the SoC Processor Core writes to the IPCX communication
132. 3 RsSvDInput Input 20kPD Input 20 4 v40 CAMERASBii 1 ViP8A Input 20kPD Input 2okPD 5 44 CAMERASBO2 1 CAMERASBO2 ViP8A Input 20kPD Input 20 6 AC53 CAMERASBO3 1 CAMERASBO3 ViP8A Input 20kPD Input 20 7 51 GP_CAMERASBO4 1 GP 4 ViP8A Input 20kPD Input 20k PD 8 52 CAMERASBOS 1 CAMERASBOS ViP8A Input 20kPD Input 2okPD 9 51 6 1 GP CAMERASBO6 ViP8A Input 20kPD Input 20k PD 10 40 GP_CAMERASBO7 1 CAMERASBO7 ViP8A Input 20kPD Input 2okPD 11 1 8 ViP8A Input 20kPD Input 2okPD 12 42 CAMERASBO 1 9 ViP8A Input 20kPD Input 2okPD 13 550 1 HPD Input 20kPD Input 20 HV_DDIO_DDC_SCL 1 HV_DDIO_DDC_SCL Input 20k PU Input 20k PU scuro HV 0010 SDA 1 HV 0010 SDA Input 20k PU Input 20k PU pbi 2 DANIO Datasheet Volume 1 of 3 Physical Interfaces Table 2 27 GPIO Multiplexing and Modes Sheet 2 of 6 Count 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
133. 3 DDR3 MO DQ 63 E46 VSS J28 SATA BH28 DDR3 MO 001621 E51 VSS N28 SATA RXPO BJ29 DDR3 MO DQ 61 F19 VSS K28 SATA RXN1 BG28 DDR3 MO DQ 60 F24 VSS M28 SATA RXNO AR53 DDR3 00161 F27 VSS N30 SATA RCOMP P BG32 DQ 59 F32 VSS M30 SATA_RCOMP_N BH34 DDR3 MO DQ 58 F35 VSS AH3 SATA_LED_N BG29 DDR3 MO DQ 57 F5 VSS AF3 SATA GP3 BJ33 DDR3 DQ 56 SATA DEVSLP1 G12 vss AGi SATA_GP2 BD28 001551 SATA DEVSLPO Gi4 55 1 BF30 DDR3 DQ 54 G22 vss AH2 SATA_GPO DDR3 MO DQ 53 G26 55 216 TEST BD34 DDR3 DQ 52 628 VSS M44 RSVD DDR3 DQ 51 G30 vss 44 RSVD BA32 DDR3 MO DQ 50 Hi9 VSS K48 RSVD AK52 DDR3 MO DQ 5 H27 VSS K47 RSVD BC34 3 MO DQ 49 H35 VSS F18 RSMRST N BF34 DDR3 MO DQ 48 H8 VSS H7 RSVD AV32 DDR3_MO_DQ 47 118 VSS H5 RSVD AV34 DDR3 MO DQ 46 119 VSS AD50 BD36 DDR3 MO DQ 45 122 VSS P18 PMU_WAKE_LAN_N BF36 DDR3 MO DQ 44 127 VSS N16 PMU WAKE N AU32 DDR3 MO DQ 43 J30 VSS C15 PMU SUSCLK AU34 DDR3 MO DQ 42 135 VSS C12 PMU SLP S4 N BA36 DDR3 MO DQ 41 138 VSS B14 PMU SLP S3 BC36 DDR3 DQ 40 142 VSS A13 PMU SLP SOix N AL53 DDR3 MO DQ 4 153 VSS 12 PMU SLP LAN BH38 DDR3 MO DQ 39 K12 VSS AF2 PMU RESETBUTTON N BH36 DDR3 MO DQ 38 K14 VSS M16 PMU PWRBTN N BJ41 DDR3 MO DQ 37 K16 VSS F14 PMU PLTR
134. 3 Mi RCOMP I VDDQ V1P35 DDR3 2 2 DDR3_DRAM_PWROK I VDDQ V1P35 DDR3 Input Input DDR3_VCCA_PWROK I VDDQ V1P35 DDR3 Input Input 2 2 2 USB 2 0 Controller Interface Signals Table 2 5 USB 2 0 Interface Signals Default Buffer State Signal Name Dir Pwrgood Assert Resetout ower State De assert State USB DN 4 0 USB2 PHY P 1 1V P 1 1V USB DP 4 0 USB2 PHY P 1 1V P 1 1V USB RCOMP USB2 PHY Output Output USB OC 1 0 I O V1P8A GPIOMV Input Input MS 20K PU 20K PU Note 1 Depends on USB 2 0 Mode 30 Datasheet Volume 1 of 3 Physical Interfaces Table 2 6 2 2 3 Table 2 7 2 2 4 Table 2 8 USB 2 0 HSIC Interface Signals Default Buffer State intel Signal Name Dir Platform Type Pwrgood Assert Resetout Power State De assert State USB HSIC 0 1 DATA I O V1P24A HSIC Buffer Weak 0 Weak 0 USB HSIC 0 1 STROBE I O 1 24 HSIC Buffer Weak 1 Weak 1 USB HSIC RCOMP 1 0 1 24 HSIC Buffer 2 2 Notes 1 gt HSIC should only be used with USB Hubs HSIC is not supported for individual USB devices The HSIC should be reset after SoC 2 1x HSIC port should be used for external hub USB 3 0 Interface Signals USB 3 0 Interface Signals Default Buffer State Signal Name Dir und Type Pwrgood Assert Resetout ower State De assert State USB3 TXN 3 0 1 US
135. 4 SMIZ SCI Generation Upon any enabled SMI event taking place while the SMI EN EOS bit is set the SoC will clear the EOS bit and assert SMI to the Processor core which will cause it to enter SMM space SMI assertion is performed using a Virtual Legacy Wire VLW message Prior system generations those based upon legacy processors used an actual SMI pin Once the SMI message has been delivered the SoC takes no action on behalf of active SMI events until Host software sets the End of SMI EOS bit At that point if any SMI events are still active the SoC will send another SMI message The SCI is a level mode interrupt that is typically handled by an ACPI aware operating system In non APIC systems which is the default the SCI IRQ is routed to one of the 8259 interrupts IRQ 9 10 or 11 The 8259 interrupt controller must be programmed to level mode for that interrupt In systems using the APIC the SCI can be routed to interrupts IRQs 11 9 or IRQs 23 20 The interrupt polarity changes depending on whether it is on an interrupt shareable with a PIRQ or not The interrupt remains asserted until all SCI sources are removed Table 16 6 shows which events can cause an SMI and SCI Note Some events can be programmed to cause either an SMI or SCI The usage of the event for SCI instead of SMI is typically associated with an ACPI based system Each SMI or SCI source has a corresponding enable and status bit Table 16 6 Causes of SMI and SCI Sh
136. 49 m n te Processor Core 3 2 2 Intel VT x Features Extended Page Tables EPT is hardware assisted page table physical memory virtualization Support guest VM execution in unpaged protected mode or in real address mode It eliminates VM exits from guest OS to the VMM for shadow page table maintenance Virtual Processor IDs VPID A Virtual Processor ID is used to tag processor core hardware structures such as TLBs to allow a logic processor to cache information such as TLBs for multiple linear address spaces This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest OS VM after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service QoS guarantees flexibility in guest VM scheduling and building Quality of Service QoS schemes Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest OS from internal malicious software based attack by preventing relocation of key system data structures like IDT Interrupt Descriptor Table GDT global descriptor table LDT Local Descriptor Table and TSS Task Segment Selector A VMM using this feature can intercept by a VM exit attempts to relocate these
137. 59 16 8 3 2 LPC Power 1 160 16 8 3 3 SERIRQ Disable ieee a 160 16 8 4 Huge ctem 160 PCU iLB Real Time Clock RE DER 160 16 9 1 Signal Descriptions enter ra gn en ink et ob See ax DECR X 160 16 9 2 FCACUIES EE EEEE E EE E ERE OE EEO 161 16 9 2 1 Update Cycles ere bee Exe ae AERE Y ERAN ERU 162 16 9 3 162 16 9 3 1 Lockable RAM 5 162 16 9 3 2 Clearing Battery Backed RTC RAM 162 16 9 3 3 Using a GPI to Clear 5 163 16 9 4 uec T 163 16 9 5 Mapped Registers 163 16 9 6 Indexed Registers er etate gehn ak thea tu landed sn sa EE CA RR RR RAT 164 PCUSIEB 8254 TIMERS eee eunti Ue Re Se d 164 16 10 1 Signal Descriptions 164 16 10 2 pU Qm 165 16 10 2 1Counter 0 System 165 16 10 2 2Counter 1 Refresh Request
138. 6 Causes of SMI and SCI Sheet 3 of 3 Interrupt Result SMI EN SMI EN Event Status Indication Enable Condition SMI 1 GBL SMI EN Ob 1 CNT S 1 5 1 CNT S 1 CNT S CI EN 1b CI EN Ob CI_EN 1b CI EN Ob USB Per Port UPRWC WE STS UPRWC Registers Write and WE SMI E 1b Enable bit is SMI STS and SYNC SMI None changed from Ob to rs 5 5 5 EN 1b USB_IS_SMI_EN 1b Notes 1 Most of the status bits except otherwise noted are set according to event occurrence regardless to the enable bit 2 GPIO status bits set only if enable criteria is true Refer to the processor Datasheet Volume 3 Section 35 2 17 and 35 4 4 for more details see Related Documents section 3 When power button override occurs the system will transition immediately to S5 The SCI will only occur after the next wake to SO if the residual status bit is not cleared prior to setting PM1 CNT SCI EN Refer to processor Datasheet Volume 3 Section 35 4 1 for more details see Related Documents section 4 1 STS EN GBL STS being set will cause an SCI even if the 1 CNT SCI EN bit is not set Software must take great care not to set the SMI ENBIOS RLS bit which causes PM1 STS EN GBL STS to be set if the SCI handler is not in place Refer to the processor Datasheet Volume 3 Section 35 4 1 for more details see Related Documents section 5 enable bits for thes
139. 6 4 2 2 Conditional Self Refresh isseire pasa nha na an 68 6 4 2 3 Dynamic Power Down Operation 68 6 4 2 4 DRAM Power Management 0 2 222222 68 7 System Memory Controller 69 7 1 DDR3L Interface Signals 69 7 2 System Memory Technology 2 4 4 4 nemen 70 8 Graphics Video and Display 22 1 71 8 1 SOC Graphics Display citer e nte satio ha eant caters RR TERR RARE REA D 71 8 1 1 Primary Display Planes B and 71 8 1 1 1 Video Sprite Planes A B C D and 71 8 1 1 2 C rsors 72 8 1 2 Display PiPC Siiicc PL 72 8 1 3 Display Physical ences hann 72 8 2 Digital Display Interfaces nnne 72 Datasheet Volume 1 of 3 8 2 1 High Definition Multi media Interface 73 8 2 1 1 5 nee 74 8 2 1 2 embedded Display
140. 75 Vref V VoL Output LOW voltage 0 25 VREF V Input HIGH voltage 0 65 Vref Vrer 0 3 V VIL Input LOW voltage 0 3 0 35 Vper I O Pad Drive Strength 40 60 Ohms Datasheet Volume 1 of 3 237 intel Table 21 25 USB HSIC DC Electrical Specification Sheet 2 of 2 Parameter Load Capacitance Electrical Specifications I O Input Impedance 21 6 10 USB 3 0 DC Specification Characteristic Trace Impedance Table 21 26 USB 3 0 DC Specification Symbol Parameter Min Typ Max Units Notes UI Unit Interval 199 94 200 06 ps 1 Differential peak peak Tx Vrx DiFF PP voltage swing 0 9 1 1 05 V VTX DIFF PP Low Power Differential 0 4 12 V 2 LOW peak peak Tx voltage swing VTX DE RATIO Tx De Emphasis 3 45 3 5 3 65 dB Rrx piFF DC DC differential impedance 88 92 Q The amount of voltage change allowed during 0 6 V 3 Receiver Detection CAC COUPLING AC Coupling Capacitor 75 200 nF 4 Maximum slew rate 10 ms s Notes mode 1 The specified UI is equivalent to a tolerance of 300 ppm for each device Period does not account for SSC induced variations 2 There is no de emphasis requirement in this mode De emphasis is implementation specific for this 3 Detect voltage transition should be an increase in voltage on the pin looking at the detect signal to avoid a high
141. 9 controllers The PIC uses the first internal INTA pulse to freeze the state of the interrupts for priority resolution On the second INTA pulse the master or slave sends the interrupt vector to the processor with the acknowledged interrupt code This code is based upon the ICW2 IVBA bits combined with the ICW2 IRL bits representing the interrupt within that controller Datasheet Volume 1 of 3 m Platform Controller Unit Overview n tel Note References to ICWx and OCWXx registers are relevant to both the master and slave 8259 controllers Table 16 34 Content of Interrupt Vector Byte Master Slave Interrupt Bits 7 3 Bits 2 0 IRQ7 15 111 IRQ6 14 110 IRQ5 13 101 IRQ4 12 100 ICW2 IVBA IRQ3 11 011 IRQ2 10 010 IRQ1 9 001 00 8 000 16 15 1 1 3 Hardware Software Interrupt Sequence 1 One or more of the Interrupt Request lines IRQ are raised high in edge mode or seen high in level mode setting the corresponding IRR bit 2 The PIC sends INTR active to the processor if an asserted interrupt is not masked 3 The processor acknowledges the INTR and responds with an interrupt acknowledge cycle Upon observing the special cycle the SoC converts it into the two cycles that the internal 8259 pair can respond to Each cycle appears as an interrupt acknowledge pulse on the internal INTA pin of the cascaded interrupt controllers Upon receiving the
142. A V1P8A V1P8A V1P8A V1P8A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Pwrgood Assert State 0 0 0 Input 20k PD 0 0 0 Input 20k PD Input 20k PU Input 20k PU 0 20k PD Z 20K PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PD 0 20k PU 1 20k PU Input 20k PU 1 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PD Input 20k PU Resetout De assert State 0 0 0 Input 20k PD 0 0 0 Input 20k PD Input 20k PU Input 20k PU 0 20k PD Z 20K PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU Z 20k PU 2 Output Output Output Output Input 20k PU Input 20k PU Input 20k PU Input 20k PU Input 20k PD I 3 put 20k PD Input 20k PD I 5 put 20k PD Input 20k PD Input 20k PU intel Optional Modes Direction Mode2 DDC SCL IO Mode3 UARTO TXD O Mode2 HV DDC SDA IO Mode3 UARTO RXD I Mode5 CO BPMO TX DFX IO Mode6 Ci BPMO TX DFX IO M
143. ACK Suspend Power Down Acknowledge Asserted by the SoC CMOS 1 8 when it does not require its Suspend well to be powered 16 2 2 Features 16 2 2 1 Sx G3 Sx Handling Power Failures Depending on when the power failure occurs and how the system is designed different transitions could occur due to a power failure The 1 bit provides the ability to program whether not the system should boot once power returns after a power loss event If the policy is to not boot the system remains in an S5 state unless previously in S4 There are only two possible events that will wake the system after a power failure PWRBTNZ PWRBTNZ is always enabled as wake event When RSMRST is low state the 1 STS EN PWRBTN STS bit is reset When the SoC exits after power returns RST goes high the PMU_PWRBTN signal is already high because the suspend plane goes high before RSM_RST goes high and the STS STS bit is Ob Alarm The PM1 STS EN RTC EN bit is in the well and is preserved after a power loss Like 1 575 EN PWRBTN STS the STS STS bit is cleared when RSM_RST goes low The SoC monitors both CORE PWROK and RSM RST to detect for power failures If CORE PWROK goes low the PMCON1 PWR FLR bit is set If RSM_RST goes low PMCON1 SUS PWR FLR is set Datasheet Volume 1 of 3 127
144. ATA 0 11 I O 1 SATA X Weak pull down SATA RXP 0 1 1 SATA X Weak pull down SATA TXN 0 1 1 SATA X 4 SATA TXP 0 1 1 SATA X 2 SATA 1 SATA X Output SATA RCOMP P IO 1 SATA X Output SMBus Signals Table 2 21 SMBus Signals and Clocks Default Buffer State Signal Name Dir Platform Type Pwrgood Assert Resetout Power State De assert State MF SMB ALERT N 1 0 V1P8A GPIOMV MS Input 20K PU Input 20K PU MF SMB CLK 10 GPIOMV MS Input 20K PU Input 20K PU MF SMB DATA 1 0 V1P8A GPIOMV MS Input 20K PU Input 20K PU 2 3 8 Intel High Definition Audio Intel HD Audio Signals Table 2 22 Intel High Definition Audio Intel HD Audio Signals and Clocks 38 Sheet 1 of 2 Default Buffer State Signal Name Dir Platform Type Pwrgood Assert Resetout 9 State De assert State MF HDA CLK yo GPIOMV MS 0 20K PD 0 20K PD or MF HDA DOCKEN N 10 GPIOMV MS 1 20 Input 20K PD HDA DOCKRST yo GPIOMV MS 0 20K PD 0 20K PD HDA RST Lo ieee GPIOMV MS Input 20K PD Input 20K PD Datasheet Volume 1 of 3 Physical Interfaces intel Table 2 22 Intel High Definition Audio Intel HD Audio Signals and Clocks 2 3 9
145. B3 X 2 USB3 TXP 3 0 1 USB3 X 2 USB3 RXN 3 0 I 1 USB3 X 2 USB3 RXP 3 0 I 1 USB3 X 2 USB3 RCOMP I O 1 USB3 X Output USB3 RCOMP P I O 1 USB3 X Output Integrated Clock Interface Signals Integrated Clock Interface Signals Default Buffer State Signal Name AE DIFF N 0 3 1 Analog 1 1 CLK DIFF P 0 3 1 Analog 0 0 ICLK OSCIN I 1 Crystal Input Crystal Input Crystal Oscillator OSCOUT 1 Crystal Output Crystal Output Crystal Oscillator ICLK ICOMP GND Analog Input Input RCOMP I O GND Analog Input Input Datasheet Volume 1 of 3 31 m e n e Physical Interfaces 2 2 5 Display Digital Display Interface DDI Signals Table 2 9 Digital Display Interface Signals Sheet 1 of 2 Default Buffer State Platform Pwrgood Assert Resetout Signal Name Dir Power Type State De assert State DDIO TXP 3 0 V1P35 MODPHY 7 Output DDIO TXN 3 0 V1P35 MODPHY 7 Output DDIO AUXP 1 0 V1P35 MODPHY 7 Output DDIO AUXN V1P35 MODPHY 7 Output DDIO RCOMP N 1 0 V1P35 MODPHY 7 Output DDIO RCOMP P 10 V1P35 MODPHY 7 Output DDIO DDC CLK mn multiplexed with V1P8A Input 20kPU Input 20k PU DDIi DDC
146. D Transmit Slave Address SMB TSA Data 0 Data 1 HD1 should not be changed or read until the interrupt status message SMB Mem HSTS INTR has been set indicating the completion of the command Any register values needed for computation purposes should be saved prior to issuing of a new command as the SMBus host controller updates all registers while completing the new command Command Protocols In all of the following commands the Host Status HSTS register is used to determine the progress of the command While the command is in operation the SMB Mem HSTS HBSY bit is set If the command completes successfully the SMB HSTS INTR bit will be set If the device does not respond with an acknowledge and the transaction times out the SMB HSTS DEVERR bit is set If software sets the SMB Mem bit while the command is running the transaction will stop and the SMB Mem HSTS FAILED bit will be set Datasheet Volume 1 of 3 143 n tel Platform Controller Unit PCU Overview Quick Command When programmed for a Quick Command the Transmit Slave Address Mem TSA register is sent The PEC byte is never appended to the Quick Protocol Software should force the SMB Config HCTL PECEN bit to Ob when performing the Quick Command Software must force the SMB Config HCFG I2C EN bit to Ob when running this command See section 5 5 1 of the System
147. DMA The data transfer from the HSUART to host memory is controlled by the DMA write channel To configure the channel in write mode channel direction in the channel control register needs to be programmed to 1 Software needs to program the descriptor start address register descriptor transfer size register and descriptor control register before starting the channel using the channel active bit in the channel control register Transmit DMA The data transfer from host memory to HSUART is controlled by DMA read channel To configure the channel in read mode channel direction in the channel control register needs to be programmed to 0 Software needs to program the descriptor start address register descriptor transfer size register and descriptor control register before starting the channel using the channel active bit in the channel control register Removing Trailing Bytes in DMA Mode When the number of entries in the Receive FIFO is less than its trigger level and no additional data is received the remaining bytes are called Trailing bytes These are DMAed out by the DMA as it has visibility into the FIFO Occupancy register FIFO Polled Mode Operation With the FIFOs enabled IIR FCR IIDO FIFOE bit set to 1 clearing IER DLH 7 IER DLH 4 0 puts the serial port in the FIFO Polled Operation mode Because the receiver and the transmitter are controlled separately either one or both can be in Polled Operation mode In thi
148. G_S4 DDR3 M1 AM13 VSS BG3 DDR VDDQ G S4 DDR3 M1 AM16 VSS BG51 DDR VDDQ G S4 DDR3 M1 MA AM24 VSS DDR VDDQ 54 DDR3 M1 AM27 VSS BH49 DDR VDDQ G S4 DDR3 M1 MA AM30 VSS BH5 DDR_VDDQ_G_S4 DDR3 M1 AM35 VSS BH50 DDR VDDQ G S4 DDR3 M1 MA AM38 VSS AF29 CORE VCC1 DDR3 M1 MA AM4 VSS AF30 CORE VCC1 DDR3 M1 MA 42 VSS AG27 CORE VCC1 DDR3 M1 MA 50 VSS AG29 CORE VCC1 DDR3 M1 MA 1 VSS AG30 CORE VCC1 DDR3 M1 Datasheet Volume 1 of 3 201 m e n tel Ball Map Ball Out and SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 4 of 11 Pin Pin Name Pin Pin Name Pin Pin Name AN11 VSS AJ27 CORE VCC1 BJ9 DDR3 M1 MA 10 AN12 VSS AJ29 CORE VCC1 BC12 DDR3 MA 1 AN14 VSS AJ30 CORE VCC1 BB7 DDR3 M1 MA O0 AN16 VSS AF36 CORE VCC1 BA12 DDR3 M1 DRAMRST N AN21 VSS AG33 CORE BG23 DDR3 M1 DQSB 7 AN24 VSS AG35 CORE VCC1 BC22 DDR3 DQSB 6 AN25 VSS AG36 CORE VCC1 AT20 DDR3 DQSB 5 AN29 VSS AG38 CORE BG15 DDR3 M1 DQSB 4 AN3 VSS AJ33 CORE VCC1 BA3 DDR3 M1 DQSB 3 AN30 VSS AJ36 CORE VCC1 AT13 DDR3 1 DQSB 2 AN33 VSS AJ38 CORE VCC1 AV6 DDR3_M1_DQSB 1 AN38 VSS AC36 CORE_VSFR_G3 AM3 DDR3_M1_DQSB 0 AN40 VSS AD35 CORE_VSFR_G3 BH22 DDR3_M1_DQS 7 AN42 VSS
149. HSIC 1 STROBE DDR3 M1 DQ BA27 VSS M38 USB HSIC 1 DATA DDR3 M1 DQ Datasheet Volume 1 of 3 203 m e n tel Ball Map Ball Out and SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 6 of 11 Pin Pin Name Pin Pin Name Pin Pin Name BA30 VSS M36 USB HSIC 0 STROBE 16 DDR3 1 DQ 18 5 55 N36 USB HSIC 0 DATA 12 DDR3 1 DQ 17 BB19 VSS 40 USB 4 14 DDR3 M1 DQ 16 BB27 VSS C45 USB DP3 AV9 DDR3 M1 DQ 15 BB35 VSS C41 USB DP2 AYA DDR3 M1 DQ 14 BB4 VSS C43 USB DP1 DDR3 M1 DQ 13 BB50 VSS C42 USB DPO DDR3 DQ 12 BC10 VSS C40 USB DN4 AV4 DDR3 DQ 11 BC14 VSS A45 USB DN3 AY6 DDR3 M1 DQ 10 BC16 VSS A41 USB DN2 AL3 DDR3 M1 DQ 1 BC26 VSS B44 USB DN1 DDR3 M1 DQ 0 BC28 VSS B42 USB DNO BH24 DDR3 1 DM 7 BC38 VSS C38 RSVD BD22 DDR3 DM 6 40 VSS B38 RSVD 18 DDR3 DM 5 44 VSS G36 RSVD BG13 DDR3 1 DM 4 BD1 VSS 136 RSVD DDR3 DM 3 BD19 VSS Y6 UART2_TXD AP10 DDR3_M1_DM 2 BD27 VSS Y7 UART2_RXD 6 DDR3_M1_DM 1 BD35 VSS V10 UART2 RTS N AP2 DDR3 M1 DM 0 BD53 VSS V9 UART2 CTS N AU16 DDR3 M1 CSB 1 BE19 VSS AD10 UART1_TXD AY16 DDR3_M1_CSB 0 BE35 VSS AD12 UART1_RXD AY12 DDR3_M1_CKE 1 12 VSS AD14 UART1_RTS_N
150. I MSIs are automatically passed upstream by the root port just as other memory writes would be INTx messages are delivered to the Legacy Block interrupt router controller by the root port Events and interrupts that are handled by the root port are shown with the supported interrupts they can deliver to the interrupt decoder router Supported Interrupts Generated From Events Packets Sheet 1 of 2 Packet Event Type MSI SERR SCI SMI GPE Packet X X PME Packet X X Power Management PM Event X X Hot Plug HP Event X X X ERR CORR Packet X Datasheet Volume 1 of 3 m PCI Express 2 0 n tel Table 18 1 Note Table 18 2 Note 18 2 2 1 Note 18 2 2 2 18 2 3 Supported Interrupts Generated From Events Packets Sheet 2 of 2 Packet Event Type MSI SERR SCI SMI GPE NONFATAL Packet X ERR FATAL Packet X Internal Error Event X VDM Packet X Table 18 1 lists the supported interrupts and events generated based on Packets received or events generated in the root port Configuration needed by software to enable the different interrupts as applicable When INTx interrupts are received by an end point they are mapped to the following interrupts and sent to the interrupt decoder router in the iLB Interrupt Generated for INT A D Interrupts INTA INTB INTC INTD Root Port 1 INTB
151. I Features Compliant to CSI 2 MIPI specification for Camera Serial Interface Version 1 00 Supports standard D PHY receiver compliant to the MIPI Specification Supports PHY data programmability up to four lanes Supports PHY data time out programming Has controls to start and re start the CSI 2 data transmission for synchronization failures and to support recovery The ISP may not support all the data formats that the CSI 2 receiver can handle Refer to Table 9 3 for formats supported by the ISP Supports all generic short packet data types Single Image Signal Processor interface for pixel transfers to support multiple image streams for all virtual channel numbers Datasheet Volume 1 of 3 m MIPI CSI Camera Serial Interface and ISP n tel D PHY Features Supports synchronous transfer in high speed mode with a bit rate of 80 1500Mb s Supports asynchronous transfer in low power mode with a bit rate of 10Mb s Differential signalling for HS data Spaced one hot encoding for Low Power LP data Data lanes support transfer of data in high speed as well as low power modes Supports ultra low power mode escape mode and high speed mode Hasa clock divider unit to generate clock for parallel data reception and transmission from and to the PPI unit Activates and disconnects high speed terminators for reception and control mode Activates and disconnects low power terminators for reception and transmission 88 D
152. Image capture 5MP frame rate 30 fps 2 D video capture Input formats Up to 1080p30 RAW 8 10 12 14 RGB444 565 888 YUV420 422 JPEG Output formats YUV422 YUV420 RAW Special Features Image and video stabilization Low light noise reduction Burst mode capture Memory to memory processing 3A Auto Exposure AE Auto White Balance AWB and Auto Focus AF High Dynamic Range HDR Multi focus Zero shutter lag 9 1 2 Simultaneous Acquisition SoC will support on the fly processing for only one image at a time While this image is being processed on the fly images from the other two cameras are saved to DRAM for later processing 82 Datasheet Volume 1 of 3 m MIPI CSI Camera Serial Interface and ISP n tel 9 1 3 9 1 4 9 1 5 9 1 6 9 1 7 9 1 8 9 1 9 Primary Camera Still Image Resolution Maximum still image resolution for the primary camera in post processing mode is limited by the resolution of the sensors Currently 5 megapixel sensors are supported Burst Mode Support The SoC supports capturing multiple images back to back at maximum sensor resolution At least 5 images must be captured in burst mode The maximum number of images that can be so captured is limited only by available system memory These images need not be processed on the fly Continuous Mode Capture SoC supports capturing images and saving them to DRAM in a ring of frame bu
153. MU RESETBUTTON N PMU SLP LAN N PMU SLP SOIX N PMU SLP S3 N PMU SLP S4 N PMU SUSCLK WAKE WAKE LAN SUS STAT N SUSPWRDNACK PWMO PWM1 SATA GPO SATA 1 DEVSLPO DEVSLP1 LEDN SDMMCS3 1 8 SDMMCS3 CD GPIO SoC Power Rail V3P3A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO Multiplexing and Modes Sheet 5 of 6 Pwrgood Assert State Input 20k PU Input 20k PU Input 20k PU Input 20k PU 1 20k PU Input 20k PD Input 20k PD Input 20k PD 0 20k PD Input 20k PU Input 20k PU Input 20k PU Input 20k PU 0 20k PD 0 20k PD 0 20k PD 0 20k PD 0 20k PD 0 20k PD Input 20k PD Input 20k PU 0 20k PU Input 20k PU Input 20k PU 0 20k PU 0 20k PU 0 20k PU 0 20k PU 0 20k PD Input 20k PU Input 20k PU 0 20k PU 0 20k PD 0 20k PD 0 20k PD Input 20k PD Input 20k PD 0 20k PD 0 20k PD
154. N series Intel Pentium Processors and Intel Celeron Processors Datasheet Volume 1 of 3 April 2015 Document Number 332092 001 You may not use or facilitate the use of this document connection with infringement or other legal analysis concerning Intel products described herein You agree to grant Intel a non exclusive royalty free license to any patent claim thereafter drafted which includes subject matter disclosed herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Intel technologies features and benefits depend on system configuration and may require enabled hardware software or service activation Learn more at Intel com or from the OEM or retailer No computer system can be absolutely secure Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Intel disclaims all express and implied warranties including without limitation the implied warranties of merchantability fitness for a particular purpose and non infringement as well as any warranty arising from course of performance course of dealing or usage in trade Intel technologies features and benefits depend on system conf
155. NT 114 0 ujaj d INT10 11 INT12 INT14 INT15 INT16 INT17 18 INT19 INT113 INT114 es ee EIEIEIEIEIE 0 MSIs generated by I O sent as 32 bit memory writes to the local APIC The address and data of the write transaction are used as shown in the following figure Figure 16 7 MSI Address and Data Destination Mode Redirection Hint Extended Dest ID Destination ID FEEh MSI Address MSI Data 0000h Trigger Mode Delivery Status 1b Destination Mode Delivery Mode Vector 00b Datasheet Volume 1 of 3 177 m Platform Controller Unit PCU Overview 16 14 2 16 14 3 Note Note 178 Destination ID DID and Extended Destination ID EDID are used to target a specific processor core s local APIC Use The I O APIC contains indirectly accessed I O APIC registers and normal memory mapped registers There are three memory mapped registers Index Register IDX Window Register WDW End Of Interrupt Register EOI The Index register selects an indirect I O APIC register ID VS RTE n to appear in the Window register The Window register is used to read or write the indirect register selected by the Index register The EOI register is written to by the Local APIC in the processor The I O APIC compares the lower eight bits written to the EOI re
156. O depending on the platform When used as an interlock switch status indication this signal should be driven to 0 to indicate that the switch is 1 0 closed and to 1 to indicate that the switch is open SATA GP 3 0 V1P8S Note SATA GP 0 is multiplexed with ISH_GPIO_12 SATA GP 1 is multiplexed with 5 50 SATA GP 2 is multiplexed with SATA_DEVSLP 0 SATA_GP 3 is multiplexed with SATA_DEVSLP 1 Serial ATA LED This is an open collector output pin driven during SATA SATA LED command activity It is to be connected external circuitry that can 85 provide the current to drive a platform LED When active the LED is When tristated the LED is off SATA TXP 1 0 Serial ATA Port 1 0 These outbound high speed differential SATA TXN 1 0 1 signals to Port 1 0 SATA RXP 1 0 I Serial ATA Port 1 and 0 These are inbound high speed differential SATA RXN 1 0 1 signals to Port 1 0 SATA RCOMP P and Serial ATA Impedance Compensation These pins used to connect SATA RCOMP N 85 the external resistors used for RCOMP Datasheet Volume 1 of 3 187 tel 9 Serial SATA 17 3 Features 17 3 1 Supported Features Table 17 2 SATA AHCI Feature Matrix Feature AHCI Enabled Native Command Queuing NCQ Supported Auto Activate for DMA Supported Hot plug Support Supported Asynchronous Sig
157. O V1P8A 234 Datasheet Volume 1 of 3 Electrical Specifications 21 6 7 Table 21 23 DDRS3L Signal Group DC Specifications DDR3L Memory Controller DC Specification Parameter Min Typ Max Units Input Low Voltage DDR VREF 200mV Input High Voltage DDR VREF 200mV Output Low Voltage DDR VDDQG S4 2 RON RON RVTT_TERM Output High Voltage DDR VDDQG S4 DDR VDDQG 54 2 RON RON RVTT_TERM Input Leakage Current HA For all DDR Signals DDR3L Clock Buffer strength 26 40 DQ DQS DQS DDR3L I O Pin Capacitance 3 0 pF Notes 21 6 8 USB 2 0 Host DC Specification Table 21 24 USB 2 0 Host DC Specification Sheet 1 of 3 1 is defined as the maximum voltage level at the receiving agent that will be received as a logical low value DDR is normally DDR 54 2 2 is defined as the minimum voltage level at the receiving agent that will be received as a logical high value DDR is normally DDR 54 2 3 and Voy may experience excursions above DDR VDDQG S4 However input signal drivers must comply with the signal quality specifications 4 RON is DDR driver resistance whereas RTT TERM is DDR ODT resistance which is controlled by DDR 5 DDR3L 1333 1600 CLK buffer Ron is 26 ohm and SR target is 4V ns DQ DQS buffer Ron is 30 ohms and SR tar
158. On On Off Off V1P8A 1 8 On On On Off V3P3A Off VSDIO 1 8 3 3 On Off Off Off 3 3 On On On On VCC HDA 1 5 1 8 On On On Off Table 6 3 ACPI PM State Transition Rules Present State Transition Trigger Next State IA Code MWAIT or LVL Rd 0 50 1 CNT SLP EN bit set G1 Sx or G2 S5 state specified by G0 S0 CO PM1_CNT SLP_TYP Power Button Override G2 S5 Mechanical Off Power Failure G3 Cx break events which include Processor G0 S0 CO snoop MSI Legacy Interrupt AONT timer 60 50 Power Button Override G2 S5 Resume Well Power Failure G3 Any Enabled Wake Event G0 S0 CO G1 S4 Power button Override G2 S5 Resume Well Power Failure G3 Any Enabled Wake Event G0 S0 CO G2 S5 Resume Well Power Failure G3 Power Returns Option to to SO CO reboot G2 S5 stay off until power button pressed or other enabled G3 wake event or G1 S4 if system state was S4 prior to the power failure Some wake events are preserved through a power failure 60 Datasheet Volume 1 of 3 intel 6 2 2 Integrated Memory Controller States Table 6 4 Memory States States Description Power up CKE asserted Active mode Precharge power down CKE de asserted not self refresh with all banks closed Active power down CKE de asserted not self refresh with at least one bank active Self Refresh CKE de asserted using device self refresh 6 3 Processor Core Power Management
159. P N 0 4 USB 2 0 PHY Resistor Compensation An external resistor must connected USE RCOMP USB 2 0 PHY USB High Speed Observation 05 2 0 On The Go ID The signal is to identify if a Host or Device is USB OTG ID USB 2 0 PHY Connected to its port Note This is applicable only for Chrome OS based systems I Over Current detection This pin is used to indicate an over current USB OC 1 0 N USB 2 0 PHY Condition to the controller Table 11 2 HSIC Signals Signal Name Description ype HSIC Data USB HSIC 0 1 DATA HSIC Buffer HSIC Strobe USB HSIC 0 1 STROBE eR I Resistor Compensation RCOMP for HSIC buffer USB HSIC RCOMP Note See Chapter 2 Physical Interfaces for additional details Figure 11 1 xHCI Port Mapping USB 1 2 USB 1 2 3 USB 1 2 3 USB 1 2 3 USB 1 2 3 Host Host Host Host USB HSIC Host Device Connector Connector Connector Connector Host Connector Port 4 Port 3 Port 2 Port 1 Connector Port 0 94 Datasheet Volume 1 of 3 m e USB Controller Interfaces tel 11 3 USB 3 0 xHCI Extensible Host Controller Interface The xHCI compliant host controller can control up to 4 four USB 3 0 and 1 one USB 2 0 host It supports devices conforming to USB 1 x to 3 0 at bit rates up to 5Gbps USB 3 0 ports support xHCI debug
160. PIRQx line to send an active high level to the PIC When a PCI interrupt is routed onto the PIC the selected IRQ can no longer be used by an active high device through SERIRQ However active low interrupts can share their interrupt with PCI interrupts PCU iLB I O APIC The I O Advanced Programmable Interrupt Controller APIC is used to support line interrupts more flexibly than the 8259 PIC Line interrupts are routed to it from multiple sources including legacy devices by means of the interrupt decoder and serial Datasheet Volume 1 of 3 175 n Platform Controller Unit PCU Overview IRQs or they are routed to it from the interrupt router in the These line based interrupts are then used to generate interrupt messages targeting the local APIC in the processor Figure 16 5 Platform Control Unit APIC Platform Control Unit 16 14 1 Features e 115 interrupt lines 0 114 Edge or level trigger mode per interrupt Active low or high polarity per interrupt Works with local APIC in processor by means of MSIs e MSIs can target specific processor core Established APIC programming model 176 Datasheet Volume 1 of 3 Platform Controller Unit PCU Overview Figure 16 6 Detailed Block Diagram To From System Bus MSI s I O APIC FECO IDX MSI Machine FECO 0010h WDW FECO 0040h INT O RTE O ID 5 INT 114 RTE 114 I
161. PME BO BATLOW pin goes GPEOa STS GPEO EN low BATLOW 575 BATLOW_EN 1b SEE a None Software Generated GPEOa STS GPEO EN GPE SWGPE STS SWGPE_EN 1b SCI SCI None DOSCI message 5 5 None enabled by from G unit GUNIT STS G Unit SCI None SCI None ASSERT_SMI SMI_STS None enabled by message from SPI SPI SMI STS SPI controller None ASSERT IS SMI SMI STS SMI EN SMI None message from USB USB IS STS USB IS SMI EN 1b ASSERT_SMI SMI_STS USB_STS SMI_EN SMI None message from USB USB_SMI_EN 1b ASSERT_SMI SMI_STS None enabled by message from 185 ILB SMI STS iLB SMI None Periodic timer SMI_STS SMI SMI None expires PERIODIC STS PERIODIC EN 1b WDT first expiration SMI STS TCO STS EN 1b SMI None 64 ms timer expires SMI_STS SMI_EN SWSMI TMR STS SWSMI_TMR_EN 1b None PM1_CNT SLP_EN SMI_STS SMI_EN bit written to 1b SMI_ON_SLP_EN_ST SMI_ON_SLP_EN Sync SMI None 5 1b PM1_CNT GBL_RLS SMI_STS BIOS_STS SMI_EN Sync SMI None written to 1b BIOS_EN 1b y DOSMI message SMI STS None enabled by from G unit GUNIT 5 STS G Unit 5 ASSERT IS SMI SMI STS None enabled by 7 message from iLB SMI STS iLB Sync SMI None 10 ALT SMI GPIO_ROUT n 01b CORE_GPIO_SMI_ST and S n ALT SMI or CORE GPIO SMI E ALT GPIO SMI N n 1b SMI None 132 Datasheet Volume 1 of 3 Platform Controller Unit Overview Table 16
162. Polarity errore ttn tenen nnne aida RR cadet sh Ra 116 15 2Data Transfer on the 12 BUS 118 15 35 and STOP Conditions irren tet recta dena ru De naa DEVE CR ede 119 15 AUART Data Transfer zit yn ner tex e xe ding eae ax wapa ke FRAN mal Farnese E NIRE 120 16 1Platform Control Unit System Management 2 1111111 142 16 2LPC Interface sui eoo Ran none S Ea ARE panes dens eda da RE 155 16 3Platform Control Unit High Precision Event Timer 168 16 A4GPIO Stack Block Diagram ri oxi RR 171 16 5Platform Control Unit APIC 176 16 6Detailed Block 177 16 7MSI Address and Data UR WR UBER E RR PE S 177 16 8Platform Control Unit 8259 Programmable Interrupt 179 18 1PCI Express 2 0 Lane 0 Signal 1 189 18 2Root Port Configuration Options 190 19 1 Map Top Left View Columns 53 29
163. Port 75 8 2 1 3 DisplayPort Auxiliary 1 3 21211 75 8 2 1 4 Hot Plug Detect APD cR er nra n candace 75 8 2 1 5 Integrated Audio Over HDMI and DisplayPort 75 8 2 1 6 High Bandwidth Digital Content Protection 75 8 3 3 D Graphics and 75 8 3 1 Pm 76 8 3 2 Engine Execution UNICS nas e 76 8 3 3 3D PipeliN E 76 8 3 3 1 Vertex Fetch VE 76 8 3 3 2 Vertex Shader VS Stage 77 8 3 3 3 Geometry Shader GS 77 pomo Mare Ecc 77 8 3 3 5 Strips and Fans SF 77 8 3 3 6 Windower IZ WIZ meme ene 77 8 4 VED Video Encode Decode oorr enata s Ra 77 8 4 1 eee LETT 78 9 MIPI CSI Camera Serial Interface and 81 9 1 Signal Description S ssns e Se au ESAE 81 9 1 1 Imaging Capabilities
164. R aS AS MU DIM KM AE URN UN UNDER TIME 152 luogo 153 16 20EPG Signals 154 16 21SERIRQ Stop Frame Width to Operation Mode 158 16 22SERIRQ Interrupt Mapping a e ER RARERRRRRRRR ER XR 158 16 23RTC Signals GE RES a 160 16 24Register Bits Reset by RST Assertion 163 16 251 0 Registers Alias Locations iere irte MARRE MER 164 16 26RTC Indexed ena tel una x DRY DE RA ER Ed ada ae e va 164 16 278254 SIGNALS gp 165 16 28Counter Operating Modes ceti etie tere da 166 162298254 Qeon sien Ares 169 16 30Generic Community Address 1 11 173 16 31Register Address Mapping 173 16 32Interrupt Controller Connections 4 2 2 42 4 444 4 4 1 1 11 nnne 179 16 33Interrupt Status a pra Ra coded sean age RE FR Rm 180 16 34Content of Interrupt Vector Byte
165. RT2 CTS N V1P8A GPIOMV MS Input 20K PU Input 20K PU 34 Datasheet Volume 1 of 3 Physical Interfaces 2 2 9 Table 2 13 I C Interface Signals 2 3 I C Interface Signals Default Buffer State Resetout Signal Name Dir Pwrgood Assert De assert ower State State 2 0 V1P8A MS 2 1K PU OD 2 1K PU OD 12 0 V1P8A GPIOMV 5 2 1K PU OD 2 1K PU OD 12C1_DATA V1P8A GPIOMV MS Input 20K PU Z 20K PU OD 12C1_CLK V1P8A MS Input 20K PU 2 20K PU OD 12C2_DATA V1P8A GPIOMV MS Input 20K PU Z 20K PU OD I2C2 V1P8A GPIOMV MS Input 20K PU 2 20K PU OD 12C3_DATA V1P8A GPIOMV MS Input 20K PU Z 20K PU OD 12C3_CLK 1 0 V1P8A GPIOMV 5 Input 20K PU 2 20K PU OD 2 4 DATA V1P8A GPIOMV MS Input 20K PU 2 20K PU OD 12C4_CLK V1P8A GPIOMV MS Input 20K PU 2 20K PU OD 12C5_DATA 1 0 GPIOMV MS Input 20K PU Z 20K PU OD I2C5 CLK 1 0 MS Input 20K PU 2 20K PU OD 2 6 DATA V1P8A GPIOMV MS Input 20K PU 2 20K PU OD 12C6_CLK V1P8A MS Input 20K PU 2 20K PU OD SIO Serial Peripheral Interface SPI Signals Table 2 14 SIO Serial Peripheral Interface SPI Signals Def
166. ST N BH42 DDR3 MO DQ 36 K22 VSS 14 PMU BATLOW N BJ37 DDR3 MO DQ 35 K24 VSS C13 PMU AC PRESENT BG37 DDR3 MO DQ 34 K30 VSS A27 PCIE_TXP3 BG43 DQ 33 K32 VSS B26 PCIE TXP2 BG42 MO DQ 32 K34 VSS A25 PCIE TXP1 BB51 DDR3 MO DQ 31 K36 VSS C24 PCIE TXPO AW53 DQ 30 206 Datasheet Volume 1 of 3 Ball Ball Out SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 9 of 11 Pin Pin Name Pin Pin Name Pin Name K4 VSS C27 PCIE_TXN3 DDR3 MO DQ 3 45 VSS C26 PCIE TXN2 DDR3 MO DQ K50 VSS C25 PCIE TXN1 DDR3 MO DQ 11 VSS B24 PCIE TXNO DDR3 MO DQ L19 VSS G24 PCIE RXP3 DDR3 MO DQ L27 VSS D22 PCIE RXP2 DDR3 MO DQ L35 VSS D20 PCIE RXP1 DDR3 MO DQ L41 VSS G20 PCIE RXPO DDR3 MO DQ 14 VSS 224 PCIE RXN3 DDR3 MO DQ M19 VSS F22 PCIE_RXN2 DDR3 MO DQ M27 VSS F20 PCIE_RXN1 DDR3 MO DQ M35 VSS 220 DDR3 M40 VSS D26 PCIE_RCOMP_P DDR3 MO DQ M45 VSS F26 PCIE_RCOMP_N DDR3 MO DQ M50 VSS 14 PCIE CLKREQ3 DDR3 MO DQ M9 VSS 14 PCIE CLKREQ2 DDR3 MO DQ N22 VSS 12 PCIE CLKREQ1 DDR3 MO DQ N24 VSS 10 PCIE CLKREQO DDR3 MO DQ N32 VSS R53 PANEL1 DDR3 MO DQ N51 VSS P51 PANEL1 BKLTEN DDR3 MO DQ N53
167. Signals and 37 2 20SATA Signals RATE 38 2 21SMBus Signals and Clocks n na mets 38 2 22Intel High Definition Audio Intel HD Audio Signals and 38 2 23Power Management Unit PMU Signals and Clocks sese e 39 2 24SPEAKER Signals and Clocks aate nk dhe sa da RR REX CFR Ra 39 2 25Miscellaneous Signals and 4 6 40 2 26Hard Strap Description and Functionality 1 40 2 27GPIO Multiplexing and a hh 42 4 1 SOC COCK Inputs 53 4 2 SOC RO RR RU 53 5 1 Temperature Reading Based on 5 000 55 6 1 General Power States for RR AY RRRRARR AR 59 6 2 Platform Voltage Rails and Power 12 2 2 1 2211 nemen eene 60 6 3 ACPI PM State Transition Rules ner tna tuya uana rne eR a ca cab 60 6 4 MEMORY States xri roster mere D
168. System Memory Signals reet eene etn kara hn nA ERRARE RANA ER 29 2 5 USB 2 0 Interface Signals eee DERE EE 30 2 6 USB 2 0 ASIC Interface 5 ae dada 31 Datasheet Volume 1 of 3 11 12 2 7 105 3 0 Interface Signals 31 2 8 Integrated Clock Interface Signals 31 2 9 Digital Display Interface Signals redeem a cda na daa daa aa RA 32 2 10MIPI CSI Interface Signals 42 nr opta Renan Fara E XR 33 2 11Storage Controller e MMC SDIO SD Interface 33 2 12High Speed UART Interface Signals cese sse daas 34 Interface aussi d NC 35 2 14SIO Serial Peripheral Interface SPI Signals 35 2 15PCU Fast Serial Peripheral Interface SPI 36 2 16PCU Real Time Clock RTC Interface 5 5 36 2 17PCU LPC Bridge Interface 5 riaki nrinn iE AANEEN 36 2 18JTAG Interface Signals rir iere 37 2 19PCI Express PCIe
169. Technology Intel 04040 00 49 3 2 1 Intel VT x 49 3 2 2 Intel VT x 50 3 3 Security and Cryptography 1 0 50 3 3 1 PCLMULQDQ 2 44 50 3 3 2 Digital Random Number Generator 2 1 2 2 20 4 1 4 1 51 3 3 3 Power Aware Interrupt Routing 51 3 4 Platform Identification and 51 3 5 iiec 51 4 Integrated 53 5 Thermal eet ER 55 5 1 OVEM E Wiseni 55 5 2 Digital Thermal 55 5 2 1 DTS TIMING 56 5 3 Egg T 57 Datasheet Volume 1 of 3 3 5 3 1 Catastrophic 1 nemen eene memes 57 5 4 SOC Programmable rer nn ond s eoa UA E ROG EU KR 57 5 4 1 AUX AERA 57 5 4 2 Aux2 AUX1 AuxO nes russes inne
170. The Low Power Engine for Audio provides acceleration for common audio and voice functions The voice and audio engine provides a mechanism for rendering audio and voice streams and tones from the operating system applications to an audio or voice codec and ultimately to the speaker headphones or Bluetooth headsets Audio streams in the SoC can be encoded and decoded by the Low Power Engine LPE in the Audio subsystem LPE Audio provides three external 125 audio interfaces Note LPE is supported for non Windows based platforms It is not supported for Windows based platforms 12 1 Signal Descriptions See Chapter 2 Physical Interfaces for additional details Table 12 1 LPE Signals Signal Name Direction Type Description GP SSP 2 0 I2S CLK I O Clock signal for 125 GP SSP 2 0 I2S FRM I O Frame select signal for 125 GP SSP 2 0 I2S DATAIN I O data for 125 GP SSP 2 0 25 DATAOUT I O TX data for 125 12 2 Features Note LPE signals multiplexed and may be used by other functions The LPE Audio Subsystem consists of the following e Integrated power efficient 32 bit architecture core with 24 bit audio processing instructions e LPE Core processing speeds up to 343 MHz Closely Coupled Memories CCMs 80KB Instruction RAM 160KB Data RAM 48KB Instruction Cache 96KB Data Cache Very low power consumption coupled with high fidelity 24 bit a
171. U 32 KHz ClocK SUS STAT N V1P8A GPIOMV MS 0 20K PU 1 SUSPWRDNACK 5 0 20 0 20K PD Speaker Signals Table 2 24 SPEAKER Signals and Clocks Default Buffer State Signal Name Dir Ll Type Pwrgood Assert Resetout ower State De assert State SPKR 10 0 20 Prg Datasheet Volume 1 of 3 39 intel 2 3 11 Miscellaneous Signals Table 2 25 Miscellaneous Signals and Clocks Physical Interfaces Default Buffer State Signal Name Dir 5 Pwrgood Assert Resetout ower State De assert State SVIDO DATA 1 5 0 0 SVIDO CLK 1 5 0 10 2 SVIDO ALERT 1 GPIOMV MS Input Input PROCHOT N IO V1P8A GPIOMV MS Z Z PLT_CLK 0 5 V1P8A GPIOMV MS 0 20k PD Clock 20K PD 2 4 Hardware Straps All straps are sampled on the rising edge of PMU_RSMRST_N Table 2 26 Hard Strap Description and Functionality Sheet 1 of 2 5 08 40 DDI SFR Bypass ICLK Xtal OSC Bypass Signal Name Purpose RAS Strap Description Weak internal 0 2010 not detected SUS 0 DDIO Detect 20k PD 1 DDIO detected Weak internal 0 2011 not detected SUS 1 DDI1 Detect 20k PD 1 1 detected Top Swap A16 Weak internal 0 Change Boot Loader address SUS 2
172. V3P3 RTC RTC PHY Input Crystal Input Crystal RTC X2 Output Crystal Output Crystal I V3P3_RTC RTC PHY Input Input RTC_TEST_N I V3P3_RTC RTC PHY Input Input RTC_EXTPAD V3P3_RTC RTC PHY Output Output CORE_PWROK I V3P3_RTC RTC PHY Input Input PMU_RSMRST_N I V3P3_RTC RTC PHY Input Input 2 3 3 PCU Low Pin Count LPC Bridge Interface Signals Table 2 17 PCU LPC Bridge Interface Signals Sheet 1 of 2 Default Buffer State Resetout Signal Name Dir a nci AD 0 3 yo Mies HS Input 20K PU Input 20K PU LPC_FRAME_N yo Wee GPIOHV HS 1 20K PU 1 LPC_SERIRQ 5 Input 20K PU Input 20K PU 36 Datasheet Volume 1 of 3 Physical Interfaces Table 2 17 PCU LPC Bridge Interface Signals Sheet 2 of 2 2 3 4 2 3 5 intel Default Buffer State Resetout Platform Pwrgood Assert Signal Name Dir Power Type State LPC CLKRUN N 1 0 URL GPIOHV HS Input 20K PU Input 20K PU V3P3A LPC CLK 0 I O GPIOHV HS 0 20K PU Clock LPC CLK 1 V3P3A GPIOHV HS Input 20K PD Input V1P8A V3P3A GPIOHV HS LPC RCOMP I O V1P8A RCOMP Z Z JTAG Interface Signals Table 2 18 JTAG Interface Signals Default Buffer State Signal Dir Platform Tuna Pwrgood Assert Resetout 9 Power Stat
173. VSS P52 PANEL1_BKLTCTL DDR3 MO DQ P10 VSS W53 PANELO VDDEN DDR3 MO DQ 19 VSS 52 PANELO_BKLTEN DDR3 MO DQ P22 VSS V51 PANELO BKLTCTL DDR3 MO DQ P27 VSS M22 OSCOUT DDR3 MO DM 7 P32 VSS P24 OSCIN DDR3 MO DM 6 P35 VSS T13 SDMMC1_RCLK DDR3 MO DM 5 P36 VSS T12 SDMMC1_D7 DDR3 MO DM 4 P4 VSS T10 SDMMC1_D6 DDR3 DM 3 P42 VSS T7 SDMMC1_D5 DDR3 MO DM 2 R1 VSS T6 5 04 SD WE DDR3 MO DNM 1 14 VSS AM7 MF_SMB_DATA DDR3_M0_DM 0 747 55 6 SMB CLK DDR3 MO CSB 1 T9 VSS 9 MF SMB ALERT DDR3 MO CSB 0 011 VSS B4 MF PLT CLK5 DDR3 MO CKE 1 U12 VSS B5 MF PLT DDR3 MO CKE 0 014 VSS B7 MF PLT CLK3 DDR3 MO CKB 1 018 VSS B8 MF PLT CLK2 DDR3 MO CKB 0 U21 VSS C9 MF PLT CLK1 DDR3 MO CK 1 U25 VSS A9 MF PLT CLKO DDR3 MO CK 0 Datasheet Volume 1 of 3 207 m e n tel Ball Map Ball Out and SoC Pin Locations Table 19 1 SoC Pin List Locations Sheet 10 of 11 Pin Pin Name Pin Pin Name Pin Pin Name 029 VSS R3 MF_LPC_CLKOUT1 BG45 DDR3_MO_CAS_N U30 VSS P2 MF_LPC_CLKOUTO BF52 DDR3 MO BS 2 U32 VSS 1 AD3 40 DDR3 MO BS 1 U33 VSS N3 MF LPC AD2 BH46 MO BS 0 U36 VSS M2 MF LPC AD1 AV28 DDR3 DRAM PWROK U38 VSS M3 MF LPC ADO D44 DDI2 TXP 3 040 VSS L13 RSVD F42 DDI2 TXP 2 042 VSS 114 RSVD 140 DDI2 TXP 1
174. _ _ 16 levels High speed data signaling common Vuscm mode voltage range guideline for 50 500 mV receiver Output Levels for Low full speed VoL Low 0 0 0 8 4 5 High Driven 2 8 3 6 4 6 1 1 0 8 Output Signal Crossover E V 1 3 2 0 V 10 CRS Voltage Output Levels for High speed Vusor High speed idle level 10 10 mV VusoH High speed data signaling high 360 440 VusoL High speed data signaling low 10 10 mV VCHIRPJ Chirp J level differential voltage 700 1100 VCHIRPK Chirp K level differential voltage 900 500 Decoupling Capacitance Cups Downstream Facing Port Bypass 120 E _ Capacitance per hub H Upstream Facing Port Bypass 1 0 _ 10 0 9 Capacitance Input Capacitance for Low Full speed Downstream Facing Port 150 pF 2 Upstream Facing Port w o cable 100 pF 3 Transceiver edge rate control 2 CEDGE capacitance pF Datasheet Volume 1 of 3 Electrical Specifications n tel Table 21 24 USB 2 0 Host DC Specification Sheet 3 of 3 Symbol Parameter Min Units Notes Input Impedance for High speed TDR specification for high speed termination Terminations ee 1 425 1 575 1 5KQ 5 Rep 4 4 14 25 15 75 KO 1 5 5 soo os v Terminations in High speed VHSTERM Termination vo
175. a digital communication interface that utilizes differential signalling to achieve a high bandwidth bus interface designed to support connections between PCs and monitors projectors and TV displays DisplayPort is also suitable for display connections between consumer electronics devices such as high definition optical disc players set top boxes and TV displays A DisplayPort consists of a Main Link Auxiliary channel and a Hot Plug Detect signal The Main Link is a uni directional high bandwidth and low latency channel used for transport of isochronous data streams such as uncompressed video and audio The Auxiliary Channel AUX CH is a half duplex bi directional channel used for link management and device control The Hot Plug Detect HPD signal serves as an interrupt request for the sink device DisplayPort Overview Main Link Isochronous Streams DP TX Auxiliary Channel Link Device Management gt DP RX Hot Plug Detect Interrupt Request DisplayPort DisplayPort SOURCE SINK Datasheet Volume 1 of 3 m e Graphics Video and Display n tel 8 2 1 2 8 2 1 3 8 2 1 4 8 2 1 5 8 2 1 6 8 3 embedded DisplayPort eDP embedded DisplayPort eDP is a embedded version of the DisplayPort standard oriented towards applications such as notebook and All In One PCs eDP is supported only on Digital Display Interfaces 0 and or
176. age 0 2 0 V 2 AUX turn around common VAUX TURN CM mode voltage 0 3 V 3 AUX Short Circuit Current Taux_SHORT Limit 90 4 Caux AC Coupling Capacitor 75 200 nF 5 Notes 1 Vaux piFFp p 2 Vauxml 2 mode voltage is equal to Vpias OF Vpias voltage 3 Steady state common mode voltage shift between transmit and receive modes of operation 4 Total drive current of the transmitter when it is shorted to its ground 5 All DisplayPort Main Link lanes as well as AUX CH must be AC coupled AC coupling capacitors must be placed on the transmitter side Placement of AC coupling capacitors on the receiver side is optional embedded Display Port AUX Channel DC Specification Table 21 13 embedded Display Port AUX Channel DC Specification Sheet 1 of 2 Symbol Parameter Min Units Notes Tw a VAUX _TERM_R DC _ 100 _ VAUX DC CM 0 1 2 2 2 _ 0 3 3 229 Datasheet Volume 1 of 3 intel Electrical Specifications Table 21 13 embedded Display Port AUX Channel DC Specification Sheet 2 of 2 21 6 1 6 Circuit Current 4 AC Coupling Capacitor 75 200 nF 5 Notes VauUx DiFFp p7 2 Vauxp Common mode voltage is equal to Vpias voltage Steady state common mode voltage shift between transmit and receive modes o
177. ally to be edge or level except for IRQO IRQ2 IRQ8 Active low interrupt sources such as a PIRQ are inverted inside the SoC In the following descriptions of the 8259s the interrupt levels are in reference to the signals at the internal interface of the 8259s after the required inversions have occurred Therefore the term high indicates active which means low on an originating PIRQ Interrupt Handling Generating Interrupts The PIC interrupt sequence involves three bits from the IRR ISR and IMR for each interrupt level These bits are used to determine the interrupt vector returned and status of any other pending interrupts Table 16 33 defines the IRR ISR and IMR Interrupt Status Registers Bit Description IRR Interrupt Request Register This bit is set on a low to high transition of the interrupt line in edge mode and by an active high level in level mode ISR Interrupt Service Register This bit is set and the corresponding IRR bit cleared when an interrupt acknowledge cycle is seen and the vector returned is for that interrupt IMR Interrupt Mask Register This bit determines whether an interrupt is masked Masked interrupts will not generate INTR Acknowledging Interrupts The processor generates an interrupt acknowledge cycle that is translated into a Interrupt Acknowledge Cycle to the SoC The PIC translates this command into two internal INTA pulses expected by the 825
178. an on 118 15 2 5 e E 119 15 2 6 Register ed one ERE 119 15 3 SIO High Speed UART 119 15 3 1 Signal 5 119 15 3 2 mM 120 15 3 2 1 VART FunctlOn errore Php ux na a RR km RE 120 15 3 2 2 Clock and Reset eee et erre D ete 120 15 3 2 3 Baud Rate eese tunes kannte kso iu da nere 121 15 3 3 WISE MEUM 121 15 3 3 1 Mode ObperatiOn eire intr pen Rin nata Fakes e ea 122 15 3 3 2 FIFO Polled Mode Operation 122 16 Platform Controller Unit PCU Overview 2 125 16 1 PCU Configuration Features for BIOS EFI Boot 125 16 1 1 BIOS EFI Swap cene enteras ninh de te dc kr MA SP AR DERE E 125 16 1 1 1 BIOS EFI Controlled 125 16 1 1 2 Hardware nnn nnn nnns 126 16 1 2 BIOS EFI Boot Stra pis
179. ardware Trips Catastrophic Trip THERMTRIP Catastrophic trip is generated by DTS whenever the ambient temperature around it reaches or extends beyond the maximum value indicated by a fuse Catastrophic trip will not trip unless enabled DTS are enabled only after HFPLL is locked Within each DTS Catastrophic trips are flopped to prevent any glitches on Catastrophic signals from affecting the SoC behavior Catastrophic trips are reset once set during power cycles Catastrophic trip signals from all DTS in the SoC are combined to generate THERMTRIP function which will in turn shut off all the PLLs and power rails to prevent SoC breakdown To prevent glitches from triggering shutdown events catastrophic trips from DTSs are registered before being sent out SoC Programmable Trips Programmable trips can be programmed to cause different actions when triggered to reduce temperature of the die Aux3 Trip By default the Aux 3 Hot Trip point is set by software firmware has an option to set these to a different value This trip point is enabled by firmware to monitor and control the system temperature while the rest of the system is being set up Aux2 1 AuxO Trip These are fully programmable trip points for general hardware protection mechanisms The programmable trips are only active after software firmware enables the trip Unlike Aux3 the Aux 2 0 trip registers default to zero To prevent spurious results software
180. atasheet Volume 1 of 3 89 90 MIPI CSI Camera Serial Interface and ISP Datasheet Volume 1 of 3 SoC Storage n tel 10 SoC Storage 10 1 SoC Storage Overview 10 1 1 Storage Control Cluster e MMC SDIO SD The SCC consists of SDIO SD and e MMC controllers to support mass storage and I O devices e Supports e MMC v4 5 1 e One SD 3 0 interface e One SDIO 3 0 interface 10 2 Signal Descriptions See Chapter 2 Physical Interfaces for additional details Table 10 1 e MMC Signals Direction Signal Description e MMC Clock SDMMC1 BASE The frequency may vary between 25 and 200 MHz Port Data bits 0 to 7 Bidirectional port used to transfer data to and from e MMC device By default after power up or reset only D 0 is used for data transfer A wider data bus can be configured for data transfer using either D 0 D 3 or D 0 D 7 by the 5 D 2 0 Multimedia carg 1 D3 N The Multi media Card includes internal pull ups for data lines D 1 D 7 I O GPIO Immediately after entering the 4 bit mode the card disconnects the internal pull ups SDMMCi 04 SD WE of lines D 1 D 2 and D 3 Correspondingly immediately after entering to the 8 SDMMC1 D 7 5 bit mode the card disconnects the internal pull ups of lines D 1 D 7 Some data signals have optional functionality 5 01 Data Line Bit 1 or Inte
181. ault Buffer State Signal Name Dir pda Type UE Bn State 5 1 0 20 0 5 1 CS 0 1 1 20K PU 1 SPI1 MOSI I 0 20 0 SPI1 MISO Input 20K Input 20K PD Note 510 SPI is supported for non Windows based platform only Datasheet Volume 1 of 3 35 Physical Interfaces intel 2 3 1 PCU Fast Serial Peripheral Interface SPI Signals Table 2 15 PCU Fast Serial Peripheral Interface SPI Signals Default Buffer State Resetout Signal Name Dir RE Type ae FST SPI GPIOMV HS 0 20K PU Output FST SPI CS 0 N GPIOMV HS 1 20K PU Output FST_SPI_CS 1 _N GPIOMV HS Input 20K PU Output FST SPI CS 2 N V1P8A GPIOMV HS 1 20K PU Output FST SPI D 0 3 10 V1P8A GPIOMV HS Input 20K PU Input 20K PU Note Flash Sharing is not supported for the processor Platform Note The SPI 50 SPI 52 and FST SPI signals do not get Tri Stated during RSMRST N assertion 2 3 2 PCU Real Time Clock RTC Interface Signals Table 2 16 PCU Real Time Clock RTC Interface Signals Default Buffer State 5 Platform Pwrgood Assert Resetout De Signal Name State assert State RTC X1 I
182. bitration on the master controller The slave controller compares this identification code to the value stored in its ICW3 and if it matches the slave controller assumes responsibility for broadcasting the interrupt vector 4 The final write the sequence 4 must be programmed for both controllers At the very least ICW4 MM must be set to a 1 to indicate that the controllers are operating in an Intel Architecture based system Operation Command Words OCW These command words reprogram the Interrupt controller to operate in various interrupt modes OCWI1 masks unmasks interrupt lines OCW2 controls the rotation of interrupt priorities when in rotating priority mode and controls the EOI function e OCW3 sets up ISR IRR reads enables disables the special mask mode SMM and enables disables polled interrupt mode Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel 16 15 1 4 16 15 1 4 1 16 15 1 4 2 16 15 1 4 3 16 15 1 4 4 Modes of Operation Fully Nested Mode In this mode interrupt requests are ordered in priority from 0 through 7 with 0 being the highest When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus Additionally the ISR for the interrupt is set This ISR bit remains set until the processor issues an EOI command immediately before returning from the service routine or if in AEOI mode on
183. ce Supports Low Pin Count LPC 1 1 Specification No support for DMA or bus mastering Supports Trusted Platform Module TPM 1 2 General Purpose Input Output Legacy control interface for SoC GPIOs I O mapped registers e 8259 Programmable Interrupt Controller Legacy interrupt support 15 total interrupts through two cascaded controllers I O mapped registers I O Advanced Programmable Interrupt Controller Legacy free interrupt support 115 total interrupts Memory mapped registers 8254 Legacy timer support Three timers with fixed uses System Timer Refresh Request Signal and Speaker Tone 152 Datasheet Volume 1 of 3 Platform Controller Unit Overview 16 7 2 2 I O mapped registers HPET High Performance Event Timers Legacy free timer support Three timers and one counter Memory mapped registers Real Time Clock RTC 242 byte RAM backed by battery Also Known As CMOS RAM Can generate wake interrupt when time matches programmed value I O and indexed registers Non Maskable Interrupt NMI support is enabled by setting the NMI Enable NMI_EN bit at I O Port 70h Bit 7 to 1b Non Maskable Interrupts NMIs can be generated by several sources as described in Table 16 19 Table 16 19 Sources NMI Source NMI Source Enabler Alternate Configuration Disabler SERR goes active Al
184. cessors and chipsets Intel virtualization Technology for IA 32 Intel 64 and Intel Architecture Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel VT x specifications and functional descriptions are included in the Inte 64 and IA 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm Other Intel VT x documents can be referenced at http www intel com technology virtualization index htm Intel VT x Objectives Robust VMMs no longer need to use paravirtualization or binary translation This means that they will be able to run off the shelf operating systems and applications without any special steps Enhanced Intel VT enables VMMs to run 64 bit guest operating systems on IA x86 processors More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide improved reliable virtualized platform Datasheet Volume 1 of 3
185. ck Thermal Management Power Management System Memory Controller Graphics Video and Display MIPI CSI Camera Serial Interface and ISP SoC Storage USB Controller Interfaces Low Power Engine LPE for Audio I S Intel Trusted Execution Engine Intel Intel High Definition Audio Intel HD Audio Serial I O 510 Overview Platform Controller Unit PCU Overview Serial ATA SATA PCI Express 2 0 Ball Map Ball Out and SoC Pin Locations Package Information e Electrical Specifications Volume 2 Registers Register Access Method Registers Mapping Address Space Registers System Memory Controller Registers SoC Transaction Router Registers Graphics Video and Display Registers MIPI CSI Camera Serial Interface and ISP Registers SoC Storage Registers USB xHCI PCI Configuration Registers Volume 3 Registers Low Power Engine LPE for Audio I2S Registers e Intel High Definition Audio Intel HD Audio Registers Serial I O SIO Registers Datasheet Volume 1 of 3 19 intel Table 1 1 1 2 20 Introduction Structure of the Processor Datasheet Sheet 2 of 2 Description e Platform Controller Unit PCU Registers Serial SATA Registers PCI Express 2 0 Regis
186. ck domains Link side Up to 24 MHz SSP1 Clock Fabric side 50 OSC SSP1 clock domains Link side Up to 24 MHz SSP2 Clock Fabric side 50 OSC SSP2 clock domains Link side Up to 24 MHz Datasheet Volume 1 of 3 m Low Power Engine LPE for Audio 125 n tel 12 5 2 12 5 3 12 5 4 Note 12 5 5 12 5 6 38 4 MHz Clock for LPE 38 4 MHz the 2X OSC clock is added to increase MIPS for low power MP3 mode This frequency will be supplied by the clock doubler internal to the SoC Clock Control Unit Calibrated Ring Osc 50 100 MHz Clock for LPE A calibrated Ring Oscillator in the SUS provides a 50 MHz or an 100 MHz clock as another option for higher MIPS for low power MP3 mode It is expected that this will be required to support decode of HE AAC streams in the low power mode Cache and CCM Clocking Data CCM Data cache Instruction CCM and Instruction Cache run off of the LPE clock These memories are in a single clock domain All Data CCM and Instruction CCM run in the same clock domain SSP Clocking SSP could be used as either clock masters or clock slaves Consequently these IPs have dual clock domains The first clock domain is clocked from an internal clock for example fabric clock and is used for generic logic like interrupt generation and register access The second clock domain drives the serial shift register either driven internally or externally When driven internally
187. ctionality ensure that there is no contention or conflict between the Hard Strap selection and GPIO direction 3 imperative that GPIO SUS 6 is sampled High Logic 1 at RSMRST to ensure proper system and GPIO functionality 4 There is no Hard Strap for DDI2 Detection Enabling DDI2 does not require a Hard Strap it is always enabled by default whether it is used for HDMI AVI or DP eDP can only be used on DDIO and DDI1 Datasheet Volume 1 of 3 41 Note Note Note Note Note n Physical Interfaces GPIO Multiplexing GPIO General Purpose IO are provided for added design flexibility There are 192 GPIOs on the processor and all these signals can be used as GPIO Each of these signals has a default mode and function based on SoC design These pins have multiple functionality modes depending on the configuration done through the BIOS Configuration of these pins as GPIOs is also done through BIOS The list in the following table provides the details on the specifications of the GPIO signals For more details on the GPIO Configuration Registers refer to the processor Datasheet Volume 3 Sections 35 5 35 9 the GPIOs listed here are powered by the 1 8VA always on rail Depending on the design implementation there may be some amount of power leakage observed in Sx state due to a Pull up on un powered devices and b Driving High into an un powered device Adding BIOS patch f
188. cycle alternately asserting and negating IRQO 16 10 2 2 Counter 1 Refresh Request Signal This counter is programmed for Mode 2 operation and impacts the period of the NSC RTS register bit Programming the counter to anything other than Mode 2 results in undefined behavior 16 10 2 3 Counter 2 Speaker Tone This counter provides the speaker tone and is typically programmed for Mode 3 operation The counter provides a speaker frequency equal to the counter clock frequency 1 193 MHz divided by the initial count value The speaker must be enabled by a write to the NSC SDE register bit 16 10 3 Use 16 10 3 1 Timer Programming The counter timers are programmed in the following fashion 1 Write a control word to select a counter 2 Write an initial count for that counter 3 Load the least and or most significant bytes as required by Control Word Bits 5 4 of the 16 bit counter 4 Repeat with other counters Only two conventions need to be observed when programming the counters First for each counter the control word must be written before the initial count is written Second the initial count must follow the count format specified in the control word least significant byte only most significant byte only or least significant byte and then most significant byte Datasheet Volume 1 of 3 165 intel Platform Controller Unit PCU Overview A new initial count may be written to a counter at any time without affect
189. d Other i to work with I O cards Read only cards and Read Write Supports Read wait Control Suspend Resume operation Interface can not be used as a wake event SDIO Interface v3 0 1 port Host Clock rate variable between 0 and 200 MHz SDIO Speed SDR104 mode up to 800Mb s data rate using 4 parallel data lines SDIO data transfer Transfer the date in 1 bit and 4 bit SD modes Storage rate Transfers the data in following UHS I modes SDR12 25 50 104 and 20850 Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity SDIO Other 22 to work with I O cards Read only cards and Read Write Supports Read wait Control Suspend Resume operation Interface can not be used as a wake event eMMC Interface v4 5 1 1 port Host Clock rate variable between 0 and 200MHz HS200 mode Up to 1600 Mb s data rate using 8 bit parallel lines eMMC Speed HS400 mode Up to 3200 Mb s data rate using 8 bit parallel lines High Speed DDR mode Up to 800 Mb s data rate using 8 bit parallel lines eMMC data transfer Transfer the date in 1 bit and 4 bit SD modes rate eMMC Other Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity USB 3 0 4 Super Speed SS Ports in total All multiplexed with HS ports USB 3 0 Max Speed 5Gb s 1 High Speed HS Ports 4 multiplexed with SS Ports 5 Ports in USB 2 0 total USB USB 2 0 Max Speed 5Gb s USB HSIC 2 High Speed Inter Chip Ports USB HSIC Max 480Mb s Only Speed Datasheet Volume 1 of 3
190. d during manufacturing for the base configuration when executing a near worst case commercially available workload as specified by Intel for the SKU segment TDP may be exceeded for short periods of time or if running a very high power workload The following table specifies the thermal limits for the processor based on the definitions above Turbo frequencies are opportunistically selected when thermal headroom exists Automatic throttling along with a proper thermal solution ensure will not be exceeded Datasheet Volume 1 of 3 215 intel Table 21 1 SoC Base Frequencies and Thermal Specifications Electrical Specifications Processor Graphics Thermal Scenario SKU Configur Frequency Frequency Design Design Ti C Segment ation LFM HFM Burst LFM HFM Dyn Power Power Hz Hz TDP W SDP W N3700 QC Base 480M 1 6G 2 4G 200M 400M 700M 6 4 90 N3150 QC Base 480M 1 6G 2 08G 200M 320M 640M 6 4 90 N3050 DC Base 480M 1 6G 2 16G 200M 320M 600M 6 4 90 N3000 DC Base 480M 1 04G 2 08G 200M 320M 600M 4 3 90 21 3 Storage Conditions This section specifies absolute maximum and minimum storage temperature and humidity limits for given time durations Failure to adhere to the specified limits could result in physical damage to the component If this is suspected Intel recommends a visual inspection to determine possible physical damage to the silicon or surface component
191. d start condition to denote a read from that device s address The slave then returns 1 or 2 bytes of data Software must force the SMB Config HCFG I2C EN bit to Ob when running this command When programmed for the read byte word command the Transmit Slave Address Mem TSA and Host Command 5 HCMD registers are sent Data is received into the Data 0 Mem on the read byte and the Data 0 Mem and Data 1 SMB Mem HD1 registers on the read word See section 5 5 5 of the System Management Bus SMBus Specification Version 2 0 for the format of the protocol 144 Datasheet Volume 1 of 3 m Platform Controller Unit Overview n tel Note Note Note Process Call The process call is so named because a command sends data and waits for the slave to return a value dependent on that data The protocol is simply a Write Word followed by a Read Word but without a second command or stop condition When programmed for the Process Call command the SoC transmits the Transmit Slave Address SMB Mem TSA Host Command SMB HCMD Data 0 SMB 0 Data 1 5 Mem HD1 registers Data received from the device is stored in the Data 0 SMB Mem HDO and Data 1 SMB Mem HD1 registers The Process Call command with SMB Config HCFG I2C EN set and the SMB Config HCTL PECEN bit set produces undefined results Software must force either SMB Config HCFG I2C SMB C
192. d to remove power to system memory The PMU 54 logic in the SoC provides a mechanism to fully cycle the power to the DRAM and or detect if the power is not cycled for a minimum time To use the minimum DRAM power down feature that is enabled by the GEN 1 54 5 bit the DRAM power must be controlled by the SLP 54 signal CORE PWROK Signal When asserted CORE PWROK is an indication to the SoC that its core well power rails are powered and stable CORE PWROK can be driven asynchronously When CORE PWROK is low the SoC asynchronously asserts PMU_PLTRST CORE PWROK must not glitch even if PMU_RSMRST is low It is required that the power rails associated with PCI Express have been valid for 99 ms prior to PWROK assertion in order to comply with the 100 ms PCI Express 2 0 Specification on PMU_PLTRST de assertion RSTBTNZ is recommended for implementing the system reset button This saves external logic that is needed if the CORE PWROK input is used Additionally it allows for better handling of the processor resets and avoids improperly reporting power failures Datasheet Volume 1 of 3 Platform Controller Unit Overview intel 16 2 2 3 4 PMU_BATLOW Battery Low The PMU_BATLOW input can inhibit waking from S4 and S5 states if there is not sufficient power It also causes an SMI if the system is already in an SO state 16 2 2
193. dance 80 100 1 MIPI CSI LP RX Mode Logic 1 input voltage 880 Logic input voltage not in ULP state 550 mV VIL ULPS Logic 0 input voltage ULP state 300 Vuyst Input hysteresis SCC SDIO DC Specification Table 21 17 provides the SDIO DC Specification For all other DC Specifications not listed in Table 21 17 refer to Table 21 36 GPIO 1 8V Core Well Signal Group DC Specification Table 21 17 SDIO DC Specification 21 6 4 Symbol Parameter Min Unit Notes Output High Voltage Measured at Vou E 7 B i maximum Current at VoL Voh 2 m SCC SD DC Specification Table 21 18 provides the SD Card DC Specification For all other DC Specifications not listed in Table 21 18 refer to Table 21 36 GPIO 1 8V Core Well Signal Group DC Specification Table 21 18 SD Card DC Specification Sheet 1 of 2 232 Symbol Parameter Min Max Unit VREF Voltage SDIO_V3P3A_V1P8A_G3 VoH 3 3 Output High Voltage 0 75 VREF 3 Output Low Voltage 0 1 VREF Datasheet Volume 1 of 3 Electrical Specifications n tel Table 21 18 SD Card DC Specification Sheet 2 of 2 Symbol Parameter 3 3 Input High Voltage 3 3V 0 3 Vit 3 3 Input Low Voltage 3 3V 0 25 VREF Von 1 8 Output High Voltage VoL
194. dard mode bit rate up to 100Kb s e Fast mode bit rate up to 400Kb s e Fast Mode Plus bit rate up to 1Mb s High Speed mode bit rate up to 1 7Mb s The 12 can communicate with devices only using these modes as long as they are attached to the bus Additionally high speed mode fast mode plus and fast mode devices are downward compatible e High Speed mode devices can communicate with fast mode and standard mode devices in a mixed speed bus system e Fast mode devices can communicate with standard mode devices in a 0 100Kb s 12 bus system However according to the I C specification standard mode devices are not upward compatible and should not be incorporated in a fast mode I C bus system since they cannot follow the higher transfer rate and unpredictable states would occur Datasheet Volume 1 of 3 117 n tel Serial I O SIO Overview 15 2 4 3 Functional Description The I C master is responsible for generating the clock and controlling the transfer of data e The slave is responsible for either transmitting or receiving data to from the master The acknowledgement of data is sent by the device that is receiving data which can be either a master or a slave Each slave has a unique address that is determined by the system designer When a master wants to communicate with a slave the master transmits a START RESTART condition that is then followed by the slave s address and a control bit R W to
195. decs can accept the same output stream processed by a single DMA engine Codec commands and responses are also transported to and from the codec by means of DMA engines The DMA engine dedicated to transporting commands from the Command Output Ring Buffer CORB in memory to the codec s is called the CORB engine The DMA engine dedicated to transporting responses from the codec s to the Response Input Ring Buffer in memory is called the RIRB engine Every command sent to a codec yields a response from that codec Some commands are broadcast type commands in which case a response will be generated from each codec A codec may also be programmed to generate unsolicited responses which the RIRB engine also processes The platform also supports Programmed I O based Immediate Command Response transport mechanism that can be used by BIOS prior to memory initialization Datasheet Volume 1 of 3 113 Intel High Definition Audio Intel HD Audio 14 1 Signal Descriptions Table 14 1 Signals Description Signal Name Description ype HDA RST Z Intel HD Audio Reset Master hardware reset to external codecs HDA SYNC Intel HD Audio Sync 48 KHz fixed rate Intel HD Audio Bit Clock Output 24 MHz serial data clock HDA_CLK o generated by the Intel HD Audio controller 00 Intel HD Audio Data Out Serial data output to the codec s The serial output is double pumped
196. determine if the master wants to transmit data or receive data from the slave The slave then sends an acknowledge ACK pulse after the address e If the master master transmitter is writing to the slave slave receiver The receiver gets one byte of data This transaction continues until the master terminates the transmission with a STOP condition e If the master is reading from a slave master receiver The slave transmits slave transmitter a byte of data to the master and the master then acknowledges the transaction with the ACK pulse This transaction continues until the master terminates the transmission by not acknowledging NACK the transaction after the last byte is received and then the master issues a STOP condition or addresses another slave after issuing a RESTART condition This behavior is illustrated in the following figure Figure 15 2 Data Transfer on the I C Bus ze PiorR Data ere iL LSB ack ACK HE dur EU from slave oo 4 from receiver Clock_ 5 1 2 7 9 1 2 e RiorP 7 TT PME PE CERT STOP AND START or Byte Complete Clock held low RESTART RESTART Interrupt within while servicing Conditions Conditions Slave interrupts 15 2 4 3 1 START and STOP Conditions When the bu
197. e De assert State JTAG TCK 10 V1P8A GPIOMV MS Input 5K PD Input 5K PD JTAG TDI 10 V1P8A GPIOMV MS Input 5K PU Input 5K PU JTAG TDO 10 V1P8A GPIOMV MS 2 2 JTAG TMS 10 V1P8A GPIOMV MS Input 5K PU Input 5K PU JTAG TRST 10 V1P8A GPIOMV MS Input 5K PU Input 5K PU JTAG_PRDY_N V1P8A GPIOMV MS 2 5K PU OD PU T Input 5K PU Input 5K PU PREQ I O V1P8A GPIOMV MS OD OD PCI Express PCIe Signals Table 2 19 PCI Express PCIe Signals and Clocks Default Buffer State Platform Pwrgood Assert Resetout signal Name Dir Power Type State De assert State PCIE_RXN 0 3 I 1 X Weak pull down PCIE RXP 0 3 I 1 X Weak pull down PCIE TXN 0 3 V1P05A PCIe PHY X 2 PCIE TXP 0 3 V1P05A PCIe PHY X 2 PCIE I O V1P05A PCIe PHY X Output PCIE RCOMP P I O V1P05A PHY X Output PCIE CLKREQ 0 3 10 V1P8A GPIOMV MS Input 20K PU Input 20K PU Datasheet Volume 1 of 3 37 intel 2 3 6 Table 2 20 SATA Signals and Clocks SATA Signals Physical Interfaces Default Buffer State 2 3 7 Signal Name Dir Pwrgood Assert Resetout ower State De assert State SATA GP 0 1 1 0 V1P8A GPIOMV MS Input 20K PD Input 20K PD SATA GP 2 3 I O V1P8A GPIOMV MS 0 20K PD 0 20K PD SATA_LED_N GPIOMV MS 1 20K PD Prg S
198. e SCI SMI messages the PMC Enable capability should be implemented in the source unit 6 Sync SMI has the same message opcode toward T Unit Special treatment regarding this Sync SMI is holding completion to host till SYNC SMI ACK message is received from T Unit 7 Sync SMI has the same message opcode toward T Unit Special treatment regarding this Sync SMI is holding the SSMI ACK message to till SYNC SMI message is received from T Unit 8 G Unit is an internal functional sub block which forms part of the graphics functional block 9 Refer to the processor Datasheet Volume 3 of 3 Section 35 4 4 for more details see Related Documents section 10 Refer to the processor Datasheet Volume 3 of 3 Section 35 4 8 for more details see Related Documents section 16 2 2 5 Platform Clock Support The SoC supports up to 6 clocks PMU PLT CLK 5 0 with a frequency of 19 2 MHz These clocks are available for general system use where appropriate and each have Control and Frequency register fields associated with them 16 2 2 6 INITZ Initialization Generation The INIT functionality is implemented as a virtual wire internal to the SoC rather than a discrete signal This virtual wire is asserted based on any one of the events described in below table When any of these events occur INIT is asserted for 16 PCI clocks and then driven high INIT when asserted resets integer registers inside the Processor cores without affecting
199. e high Xenon Flash trigger Enables Torch Mode on LED Flash IC GP CAMERASBOS JO Ena ies Red Eye Reduction LED for Xenon Triggers STROBE on LED Camera Sensor 0 Strobe Output to SoC to indicate beginning of GFP CAMERASBOG ue capture Active high signal to still camera to power down the device Camera Sensor 1 Strobe Output to SoC to indicate beginning of GP_CAMERASBO7 yo capture Active high signal to still camera to power down the device CAMERASBOS I O Active high signal to video camera to power down the device GP CAMERASBO9 I O Active low output signal to reset digital still camera 0 GP CAMERASB10 I O Active low output signal to reset digital still camera 1 CAMERASB11 I O Active low output signal to reset digital video camera Datasheet Volume 1 of 3 81 intel MIPI CSI Camera Serial Interface and ISP Figure 9 1 Camera Connectivity in Uu Uu i A uU Camera ISP Port 1 Port 1 PHY Port 2 PHY 0 0 Data 1 Data 1 C Cock deu 1 Port 3 0 MIPI CSI Controller Camera GPIO 9 1 1 Imaging Capabilities The following table summarizes imaging capabilities Table 9 3 Imaging Capabilities Feature Capabilities Sensor interface Simultaneous sensors Configurable MIPI CSI2 interfaces 3 sensors x2 x2 x2 or x1 x2 x3 2 sensors x4 x2 Up to 3 simultaneous sensors 2 D
200. e minimum voltage level at a receiving agent that will be interpreted as a logical high 2 defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low Wo CORE VCCO and CORE 4 For VIN between and CORE and CORE VCC1 Measured when driver is tri stated Datasheet Volume 1 of 3 Electrical Specifications intel Figure 21 1 Definition of Differential Voltage and Differential Voltage Peak to Peak Common Mode B 233 Vo V D V D V DIFFp p Figure 21 2 Definition of Pre Emphasis Pre emphasis 20 Log Vpiee pre V pire 1 2 Datasheet Volume 1 of 3 231 intel 21 6 2 Electrical Specifications MIPI Camera Serial Interface CSI DC Specification Table 21 16 MIPI HS RX MIPI LP RX Minimum Nominal and Maximum Voltage 21 6 3 Parameters Symbol Parameter Min Unit Notes Pin Leakage current 10 10 MIPI CSI HS RX Mode VCMRX DC Common mode voltage HS receive mode 70 330 VipTH Differential input high threshold 70 ViprL Differential input low threshold 70 mV VIHHS Single ended input high voltage 460 mV Single ended input low voltage 40 VTERM EN Single ended threshold for HS termination _ 450 enable Zip Differential input impe
201. ealAudio OggVorbis FLAC DD DD 12 2 1 2 Audio Encode The Audio core supports encoding of the following formats 98 MP3 AAC LC WMA DD 2channel Datasheet Volume 1 of 3 m Low Power Engine LPE for Audio 125 n tel 12 3 12 3 1 Detailed Block Level Description LPE Core The LPE core in the SoC runs at maximum frequency of 343 MHz and interfaces with the rest of the SoC system through the OCP bus It is one of the masters on the Audio Sub Fabric The IA 32 Processor and LPE DMA engines are the other masters on the fabric The following figure shows the LPE core and its interfaces Figure 12 1 Audio Cluster Block Diagram 12 3 2 Instruction Instruction Cache RAM To From IOSF2OCP bridge OCP 2 U 22bit APB Slave JTAG gt E LPE y Bridge 2 15 gt SSPO gt Interrupt go M N LPE 32 bit APB Slave a SSP1 conor Stim 4 ontrol M N Config Signals CLK 4KB S Data Mailbox Data RAM Cache u 32 bit APB Slave b p SSP2 gt lt 32 bit OCP Slave M N LPE DMA 00 32 bit OCP Master Writes F lt 32 bit OCP Master Reads b r 14 32 bit OCP Slave 01 32 bit OCP Master Writes 32 bit OCP Master Reads g
202. ecting the SoC and display devices utilizes transition minimized differential signaling TMDS to carry audiovisual information through the same HDMI cable HDMI includes three separate communications channels TMDS DDC and the optional CEC consumer electronics control not supported by the SoC As shown in Figure 8 2 the HDMI cable carries four differential pairs that make up the TMDS data and clock channels These channels are used to carry video audio and auxiliary data In addition HDMI carries a VESA DDC The DDC is used by an HDMI Source to determine the capabilities and characteristics of the sink Datasheet Volume 1 of 3 73 intel Figure 8 2 8 2 1 1 Figure 8 3 74 Graphics Video and Display Audio video and auxiliary control status data is transmitted across the three TMDS data channels The video pixel clock is transmitted on the TMDS clock channel and is used by the receiver for data recovery on the three data channels The digital display data signals driven natively through the SoC are AC coupled and needs level shifting to convert the AC coupled signals to the HDMI compliant digital signals HDMI Overview TMDS Data Channel 0 TMDS Data Channel 1 gt TX HDMI RX TMDS Data Channel 2 TMDS Clock Channel Hot Plug Detect Display Data Channel DDC HDMI HDMI SOURCE SINK DisplayPort DisplayPort is
203. ed to as MO Function 2 Vref signals are not connected on the SoC side leave as NC 3 There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other side is either identical or empty Table 7 2 Other Memory DDR3L Signals Direction Signal Description I Core Power OK This signal indicates the status of the DDR3 CORE PWROK DDR3 DRAM Core power supply power on in SO Active high signal indicates that DDR PHY voltage 1 5V is good DDR3 DRAM PWROK BERS VDD Power OK Asserted once the VRM is settled DDR3 MO DRAMRST DRAM Reset This signal is used to reset DRAM devices 7 2 System Memory Technology Supported Table 7 3 Supported DDR3L DRAM Devices DRAM Bank Row Column Density Width Banks Address Address Address Page Size 1Gb x8 8 A 9 0 1KB 2Gb x8 8 A 9 0 1KB 4Gb x8 8 A 9 0 1KB 8Gb x8 8 11 A 9 0 2KB 1Gb x16 8 9 0 2 2Gb x16 8 A 9 0 2KB 4Gb x16 8 BA 2 0 A 14 0 A 9 0 2KB 8Gb x16 8 BA 2 0 A 15 0 A 9 0 2KB Table 7 4 Supported DDR3L Memory Size Per Rank Memory DRAM Size Rank Chips Rank DRAM Chip DRAM Chip Density Data Width Page Size 64 bit Data Bus 1GB 8 1Gb x8 8KB 1KB 8 chips 2GB 8 2Gb x8 8KB 1KB 8chips 4GB 8
204. ed and may be used 51 8 by other functions 116 Datasheet Volume 1 of 3 Serial 510 Overview tel 15 2 4 15 2 4 1 15 2 4 2 Features 2 Protocol The 12 bus is a two wire serial interface consisting of a serial data line and a serial clock These wires carry information between the devices connected to the bus Each device is recognized by a unique address and can operate as either a transmitter or receiver depending on the function of the device Devices are considered slaves when performing data transfers as the SoC will always be a Master A master is a device which initiates a data transfer on the bus and generates the clock signals to permit that transfer At that time any device addressed is considered a slave e The SoC is always the 2 master and it supports multi master mode e The SoC can support clock stretching by slave devices The 2 DATA line is a bidirectional signal and changes only while the I2Cx CLK line is low except for STOP START and RESTART conditions e The output drivers are open drain or open collector to perform wire AND functions on the bus The maximum number of devices on the bus is limited by the maximum capacitance specification of 400 pF e Refer to Chapter 21 Electrical Specifications for details e Data is transmitted in byte packages I C Modes of Operation The I C module can operate in the following modes e Stan
205. ed and may be used by other functions 1 8 I Compensation Resistor LPC RCOMP CMOS3 3 1 8 16 8 2 Features The LPC interface to the SoC is shown in Figure 16 2 Note The SoC implements all of the signals that are shown as optional but peripherals are not required to do so Note The LPC controller does not implement bus mastering cycles or DMA 154 Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel Figure 16 2 LPC Interface Diagram 16 8 2 1 16 8 2 2 Note 16 8 2 3 Note SOC LPC Device LAD 3 0 LPC AD 3 0 LFRAME LPC_FRAME_N PMC_PLTRST OLPC SERIRQ LPC CLKRUN PMC SUS STAT N LPCPD Optional GPI LSMI Optional SERIRQ Optional CLKRUN Optional y vvv v v v Note The General Purpose Input GPI must use a SMI capable Memory Cycle Notes For cycles below 16M the LPC Controller will perform standard LPC memory cycles For cycles targeting firmware BIOS EFI code only firmware memory cycles are used Only 8 bit transfers are performed If a larger transfer appears the LPC controller will break it into multiple 8 bit transfers until the request is satisfied If the cycle is not claimed by any peripheral and subsequently aborted the LPC Controller will return a value of all 1s to the processor Trusted Platform Module TPM 1 2 Support The LPC interface
206. ed life expectancy once returned to function limits At conditions exceeding absolute specifications neither functionality nor long term reliability can be expected Parts may not function at all once returned to functional limits Although the processor contains protective circuitry to resist damage from Electrostatic discharge ESD precautions should always be taken to avoid high static voltages or electric fields Thermal Specifications The thermal solution provides both component level and system level thermal management To allow optimal operation and long term reliability of Intel processor based systems the system processor thermal solution should be designed so that the processor Remains below the maximum junction temperature specification at the maximum thermal design power TDP Conforms to system constraints such as system acoustics system skin temperatures and exhaust temperature requirements Thermal specifications given in this section are on the component and package level and apply specifically to the processor Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system The processor TDP is the maximum sustained power that should be used for design of the processor thermal solution TDP is a power dissipation and junction temperature operating condition limit specified in this document that is validate
207. eet 1 of 3 Interrupt Result SMI EN SMI EN Event Status Indication Enable Condition SMI 1 GBL SMI EN Ob 1 5 1 5 1 5 PM1 5 CI_EN 1b EN Ob CI_EN 1b 0 Power Button PM1 STS EN None Override PWRBTNOR_STS None Sel None RTC Alarm 1 STS EN 1 STS EN 575 al Power Button Press 1 STS EN 1 STS EN PWRBTN 575 PWRBTN_EN 1b SCI SMI e None EN BIOS RLS PMi 515 EN 1 STS EN EN bit written to 164 GBL STS GBL_EN 1b ACPI Timer overflow 1 STS EN PM1_STS_EN_EN 2 34 seconds TMROF_STS TMROF_EN 1b SCI SMI SCI None Datasheet Volume 1 of 3 131 intel Table 16 6 Causes of SMI and SCI Sheet 2 of 3 Platform Controller Unit PCU Overview Interrupt Result SUS GPIO SMI STS n or ALT SMI SUS GPIO SMI EN n 1b SMI EN SMI EN Event Status Indication Enable Condition SMI EN 1b GBL SMI EN Ob 1 CNT S PM1 5 1 CNT S CNT S CI CI EN Ob 1 0 GPI n GPEOa 515 GPIO ROUT n CORE GPIO STS n 10b or and GPEOa STS 5 GPEOa 505 GPIO STS n CORE GPIO RPM SCI None SCI None or GPEOa EN SUS GPIO EN n 1b Internal Bus 0 GPEOa STS GPEO EN PME Capable Agents PME BO STS PME BO EN 1b SCI SMI SCI None
208. eing serviced In the worst case a device requesting an interrupt has to wait until each of seven other devices are serviced at most once There are two ways to accomplish automatic rotation using OCW2 REOI the Rotation on Non Specific EOI Command OCW2 REOI 101b and the rotate in automatic EOI mode which is set by OCW2 REOI 100b Specific Rotation Mode Specific Priority Software can change interrupt priorities by programming the bottom priority For example if IRQ5 is programmed as the bottom priority device then IRQ6 is the highest priority device The Set Priority Command is issued in OCW2 to accomplish this where OCW2 REOI 11xb and OCW2 ILS is the binary priority level code of the bottom priority device In this mode internal status is updated by software control during OCW2 However it is independent of the EOI command Priority changes can be executed during an EOI command by using the Rotate on Specific EOI Command in OCW2 OCW2 REOI 111b and OCW2 ILS IRQ level to receive bottom priority Datasheet Volume 1 of 3 183 Platform Controller Unit PCU Overview 16 15 1 4 5 16 15 1 4 6 16 15 1 5 16 15 1 5 1 184 Poll Mode Poll mode can be used to conserve space in the interrupt vector table Multiple interrupts that can be serviced by one interrupt service routine do not need separate vectors if the service routine uses the poll command Poll mode can also be used to expand the number o
209. emphasis 7 5 9 5 11 4 1 228 Datasheet Volume 1 of 3 Electrical Specifications n tel Table 21 11 embedded Display Port DC Specification Symbol Parameter Min Typ Max Units Notes Differential Return Loss at 0 675GHz at Tx Package pins 12 7 dB 4 RLrX DIFF Differential Return Loss at 9 4 1 35 GHz at Tx Package pins TX Output Capacitance 1 5 pF 5 Notes 1 Steps between VTX DIFFP P voltages must be monotonic The actual VTX DIFFP P 1 voltage must be equal to or greater than the actual VTX DIFFP P 0 voltage the actual VTX DIFFP P 2 voltage must be greater than the actual VTX DIFFP P 1 voltage and so forth 2 The recommended minimum VTX DIFFP P delta between adjacent voltages is mV 3 Allows eDP Source devices to support differential signal voltages compatible with eDP v1 3 and lower devices and designs 4 Straight loss line between 0 675 GHz and 1 35 GHz 5 Represents only the effective lump capacitance seen at the SoC interface that shunts the TX termination 21 6 1 4 DisplayPort AUX Channel DC Specification Table 21 12 DDI AUX Channel DC Specification 21 6 1 5 Symbol Parameter Min Typ Max Units Notes AUX Peak to peak Voltage at _ VAUX DIFFp p a transmitting Device 0 29 1 38 AUX CH termination DC VAUX TERM_R resistance 7 109 7 AUX DC Common Mode VAUX DC CM Volt
210. enabled by 1 54 5 the power button is not a wake event As result it is conceivable that the user will press and continue to hold the power button waiting for the system to awake Since a 4 second press of the power button is already defined as an unconditional power down the power button timer will be forced to inactive while the power cycle timer is in progress Once the power cycle timer has expired the power button awakes the system Once the minimum SLP 54 power cycle expires the power button must be pressed for another 4 to 5 seconds to create the override condition to S5 Sleep Button The Advanced Configuration and Power Interface specification defines an optional sleep button It differs from the power button in that it only is a request to go from SO to S4 not S5 Also in an S5 state the power button can wake the system but the sleep button cannot Although the SoC does not include a specific signal designated as a sleep button one of the GPIO signals can be used to create a Control Method sleep button See the Advanced Configuration and Power Interface specification for implementation details PME BO PCI Power Management Event Bus 0 The STS PME 575 bit exists to implement PME like functionality for any internal device on Bus 0 with PCI power management capabilities PMU_RSTBTN Signal When the PMU RSTBTNZ pin is detected as active after the 16 ms debounce logic the S
211. end user has not selected enabled this feature The graphics software will automatically switch to a lower refresh rate for maximum battery life when the design application is on battery power and when the user has selected enabled this feature There are two distinct implementations of Intel SDRRS Technology static and seamless The static Intel SDRRS Technology method uses a mode change to assign the new refresh rate The seamless Intel SDRRS Technology method is able to accomplish the refresh rate assignment without a mode change and therefore does not experience some of the visual artifacts associated with the mode change SetMode method Memory Power Management The main memory is power managed during normal operation and in low power states Disabling Unused System Memory Outputs Any System Memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM signals are Reduced power consumption Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven SCKE tri state should be enabled by BIOS where appropriate since at reset all rows must
212. er communicates with the internal external codecs over the Intel HD Audio serial link The output DMA engines move digital data from system memory to a D A converter in a codec The SoC implements a single Serial Data Output SDO signal that is connected to the external codecs The input DMA engines move digital data from the A D converter in the codec to system memory The platform supports up to two external codecs by implementing two Serial Data Input SDI signals each being dedicated to a single codec Audio software renders outbound and processes inbound data to from buffers in memory The location of the individual buffers is described by a Buffer Descriptor List that is fetched and processed by the audio controller The data in the buffers is arranged in a pre defined format The output DMA engines fetch the digital data from memory and reformat it based on the programmed sample rate bits sample and number of channels The data from the output DMA engines is then combined and serially sent to the codec s over the Intel HD Audio link The input DMA engines receive data from the codec s over the Intel HD Audio link and format the data based on the programmable attributes for that stream The data is then written to memory in the predefined format for software to process Each DMA engine moves one stream of data A single codec can accept or generate multiple streams of data one for each A D or D A converter in the codec Multiple co
213. erface and ISP 9 3 1 9 3 2 9 3 3 9 3 4 86 Functional Description At a high level the Camera Subsystem supports the following modes Preview Image capture Video capture Preview Mode Once the ISP and the camera subsystem is enabled the ISP goes into the preview mode where very low resolution frames such as VGA 480p programmable are being processed Image Capture During the image capture mode the camera subsystem can acquire at a peak throughput of 5megapixels While doing this it continues to output preview frames simultaneously The ISP can output RAW RGB or YUV formats The ISP can capture one full frame at a time or perform burst mode capture where up to five full back to back frames are recorded The ISP will not limit the number of back to back full frames captured but the number is programmable and determined on how much memory can be allocated dynamically The ISP can process all the frames the fly and writes to memory only after fully processing the frames without requiring download of any part of the frame for further processing The exceptions to this approach are image stabilization and some other advanced functions requiring temporal information over multiple frames The ISP can support image stabilization in image capture model The ISP initially outputs preview frames e When the user decides to capture the picture image stabilization is enabled The ISP c
214. es not implement any external PIRQ signals The PIRQs referred to in this chapter originate from the interrupt routing unit Interrupt Controller Connections Sheet 1 of 2 8259 8259 Connected Pin Function Input 0 Internal Timer Counter 0 output or HPET 0 determined by GCFG LRE register bit 1 IRQ1 using SERIRQ Keyboard Emulation 2 Slave controller INTR output 3 IRQ3 by means of SERIRQ or PIRQx Master 4 IRQ4 by means of SERIRQ or PIRQx or PCU UART1 5 5 by means of SERIRQ or PIRQx 6 IRQ6 by means of SERIRQ or PIRQx 7 IRQ7 by means of SERIRQ or PIRQx Datasheet Volume 1 of 3 179 m e n tel Platform Controller Unit PCU Overview Table 16 32 Note 16 15 1 1 16 15 1 1 1 Table 16 33 16 15 1 1 2 180 Interrupt Controller Connections Sheet 2 of 2 8259 E Connected Pin Function 0 Inverted IRQ8 from internal RTC or 1 IRQ9 by means of SERIRQ SCI or PIRQx 2 IRQ10 by means of SERIRQ SCI or PIRQx 3 IRQ11 by means of SERIRQ SCI HPET or PIRQx 4 18012 by means of SERIRQ PIRQx or mouse emulation 5 6 PIRQx or IRQ14 from SATA Controller 7 IRQ15 by means of SERIRQ or PIRQx or IRQ15 from SATA Controller The SoC cascades the slave controller onto the master controller through master controller interrupt input 2 This means there are only 15 possible interrupts for the SoC PIC Interrupts can be programmed individu
215. esistance 40 60 2 IL Leakage Current 10 10 Pad Capacitance 9 pF 4 Pin Capacitance 10 Pull down Impedance 35 50 70 Notes 1 V1P8A G3refers to instantaneous voltage 55 SENSE 2 Measured at 0 31 GPIO 1 3 between and 1 4 CPAD includes die capacitance only No package parasitic included Figure 21 4 Definition of VHYS the DDR L Interface Timing Specification max VIH min Vin Datasheet Volume 1 of 3 241 intel 21 6 15 DC Specification Table 21 36 GPIO 1 8V Core Well Signal Group DC Specification Electrical Specifications Symbol Parameter Min Typ Max Units Notes VREF Voltage GPIO_V1P8A_G3 V Input High Voltage 0 65 VREF V Vit Input Low Voltage 0 35 VREF V Output High Voltage Vref 0 45 VREF V VoL Output Low Voltage 0 45 V Vuys Input Hysteresis 0 1 V IL Leakage Current 2 2 mA Load Capacitance 2 75 21 6 16 SIO SPI DC Specifications Table 21 37 SIO SPI DC Specifications Symbol Parameter Min Units Notes VREF T O Voltage GPIO 1P8A G3 V 3 Input High Voltage 0 65 VREF V 2 Vit Input Low Voltage 0 5 0 35 VREF V 2 Output High Voltage 0 45 1 8V V 1 VoL Output Low Voltage
216. essor 256KB Data Code RAM accessible only to the Intel 128KB On Chip Mask ROM for storage of Intel TXE code Inter Processor Communication for message passing between the Host Processor and Intel TXE e 64 byte input and output command buffers e 256 byte shared payload enables 2048 bit keys to be exchanged as part of the command Multiple context DMA engine to transfer data between Host Processor address domain System memory and the Intel TXE programmable by the Intel TXE processor only Hardware Accelerators e DES 3DES ECB CBC 128b ABA key for 3DES Key Ladder Operations Three AES engines Two fast 128 and one slow 128 256 e Exponentiation Acceleration Unit EAU for modular exponentiation modular reduction large number addition subtraction and multiplication SHA1 SHA256 384 512 MD5 88 Datasheet Volume 1 of 3 111 tel Intel Trusted Execution Engine Intel TXE 112 Datasheet Volume 1 of 3 a Intel High Definition Audio Intel HD Audio tel 14 Intel High Definition Audio Intel HD Audio The Intel High Definition Audio Intel HD Audio is an architecture and infrastructure to support high quality audio implementations for PCs The Intel High Definition Audio Intel HD Audio controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and internal external codecs The controll
217. etween P States a significant number of transitions per second are possible Thermal Monitor mode Refer to Chapter 6 Thermal Management 6 3 2 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following condition e The CO timer that tracks continuous residency in the Normal state has not expired This timer is cleared during the first entry into Deeper Sleep to allow consecutive Deeper Sleep entries to shrink the L2 cache as needed The predefined L2 shrink threshold is triggered Datasheet Volume 1 of 3 61 m e n tel Power Management 6 3 3 1 Figure 6 1 62 Low Power Idle States When the processor core is idle low power idle states C States are used to save power More power savings actions are taken for numerically higher C State However higher C States have longer exit and entry latencies Resolution of C State occur at the thread processor core and processor core level Clock Control and Low Power States The processor core supports low power states at core level The central power management logic ensures the entire processor core enters the new common processor core power state For processor core power states higher than C1 this would be done by initiating a LVLx LVLA and P LVL6 I O read to all of the cores States that require external intervention and typically map back t
218. evise RR DER DOE ran IUDICUM RE RIT 61 6 5 Processor Core States Support issida aae a aa PRETI RE ax da ER CRY 63 6 6 Coordination of Core Module Power States at the Package 2 65 7 1 Memory Channel 0 DDR3L Signals 1 1 69 7 3 Supported DDR3L DRAM eren hn csc DE NER RR PE ERR 70 7 4 Supported DDR3L Memory Size Per 1 1 1 eese 70 7 2 OtheriMMemory DDR3L Signals rre urere ke ced 70 8 1 Display Technologies 4 6 senem 72 8 2 SOC Display Config FatiOD eite pone Ene x ripe xke taken an aan e NN AN xa 72 8 3 SoC Display supported Resolutions 444 1 1 4 4 41 eee eee nens 73 8 4 Hardware Accelerated Video Decode Encode Codec 78 8 5 Resolution Details on Supported HW Accelerated Video Decode Encode Codec 78 9 1 CST Signal E 81 9 2 GPIO 519 e R MR 81 9 3 Imaging 82 10 1 ciere 91 10 2SDIO Signals me cee ohne ze d Pd
219. f RSMRST is low RSM I CMOS V3P3 Resume Well Reset Used for resetting the resume well An external RC circuit is required to guarantee that the resume well power is valid prior to this signal going high 16 9 2 Features The Real Time Clock RTC module provides a battery backed up date and time keeping device Three interrupt features are available time of day alarm with once a second to once a month range periodic rates of 122 500 ms and end of update cycle notification Seconds minutes hours days day of week month and year are counted The hour is represented in twelve or twenty four hour format and data can be represented in BCD or binary format The design is meant to be functionally compatible with the Motorola MS146818B The time keeping comes from a 32 768 KHz oscillating source which is divided to achieve an update every second The lower 14 bytes on the lower RAM block have very specific functions The first ten are for time and date Datasheet Volume 1 of 3 161 m Platform Controller Unit PCU Overview 16 9 2 1 16 9 3 16 9 3 1 16 9 3 2 16 9 3 2 1 Note 162 information The next four 0Ah to ODh are registers which configure and report RTC functions A host initiated write takes precedence over a hardware update in the event of a collision Update Cycles An update cycle occurs once a second if the B SET bit is not asserted and the d
220. f interrupts The polling interrupt service routine can call the appropriate service routine instead of providing the interrupt vectors in the vector table In this mode the INTR output is not used and the microprocessor internal Interrupt Enable flip flop is reset disabling its interrupt input Service to devices is achieved by software using a Poll command The Poll command is issued by setting OCW3 PMC The PIC treats its next I O read as an interrupt acknowledge sets the appropriate ISR bit if there is a request and reads the priority level Interrupts are frozen from the OCW3 write to the I O read The byte returned during the I O read contains a 1 in Bit 7 if there is an interrupt and the binary code of the highest priority level in Bits 2 0 Edge and Level Triggered Mode ISA systems this mode is programmed using ICW1 LTIM which sets level or edge for the entire controller In the SoC this bit is disabled and a register for edge and level triggered mode selection per interrupt input is included This is the Edge Level control Registers ELCR1 and ELCR2 If an ELCR bit is 0 an interrupt request will be recognized by a low to high transition on the corresponding IRQ input The IRQ input can remain high without generating another interrupt If an ELCR bit is 1 an interrupt request will be recognized by a high level on the corresponding IRQ input and there is no need for an edge detection The interrupt request must be removed befo
221. f operation Total drive current of the transmitter when it is shorted to its ground All DisplayPort Main Link lanes as well as AUX CH must be AC coupled AC coupling capacitors must placed on the transmitter side Placement of AC coupling capacitors on the receiver side is optional Signal DC Specification Table 21 14 DDC Signal DC Specification DCC DATA DDC CLK Table 21 15 230 Symbol Parameter Min Units Notes VREF Voltage MIPI_V1P8_S4 V Input High Voltage 0 65 VREF V 1 Input Low Voltage 0 35 VREF V 2 VoL Output Low Voltage 0 4 V 3 Jj Input Pin Leakage 30 30 4 Notes 1 defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 vis defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low 3 ink current 4 For VIN between OV and CORE Measured when driver is tri stated DDC Miscellaneous Signal DC Specification HPD BKLTCTL VDDEN BKLTEN Symbol Parameter Min Typ Max Units Notes VREF Voltage MIPI_V1P8_S4 V Input High Voltage 0 65 VREF 1 Vit Input Low Voltage 0 0 35 VREF V 2 Zpu Pull up Impedance 40 50 60 3 2 Pull down Impedance 40 50 60 3 Ij Input Pin Leakage 20 20 4 Notes 1 defined as th
222. f the clock For the PSP format the Idle and Disable modes of the 25 DATAOUT I2Sx CLK and I2Sx FRM are programmable by means of the SSPSP ETDS SSPSP SCMODE and SSPSP SFRMP bits When Transmit data is ready the 25 CLK will remain in its Idle state for the number of serial clock 125 CLK clock periods programmed within the Start Delay SSPSP STRTDLY field 125 will then start toggling 125 DATAOUT will remain in the idle state for the number of cycles programmed within the Dummy Start SSPSP DMYSTRT field 25 FRM signal will be asserted after the number of half clocks programmed in the SSPSP SFRDLY field The I2Sx FRM signal will remain asserted for the number of clocks programmed within the SSPSP SFRMWDTH then de assert Four to 32 bits can be transferred per frame Once the last bit LSB is transferred the 25 CLK will continue toggling based off the Dummy Stop SSPSP DMYSTOP field 25 DATAOUT either retains the last value transmitted or is forced to zero depending on the value programmed within the End of Transfer Data State SSPSP ETDS field when the controller goes into Idle mode unless the Enhanced SSP port is disabled or reset which forces 25 DATAOUT to zero With the assertion of 125 Receive data is simultaneously driven from the peripheral 25 DATAIN most significant bit first Data transitions on 125 based on the Serial Clock Mode selected and is sampled by t
223. fer back and forth between the master CCI and a Slave CCI Unit Figure 9 3 MIPI CSI Bus Block Diagram Unidirectional High Device e g an application engine Speed Data Link or base band containing the CSI receiver and the master Device e g a Camera containing the CSI transmitter and CCI slave N Data Lanes Where N may be 1 2 3 ord CSI Receiver DataN DataN DataN DataN CSI Transmitter Data1 Data1 Data1 Data1 Clock Clock Clock Slave 400kHz Bidirectional Master Control Link SCL SCL SDA SDA D PHY data lane signals are transferred point to point differentially using two signal lines and a clock lane There are two signaling modes a high speed mode that operates up to 1500Mbs and a low power mode that works at 10Mbs The mode is set to low power mode and a stop state at start up power up Depending on the desired data transfer type the lanes switch between high and low power modes The CCI interface consists of an 12 bus that has a clock line and a bidirectional data line 87 Datasheet Volume 1 of 3 9 4 1 88 intel MIPI CSI Camera Serial Interface and ISP The MIPI CSI 2 devices operate in a layered fashion There are 5 layers identified at the receiver and transmitter ends MIPI CSI 2 Functional Layers PHY Layer An embedded electrical layer sends and detects start of packet signalling and end of packet signalling on the data
224. ffect since no power pressed Not latched nor detected so PMU_PWRBTN held Unconditional transition to S5 state No dependence on processor or S4 low for at least 4 any other subsystem consecutive seconds Power Button Override Function If PMU_PWRBTN is observed active for at least four consecutive seconds the state machine should unconditionally transition to the S5 state regardless of present state S0 S4 even if the CORE PWROK is not active In this case the transition to the G2 S5 state should not depend on any particular response from the processor nor any similar dependency from any other subsystem The PWRBTN status is readable to check if the button is currently being pressed or has been released The status is taken after the debounce and is readable using the GEN PMCON2 PWRBTN LVL bit Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel Note Note 16 2 2 2 2 16 2 2 2 3 16 2 2 2 4 Note 16 2 2 3 Note The 4 second PMU_PWRBTN assertion should only be used if a system lock up has occurred The 4 second timer starts counting when the SoC is in a SO state If the PMU PWRBTN Z signal is asserted and held active when the system is in a suspend state S4 the assertion causes a wake event Once the system has resumed to the SO state the 4 second timer starts During the time that the 5 54 signal is stretched for the minimum assertion width if
225. ffers continuously at maximum sensor resolution This adds a round trip to memory for every frame and increases the bandwidth requirements Secondary Camera Still Image Resolution Maximum secondary camera still image resolution is 4 megapixel at 15 fps Primary Camera Video Resolution Maximum primary camera video resolution is 1080p30 Maximum primary camera dual video resolution is 1080p30 Secondary Camera Video Resolution Maximum secondary camera video resolution is 1080p30 Bit Depth Capable of processing 14 bit images at the stated performance levels Capable of processing 18 bit images at half the performance levels that is process on the fly 16 megapixel 18 bit images at 7 fps instead of 15 fps Capable of processing up to 18 bit precision The higher precision processing will be employed mainly for high dynamic range imaging HDR Datasheet Volume 1 of 3 83 m e MIPI CSI Camera Serial Interface and ISP 9 2 Imaging Subsystem Integration Figure 9 2 Image Processing Components xt data x3 data Stereo Configurations Camera Peripherals EE 9 2 1 Processor Core The processor core augments the signal processing capabilities of the hardware to perform post processing on images such as auto focus auto white balance and auto exposure The processor also runs the drivers that control the GPIOs and 12 for sensor control 9 2 2 Imaging Signal Proces
226. firmware should program the trip values prior to enabling the trip point Platform Trips PROCHOT The platform components use the signal PROCHOT to indicate thermal events to SoC Assertion of the PROCHOT input will trigger Thermal Monitor 1 or Thermal Monitor 2 throttling mechanisms if they are enabled EXTTS The SoC does not support external thermal sensors and the corresponding bits in the P unit registers will be reserved for future use if needed For SoC PROCHOT is the only mechanism for a platform component to indicate Thermal events to the P unit Datasheet Volume 1 of 3 57 n tel Thermal Management 5 7 58 SVID When the Voltage Regulator VR reaches its threshold VR Icc Max VR Hot status bits in SVID are set SVID sends SVID Status message to P unit Dynamic Platform Thermal Framework DPTF The SoC is required to support interface for OS level thermal drivers and Intel s DPTF Dynamic Platform and Thermal Framework drivers to control thermal management This interface provides high level system drivers a mechanism to manage thermal events within the SoC with respect to events outside SoC These events could potentially be triggered before PM Unit firmware performs active management as DPTF OS level drivers respond to events on platform outside of SoC In addition these interfaces also respond to interrupts from within the SoC Thermal Status The firmware captures Thermal Trip events othe
227. first internally generated INTA pulse the highest priority ISR bit is set and the corresponding IRR bit is reset On the trailing edge of the first pulse a slave identification code is broadcast by the master to the slave on a private internal three bit wide bus The slave controller uses these bits to determine if it must respond with an interrupt vector during the second INTA pulse Upon receiving the second internally generated INTA pulse the PIC returns the interrupt vector If no interrupt request is present because the request was too short in duration the PIC returns vector 7 from the master controller This completes the interrupt cycle In AEOI mode the ISR bit is reset at the end of the second INTA pulse Otherwise the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine 16 15 1 2 Initialization Command Words ICWx Before operation can begin each 8259 must be initialized In the SoC this is a four byte sequence The four initialization command words are referred to by their acronyms ICW1 ICW2 ICW3 and ICW4 The base address for each 8259 initialization command word is a fixed location in the I O memory space 20h for the master controller and AOh for the slave controller Datasheet Volume 1 of 3 181 m Platform Controller Unit PCU Overview 16 15 1 2 1 16 15 1 2 2 16 15 1 2 3 16 15 1 2 4 16 15 1 3 182 ICW1 A write
228. ge contrast brightness and other attributes 3 A corresponding decrease to the backlight brightness is applied simultaneously to produce an image with similar user perceived quality such as brightness as the original image Intel DPST 5 0 has improved the software algorithms and has minor hardware changes to better handle backlight phase in and ensures the documented and validated method to interrupt hardware phase in Intel Automatic Display Brightness The Intel Automatic Display Brightness feature dynamically adjusts the backlight brightness based upon the current ambient light environment This feature requires an additional sensor to be on the panel front The sensor receives the changing ambient light conditions and sends the interrupts to the Intel Graphics driver As per the change in Lux current ambient light illuminance the new backlight setting can be adjusted through BLC The converse applies for a brightly lit environment Intel Automatic Display Brightness increases the back light setting Datasheet Volume 1 of 3 inte 6 3 9 6 4 6 4 1 6 4 2 6 4 2 1 Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology When a Local Flat Panel LFP supports multiple refresh rates the Intel Seamless Display Refresh Rate Switching Technology Intel SDRRS Technology power conservation feature can be enabled The higher refresh rate will be used when on plugged in power or when the
229. ge operating point Deep Power Down Prior to entering the Deep Power Down Technology code named C6 State The core process will flush its cache and save its core C6 context to a special on die SRAM on a different power plane Once Deep Power Down Technology code named C6 sequence has completed The core processor s voltage is completely shut off C7 Execution cores in this state behave similarly to the C6 state Voltage is removed from the system agent domain The following state descriptions are based on the assumption that both threads are in the common low power state Core CO State The normal operating state of a core where code is being executed Core 1 1 State 1 1 is low power state entered when a core execute HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Intel 64 and IA 32 Architecture Software Developer s Manual Volume 3A 3B System Programmer s Guide for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E see Section 6 3 5 2 Package C1 C1E State on page 65 Core C6 State Individual core can enter the C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 the core will save its architectural state to a dedicated SRAM Once complete a core will have its vo
230. get is 4V ns CMD CTL buffer Ron is 20 Ohms and SR target is 1 8V ns Symbol Parameter Min Units Notes Supply Voltage Veus High power Port 4 75 5 2 VBus Low power Port 4 20 5 V Supply Current Iccprt High power Hub Port out 500 mA Iccupt Low power Hub Port out 100 Iccupr High power Function in 500 mA Icci pr Low power Function in 100 mA Unconfigured Function Hub 100 Suspended High power Device 2 5 15 Suspended Low power Device 500 HA Datasheet Volume 1 of 3 235 intel Table 21 24 USB 2 0 Host DC Specification Sheet 2 of 3 236 Electrical Specifications Symbol Parameter Min Typ Max Units Notes Input Levels for Low Full speed High driven 2 0 V 4 High floating 2 7 3 6 4 Vit Low 0 8 4 Differential Input Sensitivity D D Vor 0 2 V 1 Figure See Note 4 Differential Common Mode Range Includes VDI VcM 0 8 2 5 V range Figure See Note 4 Input Levels for High speed High speed squelch detection Vussq threshold differential signal 100 150 amplitude High speed disconnect detection Vuspsc threshold differential signal 525 625 mV amplitude High speed differential input signaling _
231. gh Precision Event Timers Specification Revision 1 0a http www intel com hardware design hpetspec 1 pd Memory Mapped Registers The register space is memory mapped to 1K block at address 00000 All registers are in the core well Accesses that cross register boundaries result in undefined behavior PCU iLB GPIO The processor SoC contains 4 GPIO controllers that interact with the operating system by means of the BIOS ACPI Firmware A GPIO Controller driver and MSFT GPIO framework provides the GPIO I O services interrupt services and event handling mechanism Datasheet Volume 1 of 3 Platform Controller Unit PCU Overview n tel Figure 16 4 GPIO Stack Block Diagram Camera Driver User Mode Device drivers x y z 10 REQUEST 10 REQUEST 2NDRY INT Win GPIO Framework extension GPIOC x lt GPIO SOUTHWEST CTRL Driver GPIO NORTH GPIO SOUTHEAST CTRL Driver CTRL Driver GPIO EAST CTRL Driver O REG ACCESS gt Shared GPIO INT Direct GPIO INT IO REQUEST e MMO REG ACCESS Datasheet Volume 1 of 3 171 m Platform Controller Unit PCU Overview 16 12 1 16 12 2 Note 16 12 3 172 Signal Description See Chapter 2 Physical Interfaces for additional details The signal description table has the following headings e Signal Name The name
232. gister to the Vector set for each interrupt RTE VCT interrupts that match this vector will have their RTE RIRR register cleared All other EOI register bits are ignored Indirect I O APIC Registers These registers are selected with the IDX register and read written through the WDW register Accessing these registers must be done as DW requests otherwise unspecified behavior will result Software should not attempt to write to reserved registers Reserved registers may return non zero values when read There is one pair of redirection RTE registers per interrupt line Each pair forms a 64 bit RTE register Specified offsets should be placed in IDX not added to IDX Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel 16 15 Figure 16 8 16 15 1 Note Table 16 32 PCU iLB 8259 Programmable Interrupt Controllers PIC The SoC provides an ISA compatible programmable interrupt controller PIC that incorporates the functionality of two cascaded 8259 interrupt controllers Platform Control Unit 8259 Programmable Interrupt Controllers Features In addition to providing support for ISA compatible interrupts this interrupt controller can also support PCI based interrupts PIRQs by mapping the PCI interrupt onto a compatible ISA interrupt line Each 8259 controller supports eight interrupts numbered 0 7 Table 16 32 shows how the controllers are connected The SoC do
233. gnals Sheet 2 of 2 Default Buffer State 2 2 8 Table 2 12 High Speed UART Interface Signals High Speed UART Interface Signals Signal Name Dir Platform Pwrgood Assert Resetout 9 State De assert State GPIOMV HS SDMMC1_RCOMP yo V1P8A OME 7 7 SDMMC2_D 2 0 1 0 V1P8A GPIOMV HS Z 20K PU Z 20K PU SDMMC2 D 3 CD 10 GPIOMV HS Z 20K PU Z 20K PU SDMMC2_CMD 1 0 GPIOMV HS Z 20K PU Z 20K PU SDMMC2_CLK yo GRIOMV HS 0 20K PD 0 SDMMC3 D 3 0 yo eed GPIOHV HS Z 20K PU Z 20K PU SDMMC3_CMD yo GPIOHV HS Z 20K PU Z 20K PU SDMMC3_PWREN_N 1 0 5 1 20K PD 1 GPIOHV HS SDMMC3 CLK yo HV 0 20K PD 0 GPIOHV HS SDMMC3_RCOMP yo do 7 2 SDMMC3 1 8 1 0 5 0 20K PD 0 Input Input SDMMC3 CD N 1 0 V1P8A GPIOMV MS 20K BU 20K PU Default Buffer State Signal Name Dir jose Type De assert tate UART1_RXD V1P8A GPIOMV MS Input 20K PU Input 20K PU UART1_TXD V1P8A GPIOMV MS 1 20K PU 1 RTS V1P8A GPIOMV MS 1 20K PU 1 UARTi CTS V1P8A GPIOMV MS Input 20K PU Input 20K PU UART2 RXD I O V1P8A GPIOMV MS Input 20K PU Input 20K PU UART2 TXD V1P8A GPIOMV MS 1 20K PU 1 UART2 RTS N V1P8A GPIOMV MS 1 20K PU 1 UA
234. go to a sleep state If the system is already in a sleep state this signal will cause a wake event If I the signal is pressed for more than 4 seconds this will cause PMU_PWRBTN CMOS V1P8 an unconditional transition power button override to the S5 state Override will occur even if the system is in the S4 states This signal has an internal pull up resistor and has an internal 16 ms debounce on the input I System Reset This signal forces an internal reset after being PMU_RESETBUTTON CMOS V1P8 debounced PMU_SLP_S4 S4 Sleep Control This signal is for power plane control It cmos viPg be used to control system power when it is in a S4 Suspend to Disk or S5 Soft Off state PMU_SLP_S3 S3 Sleep Control This signal is for power plane control It cmos viPg 2 be used to control system power when it is a 53 Suspend To RAM S4 Suspend to Disk or S5 Soft Off states PMU_SUS_STAT Suspend Status This signal is asserted by the SoC to indicate that the system will be entering a low power state soon This be monitored by devices with memory that CMOS V1P8 need to switch from normal refresh to suspend refresh mode It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered off planes PMU_SUSCLK Suspend Clock This 32 KHz clock is an output of the CMOS 1 8 generator circuit for use by other chips for refresh clock PMU SUSPWRDN
235. grammable Serial Protocol 108 Intel Trusted Execution Engine Intel 111 13 1 EEEJ i 111 13 1 1 Security Feat le s 111 13 1 1 1 Hardware Accelerators 111 Intel High Definition Audio Intel HD 2 2 2 113 14 1 Signal Descriptions eei eem electives 114 114 14 3 References BR E EU re RI aa 114 Serial I O SIO Overview eode exe edi 115 15 21 Register a E a 115 15 2 SIO Serial Peripheral Interface 5 80 a 115 15 2 1 Signal Descriptions eet rd rt ei ee Saeed da EN ax TER Ex Xa e 115 15 2 1 1 Clock Phase and Polarity essere enn nnne nnn nri 115 15 25 SIO I C Interface pe RE dM e n 116 Datasheet Volume 1 of 3 15 23 Signal Descriptions rsen E 116 15 2 4 5 M 117 denda RR LEER RARUS Od RR M 117 15 2 4 12 Modes pet eror bad 117 15 2 4 3 Functional Description eiecit dare rna da t
236. he SSP consists of four pins that are used to transfer data between the SoC and external audio codecs modems or other peripherals Although four serial data formats exist each has the same basic structure and in all cases the following pins are used in the following manner 25 CLK Defines the bit rate at which serial data is driven onto and sampled from the port I2Sx_FRM Defines the boundaries of a basic data unit comprised of multiple serial bits 25 DATAIN The serial data path for received data from system to peripheral 25 DATAOUT The serial data path for transmitted data from peripheral to system A data frame can contain from 4 to 32 bits depending on the selected format Serial data is transmitted most significant bit first The Programmable Serial Protocol PSP format is used to implement 125 Master and Slave modes are supported When driven by the Enhanced SSP the 125 CLK only toggles during active transfers not continuously unless ECRA ECRB functions are used When the I2Sx CLK is driven by another device it is allowed to be either continuous or only driven during transfers but certain restrictions on PSP parameters apply Datasheet Volume 1 of 3 107 12 6 5 1 108 tel Low Power Engine LPE for Audio 125 Normally the serial clock 125 if driven by the Enhanced SSP Port only toggles while an active data transfer is underway There are several cond
237. he controller on the opposite edge When the Enhanced SSP is a master to the frame synch 125 FRM and a slave to the clock 125 then at least three extra clocks 125 CLKs will be needed at the beginning and end of each block of transfers to synchronize control signals from the APB clock domain into the SSP clock domain a block of transfers is a group of back to back continuous transfers Datasheet Volume 1 of 3 Low Power Engine LPE for Audio 126 n tel Figure 12 4 Programmable Serial Protocol Format SSPSP SCMODE 00 01 25 CLK 10 11 125 DATAOUT 125 DATAOUT SSPSP SFRMP 1 DSxFRM p P SSPSP SFRMP 0 N y Note When in PSP format if the SSP is the master of the clock 125 CLK is an output and the SSPSP ETDS bit is cleared the End of Transfer Data State for the 25 DATAOUT line is 0 If the SSP is the master of the clock and the SSPSP ETDS bit is set the 25 DATAOUT line remains at the last bit transmitted LSB If the SSP is a slave to the clock 125 CLK is an input and modes 1 or 3 are used the ETDS can only change from the LSB if more clocks 125 are sent to the SSP that is dummy stop clocks or slave clock is free running Figure 12 5 Programmable Serial Protocol Format Consecutive Transfers SSPSP SCMODE PULL Le I 1 DATAOUT s
238. he start frame and the interrupt controller completes it These modes are entered by means of the length of the stop frame Continuous mode must be entered first to start the first frame This start frame width is 8 LPC clocks This is a polling mode In Quiet mode the LPC SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a peripheral drives SERIRQ low The interrupt controller senses the line low and drives it low for the remainder of the Start Frame Since the first LPC clock of the start frame was driven by the peripheral the interrupt controller drives SERIRQ low for 1 LPC clock less than in continuous mode This mode of operation allows for lower power operation 16 8 2 7 3 Frames Once the Start frame has been initiated the LPC SERIRQ peripherals start counting frames based on the rising edge of SERIRQ Each of the IRQ DATA frames has exactly 3 phases of 1 clock each Sample Phase During this phase a device drives LPC SERIRQ low if its corresponding interrupt signal is low If its corresponding interrupt is high then the LPC SERIRQ devices tri state LPC SERIRQ LPC SERIRQ remains high due to pull up resistors Recovery Phase During this phase a device drives SERIRQ high if it was driven low during the Sample Phase If it was not driven during the sample phase it remains tri stated in this phase Tu
239. hecks the previous frame for motion and compensates for it appropriately Auto Exposure AE Auto Focus AF and Auto White Balance AWB together known as 3A are implemented in the processor to provide flexibility Video Capture During video recording the ISP can capture video up to 1080p 30 fps and output preview frames concurrently The ISP outputs video frames to memory YUV420 or YUV422 format ISP Overview The Camera Subsystem consists of 2 parts the hardware subsystem and a software stack that implements the ISP functionality on top of this hardware The core of the ISP is a vector processor Datasheet Volume 1 of 3 m MIPI CSI Camera Serial Interface and ISP n tel 9 4 MIPI CSI 2 Receiver MIPI CSI 2 devices are camera serial interface devices They are categorized into two types a CSI transmitter device with Camera Control Interface CCI slave and CSI receiver device with CCI master Data transfer by means of MIPI CSI is unidirectional that is from transmitter to receiver CCI data transfer is bidirectional between the CCI slave and master Camera Serial Interface Bus CSI is a type of serial bus that enables transfer of data between a Transmitter device and a receiver device The CSI device has a point to point connections with another CSI device by means of D PHYs and as shown in Figure 9 3 Similarly CCI Camera Control Interface bus is a type of serial bus that enables trans
240. hich is the most significant bit MSB of the Serial Line Control register affects the selection of certain of the UART registers The LCR DLAB register bit must be set high by the system software to access the Baud Rate Generator Divisor Latches Register Map Table 16 11 Register Access List Register Address Register Offset to Base sem 2 Access Register Accessed IO Address Type Oh Ob RO Receiver Buffer Oh Ob wo Transmitter Holding Oh 1b RW Divisor Latch LSB Lowest Significant Bit ih Ob RW Interrupt Enable ih 1b RW Divisor Latch MSB Most Significant Bit 2h xb RO Interrupt Identification 2h xb FIFO Control 3h xb RW Line Control 4h xb RW Modem Control 5h xb RO Line Status 6h xb RO Modem Status 7h xb RW Scratchpad Notes 1 These registers consolidated in the Receiver Buffer Transmitter Holding Register 1 BUFFER 2 These registers are consolidated in the Interrupt Enable Register COM1 IER 3 These registers are consolidated in the Interrupt Identification FIFO Control Register COM1 IIR 4 These registers are implemented but unused since the UART signals related to modem interaction are not implemented Datasheet Volume 1 of 3 141 m Platform Controller Unit PCU Overview PCU System Management Bus SMBus The SoC provides a System Management Bus SMBus 2 0 host controller The Host controller
241. ible Color dithering diffuses the sharp color bands seen on smooth shaded objects VED Video Encode Decode The video engine is part of the Intel Processor Graphics for image processing play back and transcode of Video applications The Processor Graphics video engine has a dedicated fixed hardware pipe line for high quality decode and encode of media content This engine supports Full Hardware acceleration for decode of AVC H 264 VC 1 and MPEG2 contents along with encode of MPEG2 and AVC H 264 apart from various video processing features The new Processor Graphics Video engine adds support for processing features such as frame rate conversion image stabilization and gamut conversion Datasheet Volume 1 of 3 77 Graphics Video Display 8 4 1 Features The features for the video decode hardware accelerator in SoC are VED core can be configured on a time division multiplex basis to handle single dual and multi stream HD decoding encoding e VED provides full hardware acceleration and below Media formats is supported as follow Table 8 4 Hardware Accelerated Video Decode Encode Codec Support 8 1 Win7 Open Source Linux Codec Format Decode Level Encode Level Decode Level Encode Level Decode Level Encode Level Supported Supported HEVC H 265 Hybrid Not Supported Hybrid Not Supported Not Supported Not Supported solution solution H 264 Supported Su
242. ification iioii ies eene e tee tendu na gonna dea ran xxn 235 USB HSIC DC Specification esee eene nnn 237 USB 3 0 0 5 ipu de RE xx SERE eaae ARES RENS ERES 238 LPC DG SpedcifiCatlOn uie vane tke esa Cadena dk ec C nk a NR 238 PCU SPI DG SpecifiCatiOr 239 Power Management Thermal PMC and RTC DC Specification 239 SVID DC SPeCifiCation Iden gebe Ex Ee dA REPERTA A ERA RARE 241 GPIO 0 rate ar anas erae 242 SIO SPI DC Specifications eiut 242 SIO I C DC Specification 242 SIO UART Specification ia ca 243 126 Audio DC Specification 243 High Definition Audio DC 243 SMBus System Management DC 244 PCI Express DC Specification 0 menn 244 Serial ATA SATA DC Specification 244 Datasheet Volume 1 of 3 Figures 1 1 SoC Block Diagram NetboOk i eene n e rp Ca REA 18 5 1 DIS Mode
243. iguration and may require enabled hardware software or service activation Learn more at intel com or from the OEM or retailer All information provided here is subject to change without notice Contact your Intel representative to obtain the latest Intel product specifications and roadmaps Copies of documents which have an order number and are referenced in this document may be obtained by calling 1 800 548 4725 or visit www intel com design literature htm I2C is a two wire communications bus protocol developed by NXP SMBus is a subset of the I2C bus protocol and was developed by Intel Implementations of the I2C bus protocol may require licenses from various entities including NXP Semiconductors N V Intel amp 64 architecture requires a system with a 64 bit enabled processor chipset BIOS and software Performance will vary depending on the specifichardware and software you use Consult your PC manufacturer for more information For more information visit http www intel com content www us en architecture and technology microarchitecture intel 64 architecture general html Intel Virtualization Technology Intel VT requires a computer system with an enabled Intel processor BIOS and virtual machine monitor VMM Functionality performance or other benefits will vary depending on hardware and software configurations Software applications may not becompatible with all operating systems Consult your PC manufacturer For more information
244. in Name Y50 VSS T48 MCSI_3_CLKN CX_PREQ_N Y9 VSS M48 MCSI 2 DP 1 PRDY AC27 VSS SENSE P47 MCSI 2 DP 0 COREPWROK AD22 UNCORE VSS SENSE M47 MCSI 2 DN 1 RSVD AD24 DDI SENSE P45 MCSI 2 DIFF 035 USB VDDQ G3 P50 MCSI 2 CLKP DIFF P 2 V35 USB VDDQ G3 48 MCSI 2 CLKN DIFF P 1 B22 USB V3P3A G3 T41 MCSI 1 DP 3 DIFF P 0 C23 USB V3P3A G3 V50 MCSI 1 DP 2 RSVD AA29 USB 1 V45 MCSI 1 DP 1 CLK DIFF N 3 AA30 RSVD Y47 MCSI 1 DIFF N 2 AA32 VCCSRAMSOCIUN 1P05 T42 MCSI 1 DN 3 DIFF N 1 AA33 VCCSRAMSOCIUN 1 05 V48 MCSI 1 DN 2 CLK DIFF N 0 AA35 VCCSRAMSOCIUN 1P05 V47 MCSI 1 DN 1 RTC EXTPAD AA36 VCCSRAMSOCIUN 1P05 Y48 MCSI 1 RTC X2 AC32 VCCSRAMSOCIUN 1P05 RTC X1 V33 VCCSRAMSOCIUN_1P05 Datasheet Volume 1 of 3 3 8 209 n tel Ball Map Ball Out and SoC Pin Locations 210 Datasheet Volume 1 of 3 m e Package Information n tel 20 Package Information The SoC comes in a 27 mm x 25 mm Flip Chip Ball Grid Array FCBGA package and consists of a silicon die mounted face down on an organic substrate populated with 1170 solder balls on the bottom side Capacitors may be placed in the area surrounding the die Because the die side capacitors are electrically conductive and only slightly shorter than the die height care should be taken to avoid contacting the capacitors with electrically co
245. ing the counter s programmed mode Counting is affected as described in the mode definitions The new count must follow the programmed count format If a counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same counter Otherwise the counter will be loaded with an incorrect count The Control Word Register at port 43h controls the operation of all three counters Several commands are available Control Word Command Specifies which counter to read or write the operating mode and the count format binary or BCD Counter Latch the current count so that it can be read by the system The countdown process continues Read Back Command Reads the count value programmed mode the current state of the OUT pins and the state of the Null Count Flag of the selected counter Table 16 28 lists the six operating modes for the interval counters Table 16 28 Counter Operating Modes 16 10 3 2 16 10 3 2 1 166 Mode Function Description 0 Out signal on end of count 20 Output is 0 When count goes to 0 output goes to 1 and stays at 1 until counter is reprogrammed 1 Hardware re triggerable one shot Output is 0 When count goes to 0 output goes to 1 for one clock time 2 Rate generator divide by n counter Output is 1
246. ion Version 1 4b HDCP High bandwidth Digital Content Protection System HDCP Revision 1 4 Notes HDMI DP and eDP 1 SoC display interfaces are designed per specifications provided in industry standard listed above For specifications of each technology refer to the correspondent standard and follow guidance provided 2 The SoC supports High Definition Content Protection Technology HDCP on all supported wired displays SoC Display Configuration Sheet 1 of 2 Feature eDP DP HDMI DVI Number of Ports Maximum Resolution 2 DDI 0 1 2x4 Q2 7 Gb s 2560x1440 60Hz 3 DDI 0 2 2x4 Q2 7 Gb s 3840x2160 30Hz 2560x1600 60Hz 3 DDI 0 2 2x4 92 97 Gb s 3840 2160 30Hz 2560x1600 60Hz buffer in Panel 24bpp 24bpp 24bpp Minimum Resolution none none 480i 576i Data Rate 10 8Gb s 10 8Gb s 6 6 Gb s Standard eDP1 4 DP1 1a HDMI1 4b Power gated during display off Yes Yes Yes DRRS Refresh reduction Yes Panel command N A N A Self Refresh with Frame No No No Datasheet Volume 1 of 3 Graphics Video and Display Table 8 2 Table 8 3 8 2 1 intel SoC Display Configuration Sheet 2 of 2 Feature eDP DP HDMI DVI Content Based backlight control DPST6 CABC N A N A HDCP wired display N A ASSR support 1 4 1 4 PAVP AES encrypted buffer plane control panic attack SEC
247. is indicates that the system has not locked up Interrupts SMI The SoC SMBus controller uses INTB as its virtual interrupt wire However the system can alternatively be set up to generate SMI instead of an interrupt by setting the SMB_Config_HCFG SMI_EN bit Datasheet Volume 1 of 3 Platform Controller Unit Overview intel The following tables specify how the various enable bits in the SMBus function control the generation of the interrupt and Host SMI internal signals The rows in the tables are additive which means that if more than one row is true for a particular scenario then the Results for all of the activated rows will occur Table 16 14 Enable for PCU ALERTZ Table 16 15 SMB Mem SMB Mem SMB Config m Event HCTL INTREN HCFG SMI_EN esum SMB ALERT X 1 0 Slave SMI generated asserted low always SMBUS SMI STS reported in SMB Mem 1 0 0 Interrupt generated HSTS SMBALERT Enables for SMBus Host Events SMB Mem SMB Config Event HCTL INTREN HCFG SMI EN Event Any combination of 0 X None SMB HSTS FAILED 1 0 Interrupt generated SMB HSTS BERR 5 Mem HSTS Host SMI generated DEVERR 1 1 SMB HSTS INTR asserted Table 16 16 Enables for the Host Notify Command SMB Mem SMB Config SMB Mem SCMD HNINTREN HCFG SMI EN SCMD HNWAKEEN Result 0 X 0 None 1 0 X Interrup
248. itions however that may cause the clock to run continuously If the Receive With Out Transmit mode is enabled by setting the SSCR1 RWOT bit to 1 the 125 will toggle regardless of whether Transmit data exists within the Transmit FIFO The I2Sx CLK will also toggle continuously if the Enhanced SSP is in Network mode or if ECRA or ECRB is enabled At other times 125 will be held an inactive 25 or idle state as defined by the specified protocol under which it operates Programmable Serial Protocol PSP There are many variations of the frame behavior for different codecs and protocol formats To allow flexibility the PSP format allows 125 to be programmable in direction delay polarity and width Master and Slave modes are supported PSP can be programmed to be either full or half duplex The 125 function behavior varies between each format PSP lets programmers choose which edge of I2Sx to use for switching Transmit data and for sampling Receive data In addition programmers can control the idle state for 125 and the number of active clocks that precede and follow the data transmission The PSP format provides programmability for several parameters that determine the transfer timings between data samples There are four possible serial clock sub modes depending on the 25 edges selected for driving data and sampling received data and the selection of idle state o
249. ivide chain is properly configured During this procedure the stored time and date are incremented overflow checked a matching alarm condition is checked and the time and date are rewritten to the RAM locations The update cycle starts at least 488 ms after A UIP is asserted and the entire cycle does not take more than 1984 ms to complete The time and date RAM locations 00h to 09h are disconnected from the external bus during this time Interrupts The real time clock interrupt is internally routed within the SoC both to the I O APIC and the 8259 It is mapped to interrupt vector 8 This interrupt does not leave the SoC is it shared with any other interrupt IRQ8 from the SERIRQ stream is ignored However the High Performance Event Timers can also be mapped to IRQ8 in this case the RTC interrupt is blocked Lockable RAM Ranges The RTC battery backed RAM supports two 8 byte ranges that can be locked the RC UL and RC LL register bits When the locking bits are set the corresponding range in the RAM is not readable or writable A write cycle to those locations will have no effect A read cycle to those locations will not return the location s actual value resultant value is undefined Once a range is locked the range can be unlocked only by a hard reset which will invoke the BIOS and allow it to re lock the RAM range Clearing Battery Backed RTC RAM Clearing CMOS RAM in an SoC based platform can be done b
250. k 1 The frequency may vary between 25 and 200 MHz SDMMC3 D 3 0 SD Card Data bits O to 3 Bidirectional port used to transfer data to and from SD MMC card I O GPIO By default after power up or reset only D 0 is used for data transfer A wider data bus can be configured for data transfer using D 3 0 Note Unused data lines will be tri stated by the SoC logic SDMMC3 CD SD Card Detect Active low when a card is present Floating pulled high with internal PU when a I O GPIO card is not present Note The processor does not support plug in eMMC device Only soldered down eMMC device is supported SDMMC3 CMD SD Card Command I O GPIO This signal is used for card initialization and transfer of commands It has two modes open drain for initialization and push pull for fast command transfer SDMMC3 1P8EN SD Card 1 8V Enable I O GPIO Controls the voltage of the SD Card The default is low 3 3V The voltage is 1 8V when this signal is high SDMMC3 RCOMP SDMMC3 PWR EN SD Card RCOMP This signal is used for pre driver slew rate compensation SD Card Power Enable This signal is used to enable power on a SD device I O GPIO I O GPIO 10 3 References The 92 controller is configured to comply with SD Specification Part 01 Physical Layer Specification version 3 00 April 16 2009 SD Specification Part E1 SDIO Specification version 3 00 December 16
251. l NMI sources may alternatively generate a SMI Note ASERRZ is only generated by setting internally in the SoC GNMI NMI2SMIEN 1b IOCHK goes active The SoC uses Note AIOCHK is only generated as a 1 E SERIRQ frame 9 9 ILB NMI goes active Note Active can be defined as being GNMI GNMIED GNMI GNMIS on the positive or negative edge of the signal using the GNMI GNMIED register bit Software sets the GNMI NMIN register bit GNMI NMIN GNMI NMINS Note Datasheet Volume 1 of 3 The NSC register is documented in the PCU 8254 Timers Memory Mapped I O Registers Section 153 Note 16 8 1 Table 16 20 n tel Platform Controller Unit PCU Overview PCU iLB Low Pin Count LPC Bridge The SoC implements an LPC Interface as described in the LPC 1 1 Specification The Low Pin Count LPC bridge function of the SoC resides in PCI Device 31 Function 0 In addition to the LPC bridge interface function 031 0 contains other functional units including interrupt controllers timers power management system management GPIO and RTC Signal Descriptions LPC Signals Signal Name Description ype LPC Multiplexed Command Address Data Internal pull ups are provided for these signals AD 3 0 HSHV These signals are multiplexed and may be used by other functions 3 3 1 8 Note set LPC_AD 3 0 power supply
252. l Out and SoC Pin Locations 193 19 1 SOC LISt LOCATIONS serae eterne dale ia VERE ERE 199 Package Information repe rione tae suo cece xia teed es 211 20 1 Attributes etre i nds eet uua andes hea CR OE LX at Ada ed 211 20 2 Package Diagrams reser err Etha pesar any nen FRIES 212 Electrical Specifications 5 cast cee iei la ze lena Dea au ka dica 215 21 1 Absolute Maximum and Minimum 5 215 21 2 Thermal Specifications a Cr RR E Rd ced ca a da RTI ea DX 215 21 3 Storage Conditions sieri 216 21 3 1 Post Board exer da d D E daga SATA E 216 21 4 Voltage and Current 5 eene 217 21 4 1 VCC and Voltage Specifications 218 21 4 2 Voltage Identification 10 nennen nnn ia 218 21 5 Crystal Specifications iris nde neue aee enin acne Kx X A RR D Rea 225 21 6 DC Specifications
253. l Parameter Min Typ Max Units Notes Input High Voltage 2 3 V 1 Input Low Voltage 0 78 V 2 Notes 1 defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 Vi is definea as the minimum voltage level at a receiving agent that will be interpreted as a logical low value 240 Datasheet Volume 1 of 3 Electrical Specifications Table 21 34 PROCHOT Signal Group DC Specification Symbol Parameter Min Typ Max Units Notes VREF I O Voltage 1 Input High Voltage 0 75 VREF VREF 1 VIL Input Low Voltage 0 45 VREF 2 VoL Output Low Voltage 0 35 VREF V Output Low Current 5 Notes 1 defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high 2 Vis definea as the minimum voltage level at a receiving agent that will be interpreted as a logical low value 21 6 14 SVID DC Specification Table 21 35 SVID Signal Group DC Specification SVID DATA SVID CLK SVID ALERT N Symbol Parameter Min Typ Max Units Notes VREF T O Voltage 1 Input High Voltage 0 65 VREF V 1 VIL Input Low Voltage 0 35 VREF V 1 Vou Output High Voltage 0 45 VREF V 1 VoL Output Low Voltage 0 45 V 4 Vuvs Hysteresis Voltage 0 1 V BUffer on R
254. lanes It contains a serializer and deserializer unit to interface with the PPI lane management unit There is also a clock divider unit to source and receive the clock during different modes of operation PPI Lane Management Unit This layer does the lane buffering and distributes the data in the lanes as programmed in a round robin manner and also merges them for the PLI Low Level Protocol unit PLI Low Level Protocol Unit This layer packetizes as well as de packetizes the data with respect to channels frames colors and line formats There are ECC generator and corrector units to recover the data free from errors in the packet headers There is also a CRC checker or CRC generator unit to pack the payload data with CRC checksum bits for payload data protection Pixel Byte to Byte Pixel Packing Formats Conversion of pixel formats to data bytes in the payload data is done depending on the type of image data supported by the application It also re converts the raw data bytes to pixel format understandable to the application layer Application Depending on the type of formats camera types capability of the camera used by the transmitter the application layer recovers the image formats and reproduces the image in the display unit It also works on de framing the data into pixel to packing formats High level encoding and decoding of image data is handled in the application unit MIPI CSI 2 Receiver Features CS
255. le the owner will drive the clock signal SPI Chip Select 0 Used as the SPI bus request signal for the first FST_SPI_CS 0 _N GPIO SPI Flash device SPI Chip Select 1 Used as the SPI bus request signal for the second FST SPI CS 1 N GPIO SPI Flash devices This signal is multiplexed and may be used by other functions FST SPI D 3 0 Ric Fast SPI Data Pad Data Input output pin for the SoC Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel 16 3 2 Features 1 Descriptor has two Modes of operation i Descriptor mode with security access restrictions ii Non Descriptor mode no access security restrictions ICH7 style 1 BIOS Only 2 If the SPI Flash Signature is invalid the SPI flash operates in non descriptor mode b Supports Flash that is divided into 4 regions and accessible by two masters i Regions 4 1 Flash Descriptor and Chipset Soft Straps 2 BIOS 3 TXE 4 Platform Data ii Masters 3 1 Host Processor for BIOS 2 TXE iii Regions are allowed to extend across multiple Flash components iv Regions are aligned to 4K blocks sectors b Chipset Soft Strap region provides the ability to use Flash NVM as an alternative to hardware pull up pull down resistors for both SoC and the processor Complex i Each Unit that pulls Soft straps from SPI should have a default value that is used if the Flash Signature is invalid b The top of the Flash Descriptor contains the Flash Uppe
256. le for AHCI Support clock gating and dynamic trunk gating Serial I O 12 Ports 7 12 Speed Standard mode bit rate up to 100Kb s Fast mode bit rate up to 400Kb s Fast Mode Plus bit rate up to 1Mb s High Speed mode bit rate up to 1 7Mb s HSUART Ports 2 HSUART Baud Rate Between 300 and 3686400 SPI Note 510 SPI is supported for non Windows Operating System platforms only SPI Speed Up to 20Mb s SPI Other Single interrupt line could be assigned to interrupt PCI INT A or ACPISIO INT 1 Configurable frame format clock polarity and clock phase supporting three SPI peripherals only Two Chip selects are supported for each of the 2 SPI controllers SPI1 and 5 Supports master mode only Receive and transit buffers are both 256 x 32 bits The receive buffer has only 1 water mark The transmit buffer has 2 water marks 24 Datasheet Volume 1 of 3 Introduction intel Interface Category SoC Features SD Card Interface v3 0 1 port SD Card Speed Host Clock rate variable between 0 and 200 MHz SDR104 mode up to 800Mb s data rate using 4 parallel data lines Transfer the date in 1 bit and 4 bit SD modes SD Card data transfer rate Transfers the data in following UHS I modes SDR12 25 50 104 and 20850 Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity SD Car
257. led the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when e At least one core is in the C1 State The other cores are in a or lower power state The package enters the C1E State when All cores have directly requested by means of MWAIT C1 with sub state hint e All cores are in a power state lower that C1 C1E but the package low power state is limited to C1 C1E by means of the CST CONFIG CONTROL MSR All cores have requested C1 using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32 MISC ENABLES No notification to the system occurs upon entry to C1 C1E State Package C6 State A processor enters the package C6 low power state when e At least one core is in the C6 State The other cores are in a C6 or lower power state the processor has been granted permission by the platform Datasheet Volume 1 of 3 65 m e n tel Power Management 6 3 5 4 6 3 6 6 3 7 6 3 8 66 The platform has not granted a request to a package C7 State but has allowed a package C6 State In package C6 State all cores have saved their architectural state and have had their core voltages reduced to zero volts Package C7 State A processor enters the package C7 low power state when all cores are in the C7 State In package C7 State the processor will take ac
258. ler supports a serial IRQ scheme The signal used to transmit this information is shared between the interrupt controller and all peripherals that support serial interrupts The signal line ILB_LPC_SERIRQ is synchronous to LPC clock and follows the sustained tri state protocol that is used by LPC signals The serial IRQ protocol defines this sustained tri state signaling in the following fashion S Sample Phase Signal driven low R Recovery Phase Signal driven high T Turnaround Phase Signal released Datasheet Volume 1 of 3 m Platform Controller Unit Overview n tel The interrupt controller supports 21 serial interrupts These represent the 15 ISA interrupts IRQ 0 1 3 15 the four PCI interrupts and the control signals SMI and IOCHK Serial interrupt information is transferred using three types of frames e Start Frame ILB_LPC_SERIRQ line driven low by the interrupt controller to indicate the start of IRQ transmission Data Frames IRQ information transmitted by peripherals The interrupt controller supports 21 data frames e Stop Frame ILB_LPC_SERIRQ line driven low by the interrupt controller to indicate end of transmission and next mode of operation 16 8 2 7 2 Start Frame The serial IRQ protocol has two modes of operation which affect the start frame Continuous Mode The interrupt controller is solely responsible for generating the start frame Quiet Mode Peripheral initiates t
259. ltage in high speed 10 10 High Speed Termination 40 45 50 Q VBUS Voltage drop for detachable cables 3 1 my Notes 1 Measured at A plug 2 Measured at A receptacle 3 Measured at B receptacle 4 Measured at A or B connector 5 Measured with RL of 1 4 KQ to 3 6V 6 Measured with RL of 14 KQ to GND 7 Timing difference between the differential data signals 8 Measured at crossover point of differential data signals 9 maximum load specification is the maximum effective capacitive load allowed that meets the target VBUS drop of 330 10 Excluding the first transition from the Idle state 11 The two transitions should be a nominal bit time apart 12 For both transitions of differential signaling 13 Must accept as valid EOP 14 Single ended capacitance of D or D is the capacitance of D D to all other conductors and if present shield in the cable That is to measure the single ended capacitance of D short VBUS GND the shield line together and measure the capacitance of D to the other conductors 15 For high power devices non hubs when enabled for remote wakeup 16 Specified by eye pattern templates 21 6 9 USB HSIC DC Specification Table 21 25 USB HSIC DC Electrical Specification Sheet 1 of 2 Symbol Parameter Min Max Units VREF I O Voltage USB_HSIC_V1 2V VoH Output HIGH voltage 0
260. ltage reduced During exit the core is powered on and its architectural state is restored Core C7 State Individual core can enter the C7 state by initiating a P LVL7 I O read or an MWAIT C7 instruction The core C7 state exhibits the same behavior as core C6 state but in addition gives permission to the internal Power Management logic to enter a package 50 state if possible Datasheet Volume 1 of 3 63 m e n tel Power Management 6 3 4 5 C State Auto Demotion In general deeper C States such as C6 have long latencies and higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C State is high Therefore incorrect or inefficient usage of deeper C States has a negative impact on battery life In order to increase residency and improve battery life in deeper C States the processor supports C State auto demotion This is the C State auto demotion option C7 C6 to C1 The decision to demote a core from C7 C6 to C1 is based on each core s immediate residency history Upon each core C7 C6 request the core C State is demoted to C1 until a sufficient amount of residency has been established At that point a core is allowed to go into C6 or C7 This feature is disabled by default BIOS must enable it in the PMG CST CONTROL register The auto demotion policy is also configured by this register 6 3 5 Package C States The proces
261. m to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3 D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3 D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3 D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3 D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower uses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is poss
262. mand that has not been serviced yet by the host software as indicated by the SMB Mem SSTS HNST bit then it will NACK following the host address byte of the protocol This allows the host to communicate non acceptance to the master and retain the host notify address and data values for the previous cycle until host software completely services the interrupt Host software must always clear the SMB Mem SSTS HNST bit after completing any necessary reads of the address and data registers The following table shows the Host Notify format Table 16 17 Host Notify Format Sheet 1 of 2 150 Bit Description Driven By Comment 1 Start External Master 2 8 SMB Host Address 7 bits External Master Always 0001 000 9 Write External Master Always 0 10 ACK or NACK SoC SoC NACKs if SMB Mem SSTS HNST is 1 Device Address 7 bits External Master Indicates the address of the master loaded 11 17 into the Notify Device Address Register SMB Mem NDA 18 Unused Always 0 External Master 7 bit only address this bit is inserted to complete the byte 19 ACK SoC 22 27 Data Byte Low 8 bits External Master Loaded into the Notify Data Low Byte Register NDLB Datasheet Volume 1 of 3 Platform Controller Unit Overview Table 16 17 Host Notify Format Sheet 2 of 2 intel Bit Description Driven By Comment 28 ACK SoC 29 36 Data Byte High 8 bits External Master Loaded into
263. ming the DDS Multiplier as 44 236 800 in decimal and DDS Divisor as the system clock frequency in Hz 50 000 000 in decimal when the system clock frequency is 50 MHz The output baud rate 3686400 is equal to the base frequency divided by thirteen times the value of the divisor as follows baud rate Fbase 13 divisor The output baud rate for all other baud rates is equal to the base frequency divided by sixteen times the value of the divisor as follows baud rate Fbase 16 divisor Table 15 5 Baud Rates Achievable with Different DLAB Settings 15 3 3 DLH DLL Divisor Baud Rate Fbase 1 47923200 Hz 1 0001 3686400 Fbase 2 44236800 Hz 1 0001 2764800 3 0003 921600 6 0006 460800 9 0009 307200 12 000C 230400 15 000F 184320 18 0012 153600 24 0018 115200 48 0030 57600 72 0048 38400 144 0090 19200 288 0120 9600 384 0180 7200 576 0240 4800 768 0300 3600 1152 0480 2400 1536 0600 1800 2304 0900 1200 4608 1200 600 9216 2400 300 Use Each UART has a transmit FIFO and a receive FIFO with each FIFO holding 64 characters of data Three separate methods move data into and out of the FIFOs interrupts DMA and polled Datasheet Volume 1 of 3 121 tel 9 Serial 510 Overview 15 3 3 1 15 3 3 1 1 15 3 3 1 2 15 3 3 1 3 15 3 3 2 15 3 3 2 1 15 3 3 2 2 15 3 3 2 3 122 Mode Operation Receiver
264. nal Recovery Supported 3Gb s Transfer Rate Supported ATAPI Asynchronous Notification Supported Host and Link Initiated Power Management Supported Staggered Spin Up Supported Command Completion Coalescing N A 17 3 2 Features Not Supported Port Multiplier FIS Based Switching Command Based Switching IDE Mode Cold Presence Detect Function Level Reset Command Completion Coalescing Enclosure Management 17 4 References e Serial ATA Specification rev 3 1 Serial ATA Advanced Host Controller Interface AHCI Specification 1 3 1 Serial ATA II Extensions to Serial 1 0 Specification Revision 1 0 88 188 Datasheet Volume 1 of 3 PCI Express 2 0 n tel 18 18 1 PCI Express 2 0 There are four lanes and up to four PCI Express root ports each supporting the PCI Express Base Specification Rev 2 0 at a maximum 5 GT s signaling rate The root ports can be configured to support a diverse set of lane assignments Signal Descriptions Figure 18 1 PCI Express 2 0 Lane 0 Signal Example 18 2 Ld CYC YR 0 101 101 101 0 0 NA NI NA Features e Conforms to PCI Express Base Specification Rev 2 0 e 5 0 or 2 5 GT s operation per root port e Virtual Channel support for VCO only e x1 x2 and x4 link widths auto negotiated e Flexible Root Port 1 24 configuration options
265. nductive materials Doing so may short the capacitors and possibly damage the device or render it inactive The use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting An exclusion or keep out zone surrounds the die and capacitors and identifies the contact area for the package Care should be taken to avoid contact with the package inside this area 20 1 SoC Attributes Attribute SoC X Y dimensions mm 27 mm x 25 mm Processor Core Process nm 14 Post SMT Height mm 1 Minimum Ball Pitch mm 0 593 Die Thickness um 370 Total Pin Count 1170 Package Type FCBGA15 Datasheet Volume 1 of 3 211 Package Information intel Package Diagrams 20 2 Figure 20 1 Package Mechanical Drawing Part 1 of 3 TWIS 101 g m 115 9NIMVHO anc mu 1199 105 339 998 145 39 STI 04 HIL 13141 14360 151838 830105 10 151538 8301 119134 33
266. ng a value of OOh to it Software sets TOC TVS Software writes the new value in TOCV Software sets GCFG EN to enable interrupts Interrupts If each timer has a unique interrupt and the timer has been configured for edge triggered mode then there are no specific steps required If configured to level triggered mode then its interrupt must be cleared by software by writing a 1 back to the bit position for the interrupt to be cleared Interrupts associated with the various timers have several interrupt mapping options Software should mask GCFG LRE when reprogramming HPET interrupt routing to avoid spurious interrupts Mapping Option Number 1 Legacy Option GCFG LRE Set This forces the following mapping 8254 Interrupt Mapping Timer 8259 Mapping APIC Mapping Comment 0 IRQO IRQ2 The 8254 timer will not cause any interrupts 1 1808 IRQ8 RTC will not cause any interrupts 2 T2C IR T2C IRC Mapping Option Number 2 Standard Option GCFG LRE Cleared Each timer has its own routing control The interrupts can be routed to various interrupts in the I O APIC T 2 0 C IRC indicates which interrupts are valid options for routing If a timer is set for edge triggered mode the timers should not be shared with any other interrupts Datasheet Volume 1 of 3 169 m n tel Platform Controller Unit PCU Overview 16 11 2 16 11 3 16 12 170 References IA PC HPET Hi
267. nput 20 Input 20 Input 20 Input 20 Input 20 Input 20 Input 20 k PU k PU k PU k PD k PD k PU k PD k PU k PU k PU k PU Physical Interfaces Optional Modes Direction Mode5 CO BPM1 TX DFX O Mode6 C1_BPM1_TX DFX O Mode8 IERR O Mode5 CO BPM2 TX DFX 2 DFX O Mode5 C0_BPM3_TX DFX IO Mode6 C1_BPM3_TX DFX IO Mode6 PCI_WAKE1_N I Mode6 PCI_WAKE2_N I Mode6 PCI_WAKE3_N I Mode6 PCI_WAKE4_N I Input 20k PU Input 20k PD Input 20k PD 0 0 20 nput 20 nput 20 nput 20 nput 20 nput 20 nput 20 Input 20 1 Input 20 1 20 1 Input 20 1 0 PD 0 20k PD PD k PD PD k PD PD k PU k PU k PU k PU Z 1k PU OD Z 1k PU OD 2 20k PU OD Mode2 HDA CLK O Mode2 HDA_RSTB I Mode2 HDA SDIO O Mode2 HDA SDI1 O Mode2 HDA SDO O Mode2 HDA 5 Mode2 UARTO RXD I Mode2 UARTO TXD O Datasheet Volume 1 of 3 Physical Interfaces Table 2 27 GPIO Multiplexing and Modes Sheet 4 of 6 Count 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 SoC Pin No AH6 AF9 AF7 AE4 AD2 1 AD3 AB2 AC3 AA1 AB3 Cii B10 F12 F10 012 E8 C7 D6 112
268. ns Power Voltage Power Power Well Description Tolerance System YP V States CORE VCC1 Variable voltage rail for core VCC 0 5 1 3 amp VCC1 rails See Table 21 4 on page 218 50 merged into one single voltage rail VCC DDI VGG T Variable voltage rail for T 2 VGG 0 5 1 2 Graphics Core See Table 21 4 on page 218 50 UNCORE VNN S4 Config 1 Variable voltage 0 5 1 05 rail for SoC VNN See Table 21 4 on page 218 50 55 UNCORE VNN 54 Config 2 Fixed VID rail for 1 05 SoC VCCSRAMSOCIUN 1P05 Fixed voltage rail for P FUSE 1 G3 unit LPE TXE I Os and VCCSRAMSOCIUN 1P05 PLLs USB3 1 1 05 5 0 5 SATA 1 PCIE 1 G3 DDR V1P05A G3 Merc re LE Fixed voltage rail for SoC V1P15S 1 15 5 50 CORE 5 L2 SoC RAM Graphics CORE VSFR G3 Fixed voltage rail for I Os USB VDDQ G3 and PLLs 1 24 USBHSIC V1P2A 1 24 5 S0 S5 ICLK_VSFR_G3 MIPI V1P2A G3 GPIO V1P8A G3 Fixed voltage rail for I Os 5010 V3P3A 1 G3 1 8 5 S0 S5 FUSE 1 DDR VDDQ 54 Fixed voltage for 59 a VDDQ DDRSFR_VDDQ_G_S4 1 35 DDR3L PHY 5 50 53 RTC V3P3A G5 Fixed voltage rail for I Os 5 _ lt _ G3 am RTC V3P3RTC G5 Fixed Voltage rail for RTC 2 3VDC Q Battery or else _ 3 3 Real Time Clock 3 3 volts pre
269. nt thermal throttling mechanisms Digital Thermal Sensors SoC Sensors are based on DTS Digital Thermal Sensor to provide more accurate measure of system thermals The SoC has 8 Digital Thermal Sensors DTS provides as wires the current temperature around the real estate it occupies on the SoC These are driven to the PM unit which in turn monitors the temperature from the DTS on the SoC DTS outputs are adjusted for silicon variations For a given temperature the output from the DTS is always the same irrespective of silicon Temperature Reading Based on DTS Sheet 1 of 2 DTS Counter Temperature Reading Value 8 0 90 127 90 137 80 147 70 157 60 167 50 177 40 187 30 197 20 207 10 217 0 227 10 Datasheet Volume 1 of 3 55 m e n tel Thermal Management Table 5 1 5 2 1 Figure 5 1 56 Temperature Reading Based on DTS Sheet 2 of 2 DTS Counter Temperature Reading Value 8 0 90 237 20 247 30 255 38 Note DTS encoding of 127 always represents TjMAx at 90 C the encoding 137 from DST indicates 80 and so forth Note DTS value 255 represent the minimum temperature thus 38 C is the lowest temperature will be reported by the SoC Thermal trip points are of two types Hardware Trip The Cata
270. ntel logo are trademarks of Intel Corporation in the U S and other countries Other names and brands may be claimed as the property of others Copyright 2015 Intel Corporation 2 Datasheet Volume 1 of 3 Contents 1 Introduction oou er ana Ue OR RV 17 1 1 Document Structure and 5 ka hehe Ra ERR Ra nn nad 19 1 2 Terminology 295 se nan need o ERR PINTA 20 1 3 Feature canst denne dad i aaa FREE 22 1 4 Related Doclments 22 erede a isa ka n eme RR A REEL EE saa EAR RANA 26 2 Physical Interfaces owes M ERA REN 27 2 1 Platform Power ER RR Rr Pen Ape ux E MERE 27 2 2 SoC Physical Signal Per 1 eee ee eee eese 29 2 2 1 System Memory Controller Interface Signals DDR3L 29 2 2 2 USB 2 0 Controller Interface Signals 30 2 2 3 USB 3 0 Interface Signals rii ree rid n 31 2 2 4 Integrated Clock Interface Signals 31 2 2 5 Display Digital Display Interface DDI 32 2 2 6 MIPI CSI Camera Serial Interface and ISP Interface Signals 33 2 2 7 Storage Controller Inte
271. ntil the start or stop condition meets proper setup and hold time The SoC will also ensure minimum time between SMBus transactions as a master Bus Timing Clock Stretching Some devices may not be able to handle their clock toggling at the rate that the SoC as an SMBus master would like They have the capability of stretching the low time of the clock When the SoC attempts to release the clock allowing the clock to go high the clock will remain low for an extended period of time The SoC monitors the SMBus clock line after it releases the bus to determine whether to enable the counter for the high time of the clock While the bus is still low the high time counter must not be enabled Similarly the low period of the clock can be stretched by an SMBus master if it is not ready to send or receive data Bus Timeout SoC as SMBus Master If there is an error in the transaction such that an SMBus device does not signal an acknowledge or holds the clock lower than the allowed time out time the transaction will time out The SoC will discard the cycle and set the SMB HSTS DEVERR bit The time out minimum is 25 ms 800 RTC clocks The time out counter inside the SoC will start after the last bit of data is transferred by the SoC and it is waiting for a response The 25 ms timeout counter will not count under the following conditions 1 The SMB Mem HSTS BYTE DONE STS bit is set 2 The STS SECOND STS bit is not set th
272. o Chapter 2 Physical Interfaces for GPIO strap pin list 16 13 PCU iLB Interrupt Decoding and Routing The interrupt decoder is responsible for receiving interrupt messages from other devices in the SoC and decoding them for consumption by the interrupt router the PCU iLB 8259 Programmable Interrupt Controllers PIC and or the PCU iLB 1 0 The interrupt router is responsible for mapping each incoming interrupt to the appropriate PIRQx for consumption by the PCU iLB 8259 Programmable Interrupt Controllers PIC and or the PCU iLB I O APIC 174 Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel 16 13 1 16 13 1 1 16 13 1 1 1 16 13 1 1 2 16 13 1 2 16 13 1 2 1 16 14 Features Interrupt Decoder The interrupt decoder receives interrupt messages from devices in the SoC These interrupts can be split into two primary groups For consumption by the interrupt router e For consumption by the 8259 PIC For Consumption by the Interrupt Router When a PCI mapped device in the SoC asserts or de asserts an INT A D interrupt an interrupt message is sent to the decoder This message is decoded to indicate to the interrupt router which specific interrupt is asserted or de asserted and which device the INT A D interrupt originated from For Consumption by the 8259 PIC When a device in the SoC asserts or de asserts a legacy interrupt IRQ an inter
273. o latch multiple counter outputs at one time This single command is functionally equivalent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or reprogrammed Once read a counter is unlatched The other counters remain latched until they are read If multiple count Read Back commands are issued to the same counter without reading the count all but the first are ignored The Read Back command may additionally be used to latch status information of selected counters The status of a counter is accessed by a read from that counter s I O port address If multiple counter status latch operations are performed without reading the status all but the first are ignored Both count and status of the selected counters may be latched simultaneously This is functionally the same as issuing two consecutive separate Read Back commands If multiple count and or status Read Back commands are issued to the same counters without any intervening reads all but the first are ignored If both count and status of a counter are latched the first read operation from that counter returns the latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts returns the latched count Subsequent reads return unlatched count Datasheet Volume 1 of 3 167 Note Figure 16 3 16 11 1 16 11 1 1 16 11 1 2
274. o processor core power states States for processor core include Normal CO C1 and Stop Grant The processor core implements two software interfaces for requesting low power states MWAIT instruction extensions with sub state specifies and LVLx reads to the ACPI P BLK register block mapped in the processor core I O address space The P LVLx I O reads are converted to equivalent MWAIT C State requests inside the processor core and do not directly result in I O reads on the processor core bus The monitor address does not need to be setup before using the LVLx I O read interface The sub state specifications used for each P LVLx read can be configured in a software programmable MSR by BIOS The Cx state ends due to a break event Based on the break event the processor returns the system to CO The following are examples of such break events e Any unmasked interrupt goes active Any internal event that will cause an NMI or SMI B e Processor Pending Break Event B e MSI Idle Power Management Breakdown of the Processor Cores Core 0 State Core 1 State Processor Package State Datasheet Volume 1 of 3 intel 6 3 4 Table 6 5 6 3 4 1 6 3 4 2 6 3 4 3 6 3 4 4 Processor Core C States Description Processor Core States Support State Description CO Active mode processor executing code C1 AutoHALT state 1 AutoHALT State with lowest frequency and volta
275. oC attempts to perform a graceful reset by waiting for the relevant internal devices to signal their idleness If all devices are idle when the pin is detected active the reset occurs immediately otherwise a counter starts If at any point during the count all devices go idle the reset occurs If the counter expires and any device is still active a reset is forced upon the system even though activity is still occurring Once the reset is asserted it remains asserted for 5 6 ms regardless of whether the PMU RSTBTNZ input remains asserted or not It cannot occur again until PMU_RSTBTN has been detected inactive after the debounce logic and the system is back to a full SO state with PMU_PLTRST inactive If RST_CNT FULL_RST is set then PMU_RSTBTN will result in a full Power cycle Reset System Power Planes The system has several independent power planes as described in Table 16 5 When a particular power plane is shut off it should go to a O zero V level Datasheet Volume 1 of 3 129 m n tel Platform Controller Unit PCU Overview Table 16 5 System Power Planes 16 2 2 3 1 16 2 2 3 2 Note 16 2 2 3 3 Note 130 Plane Controlled By Description When PMU SLP 54 goes active power can be shut off to any circuit not required to wake the system from the 54 55 Since the Devices and SLP 54 memory context does not need to be preserved in the 54 55 state Memory the power to the memory can also be sh
276. ocessor using single transfers or DMA burst transfers of up to the FIFO depth Each 32 bit word from the bus fills one entry in a FIFO using the lower significant bits of a 32 bit word SSP Features The SSP port features are Inter IC Sound 125 protocols are supported by programming the Programmable Serial Protocol PSP One FIFO for transmit data TXFIFO and a second independent FIFO for receive data RXFIFO where each FIFO is 16 samples deep x 32 bits wide Data sample sizes from 8 16 18 or 32 bits 12 5Mbps maximum serial bit rate in both modes master and slave Clock master or slave mode operations Receive without transmit operation Network mode with up to eight time slots for PSP formats and independent transmit receive in any all none of the time slots After updating SSP configuration for example active slot count the SSP will need to be disabled and enabled again In other words a SSP will not function correctly if a user changes the configuration setting on the fly Operation Serial data is transferred between the LPE core or the SoC Processor Core and an external peripheral through FIFOs in one of the SSP ports Data transfers between an SSP port and memory are initiated by either the LPE core or the SoC Processor Core using programmed I O or by DMA bursts Although it is possible to initiate transfers directly from the SoC Processor Core current driver design uses LPE for all PCM ope
277. ode the SoC issues a byte count describing how many more bytes will follow in the message If a slave had 20 bytes to send the first byte would be the number 20 14h followed by 20 bytes of data The byte count may not be 0 A Block Read or Write is allowed to transfer a maximum of 32 data bytes When programmed for a block write command the Transmit Slave Address Mem TSA Host Command SMB HCMD and Data 0 Mem registers are sent Data is then sent from the Host Block Data SMB HBD register the total data sent being the value stored in the Data 0 SMB Mem HDO register On block read commands the first byte received is stored in the Data 0 SMB Mem HDO register and the remaining bytes are stored in the Host Block Data SMB Mem HBD register See section 5 5 7 of the System Management Bus SMBus Specification Version 2 0 for the format of the protocol Datasheet Volume 1 of 3 145 n tel Platform Controller Unit PCU Overview Note Note Note 146 For Block Write if the SMB Config HCFG I2C EN bit is set the format of the command changes slightly The SoC will still send the number of bytes on writes or receive the number of bytes on reads indicated the Data 0 SMB Mem register However it will not send the contents of the Data 0 SMB Mem HDO register as part of the message Also the Block Write protocol sequence changes slightly the Byte Count bits 27
278. ode2 NMI N Mode2 SDMMC3 WP I 45 intel Table 2 27 SoC Count Pin No CFIO Name 20 M2 MF LPC 21 N3 MF LPC AD2 22 1 MF LPC AD3 23 T3 LPC CLKRUN N 24 P3 LPC FRAME N 25 AK9 GP SSP 2 CLK 26 AK10 GP SSP 2 FS 27 AK13 GP SSP 2 RXD 28 AK12 GP SSP 2 TXD 29 AM10 PCIE CLKREQO N 30 AM12 PCIE CLKREQ1 N 31 AK14 PCIE CLKREQ2 N 32 14 PCIE CLKREQ3 N 33 A9 MF PLT CLKO 34 C9 MF PLT CLK1 35 B8 MF PLT CLK2 36 B7 MF PLT CLK3 37 B5 PLT 38 4 5 39 C13 AC PRESENT 40 C14 PMU BATLOW N 41 14 PMU PLTRST N 42 M16 PMU PWRBTN N 43 AF2 PMU 44 12 PMU SLP LAN 45 A13 PMU SLP SOIX N 46 14 S3 47 C12 SLP S4 48 C15 PMU SUSCLK 49 N16 PMU WAKE N 50 P18 PMU WAKE LAN N 51 Di4 SUS STAT N 52 AE3 SUSPWRDNACK 53 H5 PWMO 54 H7 PWM1 55 AH2 SATA GPO 56 AG3 SATA GP1 57 1 SATA GP2 58 AF3 SATA GP3 59 AH3 SATA LEDN 60 K2 SDMMC3 1 8 EN 61 K3 SDMMC3 CD 46 Default Mode ef ep ep m Default Function LPC LPC AD2 LPC AD3 LPC CLKRUN N LPC FRAME N 55 2 125 GP SSP 2 125 FS GP SSP 2 125 RXD GP SSP 2 I2S TXD PCIE CLKREQO N PCIE CLKREQ1 N PCIE CLKREQ2 N PCIE CLKREQ3 N PLT CLKO PLT CLK1 PLT CLK2 PLT CLK3 PLT PLT 5 PMU AC PRESENT PMU BATLOW N PMU PLTRST N PWRBTN P
279. ode5 CO 1 TX DFX O Mode6 Ci 1 TX DFX 5 BPM2 DFX Mode6 Ci 2 TX DFX Mode5 CO BPM3 TX DFX IO 1 TX 10 Mode5 CO BPMO TX DFX IO BPMO TX DFX IO 43 intel GPIO Multiplexing and Modes Sheet 3 of 6 Table 2 27 SoC Count Pin No CFIO Name 51 48 GPIO DFX6 52 41 GPIO DFX7 53 AK42 GPIO_DFX8 54 AD51 GPIO_SUSO 55 AD52 GPIO_SUS1 56 AH50 GPIO_SUS2 57 48 GPIO 5053 58 51 GPIO 5054 59 52 GPIO 5055 60 51 GPIO 5056 61 AG53 GPIO SUS7 62 AF51 SEC GPIO 51 58 63 AF52 SEC GPIO SUS9 64 51 SEC GPIO SUS10 65 51 SEC GPIO SUS11 66 AD9 MF HDA CLK 67 AB9 MF HDA DOCKEN N 68 AB7 MF H DA DOCKRST_ 69 AF13 MF_HDA_RST_N 70 AD7 MF HDA SDIO 71 AD6 SDI1 72 14 HDA SDO 73 AF12 MF HDA SYNC 74 AD13 1 CTS 75 AD14 UART1_RTS_N 76 AD12 UART1_RXD 77 AD10 UART1_TXD 78 v9 UART2 CTS N 79 V10 UART2 RTS N 80 Y7 UART2 RXD 81 Y6 UART2 TXD 82 Y3 GPIO ALERT 83 AK6 I2CO SCL 84 AH7 12 SDA 85 214 2 SCL 44 Default Mode GPI GPI GPI GPI GPI m Default Function RSVD Inputs RSVD Inputs RSVD Inputs GPIO SUSO 5051 5052 5053 5054 5055 5056 5057 SEC 5058 SEC 51 59 CSE 50510 SEC 50511 SSP 0 125 TXD
280. of a frame and active until one cycle after the end of a frame Figure 15 1 shows an 8 bit data transfer with different phase and polarity settings Figure 15 1 Clock Phase and Polarity SSCR1 SPO 0 CLK 55 5 1 SS SSCR1 SPH 0 Data out Data in SSCR1 SPH 1 Data out Data in Ina single frame transfer the SPI controller supports all four possible combinations for the serial clock phase and polarity The combinations of polarity and phases are referred to as modes which are commonly numbered according to the following convention with SSCR1 SPO as the high order bit and SSCR1 SPH as the low order bit 15 2 2 SIO I C Interface The SoC supports seven 7 instances of I C controller Both 7 bit and 10 bit addressing modes are supported These controllers operate in master mode only 15 2 3 Signal Descriptions 12 is a two wire bus for inter IC communication Data and clock signals carry information between the connected devices The following is the 2 Interface The SoC supports seven I C interfaces for general purpose to control external devices The signals are multiplexed over GPIOs Table 15 2 I C 6 0 Signals Direction Signal Name Type Description yo I C Serial Data I2C 6 0 DATA These SIO I C signals are multiplexed and may be used 51 8 A by other functions 2 1 0 I C Serial Clock I2C 6 0 CLK These SIO I C signals are multiplex
281. of Operation x e SECRET AUTRE RUNE 56 6 1 Idle Power Management Breakdown of the Processor Cores 62 8 1 SoC Graphics Display 71 8 2 E MUERE 74 8 3 DisplayPort OVerVIeW asap RA a Pa casa Do anu EORR CR RA EE Rd 74 8 4 3 D Graphics Block Diagratm enki 76 9 1 Camera ConnectlVIEV ah e 82 9 2 Image Processing Components nie gne maet e dele Fake sacre ERR 84 9 3 MIPI CSI Bus Block Diagram Dee teneri prex kae ena xo Rate Da De susc 87 LI IxHCI Port Mapping ru xe iR x RI ERE en iN i 94 12 1Audio Cluster Block Diagram sss ness emen eene enn 99 12 2Memory Connections for EPE prec e pre 100 12 355 Str Clure rnnt Ra RAE ade Peach 104 12 4Programmable Serial Protocol eee nnns 109 12 5Programmable Serial Protocol Format Consecutive Transfers 109 15 tClock Phase and
282. ogrammed to 0 when the I2Sx is enabled by either of the SSCR1 ECRA or SSCR1 ECRB bits While the PSP be programmed to generate the assertion of 25 during the middle of the data transfer after the MSB was sent the Enhanced SSP will not be able to receive data in Frame slave mode SSCR1SFRMDIR 1 if the assertion of Frame is not before the MSB is sent that is T5 lt T2 if SSCR1 SFRMDIR 1 Transmit Data will transition from the End of Transfer Data State to the next MSB value upon the assertion of Frame The Start Delay field should be programmed to 0 whenever I2Sx CLK or I2Sx FRM is configured as an input Clock state is not defined between two active frame periods Clock can be active or inactive between two active frame periods 88 110 Datasheet Volume 1 of 3 m Intel Trusted Execution Engine Intel TXE n tel 13 Note 13 1 13 1 1 13 1 1 1 Intel Trusted Execution Engine Intel TXE This section describes the security components and capabilities of the Intel Trusted Execution Engine TXE security co processor TXE firmware is required on the processor platform as part of the PCU SPI flash image The PCU SPI interface must be operating in descriptor mode in order for the TXE to be able to access its firmware Features Security Feature The Intel TXE in the SoC is responsible for supporting and handling security related features Intel TXE features e 32 bit RISC proc
283. onfig HCTL PECEN and SMB AUXC AAC to Ob when running this command See section 5 5 6 of the System Management Bus SMBus Specification Version 2 0 for the format of the protocol For process call command the value written into SMB Mem TSA RW needs to be Ob If the SMB Config HCFG I2C EN bit is set the protocol sequence changes slightly the Command Code Bits 18 11 in the bit sequence are not sent as a result the slave will not acknowledge Bit 19 in the sequence Block Read Write The SoC contains a 32 byte buffer for read and write data which can be enabled by setting SMB Mem AUXC E32B as opposed to a single byte of buffering This 32 byte buffer is filled with write data before transmission and filled with read data on reception In the SoC the interrupt is generated only after a transmission or reception of 32 bytes or when the entire byte count has been transmitted received When operating in 2 mode 5 Config HCFG I2C EN bit is set the SoC will never use the 32 byte buffer for any block commands The byte count field is transmitted but ignored by the SoC as software will end the transfer after all bytes it cares about have been sent or received For a Block Write software must either force the 5 Config HCFG I2C EN bit or both the SMB Config HCTL PECEN and SMB AUXC AAC bits to Ob when running this command The block write begins with a slave address and a write condition After the command c
284. or s logic to reduce operating power when the LPE computational capabilities are not immediately needed by the system Using the WAITI instruction to power down the processor will save more power than use of the external run stall signal because the WAITI instruction disables more of the LPE s internal clocks External Timer This timer always runs from SSP clock before M N divider at 24 25 MHz The timer starts running once the run bit refer to the External timer register definition for details is set and the clear bit is cleared The timer generates an Interrupt pulse when the counter value matches the match value The interrupt does not get generated if the match value is set to 0 The timer runs in free running mode and rolls over after all 32 bits have become all 1s The timer continues to run as long as the run bit is set Once the run bit is cleared the timer holds the current value The clear bit needs to be set to restart the timer from 0 Clocks Clock Frequencies Table 12 2 shows the clock frequency options for the audio functional blocks Clock Frequencies Clock Frequency Notes Audio core 343 250 200 MHz 100 Audio input clock trunk CCU drives one of 50 MHz 2x Osc Osc several frequencies as noted 50 RO 100 RO DMA 0 50 05 DMA1 50 05 Audio fabric clock 50 OSC Fabric clock derived from audio core clock SSPO Clock Fabric side 50 OSC SSPO clo
285. or those GPIOs before entering Sx state is applicable to reduce power leakage scenarios GPIO signals have weak internal terminations and unused pins do not need to be terminated on the platform If they are terminated then BIOS needs to disable the internal terminations to avoid any issues related to leakage Default Function for GPIO DFX 8 0 is listed as RSVD but they can be used for normal GPIO functionality The following features are not supported for the processor but the related signals have been listed in this table since they can be used as normal GPIOs ISH Integrated Sensor Hub PWM Pulse Width Modulator SIO Serial IO SPI may be supported for some non Windows operating systems Connected Standby 50 related signals Ensure that 5 N is used as native functionality If used improperly can cause the SoC to reset Table 2 27 GPIO Multiplexing and Modes Sheet 1 of 6 Count bl pl a A 42 SoC Pin No 41 45 Y41 v40 AB44 AC53 AB51 AB52 AA51 AB40 Y44 Y42 w51 Y51 Y52 cro Pefeult pefauit Function SPORG Deassert modes 1 aB41 GP CAMERASBO 1 GP_CAMERASBOO ViP8A Input 20KPD Input 20k PD 2 45 GP_CAMERASBO1 1 GP_CAMERASBO1 ViP8A Input 20kPD Inpt 20kPD 3 vai 10
286. port functionality 11 3 1 Features of USB 3 0 Host 1 SuperSpeed data interface is a four wire differential TX and RX pairs 2 Interface supports a bit rate of 5Gbps with a maximum theoretical data throughput over 3 2Gbps 11 3 1 1 USB 3 0 Features e Supported by xHCI software host controller interface e USB 3 0 port disable e Supports local dynamic clock gating and trunk clock gating e Supports USB 3 0 LPM UO U1 U2 and U3 and also a SS Disabled low power state e Support for USB 3 0 Debug Device e Supports IVCAM USB PC Camera 11 3 2 Features of USB HSIC 1 Two 2 signal strobe and data source synchronous serial interface for on board inter chip USB communication 2 Uses 240 MHz DDR signaling to provide High Speed 480Mb s USB transfers 3 Full Speed FS and Low Speed LS USB transfers are not directly supported by the HSIC interface Major feature and performance highlights are as follows e Supported by xHCI software host controller interface High Speed 480Mb s data rate only e Source synchronous serial interface 11 4 References USB 3 0 Specification e USB 2 0 Specification Includes High Speed Inter Chip USB Electrical Specification Extensible Host Controller Interface xHCI Specification v1 1 88 Datasheet Volume 1 of 3 95 96 USB Controller Interfaces Datasheet Volume 1 of 3 Low Power Engine LPE for Audio 125 intel 12 Low Power Engine LPE for Audio 12
287. pplies to LPC AD 3 0 LPC CLKRUN N and LPC FRAME N LPC SERIRQ is always a 1 8V I O irrespective of the value of LPC V1P8V3P3 S4 21 6 12 PCU SPI DC Specification Table 21 29 PCU SPI DC Specification Symbol Parameter Min Max Units Notes Input High Voltage 1 25 V Input Low Voltage 0 693 V Output High Voltage 1 17 V VoL Output Low Voltage 0 45 V Output High Current 53 3 Igi Output Low Current 3 3 mA Input Leakage Current 2 2 Input Capacitance 2 5 pF 21 6 13 Power Management Thermal PMC and RTC DC Specification Table 21 30 Power Management 1 8V Suspend Well Signal Group DC Specification Sheet 1 of 2 Symbol Parameter Min Units Notes VREF T O Voltage V1P8A V Input High Voltage 0 65 VREF V 2 Input Low Voltage 0 5 0 35 VREF V 2 VoH Output High Voltage 0 45 x 1 8V V 1 VoL Output Low Voltage 0 45 V 1 Datasheet Volume 1 of 3 239 intel Electrical Specifications Table 21 30 Power Management 1 8V Suspend Well Signal Group DC Specification Sheet 2 of 2 Symbol Parameter Min Units Notes Output High Current 2 mA 1 Output Low Current 2 1 Notes 1 data in this table apply to signals ACPRESENT BATLOW PLTRST
288. pported HW Accelerated Video Decode Encode Codec Sheet 1 of 2 Codec Format Decode Features Encode Features Profiles MP L5 up to 1080p120 4kx2kp30 Profiles CBP MP HP HEVC H 265 Not Supported Profiles CBP MP HP ees L5 2 up to 1080p240 4kx2kp60 L5 1 up to 1080p120 4kx2kp30 Profiles HD MP HL Profiles HD MP HL 1080 60 1080 30 Profiles MP Profiles MP HP L5 2 up to 4kx3kp60 4kx2kp30 per eye L5 1 up to 4kx2kp30 1080p60 per eye 78 Datasheet Volume 1 of 3 Graphics Video and Display Table 8 5 Sheet 2 of 2 intel Codec Format Decode Features Encode Features VC 1 Profiles AP Not Supported L4 1080p60 WMV9 Profiles MP HL Not Supported 1080p30 JPEG MJPEG VP8 850 Mpps 420 640 Mpps 422 420 Mpps 44 850 Mpps 420 640 Mpps 422 420 Mpps 44 Up to 4kx2kp60 Up to 4kx2kp30 VP9 Up to 1080p30 Up to 720p30 Resolution Details on Supported HW Accelerated Video Decode Encode Codec Notes 1 9 media codec GPU Accelerator to be supported post for non Windows operating systems only 2 Resolution details for media codec on open source Linux OS depends on platform features and drivers used Decode Encode features may not align to Table 9 4 that is specific to Win8 1 and Win7 operating systems 88 Datasheet Volume 1 of 79 80 Graphics Video
289. pported Supported Supported Supported Supported Not Supported Not Supported MPEG2 Supported SW only Supported SW only Supported Supported Supported As Supported As Supported As Supported As MVC two separate two separate two separate two separate Supported Supported No streams via streams via streams via streams via pp available ACV ACV ACV ACV Supported VC 1 Supported Not Supported Supported Not Supported No KPI available Not Supported Supported WMV9 Supported Not Supported Supported Not Supported No KPI available Not Supported JPEG MJPEG Supported Supported Supported Supported Supported Supported VP8 Supported Not Supported Supported Not Supported Supported Supported VP9 Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported svc Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported MPEG4P2 Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported H 263 Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Sorenson Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Xvid DivX Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported AVS Not Supported Not Supported Not Supported Not Supported Not Supported Not Supported Note 9 media codec GPU Accelerator to be supported post for non Windows operating systems only Table 8 5 Resolution Details on Su
290. r Map ii This is used by software to define Flash vendor specific capabilities b The top 256B of the flash descriptor is reserved for use by the OEM 2 Security Capabilities a Descriptor based Region Restriction Hardware enforced security restricting master accesses to different regions i Flash Descriptor region settings define separate read write access to each region per master iii Flash Security Override Pin Strap 1 Removes all descriptor based security 2 Disables the write protection to the BIOS Protected Range 4 PR4 iv Each master can grant other masters read write access to its region b Protected Range Registers Datasheet Volume 1 of 3 135 m e n tel Platform Controller Unit PCU Overview i 2sets for each master of Lockable Protected Range registers that can restrict program register accesses from the same master ii Can span multiple regions iii Separate read and write protection iv Special case BIOS write protect values are received from Soft Strap and affect all masters C SMI Write Protection for BIOS i If enabled will cause an SMI if a program register access occurs The primary purpose of this requirement is to support SMI based BIOS update utilities d lllegal Instruction protection for instructions such as Chip Erase e Lockable software sequencing opcodes 3 SPI Flash Access a Direct Read Access b Program Register Access i Hardware Sequencing 1 Software Sequencing uses Hard
291. r than THERMTRIP in status registers to trigger thermal actions Associated with each event is a set of programmable actions 88 Datasheet Volume 1 of 3 Power Management n tel 6 Power Management 6 1 Power Management Features e ACPI System States support SO S3 S4 and S5 e Processor Core Package States support CO C7 SoC Graphics Adapter States support 00 03 e Support Processor and GFx Burst Dynamic I O power reductions disabling sense amps on input buffers tri stating output buffers Active power down of Display links 6 2 Power Management States Supported The Power Management states supported by the processor are described in this section 6 2 1 System States Table 6 1 General Power States for System States Graphics Sub Legacy Name Description CPU State Adapter states State FULL ON Processor operating Individual devices may be shut G0 S0 CO down to save power The different processor operating levels are Full on DO defined by Cx states Cx State Processor manages C State itself Auto DO Halt C6 Deep G0 S0 Cx Power Down D3 Display Off C7 Deep Power Down D3 Display Off Suspend To Disk STD The context of the system is maintained on the disk of the power is shut down except z 61 54 power for the logic to resume off Display Off The S4 and S5 states are treated the same Soft Off System context is not maintained All of the power i
292. rS de Rea a 226 21 6 1 Display DC 5 227 21 6 1 1 DisplayPort DC Specification 227 21 6 1 2 HDMI DC Specification eee eee hasard aka Ra 228 21 6 1 3 embedded DisplayPort DC 228 21 6 1 4 DisplayPort AUX Channel DC Specification 229 21 6 1 5 embedded Display Port AUX Channel DC Specification 229 Datasheet Volume 1 of 3 9 10 ntel 21 6 2 21 6 3 21 6 4 21 6 5 21 6 6 21 6 7 21 6 8 21 6 9 21 6 10 21 6 11 21 6 12 21 6 13 21 6 14 21 6 15 21 6 16 21 6 17 21 6 18 21 6 19 21 6 20 21 6 21 21 6 22 21 6 23 21 6 1 6 DDC Signal DC Specification 230 MIPI Camera Serial Interface CSI DC 232 SCC SDIO DC SpecifiCatiOn ea ce genre 232 SCC SD Card DC Specification nnn nnn 232 eMMC 4 51 DC Electrical 233 JTAG Specification eee xe nee perna rie Deka ERE ERE 234 DDR3L Memory Controller DC Specification 235 USB 2 0 Host DC Spec
293. ransmit FIFO holds data from the processor to be transmitted on the serial link and a 16 byte Receive FIFO buffers data from the serial link until read by the processor The UART includes a programmable baud rate generator which is capable of generating a baud rate of between 50 bps and 115 200 bps from a fixed baud clock input of 1 8432 MHz The baud rate is calculated as follows Baud Rate Calculation 1 8432 106 BaudRate 16 x Divisor The divisor is defined by the Divisor Latch LSB and Divisor Latch MSB registers Some common values are shown in Table 16 10 138 Datasheet Volume 1 of 3 Platform Controller Unit Overview Table 16 10 Baud Rate Examples intel Desired Baud Rate Divisor Divisor Latch LSB Register Divisor Latch MSB Register 115 200 1 ih Oh 57 600 2 2h Oh 38 400 3 3h Oh 19 200 6 6h Oh 9 600 12 Ch Oh 4 800 24 18h Oh 2 400 48 30h Oh 1 200 96 60h Oh 300 384 80h ih 50 2 304 Oh 9h The UART has interrupt support and those interrupts may be programmed to user requirements minimizing the computing required to handle the communications link Each UART may operate in a polled or an interrupt driven environment as configured by software 16 4 2 1 FIFO Operation 16 4 2 1 1 FIFO Interrupt Mode Operation Receiver Interrupt When the Receive FIFO and receiver interrupts are enabled FIFO Control Register bit 1b and Interrupt Enable Register IIR bit 1b
294. rations Separate transmit and receive FIFOs and serial data paths permit simultaneous transfers in both directions to and from the external peripheral depending on the protocols chosen Programmed I O can transfer data between The LPE core and the FIFO Data register for the TXFIFO The SoC Processor Core and the FIFO Data register for the TXFIFO The LPE core and the FIFO Data register for the RXFIFO The SoC Processor Core and the FIFO Data register for the RXFIFO The SoC Processor Core and the control or status registers The LPE core and the control or status registers DMA bursts can transfer data between Universal memory and the FIFO Data register for the TXFIFO Universal memory and the FIFO Data register for the RXFIFO Universal memory and the sequentially addressed control or status registers Datasheet Volume 1 of 3 Low Power Engine LPE for Audio 125 n tel 12 6 4 12 6 5 LPE and DMA FIFO Access The LPE or DMA access data through the Enhanced SSP Port s Transmit and Receive FIFOs An LPE access takes the form of programmed I O transferring one FIFO entry per access LPE accesses would normally be triggered off of an SSSR Interrupt and must always be 32 bits wide LPE Writes to the FIFOs are 32 bits wide but the serializing logic will ignore all bits beyond the programmed FIFO data size EDSS DSS value LPE Reads to the FIFOs are also 32 bits wide but the Receive data written into
295. rdware then increases TOCV by the last value written to TOCV During run time TOCV can be read to find out when the next periodic interrupt will be generated Software is expected to remember the last value written to TOCV Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel 16 11 1 2 1 16 11 1 2 2 Table 16 29 16 11 1 2 3 Example if the value written to TOCV is 00000123h then e An interrupt will be generated when the main counter reaches 00000123h TOCV will then be adjusted to 00000246h Another interrupt will be generated when the main counter reaches 00000246h TOCV will then be adjusted to 00000369h When the incremented value is greater than the maximum value possible for TOCV the value will wrap around through 0 For example if the current value in a 32 bit timer is FFFFOOOOh and the last value written to this register is 20000 then after the next interrupt the value will change to 00010000h If software wants to change the periodic rate it writes a new value to TOCV When the timer s comparator matches the new value is added to derive the next matching point If software resets the main counter the value in the comparator s value register must also be reset by setting TOC TVS To avoid race conditions this should be done with the main counter halted The following usage model is expected 1 Software clears GCFG EN to prevent any interrupts Software clears the main counter by writi
296. re the EOI command is issued to prevent a second interrupt from occurring In both the edge and level triggered modes the IRQ inputs must remain active until after the falling edge of the first internal INTA If the IRQ input goes inactive before this time a default IRQ7 vector is returned End of Interrupt EOI Operations An EOI can occur in one of two fashions by a command word write issued to the PIC before returning from a service routine the EOI command or automatically when the ICW4 AEOI bit is set to 1 Normal End of Interrupt In normal EOI software writes an EOI command before leaving the interrupt service routine to mark the interrupt as completed There are two forms of EOI commands Specific and Non Specific When a Non Specific EOI command is issued the PIC clears the highest ISR bit of those that are set to 1 Non Specific EOI is the normal mode of operation of the PIC within the SoC as the interrupt being serviced currently is the interrupt entered with the interrupt acknowledge When the PIC is operated in modes that preserve the fully nested structure software can determine which ISR bit to clear by issuing a Specific EOI An ISR bit that is masked is not cleared by a Non Specific EOI if the PIC is in the special mask mode An EOI command must be issued for both the master and slave controller Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel 16 15 1 5 2 Note 16 15 1 6
297. reg RCOMP Offset Register 0x20 family 0x1088 Varies lt family_name gt _family_rcomp_override_re RCOMP Override Register 0x20 family 9 0 108 Varies family name family rcomp value reg RCOMP Value Register 0x20 family 0x1090 Varies lt family_name gt _family_config_rcomp_reg family_config_rcomp_reg 0x20 family 0x1094 Varies lt family_name gt _family_config_reg gpio_family_configuration_register 0x20 family 0x4000 0x0000_0000 gpio_pad_bw_mask_31_0 GPIO Broadcast Data Mask bit Register 0x4004 0x0000_0000 gpio pad bw data 31 0 GPIO Broadcast Data Register 0x4008 0x0000 0000 gpio pad broadcast reg mask 0 gpio pad broadcast reg mask 0 0x4400 name PAD CFGO Pad Control Register 0 0x400 family 0x8 pad 0x4404 pad name PAD CFG1 Pad Control Register 1 0x400 family 0x8 pad 16 12 6 Strap Logic Hard straps are used to change settings during boot prior to any on die firmware or BIOS execution Hard straps also change settings prior to any flash reads unlike the soft straps which reside in the flash data While RSMRST_N is low all strap pins in input mode Weak pull ups or downs keep straps from floating during this time Strap values can be changed by driving the strap pins or using stronger pull resistors All Straps Sampled at Posedge of RSMRST_N After the straps are sampled the pins can be used functionally as pin changes will no longer affect the strapped values Refer t
298. rface 5 33 2 2 8 High Speed UART Interface 5 34 2 2 9 I C Interface 35 2 3 SIO Serial Peripheral Interface SPI Signals 35 2 3 1 PCU Fast Serial Peripheral Interface SPI 36 2 3 2 PCU Real Time Clock RTC Interface 36 2 3 3 PCU Low Pin Count LPC Bridge Interface 5 36 2 3 4 JTAG Interface Signals 37 2 3 5 PCI Express PCIe Signals tasa gana rank Rx Cea 37 2 3 6 NIIT 38 2 3 7 SMBUS SIQNAIS EET 38 2 3 8 Intel High Definition Audio Intel HD Audio 38 2 3 9 Power Management Unit PMU Signals 39 2 3 10 Speaker Signals cR eR DE RARE REA 39 2 3 11 Miscellaneous Signals receo SEDE AREE 40 2 4 56 amp 40 2 5 GPIO dip 42 3 Processor 6 49 3 1 SOC Transaction 49 3 2 Intel virtualization
299. rn around Phase The device tri states SERIRQ 16 8 2 7 4 Stop Frame After the data frames a Stop Frame will be driven by the interrupt controller SERIRQ will be driven low for two or three LPC clocks The number of clocks is determined by the SCNT MD register bit The number of clocks determines the next mode as indicated in Table 16 21 Datasheet Volume 1 of 3 157 Platform Controller Unit PCU Overview Table 16 21 SERIRQ Stop Frame Width to Operation Mode Mapping 16 8 2 7 5 16 8 2 7 6 Stop Frame Width Next Mode Two LPC clocks Quiet Mode Any SERIRQ device initiates a Start Frame Three LPC clocks Continuous Mode Only the interrupt controller initiates a Start Frame Serial Interrupts Not Supported There are three 3 interrupts on the serial stream which are not supported by the interrupt controller These interrupts are IRQ0 Heartbeat interrupt generated off of the internal 8254 counter 0 IRQ8 RITC interrupt can only be generated internally IRQ13 This interrupt floating point error is not supported The interrupt controller will ignore the state of these interrupts in the stream Data Frame Format and Issues Table 16 22 shows the format of the data frames The decoded INT A D values are ANDed with the corresponding PCI express input signals PIRQ A D This way the interrupt can be shared The other interrupts decoded by means of
300. rotection using PAVP2 0 HDCP 1 4 wired 2 2 wireless and Media Vault DRM Other Support 4x anti aliasing Graphics Burst enabled through energy counters Datasheet Volume 1 of 3 Introduction Interface Category SoC Features interfaces 3 Digital Display 5 0015 of 3 simultaneously displays eDP support on 2 port only DDI 0 1 Configurations DP Support on all 3 ports DDI 0 2 HDMI Support on all 3 ports DDI 0 2 eDP 2 7Gb s B Transfer Data Rate DP 2 7Gb s Display HDMI 2 97Gb s Max Resolution eDP 2560 x 1440 60Hz 3840 x 2160 30Hz HDMI 3840 x2 160 30Hz Support Audio on DP and HDMI only Other Support Intel Display Power Saving Technology Intel DPST Support Display Refresh Rate Switching Technology DRRS 3 LPE SSP I2S ports No Ports Note LPE is supported for Windows Operating System platforms only Decode MP3 AAC LC HE AAC v1 2 10 PRO Lossless Voice MPEG layer 2 Real Audio OggVorbis FLAC DD DD Encode MP3 AAC LC WMA DD 2channel Supports MSI and legacy interrupt delivery Support for ACPI D3 and DO Device States Intel High Supports up to a 6 streams three input three output Other 16 channels per stream 32 bits sample e 192 KHz sample rate 24 MHz HDA CLK supports 500 double pumped at 48Mb s SDIsingle pumped at 24Mb s Supports 1 5V and 1 8V mode Supports optional Immedia
301. rrupt SDMMC1_D2 Data Line Bit2 or Read Wait SDMMC1 D3 Data Line Bit 3 SD card Detect e MMC Port Command SDMMC1_CMD I O GPIO This signal is used for card initialization and transfer of commands It has two modes open drain for initialization and push pull for fast command transfer e MMC RCOMP This signal is used for pre driver slew rate compensation SDMMC1_RCOMP I O GPIO Datasheet Volume 1 of 3 91 intel Table 10 2 SDI SoC Storage O Signals Signal Name Description ype SDMMC2 yo cpro Clock The frequency may vary between 25 and 200 MHz SDMMC2_D 2 0 SDMMC2_D 3 _CD_N 1 0 GPIO SD Card Data bits 2 0 Bidirectional port used to transfer data to and from SD MMC card By default after power up or reset only D 0 is used for data transfer A wider data bus can be configured for data transfer using D 2 0 Note Unused data lines will be tri stated by the SoC logic SDIO Port Data bit 3 Bidirectional port used to transfer data to and from the SDIO device Also Card Detect Active low when device is present SDMMC2 CMD SDIO Port Command I O GPIO This signal is used for card initialization and transfer of commands It has two modes open drain for initialization and push pull for fast command transfer Table 10 3 SD Signals Signal Name SDMMC3 Direction Type Description SD Card Cloc
302. rupt message is sent to the decoder This message is decoded to indicate to the 8259 PIC which specific interrupt IRQ 3 4 14 or 15 was asserted or de asserted Interrupt Router The interrupt router aggregates the INT A D interrupts for each PCI mapped device in the SoC received from the interrupt decoder and the INT A D interrupts direct from the Serialized IRQ controller It then maps these aggregated interrupts to 8 PCI based interrupts PIRQ A H This mapping is configured using the IR 31 0 registers PCI based interrupts PIRQ A H are then available for consumption by either the 8259 PICs or the I O APIC depending on the configuration of the 8 PIRQx Routing Control Registers PIRQA PIQRB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH Routing PCI Based Interrupts to 8259 PIC The interrupt router can be programmed to allow PIRQA PIRQH to be routed internally to the 8259 as ISA compatible interrupts IRQ 3 7 9 12 and 14 15 The assignment is programmable through the 8 PIRQx Routing Control Registers PIRQA PIQRB PIRQC PIRQD PIRQE PIRQF PIRQG and PIRQH One or more PIRQs can be routed to the same IRQ input If ISA Compatible Interrupts are not required the Route registers can be programmed to disable steering The PIRQx lines are defined as active low level sensitive When PIRQx is routed to specified IRQ line software must change the IRQs corresponding ELCR bit to level sensitive mode The SoC internally inverts the
303. s Table 21 2 Storage Conditions Prior to Board Attach Symbol Parameter Min Max Device storage temperature when exceeded for E Tabsolute storage any length of time 25 125 Tshort term storage The ambient storage temperature and time for 20 9C 85 up to 72 hours The ambient storage temperature and time for Tsustained storage up to 30 months 5 06 40 The maximum device storage relative humidity RHsustained storage for up to 30 months N A 60 RH 24 C Notes 1 Specified temperatures are not to exceed values based on data collected Exceptions for surface mount re flow are specified by the applicable JEDEC standard Non adherence may affect processor reliability 2 Component product device storage temperature qualification methods may follow JESD22 A119 low temperature and JESD22 A103 high temperature standards when applicable for volatile memory 3 Component stress testing is conducted in conformance with JESD22 A104 4 JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 21 3 1 Post Board Attach The storage condition limits for the component once attached to the application board are not specified Intel does not conduct component level certification assessments post board attach given the multitude of attach methods socket types and board types used by customers Provided as general guidance only board
304. s G2 S5 shut down except power for the logic to restart A full boot is Off Display Off required to restart A full boot is required when waking The S4 and S5 states are treated the same Mechanical OFF System content is not maintained All power shutdown except for the RTC No Wake events are possible because the system does not have any power This state occurs G3 if the user removes the batteries turns off a mechanical switch Off Display Off or if the system power supply is at a level that is insufficient to power the waking logic When system power returns transition will depend on the state just prior to the entry to G3 Datasheet Volume 1 of 3 59 n e Power Management Table 6 3 shows the transitions rules among the various states Note Transitions among the various states may appear to temporarily transition through intermediate states These intermediate transitions and states are not listed in the table The following shows the differences in the sleeping states with regards to the processor s output signals Table 6 2 Platform Voltage Rails and Power Modes Power Type M ME 50 53 54 55 G3 VCC 0 and 1 0 5 1 3 On Off Off Off VGG 0 5 1 2 On Off Off Off 0 5 1 05 On On On Off 1 05 Fixed V1P15S 1 15 On Off Off Off V1P05A 1 05 On On On Off V1P24A 1 24 On On On Off VDDQ 1 35
305. s Refer to Section 1 1 Document Structure and Scope on page 19 for high level content listings of each volume Throughout this document the N series Intel Pentium processor and Intel Celeron processor families may be referred to simply as processor Throughout this document the N series Intel Pentium processor and Intel Celeron processor families refers to the Intel Pentium processor 3700 and Intel Celeron processors N3150 N3050 and N3000 Datasheet Volume 1 of 3 17 i ntel Introduction Figure 1 1 SoC Block Diagram Netbook 10 Atom Core Atom Core Atom Core Atom Core 1MiB L2 1MiB L2 HENZI Graphics and 10 10 m SoC c HOME Transaction 5 m Router 2 5 m 10 10 Internal Clock Clock 10 HD Audio 8259 10 I S PCM E os IO 10 10 u 10 10 E 10 2 IO IO D 5 IO IO IO IO IO IO IO IO IO IO 18 Datasheet Volume 1 of 3 Introduction n tel 1 1 Document Structure and Scope The following table summarizes the structure and scope of each volume of the processor Datasheet Refer to the Related Documents section for order information Table 1 1 Structure of the Processor Datasheet Sheet 1 of 2 Description Volume 1 Architecture Ballout Package and Electrical Specifications Introduction Physical Interfaces e Processor Core Integrated Clo
306. s is idle both the clock and data signals are pulled high through external pull up resistors on the bus When the master wants to start a transmission on the bus the master issues a START condition This is defined to be high to low transition of the data signal while the clock is high e When the master wants to terminate the transmission the master issues a STOP condition This is defined to be a low to high transition of the data line while the clock is high Figure 15 3 shows the timing of the START and STOP conditions e When data is being transmitted on the bus the data line must be stable when the clock is high 118 Datasheet Volume 1 of 3 Serial 510 Overview tel Figure 15 3 START and STOP Conditions 15 2 5 15 2 6 15 3 15 3 1 Table 15 3 Datasheet Volume 1 of 3 eee 1 Change of Data Allowed 1 1 1 1 Change of Data Allowed 1 L 1 Data Line Stable Data Line Valid Stop Condition The signal transitions for the START STOP conditions as depicted above reflect those observed at the output of the master driving the 12 bus Care should be taken when observing the data clock signals at the input of the slave s because unequal line delays may result in an incorrect data clock timing relationship References I C Bus Specification and User Manual Revision 03 http ics nxp com suppor
307. s mode software checks Receiver and Transmitter status using the Line Status Register LSR The processor polls the following bits for Receive and Transmit Data Service Receive Data Service The processor checks data ready LSR DR bit which is set when 1 or more bytes remains in the Receive FIFO or Receive Buffer Register DLL Transmit Data Service The processor checks transmit data request LSR THRE bit which is set when the transmitter needs data The processor can also check transmitter empty LSR TEMT which is set when the Transmit FIFO or Holding register is empty Autoflow Control Autoflow Control uses Clear to Send nCTS and Request to Send nRTS signals to automatically control the flow of data between the UART and external modem When autoflow is enabled the remote device is not allowed to send data unless the UART asserts nRTS low If the UART de asserts nRTS while the remote device is sending data the remote device is allowed to send one additional byte after nRTS is de asserted An overflow could occur if the remote device violates this rule Likewise the UART is not Datasheet Volume 1 of 3 Serial 510 Overview tel 15 3 3 2 4 15 3 3 2 5 allowed to transmit data unless the remote device asserts nCTS low This feature increases system efficiency and eliminates the possibility of a Receive FIFO Overflow error due to long interrupt latency Autoflow mode can be used in two ways
308. s of the LPE Audio Engine and three Synchronous Serial Protocol SSP ports These ports are used in PCM mode and enable simultaneous support of voice and audio streams over 125 The SoC audio subsystem also includes two DMA controllers dedicated to the LPE The LPE DMA controllers are used for transferring data between external memory and CCMs between CCMs and the SSP ports and between CCMs All peripheral ports can operate simultaneously Introduction The Enhanced SSP Serial Ports are full duplex synchronous serial interfaces They can connect to a variety of external analog to digital A D converters audio and telecommunication codecs and many other devices which use serial protocols for transferring data Formats supported include National Microwire Texas Instruments Synchronous Serial Protocol SSP Motorola Serial Peripheral Interface SPI protocol and a flexible Programmable Serial Port protocol PSP Datasheet Volume 1 of 3 105 m tel Low Power Engine LPE for Audio 125 12 6 2 12 6 3 106 The Enhanced SSPs operate in master mode the attached peripheral functions as a slave or slave mode the attached peripheral functions as a master and support serial bit rates from 0 to 25Mbps dependent the input clock Serial data formats range from 4 to 32 bits in length Two on chip register blocks function as independent FIFOs for transmit and receive data FIFOs may be loaded or emptied by the system pr
309. scriptor Mode ii BIOS accesses in non descriptor mode to a non binary flash size will not function properly iii Phe Flash Regions must be programmed to the actual size of the Flash Component s iv If using two flash components the first flash component the one with the Flash Descriptor must be of binary size The second flash component can be a non binary size If using only one flash component it can be non binary size v The value programmed in the Flash Descriptor Component Density must be set to the next power of two value larger than the non binary size 8 Reset Capabilities a RSMRST i The SPI Controller will implement a sideband handshake handshake is reset warn message with PMC when a host reset is requested to allow the SPI Flash controller to complete any outstanding atomic sequences and quiescence the SPI Bus Note There is no N parameter headers support on SoC DTR and 32 bit addressing is not supported 16 4 PCU Universal Asynchronous Receiver Transmitter UART This section describes the Universal Asynchronous Receiver Transmitter UART serial port integrated into the PCU The UART may be controlled through Programmed 1 0 Note Only a minimal ball count comprising receive and transmit signals UART port is implemented Further a maximum baud rate of only 115 200 bps is supported For this reason it is recommended that the UART port be used for debug purposes only Datasheet Volume 1 of 3 137
310. sor ISP The ISP Imaging Signal Processor includes a 64 way vector processor enabling high quality camera functionality Key features include support of three camera sensors 9 2 2 1 MIPI CSI 2 Ports The SoC has three MIPI clock lanes and six MIPI data lanes The Analog Front End AFE and Digital Physical Layer DPHY take these lanes and connects them to three virtual ports Two data lanes are dedicated to each of the rear facing cameras and the remaining data lane is connected to the front facing camera The MIPI interfaces follow the MIPI CSI 2 specifications as defined by the MIPI Alliance They support YUV420 YUV422 RGB444 RGB555 RGB565 and RAW 8b 10b 12b Both ports 84 Datasheet Volume 1 of 3 m MIPI CSI Camera Serial Interface and ISP n tel 9 2 2 2 9 2 2 3 support compression settings specified in MIPI CSI 2 draft specification 1 01 00 Annex E The compression is implemented in hardware with support for Predictor 1 and Predictor 2 Supported compression schemes e 12 8 12 e 12 7 12 e 12 6 12 10 8 10 e 10 7 10 10 6 10 The data compression schemes above use an X Y Z naming convention where X is the number of bits per pixel in the original image Y is the encoded compressed bits per pixel and Z is the decoded uncompressed bits per pixel 2 for Camera Interface The platform supports three 3 12 ports for the camera interface These ports are used to control the camera
311. sor supports CO C1 C1E C6 and C7 power states The following is a summary of the general rules for package C State entry These apply to all package C States unless specified otherwise Package C State request is determined by the lowest numerical core C State amongst all cores A package C State is automatically resolved the processor depending on the core idle power states and the status of the platform components e Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C State The platform may allow additional power savings to be realized in the processor For package C States the processor is not required to enter CO before entering any other C State The processor exits a package C State when a break event is detected Depending on the type of break event the processor does the following e If a core break event is received the target core is activated and the break event message is forwarded to the target core If the break event is not masked the target core enters the core CO state and the processor enters package CO If the break event is masked the processor attempts to re enter its previous package state If the break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C State the package returns to its previous C State
312. sp rn fu cJ i rh Mim ffr T3 arm DSx DATAOUT T TT 1 1 l SSPSP SFRMP 1 T ee o gt 55 5 5 0 Datasheet Volume 1 of 3 109 m tel Low Power Engine LPE for Audio 125 Table 12 5 Programmable Protocol Parameters Definition Symbol Register Bit Field Range Units Serial Clock Mode Drive Sample 12Sx_CLK Idle SSPSP SCMODE 0 Fall Rise Low 1 Rise Fall Low 2 Rise Fall High 3 Fall Rise High Serial Frame Polarity High or Low SSPSP SFRMP T1 Start Delay 0 7 Clock Period SSPSP STRTDLY T2 Dummy Start 0 3 Clock Period SSPSP DMYSTRT T3 Data Size 4 32 Clock Period SSCRO EDSS AND SSCRO DSS T4 Dummy Stop 0 3 Clock Period SSPSP DMYSTOP 15 I2Sx FRM Delay 0 88 Half Clock SPSP SFRMDLY Period T6 I2Sx FRM Width 1 44 Clock Period SSPSP SFRMWDTH End of Transfer Data State Low or bit 0 SSPSP ETDS The 25 FRM Delay must not extend beyond the end of T4 125 FRM Width must be asserted for at least 1 125 CLK and should be de asserted before the end of the T4 cycle for example in terms of time not bit values T5 T6 lt T2 T4 1 lt T6 lt T2 T4 T5 6 gt T1 1 to ensure that 125 is asserted for at least 2 edges of the 25 CLK The T1 Start Delay value should be pr
313. ssuing an EOI to clear the ISR bit the interrupt controller inhibits all lower priority requests In the special mask mode any interrupts may be selectively enabled by loading the Mask Register with the appropriate pattern The special mask mode is set by OCW3 ESMM 1b and OCW3 SMM 1b and cleared where OCW3 ESMM 1b OCW3 SMM Ob I O Mapped Registers The interrupt controller registers are located at 20h and 21h for the master controller IRQ 0 7 and at and Ath for the slave controller IRQ 8 13 These registers have multiple functions depending upon the data written to them Table 16 35 is a description of the different register possibilities for each address The register descriptions after Table 16 35 represent one register possibility Datasheet Volume 1 of 3 185 m n tel Platform Controller Unit PCU Overview Table 16 35 Registers Alias Locations Registers Original I O Location Alias I O Locations 24h 28h MICW1 2Ch MOCW2 20h 30h MOCW3 34h 38h 3Ch 25h 29h MICW2 2Dh MICW3 21h 31h MICW4 35h 1 39h 3Dh A4h A8h SICW1 ACh SoCW2 AOh BOh SoCW3 B4h B8h BCh 5 SICW2 ADh SICW3 Aih Bih SICW4 B5h SoCW1 B9h BDh ELCR1 4DOh N A ELCR2 4018 88 186 Datasheet Volume 1 of 3 Serial ATA SATA 17 Serial ATA SATA 17 1 Functional Feature Descriptions Feature Na
314. strophic trip points generated by DTSs based on predefined temperature setting defined in fuses Programmable Trips Four programmable trip settings that can be set by firmware software DTS Timing DTS should be enabled only after setting up SoC and system to prevent spurious counts from DTS to trigger thermal events P unit determines when DTS is enabled Figure 5 1 shows the various control signals needed for DTS operations DTS Mode of Operation YNN SOC cji VIPI5 124 3 Sram vig 1 24 IP3 amp DTSLDO Suply Voltage vccsfrlp 35 Jw or GENCore 1 19 Fuse Invalid Fuse Valid Fuse Invalid Fuse Valid Fuse Invalid 1 cck fuse bypass isfrbypass Ido fuse valid isfrpwrok r 7 aus r Pmu Ido sfr standby isfrprecharge E p 15u oo Pmu Ido sfr L CPU core DTS supplyXvccreg 1 0 thon cl gy 0 13 1 vo Mil Ohl fF dieiemp 8 0 dieiemp dy DTS ON Datasheet Volume 1 of 3 n tel 5 3 5 3 1 5 4 5 4 1 5 4 2 Note 5 5 5 5 1 5 5 2 H
315. t The main DSP hardware is a two multiplier multiply accumulate unit a register file LPE PR to hold pairs of 24 bit data items a register file LPE OR to hold 56 bit accumulator values an arithmetic logic unit to operate on the LPE PR and LPE OR values and a shift unit to operate on the LPE PR and LPE OR values The multiply accumulate unit also supports multiplication of 32 bit values from LPE OR registers by 16 bit values from LPE PR registers with the 48 bit result written or accumulated in the LPE OR register The instructions for the DSP subsystems are built from operations that are divided into two sets the slot O set and the slot 1 set In each execution cycle zero or one operations from each set can be executed independently according to the static bundling expressed in the machine code Memory Architecture The LPE core is configured to use local memory and local caches It has 80KB of Instruction Closely Coupled Memory CCM 160KB of Data CCM 48KB of Instruction Cache and 96KB of Data Cache The LPE core also has access to 4 of mailbox memory and external DRAM Datasheet Volume 1 of 3 99 m n tel Low Power Engine LPE for Audio 125 Figure 12 2 Memory Connections for LPE 12 3 3 12 3 4 12 3 5 100 Instruction tra d 80KB 48KB Audio Fabric Prefetch buffer 8x128B LPE shim registers Mailbox D Cach memory
316. t documents interface pdf i2c bus specification pdf Register Map Refer to Chapter 23 Register Access Method Registers and Chapter 24 Mapping Address Space Registers in Volume 2 for additional information SIO High Speed UART The SoC implements two instances of high speed UART controller that support baud rates between 300 and 3686400 Hardware flow control is also supported Signal Descriptions See Chapter 2 Physical Interfaces for additional details UART 1 Interface Signals Signal Name codd Description TARTI RAD mn MS 2 2 by other functions MS used by other functions VARTI SIT MS 2 2 used by other functions VARTI CTS 5 4 1 be used by other functions 119 t el Serial 1 0 SIO Overview Table 15 4 UART 2 Interface Signals Signal Name Eo Description MS dene 2 by other functions UART2_TXD n MS used by other functions MARIA ION En MS 22 used by other functions VARTA CTS 5 2 be used by other functions 15 3 2 Features 15 3 2 1 UART Function The UART transmits and receives data in bit frames as shown in Figure 15 4 e Each data frame is between 7 and 12 bits long depending on the size of data programmed and if parity and stop bits are enabled The frame begins with a s
317. t generated 1 1 X Slave SMI generated SMBUS SMI STS Datasheet Volume 1 of 3 149 Platform Controller Unit PCU Overview 16 6 2 5 Note 16 6 2 6 16 6 2 7 16 6 2 7 1 Note PCU SMB ALERT SMB ALERT is multiplexed with UARTO_TXD When enabled and the signal is asserted the SoC can generate an interrupt an SMI Using this signal as a wake event from S4 S5 is not supported SMBus CRC Generation and Checking If the SMB AUXC AAC is set the SoC automatically calculates and drives CRC at the end of the transmitted packet for write cycles and will check the CRC for read cycles It will not transmit the contents of the Packet Error Check Data Register SMB Mem PEC PEC register for CRC The SMB Mem HCTL PECEN bit must not be set if this bit is set or unspecified behavior will result If the read cycle results in a CRC error the SMB Mem HSTS DEVERR bit and the SMB AUXS CRCE bit will be set SMBus Slave Interface The SoC does not implement a complete SMBus slave interface Only the Host Notify Command is implemented to maintain specification compatibility Format of Host Notify Command The SoC tracks and responds to the standard Host Notify command as specified in the System Management Bus SMBus Specification Version 2 0 The host address for this command is fixed to 0001000b If the SoC already has data for a previously received host notify com
318. tal Input 1 RTC_X1 Anal This signal is connected to the 32 768 KHz crystal If no external natog crystal is used the signal can be driven with the desired clock rate I Crystal Input 2 RTC X2 Analog This signal is connected to the 32 768 KHz crystal If no external crystal is used the signal should be left floating Datasheet Volume 1 of 3 Platform Controller Unit Overview Table 16 23 Signals Sheet 2 of 2 Signal Name Direction Type intel Description RTC_RST I CMOS V3P3 RTC Reset RTC Reset An external RC circuit creates a time delay for the signal such that it will go high de assert sometime after the battery voltage is valid The RC time delay should be in the 10 20 ms range Contact your Intel representative for details When asserted this signal resets all register bits in the RTC well except GEN_PMCON1 RPS Note GEN_PMCON1 RPS will only be set when RTEST is asserted low Notes Unless registers are being cleared only to be done in the G3 power state the signal input must always be high when all other RTC power planes are on Notes In the case where the RTC battery is dead or missing on the platform the signal should be deasserted before the RSMRST signal is deasserted RTEST I CMOS V3P3 RTC Battery Test RTC Battery Test An external RC circuit creates a time delay for the signal such that it will go high de assert sometime after the
319. tart bit that is represented by high to low transition Next 5 to 8 bits of data are transmitted beginning with the least significant bit An optional parity bit follows which is set if even parity is enabled and an odd number of ones exist within the data byte If odd parity is enabled and the data byte contains an even number of ones The data frame ends with one one and one half or two stop bits as programmed by users that is represented by one or two successive bit periods of a logic one Figure 15 4 UART Data Transfer Start Data Data Data Data Data Data Data Data Parity Stop Stop Bit 0 2 3 4 6 7 Bit Bit 1 Bit 2 TXD or RXD pin LSB MSB Shaded bits are optional that users can program Each UART has a Transmit FIFO and a Receive FIFO and each holds 64 characters of data There are two separate methods for moving data into out of the FIFOs Interrupts and Polling 15 3 2 2 Clock and Reset The BAUD rate generates from base frequency of 50 MHz 120 Datasheet Volume 1 of 3 Serial 510 Overview tel 15 3 2 3 Baud Rate Generator The baud rates for the UARTs are generated with from the base frequency Fbase indicated in Table 15 5 by programming the DLH and DLL registers as divisor The hexadecimal value of the divisor is IER DLH 7 0 8 DLL 7 0 Fbase 44236800 Hz can be achieved by program
320. te Command Response mechanism Interface MIPI CSI 2 0 No Ports Up to 3 ports No Lanes Up to 6 Lanes Data Rate Up to 1 5Gbps Resulting in roughly 1 2Gbps s of actual pixels 2 0 Image Up to 5 MP Imaging Resolution 2 D Video Full HD 1080p30 Audio Full HD 1080p30 Support Image Signal Processor ISP with DMA and local SRAM Image data received by MIPI CSI interface is relayed to the ISP for Other processing Support lossless compressed image streams to increase the effective bandwidth without losing data Datasheet Volume 1 of 3 23 intel Introduction Interface Category SoC Features PCI Express Interface PCIe 2 0 Signaling Rate 5 0 or 2 5 GT s operation per root port No Lanes 4 Lanes and up to 4 PCIe root ports Flexible Root port configurations Support 4 x1 1 x2 2 x1 1 x4 2 x2 Default option 4 x1 Interrupts and Events Legacy INTx and MSI Interrupts General Purpose Events Express Card Hot plug Event System error Events Power Management Link State support for LOs L1 L2 Power down in ACPI S3 state L3 Serial ATA Other Support Virtual Channel for VCO only SATA Gen3 600MB sec SATA Gen2 300MB sec SATA Geni Interface 250MB sec No Ports 2 SATA ports Signaling Rate SATA Gen3 6Gbps SATA Gen2 3Gbps SATA Gen1 1 5Gbps Other Support Hot plug Support AHCI operations Application layer is configurab
321. ters Terminology Term Description AHCI Advanced Host Controller Interface ACPI Advanced Configuration and Power Interface ccm Closely Coupled Memory CCI Camera Control Interface Cold Reset reset is when PWROK is de asserted and all system rails except VCCRTC are powered CRU Clock Reset Unit CSI Camera Serial Interface DP DispayPot TT DTS Digital Thermal Sensor EIOB Electronic In Out Board EMI Electro Magnetic Interference 1 eDP embedded DisplayPort GPIO General Purpose IO High Definition Multimedia Interface HDMI supports standard enhanced or high definition video plus multi channel digital audio on a single cable HDMI transmits all Advanced HDMI Television Systems Committee ATSC HDTV standards and supports 8 channel digital audio with bandwidth to spare for future requirements and enhancements additional details available at http www hdmi org IGD Internal Graphics Unit Intel TXE Intel Trusted Execution Engine Intel TXE ISH Integrated Sensor Hub ISP Image Signal Processor LFM Low Frequency Mode LPC Low Pin Count LPDDR Low Power Dual Data Rate memory technology LPE Low Power Engine MFM Minimum Frequency Mode MIPI DSI MIPI Display Interface Specification Datasheet Volume 1 of 3 Introduction intel Term Description MPEG Moving Picture Experts Group MSI Message Signaled Interr
322. the Line Status Register LSR As stated in the register description LSR 0 is set as long as there is byte the receiver FIFO LSR 1 through LSR 4 specify which error s has occurred for the character at the top of the FIFO Character error status is handled the same way as interrupt mode The Interrupt Identification Register is not affected since IER 2 Ob e LSR 5 indicates when the transmitter FIFO needs data LSR 6 indicates that both the transmitter FIFO and shift register are empty e LSR 7 indicates whether there any errors in the receiver FIFO Use Base I O Address COM1 The base I O address for the COM1 UART is fixed to 3F8h Legacy Interrupt COM1 The legacy interrupt assigned to the COM1 UART is fixed to IRQ3 Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel 16 4 4 Note 16 4 5 16 5 UART Enable Disable The 1 UART be enabled or disabled using the UART_CONT COMIEN register bit By default the UART is disabled It is recommended that the UART be disabled during normal platform operation An enabled UART can interfere with platform power management I O Mapped Registers There are 12 registers associated with the UART These registers share eight address locations in the I O address space Table 16 11 shows the registers and their addresses as offsets of a base address Note that the state of the COM1 LCR DLAB register bit w
323. the Notify Data High Byte Register SMB Mem NDHB 37 ACK SoC 38 Stop External Master 16 6 2 8 Function Disable The SMBus interface may be disable by setting FUNC 015 2 SMB DIS 1b 16 6 3 References System Management Bus SMBus Specification Version 2 0 http www smbus org specs Datasheet Volume 1 of 3 151 m Platform Controller Unit PCU Overview 16 7 PCU Intel Legacy Block Overview The Intel Legacy Block iLB is a collection of disparate functional blocks that are critical for implementing the legacy PC platform features These blocks include e PCU iLB Low Pin Count LPC Bridge e PCU iLB Real Time Clock RTC PCU iLB 8254 Timers PCU iLB High Precision Event Timer HPET PCU iLB GPIO e PCU iLB Interrupt Decoding and Routing e PCU iLB I O APIC e PCU iLB 8259 Programmable Interrupt Controllers PIC The iLB also implements a register range for configuration of some of those blocks along with support for Non Maskable Interrupts NMI 16 7 1 Signal Descriptions Table 16 18 iLB Signals Direction T Signal Name Type Description NMI Non Maskable Interrupt This is NMI event indication into the SoC GPIO This signal is multiplexed and may be used by other functions 16 7 2 Features 16 7 2 1 Key Features The key features of various blocks are as follows e LPC Interfa
324. the RX FIFO from the RXD line is stored with zeroes in the MSBs down to the programmed data size The FIFOs can also be accessed by DMA bursts which must be in multiples of 1 2 or 4 bytes depending upon the EDSS value and must also transfer one FIFO entry per access When the SSCRO EDSS bit is set DMA bursts must be in multiples of 4 bytes the DMA must have the Enhanced SSP configured as a 32 bit peripheral The DMA s width register must be at least the SSP data size programmed into the SSP control registers EDSS and DSS The FIFO is seen as one 32 bit location by the processor For Writes the Enhanced SSP port takes the data from the Transmit FIFO serializes it and sends it over the serial wire 12512 0 DATAOUT to the external peripheral Receive data from the external peripheral 125 2 0 DATAIN is converted to parallel words and stored in the Receive FIFO A programmable FIFO trigger threshold when exceeded generates an Interrupt or DMA service request that if enabled signals the processor or DMA respectively to empty the Receive FIFO or to refill the Transmit FIFO The Transmit and Receive FIFOs are differentiated by whether the access is a Read or a Write transfer Reads automatically target the Receive FIFO while Writes will write data to the Transmit FIFO From a memory map perspective they are at the same address FIFOs are 16 samples deep by 32 bits wide Each read or write is to a 1 SSP sample Supported Formats T
325. tion to remove power from portions of the system agent Core break events are handled the same way as in package C6 State Graphics and Video Decoder C State GFX C State GC6 are designed to optimize the average power to the graphics and video decoder engines during times of idleness GFX C State is entered when the graphics engine has no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met the processor will power gate the Graphics and video decoder engines Intel Display Power Saving Technology Intel DPST The Intel DPST technique achieves backlight power savings while maintaining visual experience This is accomplished by adaptively enhancing the displayed image while decreasing the backlight brightness simultaneously The goal of this technique is to provide equivalent end user image quality at a decreased backlight power level 1 The original input image produced by the operating system or application is analyzed by the Intel DPST subsystem An interrupt to Intel DPST software is generated whenever a meaningful change in the image attributes is detected A meaningful change is when the Intel DPST software algorithm determines that enough brightness contrast or color change has occurred to the displaying images that the image enhancement and backlight control needs to be altered 2 Intel DPST subsystem applies an image specific enhancement to increase ima
326. tive Command Queuing NCQ Description Allows the device to reorder commands for more efficient data transfers Auto Activate for DMA Hot plug Support Collapses a DMA Setup then DMA Activate sequence into a DMA Setup only Allows for device detection without power being applied and ability to connect and disconnect devices without prior notification to the system Asynchronous Signal Recovery Provides a recovery from a loss of signal or establishing communication after hot plug 6Gb s Transfer Rate ATAPI Asynchronous Notification Capable of data transfers up to 6Gb s with Gen 3 SATA Note 1 and 2 support different transfer rates A mechanism for a device to send a notification to the host that the device requires attention Host and Link Initiated Power Management Capability for the host controller or device to request Partial and Slumber interface power states Staggered Spin Up DEVSLP Enables the host to spin up hard drives sequentially to prevent power load problems on boot Device Sleep DEVSLP is a host controlled hardware signal which enables a SATA host and device to enter an ultra low interface power state 17 2 Signal Descriptions Table 17 1 Signals Description Signal Name Direction Reference Description Serial ATA Port 3 0 General Purpose This is an input pin which can be configured as an interlock switch or as a general purpose I
327. to the master or slave controller base address with data bit 4 equal to 1 is interpreted as a write to ICW1 Upon sensing this write the PIC expects three more byte writes to 21h for the master controller for the slave controller to complete the ICW sequence A write to ICW1 starts the initialization sequence during which the following automatically occur 1 Following initialization an interrupt request IRQ input must make a low to high transition to generate an interrupt The Interrupt Mask Register is cleared IRQ7 input is assigned priority 7 The slave mode address is set to 7 A Special mask mode is cleared and Status Read is set to IRR ICW2 The second write in the sequence ICW2 is programmed to provide bits 7 3 of the interrupt vector that will be released during an interrupt acknowledge A different base is selected for each interrupt controller ICW3 The third write in the sequence ICW3 has a different meaning for each controller e For the master controller ICW3 is used to indicate which IRQ input line is used to cascade the slave controller Within the SoC IRQ2 is used Therefore MICW3 CCC is set to a 1 and the other bits are set to Os For the slave controller ICW3 is the slave identification code used during interrupt acknowledge cycle On interrupt acknowledge cycles the master controller broadcasts a code to the slave controller if the cascaded interrupt won ar
328. tput mask signal for write data z Output data is masked when DM is sampled HIGH DDR3 7 01 DDR3 coincident with that output data during a Write access DM is sampled on both edges of DQS Data Strobes The data is captured at the crossing point of DDR3 MO DOSI7 0 P each P and its compliment N during read and write 3 0 pe ELT transactions For reads the strobe crossover and data are DDR3 MO 00517 01 edge aligned whereas in the Write command the strobe crossing is in the centre of the data window Die Termination ODT signal going to DRAM in order to DDR3 ODT 1 0 DDR3 turn ON the DRAM ODT during Write I Resistor Compensation This signal needs to be DDR3 MO RCOMPD DDR3 terminated to VSS on board This signal is driven from external clock source I Reference Voltage DDR3 CA interface Reference Voltage DDR3 MO OCAVREF DDR3 I Reference Voltage DDR3 DQ interface Reference Voltage DDR3 MO ODQVREF DDR3 Datasheet Volume 1 of 3 69 m e n System Memory Controller Table 7 1 Memory Channel 0 DDR3L Signals Sheet 2 of 2 Direction Type Description Signal Name Notes 1 For Channel 1 signals refer to this table 8 1 where Channel 1 signals have the same functions and descriptions as of correspondent signals of channel 0 The only exception would be the signal name For Channel 1 signals they will be referred to as DDR3 1 Function where in Channel 0 they were referr
329. udio Dual issue static super scalar VLIW processing engine Mode less switching between 16 24 and 64 bit dual issue instructions Dual MACs which can operate with 32 x 16 bit and or 24 x 24 bit operands Inter Process Communication IPC mechanism to communicate with the SoC Processor Core including 4KB mailbox memory Datasheet Volume 1 of 3 97 Low Power Engine LPE for Audio 125 Flexible audio interfaces include three SSPs with I S port functionality for bi directional audio transfers 125 mode supports PCM payloads Frame counters for all I S ports High Performance DMA DMA IP to support multiple outstanding transactions Interleaved scatter gather support for Audio DMA transfers Clock switching logic including new frequency increments External timer function with an always running clock Communicates to SRAM and external RAM through OCP fabric Communicates with Audio peripherals using audio sub fabric and Inter Processor Communication IPC mechanism to communicate with the SoC Processor Core Note Since LPE firmware must reside at a stolen memory location on 512MB boundaries below 3GB it requires more than 512MB system memory The LPE firmware itself is 1MB and is reserved by BIOS for LPE use 12 2 1 Audio Capabilities 12 2 1 1 Audio Decode The Audio core supports decoding of the following formats MP3 AAC LC HE AAC v1 2 9 10 PRO Lossless Voice MPEG layer 2 R
330. upt MSI is a transaction initiated outside the host conveying interrupt information to the receiving agent through the same path that normally carries read and write commands MSR Model Specific Register as the name implies is model specific and may change from processor model number to processor model number 1 MSR is accessed by setting ECX to the register number and executing either the RDMSR or WRMSR instruction The RDMSR instruction will place the 64 bits of the MSR in the EDX EAX register pair The WRMSR writes the contents of the EDX EAX register pair into the MSR PCU Platform Controller Unit PEG PCIe PCI Express Graphics PCI Express PMU Power Management Unit PWM Pulse Width Modulation PSP Programmable Serial Protocol Rank A unit of DRAM corresponding to the set of SDRAM devices that are accessed in parallel for a given transaction For a 64 bit wide data bus using 8 bit x8 wide SDRAM devices a rank would be eight devices Multiple ranks can be added to increase capacity without widening the data bus at the cost of additional electrical loading RTC Real Time Clock SATA Serial ATA SCI System Control Interrupt SCI is used in the ACPI protocol SDRAM Synchronous Dynamic Random Access Memory SERR System Error SERR is an indication that an unrecoverable error has occurred on an I O bus SMBus System Management Bus
331. upts Between PMC and 101 12 4 3 Power Management Options for the LPE 102 12 4 4 External TIME TM T 102 12 57 MR 102 12 5 1 Y 102 12 5 2 38 4 MHZ Clock for EPE O 103 12 5 3 Calibrated Ring Osc 50 100 MHz Clock for 103 12 54 nnne 103 12 5 5 lt da Ee UR RA 103 12 56 M N Divider cee c 103 12 5 6 1 104 12 5 6 2 Accuracy and tere en daa a 105 12 5 6 3 Configuration cicero n troi 105 12 6 zb Le usa DULL EO 105 12 6 1 ce 105 12 6 2 SSP 106 12 6 3 Scu p 106 12 6 4 and DMA FIFO ACC6SS iere renean n n ike e Rm ARENA 107 12 6 5 S pported Formats risp poi pe IIa A EA UL ERIT NER REA a RR 107 12 6 5 1 Pro
332. ut down 54 S5 requests are treated the same so PMU SLP 55 signal is implemented Individual subsystems may have their own power plane For Devices Implementation Specific example GPIO signals may be used to control the power to disk drives audio amplifiers or the display screen The suspend power planes are generally left on whenever the system has a charged main battery or is plugged in to AC power In some cases it may be preferable to disable the suspend power planes 54 55 states to save additional power This requires some external logic such as an embedded controller to ensure Suspend PMU SUSPWRDNACK that a wake event is still possible such as the power button When the SeC is enabled it is advised that the suspend power planes not be removed Doing so may result in extremely long Sx exit times since the SeC if forced to consider it a cold boot which may in turn cause exit latency violations for software using the TXE Power Plane Control with PMU SLP 54 The PMU 54 output signal can be used to cut power to the system core supply as well as power to the system memory since the context of the system is saved on the disk Cutting power to the memory may be done using the power supply or by external FETs on the motherboard SLP 54 and Suspend To RAM Sequencing The system memory suspend voltage regulator is controlled by Glue logic The PMU SLP 54 signal should be use
333. ve Edge registers enable general purpose events on a rising and falling edge respectively This only applies to GPIOs set as input The Trigger Status register is used by software to determine if the GPIO triggered a GPE This only applies to GPIOs set as input and with one or both of the Trigger modes enabled Additionally there is one additional register for each 55 GPIO e Wake Enable This register allows 55 GPIOs to trigger wake event based on the Trigger registers settings Datasheet Volume 1 of 3 Platform Controller Unit Overview 16 12 4 16 12 4 1 GPIO Registers Memory Space Address Mapping intel addresses in Table 16 30 are offsets from the memory space base address also known as IOBASE Base address for CFIO memory space registers IOBASE are located in D31 F0 0x5B Each GPIO Community has 16 bit addressing with a possible address space of 64kb Table 16 30 Generic Community Address Ranges Offset Name Access Control Group 0x0000 Access Control Policy Registers GroupO 0x0200 GPIO Controller Wake Logic Registers Group1 0x0300 GPIO Controller IMG Registers Group2 0x0400 Community Registers Group3 0x0500 PWM Registers Group4 0x600 0x62F DLL Control Registers Southeast Only 0 0600 OxOFFF Reserved area for expansion None 0x1000 Family Broadcast Write Registers Group5 0x1080 FamilyO Registers Group6 0x1100 Family1 Registers 0x4000
334. ware to provide the basic instructions of read write and erase ii Software Sequencing 1 Allows software to use any legal Opcode c Support for Boot BIOS on SPI or LPC FWH i Non boot BIOS that is accessible through program register only can be used on SPI when boot BIOS is located on some other interface Note No validation has been done with BIOS on LPC Reference design uses SPI d Prefetching Caching to improve performance i Separate 64B prefetch cache each for HOST and TXE direct read accesses 4 SFDP Parameter Discoverability 5 Flash Component Capabilities a In Descriptor mode supports two SPI Flash components using two separate chip select pins 50 and 51 Only one component supported in non descriptor mode i Components must have the same erasable block sector size ii Each component can be up to 16MB 32MB total addressable using 24 bit addressing b 1 8V SPI I O buffer VCC c Supports the SPI Fast Read Write instruction and frequencies of 20 MHz 33 MHz and 50 MHz Supports the SPI Dual Output Fast Read Write instruction with frequencies of 20 MHz 33 MHz and 50 MHz 136 Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel d Supports the SPI Dual and Quad Output Fast Read Write instruction with frequencies of 20 MHz 33 MHz and 50 MHz e Uses standardized Flash Instruction Set f Supports non power of two flash sizes with the following restrictions supported in De
335. wback Clock delay compensation is less effective at compensating for main board delay c Soft Strap and Register Requirements Soft Strap LPCCLK SLC Ob Configuration is reflected by register bit LPCC LPCCLK SLC Ob Soft Strap LPCCLK1 Ob LPC CLK 1 disabled or 1b CLK 1 enabled Configuration is reflected by register bit LPCC LPCCLK1EN Ob LPC CLK 1 disabled or 1b ILB LPC CLK 1 enabled On the main board In this configuration CLK 0 is looped back to CLK 1 on the main board a Benefit Clock delay compensating in more effective at compensating for main board delay b Drawback Only LPC is available for system clocking CLK 1 must be disabled c Soft Strap and Register Requirements Soft Strap LPCCLK SLC 1b Configuration is reflected by register bit LPCC LPCCLK SLC 1b Soft Strap Ob ILB LPC CLK 1 disabled Configuration is reflected by register bit LPCC LPCCLK1EN 0b Datasheet Volume 1 of 3 159 m n tel Platform Controller Unit PCU Overview 16 8 3 2 16 8 3 2 1 16 8 3 2 2 16 8 3 3 16 8 4 16 9 16 9 1 LPC Power Management Clock Enabling The LPC clocks can be enabled or disabled by setting or clearing respectively the LPCC LPCCLK 1 0 EN bits Clock Run Enable The Clock Run protocol is disabled by default and should only be enabled during operating system run time
336. y Controller DC Specification on page 235 Section 21 6 8 USB 2 0 Host DC Specification on page 235 Section Section 21 6 11 LPC DC Specification on page 238 Section 21 6 12 PCU SPI DC Specification on page 239 Section 21 6 13 Power Management Thermal PMC and RTC DC Specification on page 239 Section 21 6 14 SVID DC Specification on page 241 Section 21 6 15 GPIO DC Specification on page 242 Section 21 6 16 SIO SPI DC Specifications on page 242 Section 21 6 17 SIO I2C DC Specification on page 242 Section 21 6 18 SIO UART DC Specification on page 243 on page 237 Datasheet Volume 1 of 3 m e Electrical Specifications n tel e Section 21 6 19 I2S Audio DC Specification on page 243 e Section 21 39 HD Audio DC Specifications for 1 5V on page 243 e Section 21 6 21 SMBus System Management DC Specification page 244 e Section 21 6 22 PCI Express DC Specification on page 244 e Section 21 6 23 Serial ATA SATA DC Specification page 244 Note Care should be taken to read all notes associated with each parameter 21 6 1 Display DC Specification DC specifications for display interfaces e Section 21 6 1 1 DisplayPort DC Specification on page 227 e Section 21 6 1 2 HDMI DC Specification on page 228 e Section 21 6 1 3 embedded DisplayPort DC Specification on page 228 e Section 21 6 1 4 DisplayPort AUX Channel DC Specification on page 229 e Section 21 6 1 5
337. y using a jumper on RST Z or a GPI Implementations should not attempt to clear CMOS by using a jumper to pull low Using RSTZ to Clear CMOS A jumper RTC_RST can be used to clear CMOS values as well as reset to default the state of those configuration bits that reside in the RTC power well When the RSTZ is strapped to ground all the bits of PMCON1 except 1 5 which is only set by assertion TEST assertion register bit will be set and those configuration bits in the RTC power well will be set to their default state BIOS can monitor the state of this bit and manually clear the RTC CMOS array once the system is booted The normal position would cause 5 to be pulled up through a weak pull up resistor Table 16 24 shows which bits are set to their default state when RST is asserted This RST jumper technique allows the jumper to be moved and then replaced while the system is powered off RSM_RST signal needs to toggle in order for bit status to propagate and reflect in the GEN PMCON registers Datasheet Volume 1 of 3 m Platform Controller Unit PCU Overview n tel Table 16 24 Register Bits Reset RTC_RST Assertion 16 9 3 3 Note Warning 16 9 4 16 9 5 Note Register Bit Bit s Default State RCRB GENERAL CONTROL TS 1 xb GEN
338. y voltage 1 418 1 583 V Input High Voltage 0 6 Vcc V VIL Input Low Voltage E 0 4 Vcc V Vou Output High Voltage 0 9 Vcc V 1 VoL Output Low Voltage 0 10 Vcc V 2 Input Leakage Current 10 uA 3 4 Input Pin Capacitance 7 5 Pin Inductance 20 nH 5 Notes 1 At Iout 500 pA 2 At Tout 1500 pA 3 At 0 lt Vin lt Vcc 4 For SDI Serial Data In buffers or in general any bidirectional buffer with tri state output input leakage current also include hi Z output leakage 5 This is a recommendation not an absolute requirement The actual value should be provided with the component data sheet Table 21 40 HD Audio DC Specification for 1 8V Symbol Parameter Min Units Notes Supply voltage 1 71 P 1 89 Input High Voltage 0 6 Vcc Vu Input Low Voltage 0 35 Vcc V Output High Voltage 0 9 Vcc V 1 VoL Output Low Voltage 0 10 Vcc V 2 Input Leakage Current 210 3 4 Input Pin Capacitance 7 5 Pin Inductance 20 nH 5 Notes 1 AtIout 500 pA 2 AtIout 1500 pA 3 At 4 For SDI Serial Data buffers or general any bidirectional buffer with tri state output input leakage current also include hi Z output leakage 5 This is a recommendation not an absolute requirement The actual value should be

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