SD Bus Core.book
Contents
1. Nios Il Software Support El Camino GmbH Basic Concept The SD Bus peripheral is integrated into the HAL generic device model classes as a FLASH memory device The HAL provides a generic device model for nonvolatile flash memo ry devices such as SD cards The HAL API provides functions to write data to flash For example you can use these functions to implement a SD based filing subsystem Although it is not necessary for general parallel FLASH devices the HAL API also provides functions to read flash For most flash devices programs can treat the flash memory space as simple memory when reading and do not need to call special HAL API functions If the flash device has a special protocol for reading data just like SD cards you must use the HAL API to both read and write data The following two NIOS II HAL APIs provide a different level of ac cess to the flash E Simple flash access a simple API for writing buffers into flash and reading them back which in general does not preserve the prior contents of other flash erase blocks E Fine grained flash access finer grained functions for programs that need control over writ ing or erasing individual blocks This functionality is generally required for managing a file subsystem With SD cards you can write single bytes without the need to erase whole blocks or sectors So even when using simple flash access all data within a sector or block is preserved even when not writ2. SD BUS Core EI Camine with Avalon Interface Training Engineering Consultancy General Description Features El Camino GmbH April 2015 Version 3 20 The SD BUS Core with Avalon Interface allows for Qsys systems to access standard SD MMC or eMMC flash based memory devices It comes with low level SD Card driver routines for Nios II and is inte grated into the HAL generic device model classes as a FLASH memory device Therefore you do not need to write any additional low level code to read or write raw data from or to SD cards El Camino offers an op tional stand alone FAT 12 16 32 file system that can be used to read or write files on SD cards from a NIOS system Furhtermore the core is im plemented such that it works with the standard sdhci sdhci pltfm Linux drivers e g on Altera SoC devices Figure 1 Block Diagram FPGA Avalon CPU or Bridge SD BUS Core from El Camino Other Avalon Masters Slaves Avalon Switch Fabric E Supports Secure Digital Card SD Multimedia Card MMC and embedded Multimedia Card eMMC E bit and 4 bit wide bus operation Compatible with SD Host Controller Standard Specification V3 01 Supports High Capacity SD Memory Cards SDHC Supports High Speed Mode SDHS with up to 50 MHz SD Clock rate Low level Nios II drivers included Optional stand alone FAT12 FAT16 FAT32 file system available Compatible with Linux sdhci sdhci pltfm drivers D
3. Signal SD MMC Pin Function SPI Bus Mode Function SD Bus Mode 3 SD_SD1 SD_DAT 2 9 Reserved Data Line Bit 2 4 SD_CMD SD_CMD 2 Host to Card Commands and Data Command Response 5 SD_D1 SD_DAT 1 8 Reserved Data Line Bit 1 6 SD_CLK SD_CLK 5 Clock Clock 7 SD_SWWP_A WP default 8 SD_DAT SD_DAT 0 7 Card to Host Data and Status Data Line Bit 0 9 SD_SWWP_B 11 SD_SWCL A CDn default 12 SD_D3CS_A SD_DAT 3 default 1 Chip Select Active Low Card Detect Data Line Bit 3 13 SD_SWCLB 14 SD_D3CS_B 1 Chip Select Active Low Card Detect Data Line Bit 3 The SD card connector on older Altera Nios II Embedded S Evaluation Kit NEEK has only one data line connected SD_DAT 0 These NEEKSs therefor only supports the 1 bit mode of this core and is limited to about one fourth of the maximum data throughput performance Because of the buffers in the SD signal paths the timing for high speed mode cannot be met on the NEEK Custom Please contact El Camino if you require any custom solutions based on Solutions iia El Camino GmbH 15 SD BUS Core with Avalon Interface Notes Gi EI Camino Training Engineering Consultancy El Camino GmbH Landshuter Str 1 D 84048 Mainburg Germany Telefone 49 8751 8787 0 Telefax 49 8751 842876 E mail info elca de http www elcamino de El Camino GmbH El Camino GmbH Training Engineering Consultancy DIGILAB 10K10 DIGILAB picoMAX DIGILAB 10Kx240 DIGILAB 20Kx240 DIGILAB
4. megAPEX and other names of El Camino pro ducts product features and services are trademarks and or service marks of El Camino GmbH in Ger many and other countries Altera APEX Stratix Quartus NIOS and other names of Altera products product features and services are trademarks and or service marks of Altera Corporation in the United States and other countries Other product and company names mentioned in this document may be the trademarks of their respective owners No warranties This documentation is as is without any express or implied warranty of any kind inclu ding warranties of merchantability no infringement of intellectual property or of fitness for any particu lar purpose In no event shall El Camino or its suppliers be liable for any damages whatsoever including without limitation damages for loss of profits business interruption or loss of information arising out of the use of or inability to use this documentation even if El Camino has been advised of the possibility of such damages Because some jurisdictions prohibit the exclusion or limitations of lia bility for consequential or incidental damages some of the above limitations may not apply to you El Camino further does not warrant the accuracy or completeness of the information text graphics or other items contained in this document El Camino may make changes to these materials or to the pro ducts described therein at any time without notice El Camino makes no com
5. signal active low aym ml_waitrequest_n input Avalon wait request signal active low El Camino GmbH Table 2 Qsys Component Settings SD BUS Core with Avalon Interface Parameter Avalon System Clock Frequency SYSTEM_CLOCK_ FREQUENCY Legal Values 1 512 Radix Integer MHz Description This parameter is used to set the frequency of the Avalon clock csi_c0_ clk driven from the Avalon System Intercon nect Fabric SIF into the core The parameter needs to match the actual frequency of the clock connected to the core in Qsys The setting is used to pass the system clock frequency of the core to the software and calculate the nec cessary clock divider Card Interface Bus Width SD_BUS_WIDTH 1 bit mode only 4 bit mode Integer This parameter is used to set the maximum SD Bus width used by the core and the software driver Legal values for this parameter are 1 or 4 If set to 1 only SD_DAT 0 will be used for communication with the SD card SD_DAT 3 1 will still be present and can be left uncon nected A setting of 1 can be used for example with the Altera Nios Embedded Evaluation Kit NEEK which has only SD_DAT 0 connected Enable SD MMC OKEMO High Speed Support SD_HS_SUPPORT ON 1 high speed off high speed on Integer This parameter is used to turn on or off high speed mode High speed mode uses up to 50 MHz clock rates and requires careful routing of the SD sig
6. MA support for high data throughput SD BUS Core with Avalon Interface Applications Deliverables Architecture Specification The SD Bus Core is ideal for applications where a mobile standard and exchangeable storage media is required for NIOS II or SoC applica tions Together with our Windows utility it is easy to exchange raw data between a NIOS II application and the PC platform When used together with the El Camino SD MMC loader FPGA con figuration data can be combined with application data or program stor age on a removable common and compact storage media Qsys Compliant IP core in Verilog Low level Nios II software drivers for initialization read and write access Windows Utility for reading and writing raw data on request Figure 2 SD MMC Bus Core Block Diagram clock reset Avalon Slave Avalon Interface o p n Cc gt x El Camino GmbH CDn WP Register LED Set SD_CLK SD_CMD SD Bus Interface The SD Bus core has the following interfaces E Avalon Interface Control Signals clock and reset signals driven from the Avalon switch fabric and interrupt signal driven to the Avalon switch fabric SD BUS Core with Avalon Interface El Camino GmbH Avalon Slave Interface read and write access to the core registers and the data buffer for non DMA data transfers Avalon Master Interface connection to a DMA controler inside the core for SDMA
7. Single operation DMA support as specified in the SD Host Controller Standard Specification E SD Bus Interface CDn WP LED SD CLK SD CMD optional unidirectional signals i _0 _en SD_DAT3 SD_ DATO optional unidirectional signals i _0 _en The registers provide an interface to the SD Bus core and are visible via the Avalon slave port The SD_CLK SD_CMD SD_DAT3 SD_DATO CDn and WP ports provide the hardware interface to the SD card The core logic is synchronous to the clock input provided by the Avalon interface The Avalon clock is divided to generate the SD_CLK output Table 1 Port Description SD BUS Core with Avalon Interface logic 1 gt card is write protected Port Direction Function Connect to Clock Signal to the SD MMC card This clock is derived from the system SD card SD_CLK output clock by a parameterizable clock divider The frequency determines the data n5 rate and is set automatically by the sofware driver pin Bidirectional Command Response Signal SD card SD_CMD input output Optional Unidirectional Signals for implementing external tri state drivers in SD_CMD o SD_CMD i SD_CMD en enable when high pn SD card Bidirectional Data signals SD_DAT3 pin 1 SD_DAT 3 0 input output Optional unidirectional signals for implementing external tri state drivers SD_DAT2 pin 9 o 3 0 i 3 0 en 3 0 enable when hi pin SD_DAT_o 3 0 SD_DAT_i 3 0 SD_DAT_e
8. alon Memory Mapped Slave osc_clk 0x20_1000 0x0020 10f p p Avalon Memory Mapped Master Double click 0 m SD BUS Core with Avalon Interface Connectin g The following picture shows how to connect the SD Bus Core to an SD card If the SD BUS WIDTH parameter is set to 4 the software driver the Core to an will use the 4 bit mode and all four data signals SD_DAT 3 0 need SD Card to be connected Figure 5 Connecting the SD Bus Core VCC VCC VCC VCC VCC VCC VCC VCC 1 SD Bus Core csi_clockreset_reset_n SD_DAT1 csi_clockreset_clk SD_DATO Beene ins_irq0_irq SD_CLK top view XSS i P i Jaaa SD_CMD Avalon MM DAT3 SD_DAT3 Slave SD_DAT2 WP Avalon MM Master 1 Recommended Pull up resistors are 10kOhm El Camino GmbH 8 SD BUS Core with Avalon Interface Register Model An Avalon master peripheral controls and communicates with the SD Bus core via registers devided into 9 parts as listed below Figure 6 Coarse Register Map Register Set El Camino GmbH 9 SD BUS Core with Avalon Interface Table 3 Fine Register Map for SD Bus Core Offset 15 8 7 0 Offset 15 8 7 0 002h SDMA System Address High 000h SDMA System Address Low 006h Block Count 004h Block Size 00Ah Argument 008h Argument0 O0OEh Command 00Ch Transf
9. aturing a NIOS II CPU and the SD Bus Core A Qsys cyclonelll_ Qq x Project 0 New Component El Camino GmbH a System Library Bridges Bridges and Adapters amp Clock and Reset D E DSP Embedded Processors Interface Protocols g D H a e Merlin Components E Peripherals PLL Qsys Interconnect Verification Window Bridge E E E 4 m ELCA SD Host Controller Configuration amp Programming Memories and Memory Controller Microcontroller Peripherals El Camino GmbH QM WOKS File Edit System Generate View Tools Help eee o erel t System Contents z A AddressMap amp Project Settings o o Use Connections Name Description Export Clock Base End IRQ E E cpu Nios II Processor dk data_master Avalon Memory Mapped Master osc_clk IRQ 0 IRQ 316m instruction_master Avalon Memory Mapped Master dk jtag_debug_module Avalon Memory Mapped Slave dk 0x20_0800 0x0020_0fff E E ssram Generic Tri State Controller dk uas Avalon Memory Mapped Slave osc_clk Ox10_0000 Ox001f f ffF tom Tristate Conduit Master dk E E tristate_pinSharer Tri State Conduit Pin Sharer dk a tom Tristate Conduit Master osc_ck tes0 Tristate Conduit Slave dk e E tristate_bridge Tri State Conduit Bridge dk tes Tristate Conduit Slave osc_clk ed E controller ELCA SD Host Controller co s0 Av
10. er Mode 012h Response1 010h ResponseO 016h Response3 014h Response2 01Ah Response5 018h Response4 O1Eh Response7 01Ch Response6 022h Buffer Data Port 020h Buffer Data PortO 026h Present State 024h Present State 02Ah Wakeup Control Block Gap Control 028h Power Control Host Control 02Eh Software Reset Timeout Control 02Ch Clock Control 032h Error Interrupt Status 030h Normal Interrupt Status 036h Error Interrupt Status Enable 034h Normal Interrupt Status Enable 03Ah Error Interrupt Signal Enable 038h Normal Interrupt Signal Enable 03Eh 03Ch Auto CMD12 Error Status 042h Capabilities 040h Capabilities 046h Reserved 044h Reserved 04Ah Maximum Current Capabilities 048h Maximum Current Capabilities 04Eh Reserved 04Ch Reserved 052h Force Event for Error Interrupt Status 050h Force Event for Auto CMD12 Frror Status 054h ADMA Frror Status 1 05Ah ADMA System Address 31 16 1 058h ADMA System Address 15 0 1 OSEh ADMA System Address 63 48 1 05Ch ADMA System Address 47 32 1 OF2h OFOh ee OFEh Host Controller Version OFCh Slot Interrupt Status white areas not implemented in current version of the core Register Description Please see the SD Host Controller Standard Specification Version 3 00 for a detailed register description El Camino GmbH 10 SD BUS Core with Avalon Interface Resource The following results are based on synthesis and place amp route in age Quartus II Ver
11. g writing x always required always required drive letter of SD card file dat always required always required source or desitination file name default write data from file dat to SD card 5 x when omitted read data from SD card and store in file dat o offset 0 0 decimal byte offset from address 0 of SD card b bytes 512 size of file dat number of bytes to read or write h display on line help it Prototyp ng Figure 7 Prototyping Hardware The IP core can be ordered with a small prototyping board that can be used together with El Camino or Altera NIOS boards that feature a San ta Cruz prototyping header The schematics of the prototyping hardware El Camino GmbH 14 SD BUS Core with Avalon Interface can be found at the end of this document The SPI mode chip select as well as the card detect and write protect switch signals can each be rout ed to one of two connector pins This allows to cascade up to two SD prototyping boards In such a cascaded configuration some signals need to be routed individually Soldering bridges allow to put individual pro totyping boards into an A or B configuration and de activate the pull up resistors on one of them On a request basis the prototyping boards can be outfitted with connectors that support cascading The following table lists the signal mapping Table 7 J2B Pin Descriptions J2B Schematic Connect to IP Core eas Signal
12. h API Functions in the Nios II Software Developer s Handbook shows the usage of all of these func tions in one code example Fine Grained Flash Access There are three additional functions that provide complete control over writing flash contents at the highest granularity alt_get flash info alt_erase_flash_block and alt write flash_block These functions are implemented for compatibility reasons with other flash devices however are not necessary when accessing SD cards This core is compatible with the Linux sdhci sdhci pltfm drivers It has been tested on an Altera Cyclone V SoC development kit The Altera SoC device tree flow will automatically add the necessary parameters to the device tree For the sdhci pltfm driver to work with the device tree flow the follow ing patch from Alistair Pobble is required PATCH 1 5 SDHCI Add a generic registration to the SDHCI plat form driver 13 SD BUS Core with Avalon Interface Command Line The utility Nd_rd_wri allows to read and write raw data from and to SD Tool cards The tool provides its own documentation in the form of a help 00 page accessible from the command line To view the help open a DOS Command Shell and type the following command sd_rd_wr h Usage sd rd wr x file dat w o offset b bytes h Table 6 sd_rd_wr utility command line options Default when ommitted Paramter Description readin
13. ing the complete sector or block Only for compatibility reasons with other flash devices it might make sense to use fine grained flash access even with SD cards The API functions for flash devices are defined in sys alt_flash h Since the SD Bus core uses DMA to transfer data to and CS from SD cards it is important to consider cache memory coherence when using a NIOS CPU that features a data cache It is therefor strongly recommended to allocated the data buffers for read and write functions in uncached memory or to bypass the cache by setting address bit 31 to ili whenever accessing the read or write buffers from the CPU A flush of the data cache before calling the flash HAL functions is not sufficient as a single cache line may overlap with variables used inside the driver and the read or write buffers 12 SD BUS Core with Avalon Interface Linux Software Support El Camino GmbH Simple Flash Access This interface comprises alt _flash_open_dev alt_write_flash alt_read_flash and alt_flash_close_dev Writing and reading can start at any address and can be of any length as long as one stays within the boundarys of the SD card For maximum compatibility with older SD cards however it is recommneded to start writing only on block boundaris The block size can be determined with the lt get flash info i function The typical block size for most SD cards is 512 bytes The code i Example Using the Simple Flas
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15. n 3 0 enable when high SD_DAT pin 8 SD_DATO pin 7 Card Detect signal form the SD card socket SD card connector CDn input logic 0 gt card is present i card detect switch logic 1 gt socket empty Write Protect signal from the SD card socekt SD card connector WP input logic 0 gt card is not write protected write protect switch Common Avalon Control Signals csi_c0_clk input Avalon clock signal automatically csi_c0_reset_n input Avalon reset signal low adctive connected by anne f Qsys ins_i0_irq output Avalon interrupt signal Avalon MM slave interface avs_sl_writedata 31 0 input Avalon write data bus avs_sl_readdata 31 0 output Avalon read data bus avs_sl_address 5 0 input Avalon address bus Z automatically avs_sl_byteanable_n 3 0 input Avalon byteenable signals active low connected by sys avs_sl_chipselect input Avalon chipselect signal Qsy avs_sl read n input Avalon read signal active low avs_sl_write_n input Avalon write signal active low Avalon MM master interface avm_m1_writedata 31 0 output Avalon write data bus avm_m1l_readdata 31 0 input Avalon read data bus avm_m1_address 31 0 output Avalon address bus automatically avm_m1_byteenable_n 3 0 output Avalon byteenable signals active low connected by sys avm_ml read _n output Avalon read signal active low Qsy avm_ ml write n output Avalon write
16. nals Not every hard ware implementation will support high speed mode which is why automatic switching to high speed mode can be turned off here OFF 0 Export Unidirectional Card Interface UNIEN ON 1 bidirectional unidirectional Integer This parameter allows to export separate input output and enable signals for CMD and DAT With these signals exter nal tri state drivers can be implemented Figure 3 Qsys Component GUI qi r 4 ELCA SD Host Controller elca_sd_host_controller_O ELCA SD Host Controller elca_sd_host_controller Block Diagram Parameters E Show signals elca_sd_host_controller_0 interrupt_sender elca_sd_host_controller Avalon System Clock Frequency 50 Card Interface Bus Width Enable SD MMC High Speed Support OFF y Export Unidirectional Card Interface OFF y 4x El Camino GmbH SD BUS Core with Avalon Interface Integration into Qsys System The following picture shows a typical Qsys system with a NIOS proces sor and an SD Bus core The master DMA interface connections of the SD Bus core is highlighted The Avalon MM Slave port should be connected to the CPU so that it can access the registers in the core The Avalon MM Master port needs to be connected to the memory that holds the read and write buffers passed to the HAL flash API Figure 4 Typical Qsys system fe
17. sion 13 1 The maximum frequency of the data transfer is Utilization and limited by both the maximum system frequency of the SOPC builder Perform ance block and the maximum SD_CLK frequency of the SD card Table 4 Resources Ressource r 2 Maximum System Device Family Clock Logic Memory in Bits Cyclone V 853 ALMs 8192 170 MHz Arria V 848 ALMs 8192 227 MHz Stratix V 857 ALMs 8192 420 MHz MAX 10 2063 LEs 8192 168 MHz Read Write performance as shown in the following table will largely depend on the type of SD card used Table 5 Performance Avalon System Low Level Low Level Platform NIOS CPU ba Red Write FAT 32 Read FAT 32 Write BeMicro CV Cyclone V FPGA Development Kit fast 100 MHz 21 98 MB s 11 22 MB s 17 72 MB s 9 33 MB s Pretec 1GB industrial SD card Timing Requirements In order to support high speed mode up to 50 MHz SD clock rate the following I O timing requirements have to be met on SD interface sig nals 1 tco of SD_ CMD SD_DATY 3 0 has to be at least 2 ns greater than tco of SD_CLK 2 tco of SD_CLK board delay of SD_CLK maximum board delay of either SD_CMD or SD_DATT 3 0 maximum tsu of either SD_ CMD or SD_DATT 3 0 has to be smaller than 6 ns It is up to the user to either turn of High Speed support or implement the necessary timing constraints and ensure they are met El Camino GmbH 11 SD BUS Core with Avalon Interface
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