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EXC-3000VME-VXI MAGICard: User`s Manual, Rev C

1. sequence to a device whose SAL is 63 H A5 H C3 H 19 H 68 H 0000 0110 1000 0001 NIBl is the high nibble of the PARTIAL Hm HJ next byte DATA NIB3 NIB2 NIBI NIB3 NIB2 68 H WORD m 0110 0011 0001 1010 L SAL PART DATA CODE 3 NIBBLES 1100 0011 1010 0101 NIB2 NIBl A5 H FuLL 73 14 NIB4 NIB3 C3 H DATA NIB4 NIB3 NIB2 NIB1 NIB 5 is the low nibble of the WORD TTT next byte 0110 0011 0000 1001 L SAL NIB5 0000 0001 0000 0010 File Sequence no 1 AAA LDU Sequence no 2 i FILE NO LDU NO 0110 0011 0110 0011 GFI 3 general purpose L SAL SOT GFI 1 DT Destination Code 50 H printer 0101 0000 0000 0100 Word Count 4 SOT 2 data words EOT a DEST CODE WORD COUNT 0110 0011 0100 0001 Ist word of block L SAL RTS CODE bit 15 bit 0 The word count in the block s instruction block must be 4 and the LDU bit in the control word must be set to 1 The Channel Tx SAL Register in the Channel Control Register Block for the Williamsburg channel must match the SAL field 63 H in this example After this sequence an EOT would be automatically generated and sent For these particular bytes the CRC field in the EOT would be 788D H ARINC Channels 78 If the Buckhorn Window bit
2. Int od GEL OT cit A AS AA a ee page General senile ea ES len ekme O e RR RN e page Data Storage Area and Control Register Access page ARINC 429 561 568 575 582 amp Williamsburg Channels Operation page General Memory MID ee le en ee page Global Control Register na reed page channel Control Register BLOCKS ne giye an ae east page Recerver Monttor Operation in A eee eS page General Information ais rauchen page Seguential Mode Operation including Merge mode page Look Up Table Mode Operation una ee ea page Transmitter Operation Non Williamsburg Channels page Transmitter Operation Williamsburg Buckhorn Channels page Duty Cycle ner un tare iper E page MAGICard Implementation of the Williamsburg Protocol page Pull half Duplex Operation iui Lella A een page TEEnsmite rieti am an ee ee aaa ee ee RR a ll ie EES page RECE Lyen op E ana dille SI eater le page RS 232 422 485 423 Channel OpsFrat ion iui sa a e ks page General Memory Map sure A ae li page Global Control Registers a adin a rn aaa a a Be A page Channel Control Register Blocks ur ara A Ekel page Reeeiver Monitor Operation siri dabbe dl Deal page Transmitter Operation urn LIS A nein ana page Baud Rate himitations A er aed ma kei page 1 VME VXT Interface zu ee ed page
3. INSTRUCTI CHANNI ER CONDI EL 3 STATUS REGI reserved reserved CHANNI CHANNI EL 3 START TRANSMI EL 3 STA RS Channels 100 DCE DCC DCA DC8 DC6 DC4 DC2 DCO DATA CURRI reserved reserved DATA INSTRUCTI STA TUS RE reserved reserved CHANNI STAI RT TRANSMI 101 DFC DFA DF8 DF6 DF4 DF2 RS Channels DATA CURRI reserved reserved DATA
4. unless the specific each of them is unconnected see JUMPERS above signals Jumper is shorted Notes 149 POWER SUPPLY REQUIREMENTS The board s power supply requirements are defined below MAGICard with no communication channels installed 5 volt 1 5 Amps 12 volt 50 mA EACH CHANNEL REQUIRES CHANNEL TYPE 12v 12v RANSM RINC 582 2wire RINC 582 2wire INC 582 6wire INC 582 6wire 150 ORDERING INFORMATION EXC 3000VME VXI option code s B size EXC 3000VME VXI C option code s C size card card complete with shield Option Definition No of Notes Code Channels Used Ax RS 232 TX RCV 8 0000 MHz 1 channel AAx RS 232 TX RCV 7 3728 MHz 1 channel Bx RS 422 TX RCV 8 0000 MHz 1 channel BBx RS 422 TX RCV 7 3728 MHz 1 channel Cx RS 485 TX RCV 8 0000 MHz 1 c
5. 7F74 TET2 7F70 TE6E TE 6C 7F6A 7F68 7F66 7F64 7F62 7F60 TESE TESC TESA ARINC Channels 10 NS BAL CONTROL R EGISTERS cont ER DATA STORAGE MODE ST 7F58 TE56 7F54 TE52 7F50 7F4E ER COND i STATUS REGI UPT STATUS BUSY REGISTER reserved 11 700 ARINC Channels SOFTWARE RESET REGISTER 1F84 H WRITE ONLY Writing a 0 to this register resets the board Following a reset the board will xecute a self test both memory and channels clear all the on board memory and then update the Board Status Register The board indicates that it is ready by writing a value of 3000 H to the Board Ready Register TEC H Writing any non zero value to thi
6. RCV DATA START POINTER DATA CURRI LOOK UP TABLE START ADI E START ADD DATA WORD COUNT RAPAROUNI WORD COUNT ER START ARINC Channels TX SAL REGI RCV SAL 26 DTE D6E D5E DIC DIA D78 D76 D74 D72 D70 DEC D6A D68 D66 D64 D62 D60 DSC D5A D58 D56 D54 D52 D50 7DAC CHANNEL 2 RCV DATA START POINTER 7DAA 7DA8 DATA CURRI INTE 7DA6 LOOK UP TABLE START ADDRI 7DA4 E START ADDRI 7DA2 DATA WORD COUNT RE sl 7DAO RAPAROUND REGI 7D9E WORD COUNT H 7D9C 7D9A 7D98 7D96 7D94 7D92 7D90 7D8C
7. RS Channels 96 CHANNEL CONTROL REGISTER BLOCKS BAUD RATE DATA START POI DATA CURRI reserved 7 reserved 7 CHANNI CHANNI EL 0 RCV CHANNI EL 0 RCV EL 0 RCV DATA BYTE CHANNI EL 0 STA TUS REGI ER CONDI iG 7 reserved 7 reserved 7 CHANNI CHANNI EL 0 STAI RT TRANSMI EL 0 STAI 97 DARE D3E D2E D4C D4A D48 D46 D44 D42 D40 D3C D3A D38 D36 D34 D32 D30 D2C D2A D28 D26 D24 D22 D20 RS Channels DATA CURRI reserved reserved DATA NSTRUCTI CHANNEL 1 INT
8. STATUS REGI ER CONDITION REG reserved reserved CHANNEL 1 STA RT T RANSMI RS Channels 98 DTE D6E D5E DIC DIA D78 D76 D74 D72 D70 DEC D6A D68 D66 D64 D62 D60 DSC D5A D58 D56 D54 D52 D50 DATA CURRI reserved reserved DATA INSTRUCTI CHANNEL 2 INTERRUPT TRIGGER CONDITION REG CHANNEL 2 STATUS REGI reserved reserved CHANNEL 2 START TRANSMIT REGISTER CHANNEL 2 STAI 99 DAE D E D8E DAC DAA DA8 DA6 DA4 DA2 DAO DIC DIA D98 D96 D94 D92 D90 D8C D8A D88 D86 D84 D82 D80 RS Channels DATA CURRI reserved reserved DATA
9. INSTRUCTI CHANNI ER CONDI EL 5 STATUS REGI reserved reserved CHANNI CHANNI EL 5 START TRANSMI EL 5 STA RS Channels 102 E DATA CURRI reserved reserved DATA INSTRUCTI ER CONDI CHANNI EL 6 STATUS REGI reserved reserved CHANNI EL 6 START TRANSMI CHANNI EL 6 STA 103 RS Channels DATA CURRI reserved reserved DATA INSTRUCTI ER CONDI CHANNEL STA TUS REGI
10. The 62 pin connector is defined below Each channel is allocated 6 pins refered to as A to E The function of each pin depends upon the protocol implemented by the channel A table follows the connector pinout which defines the function per protocol PIN SIGNAL NAME PIN SIGNAL NAME PIN SIGNAL NAME ict cH 0 B 22 CASE GROUND 43 DIGITAL GROUND 2 cH 0 D 23 CH 0 A 44 CH 0 F 3 cH 1 B 24 CH 0 C 45 cH 0 E 4 CH 1 D 25 CH 1 A 46 CH 1 F 5 cH 2 B 26 CH 1 C 47 cH 1 E 6 Gk 2 D ill 27 CH 2 A 48 cH 2 F 7 CH 3 B 28 CH 2 C 49 cH 2 E 8 CH 3 D 29 CH 3 A 50 cH 3 F 9 cH 4 B 30 CH 3 C 51 CH 3 E 10 cH 4 D 31 CH 4 A 52 CHH 4 F 11 CH 5 B 32 CH 4 C 53 cH 4 E 12 CH 5 D 33 cHH5 A 54 CH 5 F 13 CH 6 B 34 CH 5 C 55 CHH 5 E 14 cH 6 D 35 CH 6 A 56 CH 6 F 15 cH 7 B 36 CH 6 C li 57 CH 6 E 16 cH 7 D 37 CH 7 A 58 cH 7 EF 17 CH 8 B 38 CH 7 C 59 cH 7 E 18 CH 8 D 39 CH 8 A 60 cH 8 F 19 CH 9 B 40 CH 8 C 61 CH 8 E 142 20 21 CH 9 D CH 9 E 143 CH 9 E In this table the 62 pin connector is sorted by signal name B DG Z H e Z H SI
11. a 1 undefined Lo L PARITY ON OFF L PARITY EVEN ODD E O IVER STORAGE MODE E a lt ER WRAP AROUND E a lt ER LABEL TRIGGER lu 1x MODE SELECT _ AAA lt AKA lt K lt K lt A lt A N gt ENABLE RCV FILTER TABLE Notes 1 This register can only be written to when ALL channels are turned OFF via the Start Register 2 The board should be started via the Start Register only after a minimum of 1 msec from the time that the contents of this register have been modified 3 It is recommended that ALL active channel Configuration Registers be set up immediately following the Board Ready before programming any other parameters 4 ARINC 561 568 575 582 specifications specify Lo Speed Bit Rate operation only ARINC Channels CHANNEL x CONFIGURATION REGISTER BIT DEFINITIONS Rate is selected then the bit rate is defined by the Global Programmable Bit Rate Register Tx Rise Fall 0 Hi Speed 1 Lo Speed Time 1 5 0 5usec 10 5 usec Bit Rate Select Bit Rate of channel If the Programmable Bit Parity On Off Even Odd 1 Odd standard ARI Rev Storage Model 1 Sequential Storage M
12. reserved reserved CHANNEL STAI RT TRANSMI CHANNEL STAI RS Channels 104 DATA CURRI reserved 7EC4 reserved JEC2 DATA E RE i TECO INSTRUCTI 7EBO EL 8 STATUS REGI TEA8 reserved 7EA6 reserved 7EA4 CHANNEL 8 START TRANSMIT REGISTER TEA2 EL 8 STAI CEIVE GI i 7EAO RS Channels 105 DATA CURRI reserved reserved DATA INSTRUCTI reserved reserved CHANNEL 9 START TRANSMIT REGISTER GI
13. 2000 2400 3600 4800 7200 9600 19200 38400 56000 128000 256000 oscillator B C Z Modules depending on the configuration of the MAGI 10000 6667 4545 3717 3333 1667 833 500 417 277 250 208 139 104 69 52 26 13 9 4 2 Card BR p sd ae gt OTO R UO oO DD Krol Oro DOD N o for very high baud rates there may be lost bytes on receive if DTR and CTS are not used and an inter byte 109 RS Channels gap on transmit See the section Baud Rate Limitations 110 CHANNEL x RECEIVE DATA START POINTER WR This register is used to set the start address of the receive data buffer The address must be even Sets the end address of the receiver data buffer The data will wrap around or stop depending upon the Receiver Wrap Around control bit within the Configuration Register CHANNEL x RECEIVE DATA CURRENT POINTER RD Indicates the address where the next byte is to be placed within the buffer This pointer value is incremented after th ntire receiver block data byte time tag and status is written into memory EL x RCV DATA Indicates the number of bytes received 0 64k This register wraps around It may be reset to zero by the user only when
14. BASE 06 Write Read This 16 bit read write register defines the base address of the card s A24 and A32 memory and registers The mtl most significant bits of the Offset register are the values of the mtl most significant bits of the card s A24 and A32 memory and register addresses where m is the Required Memory field of the card s Device Type register The 15 m least significant bits of the Offset register have no meaning Thus the Offset register bits 15 through 15 m map to the address lines A23 through A23 m for the A24 Address Space and to lines A3l through A3l m for the A32 Address Space FF Given A24 ADDRESSING EXAMPLE required base address 1E 0000 H LL Then write 1E H to Offset register OFFSET A X don t care TT Given A32 ADDRESSING EXAMPLE required base address FF37 0000 H Ld Then write FF37 H to Offset register OFFSET Note Once this register is set up and the Control Register s A24 A32 ENABLE bit is set the card s A24 or A32 memory and registers can be accessed 133 BASE 20 H Write Read In the case of an interrupt generated by the board the 8 least significant bits of this 16 bit register known as the STATUS ID are used as the interrupt vector during the ensuing interrupt acknowledge cycle The card is a D08 0
15. DFC DFA DF8 DF6 DF4 DF2 ER START TX SAL RE 29 ARINC Channels DATA START POI DATA CURRI LOOK UP TABLE START ADI E START ADD DATA WORD COUNT RAPAROUNI WORD COUNT ER START ARINC Channels TX SAL REGI RCV SAL 30 Ed DATA START POINTE TEGA DATA CURRI NTE 7666 LOOK UP TABLE START ADDRI 71664 E START ADDRI 71662 DATA WORD COUNT RE sl 7660 RAPAROUND REGI i TESE WORD COUNT H TESC
16. RS Channels 92 0 0 0 I BYTE LO BYTE 93 BOARD STATUS REGISTER 174 H Indicates the result of the Power on self test of the board 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OT ee al A TIT e e i Pata 1 self Test ok RESERVED Re 1 1 o Self Test Fail 9 8 7 65432 1 0 L Channel Status Bits I MEMORY OK Notes 1 The Self Test Fail is set when the channel self test fails or when the channel is not present on the board 2 The board will continue to operate on condition of Channel Self Test Failures BUT will not continue to operate on condition of a Memory failure 1872 H Indicates the revision level of the firmware ie 0114 H Rev 1 14 INTERRUPT STATUS REGISTER F70 H Indicates which channel issued the interrupt 1 Active The status bits are only reset by the user 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 rz CHANNEL BITS RS Channels 94 CHANNI EL x CONFIGURATION STATUS This register indicates to the host the type of channel channel socket on the board 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 opp Notes 1 2 SERVED
17. RS Channels 126 res RSA VME VX NTERFACE The MAGICard board interfaces to the computer via a 16 bit data bus which can be accessed in bytes or words The board may be accessed by using addresses in the form For accessing VME VXI Configuration Registers XXXX H A16 mode with ADDRESS MODIFIER CODES 29 2D For accessing Data Storage Area and Control Registers XX XXXX H A24 mode with ADDRESS MODIFIER CODES 39 3A 3D 3 XXXX XXXX H A32 mode with ADDRESS MODIFIER CODES 09 0A OD OE GI selectable via jumper JPl The MAGICard memory map is divided into two distinct blocks 1 VXI VME Configuration Registers 2 Data Storage Area and Control Registers The VXI VME Configuration Registers are used for mapping and setting parameters of the MAGICard within the user s VME or VXI system The Data Storage Area and Control Registers are used to control the operation of the MAGICard me VXI VME Configuration Registers The VXI VME Configuration registers are located within a 64 byte block in the Al6 address space between the addresses 49152 dec and 65472 dec The base address of the Configuration registers is determined by the following equation Base Address dec V 64 49152 dec V the Logical Address of th
18. This register is used to set the start address of the receive data buffer The address must be even This register is used in the Sequential Mode of operation Sets the end address of the receiver data buffer This is used in the Sequential Mode of operation The data will wrap around or stop depending upon the Receiver Wrap Around control bit within the Configuration Register CHANNEL x RECEIVE DATA CURRENT POINTER RD In Sequential Mode this register indicates the address where the next ARINC receive word is to be placed within the buffer This pointer value is incremented after th ntire receiver block is written into memory In Lookup Table Mode this register contains the address of the last ARINC receive word written to the receive data area CHANNEL x RECEIVE LOOK UP TABLE START ADDRESS WR LOOK UP TABLE MODE Sets the Start address must be even of the 256x16 byte Receiver Look Up Table This address points to the FIRST location of the look up table The board will store ONE ARINC data block for each Label received The data block contains 32 bit ARINC word 32 bit Time Tag Error Count Word and the Receive Status Word The data block will be overwritten by the subsequent reception and storage of the same ARINC Label
19. Coding Err 05 Gap sync Time Error reserved A logic it Indicates tha ARINC word Indicates tha detected in t Indicates tha between words hannels o SET TO 0 This bit is set when the status word is he ARI t a Gap less than 4 bit times between words Sync bit time between words for ARI INC word Indicates that a Hi bit count error was detected in the ARINC word Indicates that a Lo bit count error or a Null bit error was detected in the AR t a parity error was detected in the t a bit level decoding error was NC word Time error occurred for ARINC 429 575 582 2wire channels and less than INC 561 568 582 6wire 07 valia Word Global Bit 08 Merge CH ID Code 0 09 Merge CH ID Code 1 ae EI 10 Merge CH ID Code 2 ll Merge CH 15 reserved ARINC Channels word was valid in all 0000 0001 QO 40 11 00 1000 ET TO 07 ET TO 0 ET TO TO SET TO 0 nan nan nan nan nan nan hann hann o JU WEN re Oo 58 Note CH ID Code O LSI Indicates that the received ARINC respects 3 MS LOOK UP TA LOOK UP TABLE MODE In the Look
20. ER START 7E46 TX SAL REGI i 7E42 RCV SAL RE i 7E40 ARINC Channels 31 CHANNI EL 7 CONTROL REGISTER BLOCK CHANNEL 7 CONFIGURATION REGISTER CHANNEL 7 RCV DATA START POINTER ARINC DATA CURRI LOOK UP TABLE START ADI E START ADD DATA WORD COUNT RAPAROUNI WORD COUNT ER START TX SAL REGI RCV SAL Channels 32 INSTRUCTI 7EBO TX LOOP COUNTE EAE IX AMPLI REGI i TEAC ERRUPT TRI TI EG TEAA
21. read the Receiver status registers to know how many words have been received and how many invalid words if any were detected 9 READ THE RCV DATA BLOCK read the ARINC words or RS bytes and RCV Status and Time Tag Words from the on board memory Note for Williamsburg channels the Channel Control Register Block associated with the receive module is used for both receive and transmit control see the section on Channel Control Register Blocks Thus for a Williamsburg channel whose receive module is located in channel socket 4 transmit module is in channel socket 5 and CRC module is in channel socket 6 only the channel 4 Control Register Block is used The Control Register Blocks for channels 5 and 6 are not used Tr TTT lt P P_L___ Data Storage Area and Control Register Access The Data Storage Area and Control Registers reside in 16Kx16 of true dual port RAM It is within this on board dual port RAM that the user controls the operation of the board The user is advised to use 16 bit addressing when operating with 16 bit control registers or data words When accessing 8 bit control registers or data bytes it is recommended that th user us byt addressing since there is a possibility of inadvertantly overwriting a byte wide location which resides next to the desired location when using 16 bit word addressing All 16 bit
22. CHANNEL x RECEIVE FILTER TABLE START ADDRESS WR SEQUENTIAL MODE Sets the start address of the 256x8 Label Filter Table as described in the Sequential storage mode Th address must be even It is valid for several channels to use the same filter table CHANNEL x RCV DATA WORD COUNT REGISTER RD SEQUENTIAL MODE ARINC Channels 37 Indicates the number of words received 0 64k This register wraps around n nay be reset to zero by the user only when the channel is stopped ARINC Channels 38 and CHANNEL x RCV BUFFER WRAPAROUND REGISTER WR This register contains 2 bits for synchronization with the C drivers If bit 14 is set to 1 the receive buffer has wrapped around once since the last data read If bit 15 is set to 1 there have been multiple wraparounds CHANNEL x RCV DATA WORD COUNTER TRIGGER REGISTER WR SEQUENTIAL MODE This register allows the user to generate an interrupt and set a flag when a certain number of words have been received 1 64k The appropriate bit must also be set in the Channel x Interrupt Trigger Condition Register CHANNEL x RESTART WILLIAMSBURG TRANSMISSION WR Writing any non zero value to this register will reinitiate transmission in a Williams
23. FACTORY DEFAULT DIP SWITCH SETTINGS SWI is set to Logical Address 80H 1 OFF 2 to 8 ON III JUMPERS Unless otherwise specified all jumpers should be normally out Because the placement of jumpers is user specific care should be taken that signals which the user chooses to jumper are not already in use on the VME bus ED JUMP JP5 SYSFAIL P1 C10 Connects card SYSFAIL to backplane JE 4 see Factory set JPl A32SEL O Jumper in A24 address space Jumper out A32 address space JP30 EXT TRIG Pins 1 and 2 shorted positive pulses POLARITY J1 Pins 2 and 3 shorted negative pulses 1 34 VXI RELATED JUMPERS To continue the VXI Local Bus JP15 LBUS00 P2 A05 Connects LBUSA00 to LBUSCOO P2 C05 JP16 LBUSOI P2 A06 Connects LBUSA01 to LBUSCOl P2 C06 JP17 LBUSO2 P2 A08 Connects LBUSA02 to LBUSC02 P2 C08 JP6 LBUS03 P2 A09 Connects LBUSA03 to LBUSC03 P2 C09 JP7 LBUSO4 P2 All Connects LBUSA04 to LBUSC04 P2 C11 JP8 LBUSO5 P2 A12 Connects LBUSA05 to LBUSCO5 P2 C12 JP9 LBUS06 P2 Al4 Connects LBUSA06 to LBUSCO6 P2 C14 JP10 LBUSO7 P2 A15 Connects LBUSA07 to LBUSC07 P2 C15 JP11 LBUS08 P2 A17 Connects LBUSA08 to LBUSC08 P2 C17 JP12 LBUS09 P
24. lt lt _ Configuration Status Code iamsburg Rx Channel iamsburg Tx Channel 43210 Configuration Status Code looooo Undefined Channel 0 0001 ARINC 429 Receive Chan 00010 ARINC 429 Transmit Chan 0 0011 ARINC 561 Receive Chan 00100 ARINC 561 Transmit Chan 00 0 1 ARINC 568 Receive Chan 00 0 ARINC 568 Transmit Chan 00 1 ARINC 575 Receive Chan 01000 ARINC 575 Transmit Chan 0 1001 ARINC 582 2 Wire Receiv 0 010 ARINC 582 2 Wire Transmit Channel 01011 ARINC 582 6 Wire Receiv 0 1100 ARINC 582 6 Wire Transmit Channel 01 Dal reserved 0 0 reserved o 1 10000 Rs 232 Channel 10001 Rs 422 Channel 100210 Rs 485 Channel 10011 Rs 423 Channel Note 2 10100 gt J 10101 i 10 o i 1 0 T i 11000 gt AR i 11010 gt AASE x 11100 i 1 0 1 ARINC 429 Will 1 1 0 ARINC 429 Will 1 1 ARINC 429 Wil REGISTER see Global Memory Map configured in each lo rr e te 00000000 Channel Channel iamsburg CRC Channel Free Codes The RS 423 channel for future channels requires firmware 95 Revision 1 31 and up RS Channels RECEIVER DATA STORAGE MODE REGIST
25. x ERATOR RE STE This is a 16 bit register that m The value in this register should be chosen as fol For a module with a 8 0000 MHz oscillator the val value 8000000 16 x baud For a module with a 7 3728 MHz oscillator the val value 7372800 16 x baud Example 8000000 The 130208333 Minimum allowed baud rate is 50 baud The following tables available oscillators show representative 7 37280 Mhz oscillator AA BB CC ZZ Modules BR Desired Contents o 5 Desired baud rate is 38 400 from a modul 16 x 38400 Baud Rate Register should be set to baud ust be filled in prior to starting the channel lows ue is ue is e with a 8 MHz oscillator 13 decimal rates available for the two 8 00000 Mh A 1 Desired contents of as a 50 9216 75 6144 134 5 3426 10 001 150 3072 300 1536 600 768 1000 461 0 043 1200 384 1800 256 2000 230 0 043 2400 192 3600 128 4800 96 7200 64 9600 48 10000 46 0 174 19200 24 38400 12 76800 6 153600 3 230000 2 0 174 Note 50 75 110 134 5 150 300 600 1000 1200 1800
26. 7D8A 7D88 ER START 7D86 7D84 TX SAL REGI i 7D82 RCV SAL RE 7D80 ARINC Channels 27 DATA START POI DATA CURRI LOOK UP TABLE START ADI E START ADD DATA WORD COUNT RAPAROUNI DCE WORD COUNT ARINC Channels TX SAL REGI RCV SAL 28 ER START DCC DCA DC8 DC6 DC4 DC2 DCO INSTRUCTI TX LOOP COUNTE TX AMPLI ERRUPT TRI STATUS i RCV SAL I
27. MAGICard MULTI PROTOCOL ADVANCED GATEWAY INTERFACE CARD 7 FEATURES UP TO 10 COMMUNICATION CHANNELS TWO RECEIVE MONITOR MODES SEQUENTIAL PROGRAMMABLE TRANSMISSION FEATURES LOOK UP TABLE SYNC TIME BETWEEN WORDS INTER BLOCK TIME PER BLOCK 32 BIT TIME TAGGING PER WORD TX DATA BLOCK SIZE PER CHANNEL VARIABLE TX AMPLITUDE PER CHANNEL WORD STATUS TAGGING BIT RATES HI LO SPEED VARIABLE LABEL FILTERING TRANSMISSION MODES ONE SHOT START TRIGGERS LOOP N TIMES RCV ERROR COUNTER PER CHANNEL PARITY OPTIONS ERROR DETECTION PER WORD ON OFF BIT COUNT ODD EVEN SYNC TIME PARITY BIT CODING ERROR ERROR INJECTION PER BLOCK T BIT COUNT HI LO SYNC TIME MERGE MODE STORES ALL DATA STRETCH BIT FROM ALL RECEIVE CHANNELS BIT RATE FREQUENCY N ONE BUFFER AREA PARITY RCV COUNT INTE
28. SAL which d type of block requires a response instruction block s control word to be set to 1 It can be a single They consist of any combination of ARINC 429 data SOLO data words This type of block requires the LDU bit of the instruction block s control word to be set to This type of block reguires the LDU k containing an ALO word a single word block containing a TEST word or all words must contain in th label field the destination is found in the Channel Transmit SAL Register An LDU block must start with an RTS word whose word count field matches the word count in the block s instructi of Williamsburg full data words partial the case set to 1 the LCW is not included in the block ally before the SOT An EOT word is also not included in the block It automatic on block This must be followed by an SOT word and then any combination data words and character data words In of a Buckhorn window Buckhorn Window bit of the message Control Word It is generated and sent is generated and sent automatically after the last data word LAST DATA WORD E DATA WORD DATA WORD 2 1 SOT WORD RTS WORI D I LDU block 77 Ath 3rd 2nd lst location in TX data area ARINC Channels LDU EXAMPLE This is an example of how to build an LDU block to send the following 4 byte
29. Status Word are described within this section RCV DATA END PO NT ER written by user RCV DATA START PO NTE written by user ARINC Channels RECEIVE STATUS WORD n block TIME TAG WORD LO TIME TAG WORD HI DATA WORD LO DATA WORD HI RECEIVE STATUS WORD TIME TAG WORD LO TIME TAG WORD HI DATA WORD DATA WORD A 2nd block RECEIVE STATUS WORD TIME TAG WORD LO TIME TAG WORD HI DATA WORD LO DATA WORD HI 50 i et lst block RCV DATA WORD FORMAT The received Hi Word followed by Lo Word 32 bit ARINC word is stored as two 16 bit words within the memory The data bytes are shown below The numbers shown within the four bytes represent the ARINC bit locations within the 32 bit word r gt 24 23 22 21 20 19 18 17 Hi Byte i 16 15 14 13 12 11 10 09 Lo Byte DATA WORD LO 11 DATA WORD HI qe yea lt E Ka Hi Byte gt 32 31 30 29 28 27 26 25 Lo Byte ARINC WORD Note that bits 09 throug field which is organized is built the way it is Hi Word followed by Lo Word field 32 through 25 in the H Label or SAL 0 MSB h 32 are ordered from LS MSB to LSB It is
30. RS Channels 106 ti ti ti ti ti ti ti DC DA D8 D6 D4 D2 DO CHANNEL x CONFIGURATION REGISTER This register sets up various run parameters for both the receive and transmit channels Character Length Es l WS Stop Bits L i TZ Parity Enable Even Odd Parity Stick Parity A H W Handshake RS 232 um Loopback RS 485 only r z I SLED Receiver Wraparound I Receive Byte Trigger Notes 1 This register can only be written to when the respective channel is turned OFF via the Start Register For ARINC channels it is only possible to change this register if ALL channels are turned off That is not the case for RS channels 2 It is recommended that ALL active channel Configuration Registers be set up immediately following the Board Handshake procedure before programming any other parameters RS Channels 107 CHANNEL x CONFIGURATION REGISTER BIT DEFINITIONS This field determines th Bit o Length 0 1 Char number of bits in each 0 0 5 bits Length character sent 0 1 6 bits 1 rbits 1 1 8 bits This bit specifies the number of Stop bi
31. Pin Signal Name Bl B2 B3 B4 B5 B6 B7 B8 B9 0 a MW CI PwWN Ho BGOIN BGOOU BGLIN BG10U BG2IN BG20U BG3IN BG30U AMO AMI AM2 AM3 GND GND IRQ7 IRO6 IRO5 IRQ4 IRO3 IRO2 IRQ1 5V T Tx T T 148 PES ileal Ee Pin Signal Name CT C2 C3 C4 CS C6 Gi C8 C9 O E 000000000 RR RP PRP EPP 0 JU DSWNEO ini i NINE R O C22 C23 C24 C25 C26 C27 C28 C29 C30 G31 C32 D D D UUUUU Dopo po ao ii 08 09 10 OP WN RR GND SYSFAI SYSRE LWOR AMS A A pp NN op D D SRL Oot 00 LO 23 22 Ne EW WB gG I oO 12V ol lt Tx ET CTOR P2 PINOUT Du CONNE Sig Name Pin Sig Name Pin Sig Name Pin k x x x O ri NM vu o co O dmn Lo oo O oo oo oo r DD VO LL LL LL LL LOL LL pi Mm pi Mm U uy nn nn nn nn nn HH HH SENE De y D E A Die 5D HH HH m m m m mm m m m m mm HH HH HH HH HH HH HH HH RE RE OANNMTIN OR O NO ANMA OR O0 NON ANO Ion o NNN NN NNN NN MMM O L O O UL UO A O UO UL O GEO UL O O UL O UL UO O UL O UL O O UO O 0 O OL gt Q TD EORO NO HAD a a gt O Z NNNNNINMMZIO Z ZN 0 AGA LAL ALU oO VO CANMNANORAHDOANMNANUORADHDOXAN ANMA WOR OD NNN NN NNN NN MMM MAMAMAMAMAMAMAMAMAMAMAMAMAMAMAM m
32. 1 VME VXI Configuration Register un siede al a page 1 USing INESFFUBES Bi e A De ERE Re De ER i page 1 Dual Port RAM Address Mapping Diagram ooooooooooooooo ooo page Board DANIEL Bid as page LEDS ti u A AS ee ee ae a page Dip SWEECH Settings AAA ke al page Factory Default Dip Switch Settings ee ee ee ee ee ee ees page MIT SS ri tact tan te Sarda oe a Sag e O RATE REI ie Jas e to page Factory Default dumper SsetLings nenn ae tls ita page External a o EY nr Re a RE na ae ed page Size C shield disassemble assemble instructions page TONNESCLOTS nn a en ee nude page Connector B LMES it A nen ee la Aa page RE a MD GIHN EF 55 64 65 66 67 69 70 71 72 77 94 N N N N N N N N x N N N x y N N 0 lt a a NOW EW DN DN Power Supply Requirements dei RR a Ordering Information li 124 125 INTRODUCTION This document refers to the memory mapped multi channel VME and VXI systems The populated with up to 10 ARINC in any combination of transmitters and receivers injection and error detection reporting capability in the ARINC modes on a channel by channel basis The user can select from three different ARINC bit rates Lo speed Hi speed and programmable and can select individual bit rates for each RS 232 422 485 423 channel test card comes in
33. OF EACH WORD WITHIN THE BLOCK ARINC BIT 02 THIS BIT IS VALID FOR ARINC 429 575 582 2wire ONLY 02 Stretch THE SECOND ARINC BIT WITHIN EACH WORD WITHIN THE Bit Error BLOCK IS STRETCHED CAUSING A MANCHESTER CODING ERROR THIS BIT IS VALID FOR ARINC 429 575 582 2wire ONLY 03 Bit Count THIRTY THREE ARINC BITS ARE TRANSMITTED WITHIN HI Error EACH WORD WITHIN THE BLOCK 04 Bit Count THIRTY ONE ARINC BITS ARE TRANSMITTED WITHIN LO Error EACH WORD WITHIN THE BLOCK 05 Suppress FORCES A NO PARITY CONDITION WITHIN THE WORD Parity EVEN THOUGH PARITY ON HAS BEEN SELECTED IN THE EL CONFIGUI i 06 reserved SET TO O 07 reserved SET TO 0 08 reserved SET TO O 09 reserved SET TO O 10 reserved SET TO 0 11 reserved SET TO TOT 12 reserved SET TO 0 13 reserved SET TO O 14 reserved SET TO O 15 reserved SET TO O Note The SUPPRESS PARITY bit can be useful in a situation where most of the data buffers contain standard type data without parity words within the Channel binary data with parity and a few buffers contain In such a situation ie data word buffer can be ARINC Channels Configuration Register while exceptional cases forced to NO PARITY using this bit 66 BC the parity can be set ON for all BC D D NTERWORD DLY WORD CNTR This word is divided into two bytes The Interword Delay and the Word Counter Th
34. PROTOCOL CONTINUED ln el RS 485 DATA HI DATA LO unused unused CASE GROUND DIGITAL GROUND 34000 PP RS 423 34000 PP DATA TRANSMIT Note 4 DATA TRANSMIT INVERTED OPTION Note 4 DATA RECEIVE H DATA RECEIVE LO CASE GROUND DIGITAL GROUND CAN BE PAIRED WITH DATA TRANSMI Note 4 The transmit Driver Rise Fall time is set to lusec approx This value can be changed by repl End Module listed in following located on top of different Rise Fall Rise Fal 5usec 10usec 50usec 100usec Front times ar R2 50Kohm 100Kohm 500Kohm 1Mohm resistor R2 lacing the Waveshap Selected valu 147 es of R2 for CONNI ECTOR Pl PI LNOUT Pin Signal Name Al D N DPPPPPPPPPPPPPPP P PRP PPP PPP EO OND OA WwW WA WU BP WM FO D D N NP Ro O A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 DOO D01 D02 D03 D04 DOS DO6 D07 GND GND DS1 DSO GND GND AS GND IACK AM4 A07 A06 A05 A04 A03 A02 A01 12V DTACK VRITE ACKIN IACKOUT A32 5V
35. STATUS REGI TEA8 ER START TEA6 TX SAL REGI i TEA2 RCV SAL RE TEAO ARINC Channels 33 INSTRUCTI TX LOOP COUNTE TX AMPLI ERRUPT TRI STATUS ARINC Channels ER START TX SAL RE RCV SAL 34 E E bi bi bi E bi DC DA D8 D6 D4 D2 DO CHANNEL x CONFIGURATION REGISTER This register sets up various run parameters for both the receive and transmit channels Bits which are unused i receiver related bits while operating as a transmitter are ignored by the board 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 O 0 12 5KHZ LO SPEED ngn 0 1 100KHZ HI SPEED Bit 1 O PROGRAMMABLE Rate 1 TX RISE FALL TIME
36. The SOT the second word in the transmit block is then transmitted followed by the data words with the specified interword delay between consecutive words After the last data word is transmitted the EOT is constructed and transmitted It contains the calculated CRC and the last LDU bit as read from the command word in the block s instruction block A response of ACK is expected within 220 ms If a timeout occurs the LDU is retransmitted starting with the RTS word a maximum of 4 more times The timing of the interblock delay begins immediately upon reception of a legal ACK word or after the fifth timeout If at any time during the transmission of an LDU between transmission of an RTS and reception of an ACK word a NAK word is received transmission of the LDU is repeated beginning with the RTS word If a NAK is received 3 times during the course of a single LDU transmission of the next block is initiated after the interblock delay has passed If at any time during the transmission of an LDU a SYN word is received transmission of the frame starting with the block pointed to by the first instruction block is immediately initiated the loop count is not altered If at any time during transmission of an LDU an ALO word is received the reguired response an ALR word is transmitted and transmission of the LDU is repeated beginning with the RTS word ARINC Chan
37. a 0 for at least 1 msec ARINC Channels 12 BOARD READY REGISTER 7F76 H This register indicates that the board has finished its Power on sequence and that the board is ready to be accessed by the Host The board will write the value 3000 H into this register when ready HI BYTE LO BYTE BOARD STATUS REGISTER 1F74 H Indicates the result of the Power on self test of the board Williamsburg receive transmit and CRC modules are treated independently ee ler ae 1 self Test OK RESERVED or oz self Test Fail 9 8765432 1 0 L Channel Status Bits gt MEMORY OK BAUD RATE GENERATOR OSCILLATOR FREQUENCY 1 40MHz Note 0 33MHz 1 The Self Test Fail is set when the channel self test fails or when the channel is not present on the board 2 The board will continue to operate on condition of Channel Self Test Failures BUT will not continue to operate on condition of a Memory failure 1872 H Indicates the revision level of the firmware ie 0114 H Rev 1 14 NTERRUPT STATUS REGISTER 770 H Indicates which channel issued the interrupt 1 Active The status bit s are only reset by the us
38. a Time Tag Lo The resolution of the time tag is 10 usec bit TIME TAG 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 WORD LO NM K IN L ER I OI AD ER DS ER SAZ ES A ea Y Ki Ti Tr TIME TAG 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WORD HI REE aa o A ES FE ES BERN BE EB BE i ke mi EL EEE 0 MSB LSB RS Channels 119 RECEIVER STATUS BYTE 0 L Data Ready Overrun Error _________ Parity Error Framing Error Break Reserved Status Byte Bit Definitions 0 Data Ready Indicates a byte has been received 1 Overrun Indicates a byte was lost This can occur at speeds greater than 19200 baud when many channels are working simultaneously 2 Parity Err ndicates received parity did not match parity chosen in Configuration Register 3 Frame Err Indicates received character did not have a valid stop bit dicates receipt of a Break character Sa Reserved Set to 0 RS Channels 120 Ibe eee SEGG TRANSMITTER OPERATION In order to initiate a transmission both the Global Start Register and the Channel Start Transmit Register must be written to The user must create an instruction stack for the transmitter channel and write the data into the Dual Port RAM before writing to the Start Transmit
39. a self test both memory and channels clear all the on board memory and then update the Board Status Register The board indicates that it is ready by writing a value of 3000 H to the Board Ready Register 7F7C H Writing any non zero value to this register will cause the time tag to be reset to 0 Upon completion of the Time Tag Reset operation this register will be cleared by the board START STOP REGISTER 7F7A H The user can start one or more channels at the same time Writing a 1 to bit 00 starts channel 0 operation writing a 1 to the next location starts channel 1 etc Writing a 0 to a bit location will stop that channel s operation The user should wait a minimum of 350 Usec between writes to the START STOP register The Enable External Start bit is used in conjunction with on board jumpers to start the board s operation from an external event see section on VME VXI Jumpers and External Triggers for details 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 CHANNEL BITS ENABLE EXTERNAL START 0 disables enables Re Il BOARD READY REGISTER 7E76 H This register indicates that the board has finished its Power on sequence and that the board is ready to be accessed by the Host The board will write the value 3000 H into this register when ready
40. board is either executing or hasl fail 1 indicates that the card is ready to accept commands 4 6 ROSEL ndicates the state of the IROSEL2 0 bits in the Control Register ndicates the state of the CONFIGO bit in the Control Reg Indicates the state of the CONFIGI bit in the Control Indicates t inverted value of the VXI 15 A24 A32 Indicates the state of the A24 A32 ENABLE bit in the ENABLE Control Register Note The R ES ET SYSFAIL INH PASSED READY and MODID bits are included to maintain compliance with the VXI specification 130 CONTROL REGISTER VXI and VME BASE 04 Write Writing to this 16 bit register causes the actions listed below to be executed by the card Note that all bits in this register are set to 0 after assertion of VME bus line SYSRESET A24 A32 ENABLE memory enable rn CONFIG1 AR CONF IGO ROSEL2 SPARI ROSEL GI IROSELO SYSFAIL INH RESET Writing a 1 to this bit forces the card into the RESET state The user must not write a 0 into this bit for at least 100 usec after writing a 1 into
41. both B EXC 3000VME VX simulation and monitor card that operates within C sizes The card can be card as the MAGICard The MAGICard is a 429 561 568 575 582 and and RS 232 422 485 423 channels The MAGICard is the perfect solution MIL STD 1553 IEEE 488 and SDLC vue ez 7 vxz 16Kx16 lt gt z DUAL In Hz IR RAM F gt j a e lt gt FIGURE 1 MAG In addition the card has error for developing monitoring avionics communication interfaces such as ARINC RS 232 422 485 423 simulating testing and e eo ER gt CH O lt gt cao lt Locrc mopure FRonT END a AE NI EA I e evi CH 1 lt gt cH 1 lt Locrc mopULE FRonT END Bere ve E 32 Pos I io e I b cao cas es LOGIC MODULE FRONT END ICard BLOCK DIAGRAM GENERAL The MAGICard operation makes extensive use of pointers for setting up the size and location of both receiver and transmitter data blocks transmitter instruction stacks and receiver look up tables Each channel has its own pointer registers so that unique memory areas may be allocated for
42. for this reason that the data block with the Label and the ARINC B to MSI LSB In Williamsburg words th SAL B Label SAL opposite from the Label i Word and bits 24 through 09 in the Lo Word label field is replaced by the system address label gl ARINC Channels TIME TAG WORD FORMAT As stated above the Time Tag is a 32 bit word made up of two 16 bit words Time Tag Hi followed by Time Tag Lo The resolution of the time tag is 10 usec bit free 3 r gt 15 14 13 12 11 10 09 08 Hi Byte l L gt 07 06 05 04 03 02 0o1 oo Lo Byte ER O ES UP O GM Dari TIME TAG WORD LO TIME TAG WORD HI yl a P Hi Byte gt 23 22 21 20 19 18 17 16 Lo Byte 7 0 MSB LSB Note Each bit in the receive time tag represents 10 microseconds There is a latency between the time a word is received on the bus and the time that word is recorded in dual port ram This latency is affected by the number of channels and data rate of these channels The time tag reflects the time the word is written to dual port ram rather than the time the word is received over the bus In no event shall this latency exceed a single hi speed word time e g 360 microseconds ARINC Channels 52 lai RCV SEQUEN
43. should be given a value of FFFF H all ones CHANNEL x TX INSTRUCTION COUNTER WR Sets the number of TX Instruction blocks to process CHANNEL x TX LOOP COUNTER WR Sets the number of times to execute the TX instruction blocks N Times or Continuous Loop If the continuous value is selected the channel s operation can be terminated by setting the related channel bit within the Global Start Register to a 0 Value 0000 CONTINUOUS 0001 One Time 0002 Two Times FFFF 65535 Times EL x TX AMPL Sets the TX amplitude level of the TX channel This register has a resolution of 39mv bit The maximum register value gives a voltage of 10V peak measured across the ARINC bus differentially At startup and after a software reset this register is initialized to FF H which is the maximum value 00 AMPLITUDE VALUE 15 ON al 0 ARINC Channels 40 Note This register is not applicable for ARINC 561 568 582 6wire channels ARINC Channels 41 CHANNEL NT ERRUPT TR GG ER COND ON RE STE Sets the Interrupt and Trigger condition s of the board Bits 00 07 are the interrupt condition bits while bits 08 15 relate to the hardware trigger bits The trigger conditions set a pulse on the trigger TRIGO TTL Trigger Output signa
44. the first Instruction Block relates to the first data block the second to the second data block etc As stated each Instruction Block contains 4 words The first word is the Control Word which contains error injection parameters The second word contains an 8 bit Word Count which instructs the board as to the number of ARINC words to transmit within a particular block and an 8 bit inter word delay value which programs the time between words within the same buffer The third word contains a 16 bit user supplied data pointer This is a 16 bit address must be even which points to the beginning of the data words within the memory The fourth word is the Interblock Time Data Rate value and is used to program the time between data block transfers or the transmission period for the specific data block see diagram for details ARINC Channels 63 I TTI TRANSMIT BLOCK DIAGRAM TX INSTRUCTION STACK rr eee i TX DATA BUFFERS DATA WORD LO ess asi DATA WORD HI v r INTERBLOCK TIME DATA RATE WD H TX DATA POINTER k Instruction DATA WORD LO Block 2 INTERWORD DELAY WORD CNTR kl HS DATA WORD HI
45. var speed EOT not received within 400 ms of having sent CTS high speed operation status code 86 H If an RTS is received during reception of an LDU the response is sent as described above and reception of the entire LDU from the beginning is expected However the data already stored in the receive data area is not overwritten by the repeated LDU The repeated LDU is recorded after the last word received Whenever an ALO word is received an ALR word is sent in response If it received during reception of an LDU the LDU is expected to be repeated beginning with the RTS If a TEST word is received during reception of an LDU it is stored and no further action is taken If reception of an LDU is not in progress when a TEST word is received a LOOP word is sent in response Notes 1 A received LDU whose RTS word contains a non zero destination code is not automatically transferred to the indicated final destination If it is desired to transfer the LDU the user must stop the channel by setting to zero the Global Start Bit associated with the Williamsburg receive module set up a transmission instruction block and restart the channel 2 The MAGICard does not check the sequence of file or LDU sequence numbers in a received SOT word ARINC Channels 87 RS Channels OPERAT ON MANUAL FOR TH G Di RS 232 422 485 42
46. words data and control registers contained within the board s dual port RAM are stored in the following manner The HI byte is accessed at EVEN addresses while the LO byte is accessed at ODD addresses Example The Stack Pointer is located at address xxxx H BYTE LO BYTE xxxx 0 XXXX 1 Note that all addresses listed in the remainder of this document are given relative to the Base Address written by the user into Offset Register as described in Configuration Registers TO O OT OPERATION MANUAL FOR THE ARINC 429 561 568 575 582 AND WILLIAMSBURG CHANNELS ARINC Channels MAGICard GENERAL MEMORY MAP ARINC Channels CHANNEL CONTROL REGISTER BLOCK 0 reserved AREA USED FOR TX INSTRUCTION STACKS TX DATA BLOCKS RCV DATA BLOCKS RCV LOOK UP TABLES N D20 DIF N 7A00 TOEF GLOBAL CONTROL REGISTERS oS i reserved 7F86 SOFTWARE RESET REGISTER 7F84 reserved 7F82 reserved 7F80 reserved TETE RESET TIME TAG REGISTER TETC START REGISTER TETA reserved 778 TEG
47. 1 LDu Bad CRC 12 LDU Bad Word Count Timeout 15 LDU No LCW Reception aborted due to arrival of a second RTS or an ALO A data word or EOT word was received when an SOT word was expected A bad CRC was received in the EOT word An EOT was received when a data word was expected or the received RTS contained an illegal word count An EOT word was not received before the timeout interval elapsed e received LDU is valid A data word or SOT or EOT was received when an LCW word was expected in a Buckhorn window ARINC Channels 56 E STATUS WORD DALE 57 WORD RECEIV ED HI w IT COUNT E RROR LO BIT CT INVLD WD ERROR PARITY ERROR INVALID COD GAP SYNC reserved VALID WORD ING ERROR TIM E ERROR MERGE CHANNEL CODE 0 MERGE CHANNEL CODE 1 MERGE CHANNEL CODE 2 ERGE CHANNE CODE w reserved reserved reserved reserved ARINC Channels m STATUS WORD 00 Received written into memory Word 01 Hi Bit ct Error 02 Lo Bit Ct Invalid Wd 03 Parity Error 04 Invalid
48. 2 A18 Connects LBUSA09 to LBUSC09 P2 C18 JP13 LBUS10 P2 A20 Connects LBUSA10 to LBUSC10 P2 C20 JP14 LBUS11 P2 A21 Connects LBUSA11 to LBUSC1 P2 C21 JP19 MODID P2 A30 Connects card MODID to backplane JP4 EXTRSTS External card reset JP3 EXTSTRTS External Start to card SIGNALS The jumper block JP18 is provided with wire wrap pins pins pins TTLTRGO TTLTRG2 TRIGOS TRIG1 TTLTRG4 TTLTRG6 JP18 TTLTRGO TTLTRG7 12 pin jumper block for TTL TRIGGER described below Each one of t ne 5 7 6 8 may be wired to any one of the TTL according to the needs of the user 8 3 JP18 fa 5 gt 9 H1 0 TTLTRG1 TTLTRG3 EXTRSTS EXTSTARTS TTLTRG5 TTLTRG7 138 IR GG ER ES 0 7 TIL TRIGGER OUTPUT SIGNALS TRIGO Low going pulse 500nsec set per condition s written to the Interrupt Trigger Condition Register same as found on the front panel s External Trigger connector TRIGI reserved ITL TRIGGER INPUT SIGNALS EXTSTRTS External Start The card may be started externally This achieves the sam ffect as writing a to bit 0 of the Start Register The card may be started asynchronously depending on the state of jumper JP3 To use the external Start option the External Start bit within the Start Sto
49. 3 CHANNELS 88 GENERAL MEMORY MAP GLOBAL CONTROL REGISTERS CHANNEL CONTROL REGISTER BLOCK 9 CHANNEL CONTROL REGISTER BLOCK 0 reserved 7D1F _ 7A00 ne AREA USED FOR TX INSTRUCTION STACKS TX DATA BLOCKS RCV DATA BLOCKS RCV LOOK UP TABLES A 0000 RS Channels 89 _ _ ____TSTToo_ I GLOBAL CONTROL R EGISTERS RS Channels reserved SOFTWARE RESET REGISTER reserved reserved reserved E TAG REGI START STOP REGISTER reserved EFF 7F86 7F84 TE82 780 TETE TETC TETA 778 776 774 172 770 F6E TE6C 7F6A 7F68 7F66 7F64 7F62 7F60 TESE TESC TESA ER DATA STO 90 RS 232 422 485 423 OPERATING MODE REG 7F3A RS Channels 91 SOFTWARE RESET REGISTER 7F84 H Writing a 0 to this register resets the board Following a reset the board will xecute
50. 30 pins 2 and 3 see JUMPERS SIZE C SHIELD DISASSEMBLE ASSEMBLE INSTRUCTIONS If the jumper settings need to be changed or additional channels need to be installed or new revision EPROMs need to be installed please disassemble the shield cover as follows 1 remove the 6 screws holding the upper and lower shield covers together 2 slide out the upper shield cover from under the front panel 3 carry out the modifications 4 reassemble the shield covers 141 1 CONNECTORS The EXC 3000VME VXI board contains six connectors a all communications I O signals on one female high density DB 62 connector J2 In addition a subminiature BNC connector Jl is located on the front panel Mating connectors are supplied for both b two DIN type 96 pin VME VXI connectors Pl and P2 c two 0 1 spacing socket headers P3 and P4 for optional installation of a plug in adapter board SUBMINIATURE BNC Jl External Trigger Connector This connector supplies an external trigger source This front panel connector is under software control and can be activated upon the same conditions as interrupts see Interrupt Trigger Condition Register The polarity of the pulses can be selected via JP30 see Jumpers DB 62 CONNECTOR PINOUT J2 Communications I O Connector
51. 82 2 Wire Transmit Channel 0 1011 ARINC 582 6 Wire Receive Channel 01100 ARINC 582 6 Wire Transmit Channel o 1 1 RESERVED 0 0 RESERVED o 1 i 10000 Rs 232 Channel 10001 RS 422 Channel 10010 Rs 485 Channel 10011 Rs 423 Channel Note 2 J 10100 i 10 1 i 1 0 o 1 0 1 i J 11000 i 11001 J 110210 i 11011 11100 i 1 01 ARINC 429 Williamsburg Rx Channel 1 10 ARINC 429 Williamsburg Tx Channel 1 1 liamsburg CRC Channel ARINC Channels 16 Notes 1 Free Codes for future channels 2 The RS 423 channel reguires firmware Revision 1 31 and up ARINC Channels 17 RECEIVER DATA STORAGE MODE REGISTER 7F58 H This register is used to select the Receiver Data Storage Mode and the Merge Mod option ARINC data words can be stored with Time Tag and Status words appended to the data block or without these additional words Set bit 00 to a logic 0 in order to select the standard mode which appends both Time Tag and Status Words to each ARINC word stored in memory Set register bit 00 to a logic 1 to select Data Only mode Bit 01 controls the Receiver Merge Mode selection A logic 0 selects the standard independent mode which utilizes different receive buffer areas for each receive channel A logic 1 selects the Merge Mode which utilizes a single re
52. BEEN SELECTED IN THE RATION RE 06 reserved SET TO 0 Bad CRC FORCES TRANSMISSION OF AN INCORRECT CRC IN EOT WORD os rpu INDICATES MESSAGE THAT REQUIRES RESPONSE LDU TEST WORD OR ALO WORD 09 Last LDU INDICATES LAST LDU IN FILE FOR INSERTION INTO EOT 10 LDU FORCES EOUT ERROR IN THE TRANSMITTED LDU BY 11 Buckhorn CAUSES AN LDU TO BE SENT AS A SINGLE LDU BUCKHORN window WINDOW BY ADDING A LCW WORD BEFORE THE SOT 12 reserved SET TO O 13 reserved SET TO O 14 reserved SET TO O 15 reserved SET TO 0 Note The SUPPRESS PARITY bit can be useful in a situation where most of the data buffers contain standard binary data with parity and a few buffers contain BCD type data without parity In such a situation the parity can be set ON for all words within the Channel Configuration Register while exceptional cases ie BCD data word buffer can be forced to NO PARITY using this bit ARINC Channels 73 NTERWORD DLY WORD CNTR This word is divided into two bytes the Interword Delay and the Word Counter The Interword delay byt specifies the time between blocks within this data block The resolution is in the form of bit times according to the transmission b E a it rate At the Lo Speed setting the resolution will be 80 usec bit while at he H
53. CONTROL WORD A NTERBLOCK TIME DATA RATE WD TX DATA POINTER k Instruction 7 Block 1 NTERWORD DELAY WORD CNTR gt CONTROL WORD 1st word within _ _ AAA Instruction Block LI TX INSTRUCTIONH STACK POINTER ARINC Channels 64 CONTROL WORD DE Instruction Bloc L STRETCH BIT L SUPPRESS PARI L PARITY ERROR L NULL BIT ERRO E k IT COUNT H IL reserved Lo reserved Lo reserved Lo reserved Lb reserved Db reserved bP reserved Preserved reserved __ _ _ ttr_a mutifl l l reserved IT COUNT LO RROR ROR ROR ARINC Channels CONTROL WORD 00 Parity A PARITY ERROR IS INSERTED WITHIN ALL ARINC 01 Null Bit A NULL BIT ERROR IS INSERTED WITHIN THE SECOND Error BIT
54. DIAGRAM BYTE COUNTER CONTROL WORD NTERBLOCK TIME TX DATA POINTER BYTE COUNT E po CONTROL WORD ON CONTROL WORD D EFINITI 1st word within ere A A DATA BYTI TX INSTRUCTION STACK TX DATA BLOCKS INTERBLOCK TIME 4 _O J TX DATA POINTER Pe el I DATA BYTE lst word wit Instruction hin Block Instruction Block This field is reserved for future use RS Channels 122 EH J BYTE COUNTI The Byte Counter is used to specify the number of data bytes within this data block 1 65535 TX DATA POINTER This register is used to set the start address of the transmit data block The size of the block is determined by the Byte Count value NTERBLOCK TIME Instruction Blocks are accessed sequentially and their associated data bytes transmitted according to this seguential order The Interblock Time allows the user to specify the time between data blocks The resolution of this 16 bit word is one bit time according to the transmission bit rate The minimum allowed value is 1 RS 485 OPERATION RS 485 transmitters go into tristate whenever they are not transmitting a block in order to provide other
55. DJ TIMEOUT I Du GOOD LL _ LL no Lew Note bits 08 15 are relevant to Williamsburg channels only They appear in the Status Word of RTS words only and are set when the reception of the associated LDU is completed ARINC Channels 55 00 Word Received written into memory 01 Hi Bit ct Error 02 Lo Bit Ct Invalid Wd 03 Parity Error 04 Invalid Coding Err 05 Gap Sync Time Error reserved A logic 1 This bit is set when the status word is Indicates that a Hi bit count error was detected in the ARINC word Indicates that a Lo bit count or a Null bit error was detected in the ARINC word Indicates that a parity error was detected in the ARINC word Indicates that a bit level decoding error was detected in the ARINC word Indicates that a Gap Sync Time error occurred between words less than 4 bit times between words for ARINC 429 575 582 2wire channels and less than 1 bit time between words for ARINC 561 568 582 6wire channels SET TO 0 07 valia Word Global Bit Indicates that the received ARINC word was valid in all respects 08 LDU Busy A response of BUSY was sent to received RTS 09 LDU Aborted 10 LDU No SOT 1
56. ELAY WORD CNTR gt CONTROL WORD 1st word within Instruction Block TX INSTRUCTION STACK POINTER ARINC Channels 71 CONTROL WORD DEFI Instruction Block AAA LAST DU L NULL BIT L PARITY ERROR ERROR STRETCH 1 E TE RROR I SUPPRESS AA reserved AO BAD CRC _____ DU IT COUNT HI ERROR IT COUNT LO ERROR PARITY gt LDU TIMEOUT 2 BUCKHORN I reserved I reserved EEE reserved I reserved ARINC Channels 12 WINDOW CONTROL WORD 00 N ALL ARI ECOND ARI IS BIT WITHI ED CAUSI NC ETCH STR 05 Suppress FORCES A NO PARITY CONDITION WITHIN THE WORD Parity EVEN THOUGH PARITY ON HAS
57. ER F58 H This register is used to select the Receiver Data Storage Mode Data bytes can be stored with Time Tag and Status Byte appended to the data block or without these additional bytes Set bit 00 to a logic 0 in order to select the standard mode which appends both Time Tag and Status Byte to each data byte stored in memory Set register bit 00 to a logic 1 to select Data Only mode 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Lo gt ror L RCV DATA STORAGE MODE 0 STANDARD MODE 1 STORE ONLY DATA T Notes 1 There is no Merge Mode option for RS type channels 2 A change in this register is only noted by the firmware after the Start Stop Register contains a value of 0 for at least 1 msec RS 232 422 485 423 OPERATING MODE REGISTER F3A H This register is used to select the mode of operation for all RS 232 422 485 423 channels The channels will operate in regular mode if 0 is written to this register and in fast mode if 1 is written In regular mode operation together with high speed ARINC channels is supported However at high baud rates data will be lost In fast mode operation at high baud rates is supported but high speed ARINC receive modules may lose data In addition in fast mode received bytes are stored without status and time tag For more information on these modes see the section Baud Rate Limitations
58. F40 H Sets the Interrupt and Trigger condition s for ARINC receive channels in Merge Mode Bits 00 07 are the interrupt condition bits while bits 08 15 relate to the hardware trigger bits The trigger conditions set a pulse on the trigger subminiature BNC J1 connector VEIA iii ik ir ER 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Interrupt Conditions G Z G un zj UO L___Rcv LABEL RECEIVED I RCV INTERVAL CT TRIGGER G Z G n zj UO IR DATA WORD CT TRIGGER AAA F CR TUE RCV ERROR WORD RECEIVED _________________rcv STOPPED BUFFER FULL Trigger Conditions Z Gq un El J vo Q lt EX gt DJ BEL RECEIVED I RCV INTERVAL CT TRIGGER I RCV DATA WORD CT TRIGGER A WORD RECEIVED ARCO V STOPPED ON BUFFER FULL Notes The RCV LABEL RECEIVED interrupt or trigger only occurs upon reception of a label which has been marked for interrupt in the filter table In order to activate the RCV INTERVAL CT TRIGGER interrupt or trigger the Receiver Merge Interval Count Trigger Register must also be set ARINC Channels 22 In order t
59. GNAL NAME 43 DIGITAL GROUND GROUND B CASE 144 FUNCTIONAL DEFINITION OF PINS FOR J2 ACCORDING TO PROTOCOL D po INC 429 575 582 2wire Transmit or Receive DATA HI DATA LO unused unused CASE GROUND DIGITAL GROUND 34000 PP INC 561 568 582 6wire Transmit or Receive D pol DATA SYNC CLK HI DATA LO SYNC LO CLK LO a YHOO WwW PP Note 1 A common CASE GROUND and a common DIGITAL GROUND are available for these protocols see connector pinout on previous page 2 For channels containing this type of protocol a jumper has to be disconnected on the soldered side of the printed circuit board as follows CH n JP2n n channel number For example for channel 3 the jumper JP23 30m RS 232 TXD RXD CTS INPUT DTR OUTPUT CASE GROUND DIGITAL GROUND 340000 PP Rs 422 DATA TRANSMIT H DATA TRANSMIT LO DATA RECEIVE H Note 3 DATA RECEIVE LO Note 3 CASE GROUND Inu 145 cut F DIGITAL GROUND Note 3 The receive inputs are terminated with a 1200hm resistor between HI and LO inputs 146 FUNCTIONAL DEFINITION OF P INS FOR 42 ACCORDI ING TO
60. IGGER F48 H This 16 bit value allows the user to generate an interrupt or pollable bit every N number of words The appropriate bit must also be set in the Receiver Merg Interrupt Trigger Condition Register RECEIVER MERGE ERROR COUNT REGISTER F46 H 16 Bit counter Indicates the number of error words received on the channel This counter register wraps around and is only reset by the user F44 H Starts storage of data upon receipt of Label xx H F42 H 15 14 13 12111 10 09 08 07 06 05 04 03 02 01 00 gm LU o L RECEIVER WRAP AROUND LL RECEIVER LABEL TRIGGER I ENABLE RCV FILTER TABLE Receiver pa Data storage is halted when the buffer is full Wrap Around 0 Receiver wraps around the data within the block Receiver 1 Start data storage upon receipt of Label xx Label Trigger 0 Receiver stores data without Start Label Trigger Enable Rev ei Enable filter table stores Labels per table Filter Table 0 Disables table Stores all Labels ARINC Channels 21 RECEIVER MERGE INTERRUPT TRIGGER CONDITION REGISTER
61. INTERRUPTER and as a result will place these 8 bits on lines D00 D07 of the VME bus during the interrupt acknowledge cycle STATUS ID X don t care BASE 22 H Write Read SAME AS ABOVE 134 lrn A DUAL PORT RAM ADDRESS MAPPING DIAGRAM LOGICAL ADDRESS Dip Switch SW1 Board Configuration Registers ADAPTER BOARD IDVECT 22H IDVECT 20H OFFSET REGISTER 06H cl STATUS CNTRL REGISTER 04H DEVICE TYPE 02H D REGISTER 00H lL A16 ADDRESS SPACE I O A16 ADDRESSING EXAMPLE Given required configuration registers base address Then set dip switch SWI to LOGICAL ADDRESS 80 H OFF ON ON ON ON ON ON ON SW1 1 2 3 4 5 6 7 8 1 35 DATA STORAGE AREA AND CNTRL REGISTERS RESERVED 8000 ON BOARD Dual Port RAM A24 A32 ADDRESS SPACI GI E000 H BOARD LAYOUT Toy lt i 2 a m g2 gi COMMUNICATIONS EXTERNAL CONNECTOR TRIGGER P4 P3 OPT ADAPTER 1 BOARD CONNECTORS T
62. MAT The figure below illustrates the format of the TX data words within the memory DATA WORD LO 4th DATA WORD HI 3rd DATA WORD LO 2nd DATA WORD HI 1st location AA in TX data area The figure below defines the locations and bit definitions of the data bytes within the memory gt 24 23 22 21 20 19 18 17 Hi Byte pa m gt 16 15 14 13 12 11 10 09 Lo Byte DATA WORD LO DATA WORD HI di e dae Li Hi Byte Label SAL L_ gt 32 31 30 29 28 27 26 25 Lo Byte 4 0 MSB LSB Note The numbers contained within the bytes above represent the ARINC bit locations within the 32 bit word Label or SAL Serial e i G ard A aeg 32 Data AAA PES e MSB LSB LSB MSB Note that bits 09 through 32 are ordered from LSB to MSB opposite from the Label field which is organized MSB to LSB It is for this reason that the data block is built the way it is Hi Word followed by Lo Word with the Label and the ARINC ARINC Channels 75 field 32 through 25 in the Hi Word and bits 24 through 09 in the Lo Word 76 Tx DATA BLOCK There are two types of blocks of data for transmission The first type is blocks that require no handshaking word with labels and Williamsburg bit oriented 0 The secon bit of the word bloc an LDU In each case
63. RVAL TRIGGER RS 232 422 485 423 CHANNELS PER CHANNEL BAUD RATE UP TO 256K INTERRUPT AND POLLING MODES FROM 5 TO 8 DATA BITS EVEN ODD NO STICK PARITY PROGRAMMABLE HARDWARE TRIGGER SELECTABLE CTS DTR CONTROL RS 232 SELECTABLE LOOPBACK RS 485 32Kx8 DUAL PORT RAM EASY TO INSTALL AND OPERATE The EXC 3000VME VX MAGICard is a multi protocol test and simulation card for VME and VXI systems One card can contain up to 10 ARINC and RS 232 422 485 423 channels in any combination of transmitters and receivers In addition one protocol channel plug in adapter board can be added These include MIL STD 15537 EEE 488 and SDLC In addition unique customer interfaces can usually be implemented either on the main board or in the form of plug in adapter boards The transmitters for all standard protocols operate via a transmitter instruction stack which allows for the scheduling of data transmission and reduce the need for host computer intervention The receivers allow filtering and multi storage modes of data words The card is easy to use and custom application programs can be written in all standard languages such as Pascal C Basic Assembler etc TABLE OF CONTENTS
64. Register The Channel Configuration Register and the Channel Baud Rate Generator must be set before writing to the Global Start Register It is permissible to write a zero to the Channel Start Transmit Register update the instruction stack and data then restart transmission by restoring it to one without writing a zero to the Global Start Register This is necessary in order not to interfere with the receive operation TRANSMIT INSTRUCTION STACK The Transmit Instruction Stack is divided into instruction blocks each containing 4 words Fach section relates to a data block A data block is composed of one or more bytes which the user desires to transmit contiguously The stack is sequential so that the first instruction block relates to the first data block the second to the second data block etc As stated each section contains 4 words The first word is the Control Word which is reserved for future use The second word contains a 16 bit byte_count which instructs the board as to the number of serial bytes to transmit within a particular block The third word contains a 16 bit user supplied data pointer This is a 16 bit address must be even which points to the beginning of the data within the memory The fourth word is the Interblock Time value and is used to program the time between blocks RS Channels 121 TX STACK PNTR ll TRANSMIT BLOCK
65. S channels set the Channel Start Transmit Register to 1 4 SETUP THE TX INSTRUCTION BLOCKS update the Instruction Blocks with information relating to each ARINC TX data block i e error injection pointer to the TX data blocks delay between data blocks See the section on Transmitter Operation for details 5 WRITE THE TX DATA BLOCKS write the ARINC words or bytes for RS channels into the on board memory at locations pointed to by the instruction stack s TX Data Pointers 6 SETUP THE RECEIVER RELATED CHANNEL CONTROL REGISTERS program the Channel Configuration registers parity bit rate etc updat he Receive Start and End Pointers E update the Look Up Table Start Address Register if using this mode update the Filter Table Start Address Register if using this mode update the Label Trigger Register if using a Label to start storage update Counter Trigger Registers not required for RS channels set the Channel Start Receive Register to 1 7 START write to the Global Start Register setting the appropriate channel s start bits Each channel can be started individually at different times see Global Registers and definitions 8 READ THE RECEIVE STATUS REGISTERS i e Word Counter Error Counter
66. SWI1 C JP1 VME VX VME 8 m P2 P1 Note B size card shown The individual functions of the front panel leds are listed below MODID LD3 Reflects the state of the MODID pin on the VXI bus JP19 must be installed This LED has no function in a VME system PASSED LD2 Indicates that the card passed the power on self test routine Reflects the state of the same bit in the Configuration Status Registers READY LD1 Indicates that the card is ready to receive commands Reflects the state of the same bit in the Configuration Status Register 136 DIP SWITCH SETTINGS The MAGICard contains 1 Dip Switch which controls the Logical Address of board The definition of the switch is described below CARD LOGICAL ADDRESS DIP SWITCH SETTINGS Address as described Dipwitch SWI is used to select the card s Logical in the section Configuration Registers The Logical Address is set as shown below Logical Address Switch SW1 1 2 3 4 5 6 7 8 Note numbers indicate LLL switch positions A13 A12 All A10 A9 A8 A7 A6 Switch ON or Closed logic 0 at bit position Switch OFF or OPEN logic 1 at bit position Example for a logical address of 80 Hex set position 1 to OFF or OPEN and ALL other switches to ON or CLOSED
67. TIAL MODE DIAGRAM This diagram illustrates ONE receiver channel 256 X 8 RECEIVER FILTER TABLE RCV DATA END POINTER _ TZT1 a LABEL CONTROL BYTE LS last word TETE ARINC LABEL gt V D UJ a EA Q O Z H po O E UY K H 1 LABEL CONTROL BYTE TABLE POINTER sets the start address of L label filter table The A is used as an index into t LABEL CONTROL BYTE n RCV STATUS WORD esset sai TIME TAG LO TIME TAG HI DATA WORD LO DATA WORD HI L RCV DATA START POINTER R the INC label 1 STORE WORD 0 DON T STORE LA 1 INT his table ERRUPT 53 ARINC Channels 54 DON T INTERRUPT RECEIVE SEQUENTIAL MODE STATUS WORD L WORD RECEIVED w IT COUNT ERROR L 10 BIT CT INVLD WD ERROR L PARITY ERROR IL INVALID CODING ERROR L cap SYNC TIME T RROR gt gt gt gt A reserved VALID WORD pu BUSY LDU ABORTED gt LDU NO SOT Lo EDU BAD CRC gt LDU BAD WORD COUNT A
68. To activate the RCV I NTERVAL CT TR GG Le ER the board Bits 00 07 are the te to the hardware trigger bits subminiature BNC Jl connector Interrupt Conditions reserved Trigger Conditions LTX END OF BLOCK L__txX END OF FRAME reserved L____rcy INTERVAL CT TRIGGER ___________rcv DATA BYTE CT TRIGGER I RCV ERROR RECEIVED ________RCy STOPPED BUFFER FULL u u TX END OF BLOCK IX END OF FRAME reserved RCV INTERVAL CT TRIGGER RCV DATA BYTE CT TRIGGER RCV ERROR RECEIVED RCV STOPPED BUFFER FULL reserved Channel x Rcv RS Channels interrupt or trigger Interval Counter Trigger Register must also be set the To activate the RCV DATA WORD CT IR GG ER interrupt or trigger the Channel x Rcv Word Counter Trigger Reg must also be set LTS RS Channels CHANNEL x STATUS REGISTER RD This register indicates the operational status of the channel This register can be used to poll the status of the channel purposes or can be used with interrupts In this case the register indicates the condition s which caused the interrupt A log
69. X FA L 43 ED LDU bit is relevant to Williamsburg channels only ARINC Channels CHANNEL x STATUS REGISTER RD This register indicates the operational status of the channel This register can be used to poll the status of the channel or it can be used with interrupts When used in conjunction with interrupts the register indicates the condition s which caused the interrupt A logic 1 indicates an active bit Status bits must be reset by the user L RESERVED L TX END OF BLOCK ND OF FRAM E LS L TX L RCV LABEL RECEIVED L___________ RCV INTERVAL CT TRIGGER IL RCV WORD CT TRIGGER RCV ERROR WORD RECEIVED __ A RCV STOPPED ON BUFFER FULL AA TX FAILED LDU A cv BAD LDU Rcv GOOD LDU In Look Up Mode the RCV LABEL RECEIVED Status bit is set upon receipt of any label for which an interrupt has been requested via the label s Control Byte In Sequential Mode it is set upon receipt of any label for which an interrupt has been requested via the filter table The TX LDU FAILED Status bit is relevant only to Williamsburg channels It is set when a block was not successfully transmitted due to timeouts or lack of the desire
70. amsburg ALO word must have a word count of 1 It requires as response a Williamsburg ALR word within 200 ms If a timeout occurs the ALO is retransmitted a maximum of two more times The timing of the interblock delay begins immediately upon reception of a legal ALR word or after ARINC Channels 84 the third timeout 85 LDU BLOCK A block containing an LDU must contain as its first word a Williamsburg RTS word When this word is transmitted a response of CTS NCTS or BUSY is expected within 150 ms for high speed operation or within 500 ms for low or variable speed operation If a NCTS or illegal CTS is received the RTS is retransmitted up to 4 more times before passing on to the next block The delay is 100 ms for high speed operation and 500 ms for low or variable speed If a BUSY is received the RTS is retransmitted up to 19 more times befor passing on to the next block The delay is 1 sec for high speed operation and 15 sec for low or variable speed operation If a timeout occurs the RTS is retransmitted up to 4 more times before passing on to the next block If a legal CTS word is received the next word sent depends on the state of the Buckhorn Window bit of the message s Control Word If this bit is set to 1 a LCW is constructed and transmitted It contains a remaining LDU field of 1 and the word count from the RTS Otherwise a LCW is not sent
71. burg channel It allows the user to reload new messages after the termination of transmission and to transmit them without interfering with the receive function The register is automatically cleared to zero LT CHANNEL x RCV INTERVAL COUNTER TRIGGER REGISTER WR SEQUENTIAL MODI This register allows the user to generate an interrupt and set a flag upon reception of every N number of words The appropriate bit must also be set in the Channel x Interrupt Trigger Condition Register CHANNEL x RCV ERROR COUNT REGISTER RD SEQUENTIAL MODE This 16 bit counter indicates the number of errors received on a particular channel This register wraps around The user can reset this register by writing 0000 to it CHANNEL x RCV LABEL TRIGGER REGISTER WR SEQUENTIAL MODE This register is used in conjunction with the Receiver Label Trigger bit within the Configuration Register to enable the reception and storage of data upon receipt of a specific ARINC label xxxx xxxx 00 LABEL tS 8 7 0 ARINC Channels 39 CHANNEL x TX INSTRUCTION STACK POINTER WR Sets the starting address of the TX Instruction Stack This address must be even For a Williamsburg channel which is being started that has no data to transmit the stack pointer
72. ceiver buffer for all channels Each Receive Status Word in this case is tagged with Channel ID information 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 L RCV DATA STORAGE MODE 0 STANDARD MODE Lo gt S npon 0 1 STORE ONLY DATA L MERGE MODE OPTION 0 INDEPENDENT CHANN 1 MERGE MODE GI FH Notes 1 If Data Only Storage Mode is selected bit 00 set to 1 storage will be per independent channel regardless of the state of bit 01 2 Data Only Storage Mode is not available in Lookup Table Mode 3 Merge Mode is not available for Williamsburg channels or for RS 232 422 or 485 channels Even if Merge Mode is chosen these channels will store received data in the channel receive buffer 4 A change in this register is only noted by the firmware after the Start Stop Register contains a value of 0 for at least 1 msec ARINC Channels 18 RECEIVER MERGE START POINTER E56 H Set the start address of the Receive Data Buffer The address must be even 1E54 H Set the End Address of the Receive Data Buffer The data will wrap around or stop when the buffer is full End address is reached depending upon the contents of the Receiver Merge Configuration Reg
73. ch is organized MSB to LSB It is for this reason that the data block ARINC Channels 68 is built the way it is Hi Word followed by Lo Word with the Label and the ARINC field 32 through 25 in the Hi Word and bits 24 through 09 in the Lo Word ARINC Channels 69 TRANSMITTER OPERATION WILLIAMSBURG BUCKHORN CHANNELS The MAGICard Williamsburg channel sets support the Williamsburg protocol section 2 5 of the ARINC 429 specification as well as the fast Buckhorn protocol section 2 6 of the ARINC 429 spec Both protocols are supported at both high and low speed The method implemented in the transmit mode requires the user to create an instruction stack for the transmitter channel write the data into the Dual Port RAM and start transmission by writing to the Start Register found within the Global Register area The sequence of writes to memory is not important except for the Write to Start Register operation which is performed last TRANSMIT INSTRUCTION STACK The Transmit Instruction Stack is divided into Instruction Blocks each containing 4 words Fach Instruction Block relates to a Data Buffer A Data Buffer contains one or more ARINC words which the user desires to transmit with the same amount of delay time between each word The stack is sequential so that the first Instruction Block relates to th
74. d in conjunction with or instead of interrupt processing MERGE MODE The Merge Mode operates in the same manner as the Sequential Mode except that all receive channels are merged into one data buffer area The control registers for the Merge Mode are located and defined in the global register section In this mode the receive data blocks are stored in sequential order and each receive Status Word is tagged with a Channel ID indicating on which channel the data was received Each data block contains a Time Tag word as in the standard Sequential Mode of operation ARINC Channels 49 EQUENT BUFE ER STORAGE EQUENCE ithin t hannel he drawing bel T W E The Start and s b E ow illustrates t AL MOD GI he way in which the receive data blocks are stored he dual port RAM while in the sequential mode of Error Count Register is updated with operation The Receiver every invalid word which is stored End pointers set up the buffer top when the end pointer is reached or will uffer depending upon the condition of the hannel Configuration Register The Time Tag Tag is set to zero upon power up or software siz The receive data storage will wrap around to the beginning of the Receiver Wrap Around bit within the resolution is 10 usec bit The Time reset The contents of the Receiver
75. d response It is relevant to blocks containing a Williamsburg TEST word an ALO word or an LDU blocks requiring responses The RCV BAD LDU and RCV GOOD LDU bits are relevant only to Williamsburg channels They are set according to the quality of received LDU s and are not associated with an interrupt Conditions which cause the BAD LDU bit to be set are bad word ARINC Channels count bad CRC missing SOT timeout sent response of BUSY and LDU reception aborted due to reception of another RTS or ALO ARINC Channels 45 CHANNEL x DEST CODE BUSY BUFFER START WR For Williamsburg channels it is possible to force a response of BUSY to an RTS for test purposes by using this register If the non zero value of this register matches the destination code of the received RTS the channel will respond with BUSY instead of the normal CTS For transmission in Data Rate Mode the user must allocate a scratch buffer for use by the firmware Its length must be at least TX INSTRUCTION COUNTER x 10 4 bytes If the buffer is not long enough the channel will turn itself off without transmitting This register contains the start address of the buffer The address must be a word boundary EL x FULL DUPLE For Williamsburg channels it is possible to operate in full duplex or half duplex mode as described be
76. e Interword delay byt specifies the time between blocks within this data block The resolution is in the form of bit times according to the transmission b E a it rate At the Lo Speed setting the resolution will be 80 usec bit while at he Hi Speed setting it would be 10 usec bit The programmable setting would be ccording to its bit rate The Word Counter is used to specify the number of data words within this data block 1 255 TX DATA POINTER This register is used to set the start address of the transmit data buffer The size of the buffer is determined by the Word Count value T NTERBLOCK TIME DATA RATE WORD This word has two functions In the standard transmit mode the Instruction Blocks are accessed sequentially and their associated data words transmitted according to this sequential order The Interblock Time allows the user to specify the time between data blocks The resolution of this 16 bit word is according to the transmission bit rate At the Lo Speed setting the resolution will be 80 usec bit while at the Hi Speed setting it would be 10 usec bit The programmable setting would be according to its bit rate The interblock time is inserted AFTER the block transmission In Data Rate mode the user can specify the transmission period of the particular data block If the number n is written to thi
77. e card is an integer which varies between 0 and 255 and is defined by the user via the 8 pole dipswitch SWI see the section on dipswitch setup at the end of this manual In order to ensure correct operation of the MAGICard within the user s VME or VXI system the configuration registers must be re initialized after power up or after assertion of SYSRESET For a full explanation of the VXI Configuration registers and other topics relating to operation of the VXI bus refer to the VXI Bus System Specification 127 Kh Configuration Register Memory Map ADAPTER BOARD IDVECT BASE 22 H DVECT BASE 20 H OFFSET REGISTER BASE 06 H STATUS CONTROL REGISTER BASE 04 H DEVICE TYPE BASE 02 H D REGISTER BASE 00 H D REGISTER VXI only BASE 00 Read The contents of this 16 bit register provides the following information about the MAGICard s configuration 0 1 A32 ADDRESS SPACE JP1 not installed 0 O A24 ADDRESS SPACE JP1 installed REGISTER BASED MANUFACTURER ID 3924 Dec F54 Hex Note This register contains the same value whether set up for VME or VXI installation The VXI
78. e first data block the second to the second data block etc As stated each Instruction Block contains 4 words The first word is the Control Word which contains error injection parameters and Williamsburg control The second word contains an 8 bit Word Count which instructs the board as to the number of ARINC words to transmit within a particular block and an 8 bit inter word delay value which programs the time between words within the same buffer The third word contains a 16 bit user supplied data pointer This is a 16 bit address must be even which points to the beginning of the data words within the memory The fourth word is the Interblock Time value and is used to program the time between data block transfers see diagram for details ARINC Channels 70 I TTI TRANSMI BLOCK DIAGRAM TX INSTRUCTION STACK rr eee i TX DATA BUFFERS DATA WORD LO ess asi DATA WORD HI v r NTERBLOCK TIME P Se 00 TX DATA POINTER i k Instruction HA DATA WORD LO Block 2 INTERWORD DELAY WORD CNTR kl DATA WORD HI CONTROL WORD Pe INTERBLOCK TIME i m TX DATA POINTER Instruction 7 Block 1 NTERWORD D
79. e mode which allows the user to store words in specific locations of memory according to the Label and the Merge Mode which syphons ALL receiver channel data into ONE receiver buffer area In all these modes the data words are stored with a 16 bit Receiver Status Word and a 32 bit time tag value In data only mode the status and time tag is not stored In the Merge Mode the channel ID information indicating on which channel the data was received is contained within the Receiver Status Word OPERATION The board is initialized in a wait loop looking for a START command from the computer This command issued by writing to the Global Start Register instructs the board to begin operation on the active channel s SEQUENTIAL MODE The sequential mode has a software selectable feature which filters the storage of specific user selected Labels or stores all Labels within a buffer The data buffer s size and location within the memory is programmed via a Start and End P E ointer Each received ARINC data word is tagged with a Status word indicating he status of the receive word and a 32 bit Time Tag value These five 16 bit words make up a single receive data block In addition the sequential mode offers the user the capability of storing just the ARINC data without the Time Tag and Status Words This is global selection which affec
80. each channel It is also possible for multiple channels to share memory areas more than one receiver channel for example may point to and use the same Label Look Up Table which controls which labels will be stored by the card The transmitter and receiver operations necessary to operate the card are described below in general terms See the sections on the Transmitter and Receive Operations for details after power on 1 POWER ON OPERATION board clears the memory and executes initialization procedure user waits for BOARD READY Register to be valid s register definitions 2 SETUP VERIFY THE GLOBAL REGISTERS user can check the results of the power on self test by reading the Board Status Register user can verify the configuration of each channel TX or Rcv by reading the Configuration Status Registers update the Programmable Bit Rate Register only if it is used update the IROSEL field in the CONTROL configuration register 3 SETUP THE TRANSMITTER RELATED CHANNEL CONTROL REGISTERS program the Channel Configuration registers parity bit rate etc update the Transmit Instruction Stack Pointer for each channel update the Transmit Instruction Counter t G update the Transmit Amplitude Register for each channel for R
81. er All interrupts from a Williamsburg channel set the bit corresponding to the position of the receive module 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SR E SEE ARINC Channels 13 RESERVED 9 8 7 6 5 4 3 2 1 0 CHANNEL BITS 14 STE BLE I RATE PROGRAMMA Sel only read by the firmware when the Start Register i e all channels are inactive lects the programmable bit rate value for the ARI INC channels This register is 7F7A contains a value of 0 for at least 1 msec 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Bit Rate Value lt o gt lt gt LI gt same value as I Baud Rate Generator Oscillator Frequency bit If the Baud Rate Generator oscillator frequency is 33MHz as indicated by a value of 0 in the Baud Rate Generator Oscillator Frequency bit of the Board Status Register bit 15 of the Programmable Bit Rate Register must be 0 The formula for calculating the Bit Rate Value BRV is 4125 BRV ek freq Khz Examp1 Desired frequency is 100 Khz 4125 BRV I 41 1 40 Dec or 0028 Hex 100 NOTE THAT THE NUMBER HAS BEEN ROUNDED OFF 41 NOT 41 25 Write the word 0028 H to this register llator frequency is 40MHz as indicated by a value bit of the B
82. g only of ARINC 429 data words and Williamsburg SOLO words requires no response This is indicated in the block s instruction block s control word by setting the LDU bit to 0 Such a block will be transmitted with the specified interword delay and intermessage delay before the next block GI BLOCKS REQUIRING RESPONSI If the LDU bit of a block s control word in its instruction block is set that indicates that the block requires response For such a block the intermessag delay is timed from the reception of th xpected response or after the maximum number of timeouts The label field of every word within a block requiring a response must contain the destination SAL found in the Channel TX SAL Register There are thr types of blocks that require responses which are described below TEST BLOCK The TEST LOOP sequence is used to test the integrity of a Williamsburg communication link A block containing a Williamsburg TEST word must have a word count of 1 It requires as response a Williamsburg LOOP word with the identical 16 bit test pattern within 200 ms If a timeout occurs the TEST word is not retransmitted The timing of the interblock delay begins immediately upon reception of a legal LOOP word or a timeout ALO BLOCK The ALO ALR sequence is used to establish Williamsburg communiciation between two devices A block containing a Willi
83. hannel CCx RS 485 TX RCV 7 3728 MHz 1 channel Zx RS 423 Tx Rcv 8 0000MHz 1 channel 3 ZZx RS 423 Tx Rcv 7 3728MHz 1 channel 3 Dx ARINC 429 Transmitter 1 channel Ex ARINC 429 Receiver 1 channel Fx ARINC 429 Williamsburg set 3 channels Gx ARINC 561 Transmitter 1 channel Hx ARINC 561 Receiver 1 channel Ix ARINC 575 Transmitter 1 channel Jx ARINC 575 Receiver 1 channel Kx ARINC 568 Transmitter 1 channel Lx ARINC 568 Receiver 1 channel Mx ARINC 582 2wire Transmitter 1 channel Nx ARINC 582 2wire Receiver 1 channel Ox ARINC 582 6wire Transmitter 1 channel Px ARINC 582 6wire Receiver 1 channel ol MB BCRM V 1553B BC RT Monitor adapter board S1 MB IEEE488 V IEEE 488 Interface adapter board TI MB SDLC V 4 channels of SDLC 232 422 adapter board Important Notes 1 The x following the Option Code denot 1 2 When ordering a card with a number of part number must be in the following form Example D2 Two ARINC 429 Transmitters s the number of channels per card different protocol channels the EXC 3000VM E VX AxBxCxDx 3 RS 423 channel reguires firmware Revision 1 31 and up Part numbers for additional Channel Modules EST EXC 3000 AM Part for additional RS 232 module set EXC 3000 PM Part for additional AR 152 NC 582_6wire Receiver module set The information contained in t
84. his document is believed to be accurate However no responsibility is assumed by Excalibur Systems Inc for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice January 1996 Rev C 2 153
85. i Speed setting it would be 10 usec bit The programmable setting would be ccording to its bit rate The Word Counter is used to specify the number of data words within this data block 1 255 TX DATA POINTER This register is used to set the start address of the transmit data buffer The size of the buffer is determined by the Word Count value NTERBLOCK TIME During transmission Instruction Blocks ar accessed sequentially and their associated data words transmitted according to this sequential order The Interblock Time allows the user to specify the time between data blocks For blocks that require no response LDU bit of the control word in the command block set to 0 the resolution of this 16 bit word is according to the transmission bit rate At the Lo Speed setting the resolution will be 80 usec bit while at the Hi Speed setting it would be 10 usec bit The programmable setting would be according to its bit rate The interblock time is inserted AFTE the block transmission For blocks that do require a response the resolution of this 16 bit word is always 80 usec bit regardless of the speed setting The interblock time is inserted AFTER reception of th xpected response or after the maximum number of timeouts For these blocks the delay may be up to 1 ms longer than requested ARINC Channels 74 Tx DATA BLOCK FOR
86. ic 1 indicates an active bit Status bits are only reset by the user or a reset L RESERVED L TX END OF BLOCK IND OF FRAME E L TX reserved IL rcv INTERVAL CT TRIGGER L RCV WORD CT TRIGGER L RCV ERROR RECEIVED eee RCV STOPPED ON BUFFER FULL CHANNEL x START TRANSMIT REGISTER WR When the channel is enabled via the Global Start Register writing a one to this register initiates transmission according to the transmit instruction block and data which has been previously set up Setting it to zero will terminate the transmission but allow the receive operation to continue It is permissible to set this register to zero update the transmit command block and data and restore the register to one while the channel is enabled When the requested transmit operation is completed this register is reset to zero CHANNEL x START RECEIVE REGISTER WR When the channel is enabled via the Global Start Register writing a one to this register initiates receive according to the receive parameters which have been previously set up Setting it to zero will terminate the receive operation but allow transmission to continue It is permissible to set this register to zero update the receive parameters and
87. in the Channel Control Register Block for the Williamsburg channel must match the Destination SAL field 63 H in this example and the Rx SAL Register must match the Source SAL field ARINC Channels 80 IZ DUTY CYCLE The MAGICard card has a processing overhead time of approximately 50 microseconds per channel 150 microseconds per Williamsburg channel during actual reception or transmission This permits 10 channels to run at hi speed with an interword delay of 18 bit times resulting in an effective throughput of 1 word per channel every 500 microseconds If fewer channels are used a smaller inter word delay can be realized If the duty cycle is exceeded in the Transmit Mode all data will be sent but the interword times may be elongated In the Receive Mode exceeding the maximum duty cycle will result in occasional loss of data ARINC Channels 81 ARINC Channels MAG ICARD MP LEM ENTAT ON OF AMSBURG PROTOCOL 82 7 FULL HALF DUPLEX GI A Williamsburg channel can be configured for full or half duplex operation by writing to the Channel Full Duplex Register in the Channel Control Register Block FULL DUPLEX In full duplex operation the channel is capable of simultaneously handling a block of incoming data and transmitting a block HALF DUPLEX In half duple
88. ion and are described in the Channel Register section of this manual RS Channels 117 BUFFER STORAGE SEQUENCE The drawing below illustrates the way in which the receive data blocks are stored dual port RAM while in the sequential mode of operation within the end pointe End pointers set up the buffer size Th r is reached or will Tim RCV DATA END POINTER written by user Ls receiv T 7 Tag resolution is Byte are described within this section ME TAG WORD LO ME TAG WORD E TAG WOR HI 10 Hsec bit T D LO TIME TAG WORD H STATUS BYTE DATA TIME TAG WORD LO TIME TAG WORD HI STATUS BYTE m a I lst block RCV DATA START POINTER written by user RS Channels 118 BYTI n block STATUS BYTE DATA BYTE The contents o The Start and data storage will stop when the wrap around to the beginning of the buffer depending upon the condition of the Receiver Wrap Around bit within the Channel Configuration Register Th the Receiver Status TIME TAG WORD FORMAT Time As stated above the Time Tag is a 32 bit word made up of two 16 bit words Tag Hi followed by
89. is set in the message s Control Word a LCW word will be automatically inserted before the SOT with a remaining LDU count of 1 and a word count which matches the word count field of the RTS ARINC Channels 79 LT TEST EXAMPLI This is an example of how to build a TEST block to test the integrity of a Williamsburg interface with a device whose SAL is 63 H The block consists of a single TEST word as shown 0101 1010 1111 0000 TEST PATTERN 5AFO H ae TEST PATTERN 0110 0011 0101 0000 ist word of block L SAL TEST CODE bit 15 bit 0 The block s instruction block must have a word count of 1 and the LDU bit of the control word must be set to 1 The Channel Tx SAL Register in the Channel Control Register Block for the Williamsburg channel must match the SAL field 63 H in this example ALO EXAMPLE This is an example of how to build an ALO block to establish Williamsburg communication with a device whose SAL is 63 H The block consists of a single ALO word as shown The SAL of the source is 57 H Window Size bit Buckhorn only 0101 0111 0001 0010 Version Number 2 a SRC SAL VER 0110 0011 0100 0111 Ist word of block L DEST SAL ALO CODE bit 15 bit 0 The block s instruction block must have a word count of 1 and the LDU bit of the control word must be set to 1 The Channel Tx SAL Register
90. ister Wrap around bit E52 H Indicates the current address within the Receiver buffer This pointer value is incremented after th ntire receiver block ARINC word time tag and status is written into memory RECEIVER MERGE FILTER TABLE START ADDRESS 7F50 H Sets the start address of the 256x8 Label Filter Table as described in the Sequential storage mode The address must be even RECEIVER MERGE WORD COUNTER F4E H Indicates the number of words received 0 64k This register wraps around and may be reset by the user only after the channel is stopped RECEIVER MERGE WORD COUNT TRIGGER REG FAC H Sets a trigger used for polling or interrupts which indicates when a specific number of words have been received 1 64k The appropriate bit must also be set in the Receiver Merge Interrupt Trigger Condition Register RECEIVER MERGE BUFFER WRAPAROUND REG 7F4A H ARINC Channels 19 This register contains 2 bits for synchronization with the C drivers If bit 14 is set to 1 the receive buffer has wrapped around once since the last data read If bit 15 is set to 1 there have been multiple wraparounds ARINC Channels 20 RECEIVER MERGE INTERVAL COUNT TR
91. it That is once in the RESET state the card must remain in this state for at least 100 usec While in the RESET state the card is completely inactive and will not respond to any commands Upon releasing the card from the RESET state write 0 to this bit the card will perform its self test routines The board may also be reset via the Software Reset Register defined whithin the main body of this manual This second method is the preferred mechanism for resetting the card SYSFAIL INHIBIT Writing a 1 to this bit disables the card from driving the VME bus line SYSFAIL in the case when JP5 is shorted s Jumpers otherwise it has no effect 131 ROSEL 2 0 Writing to these bits selects which one of the VME bus Interrupt Request lines IRQ1 IRQ7 will be driven active when the card generates an interrupt The following table shows the relationship between IROSEL 2 0 and IRQ7 1 ECTED INTERRUPT L NONE 0 0 0 IRO1 0 IRO2 0 1 0 iv 4 IRQ4 1 0 0 IRQ5 1 0 1 IRQ6 1 1 0 USING INTERRUPTS Note The interrupt generated on the selected IRO line is the logical OR of the two interrupt generating sources on the card An interrupt which was generated by the board Controlle
92. l or the VXI kl ee ee ee l 5 4 3 2 11 10 o3 os 0o7 o6 0o5 oa o3 0o2 o1 Joo subminiature BNC Jl connector Interrupt Conditions LTX END OF BLOCK L__TX END OF FRAME L RCV LABEL RECEIVED Rev INTERVAL CT TRIGGER ____________rcv DATA WORD CT TRIGGER ___Rc ERROR WORD RECEIVED L___Rcv STOPPED BUFFER FULL L TX FAILED LDU Trigger Conditions L TX END OF BLOCK TX END OF FRAME Le ___________rcv LABEL RECEIVED Rc INTERVAL CT TRIGGER L_ K lt Cv DATA WORD CT TRIGGER L__ RCV ERROR WORD RECEIVED ARO V STOPPED BUFFER FULL TX FAILED LDU The RCV LAI EL R ECE ED reception of a label which has been marked for interrupt or trigger only occurs upon interrupt in a filter table or lookup table Channel x Rc ARINC Channels vV To activate the RCV I 42 NTERVAL CT TRIGGER interrupt or trigger the Interval Counter Trigger Register must also be set To activate the RCV DATA WORD CT TRIGGER interrupt or trigger the Channel x Rcv Word Counter Trigger Register must also be set The T
93. low Writing a 1 to this register configures the channel for full duplex operation Writing a 0 results in half duplex operation For transmission in Data Rate Mode this register contains the end address of the buffer which must be assigned by the user CHANNEL x TX SAL REGISTER WR This register is relevant to Williamsburg channels only This register contains the SAL system address label of the destination for transmitted Williamsburg blocks Every word contained in a block of Williamsburg format data to be transmitted must contain this SAL in its label field This value is used for constructing responses CTS NCTS BUSY ACK NAK SYN ALR and LOOP CHANNEL x RCV SAL REGISTER WR This register is relevant to Williamsburg channels only This register contains the SAL of the label Only received words which contain this SAL in their label field are considered to be in the Williamsburg format Words not containing this SAL are taken to be ARINC 429 words with labels ARINC Channels 46 GENERAL INFORMATION The user sets up each receiver channel s mode of operation by writing to the various Channel Control Registers one set per channel Each receiver channel has three basic modes of operation Sequential mode which stores data in sequential locations within the receive data area the Look up tabl
94. nels 86 If data is receive which does not contain the SAL of the Williamsburg channel as found in the Channel Rx SAL Register or has a parity error the data is stored sequentially in the receive data area and no further action is taken If an RTS word is received the channel enters LDU mode If the word count field of the RTS word is less than the legal minimum of 3 a response of NCTS is sent If the destination code field of the RTS matches the non zero contents of the Channel Destination Code Busy Register a response of BUSY is sent this is for test purposes only Otherwise a response of CTS is sent and reception of an LCW word Buckhorn only SOT word data words and an EOT word is expected If an LCW word is received the expected number of LDUs is specified in the remaining LDUs field If the LDU is received with no errors a response of ACK is sent A NAK word is sent in the following cases A data word LCW word or EOT word is received when expecting SOT status code 80 H An expected LCW is not received Remaining LDUs field of received LCW is not 1 less than in previous LCW status code 7F H EOT is received earlier or later than expected RTS or LCW indicates word count less than 3 status code 88 H CRC field in the EOT does not agree with the calculated CRC status code 85 H EOT not received within 2 5 secs of having sent CTS low or
95. o activate the RCV DATA WORD CT trigger the Receiver Merge Word Count Trigger Reg m 23 IR GG ER interrupt or ust also be set ARINC Channels RECEIVER MERGE STATUS REGISTER TESE H This register indicates the operational status of the Merge Mode receive buffer This register can be used to poll the status of the channel or it can be used with interrupts When used in conjunction with interrupts the register indicates the condition s which caused the interrupt A logic 1 indicates an active bit Status bits are only reset by the user I RESERVED L UNUSI GI UO tH U L unus L rcv LABEL RECEIVED 2 RCV INTERVAL CT TRIGGER IL RCV WORD CT TRIGGER _ RCV ERROR WORD RECEIVED A RCV STOPPED BUFFER FULL The RCV LABEL RECEIVED Status bit is set upon receipt of any label for which an interrupt has been requested via the filter table NTERRUPT STATUS BUSY REGISTER 7F3C H The Interrupt Status Busy Register indicates whether th Channel x Status Register the Receiver Merge Status Register and the Interrupt Status Register may be accessed by the user A 1 in any channel bit position indicates that the corres
96. oard Status If the Baud Rate Generator osci of 1 in the Baud Rate Generator Oscillator Frequency Register bit 15 of the Programmable calculating the Bit Rate Value BRV is 5000 BRV Sil freq Khz Examp1 Desired frequency is 12 5 Khz 5000 BRV 1 400 1 12 5 Write the word 818F H to this register Bit Rate Register must be 1 15 The formula for 399 Dec or 018F Hex ARINC Channels CHANNEL x CONFIGURATION STATUS REGISTER see Global Memory Map This register indicates to the host the type of channel configured in each channel socket on the board 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 LO RESERVED u Configuration Status Code 43210 Configuration Status Code 000 0 07 Undefined Channel 00001 ARINC 429 Receive Channel 00010 ARINC 429 Transmit Channel o 0 011 ARINC 561 Receive Channel 00100 ARINC 561 Transmit Channel o o 1 ARINC 568 Receive Channel 00 0 ARINC 568 Transmit Channel 00 1 ARINC 575 Receive Channel 01000 ARINC 575 Transmit Channel 0 001 ARINC 582 2 Wire Receiv Channel 01010 ARINC 5
97. ode 0 Look up Table Mode Receiver Ica Data storage is halted when the buffer is full Wrap Around 0 Receiver wraps around the data within the block This bit is not used in Lookup Table Storage Mode Receiver Ica Start data storage upon receipt of Label xx Label Trigger 0 Receiver stores data without Start Label Trigger TX Mode Select ie Data Rate mode per data block See text see note 0 Interblock Gap Time mode Enable Rev 1 Enable filter table stores Labels per table Filter Table 0 Disables table Stores all Labels Notes a Data Rate value and to send data blocks on a scheduled data rate basis Block 1 every 50 ms and Data Block 2 every 25 ms etc In this TX Mode Select This bit allows the user to select the transmission mode A logic 1 instructs the transmitter to use the Interblock Time Data Rate Word as ie Data mode a scratch buffer must be allocated via the Channel Buffer Start and Channel Buffer End Registers This mode is not supported by Williamsburg channels A logic 0 instructs the transmitter to use the Interblock Time Data Rate Word as an Inter block Gap Time 2 Receiver Label Trigger S description of the RCV Start Label Register Trigger 3 Tx Rise Fall Time bit Not applicable for ARINC 561 568 582 6wire channels ARINC Channels 36 CHANNEL x RECEIVE DATA START POINTER WR
98. p Register must be set to a logic 1 The desired channel Start bits are then set within this register The card s operation is then started by pulsing the EXTSTRTS line ASYNCHRONOUS START JP3 Short pins 1 and 2 EXTRSTS External Reset The card may be initialized by applying a low going pulse 100ns minimum on this line The initialization function performed here is the same as that performed by writing to the Card Initialization Register If this function is enabled then pins 1 and 2 of JP4 must be shorted If it is not then pins 2 and 3 of JP4 must be shorted together 139 FACTORY DEFAULT JUMPER SETTINGS JP2 Installed A24 Address Space JP4 Short pins 2 and 3 Disable Ext Reset Option JP3 Short pins 2 and 3 Disable External Start Option EXC 3000VME VXI C xx board JP30 Short pins 1 and 2 Positive pulses on the External JP19 Installed Connect MODID to bus only for the Trigger connector Note For this minimum configuration all other jumpers are left open 140 ee EXTERNAL TRIGGER H he external trigger pulse signal is open collector with a pull up resistor and hort circuit protection The signal polarity and timing is shown below u lt 500 nsec gt ov AS ia Note In case negative polarity pulses are required short jumper JP
99. ponding Channel Status Register and the global Interrupt Status Register are busy and should not be accessed by the user A 1 in bit 10 indicates that the Receiver Merge Status Register is busy Note Before accessing the global Interrupt Status Register the user should wait until the Interrupt Status Busy Register 0 He will then have at least 15 microseconds to safely access the status registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 L RESERVED I M 9 8 7 6 5 4 3 2 1 0 Channel Bits ARINC Channels BLOCKS DATA START POI DATA CURRE LOOK UP TABLE START Al DATA WORD COUNT RAPARO TX SAL REGI RCV SAL RE 25 ER START D4E D3E D2E D4C D4A D48 D46 D44 D42 D40 D3C D3A D38 D36 D34 D32 D30 D2C D2A D28 D26 D24 D22 D20 ARINC Channels
100. r will result in the interrupt routine whose vector resides in the IDVECT register The card will place the value in the DVECT register called the STATUS ID onto the VME data lines when issuing the interrupt acknowledge cycle Th user s processor will use this value to determine which entry in the user s interrupt vector table to jump to Within this interrupt routine the actual cause of the interrupt can be determined by polling the INTERRUPT_STATUS Register Likewise an interrupt which was generated b Es y the ADAPTER BOARD will result in the interrupt routine whose vector resides in he ADAPTER_BOARD_IDVECT register For all interrupts the interrupt request is cleared automatically at the end of the interrupt acknowledge cycle This method is referred to within the VME specification as ROAK Release On Acknowledge CONFIG 0 1 Reserved for future use A24 A32 ENABLE Memory enable Writing a 1 to this bit enables access to the card s A24 or A32 VME bus registers and memory If this bit is set to 0 none of the on card registers and memory which are resident in the A24 or A32 address spaces may be accessed The Configuration registers of course remain accessible regardless of the state of this bit as they reside in the A16 address space of the card 132
101. restore the register to one while the channel is enabled When the requested receive operation is completed this register is reset to zero RS Channels GENERAL INFORMATION The user sets up each channel s mode of receive operation by writing to the various Channel Control Registers one set per channel In sequential mode the data bytes are stored with a status byte and a 32 bit time tag value In Data Only Mode and Fast Operation Mode only data is stored OPERATION The board is initialized in a wait loop looking for a START command from the computer This command issued by writing to the Global Start Register instructs the board to begin operation on the ACTIVE channel s Additionally the channel Start Receive Register must be written to The data is stored in sequential order The data buffer s size and location within the memory is programmed via a Start and End pointer Each received data byte has an accompanying Status Byte and a 32 bit Time Tag value These six bytes make up a single receive data block In addition the data can be stored without the Time Tag or Status This is global selection which affects all receiver channels see Receiver Data Storage Mode Register in the Global Register section of this manual Interrupts and pollable status registers allow for numerous event recognit
102. s values ar and whether or not interrupts are used The maximum baud rates are approximat dependent upon many factors such as the si The allowed baud rates are but concurrent high speed ARINC operation is not disturbed In each received byte is stored without status and time tag but high speed ARINC channels may lose data High baud The following determine which baud rates since thes e of transmitted blocks In all equations BR is the baud rate in Khz R is the number of RS 232 422 485 423 channels running on the board and A is the number of ARINC channels running on the board a Williamsburg channel set counts as 3 ARINC channels For fast operation with channels working half duplex receiving only the approximate maximum baud rate which will not result in data loss is 160 000 BR Khz 120 188xR 50xA For fast operation with channels working full duplex transmitting and receiving the approximate maximum baud rate which will not result in data loss is 160 000 BR Khz 120 372xR 50xA For the regular operation mode with channels working full duplex the approximate maximum baud rate which will not result in data and receiving loss is 10 000 BR Khz 120 51xR 50xA 125 transmitting RS Channels Note The maximum allowed baud rate for RS 232 422 485 423 channels is 250 Kbaud even if the calculated value of BR is greater
103. s location then the message will be transmitted every n bit times At the Lo Speed setting one bit time is 80 usec while at the Hi Speed setting it is 10 usec At the programmable setting a bit time is according to the specified bit rate The selection of the modes is determined by the TX Mode Select bit within the Channel Configuration Register Note that in Data Rate mode a scratch buffer for the firmware must be allocated via the Channel Buffer Start and Channel Buffer End Registers ARINC Channels 67 Tx DATA BLOCK FORMAT The figure below illustrates the format of the TX data words within the memory DATA WORD LO Ath DATA WORD HI 3rd DATA WORD LO 2nd DATA WORD HI 1st location in the nt TX data area The figure below defines the locations and bit definitions of the data bytes within the memory gt 24 23 22 21 20 19 18 17 Hi Byte m gt 16 15 14 13 12 11 10 09 Lo Byte DATA WORD LO DATA WORD HI di e dae Li Hi Byte Label L_ gt 32 31 30 29 28 27 26 25 Lo Byte 4 0 MSB LSB Note The numbers contained within the bytes above represent the ARINC bit locations within the 32 bit word Label Serial i m 2 aT ir OE HO ard A E emek IO 32 Note that bits 09 through 32 are ordered from LSB to MSB opposite from the Label field whi
104. s register will cause the time tag to be reset to 0 Upon completion of the Time Tag Reset operation this register will be cleared by the board START STOP REGISTER JETA H The user can start one or more channels at the same time Writing a 1 to bit 00 starts channel 0 operation writing a 1 to the next location starts channel 1 etc Writing a 0 to a bit location will stop that channel s operation To start or stop a Williamsburg channel it is necessary to write to the bit corresponding to the channel socket of the receive module For example for a Williamsburg channel whose receive module resides in channel socket 7 transmit module in channel socket 8 and CRC module in channel socket 9 it is necessary to write a 1 to bit 07 to turn the channel on or a 0 to turn it off The user should wait a minimum of 500 usec between writes to the START STOP register The Enable External Start bit is used in conjunction with on board jumpers to start the board s operation from an external event see section on VME VXI Jumpers and External Triggers for details L 2 ENABLE EXTERNAL START 0 disables 1 enables Note a change in a channel s TX Amplitude Register or Configuration Register in the Programmable Bit Rate Register or in the Receiver Data Storage Mode Register is acted upon by the firmware only after the Start Stop Register contains
105. specification reguires all VXI devices to identify themselves via the above fields This location is not defined m under the VME specification 128 BASE 02 Read This 16 bit register contains a fixed Device Type Identifier as well as a four bit field which reflects the Required Memory usage of the card 1 1 1 1 REQUIRED MEMORY m A32 SPACE JP1 not installed 0 1 1 1 REQUIRED MEMORY m A24 SPACE JP1 installed MODEL CODE 3000 Dec BB8 Hex Note This register contains the same value whether set up for VME or VXI installation The VXI specification reguires all VXI devices to identify themselves via the above fields This location is not defined under the VME specification 129 STATUS REG VXI and VME BASE 04 Read A read of this 16 bit register provides information about the card s as defined below nn 424 432 ENABLE ndicates the state of the RE ndicates the state of the SYSFAIL INHIBIT bit in the IL Dr IT Control Register ed it s self test A 1 indicates that the self test successfully completed 2 PasseD a 0 indicates that the
106. t e e il ARINC Channels Rcv Look up H TABLE POINTER 60 LOOK UP TABLE RECEIVE STATUS CONTROL WORD RD WR r_ CONTROL BYTE r STATUS BYTE _ L WORD RECEIVED L LO BIT CT INVLD WD ERR L HI BIT COUNT ERROR ll PARITY ERROR ___________ INVALID CODING ERROR GAP SYNC TIME T RROR Pe reserved VALID WORD Lo reserved Lo reserved Preserved Preserved Preserved Preserved LP reserved bP ENABLE LABEL INTERRUPT ARINC Channels LOOK UP TABLE RECEI lt E STATUS CONTROL WORD A ee 00 word A logic 1 This bit is set when the status word is Received written into memory 01 Hi Bit Ct Indicates that a Hi bit count error was detected in Error the ARINC word 02 Lo Bit Ct Indicates that a Lo bit count error or a Null bit Invalid Wd error was detected in the ARINC word 03 Parity Indicates that a parity error was detected in the Error ARINC word 04 Invalid Indicates that a bit level decoding error was Coding Err detected in the ARINC word 05 Gap Sync Indicates that a Gap Sync Time error occurred Time Error between words less than 4 bit times be
107. the channel is stopped CHANNEL x RCV BUFFER WRAPAROUND REGISTER WR This register contains 2 bits for synchronization with the C drivers If bit 14 is set to 1 the receive buffer has wrapped around once since the last data read If bit 15 is set to 1 there have been multiple wraparounds CHANNEL x RCV DATA BYTE COUNTER TRIGGER REGISTER WR This register allows the user to generate an interrupt and set a flag when a certain number of bytes have been received 1 64k The appropriate bit must also be set in the Channel x Interrupt Trigger Condition Register CHANNEL x RCV INTERVAL COUNTER TRIGGER REGISTER WR This register allows the user to generate an interrupt and set a flag upon reception of every N number of bytes The appropriate bit must also be set in RS Channels 111 the Channel x Interrupt Trigger Condition Register 112 CHANNEL x RCV ERROR COUNT REGISTER RD This 16 bit counter indicates the number of errors received on a particular channel This register wraps around The user can reset this register by writing 0 to it even while the channel is running CHANNEL x RCV START BYTE TRIGGER REGISTER WR This register is used in conjunction with the Receiver Byte Trigger bit within the Configuration Register
108. to enable the reception and storage of data upon receipt of a specific byte 00 TRIGGER BYTE 15 8 7 0 CHANNEL x TX INSTRUCTION STACK POINTER WR Sets the starting address of the TX Instruction Stack The address must be even CHANNEL x TX INSTRUCTION COUNTER WR Sets the number of TX Instruction blocks to process CHANNEL x TX LOOP COUNTER WR Sets the number of times to execute the TX instruction blocks N Times or Continuous Loop If the continuous value is selected the channel s operation can be terminated by setting the related channel bit within the Global Start Register to a 0 or its Start Transmit Register to 0 Value 0000 CONTINUOUS 0001 One Time 0002 Two Times FFFF 65535 Times RS Channels 113 CHANNEL NT ERRUPT TRI GG ER CONDI TION RE STE Sets the interrupt condition bits while bits 08 15 relat The trigger conditions set a pulse on the trigger or the VXI Interrupt and Trigger condition s o if TRIGO TTL TR GG ER output signal Ki ii a i 1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 EEE ___ 100q 0 1l _ _ 1 be l l_ r r r r r oooooe orrori Notes
109. transmitters with an opportunity to safely transmit data This includes the Interblock Time and the time between frames If there are gaps between bytes within a block which can happen at high baud rates the transmitter does not enter tristate The transmitter goes into tristate immediately after the last stop bit of the last byte of a block has been transmitted and remains tristated until the beginning of the transmission of the start bit of the next byte RS Channels 123 TX DATA BLOCK FORMAT The figure below illustrates the format of the TX data bytes within the memory Ir E DATA BYTE 3 4th DATA BYTE 2 3rd DATA BYTE 1 2nd DATA BYTE 0 lst byte location in TX data area RS Channels 124 z T BAUD RATE LIMITATIONS of the MAGICard for There are configurations there will b interbyt gaps in transmission received data There are two modes of operation RS 232 422 485 423 Channel Operation Mode which the RS 232 422 485 423 channels must be less than the maximum of 250 Kbaud If and a possibility see the description of the Register baud rate of the not of losing In regular mode each received byte may be stored with status and time tag relatively low fast mode rates are acceptable equations are meant to be a guide to allow the user to may be used without data los
110. ts 2 stop transmitted or received with each character 0 one stop bit is used 1 two stop bits are used for lengths 6 7 and 8 1 5 stop bits are used if 5 bit chars were chosen 3 Parity 1 Parity 0 No Parity Even Odd Even parity 0 Odd parity if bit 3 is 1 5 stick If bits 3 4 and 5 are all 1 the parity bit will Parity always be set to zero If 3 and 5 are 1 and 4 is zero the parity bit will always be 1 If bit 5 is zero regular Even and Odd parity will be used 6 H w 1 Transmit only when CTS is high set DTR hi if Protocol in danger of overrun 0 Ignore CTS and DTR 7 Loopback 1 Channel receives even during transmission RS 485 0 Channel receives at all times except during only transmission when receive is enabled 8 Receiver 1 Data storage is halted when buffer full wrap 0 Receiver wraps around data within the block Around 9 Receiver 1 Start data storage upon receipt of Byte xx Byte 0 Receiver stores data without Start Byte Trigger Note Receiver Byte Trigger See description of the RCV Start Byte Trigger Register 2 If H W protocol is enabled for RS 232 there will be an interbyte delay of at least 1 bit time RS Channels 108 CHANNEL BAUD RATE
111. ts all receiver Channels see Receiver Data Storage Mod Register in the Global Register section of this manual A 16 bit Error Count register indicates the number of invalid words received Interrupts and pollable status registers allow for numerous event recognition and are described in the Channel Register section of this manual The Sequential Storage Mode is the only storage mode supported by Williamsburg channels Received Williamsburg words which are responses to transmissions are stored sequentially with received data in order of arrival If a received LDU must be repeated due to an error the defective LDU will not be overwritten but rather the retransmitted LDU will be stored after the defective version ARINC Channels 47 48 LOOK UP TABLE MODE In the Look up table mode the word s LABEL is used by the board as an offset to a 256 word look up table The table is programmed by the user with address pointers as to where to write the Receiver Data Block Each block contains the 32 bit ARINC word 32 bit Time Tag an error count and status word The 256 word table can be placed anywhere within the memory via a user programmable Receiver Look up Table Pointer The user has the ability to monitor the operational status of each channel and to be interrupted on various events In addition there exist pollable registers which can be use
112. tween words for ARINC 429 575 582 2wire channels and less than 1 bit time between words for ARINC 561 568 582 6wire channels reserved SET TO ON 07 valia Word Global Bit Indicates that the received ARINC word was valid in all respects 08 reserved SET TO MOT reserved reserved reserved reserved reserved reserved 15 Enable Enables the interrupt on Label received capability Label Int This bit is used in conjunction with the Interrupt Trigger Condition Register ARINC Channels 62 TRANSMITTER OPERATION NON WILLIAMSBURG CHANNELS The method implemented in the transmit mode requires the user to create an instruction stack for the transmitter channel write the data into the Dual Port RAM and start transmission by writing to the Start Register found within the Global Register area The sequence of writes to memory is not important except for the write to the Global Start Register which is performed last TRANSMIT INSTRUCTION STACK The Transmit Instruction Stack is divided into Instruction Blocks each containing 4 words Fach Instruction Block relates to a Data Buffer A Data Buffer contains one or more ARINC words which the user desires to transmit with the same amount of delay time between each word The stack is sequential so that
113. up tabl a 256 word look up table pointers as to where to writ 32 bit ARI NC word e mode The table the word s LAI BEL is used by the board as an offset to is programmed by the user with address th Receiver Data 32 bit Time Tag an error count Block Bach block contains the and status word The 256 word table can be placed anywhere within the memory via a user programmable Receiver Look up Table Pointer The user has the ability to monitor the operational status of each channel and to be interrupted on various events In addition there exist pollable registers which can be used with or instead of interrupt processing ARI NC LA na 256 X 16 BLE PER CHANN TAI ADDRI ESS POI NTER ESS POI NT gt ADDRESS POINTER A e ADDRESS POINTE 59 lt E STATUS CNTL WORD ERROR COUNT u aa ME TAG LO N TIME TAG HI aa ERE DATA WOR az DATA WOR D LO D HI l HA DATA ARI EA E Do A el EIV E STATUS CNTL WORD ERROR COUNT ER TIME TAG LO SN TIME TAG HI Po DATA WOR DATA WOR D LO D HI il _ _ i
114. x operation a channel will only accept incoming data if it is between transmission of consecutive blocks or has no blocks to transmit If a channel receives data in the Williamsburg format while waiting between blocks it will not initiate transmission of the next block until it has completed reception of the incoming block and has responded to it This can result in larger than expected intermessage gaps If an RTS word is received after transmission of an RTS i e a race condition exists between 2 channels the channel waits before acting The wait varies randomly between 62 5 ms and 500 ms in steps of 62 5 ms If during this period an RTS is received it is handled normally and transmission of the pending transmit block is put off until the incoming LDU is processed Otherwise the RTS is retransmitted This process is repeated until the conflict is resolved Notes 1 An incoming ALO word will be accepted and handled properly at any time even in half duplex mode during transmission of a block 2 During the interblock delay after a non LDU block only the Williamsburg channel will not send responses This is true in both full and half duplex mode ARINC Channels 83 II TRANSMIT There are different types of blocks of data to be transmitted each of which is handled as descibed below GI BLOCKS NOT REQUIRING RESPONSI A block consistin

EXC-3000VME-VXI MAGICard: User`s Manual, Rev C

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