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CYV15G0404DXB Independent Clock Quad HOTLink II - Digi-Key

1. Monitor INA1 E a o i Nai 5 5 Sb 85 E 78 gt RXDA 7 0 INA2 amp E om Sm 2 ata 50 TXLBA gt Recovery 2 ka AA ULER gt PLL x e RXSTA 2 0 SPDSELB RXPLLPDB Clock E gt Me RXCLKA RCLKENB gt Select 2 p Receive INSELB Signal Monitor gt INB1 o0 NBI 25 RXDBI7 0 INB2 Bea Clock amp h INB2 Data 6 TXLBB gt Recovery c RXSTB 2 0 ULCB P PLL d SPDSELC RXPLLPDC 22 lt RXCLKB E Select RXCLKB LPENGC p Receive Signal p gt Monitor gt eae 8 55 5 D m O0 um 5 RXDC 7 0 188 359 N 58 INC2 Clock amp S Be 2 Data A A 62 3 TXLBC gt Recovery x RXSTC 2 0 ULCC gt PLL A SPDSELD RXPLLPDD Clock h RXCLKC RCLKEND gt gt
2. Transmit Path Block Diagram RECLCK A D are Internal Reclocker Signals REFCLKA TXLB A D are Internal Serial Loopback Signals gt Bit Rate Clock REFCLKA Transmit PuL Internal Signal lt 2 1 THRE L Glock Multiplier A EM SPDSELA TXCLKOA lt a Character Rate Clock A r RECLCKA TXERRA q TXCLKA PABRSTA TXBISTA 0 1 TXCKSELA gt V V Y 8 _ S 5 t V P gt OUTA1 TXDAT 758 9 251 ol OUTAT oz o 5 A9 R OUTA2 1 0 gla o E gt g gm cO LL o OUTA2 REFCLKB gt TXLBA REC cess Bit Rate Clock IDCM ransmit TXRATEB Clock Multiplier OEB 2 1 SPDSELB gt TXCLKOB lt lt Character Rate Clock RECLCKB TXERRB TXCLKB PABRSTB TXBISTB OEB 2 1 l TXCKSELB V V Y V _ Fa gt 2 10 2 5 10 m o 10 10 gt 1 OUTBI TXDB 7 0 22 F 2 co 9 m 5 OUTB2 574 c o gt OUTB2 a lt TXLBB REFCLKC REFCLKC Eee Transmit PLL ae TXRATEC P Kb OEC 2 1 SPDSELC gt TXCLKOC Character Rate Clock C Senne
3. _ m EP CYPRESS CYV15G0404DXB PERFORM Table 14 Valid Data Characters TXCTx 0 0 RXSTx 2 0 000 continued D Bits Current RD Current RD Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj Name EDCBA abcdei fghj abcdei fghj D0 2 010 00000 100111 0101 011000 0101 D0 3 011 00000 100111 0011 011000 1100 D1 2 010 00001 011101 0101 100010 0101 D1 3 011 00001 011101 0011 100010 1100 D2 2 010 00010 101101 0101 010010 0101 D2 3 011 00010 101101 0011 010010 1100 03 2 010 00011 0001 0101 110001 0101 03 3 011 00011 0001 100 110001 0011 D4 2 010 00100 0101 0101 001010 0101 24 3 011 00100 0101 0011 001010 1100 95 2 010 00101 101001 0101 101001 0101 D5 3 011 00101 101001 1100 101001 0011 D6 2 010 00110 011001 0101 011001 0101 D6 3 011 00110 011001 1100 011001 0011 2 010 00111 11000 0101 000111 0101 07 3 011 00111 11000 1100 000111 0011 28 2 010 01000 11001 0101 000110 0101 28 3 011 01000 11001 0011 000110 1100 29 2 010 01001 100101 0101 100101 0101 D9 3 011 01001 100101 1100 100101 0011 D10 2 010 01010 010101 0101 010101 0101 D10 3 011 01010 010101 1100 010101 0011 D11 2 010 01011 0100 0101 110100 0101 D11 3 011 01011 0100 1100 110100 0011 D12 2 010 01100 001101 0101 001101 0101 D12 3 011 01100 001101 1100 001101 0011 1 3 2 010 01101 101100 0101 101100 0101 13 3 011 01101 101100 1100 101100 001
4. Parameter Description Min Max Unit trig CML Output Rise Time 20 80 CML Test Load SPDSELx HIGH 60 270 ps SPDSELx MID 100 500 ps SPDSELx LOW 180 1000 ps tea 221 CML Output Fall Time 80 20 CML Test Load SPDSELx HIGH 60 270 ps SPDSELx MID 100 500 ps SPDSELx LOW 180 1000 ps 202931 Deterministic Jitter peak pea IEEE80232 27 7520 30 31 Random Jitter 82 IEEE 802 3z 11 ps ieee REFCLKx jitter tolerance Phase noise limits TBD trxLock Transmit PLLx lock to REFCLKx 200 us CYV15G0404DXB Receive Serial Inputs and CDR PLL Characteristics Over the Operating Range tRxLOCK Receive PLL lock to input data stream cold start 376k UI Receive PLL lock to input data stream 376k Ul tRXUNLOCK Receive PLL Unlock Rate 46 Ul Total Jitter 2 IEEE 802 3z 600 ps 221 Deterministic Jitter Tolerance IEEE 802 3z 370 ps Capacitance Parameter Description Test Conditions Max Unit CINTTL TTL Input Capacitance 25 fo 1 MHz Voc 3 3V 7 pF CiNPECL PECL input Capacitance 25 fo 1 MHz Voc 3 3V 4 pF CYV15G0404DXB HOTLink II Transmitter Switching Waveforms trXCLK Transmit Interface Write Timing TXCLKx selected TXCLKx TXDx 7 0 TXCT x 1 0 XX Transmit Interface Write Timing t REFCLKx selected ia TENE TXRATEx 0 RE
5. Signals internal pull up WREN LVTTL input Control Write Enable The WREN input writes the values of the DATA 7 0 bus into asynchronous the latch specified by the address location on the ADDR 3 0 internal pull up ADDR 3 0 LVTTL input Control Addressing Bus The ADDR S3 0 bus is the input address bus used to asynchronous configure the device The WREN input writes the values of the DATA 7 0 bus into the internal pull up latch specified by the address location on the ADDR 3 0 bus Table 9 lists the configuration latches within the device and the initialization value of the latches upon the assertion of RESET Table 10 shows how the latches are mapped in the device DATA 7 0 LVTTL input Control Data Bus The DATA 7 0 bus is the input data bus used to configure the asynchronous device The WREN input writes the values of the DATA 7 0 bus into the latch specified by address location on the ADDR 3 0 Table 9 lists the configuration latches within the device and the initialization value of the latches upon the assertion of RESET Table 10 shows how the latches are mapped in the device Internal Device Configuration Latches RFMODE A D 1 0 Internal Latchf8 Reframe Mode Select FRAMCHAR A D Internal Framing Character Select DECMODE A D Internal Latchf8 Receiver Decoder Mode Select DECBYPJ A D Internal Latchle Receiver Decoder Bypass
6. RXCLKx Rise Time 0 3 1 2 ns tRxCLKF 20 Fall Time 0 3 1 2 ns Status and Data Valid Time to RXCLKx 0 RXCKSELx 0 50 2027 ms Full Rate Status and Data Valid Time to RXCLKx RXRATEx 1 RXCKSELx 0 5UI 1 3 241 ns Half Rate 1 Status and Data Valid Time to RXCLKx RXRATEx 0 RXCKSELx 0 5UI 1 8 241 5 Full Rate Status and Data Valid Time to RXCLKx RXRATEx 1 RXCKSELx 0 5UI 2 6 241 ns Half Rate CYV15G0404DXB REFCLKx Switching Characteristics Over the Operating Range fREF REFCLKx Clock Frequency 19 5 150 MHz tREFCLK REFCLKx Period 1 fper 6 6 51 28 ns tREFH REFCLKx HIGH Time TXRATEx 1 Half Rate 5 9 ns REFCLKx HIGH Time TXRATEx 0 Full Rate 2 91201 ns tREFL REFCLKx LOW Time TXRATEx 1 Half Rate 5 9 ns REFCLKx LOW Time TXRATEx 0 Full Rate 2 9170 ns IREFD A REFCLKx Duty Cycle 30 70 2227 22 REFCLKx Rise Time 20 80 2 ns 227 227 REFCLKx Fall Time 20 80 2 ns Notes 20 Tested initially and after any design or process changes that may affect these parameters but not 100 tested 21 The ratio of rise time to falling time must not vary by greater than 2 1 22 For a given operating frequency neither rise or fall specification can be greater than 20 of the clock cycle period or the data sheet maximum time 53 Unit OO hen TXBATEX
7. Signal A01 CML IN C07 ULCC LVTTL IN PU F17 RCLKENA LVTTL IN PD A02 OUTC1 CML OUT C08 GND GROUND F18 RXSTB 1 LVTTL OUT A03 2 CML IN 09 DATA 7 LVTTL IN PU 19 TXCLKOB LVTTL OUT A04 OUTC2 CML OUT C10 DATA 5 LVTTL IN PU F20 RXSTB O LVTTL OUT 05 VCC POWER C11 DATA 3 LVTTL IN PU G01 TXDC 7 LVTTL IN A06 IND1 CML IN C12 DATA 1 LVTTL IN PU G02 WREN LVTTL IN PU A07 OUTD1 CML OUT C13 GND GROUND G03 TXDC 4 LVTTL IN 08 GND GROUND C14 RCLKENB LVTTL IN PD G04 TXDC 1 LVTTL IN 09 2 CML IN C15 SPDSELD 3 LEVEL SEL G17 SPDSELB 3 LEVEL SEL A10 OUTD2 CML OUT C16 G18 LPENC LVTTL IN PD 11 1 CML IN C17 LDTDEN LVTTL IN PU G19 SPDSELA 3 LEVEL SEL 12 OUTA1 CML OUT C18 TRST LVTTL IN PU G20 RXDB 1 LVTTL OUT A13 GND GROUND C19 LPEND LVTTL IN PD H01 GND GROUND A14 2 CML IN C20 TDO LVTTL 3 5 OUT H02 GND GROUND A15 OUTA2 CML OUT 001 LVTTL IN PD H03 GND GROUND A16 VCC POWER 002 LVTTL IN PU 04 GND GROUND 17 1 CML IN 003 INSELD LVTTL IN H17 GND GROUND A18 OUTB1 CML OUT 004 INSELA LVTTL IN H18 GND GROUND 19 2 CML IN 005 VCC POWER H19 GND GROUND A20 OUTB2 CML OUT 006 ULCA LVTTL IN PU H20 GND GROUND 01 INC1 CML IN 007 SPDSELC 3 LEVEL SEL J01 TXCTO 1 LVTTL IN 2 OUTC1 CML OUT 008 GND GROUND 402 TXDC 5 LVTTL IN B03 INC2 CML IN D09 DATA 6 LVTTL IN PU J03 TXDO 2 LVTTL IN 804 OUTC2 CML OUT D10 DATA 4 LVTTL IN PU J04 T
8. TX Rx TX TX Veg TX REF RX DD 6 CLKD CLKD DD 5 000 CLKOD CLKA CLKA DA O DAIS ERRD 6 DAIS Document 38 02097 Rev B Page 6 of 44 Feedback CYPRESS PERFORM CYV15G0404DXB Pin Configuration Bottom View UJ Y Note 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OUT IN OUT IN OUT IN GND OUT N OUT OUT IN Veg OUT N OUT IN B2 B2 Bi 1 A2 A2 Alt At D2 D2 Di D1 C2 1 1 OUT IN OUT IN OUT IN GND OUT N OUT N GND OUT IN vcc OUT N OUT IN B2 B2 Bi Bi A2 A2 1 1 D2 D2 01 01 C2 2 TDO LP TRST LDTD Vog SPD RCLK GND DATA DATA DATA DATA GND ULCC ULCD vog N Ts TDI END EN SELD ENB 1 3 5 7 SELB SELC TMEN3 SCAN vcc LP ULCB LP GND DATA DATA DATA DATA GND SPD ULCA vog N RESET TCLK EN2 ENA ENB 0 2 4 6 SELC SELA SELD Voc Voc Voc Voc Voc Voc RX TX RCLK RCLK TX RX Rx STB 0 CLKOB STB 1 END DC 0 DC 7 DC
9. 10 8 6 4 gt 8 7 5 3 ii cooo Nooo 4X 0000 L cooo _ 0 0 SO OoOo 000000 24 13 600 0Q0 0000000 00000000 KS 1 2 0 50 0 20 mE TOP OF SECIION MOLD COMPOUND OF BALLS 51 85123 Page 43 of 44 Feedback I Ed CYPRESS CYV15G0404DXB PERFORM Document History Page Document Title CYV15G0404DXB Independent Clock Quad HOTLink II Transceiver with Reclocker Document Number 38 02097 ISSUE ORIG OF REV ECN NO DATE CHANGE DESCRIPTION OF CHANGE 231494 BCD New Data Sheet 384307 Revised setup and hold times RXDv tRxDv REFxDV 85 tRIS
10. RX TX TX RX RX RX RX TX DA 5 DA 6 CLKA DA 5 DA O CLKA CLKA CLKOD DD 0 205 CLKD DD 7 CLKD 1 NC Do Not Connect Document 38 02097 Rev Page 7 of 44 Feedback Pin Defi nitions CYV15G0404DXB Quad HOTLink Il Transceiver LVTTL Input Characteristics Signal Description command character sent Transmit Data Inputs TXDx 7 0 data inputs are captured on the rising edge of the latch via the device configuration interface and passed to the encoder or Transmit transmit interface clock The transmit interface clock is selected by the TXCKSELx Shifter When the Encoder is enabled TXDx 7 0 specifies the specific data or CYV15G0404DXB Name synchronous Transmit Path Data and Status Signals sampled by the associated Transmit Control TXCTx 1 0 inputs are captured on the rising edge of the transmit interface clock The transmit interface clock is selected by the TXCKSELx latch TXDA 7 0 TXCLKx REFCLKxTE2I LVTTL Input synchronous sampled by the associated through the device configuration interface and passed to the encoder or transmit shifter The TXCTA 1 0 inputs identify how the associated TXDx 7 0 characters are interpreted When the encoder is bypassed these inputs are interpreted as data bits When the encoder is enabled these inputs determine if the TXDx 7 0 charact
11. Select E RXCLKC LPEND P Receive INSELD gt Signal p gt LFID IND1 Z Monitor my EN IND1 5 5 EI 5 78 gt RXDD 7 0 IND2 om OM an gt Clock amp EE i IND2 Data o gt AA TXLBD P _ RXSTD 2 0 ULCD pe PLL A DASEL A D 1 0 LDTDEN gt 2 lt RXCLKD Select RXCLKD RFMODE A D 1 0 gt gt RFEN A D gt FRAMCHAR A D T DECMODEB A D RXBISTA D J RXCKSEL A D DECBYP A D RXRATE A D gt Document 38 02097 Rev Page 4 of 44 Feedback CYV15G0404DXB gt Internal Signal a lt CYPRESS PERFORM Device Configuration and Control Block L RFMODEJA D 1 0 0 ILI gt FRAMCHAR A D WREN T Dece on a a DECMODE A D ADDR 3 in He gt RXBISTIA D ion and Control 4 gt gt RXCKSEL A D gt DECBYP A D SS eee gt RXRATE A D SDASEL A D 1 0 gt RXPLLPD A D eee J gt TXRATE A D 4 gt TXCKSEL A D PABRSTIA D 4 gt TXBISTI A D gt OE A D 2 1 e e ENCBYP A D GLEN 11
12. m A S RFMODEA 1 RFMODEA 0 FRAMCHARA DECMODEA DECBYPA RXCKSELA GLENO 10111111 m iB A S SDASEL2A 1 SDASEL2A 0 SDASEL1A 1 SDASEL1A 0 ENCBYPA TXCKSELA TXRATEA GLEN1 10101101 m A D RFENA RXPLLPDA RXBISTA TXBISTA OE2A OE1A PABRSTA GLEN2 10110011 S RFMODEB 1 RFMODEB 0 FRAMCHARB DECMODEB DECBYPB RXCKSELB GLEN3 10111111 m B SDASEL2B 1 SDASEL2B 0 SDASEL1B 1 SDASEL1B 0 ENCBYPB TXCKSELB TXRATEB GLEN4 10101101 B D RFENB RXPLLPDB RXBISTB TXBISTB OE2B OE1B PABRSTB GLENS 10110011 Ea C RFMODEC 1 RFMODEC 0 FRAMCHARC DECMODEC DECBYPC RXCKSELC RXRATEC GLEN6 10111111 rm C S SDASEL2C 1 SDASEL2C 0 SDASEL1C 1 SDASEL1C 0 ENCBYPC TXCKSELC TXRATEC GLEN7 10101101 m C D RFENC RXPLLPDC RXBISTC TXBISTC OE2C OE1C PABRSTC GLEN8 10110011 T D S RFMODED 1 RFMODED 0 FRAMCHARD DECMODED DECBYPD RXCKSELD RXRATED GLEN9 10111111 7 D S SDASEL2D 1 SDASEL2D 0 SDASEL1D 1 SDASEL1D 0 ENCBYPD TXCKSELD TXRATED GLEN10 10101101 TUN D D RFEND RXPLLPDD RXBISTD TXBISTD OE2D OE1D PABRSTD GLEN11 10110011 12 GLOBAL RFMODEGL 1 RFMODE FRAMCHARGL DECMODEGL DECBYPGL RXCKSELGL RXRATEG FGLENO N A 1100b GLIO L E GLOBAL S SDASEL2GL 1 SDASEL1GL 1 SHAS ENCBPGL TXCKSELGL TXRATEG FGLEN1 N A GLOBAL D RFENGL RXPLLPDGL RXBISTGL TXBISTGL
13. OY 0 In operating link this is equivalent to 25 re ee iS a simultaneous condition with the and tper parameters This means that at faster character rates the REFCLKx duty cycle Document 38 02097 Rev B Page 28 of 44 Feedback CYPRESS CYV15G0404DXB PERFORM CYV15G0404DXB AC Electrical Characteristics continued Parameter Description Min Max Unit trREFDS Transmit Data Set up Time to REFCLKx Full Rate 2 4 ns 0 TXCKSELx 1 Transmit Data Set up Time to REFCLKx Half Rate 2 3 ns TXRATEx 1 TXCKSELx 1 trREFDH Transmit Data Hold Time from REFCLKx Full Rate 1 0 ns TXRATEx 2 0 TXCKSELx 1 Transmit Data Hold Time from REFCLKx Half Rate 1 6 ns TXRATEx 1 TXCKSELx 1 tRREFDA Receive Data Access Time to REFCLKx RXCKSELx 1 9 7175 ns Receive Data Valid Time Window RXCKSELx 1 1001 5 8 ns tREFxDV_ Received Data Valid Time to when RXCKSELx 1 10024 6 16 ns TXRATEx 0 RXRATEx 0 Received Data Valid Time to when RXCKSELx 1 5UI 2 53127 ns TXRATEx 0 RXRATEx 1 Received Data Valid Time to RXCLK when RXCKSELx 1 TXRATEX 1 10UI 5 86771 ns REFxDV Received Data Valid Time from RXCLK when RXCKSELx 1 1 4 ns TXRATEx 0 RXRATEx 0 Received Data Valid Time from RXCLK when RXCKSELx 1
14. M NJ CYPRESS Features m Quad channel transceiver for 195 to 1500 MBaud serial signaling rate Aggregate throughput of up to 12 Gbits second m Second generation HOTLink technology m Compliant to multiple standards SMPTE 292M SMPTE 259M DVB ASI Fibre Channel ES and Gigabit Ethernet IEEE802 3z 10 bit uncoded data or 8B 10B coded data Truly independent channels Each channel is able to Perform reclocker function Operate at a different signaling rate Transport a different data format m Internal phase locked loops PLLs with no external PLL components m Selectable differential PECL compatible serial inputs per channel Internal DC restoration Redundant differential PECL compatible serial outputs per channel No external bias resistors required Signaling rate controlled edge rates Source matched for 500 transmission lines MultiFrame Receive Framer provides alignment options Comma or full K28 5 detect Single or multibyte Framer for byte alignment Low latency option m Selectable input and output clocking options CYV15G0404DXB Independent Clock Quad HOTLink IITM Transceiver with Reclocker m Synchronous LVTTL parallel interface m JTAG boundary scan m Built In Self Test BIST for at speed link testing m Link quality indicator by channel Analog signal detect Digital signal detect m Low power 3W at 3 3V typical m Single 3 3V supply
15. m 256 ball thermally enhanced BGA m 0 25 BICMOS technology m JTAG device ID 0C811069 x Functional Description The CYV15G0404DXB Independent Clock Quad HOTLink Transceiver is a point to point or point to multipoint communica tions building block enabling the transfer of data over a variety of high speed serial links including SMPTE 292 SMPTE 259 and DVB ASI video applications The signaling rate can be anywhere in the range of 195 to 1500 MBaud for each serial link Each channel operates independently with its own reference clock allowing different rates Each transmit channel accepts parallel characters in an input register encodes each character for transport and then converts it to serial data Each receive channel accepts serial data and converts it to parallel data decodes the data into characters and presents these characters to an output register The received serial data can also be reclocked and retransmitted through the serial outputs Figure 1 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404DXB chips Figure 1 HOTLink II System Connections 10 lt 10 Reclocker 10 T 8 09 9 510 58 Video Coprocessor 10 Serial Links gt q Independent lt Serial Links e Channel gt annel 10 CYV15G0404DXB CYV15G0404DXB 5 Rec
16. Max 1350 Input LOW Current Vin Vite Min 700 7 Common Mode input range Vcc 2 0V 0 5 min 1 25 3 1 V Voc 0 5V max Power Supply Typ Max log 1977 Max Power Supply Current REFCLKx Commercial 910 1270 mA MAA Industrial 1320 mA loc re Typical Power Supply Current REFCLKx Commercial 900 1270 mA 125 MHz Industrial 1320 mA AC Test Loads and Waveforms 3 3V R1 RI 1000 RL R1 5900 4350 Includes fixture and lt 7 pF i fixture and 18 CML Output Test Load probe capacitance LVTTL Output Test Load 3 0V c LVTTL Input Test Wavetorm d CML LVPECL Input Test Waveform Notes 15 The common mode range defines the allowable range of INPUT and INPUT when INPUT INPUT This marks the zero crossing between the true and complement inputs as the signal switches between a logic 1 and a logic 0 16 Maximum ICC is measured with VCC MAX RFENx 0 TA 25 C with all channels and Serial Line Drivers enabled sending a continuous alternating 01 pattern and outputs unloaded 17 Typical ICC is measured under similar conditions except with VCC 3 3V TA 25 C RFENx 0 with all channels enabled and one Serial Line Driver per transmit channel sending a continuous alternating 01 pattern The redundant outputs on each channel are powered down and the parallel outputs are unloaded 18 Cypress uses constant curre
17. Running disparity at the end of the transmission character is the running disparity at the end of the 4 bit subblock Running disparity for the subblocks is calculated as follows 1 Running disparity at the end of any subblock is positive if the subblock contains more ones than zeros It is also positive at the end of the 6 bit subblock if the 6 bit subblock is 000111 and it is positive at the end of the 4 bit subblock if the 4 bit subblock is 0011 2 Running disparity at the end of any subblock is negative if the subblock contains more zeros than ones It is also negative at the end of the 6 bit subblock if the 6 bit subblock is 111000 and it is negative at the end of the 4 bit subblock if the 4 bit subblock is 1100 3 Otherwise running disparity at the end of the subblock is the same as at the beginning of the subblock Use of the Tables for Generating Transmission Characters The appropriate entry in Table 14 for the valid data byte or Table 15 for Special Character byte identify which transmission character is generated The current value of the transmitter s running disparity is used to select the transmission character from its corresponding column For each transmission character Table 13 Code Violations Resulting from Prior Errors CYV15G0404DXB transmitted a new value of the running disparity is calculated This new value is used as the transmitter s current running disparity for the next valid data byte or Special
18. When OE2x 1 the OE2C associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter When OE2D OE2x 0 the associated serial data output driver is disabled When a driver is disabled via the configuration interface it is internally powered down to reduce device power If both serial drivers for a channel are in this disabled state the associated internal logic for that channel is also powered down A device reset RESET sampled LOW disables all output drivers OE1A Primary Differential Serial Data Output Driver Enable The initialization value of the OE1x latch 2 0 OE1x OE1B selects if the OUT1 primary differential output drivers are enabled or disabled When OE1x 1 the associated OE1C serial data output driver is enabled allowing data to be transmitted from the transmit shifter When OE1x 0 OE1D the associated serial data output driver is disabled When a driver is disabled via the configuration interface it is internally powered down to reduce device power If both serial drivers for a channel are in this disabled state the associated internal logic for that channel is also powered down A device reset RESET sampled LOW disables all output drivers PABRSTA Transmit Clock Phase Alignment Buffer Reset The initialization value of the PABRSTx latch 1 The PABRSTB PABRSTx is used to re center the Transmit Phase Align Buffer When the configuration latch PABRSTx is PABRSTC written as a 0 the phase
19. 001 00010 101101 1001 010010 1001 23 0 000 00011 0001 1011 110001 0100 23 1 001 00011 0001 1001 110001 1001 24 0 000 00100 0101 0100 001010 1011 24 1 001 00100 0101 1001 001010 1001 05 0 000 00101 101001 1011 101001 0100 05 1 001 00101 101001 1001 101001 1001 26 0 000 00110 011001 1011 011001 0100 06 1 001 00110 011001 1001 011001 1001 27 0 000 00111 11000 1011 000111 0100 27 1 001 00111 11000 1001 000111 1001 28 0 000 01000 11001 0100 000110 1011 08 1 001 01000 11001 1001 000110 1001 29 0 000 01001 100101 1011 100101 0100 29 1 001 01001 100101 1001 100101 1001 210 0 000 01010 010101 1011 010101 0100 210 1 001 01010 010101 1001 010101 1001 211 0 000 01011 0100 1011 110100 0100 211 1 001 01011 0100 1001 110100 1001 212 0 000 01100 001101 1011 001101 0100 212 1 001 01100 001101 1001 001101 1001 213 0 000 01101 101100 1011 101100 0100 213 1 001 01101 101100 1001 101100 1001 214 0 000 01110 0 00 1011 011100 0100 214 1 001 01110 011100 1001 011100 1001 215 0 000 01111 010111 0100 101000 1011 215 1 001 01111 010 1001 101000 1001 216 0 000 10000 0110 0100 100100 1011 216 1 001 10000 0110 1001 100100 1001 217 0 000 10001 100011 1011 100011 0100 217 1 001 10001 100011 1001 100011 1001 218 0 000 10010 010011 1011 010011 0100 218 1 001 10010 010011 1001 010011 1001 219 0 000 10011 110010 1011 110010 0100 219 1 001 10
20. 0010 012 5 101 01100 001101 1010 001101 1010 013 4 100 01101 101100 1101 101100 0010 013 5 101 01101 101100 1010 101100 1010 014 4 100 01110 011100 1101 011100 0010 014 5 101 01110 011100 1010 011100 1010 015 4 100 01111 010111 0010 101000 1101 015 5 101 01111 010111 1010 101000 1010 016 4 100 10000 011011 0010 100100 1101 016 5 101 10000 011011 1010 100100 1010 017 4 100 10001 100011 1101 100011 0010 017 5 101 10001 100011 1010 100011 1010 018 4 100 10010 010011 1101 010011 0010 018 5 101 10010 010011 1010 010011 1010 019 4 100 10011 110010 1101 110010 0010 019 5 101 10011 110010 1010 110010 1010 020 4 100 10100 001011 1101 001011 0010 020 5 101 10100 001011 1010 001011 1010 021 4 100 10101 101010 1101 101010 0010 221 5 101 10101 101010 1010 101010 1010 022 4 100 10110 011010 1101 011010 0010 022 5 101 10110 011010 1010 011010 1010 223 4 100 10111 111010 0010 000101 1101 023 5 101 10111 111010 1010 000101 1010 224 4 100 11000 110011 0010 001100 1101 024 5 101 11000 110011 1010 001100 1010 025 4 100 11001 100110 1101 100110 0010 025 5 101 11001 100110 1010 100110 1010 026 4 100 11010 010110 1101 010110 0010 026 5 101 11010 010110 1010 010110 1010 227 4 100 11011 110110 0010 001001 1101 027 5 101 11011 110110 1010 001001 1010 028 4 100 11100 001110 1101 001110 0010 028 5 101 11100 001110 1010 001110 1010 029 4 100 11101 101110 0010 010001 1101 029 5 101
21. 11101 101110 1010 010001 1010 030 4 100 11110 011110 0010 100001 1101 230 5 101 11110 011110 1010 100001 1010 231 4 100 11111 101011 0010 010100 1101 D31 5 101 11111 101011 1010 010100 1010 Document 38 02097 Rev Page 40 of 44 Feedback Cypress CYV15G0404DXB Table 14 Valid Data Characters TXCTx 0 0 RXSTx 2 0 000 continued Bits Current RD Current RD Bits Current RD Current RD y Name HGF EDCBA abcdei fghj abcdei fghj Name HGF EDCBA abcdei fghj abcdei fghj D0 6 110 00000 100111 0110 011000 0110 0 7 111 00000 100111 0001 011000 1110 21 6 110 00001 011101 0110 100010 0110 21 7 111 00001 011101 0001 100010 1110 22 6 110 00010 101101 0110 010010 0110 22 7 111 00010 101101 0001 010010 1110 23 6 110 00011 110001 0110 110001 0110 23 7 111 00011 110001 1110 110001 0001 24 6 110 00100 110101 0110 001010 0110 24 7 111 00100 110101 0001 001010 1110 25 6 110 00101 101001 0110 101001 0110 25 7 111 00101 101001 1110 101001 0001 06 6 110 00110 011001 0110 011001 0110 6 7 111 00110 011001 1110 011001 0001 27 6 110 00111 111000 0110 000111 0110 D7 111 00111 111000 1110 000111 0001 D8 6 110 01000 111001 0110 000110 0110 D8 7 111 01000 111001 0001
22. 5UI 1 83127 ns TXRATEx 0 RXRATEx 1 Received Data Valid Time from RXCLK when RXCKSELx 1 1 027 ns 1 IREFRX 2 REFCLKx Frequency Referenced to Received Clock Period 0 15 0 15 CYV15G0404DXB Bus Configuration Write Timing Characteristics Over the Operating Range tDATAH Bus Configuration Data Hold 0 ns tDATAS Bus Configuration Data Setup 10 ns twRENP Bus Configuration WREN Pulse Width 10 ns CYV15G0404DXB JTAG Test Clock Characteristics Over the Operating Range Test Clock Frequency 20 MHz JTAG Test Clock Period 50 ns CYV15G0404DXB Device RESET Characteristics Over the Operating Range Device RESET Pulse Width 30 ns CYV15G0404DXB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range Parameter Description Condition Min Max Unit Bit Time 5128 666 ps Notes 26 Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock the receive data out of the output register For predictable timing users can use this parameter only if REFCLK period is greater than sum of taperp and set up time of the upstream device When this condition is not true RXCLKx a buffered or divided version of REFCLK when RXCKSELx 1 cou used to clock the receive data out of the device 27 Measured using a 50 duty cycle reference clock 28 REFCLKx has no phase or frequency relationship with
23. An additional latch bank 15 is used as a global mask vector to control the update of the configuration latch banks on a bit by bit Table 9 Device Configuration and Control Latch Descriptions Name Signal Description CYV15G0404DXB basis logic 1 in a bit location allows for the update of that same location of the target latch bank s whereas a logic 0 disables it The reset value of this latch bank is FFh thereby making its use optional by default The mask latch bank is not maskable The functionality is not affected by the bit 0 value of the mask latch bank Latch Types There are two types of latch banks static S and dynamic D Each channel is configured by two static and one dynamic latch bank The S type contain those settings that normally do not change for a given application while the D type controls the settings that could change dynamically during the application s lifetime The first row of latches for each channel address numbers 0 3 7 and 10 are the static receiver control latches The second row of latches for each channel address numbers 1 4 8 and 11 are the static transmitter control latches The third row of latches for each channel address numbers 2 5 9 and 12 are the dynamic control latches that are associated with enabling dynamic functions within the device Latch Bank 14 is also useful for those users that do not need the latch based programmable feature of the device This lat
24. DINx 1 TXDx 1 TXDx 2 DINx 2 TXDx 2 TXDx 3 DINx 3 TXDx 3 TXDx 4 DINx 4 TXDx 4 TXDx 5 DINx 5 TXDx 5 TXDx 6 DINx 6 TXDx 6 TXDx 7 DINx 7 TXDx 7 0 DINx 8 TXCTXx 0 TXCTx 1 MSB DINx 9 TXCTX 1 Note 7 LSB shifted out first If the phase offset between the initialized location of the input clock and REFCLKx exceeds the skew handling capabilities of the phase align buffer an error is reported on that channel s TXERRx output This output indicates an error continuously until the phase align buffer for that channel is reset While the error remains active the transmitter for that channel outputs a continuous 0 7 character to indicate to the remote receiver that an error condition is present in the link Each phase align buffer may be individually reset with minimal disruption of the serial data stream When a phase align buffer error is present the transmission of a word sync sequence recenters the phase align buffer and clears the error indication Note K28 5 characters may be added or removed from the data stream during the phase align buffer reset operation When used with non Cypress devices that require a complete 16 character word sync sequence for proper receive elasticity buffer operation follow the phase alignment buffer reset by a word sync sequence to ensure proper operation Encoder Each character received from the Input register or phase align buffer is passed to the en
25. Feedback mission of any transmission character the transmitter selects the proper version of the transmission character based on the current running disparity value and the transmitter calculates a new value for its running disparity based on the contents of the transmitted character Special character codes C1 7 and C2 7 can be used to force the transmission of a specific special character with a specific running disparity as required for some special sequences in X3 230 After powering on the receiver may assume either a positive or negative value for its initial running disparity Upon reception of any transmission character the receiver decides whether the transmission character is valid or invalid according to the following rules and tables and calculates a new value for its running disparity based on the contents of the received character The following rules for running disparity are used to calculate the new running disparity value for transmission characters that have been transmitted and received Running disparity for a transmission character is calculated from subblocks where the first six bits abcdei form one subblock and the second four bits fghj form the other subblock Running disparity at the beginning of the 6 bit subblock is the running disparity at the end of the previous transmission character running disparity at the beginning of the 4 bit subblock is the running disparity at the end of the 6 bit subblock
26. OE2GL OE1GL PABRSTG FGLEN2 N A 15 MASK D D7 D6 D5 D4 D3 D2 D1 D0 11111111 11116 JTAG Support reset using RESET The JTAG state machine is initialized using The CYV15G0404DXB contains JTAG port to allow system level diagnosis of device interconnect Of the available JTAG modes boundary scan and bypass are supported This capability is present only on the LVTTL inputs and outputs and the REFCLKx clock input The high speed serial inputs and outputs are not part of the JTAG test chain To ensure valid device operation after power up including non JTAG operation the JTAG state machine must also be initialized to a reset state This is done in addition to the device Document 38 02097 Rev B TRST asserting it LOW and de asserting it or leaving it asserted or by asserting TMS HIGH for at least five consecutive TCLK cycles This is necessary to ensure that the JTAG controller does not enter any of the test modes after device power up In this JTAG reset state the rest of the device is in normal operation Note The order of device reset using RESET and JTAG initial ization does not matter Page 23 of 44 Feedback 3 Level Select Inputs Each 3 Level select inputs reports as two bits in the scan register These bits report the LOW MID and HIGH state of the associated input as 00 10 and 11 respectively JTAG ID The JTAG device ID for the CYV15G0404DXB is 0C811069 x Receive Character Statu
27. Page 13 of 44 Feedback Transmit Modes Encoder Bypass When the Encoder is bypassed the character captured from the TXDx 7 0 and TXCTx 1 0 input register is passed directly to the transmit shifter without modification With the encoder bypassed the TXCTx 1 0 inputs are considered part of the data character and do not perform a control function that would otherwise modify the interpretation of the TXDx 7 0 bits The bit usage and mapping of these control bits when the Encoder is bypassed is shown in Table 2 Table 2 Encoder Bypass Mode Signal Name Bus Weight 10B Name TXDx 0 LSB 20 all TXDx 1 21 b TXDx 2 2 TXDx 3 23 d TXDx 4 24 e TXDx 5 25 i TXDx 6 25 f TXDx 7 g g TXCTx 0 28 h TXCTx 1 MSB 29 j When the encoder is enabled the TXCTx 1 0 data control bits control the interpretation of the TXDx 7 0 bits and the characters generated by them These bits are interpreted as listed in Table 3 Table 3 Transmit Modes TXCTx 1 01 0 0 Characters Generated Encoded data character 0 1 K28 5 fill character 1 0 Special character code 1 1 16 character Word Sync Sequence Word Sync Sequence When TXCTx 1 0 11 16 character sequence of K28 5 characters known as a word sync sequence is generated on the associated channel This sequence of K28 5 characters may start with either a positive or negative dispa
28. RFMODEx 1 0 01 the Alternate mode Multi Byte Framer is enabled Like the Cypress mode Multi Byte Framer multiple framing characters must be detected before the character boundary is adjusted In this mode the data stream must contain a minimum of four of the selected framing Note CYV15G0404DXB characters received as consecutive characters on identical 10 bit boundaries before character framing is adjusted 10B 8B Decoder Block The decoder logic block performs two primary functions m Decoding the received transmission characters to data and special character codes m Comparing generated BIST patterns with received characters to permit at speed link and device testing The framed parallel output of each deserializer shifter is passed to its associated 10B 8B Decoder where if the decoder is enabled the input data is transformed from a 10 bit transmission character back to the original data or special character code This block uses the 10B 8B decoder patterns in Table 14 and Table 15 Received special code characters are decoded using Table 15 Valid data characters are indicated by 0006 bit combination on the associated RXSTx 2 0 status bits and special character codes are indicated by a 001b bit combination of these status outputs Framing characters invalid patterns disparity errors and synchronization status are presented as alternate combinations of these status bits When 0 the 10B 8B decode
29. RXCKSELJA D Internal Latch Receive Clock Select RXRATE A D Internal Latch Receive Clock Rate Select SDASEL A D 1 0 Internal Latch Signal Detect Amplitude Select ENCBYP A D Internal Latch Transmit Encoder Bypass TXCKSEL A D Internal Latch Transmit Clock Select 6 6 6 6 6 TXRATE A D Internal Latch 8 Transmit PLL Clock Rate Select RFEN A D Internal Latchf8l Reframe Enable RXPLLPD A D Internal Receive Channel Power Control RXBIST A D Internal Receive Bist Disabled TXBIST A D Internal Transmit Bist Disabled OE2 A D Internal Differential Serial Output Driver 2 Enable OE1 A D Internal Latch 8 Differential Serial Output Driver 1 Enable PABRST A D Internal Transmit Clock Phase Alignment Buffer Reset GLEN 11 0 Internal Global Latch Enable FGLEN 2 0 Internal Force Global Latch Enable Note 6 See Device Configuration and Control Interface for detailed information on the internal latches Document 38 02097 Rev B Page 11 of 44 23 vage Ro 55 PERFORM Pin Definitions continued CYV15G0404DXB Quad HOTLink Il Transceiver CYV15G0404DXB Name Characteristics Signal Description Factory Test Modes Factory Test 2 SCANENe input is for facto
30. a predictable yet pseudo random sequence that can be matched to an identical LFSR in the attached Receiver s A device reset RESET sampled LOW presets the BIST enable latches to disable BIST on all channels All data and data control information present at the associated TXDx 7 0 and TXCTx 1 0 inputs are ignored when BIST is active on that channel If the receive channels are configured for reference clock operation each pass is preceded by a 16 character word sync sequence to allow elasticity buffer alignment and management of clock frequency variations Transmit PLL Clock Multiplier Each Transmit PLL Clock Multiplier accepts a character rate or half character rate external clock at the associated REFCLKx input and that clock is multiplied by 10 or 20 as selected by TXRATEx to generate a bit rate clock for use by the transmit shifter It also provides a character rate clock used by the transmit paths and outputs this character rate clock as TXCLKOx Each clock multiplier PLL is able to accept REFCLKx input between 19 5 MHz and 150 MHz however this clock range is limited by the operating mode of the CYV15G0404DXB clock multiplier TXRATEx and by the level on the associated SPDSELx input SPDSELx are 3 level select 4 inputs that select one of three operating ranges for the serial data outputs and inputs of the associated channel The operating serial signaling rate and allowable range of REFCLKx frequencies are listed
31. and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 02097 Rev Revised December 14 2007 Page 44 of 44 IBM and ESCON are registered trademarks and FICON is a
32. of the TXCLKx input clock relative to its associated is initialized PABRST PABRSTD is an asynchronous input but is sampled by each TXCLKxT to synchronize it to the internal clock domain PABRSTx is a self clearing latch This eliminates the requirement of writing a 1 to complete the initialization of the Phase Alignment Buffer GLEN 11 0 Global Enable The initialization value of the GLENx latch 1 GLENx is used to reconfigure several channels simultaneously in applications where several channels may have the same configuration When GLENx 1 for a given address that address is allowed to participate in a global configuration When GLENx 0 for a given address that address is disabled from participating in a global configuration FGLEN 2 0 Force Global Enable The initialization value of the FGLENx latch is NA The FGLENXx latch forces GLobal ENable no matter what the setting is on the GLENXx latch If FGLENx 1 for the associated Global channel FGLEN forces the global update of the target latch banks Page 22 of 44 Feedback Document 38 02097 Rev B Device Configuration Strategy The following is a series of ordered events needed to load the configuration latches on a per channel basis 1 Pulse RESET Low after device power up This operation resets all four channels Initialize the JTAG state machine to its reset state as detailed in the JTAG Support section Set the static receiver
33. or special character codes to 10 bit transmission characters using an integrated 8B 10B encoder When directed to encode the character as a special character code the encoder uses the special character encoding rules listed in Table 15 When directed to encode the character as a data character it is encoded using the data character encoding rules in Table 14 The 8B 10B encoder is standards compliant with ANSI NCITS ASC X3 230 1994 Fibre Channel IEEE 802 32 Gigabit Ethernet the ESCON and channels ETSI DVB ASI and ATM Forum standards for data transport Many of the special character codes listed in Table 15 may be generated by more than input character The CYV15G0404DXB is designed to support two independent but non overlapping special character code tables This allows the CYV15G0404DXB to operate in mixed environments with other Cypress HOTLink devices using the enhanced Cypress command code set and the reduced command sets of other non Cypress devices Even when used in an environment that normally uses non Cypress Special Character codes the selective use of Cypress command codes can permit operation where running disparity and error handling must be managed Following conversion of each input character from eight bits to a 10 bit transmission character it is passed to the transmit shifter and is shifted out LSB first as required by ANSI and IEEE standards for 8B 10B coded serial data streams
34. the recovered clock s and only acts as a centering reference to reduce clock synchronization time REFCLKxx must be within 1500 PPM 0 15 of the transmitter PLL reference REFCLKx frequency Although transmitting to a HOTLink II receiver neces sitates the frequency difference between the transmitter and receiver reference clocks to be within 1500 PPM the stability of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard For example to be IEEE 802 3z Gigabit Ethernet compliant the frequency stability of the crystal needs to be within 100 29 While sending continuous K28 5s outputs loaded to a balanced 1000 load measured at the cross point of differential outputs over the operating range 30 While sending continuous K28 7s after 100 000 samples measured at the cross point of differential outputs time referenced to REFCLKx input over the operating range 31 Total jitter is calculated at an assumed BER of 1E 12 Hence Total Jitter tJ 14 tDJ 32 Also meets all Jitter Generation and Jitter Tolerance requirements as specified by SMPTE 259 SMPTE 292 ESCON FICON Fibre Channel and DVB ASI Document 38 02097 Rev B Page 29 of 44 Feedback J Cypress CYV15G0404DXB PERFORM CYV15G0404DXB AC Electrical Characteristics continued
35. trademark of International Business Machines HOTLink is a registered trademark and HOTLink Il and MultiFrame are trademarks of Cypress Semiconductor All product and company names mentioned in this document may be the trademarks of their respective holders Feedback
36. 0 gt FLEN 2 0 Document 38 02097 Rev Page 5 of 44 Feedback Cypress CYV15G0404DXB PERFORM Pin Configuration Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IN OUT IN OUT Vo IN GND IN OUT IN GND IN OUT Veg IN OUT IN OUT ce ce Di D1 D2 D2 At At A2 A2 Bi Bi B2 Ba B IN OUT IN OUT Vo IN GND IN OUT IN OUT GND IN OUT Veg IN OUT IN OUT 1 C2 C2 D1 01 02 02 1 1 2 A2 Bi Bi B2 B2 C Ln TDI TMS INSELCINSELB ULCD ULCC GND DATA DATA DATA DATA GND RCLK SPD vcc LDTD TRST LPEND TDO 7 5 3 1 ENB SELD EN D D TCLK INSELD INSELA ULCA SPD GND DATA DATA DATA GND LPENB ULCB LPENA VCC SCAN TMENS SELC 6 4 2 0 EN2 E Voc Voc Voc Voc RX TX RCLK TX RX DC 6 DC 7 END ENA STB 1 CLKOB STB 0 G Tx WREN TX TX SPD LP SPD RX DC 7 DC 4 DCI1 SELB SELA DB 1 H GND GND GND GND GND G
37. 00010 C282 C5C 010 11100 001111 0101 110000 1010 K28 3 C3 0 C03 00000011 C28 3 C7C 011 11100 001111 0011 110000 1100 C4 0 04 00000100 C284 C9C 100 11100 001111 0010 110000 1101 2 511 42 C5 0 C05 00000101 C28 5 CBC 101 11100 001111 1010 110000 0101 K28 6147 C6 0 C06 00000110 28 6 CDC 110 11100 001111 0110 110000 1001 28 7147 43 C7 0 C07 00000111 C28 7 111 11100 001111 1000 110000 0111 K23 7 C8 0 C08 00001000 C237 111 10111 111010 1000 000101 0111 27 7 C9 0 C09 00001001 27 7 111 11011 110110 1000 001001 0111 29 7 C10 0 COA 00001010 29 7 CFD 111 11101 101110 1000 010001 0111 K30 7 C11 0 COB 00001011 C30 7 CFE 111 11110 011110 1000 100001 0111 End of Frame Sequence EOFxx C2 1 C22 001 00010 C2 1 C22 001 00010 28 5 0 28 5 1 Code Rule Violation and SVS Tx Pattern Exception 45 0 7 111 00000 CO 7 CEO 111 00000 100111 1000 011000 0111 K28 5H8l C1 7 CE1 111 00001 C1 7 CE1 111 00001 001111 1010 001111 1010 4K28 5 71 C2 7 CE2 11100010 2 7 111 00010 110000 0101 110000 0101 Running Disparity Violation Pattern Exception C4 7 CE4 111 00100 C4 7 CE4 111 00100 110111 0101 001000 1010 Notes 38 All codes not shown are reserved 39 Notation for Special Character Code Name is consistent with Fibre Channel and ESCON naming conventions Spe
38. 000110 1110 9 6 110 01001 100101 0110 100101 0110 9 7 111 01001 100101 1110 100101 0001 D10 6 110 01010 010101 0110 010101 0110 D10 7 111 01010 010101 1110 010101 0001 D11 6 110 01011 110100 0110 110100 0110 D11 7 111 01011 110100 1110 110100 1000 D12 6 110 01100 001101 0110 001101 0110 D12 7 111 01100 001101 1110 001101 0001 91356 110 01101 101100 0110 101100 0110 013 7 11101191 101100 1110 101100 1000 D14 6 110 01110 011100 0110 011100 0110 D14 7 111 01110 011100 1110 011100 1000 D15 6 110 01111 010111 0110 101000 0110 D15 7 111 01111 010111 0001 101000 1110 D16 6 110 10000 011011 0110 100100 0110 D16 7 111 10000 011011 0001 100100 1110 D17 6 110 10001 100011 0110 100011 0110 111 10001 100011 0111 100011 0001 D18 6 110 10010 010011 0110 010011 0110 D18 7 111 10010 010011 0111 010011 0001 D19 6 110 10011 110010 0110 110010 0110 D19 7 111 10011 110010 1110 110010 0001 D20 6 110 10100 001011 0110 001011 0110 D20 7 111 10100 001011 0111 001011 0001 D21 6 110 10101 101010 0110 101010 0110 D21 7 111 10101 101010 1110 101010 0001 D22 6 110 10110 011010 0110 011010 0110 D22 7 111 10110 011010 1110 011010 0001 D23 6 110 10111 111010 0110 000101 0110 D23 7 111 10111 111010 0001 000101 1110
39. 011 10010 1001 110010 1001 220 0 000 10100 001011 1011 001011 0100 220 1 001 10100 001011 1001 001011 1001 221 0 000 10101 101010 1011 101010 0100 221 1 001 10101 101010 1001 101010 1001 222 0 000 10110 011010 1011 011010 0100 222 1 001 10110 011010 1001 011010 1001 223 0 000 10111 11010 0100 000101 1011 223 1 001 10111 11010 1001 000101 1001 224 0 000 11000 10011 0100 001100 1011 224 1 001 11000 10011 1001 001100 1001 225 0 000 11001 100110 1011 100110 0100 D25 1 001 11001 100110 1001 100110 1001 226 0 000 11010 010110 1011 010110 0100 D26 1 001 11010 010110 1001 010110 1001 D27 0 000 11011 0110 0100 001001 1011 D27 1 001 11011 0110 1001 001001 1001 D28 0 000 11100 001110 1011 001110 0100 D28 1 001 11100 001110 1001 001110 1001 D29 0 000 11101 101110 0100 010001 1011 D29 1 001 11101 101110 1001 010001 1001 230 0 000 11110 011110 0100 100001 1011 D30 1 001 11110 011110 1001 100001 1001 D31 0 000 11111 101011 0100 010100 1011 D31 1 001 11111 101011 1001 010100 1001 Document 38 02097 Rev Page 38 of 44 Feedback
40. 1 D14 2 010 01110 011100 0101 011100 0101 D14 3 011 01110 011100 1100 011100 0011 D15 2 010 01111 010 0101 101000 0101 D15 3 011 01111 010 0011 101000 1100 D16 2 010 10000 0110 0101 100100 0101 D16 3 011 10000 0110 0011 100100 1100 D17 2 010 10001 100011 0101 100011 0101 D17 3 011 10001 100011 1100 100011 0011 D18 2 010 10010 010011 0101 010011 0101 91843 011 10010 01001 100 010011 0011 D19 2 010 10011 110010 0101 110010 0101 D19 3 011 10011 10010 1100 110010 0011 D20 2 010 10100 001011 0101 001011 0101 D20 3 011 10100 001011 1100 001011 0011 D21 2 010 10101 101010 0101 101010 0101 D21 3 011 10101 101010 1100 101010 0011 D22 2 010 10110 011010 0101 011010 0101 D22 3 011 10110 011010 1100 011010 0011 D23 2 010 10111 11010 0101 000101 0101 023 3 011 10111 11010 0011 000101 1100 24 2 010 11000 10011 0101 001100 0101 D24 3 011 11000 10011 0011 001100 1100 25 2 010 11001 100110 0101 100110 0101 025 3 011 11001 100110 1100 100110 0011 26 2 010 11010 010110 0101 010110 0101 D26 3 011 11010 010110 1100 010110 0011 D27 2 010 11011 0110 0101 001001 0101 27 3 011 11011 0110 0011 001001 1100 D28 2 010 11100 001110 0101 001110 0101 D28 3 011 11100 001110 1100 001110 0011 D29 2 010 11101 101110 0101 010001 0101 D29 3 011 11101 101110 0011 010001 1100 D30 2 010 11110 011110 0101 100001 0101 030 3 011 11110 011110 0011 100001 1100 31 2 010 11111 101011 0101 010100 0101 D31 3 011 11111 101011 0011 010100 1100 Document 38 02097 Rev Page 39
41. 6 RX SPD LP SPD TX TX WREN TX DB 1 SELA ENC SELB DC 1 DC 4 DC 7 GND GND GND GND GND GND GND GND RX RX RX RX TX TX TX TX DB 2 DB 5 DB 0 STB 2 DC 3 DC 5 LFIB Rx RX RX REF RX DB 7 DB 4 0813 CLKC CTC 0 CLKC DC 2 TX RX RX RX TX REF RX DB 6 CLKB CLKB 0816 DC 6 DC 3 TX TX REF REF TX RX RX CLKB ERRB CLKB CLKB ERRC ENC 5 GND GND GND GND GND GND GND GND TX TX TX RX RX RX RX DB 2 DB 3 DB 4 0815 STC 1 STC 0 DC 1 TX TX TX RX RX TX RX DB 7 CTB 1 DB 0 DB 1 CLKC CLKC CLKOC STC 2 Vcc Voc Voc Voc Voc Voc Voc RX TX RX Veg TX TX GND TX REF ADDR TXC TX TX TX TX STA 1 STA 2 CTB 0 DA 2 CTA 0 DAH CLKD 0 DD 1 202 CTD 1 DD 2 DD 1 DD 0 RX RX RX Veg TX TX TX REF ADDR FX RX RX Tx TX TX STA 0 DA 0 DA 3 DA 7 DA 7 DA 3 CLKOA CLKD 2 STD 2 STD 0 DD 3 DD 6 DD 4 RX RX REF IFA vog TX TX TX RX ADDR ADDR RX RX FD Tx TX DA 1 CLKA DA 6 DA 2 ERRA CLKA 1 STD 1 CLKD 0015 RX RX REF TX vog TX TX
42. BYPC Mode is selected by DECMODEx When DECBYPx 0 the decoder is bypassed and raw 10 bit characters DECBYPD are passed through the receiver Document 38 02097 Rev B Page 20 of 44 Feedback CYV15G0404DXB Receive Clock Select The initialization value of the RXCKSELx latch 1 RXCKSELx selects the receive clock source used to transfer data to the Output Registers and the clock source for the RXCLK output When RXCKSELx 1 the associated Output Registers are clocked by REFCLKx at the associated RXCLKx x Table 9 Device Configuration and Control Latch Descriptions continued output buffer When RXCKSELx 0 the associated Output Registers are clocked by the Recovered Byte clock at the associated RXCLKx output buffer These output clocks may operate at the character rate or half Signal Description Receive Clock Rate Select The initialization value of the RXRATEx latch 1 RXRATEx is used to select the the character rate as selected by RXRATEx When RXRATEx 1 and RXCKSELx 0 the RXCLKx clock outputs are complementary clocks that follow the recovered clock operating at half the character rate Data for the associated receive channels should be When RXRATEx 0 and RXCKSELx 0 the RXCLKx clock outputs are complementary clocks that follow the recovered clock operating at the character rate Data for the associated receive channels should be latched Name RXCKSELA RXCKSELB RXCKSEL
43. C RXCKSELD RXRATEA RXRATEB rate of the RXCLKx clock output RXRATEC RXRATED latched alternately on the rising edge of RXCLKx and RXCLKx on the rising edge of or falling edge of RXCLKx When RXRATEx 1 with RXCKSELx 1 and REFCLKxt is a full rate clock the RXCLKx clock outputs are complementary clocks that follow the reference clock operating at half the character rate Data for the associated receive channels should be latched alternately on the rising edge of RXCLKx and RXCLKx When RXRATEx 0 with RXCKSELx 1 and REFCLKxt is a full rate clock the RXCLKx clock outputs are complementary clocks that follow the reference clock operating at the character rate Data for the associated receive channels should be latched on the rising edge of RXCLKx or falling edge of RXCLKx When RXCKSELx 1 and REFCLKxz is half rate clock the value of RXRATEx is not interpreted and the clock outputs are complementary clocks that follow the reference clock operating at half the character rate Data for the associated receive channels should be latched alternately on the rising edge of Primary Serial Data Input Signal Detector Amplitude Select The initialization value of the SDASEL1x 1 0 latch 10 SDASEL1x 1 0 selects the trip point for the detection of a valid signal for the INx1 Primary Differential Serial Data Inputs SDASEL1A 1 0 SDASEL1B 1 0 SDASEL1C 1 0 SDASEL1DJ 1 0 When SDASEL1x 1 0 01
44. Character byte encoded and transmitted Table 12 shows naming notations and examples of valid transmission characters Use of the Tables for Checking the Validity of Received Transmission Characters The column corresponding to the current value of the receiver s running disparity is searched for the received transmission character If the received transmission character is found in the proper column then the transmission character is valid and the associated data byte or special character code is determined decoded If the received transmission character is not found in that column then the transmission character is invalid This is a code violation Independent of the transmission character s validity the received transmission character is used to calculate a new value of running disparity The new value is used as the receiver s current running disparity for the next received trans mission character Table 12 Valid Transmission Characters Data Din or Q Byte Name N our Hex Value 765 43210 D0 0 000 00000 00 D1 0 000 00001 01 D2 0 000 00010 02 D5 2 010 00101 45 D30 7 111 11110 FE D31 7 111 11111 FF Detection of a code violation does not necessarily show that the transmission character in which the code violation was detected is in error Code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the t
45. Conventions Information transmitted over a serial link is encoded eight bits at a time into a 10 bit Transmission Character and then sent serially bit by bit Information received over a serial link is collected ten bits at a time and those transmission characters that are used for data characters are decoded into the correct 8 bit codes The 10 bit transmission code supports all 256 8 bit combinations Some of the remaining transmission characters special characters are used for functions other than data trans mission The primary use of a transmission code is to improve the trans mission characteristics of a serial link The encoding defined by the transmission code ensures that sufficient transitions are present in the serial bit stream to make clock recovery possible at the receiver Such encoding also greatly increases the likelinood of detecting any single or multiple bit errors that may occur during transmission and reception of information In addition some special characters of the transmission code selected by Fibre Channel Standard contain a distinct and easily recognizable bit pattern that assists the receiver in achieving character alignment on the incoming bit stream Notation Conventions The documentation for the 8B 10B Transmission Code uses letter notation for the bits in an 8 bit byte Fibre Channel Standard notation uses bit notation of A D E F G H for the 8 bit byte for the raw 8 bit data and the let
46. D24 6 110 11000 110011 0110 001100 0110 D24 7 111 11000 110011 0001 001100 1110 D25 6 110 11001 100110 0110 100110 0110 25 7 211 11001 100110 1110 100110 0001 D26 6 110 11010 010110 0110 010110 0110 D26 7 111 11010 010110 1110 010110 0001 D27 6 110 11011 110110 0110 001001 0110 D27 7 111 11011 110110 0001 001001 1110 D28 6 110 11100 001110 0110 001110 0110 D28 7 111 11100 001110 1110 001110 0001 D29 6 110 11101 101110 0110 010001 0110 D29 7 114 11101 101110 0001 010001 1110 D30 6 110 11110 011110 0110 100001 0110 D30 7 111 11110 011110 0001 100001 1110 D31 6 110 11111 101011 0110 010100 0110 D31 7 111 11111 101011 0001 010100 1110 Document 38 02097 Rev Page 41 of 44 Feedback CYV15G0404DXB Table 15 Valid Special Character Codes and Sequences special character code or RXSTx 2 0 001 8 39 S C Byte Name Cypress Alternate Current RD Current RD S C Code Name Sc Bye s NL abcdei fghj abcdei fghj K28 0 CO 0 C00 00000000 28 0 C1C 000 11100 001111 0100 110000 1011 K28 1147 C1 0 C01 00000001 C28 1 001 11100 001111 1001 110000 0110 K28 2147 C2 0 C02 000
47. E tou B 1845306 See ECN UKK VED Added clarification for the necessity of JTAG controller reset and the methods to implement it Cypress Semiconductor Corporation 2005 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of
48. FL gt REFCLKx tTREFDH TXDx 7 0 XK X Document 38 02097 Rev Page 30 of 44 Feedback CYV15G0404DXB CYPRESS PERFORM CYV15G0404DXB HOTLink II Transmitter Switching Waveforms continued Transmit Interface Write Timing REFCLKx selected 1 REFCLKx TXDx 7 0 TXCTx 1 0 Note 33 When REFCLKxz is configured for half rate operation TXRATE 1 and data is captured using REFCLKx instead of a TXCLKx clock Data is captured using both the rising and falling edges of REFCLKx Transmit Interface TXCLKOx Timing TXRATEx 1 REFCLKx Note 34 Note 35 TXCLKOx internal Transmit Interface TXCLKOx Timing TXRATEx 0 REFCLKx trxcLko Note 35 trxoH TXCLKOx Page 31 of 44 Document 38 02097 Rev Feedback gt X CYPRESS CYV15G0404DXB PERFORM Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver Receive Interface Read Timing REFCLKx Selected full RXCLKx REFCLKx tRREFDA tRREFDW tRREFDW RXDx 7 0 RXSTX2 0 36 TXERRx RXCLKx Notes 34 The TXCLKOx output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of 35 The rising edge of TXCLKOx output has no direct phase r
49. KSELx 1 the associated input register TXDx 7 0 and TXCT x 1 0 is clocked by REFCLKxT In this mode the phase alignment buffer in the transmit path is bypassed When TXCKSELx 0 the associated TXCLKxT is used to clock in the input registers ENCBYPA ENCBYPB ENCBYPC ENCBYPD TXCKSELA TXCKSELB TXCKSELC TXCKSELD TXDx 7 0 and 1 01 Document 38 02097 Rev B CYV15G0404DXB Table 9 Device Configuration and Conirol Latch Descriptions continued Transmit PLL Clock Rate Select The initialization value of the TXRATEx latch 0 TXRATEx is used to select the clock multiplier for the Transmit PLL When TXRATEx 0 each transmit PLL multiples the associated REFCLKxx input by 10 to generate the serial bit rate clock When TXRATEx 0 TXCLKOx output clocks are full rate clocks and follow the frequency and duty cycle of the associated REFCLKx input When 1 each Transmit PLL multiplies the associated REFCLKx input by 20 to generate the serial Signal Description bit rate clock When 1 the TXCLKOx output clocks are twice the frequency rate of the REFCLKx input When TXCKSELx 1 and TXRATEx 1 the Transmit Data Inputs are captured using both the rising and falling edges of REFCLKx TXRATEx 1 and SPDSELx is LOW is an invalid state and this combination Name TXRATEA TXRATEB TXRATEC TXRATED is reserved RFENA Reframe Enab
50. KSELx latch If RXCLKx is a full rate clock the RXCLKx clock outputs are complementary clocks operating at the character rate The RXDx 7 0 outputs for the associated receive channels follow rising edge of RXCLKx or falling edge of RXCLKx If RXCLKxsx is a half rate clock clock outputs are complementary clocks operating at half the character rate The RXDx 7 0 outputs for the associated receive channels follow both the falling and rising edges of the associated RXCLKxx clock outputs RXSTA 2 0 RXSTB 2 0 RXSTC 2 0 RXSTD 2 0 LVTTL Output synchronous to the selected RXCLK output or REFCLKx input Parallel Status Output RXSTA 2 0 status outputs change relative to the receive interface clock The receive interface clock is selected by the RXCKSELx latch If is a full rate clock the RXCLKx clock outputs are complementary clocks operating at the character rate The RXSTAx 2 0 outputs for the associated receive channels follow rising edge of RXCLKx or falling edge of RXCLKx If RXCLKxsx is a half rate clock clock outputs are complementary clocks operating at half the character rate The RXSTAx 2 0 outputs for the associated receive channels follow both the falling and rising edges of the associated RXCLKx clock outputs When the decoder is bypassed RXSTx 1 0 become the two low order bits of the 10 bit received character RXSTx 2 HIGH indicates the presence of a Comma ch
51. N 01 TXDD 6 LVTTL IN P18 TXDB 4 LVTTL IN TXDD 4 LVTTL IN 02 TXCLKD LVTTL IN PD P19 TXDB 3 LVTTL IN TXCTD O LVTTL IN Y03 RXDD 7 LVTTL OUT P20 TXDB 2 LVTTL IN V04 RXDD 6 LVTTL OUT 04 RXCLKD R01 RXSTC 2 LVTTL OUT V05 05 VCC POWER R02 TXCLKOC LVTTL OUT RXDD S3 LVTTL OUT 06 RXDD 5 LVTTL OUT R03 RXCLKC LVTTL OUT V07 RXSTD O LVTTL OUT 07 RXDD 0 LVTTL OUT R04 RXCLKC LVTTL OUT V08 GND GROUND 08 GND GROUND R17 TXDB 1 LVTTL IN RXSTD 2 LVTTL OUT YO9 TXCLKOD LVTTL OUT R18 TXDB 0 LVTTL IN 10 ADDR 2 LVTTL IN PU Y10 NC NO CONNECT R19 TXCTB 1 LVTTL IN V11 REFCLKD PECL IN Y11 TXCLKA LVTTL IN PD R20 TXDB 7 LVTTL IN 12 TXCLKOA LVTTL OUT 12 RXCLKA LVTTL OUT 01 V13 GND GROUND Y13 GND GROUND T02 VCC POWER 14 3 LVTTL IN Y14 0 LVTTL IN T03 VCG POWER V15 TXDA 7 LVTTL IN Y15 TXDA 5 LVTTL IN 04 VCC POWER V16 VCC POWER Y16 VCC POWER T17 V17 RXDA 7 LVTTL OUT 17 TXERRD LVTTL OUT T18 V18 RXDA 3 LVTTL OUT Y18 REFCLKA PECL IN T19 19 RXDA O LVTTL OUT Y19 RXDA 6 LVTTL OUT T20 V20 RXSTA 0 LVTTL OUT Y20 RXDA 5 LVTTL OUT 001 TXDD 0 LVTTL IN wot TXDD 5 LVTTL IN 002 TXDD 1 LVTTL IN W02 TXDD 7 LVTTL IN Document 38 02097 Rev B Page 35 of 44 CYPRESS PERFORM X3 230 Codes and Notation
52. ND GND GND J TX TX TX TX RX RX RX RX 5 DC 3 STB 2 DB 5 DB 2 K mE RX REF TX TX RX RX RX DC 2 CLKC CTC 0 CLKC DB 3 DB 4 0817 L ss RX REF TX RX RX TX DC 8 CLKC DC 6 DB 6 CLKB CLKB M RX RX ROLK TX REF REF TX TX DC 4 DC 5 ERRC CLKB CLKB ERRB CLKB N GND GND GND GND GND GND GND GND P RX RX RX RX TX TX TX TX STC 0 STC 1 DB 5 DB 4 DB 3 0812 R RX TX RX RX TX TX TX TX STC 2 CLKOC CLKC CLKC DB 1 DB 0 CTB 1 0877 Voc Voc Voc 0 Tx TX TX TX RX TX ADDR REF TX GND TX TX Vee TX RX RX DD 0 DD 1 DD 2 CTD 1 DD 2 DD 1 0 CLKD DAH CTA 0 DA 2 CTB 0 STA 2 STA 1 V TX TX TX RX RX Rx Rx ADDR REF TX GND TX TX Veg RX nx RX DD 3 CTD 0 DD 6 DD 3 STD 0 STD 2 2 CLKD CLKOA DA 3 DA 7 DA 7 DA 3 DA 0 STA 0 TX Tx RX GND ADDR ADDR RX TX GND TX TX CFIA REF RX RX DD 5 DD 7 CLKD DD 4 STD 1 3 1 CLKA ERRA DA 2 Y TX TX RX Rx RX RX GND TX
53. OW TMS LVTTL Input Test Mode Select Used to control access to the JTAG Test Modes If maintained internal pull up high for 25 TCLK cycles the JTAG test controller is reset TCLK LVTTL Input JTAG Test Clock internal pull down TDO 3 State LVTTL Output Test Data Out JTAG data output buffer High Z while JTAG test mode is not selected TDI LVTTL Input Test Data In JTAG data input port internal pull up TRST LVTTL Input JTAG reset signal When asserted LOW this input asynchronously resets the internal pull up JTAG test access port controller Power Voc 3 3V Power GND Signal and Power Ground for all internal circuits CYV15G0404DXB HOTLink II Operation The CYV15G0404DXB is a highly configurable independent clocking quad channel transceiver designed to support reliable transfer of large quantities of data using high speed serial links from multiple sources to multiple destinations This device supports four single byte channels CYV15G0404DXB Transmit Data Path Input Register The bits in the Input Register for each channel support different assignments based on if the input data is encoded or unencoded These assignments are shown in Table 1 When the ENCODER is enabled each input register captures eight data bits and two control bits on each input clock cycle Document 38 02097 Rev B When the encoder is bypassed the control bits are part of the preencoded 10 bit characte
54. PERIOD RECOVERED BYTE CLOCK PERIOD 4096 During the time that the range control forces the RXPLL VCO to track REFCLKx the LFIx output is asserted LOW After a valid serial data stream is applied it may take up to one RANGE CONTROL SAMPLING PERIOD before the PLL locks to the input data stream after which LFIx should be HIGH Receive Channel Enabled The CYV15G0404DXB contains four receive channels that be independently enabled and disabled Each channel can be enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface When the RXPLLPDx latch 0 the associated PLL and analog circuitry of the channel is disabled Any disabled_channel indicates a constant link fault condition on the LFlx output When RXPLLPDx 1 the associated PLL and receive channel is enabled to receive and decode a serial stream Note When a disabled receive channel is reenabled the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms Clock Data Recovery The extraction of a bit rate clock and recovery of bits from each received serial stream is performed by a separate CDR block within each receive channel The clock extraction function is performed by an integrated PLL that tracks the frequency of the transitions in the incoming bit stream and align the phase of the internal bit rate clock to the transitions in th
55. TXERRC lt 1 TXCLKC PABRSTC BIS S 1 TXCKSELC y V V Y 8 S V TXDC 7 0 5 2 ms 2 OUTCI a B8 L ro TXCTC 1 0 gt 0 m ae __ F OUTC2 E 2 OUTC2 a gt TXLBC REFCLKD gt Bit Rate Clock ransmit r RECLCKD F Clock Multiplier D q SPDSELD gt ENCBYPD TXCLKOD Character Rate Clock D REPEAT TXERRD TXCLKD PABRSTD TXBISTD 0 1 TXCKSELD V JM OUTD1 5 e 10 96 OUTD1 LL TXDDI7 0 ad i j gt OUTD2 o Dx OUTD2 TXCTD 1 m cCTD 0 gt TXLBD Document 38 02097 Rev B Page 3 of 44 Feedback Z CYPRESS CYV15G0404DXB PERFORM Receive Path Block are Internal Reclocker Signals gt Internal Signal TXLB A D are Internal Serial Loopback Signals RESET JTAG SPDSELA TMS RXPLLPDA eae TCLK sa gt it RECLCKA Controller TS p LPENA gt gt Receive TDO INSELA p Signal p gt LFA
56. To prevent a buffer overflow or underflow on a receive channel a minimum density of framing characters must be present in the received data streams When the receive channel output register is clocked by a recovered clock no characters are added or deleted and the receiver elasticity buffer is bypassed Power Control CYV15G0404DXB supports user control of the powered up or down state of each transmit and receive channel The receive channels are controlled by the RXPLLPDx latch through the device configuration interface When RXPLLPDx 0 the associated PLL and analog circuitry of the channel is disabled The transmit channels are controlled by the OE1x and the OE2x latches through the device configuration interface When a driver is disabled through the configuration interface it is internally powered down to reduce device power If both serial drivers for a channel are in this disabled state the associated internal logic for that channel is powered down as well Device Reset State When the CYV15G0404DxXgB is reset by assertion of RESET all state machines counters and configuration latches in the device are initialized to a reset state and the elasticity buffer pointers are setto a nominal offset Additionally the JTAG controller must also be reset to ensure valid operation even if JTAG testing is not performed See the JTAG Support section for JTAG state machine initialization See Table 9 for the initialize values of th
57. XDC 3 LVTTL IN 805 VCC POWER D11 DATA 2 LVTTL IN PU J17 RXSTB 2 LVTTL OUT 06 IND1 CML IN D12 DATA 0 LVTTL IN PU J18 RXDBJ O LVTTL OUT B07 OUTD1 CML OUT D13 GND GROUND J19 RXDB 5 LVTTL OUT B08 GND GROUND D14 LPENB LVTTL IN PD J20 RXDB 2 LVTTL OUT B09 IND2 CML IN D15 ULCB LVTTL IN PU K01 RXDC 2 LVTTL OUT B10 OUTD2 CML OUT D16 REFCLKC PECL IN B11 INA1 CML IN D17 LPENA LVTTL IN PD TXCTC O IN 12 OUTA1 CML OUT 018 VCC POWER K04 TXCLKC LVTTL IN PD B13 GND GROUND 019 SCANEN2 LVTTL IN PD K17 RXDB 3 LVTTL OUT B14 2 CML IN D20 LVTTL IN PD K18 RXDB 4 LVTTL OUT B15 OUTA2 CML OUT E01 K19 RXDB 7 LVTTL OUT B16 VCC POWER E02 VCC POWER K20 LFIB LVTTL OUT B17 INB1 CML IN E03 101 RXDC 3 LVTTL OUT B18 OUTB1 CML OUT E04 102 REFCLKC PECL IN 19 2 CML IN E17 03 LFIC LVTTL OUT B20 OUTB2 CML OUT E18 VCC POWER 104 TXDC 6 LVTTL IN C01 TDI LVTTL IN PU E19 VCC POWER L17 RXDB 6 LVTTL OUT C02 TMS LVTTL IN PU E20 VCC POWER L18 RXCLKB LVTTL OUT C03 INSELC LVTTL IN F01 RXDC 6 LVTTL OUT L19 RXCLKB LVTTL OUT Document 38 02097 Rev B Page 34 of 44 Feedback CYPRESS CYV15G0404DXB PERFORM Table 11 Package Coordinate Signal Allocation continued Signa
58. aracter in the Output Register When the decoder is enabled RXSTx 2 0 provide status of the received signal See Table 11 for a list of received character status RXCLKA RXCLKB RXCLKC RXCLKD Receive Path Clock Signals LVTTL Output Clock Receive Clock Output RXCLKxt is the receive interface clock used to control timing of the RXDx 7 0 and RXSTA 2 0 parallel outputs The source of the RXCLKx outputs is selected by the RXCKSELx latch via the device configuration interface These true and complement clocks are used to control timing of data output transfers These clocks are output continuously at either the dual character rate 1 20 the serial bit rate or character rate 1 10 the serial bit rate of the data being received as selected by RXRATEx When configured such that the output data path is clocked by the REFCLKxx instead of a recovered clock the RXCLKx output drivers present a buffered or divided form depending on RXRATEx of the associated REFCLKx that are delayed in phase to align with the data This phase difference allows the user to select the optimal clock REFCLKx RXCLK for setup or hold timing for their specific system When REFCLKxt is a full rate clock the RXCLKx rate depends on the value of RXRATEx When REFCLKxt is a half rate clock and RXCKSELx 0 the RXCLKx rate depends on the value of RXRATEx When is a half rate clock and RXCKSELx 1 the RXCLKx rate does not depend o
59. ch bank could be used in those applications that do not need to modify the default value of the static latch banks and that can afford a global that is not independent control of the dynamic signals In this case this feature becomes available when ADDR 3 0 is left unchanged with a value of 1110 and WREN is left asserted The signals present in DATA 7 0 effectively become global control pins and for the latch banks 2 5 8 and 11 RFMODEA 1 0 8 1 0 RFMODEC 1 0 RFMODEDf 1 0 Reframe Mode Select The initialization value of the RFMODEx 1 0 latches 10 RFMODEx is used to select the operating mode of the framer When RFMODEx 1 0 00 the low latency framer is selected This frames on each occurrence of the selected framing character s in the received data stream This mode of framing stretches the recovered clock for one or multiple cycles to align that clock with the recovered data When RFMODE 1 0 01 the alternate mode Multi Byte parallel framer is selected This requires detection of the selected framing character s in the received serial bit stream on identical 10 bit boundaries on four directly adjacent characters The recovered character clock remains in the same phasing regardless of character offset When RFMODEx 1 0 210 the Cypress mode Multi Byte parallel framer is selected This requires a pair of the selected framing character s on identical 10 bit boundaries within a span of 50 bits before
60. cial Character Code Name is intended to describe binary information present on I O pins Common usage for the name can either be in the form used for describing Data patterns i e 0 0 through C31 7 or in hex notation i e Cnn where nn the specified value between 00 and FF 40 Both the Cypress and alternate encodings may be used for data transmission to generate specific Special Character Codes The decoding process for received characters generates Cypress codes or Alternate codes as selected by the BOE 7 0 configuration inputs 41 These caracters are used for control of ESCON interfaces They can be sent as embedded commands or other markers when not operating using ESCON protocols 42 character is used for framing operations by the receiver It is also the pad or fill character transmitted to maintain the serial link when no user data is available 43 Care must be taken when using this Special Character code When 7 0 or a 0 7 is followed by a D11 x or D20 x an alias K28 5 sync character is created These sequences can cause erroneous framing and should be avoided while RFENx 1 44 C2 1 Transmit either K28 5 K28 5 as determined by Current RD and modify the Transmission Character that follows by setting its least significant bit to 1 or 0 If Current RD at the start of the following character is plus the LSB is set to 0 and if Current RD is minus the LSB becomes 1 This modification allows construction
61. coder logic This block interprets each character and any associated control bits and outputs a 10 bit transmission character Document 38 02097 Rev B CYV15G0404DXB Depending on the operational mode the generated transmission character may be m The 10 bit preencoded character accepted in the input register m The 10 bit equivalent of the 8 bit Data character accepted in the input register m The 10 bit equivalent of the 8 bit Special Character code accepted in the input register m The 10 bit equivalent of the CO 7 violation character if a phase align buffer overflow or underflow error is present m A character that is part of the 511 character BIST sequence m A K28 5 character generated as an individual character or as part of the 16 character Word Sync Sequence Data Encoding Raw data as received directly from the transmit input register is seldom in a form suitable for transmission across a serial link The characters must usually be processed or transformed to guarantee m aminimum transition density to allow the receive PLL to extract a clock from the serial data stream m A DC balance in the signaling to prevent baseline wander m Run length limits in the serial data to limit the bandwidth requirements of the serial link m the remote receiver a way of determining the correct character boundaries framing When the encoder is enabled ENCBYPx 1 the characters transmitted are converted from data
62. ctor The transition density detector limit is one transition in every 60 CYV15G0404DXB Quad HOTLink Il Transceiver CYV15G0404DXB consecutive bits When LDTDEN is LOW only the range controller determines if the LVTTL Input internal pull down RXPLL tracks REFCLKx or the selected input serial data stream For the cases when RXCKSELx 0 recovered clock it is recommended to set LDTDEN HIGH Reclocker Enable When RCLKENx is HIGH the RXPLL performs clock and data recovery functions on the input serial data stream and routes the deserialized data to the RXDx 7 0 and RXSTA 2 0 parallel data outputs as configured by DECBYPx It also presents the reclocked serial data to the enabled differential serial outputs When RCLKENXx is LOW the receive reclocker is disabled and the 7 0 parallel data inputs and TXCTx 1 0 inputs are interpreted as configured by ENCBYPx to generate appropriate 10 bit characters that are presented to the differential serial RCLKENA RCLKENB RCLKENC RCLKEND LVTTL Input internal pull up The reclocker feature is optimized to be used for SMPTE video applications Use Local Clock When ULCx is LOW the RXPLL is forced to lock to REFCLKx instead of the received serial data stream While ULCx is LOW the LFIx for the the input data streams This function is used in applications in which a stable ULCA ULCB ULCC ULCD 3 Level Select static control input outputs a
63. e input is more positive than the complement input A logic 0 exists when the complement input is more positive than true input 14 The common mode range defines the allowable range of REFCLKx REFCLKx when REFCLKx REFCLKx This marks the zero crossing between the true and complement inputs as the signal switches between a logic 1 and a logic 0 Document 38 02097 Rev B Page 26 of 44 _ gt CYPRESS CYV15G0404DXB PERFORM CYV15G0404DXB DC Electrical Characteristics continued Parameter Description Test Conditions Min Max Unit Differential CML Serial Outputs OUTA1 OUTA2 OUTB1 OUTB2 OUTC1 OUTC2 OUTD1 OUTD2 Output HIGH Voltage 1000 differential load Vcc 0 5 Vcc 0 2 V Voc Referenced 1500 differential load 05 02 V Output LOW Voltage 1000 differential load Vcc 1 4 Voc 0 7 V Referenced 1500 differential load 1 4 07 V Output Differential Voltage 1000 differential load 450 900 mV OUT GUT 1500 differential load 560 1000 Differential Serial Line Receiver Inputs INA1 INA2 INB1 INB2 INC1 INC2 IND1 IND2 Input Differential Voltage IN IN 100 1200 mV Highest Input HIGH Voltage Vcc V VILE Lowest Input LOW Voltage Vcc 2 0 V Input HIGH Current Vin
64. e configuration latches Following a device reset it is necessary to enable the transmit and receive channels used for normal operation This is done by sequencing the appropriate values on the device configuration interface Output Bus Each receive channel presents an 11 signal output bus consisting of An 8 bit data bus m A 3 bit status bus The signals present on this output bus are modified by the present operating mode of the CYV15G0404DXB as selected by the DECBYPx configuration latch This mapping is shown Table 7 11 When the receive paths are configured for REFCLKx operation each pass must be preceded by a 16 character Word Sync Sequence to allow management of clock frequency variations Document 38 02097 Rev B Page 18 of 44 Feedback Table 7 Output Register Bit Assignments Signal Name F DECBYPx 0 DECBYP 1 RXSTx 2 LSB COMDETx RXSTX 2 RXST 1 DOUTx 0 RXSTX 1 RXSTX 0 DOUTX 1 RXSTX 0 RXDx 0 DOUTX 2 RXDx 0 RXDX 1 DOUTxX 3 RXDx 1 RXDx 2 DOUTX 4 RXDx 2 RXDx 3 DOUTx 5 RXDx 3 RXDx 4 DOUT x6 RXDx 4 RXDx 5 DOUTX 7 RXDx 5 RXDx 6 DOUTx 8 RXDx 6 RXDx 7 MSB DOUTX 9 RXDx 7 When the 10B 8B decoder is bypassed the framed 10 bit value is presented to the associated output register along with a status output signal indicating if the character in the output register is one of the selected framing character
65. e selected serial data stream Document 38 02097 Rev B CYV15G0404DXB Each CDR accepts a character rate bit rate 10 or half character rate bit rate 20 reference clock from the associated REFCLKx input This REFCLKx input is used to Ensure that the VCO within the CDR is operating at the correct frequency rather than a harmonic of the bit rate Reduce PLL acquisition time m Limit unlocked frequency excursions of the CDR VCO when there is no input data present at the selected serial line receiver Regardless of the type of signal present the CDR attempts to recover a data stream from it If the signalling rate of the recovered data stream is outside the limits set by the range control monitors the CDR tracks REFCLKxx instead of the data stream Once the CDR output RXCLK frequency returns close to REFCLKx frequency the CDR input is switched back to the input data stream If no data is present at the selected line receiver this switching behavior may result in brief RXCLK frequency excursions from REFCLKx However the validity of the input data stream is indicated by the LFlx output The frequency of REFCLKx is required to be within 1500 ppm of the frequency of the clock that drives the REFCLKxx input of the remote transmitter to ensure a lock to the incoming data stream For systems using multiple or redundant connections the can be output to select an alternate data stream When an LFIx
66. e serial data inputs are ignored When LPENx is LOW the LPENA LPENB LPENC LPEND Notes internal serial loop back function is disabled 4 3 Level Select inputs are used for static configuration These are ternary inputs that make use of logic levels of LOW MID and HIGH The LOW level is usually implemented by not connecting the input left floating which allows it to self bias to the proper level 5 See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface Document 38 02097 Rev B LVTTL Input implemented by direct connection to Vgg ground The HIGH level is usually implemented by direct connection to power The MID level is usually Page 10 of 44 Feedback Ed gt rE CYPRESS RFORM Pin Definitions continued CYV15G0404DXB Quad HOTLink Il Transceiver CYV15G0404DXB Device Configura tion and Control Bus Name Characteristics Signal Description LFIA LVTTL Output Link Fault Indication Output LFIx is an output status indicator signal LFIx is the LFIB asynchronous logical OR of five internal conditions LFIx is asserted LOW when any of these condi LFIC tions are true LFID m Received serial data rate outside expected range m Analog amplitude below expected levels m Transition density lower than expected m Receive channel disabled m ULCx is LOW m
67. ection of the selected framing character To reduce the impact on external circuits that use the recovered clock the clock period is not stretched by more than two bit periods in any one clock cycle When operated with a character rate output clock the output of properly framed characters may be delayed by up to nine character clock cycles from the detection of the selected framing character When operated with a half character rate output clock the output of properly framed characters may be delayed by up to 14 character clock cycles from the detection of the framing character When RFMODEx 1 0 10 the Cypress Mode Multi Byte framer is selected The required detection of multiple framing characters makes the associated link much more robust to incorrect framing due to aliased SYNC characters in the data stream In this mode the framer does not adjust the character clock boundary but instead aligns the character to the already recovered character clock This ensures that the recovered clock does not contain any significant phase changes or hops during normal operation or framing and allows the recovered clock to be replicated and distributed to other external circuits or components using PLL based clock distribution elements In this framing mode the character boundaries are only adjusted if the selected framing character is detected at least twice within a span of 50 bits with both instances on identical 10 bit character boundaries When
68. elationship to the REFCLKxx input 36 TXERRx is synchronous to RXCLKx only when RXCLKx is selected as REFCLK Receive Interface t Read Timing REFCLK REFCLKx Selected tREFH tREFL half rate RXCLKx REFCLKx tRREFDA tRREFDA RREFDW tRREFDW REFxDV tREFxDV RXCLKx Note 37 Receive Interface Recovered Glock selected RXRATEx 0 RXCLKx RXCLKx RXDx 7 0 tRXDV RXSTx 2 0 QC X lt lt lt tRxDV Document 38 02097 Rev B Page 32 of 44 Feedback Cypress CYV15G0404DXB PERFORM Switching Waveforms for the CYV15G0404DXB HOTLink II Receiver Receive Interface Read Timing Recovered Clock selected 1 RXCLKx RXCLKx RXDx 7 0 RXSTx 2 0 Note 37 When operated with half rate REFCLKx the setup and hold specifications for data relative to RXCLKx are relative to both rising and falling edges of the respective clock output Bus Configuration Write Timing ADDR 3 0 DATA 7 0 Document 38 02097 Rev Page 33 of 44 Feedback CYPRESS CYV15G0404DXB PERFORM Table 11 Package Coordinate Signal Allocation Signal Signal Signal Signal Signal
69. ent state of the BIST state machine If the number of detected errors ever exceeds the number of valid matches by greater than 16 the state machine is forced to the WAIT_FOR_BIST state where it monitors the receive path for the first character of the next BIST sequence 00 0 Also if the Elasticity Buffer ever hits an overflow underflow condition the status is forced to the BIST START until the buffer is re centered approximately nine character periods To ensure compatibility between the source and destination systems when operating in BIST modes the sending and receiving ends of the link must use the same receive clock configuration Device Configuration and Control Interface The CYP V 15G0404DX is highly configurable through the configuration interface The configuration interface allows the device to be configured globally or allows each channel to be configured independently Table 9 lists the configuration latches within the device including the initialization value of the latches upon the assertion of RESET Table 10 shows how the latches are mapped in the device Each row in the Table 10 maps to a 8 bit latch bank There are 16 such write only latch banks When WREN 0 the logic value in the DATA 7 0 is latched to the latch bank specified by the values ADDR 3 0 The second column of Table 10 specifies the channels associated with the corre sponding latch bank For example the first three latch banks 0 1 and 2 consist
70. er generated by the LFSR and indicates compare errors and BIST status at the RXSTx 2 0 bits of the Output Register When BIST is first recognized as being enabled in the Receiver the LFSR is preset to the BIST loop start code of D0 0 This code D0 0 is sent only once per BIST loop The status of the BIST progress and any character mismatches are presented on the RXSTx 2 0 status outputs 10 The standard definition of a Comma contains only seven bits However since all valid Comma characters within the 8B 10B character set also have the eighth bit as an inversion of the seventh bit the compare pattern is extended to a full eight bits to reduce the possibility of a framing error Document 38 02097 Rev B Page 17 of 44 Feedback CYPRESS PERFORM Code rule violations or running disparity errors that occur as part of the BIST loop do not cause an error indication RXSTx 2 0 indicates 010b or 100b for one character period per BIST loop to indicate loop completion This status can be used to check test pattern progress These same status values are presented when the decoder is bypassed and BIST is enabled on a receive channel The specific status reported by the BIST state machine are listed in Table 11 These same codes are reported on the receive status outputs The specific patterns checked by each receiver are described in detail in the Cypress application note HOTLink Built In Self Test The sequence com
71. er is encoded as data a special character code or replaced with other special character codes See Table 3 for details 1 a one TXCTA 1 0 TXCTB 1 0 TXCTC 1 0 TXCTD 1 0 TXCLKxT or REFCLKxf 2 LVTTL Output synchronous to REFCLKx1 BI synchronous to Transmit Path Error TXERRx is asserted HIGH to indicate detection of a transmit phase align buffer underflow or overflow If an underflow or overflow condition is detected TXERRx for the channel in error is asserted HIGH and remains asserted until either a word sync sequence is transmitted on that channel or the transmit phase align buffer is recentered with the PABRSTx latch through the device configu ration interface When TXBISTx 0 the BIST progress is presented on the associated TXERRx output The TXERRx signal pulses HIGH for one transmit character clock period to indicate a pass through the BIST sequence once every 511 TXERRA TXERRB TXERRC TXERRD RXCLKx when selected as REFCLKx asynchronous t transmit chann enable disabl asynchronous to loss or return of REFCLKx Differential LVPECL or 527 depending on RXCKSELx character times If RXCKSELx character pulse occurs every 527 character times If RXCKSELx 0 a one character pulse occurs every 511 character times TXERRx is also asserted HIGH when any of these conditions is true m The TXPLL for the associated channel is powered down This occurs when OE2x a
72. er outputs C2 7 if K28 5 is received with RD otherwise K28 5 is decoded as 5 0 or C1 7 48 C4 7 Transmit a deliberate code rule violation to indicate a Running Disparity violation The receiver only outputs this Special Character if the Transmission Character being decoded is found in the tables but Running Disparity does not match This might indicate that an error occurred in a prior byte Document 38 02097 Rev B Page 42 of 44 Feedback 55 PERFORM Ordering Information CYV15G0404DXB Speed Ordering Code Package Name Package Type sg be Standard CYV15G0404DXB BGC BL256 256 Ball Thermally Enhanced Ball Grid Array Commercial Standard CYV15G0404DXB BGI BL256 256 Ball Thermally Enhanced Ball Grid Array Industrial Package Diagram 256 Lead L2 Ball Grid Array 27 x 27 x 1 57 mm BL256 0 15 C BOTTOM VIEW BALL SIDE 0 30 Q C A 24 13 CORNER LD 60 75 0 15 256X VIEW 5 0 20 4x pA 27 00 0 13 CORNER LD 1 L E _ _ A L L B 1 57 0 175 0 97 REE L L 10 15 Torr r nine 26 2 0 15 SEATING PLANE SIDE VIEW Document 38 02097 Rev B 20 18 16 14 12 19 17 15 15 1
73. he clock boundaries are not adjusted and COMDETx may be asserted during the rising edge of RXCLKx if an odd number of characters were received following the initial framing Receive Status Bits When the 10B 8B decoder is enabled each character presented at the output register includes three associated status bits These bits are used to identify m f the contents of the data bus are valid The type of character present The state of receive BIST operations Character violations These conditions often overlap for example a valid data character received with incorrect running disparity is not reported as a valid data character It is instead reported as a decoder violation of some specific type This implies a hierarchy or priority level to the various status bit combinations The hierarchy and value of each status are listed in Table 11 A second status mapping listed in Table 11 is used when the receive channel is configured for BIST operation This status is used to report receive BIST status and progress BIST Status State Machine When a receive path is enabled to look for and compare the received data stream with the BIST pattern the RXSTx 2 0 bits identify the present state of the BIST compare operation The BIST state machine has multiple states as shown in Figure 2 and Table 11 When the receive PLL detects an out of lock condition the BIST state is forced to the Start of BIST state regardless of the pres
74. in Table 4 Table 4 Operating Speed Settings SPDSELx TXRATE Frequency LOW 1 reserved 195 400 0 19 5 40 MID Open 1 20 40 400 800 0 40 80 HIGH 1 40 75 800 1500 0 80 150 Page 14 of 44 Feedback CYPRESS PERFORM REFCLKx inputs are differential inputs with each input internally biased to 1 4V If the REFCLKx input is connected to a TTL LVTTL or LVCMOS clock source the input signal is recognized when it passes through the internally biased reference point When driven by a single ended TTL LVTTL or LVCMOS clock source connect the clock source to either the true or complement REFCLKx input and leave the alternate REFCLKx input open floating When both the REFCLKx and REFCLKx inputs are connected the clock source must be a differential clock This can either be a differential LVPECL clock that is DC or AC coupled or a differential LVTTL or LVCMOS clock By connecting the REFCLKx input to an external voltage source it is possible to adjust the reference point of the REFCLKx input for alternate logic levels When doing so ensure that the input differential crossing point remains within the parametric range supported by the input Serial Output Drivers The serial output interface drivers use differential Current Mode Logic CML drivers to provide source matched drivers for trans mission lines These drivers accept data from the tran
75. indication is detected external logic can toggle selection of the associated INx1 and INx2 input through the associated INSELx input When a port switch takes place it is necessary for the receive PLL for that channel to reacquire the new serial stream and frame to the incoming character boundaries Reclocker The CYV15G0404DXB contains a reclocker mode on each receive channel that can be independently enabled and disabled When the reclocker mode is enabled by RCLKENXx the received serial data is reclocked and transmitted through the enabled differential serial outputs of the selected channel In the reclocker mode the RXPLL performs clock and data recovery functions on the input serial data stream and the reclocked serial data is routed to the enabled differential serial outputs The serial data is also routed to the deserializer and the deserialized data is presented to the RXDx 7 0 and RXSTA 2 0 parallel data outputs as configured by DECBYPx When the reclocker is enabled the data on the TXDx 7 0 and TXCT 1 0 is ignored and not transmitted through the enabled serial outputs Deserializer Framer Each CDR circuit extracts bits from the associated serial data stream and clocks these bits into the shifter framer at the bit clock rate When enabled the framer examines the data stream looking for one or more COMMA or K28 5 characters at all possible bit positions The location of this character in the data stream determines the charac
76. ion Code The following information describes how the tables are used for both generating valid transmission characters encoding and checking the validity of received transmission characters decoding It also specifies the ordering rules followed when transmitting the bits within a character and the characters within any higher level constructs specified by a standard Transmission Order Within the definition of the 8B 10B transmission code the bit positions of the transmission characters are labeled a b c d e i f g h j Bit is transmitted first followed by bits b d e i f h and j in that order Note that bit i is transmitted between bit e and bit f rather than in alphabetical order Valid and Invalid Transmission Characters The following tables define the valid data characters and valid special characters K characters respectively The tables are used for both generating valid transmission characters and checking the validity of received transmission characters In the tables each valid data byte or special character code entry has two columns that represent two transmission characters The two columns correspond to the current value of the running disparity Running disparity is a binary parameter with either a negative or positive value After powering on the transmitter may assume either a positive or negative value for its initial running disparity Upon trans Page 36 of 44
77. l Signal Signal Signal Signal Signal C04 INSELB LVTTL IN F02 RXDC 7 LVTTL OUT L20 TXDB 6 LVTTL IN C05 VCC POWER 203 TXDC 0 LVTTL IN 01 RXDC 4 LVTTL OUT C06 ULCD LVTTL IN PU 204 RCLKEND LVTTL IN PD Mo2 RXDC 5 LVTTL OUT RCLKENC LVTTL IN PD 003 TXDD 2 LVTTL IN W03 LFID LVTTL OUT M04 TXERRC LVTTL OUT UO4 TXCTD 1 LVTTL IN W04 RXCLKD LVTTL OUT M17 REFCLKB PECL IN 005 W05 VCC POWER M18 REFCLKB PECL IN 006 RXDD 2 LVTTL OUT W06 RXDD 4 LVTTL OUT M19 TXERRB LVTTL OUT 007 RXDD 1 LVTTL OUT 07 RXSTD 1 LVTTL OUT M20 TXCLKB LVTTL IN PD 008 GND GROUND W08 GND GROUND NO1 GND GROUND 009 TXCTA 1 LVTTL IN wog ADDR 3 LVTTL IN PU N02 GND GROUND U10 ADDR 0 LVTTL IN PU W10 ADDR 1 LVTTL IN PU N03 GND GROUND U11 REFCLKD PECL IN W11 RXCLKA LVTTL OUT N04 GND GROUND U12 TXDA 1 LVTTL IN W12 TXERRA LVTTL OUT N17 GND GROUND U13 GND GROUND W13 GND GROUND N18 GND GROUND U14 TXDA 4 LVTTL IN W14 TXDA 2 LVTTL IN N19 GND GROUND 015 TXCTA O LVTTL IN W15 TXDA 6 LVTTL IN N20 GND GROUND U16 W16 RXDC 1 LVTTL OUT U17 RXDA 2 LVTTL OUT W17 LFIA LVTTL OUT P02 RXDC 0 LVTTL OUT U18 TXCTB O LVTTL IN W18 REFCLKA PECL IN RXSTC O LVTTL OUT U19 RXSTA 2 LVTTL OUT W19 RXDA 4 LVTTL OUT P04 RXSTC 1 LVTTL OUT U20 RXSTA 1 LVTTL OUT W20 RXDA 1 LVTTL OUT P17 TXDBI 5 LVTTL IN V01 TXDD 3 LVTTL I
78. latch bank for the target channel May be performed using a global operation if the application permits it Optional step if the default settings match the desired configuration Set the static transmitter latch bank for the target channel May be performed using a global operation if the application permits it Optional step if the default settings match the desired configuration wo Table 10 Device Control Latch Configuration Table CYV15G0404DXB 4 Set the dynamic bank of latches for the target channel Enable the Receive PLLs and transmit channels May be performed using a global operation if the application permits it Required step 5 Reset the Phase Alignment Buffer for the target channel May be performed using a global operation if the application permits it Optional if phase align buffer is bypassed When a receive channel is configured with the decoder bypassed and the receive clock selected as recovered clock in half rate mode DECBYPx 0 RXRATEx 0 RXCKSELx 0 the channel cannot be dynamically reconfigured to enable the decoder with RXCLKx selected as the REFCLKx DECBYPx 1 RXCKSELx 1 If such a change is desired a global reset should be performed and all channels should be reconfigured to the desired settings ADDR Channel Type DATA7 DATAG 5 DATA4 DATA3 DATA2 DATA1 DATAO
79. le initialization value of the RFENx latch 1 RFENx selects if the receiver framer is RFENB enabled or disabled When RFENXx 1 the associated channel s framer is enabled to frame per the presently RFENC enabled framing mode and selected framing character When RFENXx 0 the associated channel s framer is RFEND disabled and no received bits alters the frame offset RXPLLPDA Receive Channel Enable The initialization value of the RXPLLPDx latch 0 RXPLLPDx selects if the RXPLLPDB associated receive channel is enabled or powered down When RXPLLPDx 0 the associated PLL and RXPLLPDC analog circuitry is powered down When RXPLLPDx 1 the associated PLL and analog circuitry is enabled RXPLLPDD RXBISTA Receive Bist Disabled The initialization value of the RXBISTx latch 2 1 RXBISTx selects if receive BIST is RXBISTB disabled or enabled When RXBISTx 1 the receiver BIST function is disabled When RXBISTx 0 the RXBISTC receive BIST function is enabled RXBISTD TXBISTA Transmit Bist Disabled The initialization value of the TXBISTx latch 1 TXBISTx selects if the transmit BIST TXBISTB is disabled or enabled When TXBISTx 1 the transmit BIST function is disabled When TXBISTx 0 the TXBISTC transmit BIST function is enabled TXBISTD OE2A Secondary Differential Serial Data Output Driver Enable The initialization value of the OE2x latch 0 OE2B OE2Xx selects if the OUT2 secondary differential output drivers are enabled or disabled
80. locker lt 5 0 Serial Links gt 5 10 10 Serial Links gt Cable Connections Cypress Semiconductor Corporation Document 38 02097 Rev B 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised December 14 2007 Feedback __ Ed lt CYPRESS PERFORM The CYV15G0404DXB satisfies the SMPTE 259M and SMPTE 292M compliance according to SMPTE EG34 1999 Pathological Test Requirements As a second generation HOTLink device the CYV15G0404DXB extends the HOTLink family with enhanced levels of integration and faster data rates while maintaining serial link compatibility data command and BIST with other HOTLink devices The transmit TX section of the CYV15G0404DXB Quad HOTLink II consists of four independent byte wide channels Each channel accepts either 8 bit data characters or preencoded 10 bit transmission characters Data characters may be passed from the transmit input register to an integrated 8B 10B Encoder to improve their serial transmission characteristics These encoded characters are then serialized and output from dual Positive ECL PECL compatible differential transmission line drivers at a bit rate of either 10 or 20 times the input reference clock for that channel The receive RX section of the CYV15G0404DXB Quad HOTLink 11 consists of four independent byte wide channels Each channel accepts a serial bit strea
81. lost Output Short Circuit Current Vout ovla Vec 33 20 100 lozL High Z Output Leakage Current Vout OV Voc 20 20 LVTTL compatible Inputs Viet Input HIGH Voltage 2 0 Voc 0 3 V Input LOW Voltage 0 5 0 8 V liar Input HIGH Current REFCLKx Input 1 5 Other Inputs Vin Voc 40 Input LOW Current REFCLKx Input 0 0V 1 5 Other Inputs 0 0V 40 Input HIGH Current with internal pull down Vij 200 li PUT Input LOW Current with internal pull up Vin 0 0V 200 LVDIFF Inputs REFCLKx Vpierl 3l Input Differential Voltage 400 Vcc mV ViHHP Highest Input HIGH Voltage 1 2 Vcc V Lowest Input LOW voltage 0 0 2 V Mode Range 1 0 12 V 3 Level Inputs Three Level Input HIGH Voltage Min lt Vcc lt Max 0 87 Voc Voc V VIMM Three Level Input MID Voltage Min lt Voc lt 0 47 Voc 0 53 V Three Level Input LOW Voltage Min lt Voc lt Max 0 0 0 13 Voc V Input HIGH Current Vin Voc 200 Input MID current Vin 2 50 50 Input LOW current Vin GND 200 Notes 12 Tested one output at a time output shorted for less than one second less than 10 duty cycle 13 This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic 1 or logic 0 A logic 1 exists when the tru
82. m from one of two PECL compatible differential line receivers and using a completely integrated Clock and Data Recovery PLL recovers the timing information necessary for data reconstruction Each recovered bit stream is deserialized and framed into characters CYV15G0404DXB 8B 10B decoded and checked for transmission errors Recovered decoded characters are then written to an internal elasticity buffer and presented to the destination host system The integrated 8B 10B encoder or decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface The parallel IO interface may be configured for numerous forms of clocking to provide the highest flexibility in system archi tecture In addition to clocking the transmit path with a local reference clock the receive interface may also be configured to present data relative to a recovered clock or to a local reference clock Each transmit and receive channel contains an independent BIST pattern generator and checker This BIST hardware allows at speed testing of the high speed serial data paths in each transmit and receive section and across the interconnecting links The CYV15G0404DXB is ideal for port applications where different data rates and serial interface standards are necessary for each channel Some applications include multi format routers and switchers I 5 o 5 8 be a Ge Ne fF o xr me o m
83. n the value of RXRATEx and operates at the same rate as REFCLKx Device Control Si gnals RESET LVTTL Input asynchronous internal pull up Asynchronous Device Reset RESET initializes all state machines counters and configuration latches in the device to a known state RESET must be asserted LOW for a minimum pulse width When the reset is removed all state machines counters and configuration latches are at an initial state As per the JTAG specifications the device RESET cannot reset the JTAG controller Therefore the JTAG controller has to be reset separately Refer to JTAG Support on page 23 for the methods to reset the JTAG state machine See Table 9 for the initialize values of the device configu ration latches Document 38 02097 Rev B Page 9 of 44 Feedback Pin Definitions continued Characteristics LVTTL Input internal pull up Signal Description Level Detect Transition Density Enable When LDTDEN is HIGH the signal level detector range controller and transition density detector are all enabled to determine if the tracks REFCLKx or the selected input serial data stream If the signal level detector range controller or transition density detector are out of their respective limits while LDTDEN is HIGH the RXPLL locks to until such a time they become valid The SDASEL A D 1 0 configure the trip level of the signal level dete
84. nd 1 for a given channel are simultaneous disabled by setting OE2x 0 and OE1x 0 m The absence of the REFCLKxz signal LVTTL clock source connect the clock source to either the true or complement REFCLKx input and leave the alternate REFCLKx input open floating When driven Reference Clock REFCLKx clock inputs are used as the timing references for the transmit and receive PLLs These input clocks may also be selected to clock the transmit and receive parallel interfaces When driven by a single ended LVCMOS or by an LVPECL clock source the clock must be a differential clock using both inputs Transmit Path Clock Signals or single ended LVTTL input clock Transmit Path Input Clock When configuration latch TXCKSELx 0 the associated TXCLKx input is selected as the character rate input clock for the REFCLKA REFCLKB REFCLKC REFCLKD TXCLKA TXCLKB LVTTL Clock Input internal pull down TXDx 7 0 and TXCTx 1 0 inputs In this mode the TXCLKx input must be frequency coherent to its associated TXCLKOx output clock but may be offset in phase by any amount Once initialized TXCLKx is allowed to drift in phase as much as 180 degrees If the input phase of TXCLKx drifts beyond the handling capacity of the phase align buffer TXERRx is asserted to indicate the loss of data and remains asserted until the phase align buffer is initialized The phase of the TXCLKx input clock relative to its associa
85. nt ATE load configurations and forcing functions This figure is for reference only 19 The LVTTL switching threshold is 1 4V All timing references are made relative to where the signal edges cross the threshold voltage Document 38 02097 Rev Page 27 of 44 Feedback gt CYPRESS CYV15G0404DXB PERFORM CYV15G0404DXB AC Electrical Characteristics Parameter Description Min Max Unit CYV15G0404DXB Transmitter LVTTL Switching Characteristics Over the Operating Range frs TXCLKx Clock Cycle Frequency 19 5 150 MHz trxcLK TXCLKx Period 1 frs 6 66 51 28 ns trxci kl TXCLKx HIGH Time 2 2 ns TXCLKx LOW Time 2 2 ns 22 TXCLKx Rise Time 0 2 1 7 ns 2227 22 TXCLKx Fall Time 0 2 1 7 ns trxps Transmit Data Set up Time to TXCLKxT TXCKSELx z 0 2 2 ns trxpH Transmit Data Hold Time from TXCLKxT TXCKSELx z 0 1 0 ns tros TXCLKOXx Clock Frequency 1x or 2x REFCLKx Frequency 19 5 150 MHz trxcLKo TXCLKOXx 1 6 66 51 28 ns trxcLKOD TXCLKO Duty Cycle centered at 60 HIGH time 1 9 0 ns CYV15G0404DXB Receiver LVTTL Switching Characteristics Over the Operating Range fas RXCLKx Clock Output Frequency 9 75 150 MHz tRxCLKP Period 1 fns 6 66 102 56 ns RXCLKD RXCLKxx Duty Cycle Centered at 50 Full Rate and Half Rate when 1 0 1 0 ns RXCKSELx 0
86. odules The common mode tolerance of these line receivers accommodates a wide range of signal termination voltages Each receiver provides internal DC restoration to the center of the receiver s common mode range for AC coupled signals Notes CYV15G0404DXB The local internal loopback LPENXx allows the serial transmit data outputs to be routed internally back to the clock and data recovery circuit associated with each channel When configured for local loopback the associated transmit serial driver outputs are forced to output a differential logic 1 This prevents local diagnostic patterns from being broadcast to attached remote receivers Signal Detect Link Fault Each selected line receiver that is routed to the clock and data recovery PLL is simultaneously monitored for m Analog amplitude above amplitude level selected by SDASELx m Transition density above the specified limit m Range controls report the received data stream inside normal frequency range 1500 ppm m Receive channel enabled m The presence of a reference clock m ULCx is not asserted All of these conditions must be valid for the signal detect block to indicate a valid signal is present This status is presented on the Link Fault Indicator output associated with each receive channel which changes synchronous to the selected receive interface clock Analog Amplitude While most signal monitors are based on fixed constants the analog am
87. of 44 Feedback CYPRESS CYV15G0404DXB Table 14 Valid Data Characters TXCTx 0 0 RXSTx 2 0 000 continued DE Bits Current RD Current RD Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj Name EDCBA abcdei fghj abcdei fghj D0 4 100 00000 100111 0010 011000 1101 D0 5 101 00000 100111 1010 011000 1010 D1 4 100 00001 011101 0010 100010 1101 D1 5 101 00001 011101 1010 100010 1010 D2 4 100 00010 101101 0010 010010 1101 D2 5 101 00010 101101 1010 010010 1010 D3 4 100 00011 110001 1101 110001 0010 D3 5 101 00011 110001 1010 110001 1010 D4 4 100 00100 110101 0010 001010 1101 D4 5 101 00100 110101 1010 001010 1010 D5 4 100 00101 101001 1101 101001 0010 05 5 101 00101 101001 1010 101001 1010 26 4 100 00110 011001 1101 011001 0010 26 5 101 00110 011001 1010 011001 1010 27 4 100 00111 111000 1101 000111 0010 101 00111 111000 1010 000111 1010 28 4 100 01000 111001 0010 000110 1101 28 5 101 01000 111001 1010 000110 1010 29 4 100 01001 100101 1101 100101 0010 29 5 101 01001 100101 1010 100101 1010 010 4 100 01010 010101 1101 010101 0010 010 5 101 01010 010101 1010 010101 1010 011 4 100 01011 110100 1101 110100 0010 01 5 101 01011 110100 1010 110100 1010 012 4 100 01100 001101 1101 001101
88. of X3 230 EOF frame delimiters wherein the second data byte is determined by the Current RD For example to send EOFdt the controller could issue the sequence 2 1 021 4 D21 4 D21 4 and the HOTLink Transmitter sends either K28 5 D21 4 D21 4 D21 4 or 28 5 021 5 D21 4 D21 4 based on Current RD Likewise to send EOFati the controller could issue the sequence C2 1 D10 4 D21 4 D21 4 and the HOTLink Transmitter sends either K28 5 D10 4 D21 4 021 4 or K28 5 D10 5 D21 4 D21 4 based on Current RD The receiver never outputs this Special Character since K28 5 is decoded as C5 0 C1 7 or C2 7 and the subsequent bytes are decoded as data 45 C0 7 Transmit a deliberate code rule violation The code chosen for this function follows the normal Running Disparity rules Transmission of this Special Character has the same effect as asserting TXSVS HIGH The receiver only outputs this Special Character if the Transmission Character being decoded is not found in the tables 46 C1 7 Transmit Negative K28 5 28 5 disregarding Current RD The receiver only outputs this Special Character if K28 5 is received with the wrong running disparity The receiver outputs C1 7 if K28 5 is received with RD otherwise K28 5 is decoded as C5 0 or C27 47 2 7 Transmit Positive K28 5 28 5 disregarding Current RD The receiver only outputs this Special Character if K28 5 is received with the wrong running disparity The receiv
89. of configuration bits for channel A The latch banks Page 19 of 44 Feedback Er 12 13 and 14 consist of global configuration bits and the last latch bank 15 is the mask latch bank that can be configured to perform bit by bit configuration Global Enable Function The global enable function controlled by the GLENx bits is a feature that is used to reduce the number of write operations needed to setup the latch banks This function is beneficial in systems that use a common configuration in multiple channels GLENXx bit is present in bit 0 of latch banks 0 through 11 only Its default value 1 enables the global update of the latch bank s contents Setting the GLENx bit to 0 disables this functionality Latch Banks 12 13 and 14 load values in the related latch banks in a global manner A write operation to latch bank 12 could do a global write to latch banks 0 3 6 and 9 depending on the value of GLENXx in these latch banks latch bank 13 could do a global write to latch banks 1 4 7 and 10 and latch banks 14 could do a global write to latch banks 2 5 8 and 11 The GLENx bit cannot be modified by a global write operation Force Global Enable Function FGLENXx forces the global update of the target latch banks but does not change the contents of the GLENx bits If FGLENx 1 for the associated global channel FGLENx forces the global update of the target latch banks Mask Function
90. pared by the CYV15G0404DXB is identical to that in the CY7B933 CY7C924DX and CYP V 15G0401 DXB allowing interoperable systems to be built when used at compatible serial signaling rates If the number of invalid characters received ever exceeds the number of valid characters by 16 the receive BIST state machine aborts the compare operations and resets the LFSR to the 00 0 state to look for the start of the BIST sequence again When Receive BIST is enabled on a channel do not enable the low latency framer The BIST sequence contains an aliased K28 5 framing character which causes the receiver to update its character boundaries incorrectly The receive BIST state machine requires the characters to be correctly framed for it to detect the BIST sequence If the low latency framer is enabled the framer misaligns to an aliased SYNC character within the BIST sequence If the alternate multi byte framer is enabled and the receiver outputs are clocked relative to a recovered clock it is generally necessary to frame the receiver before BIST is enabled If the receive outputs are clocked relative to REFCLKx the transmitter precedes every 511 character BIST sequence with a 16 character word sync sequence A device reset RESET sampled LOW presets the BIST enable latches to disable BIST on all channels Receive Elasticity Buffer Each receive channel contains an elasticity buffer that is designed to support multiple clocking modes These b
91. plitude level detection is adjustable to allow operation with highly attenuated signals or in high noise environments The analog amplitude level detection is set by the SDASELx latch via device configuration interface The SDASELx latch sets the trip point for the detection of a valid signal at one of three levels as listed in Table 5 This control input affects the analog monitors for all receive channels Table 5 Analog Amplitude Detect Valid Signal Levels SDASEL Typical Signal with Peak Amplitudes Above 00 Analog Signal Detector is disabled 01 140 mV p p differential 10 280 mV p p differential 11 420 mV p p differential The analog signal detect monitors are active for the line receiver as selected by the associated INSELx input When configured for local loopback no input receivers are selected and the LFIx output for each channel reports only the receive VCO frequency out of range and transition density status of the associated transmit signal When local loopback is active the associated analog signal detect monitor is disabled 8 When a disabled transmit channel i e both outputs disabled is re enabled the data on the serial outputs may not meet all timing specifications for up to 250 ms 9 The peak amplitudes listed in this table are for typical waveforms that have generally 3 4 transitions for every ten bits In a worse case environment the signals may have a sign wave appearance highest tran
92. r When the encoder is enabled the TXCTx 1 0 bits are inter preted along with the associated TXDx 7 0 character to generate a specific 10 bit transmission character Phase Align Buffer Data from each input register is passed to the associated phase align buffer when the 7 0 and TXCTx 1 0 input registers are clocked using TXCLKx TXCKSELx 0 and TXRATEx 0 When the TXDx 7 0 and 1 0 input registers are clocked using REFCLKx TXCKSELx 1 and REFCLKxz is a full rate clock the associated phase alignment buffer in the transmit path is bypassed These buffers are used to absorb clock phase differences between the TXCLKx input clock and the internal character clock for that channel Page 12 of 44 Feedback Once initialized TXCLKx is allowed to drift in phase as much as 180 degrees If the input phase of TXCLKx drifts beyond the handling capacity of the phase align buffer TXERRx is asserted to indicate the loss of data and remains asserted until the phase align buffer is initialized The phase of the TXCLKx relative to its associated internal character rate clock is initialized when the configuration latch PABRSTx is written as 0 When the associated TXERRx is deasserted the phase align buffer is initialized and input characters are correctly captured Table 1 Input Register Bit Assignments Signal Name Unencoded Encoded TXDx 0 LSB DINx 0 TXDx 0 TXDx 1
93. r 298 gg og 98 CYV15G0404DXB Transceiver Logic Block Diagram TXDC 7 0 TXCTC 1 0 RXDC 7 0 RXSTC 2 0 TXDDJ 7 0 TXCTD 1 0 RXDD 7 0 RXSTD 2 0 a REFCLKC lt Phase Align Buffer Elasticity Buffer Phase Align Buffer Elasticity Buffer Phase Align Buffer Elasticity Buffer Phase Align Buffer Elasticity Buffer Encoder 8B 10B Decoder 8B 10B Framer Encoder 8B 10B Decoder 8B 10B Framer Encoder 8B 10B Decoder 8B 10B Framer Encoder 8B 10B Decoder 8B 10B Framer Serializer Deserializer RX Serializer Deserializer Serializer Deserializer Serializer Deserializer RX 58 Ha Sa Ha HA lt lt lt lt m m ad aao 2 55 55 55 5 5 Document 38 02097 Rev Page 2 of 44 Feedback 55 PERFORM CYV15G0404DXB
94. r composed of the bits H G and F in that order When c is set to K xx and y are derived by comparing the encoded bit patterns of the Special Character to those patterns derived from encoded valid data bytes and selecting the names of the patterns most similar to the encoded bit patterns of the special character Using these conventions the transmission character used for the examples above is referred to by the name D5 2 The special character K29 7 is so named because the first six bits abcdei of this character make up a bit pattern similar to that resulting from the encoding of the unencoded 11101 pattern 29 and because the second four bits fghj make up a bit pattern similar to that resulting from the encoding of the unencoded 111 pattern 7 Note This definition of the 10 bit transmission code is based on the following references which describe the same 10 bit trans mission code m Widmer and Franaszek A DC Balanced Parti tioned Block 8B 10B Transmission Code IBM Journal of Research and Development 27 No 5 440 451 September 1983 m U S Patent 4 486 739 Peter Franaszek and Albert X Widmer Byte Oriented DC Balanced 0 4 8B 10B Partitioned Block Transmission Code December 4 1984 Fibre Channel Physical and Signaling Interface ANS X3 230 1994 ANSI FC PH Standard m IBM Enterprise Systems Architecture 390 ESCON I O Interface document number 5 22 7202 8B 10B Transmiss
95. r is bypassed through the configuration interface When bypassed raw 10 bit characters are passed through the receiver and presented at the RXDx 7 0 and the RXSTA 1 0 outputs as 10 bit wide characters When the decoder is enabled by setting DECBYPx 1 through the configuration interface the 10 bit transmission characters are decoded using Table 14 and Table 15 Received Special characters are decoded using Table 15 The columns used in Table 15 are determined by the DECMODEX latch through the device configuration interface When DECMODEx 0 the ALTERNATE table is used and when DECMODEx 1 the CYPRESS table is used Receive BIST Operation The receiver channel contains an internal pattern checker that can be used to validate both device and link operation These pattern checkers are enabled by the associated RXBISTx latch using the device configuration interface When enabled a register in the associated receive channel becomes a signature pattern generator and checker by logically converting to a Linear Feedback Shift Register LFSR This LFSR generates a 511 character or 526 character sequence that includes all data and special character codes including the explicit violation symbols This provides a predictable yet pseudo random sequence that can be matched to an identical LFSR in the attached transmitters When synchronized with the received data stream the associated Receiver checks each character in the Decoder with each charact
96. ransmission character in which the error occurred Table 12 shows an example of this behavior RD Character RD Character RD Character RD Transmitted data character 021 1 010 2 23 5 Transmitted bit stream 101010 1001 010101 0101 111010 1010 Bit stream after error 1010101011 010101 0101 111010 1010 Decoded data character D21 0 D10 2 Code Violation Document 38 02097 Rev B Page 37 of 44 Feedback S CYPRESS CYV15G0404DXB PERFORM Table 14 Valid Data Characters TXCTx 0 0 RXSTx 2 0 000 cus Bits Current RD Current RD Bate Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj Name EDCBA abcdei fghj abcdei fghj D0 0 000 00000 100111 0100 011000 1011 0 1 001 00000 100111 1001 011000 1001 21 0 000 00001 011101 0100 100010 1011 21 1 001 00001 011101 1001 100010 1001 02 0 000 00010 101101 0100 010010 1011 02 1
97. rity K28 5 as deter mined by the current running disparity and the 8B 10B coding rules The disparity of the second and third K28 5 characters in this sequence are reversed from what normal 8B 10B coding rules would generate The remaining K28 5 characters in the sequence follow all 8B 10B coding rules The disparity of the generated K28 5 characters in this sequence follow a pattern of either Of The generation of this sequence once started cannot be stopped until all 16 characters have been sent The content of the associated input registers are ignored for the duration of this Document 38 02097 Rev B CYV15G0404DXB sequence At the end of this sequence if the TXCTx 1 0 11 condition is sampled again the sequence restarts and remains uninterruptible for the following 15 character clocks Transmit BIST Each transmit channel contains an internal pattern generator that can be used to validate both the link and device operation These generators are enabled by the associated TXBISTx latch through the device configuration interface When enabled a register in the associated transmit channel becomes a signature pattern generator by logically converting to a Linear Feedback Shift Register LFSR This LFSR generates a 511 character or 526 character sequence that includes all data and special character codes including the explicit violation symbols This provides
98. ry testing only Leave this input as a NO Factory Test 3 TMENG input is for factory testing only Leave this input as a NO Primary Differential Serial Data Output The OUTx1 PECL compatible CML outputs 3 3V referenced are capable of driving terminated transmission lines or standard fiber optic transmitter modules and must be AC coupled for PECL Secondary Differential Serial Data Output The OUTx2 PECL compatible CML outputs 3 3V referenced are capable of driving terminated transmission lines or standard fiber optic transmitter modules and must be AC coupled for PECL compatible connections Primary Differential Serial Data Input The input accepts the serial data stream for deserialization and decoding The INx1 serial stream is passed to the receive CDR circuit to extract the data content when INSELx HIGH JTAG Interface SCANEN2 LVTTL input internal pull down CONNECT or GND only LVTTL input internal pull down CONNECT or GND only Analog OUTA1 CML Differential OUTB1 Output OUTC1 OUTD1 compatible connections OUTA2 CML Differential OUTB2 Output OUTC2 OUTD2 INA1 Differential Input INB1 INC1 IND1 INA2 Differential Input INB2 INC2 IND2 Secondary Differential Serial Data Input The INx2 input accepts the serial data stream for deserialization and decoding The INx2 serial stream is passed to the receiver CDR circuit to extract the data content when INSELx L
99. s The bit usage and mapping of the external signals to the raw 10B transmission character is shown in Table 8 Table 8 Decoder Bypass Mode Signal Name Bus Weight 10 Bit Name RXSTx 2 LSB COMDETx RXSTX 1 20 a Rxsmo 2 b RXDx 0 2 RXDx 1 23 d 2 e RXDx 3 25 i RXDx 4 26 f 2 RXDx 6 28 h RXDx 7 MSB 29 j The COMDETx status output operates the same regardless the bit combination selected for character framing by the FRAMCHARx latch COMDETx is HIGH when the character in the output register contains the selected framing character at the proper character boundary and LOW for all other bit combina tions When the low latency framer and half rate receive port clocking are also enabled the framer stretches the recovered clock to the nearest 20 bit boundary such that the rising edge of RXCLKx occurs when COMDETx is present on the associated output bus When the Cypress or alternate mode framer is enabled and half rate receive port clocking is also enabled the output clock is not modified when framing is detected but a single pipeline stage may be added or subtracted from the data stream by the framer logic such that the rising edge of RXCLKx occurs when is present on the associated output bus Document 38 02097 Rev B CYV15G0404DXB This adjustment only occurs when the framer is enabled When the framer is disabled t
100. s Bits CYV15G0404DXB Description 2 0 Priority Receive BIST Status Receive BIST Enabled 000 7 Normal character received The valid Data BIST Data Compare Character compared correctly character on the output bus meets all the formatting requirements of Data characters listed in Table 14 001 7 Special code detected The valid special BIST Command Compare Character compared character on the output bus meets all the correctly formatting requirements of Special Code characters listed in Table 15 but is not the presently selected framing character or a decoder violation indication 010 2 Receive Elasticity buffer underrun overrun BIST Last Good Last Character of BIST sequence error The receive buffer was not able to detected and valid add drop a K28 5 or framing character 011 5 Framing character detected This indicates that a character matching the patterns identified as a framing character as selected by FRAMCHARX was detected The decoded value of this character is present in the associated output bus 100 4 Codeword violation The character on the BIST Last Bad Last Character of BIST sequence output bus is a C0 7 This indicates that the detected invalid received character cannot be decoded into any valid character 101 1 Loss of sync This indicates a PLL Out of Lock BIST Start Receive BIST is enabled on this channel condition but character compares have no
101. sition density with repeating 0101 Signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mV Document 38 02097 Rev B Page 15 of 44 Feedback CYPRESS PERFORM Transition Density The transition detection logic checks for the absence of transi tions spanning greater than six transmission characters 60 bits If no transitions are present in the data received the detection logic for that channel asserts LFIx Range Controls The CDR circuit includes logic to monitor the frequency of the PLL Voltage Controlled Oscillator VCO used to sample the incoming data stream This logic ensures that the VCO operates at or near the rate of the incoming data stream for two primary cases m When the incoming data stream resumes after a time in which it has been missing m When the incoming data stream is outside the acceptable signaling rate range To perform this function the frequency of the RXPLL VCO is periodically compared to the frequency of the REFCLKx input If the VCO is running at a frequency beyond 1500 ppm as defined by the REFCLKx frequency it is periodically forced to the correct frequency as defined by REFCLKx SPDSELx and TXRATEx and then released in an attempt to lock to the input data stream The sampling and relock period of the range control is calculated in the following manner RANGE CONTROL SAMPLING
102. smit shifters They have signal swings equivalent to that of standard PECL drivers and are capable of driving AC coupled optical modules or transmission lines When configured for local loopback LPENx HIGH all enabled serial drivers are configured to drive a static differential logic 1 Transmit Channels Enabled Each driver can be enabled or disabled separately using the device configuration interface When a driver is disabled through the configuration interface it is internally powered down to reduce device power If both serial drivers for a channel are in this disabled state the associated internal logic for that channel is also powered down A device reset RESET sampled LOW disables all output drivers 8 CYV15G0404DXB Receive Data Path Serial Line Receivers Two differential line receivers INx1 and 2 are available on each channel for accepting serial data streams The active serial line receiver on a channel is selected using the associated INSELx input The serial line receiver inputs are differential and can accommodate wire interconnect and filtering losses or trans mission line attenuation greater than 16 dB For normal operation these inputs should receive a signal of at least VlpiFF gt 100 mV or 200 mV peak to peak differential Each Line Receiver can be DC or AC coupled to 3 3V powered fiber optic interface modules any ECL PECL family not limited to 100K PECL or AC coupled to 5V powered optical m
103. ssociated channel is LOW indicating a link fault RXCLKxx is needed In cases when there is an absence of valid data transitions for long period of time or the high gain differential serial inputs INx are left floating When ULCx is HIGH the RXPLL performs Clock and Data Recovery functions on there be brief frequency excursions of the RXCLKx outputs from REFCLKx Serial Rate Select The SPDSELx inputs specify the operating signaling rate range of each channel s transmit and receive PLL Receive Input Selector The INSELx input determines which external serial bit SPDSELA SPDSELB SPDSELC SPDSELD LVTTL Input asynchronous LOW 195 400 MBd MID 400 800 MBd HIGH 800 1500 stream is passed to the receiver s clock and data recovery circuit When INSELx is HIGH the primary differential serial data input INx1 is selected for the associated receive channel When INSELx is LOW the secondary differential serial data input Loop Back Enable The LPENx input enables the internal serial loop back for the associated channel When LPENx is HIGH the transmit serial data from the INSELA INSELB INSELC asynchronous INSELD internal pull down INx2 is selected for the associated receive channel associated channel is internally routed to the associated receive Clock and Data Recovery CDR circuit All enabled serial drivers on the channel are forced to differ ential logic 1 and th
104. t yet commenced This also indicates a PLL Out of Lock condition and Elasticity Buffer overflow underflow conditions 110 6 Running disparity error The character on the BIST Error While comparing characters a mismatch output bus is a C4 7 C1 7 or C2 7 was found in one or more of the decoded character bits 111 3 Reserved BIST Wait The receiver is comparing characters but has not yet found the start of BIST character to enable the LFSR Document 38 02097 Rev B Page 24 of 44 Feedback lt z OE Yt CYPRESS CYV15G0404DXB Receive BIST 14 Detected LOW RX PLL of Lock red BIST START 101 Figure 2 Receive BIST State Machine Monitor Data RXSTx RXSTx BIST_WAIT 111 PERFORM gt Received RXSTx BIST_START 101 u Elasticity Yes Buffer Error Start of BIST Detected Yes RXSTx BIST_DATA_COMPARE 000 BIST_COMMAND_COMPARE 001 RXSTx No Match BIST COMMAND COMPARE 001 Compare Command Next Character RXSTx BIST_DATA_COMPARE 000 Data or Command Mismatch Data No Auto Abort Condition End of BIST State No End of BIST Yes RXSTx BIST_LAST_GOOD 010 State Yes RXSTx BIST_LAST_BAD 100 No RXSTx BIST_ERROR 110 lt Document 38 02097 Re
105. ted REFCLKxt is initialized when the configuration latch align buffer is initialized and input characters are correctly captured TXCLKC TXCLKD PABRSTx is written as 0 When the associated TXERRx is deasserted the phase Notes 2 When REFCLKxt is configured for half rate operation these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx 3 When is configured for half rate operation these outputs are presented relative to both the rising and falling edges of the associated REFCLKxz Document 38 02097 Rev B Page 8 of 44 Feedback Pin Definitions continued CYV15G0404DXB Quad HOTLink Il Transceiver CYV15G0404DXB Name Characteristics Signal Description TXCLKOA LVTTL Output Transmit Clock Output TXCLKOx output clock is synthesized by each channel s TXCLKOB transmit PLL and operates synchronous to the internal transmit character clock TXCLKOC TXCLKOXx operates at either the same frequency as REFCLKx TXRATE 0 or at TXCLKOD twice the frequency of REFCLKx TXRATE 1 The transmit clock outputs have no fixed phase relationship to REFCLKx Receive Path Data and Status Signals RXDA 7 0 LVTTL Output synchronous to the selected RXCLK output or REFCLKx input Parallel Data Output RXDx 7 0 parallel data outputs change relative to the receive interface clock The receive interface clock is selected by the RXC
106. ter boundaries of all following characters Framing Character The CYV15G0404DXB allows selection of different framing characters each channel Two combinations of framing characters are supported to meet the requirements of different interfaces The selection of the framing character is made Page 16 of 44 Feedback CYPRESS PERFORM through the FRAMCHARx latches through the configuration interface The specific bit combinations of these framing characters are listed Table 6 When the specific bit combination of the selected framing character is detected by the framer the bound aries of the characters present in the received data stream are known Table 6 Framing Character Selector FRAMCHARx Bits Detected in Framer Character Name Bits Detected 0 00111110XxI70 11000001 1 28 5 0011111010 28 5 1100000101 The framer each channel operates in one of three different modes Each framer is enabled or disabled using the RFENx latches using the configuration interface When the framer is disabled RFENx 0 no combination of received bits alters the frame information When the low latency framer is selected RFMODEx 1 0 00 the framer operates by stretching the recovered character clock until it aligns with the received character boundaries In this mode the framer starts its alignment process on the first det
107. ters a b c d e i f g h j for encoded 10 bit data There is a correspondence between bit A and bit a B and b C and c D and d E and e F and f G and g and H and h Bits i and j are derived respectively from A B C D E and The bit labeled A in the description of the 8B 10B Transmission Code corresponds to bit 0 in the numbering scheme of the FC 2 specification B corresponds to bit 1 as shown below 2 bit designation 76543210 HOTLink D Q designation 76543210 8 10 bit designation HGFEDCBA To clarify this correspondence the following example shows the conversion from an FC 2 Valid Data Byte to a Transmission Character FC 2 45H Bits 7654 3210 0100 0101 Converted to 8B 10B notation note that the order of bits has been reversed Data Byte Name D5 2 Bits ABCDE FGH 10100 010 Translated to a transmission Character in the 8B 10B Trans mission Code Bits abcdei fghj 101001 0101 Each valid transmission character of the 8B 10B Transmission Code has been given a name using the following convention where is used to show whether the Transmission Character is a Data Character c is set to D and SC D LOW or a special character c is set to K and SC D HIGH When c Document 38 02097 Rev B CYV15G0404DXB is set to D xx is the decimal value of the binary number composed of the bits E D C B and A in that order and the y is the decimal value of the binary numbe
108. the character boundaries are adjusted The recovered character clock remains in the same phasing regardless of character offset RFMODEx 1 0 11 is reserved for test Framing Character Select The initialization value of the FRAMCHARXx latch 1 FRAMCHARx is used to FRAMCHARA FRAMCHARB select the character or portion of a character used for framing of each channel s received data stream When FRAMCHARC FRAMCHARx 1 the framer looks for either disparity of the K28 5 character When 0 the FRAMCHARD _ framer looks for either disparity of the 8 bit Comma characters The specific bit combinations of these framing characters are listed in Table 6 DECMODEA Receiver Decoder Mode Select The initialization value of the DECMODEx latch 1 DECMODEx selects DECMODEB the Decoder Mode used for the associated channel When DECMODEx 1 and decoder is enabled the DECMODEC Cypress Decoding Mode is used When DECMODEx 0 and decoder is enabled the Alternate Decoding DECMODED mode is used When the decoder is enabled DECBYPx 1 the 10 bit transmission characters decoded using Table 14 and Table 15 The column used in the Special Characters Table 15 is determined by the DECMODEX latch DECBYPA Receiver Decoder Bypass The initialization value of the DECBYPx latch 1 DECBYPx selects if the DECBYPB Receiver Decoder is enabled or bypassed When 1 the decoder is enabled and the Decoder DEC
109. the typical differential voltage threshold level is 140 mV RXCLKx and RXCLKx When SDASEL1x 1 0 00 the Analog Signal Detector is disabled When SDASEL1x 1 0 10 the typical differential voltage threshold level is 280 mV When SDASEL1x 1 0 11 the typical differential voltage threshold level is 420 mV Secondary Serial Data Input Signal Detector Amplitude Select The initialization value of the SDASEL2x 1 0 latch 10 SDASEL2x 1 0 selects the trip point for the detection of a valid signal for the INx2 SDASEL2A 1 0 SDASEL2B 1 0 SDASEL2C 1 0 SDASEL2D 1 0 When SDASEL2x 1 0 01 the typical differential voltage threshold level is 140 mV Secondary Differential Serial Data Inputs When SDASEL2x 1 0 00 the Analog Signal Detector is disabled When SDASEL2x 1 0 10 the typical p p differential voltage threshold level is 280 mV When SDASEL2x 1 0 11 the typical differential voltage threshold level is 420 mV Transmit Encoder Bypassed The initialization value of the ENCBYPx latch 1 ENCBYPx selects if the Transmit Encoder is enabled or bypassed When ENCBYPx 1 the Transmit encoder is enabled When Page 21 of 44 Feedback ENCBYPx 0 the Transmit Encoder is bypassed and raw 10 bit characters are transmitted Transmit Clock Select The initialization value of the TXCKSELx latch 1 TXCKSELx selects the clock Source used to write data into the Transmit Input Register When TXC
110. uffers allow data to be read using a clock that is asynchronous in both frequency and phase from the elasticity buffer write clock or to be read using a clock that is frequency coherent but with uncon trolled phase relative to the elasticity buffer write clock If the chip is configured for operation with a recovered clock the elasticity buffer is bypassed Each elasticity buffer is 10 characters deep and supports and an 11 bit wide data path It is capable of supporting a decoded character and three status bits for each character present in the buffer The write clock for these buffers is always the recovered clock for the associated read channel Receive Modes When the receive channel is clocked by REFCLKx the RXCLKxx outputs present a buffered or divided depending on Note CYV15G0404DXB RXRATEx and delayed form of REFCLKxz In this mode the receive elasticity buffers are enabled For REFCLKx clocking the elasticity buffers must be able to insert K28 5 characters and delete framing characters as appropriate The insertion of a K28 5 or deletion of a framing character can occur at any time on any channel However the actual timing of these insertions and deletions is controlled in part by how the transmitter sends its data Insertion of a K28 5 character can only occur when the receiver has a framing character in the elasticity buffer Likewise to delete a framing character one must also be in the elasticity buffer
111. v B Page 25 of 44 Feedback CYPRESS CYV15G0404DXB PERFORM Maximum Ratings Static Discharge 2000 V according to MIL STD 883 Method 3015 Exceeding maximum ratings may impair the useful life of device These user guidelines are not tested Storage Temperature 65 to 150 C Ambient Temperature with Power Applied 55 C to 125 C Supply Voltage to Ground Potential 0 5 to 3 8V DC Voltage Applied to LVTTL Outputs Power Up Requirements The CYP V 15G0404DXB requires one power supply The Voltage on any input or IO pin cannot exceed the power pin during power up Operating Range Latch up Current seen gt 200 mA High Z State eee 0 5V to Voc 0 5V Range Ambient Temperature u Output Current into LVTTL Outputs LOW 60 mA Commercial 0 G to 70 13 3V 15 DC Input Voltage 0 5V to Voc 0 5V Industrial 40 C to 85 13 3V 45 CYV15G0404DXB DC Electrical Characteristics Parameter Description Test Conditions Min Max Unit LVTTL compatible Outputs Output HIGH Voltage 4 Vcc Min 2 4 V Vout Output LOW Voltage lo 4 mA Voc Min 0 4 V

CYV15G0404DXB Independent Clock Quad HOTLink II - Digi-Key

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