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Blackfin® Processor and SDRAM Technology Application

1. P Listing 9 Splitting memory into pages Pages for ADSP BF561 Processors ADSP BF561 processors have a 32 bit memory interface When using the 16 bit interface addressing 1s the same as for ADSP BF53x processors The 32 bit address mapping scheme of the ADSP BF561 processor is defined in Figure 42 Row Column 2 MSB Figure 42 ADSP EBCAW 11 17 EBCAW 2 EBCAW 1 2 1 0 BF561 memory mapping scheme Table 3 shows page size for 32 bit EBIU with regard to the EBCAw bits Blackfin Processor and SDRAM Technology EE 326 Page 36 of 53 ANALOG DEVICES EBCAW Page bytes in Hex Table 3 Page sizes for 32 bit EBIU What s the advantage of accessing the pages separately If we can ensure that we stay within a page no additional precharge and activate commands are needed saving time Figure 43 shows a peripheral DMA approach to avoid page switches The DMA writes the incoming data to pages to different banks BANK 0 Open Page Figure 43 Open page DMA approach 6 3 SDRAM Performance Items for Core Accesses Core accesses are the most performance critical SDRAM accesses So if you do not use data cache for any reason you must have a strategy to organize accesses to the SDRAM This section describes the reason for this bottleneck and how to handle it Buffers are used to handle the data transfer between the system clock domain and the core clock domain These buffers are organized as a state
2. register name EBIU_SDBCTL reset value 0x 25 core Common register name EBIU_SDGCTL reset value 0x0091998d core Common register name EBIU_AMGCTL reset value xff core Common zc register reset definitions Bo xBo aia aa no no do Eo no NES v En o Eo nS Bo o nn Eo SER SES E Bo alie EB Ee Ee ER ER ER ER ER MER SER ES MES Eo SER MES Eo MER MES MP MER MS MP MER NER MP EP NE aiie E NES MB Ee E P ER Ee ER ER ER ER ER ME gi ee a a a a 7 gt Li zl ee o E a a of mT Toti one 4 Vn mare tata t o To dT le ma tr har LA d II 2 Lt iL nf LL ULG RET i anges LE LIED lLiit c REL Z zl L X a eke ot customized TTI e tri fac litate X 1 13 e TH ar z a a ki IL I m Tmt mte a hi m ia de mnm imul ee m e e ee A LIII EL b e e uu n Paa ee zl Ld d d e edd 5 5 8 05 05 8 8 ee 5 8 5 58 8 8 B B RA A BA bh A Ab A A E A A A A eee ee eee RA b A B i mmi LI lt visualdsp proc xml gt Figure 7 A portion of the ADSP BF5xx proc xml file VisualDSP 4 5 The processor xm1 file is read at startup only Any editing while VisualDSP IDDE is up and running will not take effect Ensure that you have edited the values before invoking VisualDSP development tools When VisualDSP tools are running the values in the xmu files are used to set the corresponding SDRAM values of the Analog Devices EZ KIT Lite development board For VisualDSP release 5 0 or higher it s not recommended to mod
3. A periodic restoration of an SDRAM cell charge needed to maintain data The time period in which one row of an SDRAM 1s refreshed The minimum time that each row in the SDRAM must be refreshed Part of the memory array A bit is stored where a row and column intersect Single data rate The data is transferred only once at one clock cycle This definition was introduced to differentiate this SDRAM from DDR In normal operating mode the Blackfin processor will control the refresh of the data cells by sending an auto refresh command But if the application has a need to give up control over the SDRAM for example when the processor 1s going into hibernate mode or in a multiprocessor application the SDRAM has to take over the responsibility of its data consistency Another case to send the SDRAM in self refresh is reducing power consumption When the Blackfin processor is sending a self refresh command the SDRAM will clock itself and will do self refresh cycles The disadvantage is the delay when you want to access a SDRAM in self refresh An input control signal that latches data synchronously into the SDRAM A circuit board configuration in which a signal trace is placed between two reference planes A memory device that has its signals synchronized to a reference clock One or more components used in conjunction with a transmission line to control signal reflections The time from which data is latched into the SDRAM until it is actual
4. offer an additional approach to initializing the EBIU register settings During booting the boot ROM program is able to initialize the EBIU settings by the programmed values in the OTP The OTP consists of a region called the Preboot Settings PBS block which must be programmed via the orP write function The PBSO2L page contains the EBIU settings Refer to your processor s Hardware Reference for an overview After setting up the EBIU control registers the boot process accesses the SDRAM at address 0x00000000 in order to initialize the SDRAM By default setting a read access will be performed Since a read access consumes more time than a write access this access can be customized by the OTP EBIU POWERON DUMMY WRITE bit Figure 10 which replaces the read access with a write access and saves time By using this option you must ensure that no important data 1s stored at this address before going to reset or hibernate Lower PBS02 Half Page PBSO2L Upper 63 48 One time Programmable 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 OTPoxiAL ax 91919 o o o o o o o o o 9 Defaultoxoooo OTP EBIU SDRCC Values to be written to the EBIU SDRCC register OTP EBIU POWERON DUMMY WRITE Issue dummy write to address 0x0000 0000 after initialization instead of dummy read Figure 10 Dummy write option Declare local variable DU64 Data Enable the EBIU Init settings Data h 0x04000000 use the cont
5. Magic by Howard W Johnson and Martin Graham 1993 PTR Prentice Hall ISBN 0 13 395724 1 11 High Speed Signal Propagation Advanced Black Magic by Howard W Johnson and Martin Graham 2003 PTR Prentice Hal ISBN 0 13 084408 X 12 EMV Design Richtlinien by Bernd F ste and Stefan Oing 2003 Franzis Verlag GmbH ISBN 3 7723 5499 8 Readings 13 ADSP BF53x ADSP BF56x Blackfin Processor Programming Reference Rev 1 2 February 2007 Analog Devices Inc Document History Revision Description Rev I May 12 2005 Initial release by Fabian Plepp Blackfin Processor and SDRAM Technology EE 326 Page 53 of 53
6. UH DIAM UE Dra UR UM e duU 22 da ke L AD ye ee PrODOCGODOBhI uicta Heresies se es cucina cuite im tuoi co e eae 22 4 1 2 ADSP BF561 Processors 16 bit SL AM LuLmedaUMueD Er MEME AC RARI M MES AL M E LM CAU Eae 22 4 1 3 ADSP BF561 Processors 32 bit JSDBAM iitee e E EPeR papi eR IEPeP Pe trovere SPEED Rode sab SIR e Delos Ex IDE T E EE NP ee pep R Dna sdEe PRIMO nenne 23 o TET oio e ucro u e 24 dadl NE ete ches I qoe Bd eera MM DURER M MEER E MM MUNI MEME RUE 24 a AUSLd BeTLOSES ON nu Ed Meu MM MI IU MIC M CM DIM eee eee 25 4 3 Design Guidelines for the SDRAM ConnectioOn s sssssrsrssserressssresarsresarsreserstoesarsresarsreresstesssstceesastecsaesessaeseesaeseesens 26 nS Pe Com ronen Placere COns le lt 6 arg CLON ease 26 4 3 2 Using the Rounding Function or Your Layout Tool at Trace Edges sicsicscessaszscencatvadedevtsstasecidndessetine 2 4 3 3 Placing the VCC and GND Planes with as Little Distance as Possible eene 27 Blackfin Processor and SDRAM Technology EE 326 Page 2 of 53 ANALOG DEVICES 4 3 47 Insulating Critical Signals by Placing Them in the Inner Layet25 2 t rex ennan 28 4 3 5 Placing the Series Resistor Close to the SDBEAML etes per erdebors eleeseslevERE oet CVb epos uve oes ela nhe esi ooa uus 28 4 940 Avoiding Trenches in the GND IOS ees euEUE rte o tb IUe telas e Pod IaUE Ea a S Prop uU epi prop Rue e DIE Naia 28 Ac Sed Minimizing Back current Paths Irom VlodSmounsudenn ONER
7. We assume we have n elements each with the same Rp Rs C and L Blackfin Processor and SDRAM Technology EE 326 Page 49 of 53 ANALOG DEVICES Multiply both sides by 1 Z n x Y x Z Yr x Z 1 Z U Z Z e n n n I Tx Z Z Y n Z Zx Z 4 t 4 Y n Assuming a transmission line consists of infinite elements with the length 0 Z Zx Z oL R Z lim Ed A 2 NI aM nos VE OH Y j X 1 Rp As you increase the frequency the terms R and G may eventually be neglected as they are overwhelmed by j L and j C respectively leading to a steady plateau in impedance The fine balance between the inductive impedance joL and the capacitive admittance joC holds the impedance constant at high frequencies This constant impedance plateau greatly aids the design of high speed digital circuits as it makes possible the termination of transmission lines with a single resistor The value of characteristic impedance at the plateau is called Zo Z lim Zc 0 00 Calculating the Inductance of a Microstrip Trace It is strongly recommended to measure these values but to estimate the value you can use the following formulas Lasme W whereby L is the inductance in nH inch h s the height above the plane mils w is the trace width mils Calculating the Capacitance NEP 0 r d Blackfin Processor and SDRAM Technology EE 326 Page 50 of 53 ANALOG DEVICES whereby A 1s
8. address space will be fragmented as shown in Figure 31 Wi Internal Bank 3 Internal Bank 2 Internal Bank 1 LARG Internal Bank O Figure 31 Address space The aliased address space s content is a copy of the according bank and every write access to this space results in a write access into the real bank This must be considered by the Linker Description File LDF or the Blackfin processor will place instructions and data into addresses that do not exist This type of address failure cannot be detected by the Blackfin processor There is no NM functionality that tests whether an address is valid This will cause failures later in your application when the core is tries to read from a non existent address space getting dummy values and then interprets this as valid instruction code or data Blackfin Processor and SDRAM Technology EE 326 Page 30 of 53 ANALOG DEVICES 5 2 Changing the LDF File First ensure that the Lpr file will not be changed by the Expert Linker wizard Therefore open the Project Options dialog box Project gt Project Options to the Remove Startup Code LDF page and select the Leave the files in the project but stop regenerating them option Figure 32 Project Options for LessMemorythan4MB d Processor amp Remo El Load EA Options You curently have Startup Code and LDF files added to your project 5 Compression If you choose to remove these files from the project
9. machine which enables you to change the core and system clock without concern for internal processes Depended on the core system clock ratio wait states are introduced to organize reads and writes by the core to and from the system domain One approach to solving this problem is to work with DMA transfers Therefore we are using DMA to transfer data that we want to process into internal memory DMA has an internal FIFO buffer structure and can read from SDRAM without additional time penalties Software planning and design is essential especially when working with very large size of the array gt gt internal data memory multi dimensional arrays In this case your algorithm must access this array in different manners You can use DMA to order the array optimally for your algorithm Blackfin amp Processor and SDRAM Technology EE 326 Page 37 of 53 ANALOG DEVICES 6 3 1 Code Overlays A disadvantage of using cache 1s that the cache expects a program flow that may not fit to your program thus it results often in cache misses Another approach is to load the necessary code into internal memory by DMA transfer the code will be organized by an intelligent overlay manager that can predict which piece of code is needed next Whether there are any performance improvements by using an overlay manager depends very much on your system design and on program flow For most applications an optimization of the cache will be a better and easier approach t
10. the length times the width of the trace d is the distance between ground and the trace This must be calculated for every ground plane IPC s and Douglas Brooks approach of Z Chapter 4 IPC and Douglas Brooks offer some equations for PCBs which are very easy to use Microstrip Trace 87 598 H Je 141 X0 8 W T Embedded Trace Ly Nerea eese yea TRU ate h puce ud LL sebo S m ara a n n aa E A m uud DUd TEE Es ME te Hn HERES ium Bisons uuTKe uM MEM EEE p OT e 60 1 9 QH T de 08 W4T Asymmetric Stripline Trace W 80 19 QH T A Je 0 8 W T 4 Hl whereby H1 gt H Blackfin Processor and SDRAM Technology EE 326 Page 51 of 53 ANALOG DEVICES Dielectric Constants of Printed Circuit Boards PCBs Chapter 4 The tables are taken from A Survey and Tutorial of Dielectric Materials Used in the Manufacture of Printed Circuit Boards Several Commonly Available Woven Glass Reinforces Laminates Material Tan f tandard FR 4 Epoxy Glass 125C 0 02 7 022 150C 0 022 170C 0 012 T800 E 0 008 185C 7 023 715C 0 005 GETEK GETEK T Epoxy Glass j aafo 2 la e s la le olyimide Glass 0 015 eflon 0 0002 Measured with a TDR using velocity method mE Resin content 55 Tg glass transition temperature DBV dielectric breakdown voltage er relative dielectric constant WA water absorption Tan f loss tangent All materials with wove
11. to Zo Consider whether you even need termination An additional resistor emits further EMI 4 3 Design Guidelines for the SDRAM Connection With regard to EMC and signal integrity the following design guidelines are recommended When you start your SDRAM PCB layout do not treat all signals the same consider the importance of each signal and place the traces of the most critical signals first The following succession is suggested 1 Clock distribution 2 Data lines and pow lines command lines including 3A10 3 Address lines 4 Other signals e g CKE 4 3 1 Component Placement Considerations Consider the following points while laying out your PCB m Place the SDRAM chips close to the Blackfin processor m Keep the traces as short as possible m When you are distributing a signal all traces should have the same path length Figure 17 to the devices if possible Avoid loops like the one shown in Figure 18 S D R A M S D R A M Figure 17 Right spread traces and make their lengths equal Blackfin Processor and SDRAM Technology EE 326 Page 26 of 53 ANALOG DEVICES Figure 18 Wrong traces that loop around 4 3 2 Using the Rounding Function of Your Layout Tool at Trace Edges Figure 19 shows a PCB trace edge that does not use rounding Figure 20 shows the same trace edge when the rounding feature 1s enabled Figure 20 Right Trace edges are rounded 4 3 3 Placing the VCC and GND Planes with as L
12. while the core is powered down The Blackfin processor can be awoken by several external events The process of read writing data alternately from two or more pages in the SDRAM Joint Electron Device Engineering Council The length of time usually expressed in clock cycles from a request to read a memory location and when the data is actually ready The time it takes for a complete memory operation such as a read or write to take place A trace configuration where there is a reference plane on only one side of a signal trace The number of bytes that can be accessed with one row address An operation that takes place when RAS is taken logic low and a column address is strobed in The SDRAM remembers the last row address and stays on that row and moves to the new column address Printed circuit board Row address strobe The control signal that latches the row address into the SDRAM It is used in conjunction with the column address to select an individual memory location The time between a row access strobe and a column address strobe Page 43 of 53 read time refresh refresh cycle refresh period row SDR SDRAM self refresh strobe stripline synchronous memory termination write time Blackfin amp Processor and SDRAM Technology EE 326 ANALOG DEVICES The time required for data to appear at the output once the row and column address become valid Read time is also referred to as access time
13. 0003800 TYPE RAM START 0x00004000 TYPE RAM START 0x00004800 bank 0 of a 10 bit memory of a BF53x END 0x000007FF END 0x00000FFF END Ox000017FF END 0x00001FFF END 0x000027FF END Ox00002FFF END 0x000037FF END Ox00003FFF END 0x000047FF END 0x00004FFF if we would define a section for each page we have to define 8192 so we define sections only for the amount of pages which are performance relevant SDRAM BANK 0 OTHER TYPE RAM START 0x00005000 END OxOOFFFFFF WIDTH 8 the pages on the second bank SDRAM BANK 1 PAGE 0 SDRAM BANK 1 PAGE 1 SDRAM BANK 1 PAGE 2 SDRAM BANK 1 PAGE 3 SDRAM BANK 1 PAGE 4 SDRAM BANK 1 PAGE 5 SDRAM BANK 1 PAGE 6 PROCESSOR pO SECTIONS TYPE RAM START 0x01000000 TYPE RAM START 0x01000800 TYPE RAM START 0x01001000 TYPE RAM START 0x01001800 TYPE RAM START 0x01002000 TYPE RAM START 0x01002800 TYPE RAM START 0x01003000 EDEN INPUT SECTION ALIGN 4 INPUT SECTIONS SOBJECTS sdramOpageO0 gt SDRAM BANK 0 PAGE 0 j j END 0x010007FF ENDUCOXOTOOOEFEFE END OxO10017FF END 0x01001FFF _ END 0x010027FF END 0x01002FFF END 0x010037FF WIDTH WIDTH Wi TH WIDTH WIDTH WIDTH We ery WIDTH WIDTH WIDTH 8 8 8 8 8 8 8 8 8 8 j MR P M M M P
14. 23 m Connect spoMo to DoM of SDRAMA D24 D31 Blackfin amp Processor and SDRAM Technology EE 326 Page 23 of 53 ANALOG DEVICES Buceo BF561 SDRAM NEN FL Bae hon DRAMO eee Deen o OORA SDQM2 DQML DRAM 1 DQMH DRAM 1 Figure 14 ADSP BF561 processors connections between the Blackfin processor and 32 bit SDRAM Another problem is caused when the BR pin is left floating The Blackfin processor interprets the signal as bus request and will answer with the Bc signal which will block the parallel bus for an infinite time So always put a pull up resistor on the BR pin Use decoupling capacitors to decouple the SDRAM power supply Add a series resistor close to each data pin of the SDRAM The next section explains how to determine the resistance 4 2 High Speed Design The layout of the SDRAM connection is a critical factor especially on low power designs This section explains how to optimize the design of the SDRAM layout to fit your application s requirements The most critical connections are the clock the lower address lines the Dom and the data lines 4 2 1 Effects that Impact Signal Quality This section describes effects that are influenced by your hardware design Reflection If the impedance of a connection line is equivalent to the input resistance of the receiver the energy will be fully absorbed by the resistance Otherwise the transmission s energy will be thrown back This will interfere wi
15. A17 pq A16 Eg A15 MA5 A14 E6 A13 A11 aio bp ETE 8 cia AT FB 6 aio 5 BTS 6 Pair A3 A ABESSDQMS 7344 ABE2SDQM B73 ABE1SDQM1 ABEOSDQMO M15 pL 30 L16 e pos Lig SE LES si EAE K14 amus Jig mur H14 p19 Hee H13 D18 H15 H12 G12 KEERN G15 N E14 EN LEE N E2 N LEIS N PETS oS LETS N D16 RN D15 N LETA EN KAAN E2 N LCIS N B16 AN SEE ues LI LI Li LI LJ LI oD LJ A11 A12 ADSP BF561 BGA Blackfin Processor and SDRAM Technology EE 326 ANALOG DEVICES 6 VSSQ MT48LC16M16 TSOP54 VDD 49 VDD 27 SENS 18 es ElSDOMI 39 15 ABI ABEOSDOMO Y 4 E i SER x Eu aE A AO U5 MT48LC 16M16 TSOP54 cap eur L3 9 S VE NR L 3 5 fe Ya Al AO U14 Page 47 of 53 ANALOG DEVICES ADSP BF561 in 32 Bit Mode MT48LC16M16 TSOP54 A25 A24 A23 A22 SRAS 18 l A RAS A20 DQMH A19 A18 eS A17 A16 To SDRAM A15 A14 SWE 16 9 To Blackfin A12 A11 pee E ec cu Pn E ee EN fe hy a je a AE EENAA AE je E ee EN A4 A3 A2 he E ERE ABE3SDQM83 EM ABE2SDQM2 To Blackfin ABE1SDQM1 ABEOSDQMO To SDRAM 2 U16 To Blackfin nae O ac D30 D29 D28 D27 D26 D25 D24 D23 MT48LC 16M16 TSOP54 D22 D21 D20 To SDRAM 1 SWE 16 WE ABEI1SDQM1 39 EONS 15 DQMH pro E DOML a CKE CAS To Blackfin I OO o DL
16. AM is specified At the Blackfin processor you can set the temperature via the TCsR bit of the EBIU_SDGCTL register The value of TcsrR indicates the temperature border for example 45 C means you are operating below 45 C Many applications use most of the SDRAM devices only to buffer data arrays which occurs after the processing For these applications the partial array self refresh feature 1s a good approach to saving power This feature enables your application to select the memory banks that are to be refreshed during idle mode If you have any code on the SDRAM place it at SDRAM bank 0 and bank 1 otherwise it will be lost For this application use a low voltage 1 8V or 2 5V Blackfin processor 7 4 Going into Hibernate and Recover ADSP BF537 ADSP BF54x and ADSP BF52x processors preserve SDRAM content while the processor is sent to hibernate mode Therefore the ckELow bit in the vR_cTL register must be set to 1 to maintain the CKE signal low during hibernate which will prevent the SDRAM from losing data The content of internal memory and all registers except the vR_cTL register will be lost Therefore the program has to write all the register settings and the internal memory content to SDRAM The following steps are used to go into hibernate mode and recover the data Step 1 Save all important registers to the SDRAM Save the important data of your internal memory to the SDRAM Ensure that the cKELOow bit is set in the vR
17. DQ Figure 5 Timing To verify that the read operation processed correctly ensure that to gt tsspar tac Blackfin Processor and SDRAM Technology EE 326 Page 9 of 53 ANALOG DEVICES 2 SDRAM Initialization SDRAM initialization impacts application performance and SDRAM power consumption Therefore a better understanding of the settings is highly desirable This section describes how to set up the EBIU External Bus Interface Unit registers in order to run your application In order to initialize the SDRAM use one of the following approaches a SDRAM initialization via an emulator and VisualDSP xmt files m SDRAM initialization by setting the registers within the application m SDRAM initialization by using the VisualDSP system service model a SDRAM initialization by an initialization file before loading the actual application a SDRAM initialization by the values in the OTP One Time Programmable memory 2 1 SDRAM Initialization Via an Emulator and VisualDSP XML Files In the early stages of software development you upload your software via an in circuit emulator ICE The emulator can set up the EBIU registers automatically when you upload a program to the processor To enable this functionality from the VisualDSP settings menu chose Target Options From the resulting Target Options dialog box Figure 6 select the Use XML reset values option Target Options Device O a Reset options Other Options Co
18. E AE 29 5 Using a Blackfin Processor with Less than 16 MB Of SDRAM ueste ee PIPER eu iceYbute d e vbr eu saves red exer a aka 30 SANE SMS Iste arsi RR 30 cT ame Gl arc 06 jal alt ile on a a AME NNUS 3l ay TS s NES co depo DR SN 3l SPENCER Ud CE uu NUES RU H 32 Inereaosling the SDRAM Perl ortance Ol Tour BSy8LDeaGiek oat at Ie NUMEN MN Oe ENS 33 Cal Goa MUNERE etes nad Gm ete i TTE 33 cod OP Ie I II mo c m 34 Pages for th ADSOE BE5SSX TPEPOGOSSOEDS aisredodieteui enoi iE ERE C E EERE UNE U DE UR ARMES Ne b REM CRM P I E diea M EE eM Rd M DU RENE 35 Fages tOr D icu cielo cases omes 36 Gio PARAM PeSrrormanose Itens ftor Coro JDUEEDSE B eepe eden MUEVE M rU Mu exis peu PUE RU UNA E MEME 37 Boss code cU Ta E conce MEM M M MD M DEED LE MEM EE 38 6 4 SDRAM Performanee Items When Uing Cae usadas nive Konto Les tiv ax Coe saepe tive osea oscar Mia sera UR DM ed Fuse ta Ra Cod M Ne E Case 38 sog RERUM 38 biu NL C VO VY C co a 72 7 7 7 9 38 Te Oa ie ie Owe Con nere SORT 39 Tad MAC COCUC EO Powsrt Osnsu npblon a Ss eU Pm Etede iei paige sts ene seemeawesderenchede ESA ETA 39 T23 Tips FOr Lowering SDRAM PoWEE ConsSU
19. EM SDRAMO BANKI in the SECTIONS area again PROCESSOR pO OUTPUT SCOMMAND LINE OUTPUT FILE RESOLVE start OxFFAO00000 KEEP start main SECTIONS ER sdramO Danki INPUT SECTION ALIGN 4 INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS sdramO SLIBRARIES sdram0 sdramO bank1 SLIBRARIES sdramO Danki sdramO0 data LIBRARIES sdramO data edo on ten EORR SS datal SLIBRARIES datal voldata SLIBRARIES voldata constdata SLIBRARIES constdata eode shIBEARTES spite edt SLIBRARIES edt Cht Sai BRARTES lt CHE INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS INPUT SECTIONS SOBJECTS gt MEM SDRAMO BANK1 N NN NN nn NOS eer SECTIONS yes lg ces Listing 8 Specifying memory sections Blackfin Processor and SDRAM Technology EE 326 Page 20 of 53 ANALOG DEVICES We see that several libraries and objects are mapped into this memory space You can map an object or library to more than one memory section In this case the linker decides which part of the data or code 1s placed into each section of memory To place data explicitly in one memory section if using C C use the pragma section directive In our case we want to place the global variable x into internal SDRAM bank 1 The label sdram0_bank1 is only
20. Engineer to Engineer Note EE 326 ANALOG Technical notes on using Analog Devices DSPs processors and development tools DEVICES Visit our Web resources hitp www analog com ee notes and http www analog com processors or e mail processor support analog com or processor tools support analog com for technical support Blackfin Processor and SDRAM Technology Contributed by Fabian Plepp Rev I May 12 2008 Introduction The Analog Devices Blackfin family of processors provides an External Bus Interface Unit EBIU with which to interface to SDRAM This EE Note covers the following topics m Register settings and their meaning m SDRAM initialization m SDRAM hardware design m Using less than 16MB of SDRAM m Performance optimization m Power optimization This EE Note discusses SDR SDRAM not DDR SDRAM This EE Note applies only to ADSP BF53x ADSP BF52x and ADSP BF561 processors It does not apply to ADSP BF54x processors Although this document covers basic aspects of SDRAM functionality you should read The ABCs of SDRAM EE 126 for more information This document is separated into different topics so you do not need to read the entire document when you are looking for specific information Copyright 2008 Analog Devices Inc All rights reserved Analog Devices assumes no responsibility for customer product design or the use or application of customers products or for any infringements of patents or rights of other
21. Ey Compiler Instrumented 4 Remove the files from the project and send them to the recycle bin Leave the files in the project but stop regenerating them Figure 40 Project Options dialog box settings Now we are able to change the Linker Description File LDF Pages for the ADSP BF53x Processors ADSP BF53x processors have a 16 bit memory interface The address mapping scheme is defined in Figure 41 Row Column 2MSB EBCAW 10 16 EBCAW 1 EBCAW 1 0 Figure 41 ADSP BF53x memory mapping scheme There are different page sizes depending on the SDRAM being used Table 2 shows 16 bit EBIU page size with regard to the EBcAw bits EBCAW Page bytes in Hex Table 2 Page sizes for 16 bit EBIU Consider a column address width of 10 bits Every page has 0x800 bytes and we are able to define our memory mapping in the LDF file Listing 9 Blackfin Processor and SDRAM Technology EE 326 Page 35 of 53 ANALOG DEVICES MEMORY mE We define 10 pages in SDRAM BANK 0 PAGE 0 SDRAM BANK 0 PAGE 1 SDRAM BANK 0 PAGE 2 SDRAM BANK 0 PAGE 3 SDRAM BANK 0 PAGE 4 SDRAM BANK 0 PAGE 5 SDRAM BANK 0 PAGE 6 SDRAM BANK 0 PAGE 7 SDRAM BANK 0 PAGE 8 SDRAM BANK 0 PAGE 9 TYPE RAM START 0x00000000 TYPE RAM START 0x00000800 TYPE RAM START 0x00001000 TYPE RAM START 0x00001800 TYPE RAM START 0x00002000 TYPE RAM START 0x00002800 TYPE RAM START 0x00003000 TYPE RAM START 0x0
22. ItiDDb senses nietr nr e ERE S PE TUR peius P ru da opes MH PE CO din ORN RARE R 39 CU IME NES Di R 40 74 Going into Hibernate eM olcheR m 40 Sur m LT eee 40 cinco EE cE 41 usos E E E et ota iene aaee eotuaeaneoten 4 Tap dEscuelburiTC Dele TOC Low Power Com iOD essenin en OEE E a Eaa 41 T c POT u 42 Lwscasa ECIAM RENO Ceo PRE ae nee ee Ce eee ee ee ee ee 42 Appendix BE Code Rxumples SoeHemdLccB y And Fee SUUS eaii E E E Or A 45 Ni alsace veel cue a ol ame G5 ism PTT 45 Schematics to Interface SDRAM to the Blackfin Processor Chapter A sessa onenean a 46 ADSP BES0L xum oes II Biene Metu ne ee eRe Mb UEM EM M Ie ee eee ree ener eee ee eee 47 ADOP BF561 I 32 BIE MOJE eee ee r 48 iov elbiras qoo MO B erp Dunk oo 2y Chap so m 49 CalboculeLins the Inductagnoe OT a MLCOPOSLEID EGO ro Ut Ee ErR MI TER PURI MU PEE KU rea SPEED NI D s VE UINMU Er P MM UUE 50 e NEeNE suas sto qo ieshE n e NOTTIT o 50 Blackfin Processor and SDRAM Techno
23. L PO L lo EBIU SDGCTL RO H ila d CDDBG amp Control disable during bus grant off FBBRW amp Host back to back read to write off EBUFE amp External buffering enabled off SRFS amp Self refresh setting off PSM amp Powerup sequence mode PSM first PUPSD amp Powerup start delay PUPSD off TCSR Temperature compensated self refresh at 85 EMREN Extended mode register enabled on PSS Powerup sequence start enable PSSE on TWR 2 Write to precharge delay TWR 2 14 15 ns TRCD 3 RAS to CAS delay TRCD 3 15 20ns TRP 3 Bank precharge delay TRP 2 15 20ns TRAS 6 Bank activate command delay TRAS 4 PASR_BO Partial array self refresh Only SDRAM Bank0O cu CAS latency SCTLE I 7 SDRAM clock enable POTIS re CDDBG amp Control disable during bus grant off FBBRW amp Fast back to back read to write off EBUFE amp External buffering enabled off SRFS amp Self refresh setting off PSM amp Powerup sequence mode PSM first PUPSD amp Powerup start delay PUPSD off TCSR Temperature compensated self refresh at 85 EMREN Extended mode register enabled on PSS Powerup sequence start enable PSSE on TWR 2 Write to precharge delay TWR 2 14 15 ns TRCD 3 RAS to CAS delay TRCD 3 15 20ns TRP 3 Bank precharge delay TRP 2 15 20ns TRAS 6 Bank activate command delay TRAS 4 PASR_BO Partial array self refr
24. NANOSEC set TRE to 18Hns ADI EBIU TIME MyTRP 18 ADI EBIU TIMING UNIT NANOSEC set TROD te lens ADI EBIU TIME MyTRCD 18 ADI EBIU TIMING UNIT NANOSEC set CAS threshold frequency U2 MAS Enable Extended Mode Register because we are using Mobile SDRAM ADI EBIU SDRAM EMREN MyEMREN ADI EBIU SDRAM EMREN ENABLE Refresh only the first bank ADI EBIU PASR MyPASR ADI EBIU PASR INTO ONLY Temperature Compensation at 85 C ADI EBIU SDRAM TCSR MyTCSR ADI EBIU SDRAM TCSR 85DEG we don t have any registered buffer ADI EBIU SDRAM EBUFE MyEBUFE ADI EBIU SDRAM EBUFE DISABLE Blackfin Processor and SDRAM Technology EE 326 Page 14 of 53 ANALOG DEVICES no fast back to back read write ADI EBIU SDRAM FBBRW MyFBBRW ADI EBIU SDRAM FBBRW DISABLE Do not disable the Control during bus grant ADI EBIU SDRAM CDDBG MyCDDBG ADI EBIU SDRAM CDDBG DISABLE We don t need any delay at Power Up ADI EBIU SDRAM PUPSD MyPUPSD ADI EBIU SDRAM PUPSD NODELAY Do first the refresh ADI EBIU SDRAM PSM MyPSM ADI EBIU SDRAM PSM REFRESH FIRST Listing 3 Initialization of the EBIU structure Table 1 Overview of EBIU commands After setting up the parameters we need to initialize the service Therefore we bundle the parameters to a command table and afterwards call the aai EBIU init function ADI EBIU COMMAND PAIR Sdram Values ADI EBIU CMD SET SDRAM BANK SIZE void amp bank si
25. O Bee alo M To Blackfin To Blackfin O gt o m CD op op C N n lt n BR BG UJ ab ADSP BF561 BGA Blackfin Processor and SDRAM Technology EE 326 Page 48 of 53 ANALOG DEVICES Excursus Calculating Z Chapter 4 This section describes the Telegrapher s equation approach The SDRAM connection is a transmission line This is the reason the telegrapher s equations accurately model the propagation of electrical currents and voltages along the structure The trace is not an ideal conductor so we have to use an equivalent circuit diagram Figure 47 that includes the influence of the trace itself Inpu Figure 47 Equivalent circuit including the influence of the trace itself But a trace consists not only of one of these structures We can imagine a connection line Figure 48 as a nearly infinite series of them STAGE 1 Inpu L Rs C Rp Figure 48 A connection line made up of infinite traces The variable Zc is a function of the impedance and depends on the frequency If you want to write it mathematically correct you have to write Zc The variable Zo is a single valued constant showing the value of characteristic impedance at a particular frequency Wo We simplify the model by defining the impedances Y and Z Z ja L Rs Y j C 1 Rp The resulting impedance is the sum of the impedance of Z and the impedance of Y and all the other stages in parallel
26. OG DEVICES 1 4 Mobile Low Power SDRAM Options Blackfin processors support mobile SDRAM chips also called low power SDRAM Depending on the series of Blackfin processors you can use 3 3V 2 5V and 1 8V SDRAM In order to use 2 5V and 1 8V chips verify in the processor s data sheet electrical specifications that the processor is able to have an output low voltage of 0 3 V maximum The mobile SDRAM archives low power consumption not only by its lower voltage but also by its low currents Another advantage of mobile SDRAM is the ability to deactivate the self refresh of the several banks you are not using and to reduce the self refresh rate by defining the temperature These features enable you to optimize power consumption for your specific application If not otherwise stated in the Blackfin data sheet at 1 8V vDDEXT the maximal frequency of the system clock is limited to 100 MHz To use the extended registers of mobile SDRAM you must set the EMREN bit 1 4 1 PASR Partial Array Self Refresh Every refresh consumes power If the application does not need to store the complete memory in special modes this feature provides a way to disable the refresh of several banks of the SDRAM The benefit of this feature 1s lower power consumption Take for example an application that stores data e g a picture into SDRAM does some signal processing transmits the data or stores it to a non volatile memory e g flash and goes back into sle
27. _cTL register and the self refresh bit in the SDGCTL register Send the processor into hibernate mode Figure 44 and Listing 11 gt BLACK oe SDRAM R3 Internal memory Figure 44 Going into Hibernate mode Blackfin Processor and SDRAM Technology EE 326 Page 40 of 53 ANALOG DEVICES SaveTheMemory SaveTheRegister Let s setup the RTC to wake up SetupRTC TaeMa Sk ella 6 PNR Cm WAKE wake by CKELOW keeps the content of the SDRAM CANWE ensures that the CAN RX can wake up the BF pVR CTL amp FREQ Send to hibernate Listing 11 Going into Hibernate mode Step 2 The processor is in hibernate mode Figure 45 The content of all registers except vR_cTL are lost The data 1s stored in SDRAM gt BLACK ao SDRAM Self refresh Figure 45 Hibernate mode Step 3 After waking up the processor from hibernate mode Figure 46 the processor boots in the initialization file By checking the cKELow bit the processor determines whether it is coming from hibernate or from reset When the Blackfin processor is coming from reset the processor continues the boot process otherwise it calls a routine to restore the internal memory and the registers and then jumps to the execution code Init Code Buchs SDRAM CKELOW set 0 boot normal 1 restore data and jump to program Internal Internal memory memory Figure 46 Recovering from hibernate mode 7 5 Structuring D
28. ails 1 1 Basics of SDRAM Although SRAM stores binary data using transistors DRAM uses a capacitor and a transistor The capacitor is the storage itself when charged it will be a logical 1 otherwise a logical 0 The transistor acts as a gate that controls access to the cell and traps the charge The disadvantage of this technology is that capacitors discharge over time To prevent the loss of data the DRAM must be refreshed periodically to restore the charge on the memory cells Thus a read and write operation must be performed to every memory location in the memory array at least once during the refresh rate period which is typically specified in milliseconds Precharge Circuit Address Buffer 7v Row Decoder D 3 O Z 2 D lt Sense Amplifer I O Gate Internal SDRAM ore Control OE Y A W Y aT DQ Figure 1 SDRAM Column Decoder IL The DRAM cells are organized in an array of rows and columns Every single cell can be accessed by a well defined row and column address The row is often called the page and the number of columns is referred to as the page size The address is time multiplexed the row address is transmitted first then the column address is transmitted The RAS row access strobe and by the cas column access strobe sign
29. als control the time multiplexing of the row and column address The RAS signal indicates that a row address is available to be loaded into the address buffer and decoded by the internal row address decoder After a short delay the CAS signal indicates that the column address which is available in the address buffer is forwarded to the column address decoder If wE is high a read command is processed The cells that are addressed by a row are read out completely amplified and written back to the cells The columns that are addressed are transmitted over the data bus Blackfin amp Processor and SDRAM Technology EE 326 Page 5 of 53 ANALOG DEVICES If the wE is low a write command is processed The isolated writing of a single cell is not possible thus a complete row is first read into a buffer In the buffer the elements to be changed are written and the complete row is written back to the array 1 2 SDRAM Parameters in Blackfin Registers 1 2 1 EBCAW SDRAM External Bank Column Address Wiath Often the external bank column address width is called the page size of the SDRAM Blackfin processors support page sizes of 512 bytes 8 bits 1 Kbytes 9 bits 2 Kbytes 10 bits and 4 Kbytes 11 bits Row Column 2MSB EBCAW 10 16 EBCAW 1 EBCAW 1 0 Besides the byte address bit which is the least significant bit LSB these bits are the least significant bits of the logical address Depended on the width of the column add
30. ata for Low Power Consumption Not only are the precharge and activate operations time consuming they also have a massive impact on power consumption Therefore keep the number of these operations as low as possible A precharge operation during the application will be executed at page breaks and SDRAM refreshes Therefore organize the data in a way that keeps the number of page breaks as low as possible Refer to Increasing the SDRAM Performance of Your System for examples Blackfin Processor and SDRAM Technology EE 326 Page 41 of 53 Appendices Appendix A Glossary access time array asynchronous auto precharge auto refresh bank burst mode bypass capacitor bus cycle CAS CAS before RAS CBR column crosstalk DDR DQM DRAM EBIU Blackfin Processor and SDRAM Technology EE 326 ANALOG DEVICES The time from the start of one device access to the time when the next access can be started Memory area for data storage The array consists of rows and columns where each memory cell is located at an address where an intersection occurs Each bit in memory is found by its row and column coordinates A process where operations proceed independently An SDRAM function that closes a page at the end of a burst operation A mode where an internal oscillator establishes the refresh rate and an internal counter keeps track of the address to be refreshed A bank can mean the number of physical banks sa
31. ckfin processors see Brief Introduction to SDRAM m Lower the refresh rate in a low temperature environment The refresh rate of 64 ms is specified for the worst case scenario high temperature Thus you still have room left to lower it when you are operating in a standard environment m Try to do data transfers between memory banks not within memory banks m Enable the self refresh bit SRFS in the EBIU_SDGCTL register In this mode the power dissipation of the SDRAM is at the lowest point Blackfin Processor and SDRAM Technology EE 326 Page 39 of 53 ANALOG DEVICES 7 3 Mobile SDRAM Use mobile SDRAM or low power SDRAM for embedded applications with high power consumption requirements In these applications the SDRAM is used very infrequently thus most of the time it 1s in the idle state Mobile SDRAM offers special modes that reduce the power consumption when the SDRAM is in idle mode Features that are supported by Blackfin processors are temperature compensated self refresh TCSR and partial array self refresh The temperature compensated self refresh feature allows you to reduce the self refresh frequency while it is in the idle state at temperatures below 45 C The leakage of the memory cells is very temperature dependent when the temperature is high the leakage is higher than when the temperature 1s low The self refresh rate for standard SDRAM is set to a worst case value for the highest temperature and the SDR
32. d on different pages on the same bank An activate and precharge must be executed after each switch between source and destination DMA Additionally we need to take into account that the core or the cache is may access the bank as well There is a delay every time between the reads and the writes This delay can be enlarged by the internal DMA architecture The DMA is designed as a feedback control state machine which introduces additional wait states under special circumstances To avoid such a time consuming case organize the memory in a way that allows inter bank DMA copies Figure 38 shows such an approach Blackfin amp Processor and SDRAM Technology EE 326 Page 33 of 53 ANALOG DEVICES Open Page Figure 38 Multi banking approach via DMA and core The core gets its code from bank 0 and the MDMA transfer runs from bank 3 to bank 2 Figure 39 shows the sequence of the data transfer between two banks As shown the number of precharge commands and activate commands decreases significantly As discussed earlier because precharge and activate commands are time intensive procedures this technique saves a lot of time Source Destination Source Destination Source Destination DMA DMA DMA DMA DMA DMA AR Bw R R EA B Activate R Read Accesses Write Accesses P Precharge Bank 3 Bank 2 Bank 3 Bank 2 Bank 3 Bank 2 Figure 39 Intelligent bank accesses 6 2 Optimal Pages Accesses This section describes how to improv
33. e Before Loading the Application If you want to place instruction and data sections into your SDRAM at initialization time you must use an initialization file that initializes the SDRAM before the application is loaded Therefore start a project and code an initialization file Build this project into a pxe file The initialization DxE file can be included into a loader file of your actual application via the Project Options dialog box Project Load Options page Project Options for Init amp dramUsingAsm 5g Source Language 5i ih Preprocessor p 2 mm Pacer Ld Boot Mode Boot Format Output Width Ri Processor 2 S Flas PROM UART 9 Intel hex Bit i Profile quided Optin SPI O TWI O ASCII 16bit i SPI Slave Include Binary aa Link 01 EE General Wait state Baud rate Hold time Programmable flag B LDF Preprocessing E Elimination i v Use det Stall ai Start a prz EN Fh Processor 3 Use default start address Start address F Load Verbose EE Options Initialization file Use default decompression INIT file rinit code ADSP BF537 INIT CODEXADSP BF537 InitCode dxe Output file 2 Additional options Figure 11 Specifying project load options Listing 6 shows an example of how initialization code can be implemented Blackfin Processor and SDRAM Technology EE 326 Page 17 of 53 ANALOG DEVICES include defBF537 h Section program save all r
34. e page accesses If you are able to keep accesses within a page now further activate and precharge commands are necessary besides those that are issued to do the refresh The following description shows how to access pages separately Open the Remove Startup Code LDF page of the Project Options dialog box Project gt Project Options and select the Leave the files in the project but stop regenerating them option Also select the Remove the generated LDF check box Be sure to confirm the selections by clicking the OK button Blackfin Processor and SDRAM Technology EE 326 Page 34 of 53 ANALOG DEVICES Project Options for PerformanceExample f Processor Remov is Load EA Options You currently have Startup Code and LDF files added to your project Tay Compression f you choose to remove these files from the project the following linker fy Kernel and compiler switches will be removed E Spitter DUSER_CRT PerformanceExample_basiccrt doj ds Pre build DUSE FILEIO ER Post build 2 Remove Startup Code LDF Which generated files do you want to remove Fis LDF Settings Remove the generated LDF jy System Heap Remove the generated Startup Code 5 User Heap y System Stack Do you want to iy External Memory Remove the files from the project but leave them on the disk jy Advanced Options 3 l Startup Code Settings E Cache and Memory Pro ER Processor Clock and Por ER Run time Initialization Not change anything
35. e receiver which is thrown back to the transmitter Since the lengths of SDRAM traces are short and the traces of one signal from the Blackfin processor to each of the SDRAM chips have nearly the same length this effect will not impact the SDRAM s functionality Transmitter Receiver JL Transmitter AAA Receiver Figure 15 Using series termination To avoid a second reflection from the driver transmitter the resistor must have the right value The value for the series termination resistor has to be set so that the sum of it and the output impedance of the driver equals the impedance of the trace As an equation we get the following R Z Zour whereby Zour is the output impedance of the transmitter The read command is more critical than a write command Thus place the resistor of the data line as close as possible to the SDRAM data pin Parallel Termination The alternative is to use a parallel termination Figure 16 As mentioned earlier this 1s not necessary for standard SDRAM when you follow the design guidelines at the end of this chapter Blackfin amp Processor and SDRAM Technology EE 326 Page 25 of 53 ANALOG DEVICES E Transmitter Receiver Figure 16 Using parallel termination ZA Reflection coefficent p Z tZ To keep the reflection as low as possible the parallel termination resistor Z1 should be equivalent
36. e sequential access for 1 0 1 lt 3 i for j 0 j lt 3 jt t for k 0 k lt 3 k MyArray i j k getValue be Listing 10 Accessing an array optimal Blackfin amp Processor and SDRAM Technology EE 326 Page 38 of 53 ANALOG DEVICES 7 Optimizing Power Consumption Blackfin processors are used often in portable applications or low power applications In such applications it is essential to drive the power consumption as low as possible The SDRAM boosts power consumption by a high percentage Therefore the right choice use of and configuration of SDRAM are fundamental to low power design This section provides an overview of ways to minimize power consumption 7 1 Introduction Power Consumption Figures Although various standard symbols Table 4 are used by device manufacturers to define power consumption the procedures used to measure these figures vary Thus there are differences in interpreting these values Symbo Meaning Operating current in active mode Precharge standby current ve No operating standby current I Operating current in burst mode all banks activated Auto refresh current CC5 Self refresh current CC6 Table 4 Power consumption measurement symbols 7 2 Tips for Lowering SDRAM Power Consumption Following are tips toward lowering SDRAM power consumption m Use as less SDRAM as possible m Use 1 8V or 2 5V mobile SDRAM this is not possible for all Bla
37. egisters on the stack SP ASTAT SP L3 Setup the PLL Settings Ensure no other interrupt will disturb us CLE Ril Setup the voltage regulator PO L lo VR CTL PO H hi VR CTL RO 0s DEO S w PO RO Wait the VR settings are done idle Setup the DIV of ssclk and cclk poc Do PIED IS RO CO saz WOO Setup wait cycles until PLL is set IG Ik Whe EEEE OCE NDE ROPERO 2200 83 Cz a w PO RO Setup the PLL BO ty ces We PELT OTE RO 0x2000 z w PO RO Wait the PLL settings are done idle restore interrupts equ ki Our program needs 4 MBs of RAM PO Sie OST EPEIUS APT PO H hi EBIU AMGCTL Asynchronous Memory Global Control Register Uncomment your setting RG Ox0 0H e AMBEN NONE Z No Asynchronous Memory d AMBEN BO Z 1MB Asynchronous Memory ee AMBEN BO B1 Z 2MB Asynchronous Memory if AMBEN BO B1 B2 Z 3MB Asynchronous Memory AMBEN ALL Z 4MB Asynchronous Memory W PO RO Setup the SDRAM SDRAM Refresh Rate Setting PAO a DEPTHS IDEE BONIA TO HS EO IBIS ied RO Ox406 z w PO RO DIanLfir A Drannanany nmi Dial s TEIN I i WV CA YCESSOF al ANALOG DEVICES SDRAM Memory Bank Control Register 20 el lan mew Siew PO L lo EBIU_SDBCTL RO EBCAW 9 Page size 512 EBSZ 64 64 MB of SDRAM EBE SDRAM enable Wile RO SDRAM Memory Global Control Register PO H hi EBIU SDGCT
38. emory space because you overwrite something in the other address space Therefore we define the LpF file that way so we will not place anything into the mirrored RAM MEM SDRAMO BANKO TYPE RAM START 0x00000000 END OxOOIFFFFF WIDTH 8 MEM SDRAMO BANK1 TYPE RAM START 0x00400000 END OxOOB5FFFFF WIDTH 8 MEM SDRAMO BANK2 TYPE RAM START 0x00800000 END OXOO9FFFFF WIDTH 8 MEM SDRAMO BANK3 TYPE RAM START 0x00CO0000 END OxOODFFFFF WIDTH 8 5 3 SDRAMs with 2 Banks Several SDRAMs have only two banks The hardware connection has to be like Figure 34 Addr 1 Blackfin Figure 34 Hardware connection for SDRAM with two banks BA 1s the bank selection pin of the SDRAM It must be connected with the Addr 18 of the Blackfin processor Leave Addr 19 floating Connect the other addresses as described in SDRAM Hardware Design Set the EBIU_SDBCTL SDRAM memory bank control register to 16 Mbytes The logical address space will be fragmented as shown in Figure 35 Internal Bank 1 Internal Bank O Figure 35 Fragmented logical address space So we have to use adjust the LDF file again to set up the memory space Proceed as described above Figure 36 shows an example memory space for a 16 Mbit 2 MB SDRAM MEM SDRAMO BANKO TYPE RAM START 0x00000000 END OxOOOFFFFF WIDTH 8 MEM SDRAMO BANKI TYPE RAM START 0x00400000 END OxOOAFFFFF WIDTH 8 Figure 36 Example Memory space fo
39. ent of PBSO2L for the EBIU other settings Data l OCP whiwe xs OTI NOWER HALE SD a Assign SDRAM values The low data byte is the EBIU SDGCTL register Data l CDDBG amp Control disable during bus grant off FBBRW amp Fast back to back read to write off EBUFE amp External buffering enabled off SRFS amp Self refresh setting off PSM amp Powerup sequence mode PSM first PUPSD amp Powerup start delay PUPSD off TCSR Temperature compensated self refresh at 85 EMREN Extended mode register enabled on Blackfin Processor and SDRAM Technology EE 326 Page 16 of 53 ANALOG DEVICES PSS Powerup sequence start enable PSSE on IWR 2 Write to precharge delay TWR 2 14 15 ns IRD gt RAS to CAS delay TRCD 3 15 20ns TRER Bank precharge delay TRP 2 15 20ns TRAS 6 Bank activate command delay TRAS 4 PASR BO Partial array self refresh Only SDRAM Bank0 CL gt CAS latency eiu EIE The upper 32 bit are EBIU SDBCTL 0 15 and EBIU SDRRC 16 27 Further we will Set the dummy write bit 32 which will speed up the initialization Data h 0x80000000 dummy write bit 0x406 lt lt 16 Refresh rate EBCAW 9 Page size 512 EBSZ 64 64 MB of SDRAM EBE SDRAM enable 1 otp write 0xIAa Ole LOWER HALE Data Listing 5 Initialization via PBS 2 5 Initializing Memory via Initialization Cod
40. ep mode Most of the SDRAM is needed only for the signal processing The data is absolved after processing so the banks in which the data 1s placed does not need to be refreshed 1 4 2 TCSR Temperature Compensated Self Refresh In standard SDRAMs the self refresh rate is set to the worst case scenario A high temperature will cause a higher discharge of the capacitors which requires a higher refresh rate to maintain the data But a higher refresh rate will effect higher power consumption By means of the TCsR bit the user application is able to set the self refresh rate according to the temperature which it 1s measuring 1 5 Options to Fit the SDRAM Timing Sometimes the timing parameter specification of an SDRAM does not fit the specification of the EBIU Therefore the PLL control register provides an option to delay the output signal and shift the input latch mechanism for 200 ps 15 14 13 12 1110 9 8 7 6 5 4 3 2 1 O OxFFCO 0000 io olo 1 io fi o o jo fo io o Jo fo Reset 0x1400 MSEL 5 0 EET DF Divide Frequency Multiplier Select 0 Pass CLKIN to PLL See Table 8 1 on page 8 5 for 1 Pass CLKIN 2 to PLL CLKIN VCO multiplication PLL OFF factors 0 Enable power to PLL BYPASS 1 Disable power to PLL 0 Do not bypass PLL STOPCK Stop Clock 1 Bypass PLL 0 CCLK on Output Delay 1 CCLK off 0 Do not add output delay PDWN Power Down 1 Add approximately 200 ps of delay to external memory ou
41. esh Only SDRAM Bank0O CL 3 CAS latency SCTLE S SDRAM clock enable PO RO ssync Restore registers from the stack L3 SP 4 ASTAT SP RTS Listing 6 Initialization via an initialization file Blackfin Processor and SDRAM Technology EE 326 Page 19 of 53 ANALOG DEVICES 3 Using an LDF File to Place Data and Program Code in Memory If the SDRAM is initialized before the application is loaded see SDRAM Initialization by the Values in the OTP Memory you can place data and code into the memory sections Therefore you must define a memory region in the Linker Description File LDF and inform the linker as to the data or code that is to be placed into memory Let s assume we want to place data in SDRAM bank 1 If we take a closer look into a standard Linker Description File LDF which is generated by the VisualDSP Expert Linker wizard in this example we will have 512 MB of SDRAM we see the internal SDRAM banks are named separately MEMORY MEM SYS MMRS TYPE RAM START OxFFCO0000 END OxFFDFFFFF WIDTH 8 b MEM SDRAMO BANKO TYPE RAM START 0x00000004 END OxO7ffffff WIDTH 8 MEM SDRAMO BANK1 TYPE RAM START 0x08000000 END OxOfffffff WIDTH 8 MEM SDRAMO BANK2 TYPE RAM START 0x10000000 END Ox17ffffff WIDTH 8 MEM SDRAMO BANK3 f TYPE RAM START 0x18000000 END Oxl1fffffff WIDTH 8 MEMORY Listing 7 Assigning memory We will find the memory label M
42. face to SRAM ROM FIFO flash memory and FPGA ASIC designs Page 42 of 53 EMC EMI external buffer FBBRW FPM hibernate interleaving JEDEC latency memory cycle time microstrip page page mode PCB RAS to CAS delay Blackfin amp Processor and SDRAM Technology EE 326 ANALOG DEVICES Compliance to rules and regulations controlling EMI Interference caused by electromagnetic radiation An external buffer 1s needed to drive the SDRAM command clock clock enable and address pins if they have a higher load than 50 pF The resulting capacitance is the number of input pins multiplied by the capacitance of a SDRAM input pin an input pin of the SDRAM has around 4 5 pF consult your SDRAM data sheet plus the capacitance of the PCB track Fast back to back read to write In the standard application the write command is delayed by one clock cycle after a read command is processed Fast back to back read to write enables to write directly after the read command processing without the 1 cycle delay Due to the fact that your data bus has to switch quickly between the read and write data this feature is very dependent on the capacity of your data bus This includes the number of SDRAM chips and the design of the data bus circuit paths Fast page mode A common SDRAM data access scheme A special power mode of the Blackfin processor that provided the lowest power dissipation The I O supply keeps established
43. hange the EBIU settings is by means of system services The main advantage of using the EBIU system service 1s that you can set the EBIU without any calculations And second benefit is that the changes to the EBIU are in accordance to the PLL changes so you do not need to be concerned about the actual system clock frequency The initialization is done by the adi ebiu init function We will take the same SDRAM as in the section above To perform an initialization using the system services we have to pass the SDRAM parameters to the system Therefore we are using a command structure called Apr EBIU COMMAND PAIR Table 1 To initialize the structure in our example we set the variables for the 75 as shown in Listing 3 set the sdram to 64 MB ADI EBIU SDRAM BANK VALUE bank size 0 ADI EBIU SDRAM BANK 64MB set the sdram to 9 bit Column Address Width like we see in the Address Configuration A0 A8 gt 9bits Column Address ADI EBIU SDRAM BANK VALUE bank caw 0 ADI EBIU SDRAM BANK SIZE ADI EBIU SDRAM BANK COL 9BIT 9bit CAW set the twr to 2 sclk no time ADI EBIU TIMING VALUE MyTWR 2 M a2 eyele 0 ADI EBIU TIMING UNIT PICOSEC 0 ns set refresh rate to 64ms at 8192 rows as seen in the data sheet ADI EBIU TIMING VALUE Refresh SDRAM Refresh rate 8192 JL 8192 cycles 64 ADI EBIU TIMING UNIT MILLISEC 64ms set TRAS to inns ADI EBIU TIME MyTRAS 45 ADI EBIU TIMING UNIT
44. ify the xw files in the ArchDef folder directly Use the custom board support which is described in the following paragraph With custom board support in VisualDSP release 5 0 or higher it 1s easier to set reset values in an application This feature enables developers to have multiple sets of reset settings and to change between them without having to start up VisualDSP tools again Open a text editor and place code like the following into a file and save it In this example Listing 1 the filename is My custom board reset settings xml lt xml version 1 0 standalone yes gt s lt custom visualdsp proc xml xmlns xsi http www w3 org 2001 XMLSchema instance xSi noNamespaceSchemaLocation Program Files Analog Devices VisualDSP 5 0 System ArchDef ADSP custom board xsd processor family BLACKFIN file My custom board reset settings xml gt lt l kk kc k ko k k kk ck ke ck e ck e ce e e e e x e e e e e e e ne en ene ene e e C e x e ke e e kx e kx ko kx ko kx ke ke ko ke ko kk ko ko ko ko ko ko ko k k kk lt My custom board reset settings xml aS lt l kk kc k k ko k kk ck ke nk e nk ee e e e e x e x e e e ene ene ene ene e e Ce e C e c ke kx ke kx e kx e kx ke kx ko ke ck ke ko ke ko ko kc ko ko ko ko ko ko k kkk custom register reset definitions register name EBIU SDRRC reset value 0x03A0 core Common gt register name EBIU SDBCTL reset value 0x25 core Comm
45. ing Trenches in the GND Plane Figure 27 shows a GND plane with a trench The GND plane in Figure 28 avoids having a trench Blackfin amp Processor and SDRAM Technology EE 326 Page 28 of 53 ANALOG DEVICES GND Plane Figure 27 Wrong ground plane with a trench GND Plane Figure 28 Right ground plane without a trench 4 3 7 Minimizing Back Current Paths from Vias If you are not able to avoid a direction change in a via from one layer to another try to minimize the way of the back current Figure 29 shows a signal path that runs in two directions from the via The direction change in Figure 30 is better Figure 29 Wrong layer to layer direction change Figure 30 Right avoiding a direction change Blackfin Processor and SDRAM Technology EE 326 Page 29 of 53 ANALOG DEVICES 5 Using a Blackfin Processor with Less than 16 MB of SDRAM Using less than 16 MBs 128 Mbits of SDRAM is especially important for low power applications This section provides guidance for applications that use less than 16 MBs 5 1 System Settings Adadr 1 Blackfin On the hardware side there are no special settings Just connect the address lines as described in SDRAM Hardware Design The first step in using less than 16 MB is setting the SDRAM external bank size bits of the EBIU_SDBCTL SDRAM memory bank control register to 16 Mbytes This configures the Blackfin processor s internal address to expect 16 Mbytes and the
46. ittle Distance as Possible Figure 21 shows a 4 layer PCB which does not insulate the critical signals Figure 22 shows proper insulation of a 4 layer PCB critical signals other signals VCC i GND TER other signals ritical signals iz Bold layer L As thin as possible Figure 22 Right VCC and GND planes are close together Blackfin amp Processor and SDRAM Technology EE 326 Page 27 of 53 ANALOG DEVICES 4 3 4 Insulating Critical Signals by Placing Them in the Inner Layers Figure 23 shows a 6 layer PCB in which critical signals are not insulated Figure 24 shows proper insulation other signals j other signals SX VCC Figure 23 Wrong critical signals not properly insulated other signals GND d critical signals a other signals Figure 24 Right minimize the distance between critical signals and the ground plane 4 3 5 Placing the Series Resistor Close to the SDRAM Figure 25 shows a signal path that with too many vias the series resistor is too far from the SDRAM in 26 shows a short signal path without vias an a series resistor that 1s next to the SDRAM NANN WES NNNM eun S Ss WSS NC SAS Y OND Y S US Y Figure 25 Wrong too many vias in critical signal path and series resistor is too far away L3 du NAA NAS SSK SN SS S Ta a Tha 089 708 98097080808 08 09 9989 990989 09998 9998 C Figure 26 Right the series resistor is close to the SDRAM 4 3 6 Avoid
47. k to back read to write off EBUFE amp External buffering enabled off SRFS amp Self refresh setting off PSM amp Powerup sequence mode PSM first PUPSD amp Powerup start delay PUPSD off EIS R Temperature compensated self refresh at 85 EMREN Extended mode register enabled on PSS Powerup sequence start enable PSSE on TWR 2 Write to precharge delay TWR 2 14 15 ns TRCD 3 RAS to CAS delay TRCD 3 15 20ns TRP 3 Bank precharge delay TRP 2 15 20ns TRAS 6 Bank activate command delay TRAS 4 PASR BO Partial array self refresh Only SDRAM Bank0 Cree CAS latency SCTLE SDRAM clock enable Listing 2 Initialization via registers Blackfin Processor and SDRAM Technology EE 326 Page 13 of 53 ANALOG DEVICES The code in assembly language can be found in Initialization Code Chapter 2 What will happen if we need to change the PLL settings later in the application To obtain the best memory performance we have to change our settings as well If memory performance does not matter we have to calculate the values at the worst case scenario Examples of initializing the SDRAM on the ADSP BF537 EZ KIT Lite in assembler and C and on the ADSP BF561 EZ KIT Lite in C are included together with this EE Note 2 3 Initialization Using System Services Another way to initialize the SDRAM is to handle the setup in the application itself The most comfortable way to c
48. layed by the external bus grant 1 3 2 PUPSD Power Up Startup Delay This option sets a delay of 15 system clock cycles for the power up start sequence If one processor passes the SDRAM to another processor it has to send the SDRAM into self refresh mode Once self refresh mode is engaged the SDRAM provides its own internal clocking causing it to perform its own auto refresh cycles The SDRAM must remain in self refresh mode for a minimum period equal tot The procedure for exiting self refresh mode requires a sequence of commands First cLK must be stable stable clock is defined as a signal cycling within timing constraints specified for the clock pin prior to CKE going back high When cxe is high the SDRAM must have Nop commands issued for t because this length of time is required for the completion of any internal refresh in progress To take the time period t into account a delay of 15 cycles will occur until the Blackfin processor starts its power up sequence 1 3 3 CDDBG Control Disable During Grant If you are working in a multiprocessor environment with shared memory where other devices than the Blackfin processor have access to memory this feature enables the external memory interface of the processor to additionally three state the address and data pins its memory control pins SRAS SCAS SWE SA10 and SCKE and its clock pin CLKOUT Blackfin amp Processor and SDRAM Technology EE 326 Page 7 of 53 ANAL
49. logy EE 326 Page 3 of 53 ANALOG DEVICES IPC S and Douglas Brooks approach of Zo Chapter 4 s ssesesesesessssesescesesesessesesesesesesossesescsesesossesesesesesosoesesesesese 51 liM okay Stes cub Milia e enero Mee men ae On REE tee Oe ee ee ON ER Tee On ee ene eet oe ON een OS Reena ere oe RE re ae Seen ane meee ee re oe 51 Title crs lelate ie hier mela ep acy ome aroha sce eee nr 51 Re L Mia ie TORTE 51 pesa dun cue aM crgo NO Maie RR 51 DielectrroG Constants of Printed Circuit Boards PCBS Chapter 442 aosssesssevetent cr venden v RREESEVE RN a Re eR eM EN YYS 52 Several Commonly Available Woven Gless RBOIDUIOPOSS Lamina SS yi edes dadas a d Dd V Ha TR Dd 52 List Or Non Woven or Very Low Glass Content Laminate MaLetlL3 Suave RAD ed S gH EE SA RD AR d 52 een ea le c PERRO 53 PEO E E mms 53 POCOO Lo o a TT E E i 53 Blackfin Processor and SDRAM Technology EE 326 Page 4 of 53 ANALOG DEVICES 1 Brief Introduction to SDRAM This section describes SDRAM Synchronous Dynamic Random Access Memory parameters and SDRAM related system setups This provides a base on which to build a better understanding of the EBIU External Bus Interface Unit register variables Further it will give you a foundation from which to base other decisions It is not a detailed discussion of SDRAM refer to The ABCs of SDRAM EE 126 for more det
50. ly stored in a memory location Page 44 of 53 ANALOG DEVICES Appendix B Code Examples Schematics and Excursus Initialization Code Chapter 2 Listing 12 shows an example of initialization in assembly language SDRAM Refresh Rate Setting PO H HIVEBIU ODER pO G ToO EBIU T ODRRO ROTO AO ug wIPOI RO SDRAM Memory Bank Control Register IO T gab Oe JE CP SIDTS EMEN POLL I OESTE SIDES RO EBCAW 9 Page size 512 EBSZ 64 64 MB of SDRAM EBE SDRAM enable w PO RO SDRAM Memory Global Control Register PO glk Ue INC CDC TOF POL Ike HIE SID GICAL 20 Tales ba i CDDBG amp Control disable during bus grant off FBBRW amp Fast back to back read to write oft EBUFE amp External buffering enabled off SRFS amp Self refresh setting off PSM amp Powerup sequence mode PSM first PUPSD amp Powerup start delay PUPSD off TCSR Temperature compensated self refresh at 85 EMREN Extended mode register enabled on PSS Powerup sequence start enable PSSE on TWR 2 Write to precharge delay TWR 2 14 15 ns TRCD 3 RAS to CAS delay TRCD 3 15 20ns TRP 3 Bank precharge delay TRP 2 15 20ns TRAS 6 Bank activate command delay TRAS 4 PASR_BO Partial array self refresh Only SDRAM Bank0O CES CAS latency SCTLE SDRAM clock enable RO L on CDDBG amp Control disable during bus grant off FBBRW amp Fa
51. mapped to internal SDRAM bank 1 and no other section So we will use this label to map our variable define a variable which lies in SDRAM Bank 1 pragma S CCo fM dramon pank 1b Jhexcrer sige x 0 We can do the same with our instruction code by assigning the prototypes of our functions to a section define a function prototype of a function which lies in SDRAM Bank 1 pragma SCOLION scean e Pank iO Volde roo As described in Increasing the SDRAM Performance of Your System sometimes it is useful to map a data section manually to prevent delays caused by opening and closing a page Therefore we define our own memory section in the LpF file MEM SDRAMO BANK2 TYPE RAM START 0xX02000000 T END OXO2FELEEE WIDTH s MEM SDRAMO BANK3 TYPE RAM START 0x 03000800 END OXO3EEEFEE WIDTH 8 define my own page MEM SDRAMO BANK3 PAGEO TYPE RAM START 0x03000000 END 0x030007FF WIDTH 8 In the sEcTIons part of the Linker Description File we will link all objects labeled MyDefinedMemory into this memory space sdram Dank page INPUT SECTION ALIGN 4 INPUT SECTIONS SOBJECTS MyDefinedMemory MEM SDRAMO BANK3 PAGEO Afterwards in our C C file we place our array into this memory section define an array which lies in my own defined memory space Bank 3 Page 0 pragma section MyDefinedMemory long int MyArray 100 Blackfin Processor and SDRAM Techn
52. me as rows on the SDRAM module It can also mean the number of internal logical banks usually 4 banks nowadays within an individual SDRAM device Bursting is a rapid transfer of data to a series of memory cell locations A capacitor with the primary function of stabilizing a power supply voltage especially for an adjacent device or circuit A single transaction between a memory device and the system domain of the Blackfin processor Column address strobe A control signal that latches a column address into the SDRAM control register Column address strobe before row address strobe CBR is a fast refresh function that keeps track of the next row to be refreshed Part of the memory array A bit is stored where a row and column intersect A signal induced in one wire or trace by current in another wire or trace Double data rate The data is transferred on the rising and falling edge of the clock Since the address lines keep the same data of sequential addresses are transferred Data mask signal used for masking during a write cycle There is one DQM signal per eight I Os Dynamic Random Access Memory A type of memory device usually used for mass storage in computer systems The term dynamic refers to the constant refresh the memory must have to retain data External Bus Interface Unit It provides mainly the synchronous external memory interface to SDRAM which is compliant to the PC100 and PC133 standard and an asynchronous inter
53. n glass reinforcement except teflon List of Non Woven or Very Low Glass Content Laminate Materials Information from manufacturer s data sheets Tg glass transition temperature DBV dielectric breakdown voltage er relative dielectric constant WA water absorption Blackfin amp Processor and SDRAM Technology EE 326 Page 52 of 53 ANALOG DEVICES References The ABCs of SDRAM EE 126 Rev 1 March 2002 Analog Devices Inc System Optimization Techniques for Blackfin Processors EE 324 Rev 1 July 2007 Analog Devices Inc ADSP BF533 Blackfin Processor Hardware Reference Rev 3 2 July 2006 Analog Devices Inc ADSP BF537 Blackfin Processor Hardware Reference Rev 3 0 December 2007 Analog Devices Inc ADSP BF561 Blackfin Processor Hardware Reference Rev 1 1 February 2007 Analog Devices Inc ADSP BF534 ADSP BF536 ADSP BF537 Blackfin Embedded Processor Data Sheet Rev E March 2008 Analog Devices Inc 7 A Survey and Tutorial of Dielectric Materials Used in the Manufacture of Printed Circuit Boards By Lee W Ritchey Speeding Edge for publication in November 1999 issue of Circuitree magazine Copyright held by Lee Ritchey of Speeding Edge September 1999 8 Writing Efficient Floating Point FFTs for ADSP TS201 TigerSHARC Processors EE 218 Rev 2 March 2004 9 Micron Technical Note 48 09 LVTTL DERATING FOR SDRAM SLEW RATE VIOLATIONS 10 High Speed Digital Design A Handbook of Black
54. nnections between the Blackfin processor and SDRAM 4 1 2 ADSP BF561 Processors 16 bit SDRAM m Connect the Blackfin processor s ADDR2 to the SDRAM s A1 ADDR3 to A2 etc m Connect the Blackfin processor s spow3 to the SDRAM s ao m Do not use the ADDR11 of the Blackfin processor connect SA10 to A10 Connect ADDR18 to the SDRAM s BAO Blackfin amp Processor and SDRAM Technology EE 326 Page 22 of 53 ANALOG DEVICES m Connect ADDR19 to the SDRAM s Bal m Connect SDQMO to DOML or to DoM see above m Connect SDQM1 to DOMH or to DoM see above Connect the sMsx to the cs lines when using x16 and are using more than one SDRAM to each chip one sms line when using x8 and are using more than two SDRAMs to each pair of two one sws line Buceo BF561 Figure 13 ADSP BF561 processors connections between the Blackfin processor and 16 bit SDRAM 4 1 3 ADSP BF561 Processors 32 bit SDRAM m Connect the Blackfin processor s ADDR2 to the SDRAM s ao ADDR3 to A1 etc Do not use the ADDR12 of the Blackfin connect sA10 to A10 m Connect ADDR18 to the SDRAM s Bao m Connect ADDR19 to the SDRAM s Bal m Connect SsDoMO0 to DomL of SDRAMI D0 D15 m Connect SDOM1 to DOMH of SDRAM 1 m Connect spoM3 to DoML of SDRAM2 p16 D31 m Connect spoua4 to DOMH of SDRAM2 If you are using 8 bit SDRAM m Connect spoMo to DoM of SDRAMI p0 D7 m Connect spoMo to DoM of SDRAM2 D8 D15 m Connect spoMo to DoM of SDRAMS D16 D
55. o improve system performance The first challenge is to identify the modules of your program that are relatively independent and do not need to call each other directly Separate the overlays from the program and place their machine code in the larger memory Develop an overlay manager that organizes intelligent DMA transfers of the overlays from the SDRAM to the internal memory 6 4 SDRAM Performance Items When Using Cache Code Optimizing memory for cache access means reducing cache misses We have to organize the code and data in a way that minimizes cache misses When optimizing the code for cache accesses keep the code straight as possible and declare functions that are not often used in the program code as inline This keeps the code compact and minimizes the number of cache misses Functions that are often called should be placed into internal memory if possible Data Look at the algorithm and try to find a way to perform sequential data accesses An example for a Fast Fourier Transformation FFT that accesses the data sequentially is shown in Writing Efficient Floating Point FFTs for ADSP TS201 TigerSHARCQ Processors EE 218 In C a multi dimensional array has the following order in memory here a 3 D array A ooo A oo Adon A10 Ao Aiia A020 A021 A0272 100 Aiga 02 o Aii A15 A0 A21 A53 00 Aaii 02 Adio Ajit 12 550 A54 Aja Listing 10 shows the code to fill an array by th
56. ocessor Environment Options Blackfin processors can be used in a multiprocessor environment One approach to interfacing the processors with one another is to share external memory and pass the messages via external memory to the other processors In order to provide arbitration functionality Blackfin processors have dedicated pins for this purpose To use the Blackfin processor in a multiprocessor environment with shared memory you must connect the BR BG and BGH pins to provide an access control When the external device requires access to the bus it asserts the Bus Request BR pin signal If no other request is pending the external bus request will be granted The processor will three state the data and address bus and the bus grant Bc pin signal will be asserted When the bus is granted to another external device any data or instruction fetch from the external memory will stop the processor until the bus is released and the access can be executed When the external device releases BR the processor deasserts BG and continues execution from the point at which it stopped The processor asserts the BGH pin when it is ready to start another external port access but is held off because the bus was previously granted 1 3 1 BGSTAT Bus Grant Status When the bus has been granted the BcGsTAT bit in the SDSTAT register is set This bit can be used by the processor to check the bus status to avoid initiating a transaction that would be de
57. ology EE 326 Page 21 of 53 ANALOG DEVICES 4 SDRAM Hardware Design Since the SDRAM is driven by frequencies greater than 50 MHz the hardware layout must fulfill the requirements of high speed design Nowadays hardware designs satisfy many standards concerning EMI and EMC They have to ensure the signal integrity at high frequencies and many of them are set in a low power environment Therefore the right printed circuit board PCB design is a key factor This section explains how to design the connection between the Blackfin processor and the SDRAM on a PCB 4 1 Connecting SDRAM to a Blackfin Processor Schematics Blackfin processors provide a glueless interface to SDRAM Depending on the Blackfin processor SDRAMS with a power supply requirement of 1 8V to 3 3V are supported A common design mistake occurs when is the Blackfin processor address pins are not connected to the SDRAM correctly The address lines must be connected as described next 4 1 1 ADSP BF53x Series Processors m Connect Blackfin processor s ADDR1 to the SDRAM Ao ADDR2 to A1 etc Do not use the ADDR11 of the Blackfin connect sA10 to A10 m Connect ADDR18 to the SDRAM s Bao m Connect ADDR19 to the SDRAM s BA1 m Connect ABEO to the Domt pin for 16 bit SDRAM or to pom of the chip s connected to D0 D7 m Connect ABE1 to the pomu pin for 16 bit SDRAM or to pow of the chip s connected to D8 p15 Figure 12 ADSP BF53x processors co
58. on gt register name EBIU SDGCTL reset value 0x0091998D core Common gt lt custom register reset definitions gt lt custom visualdsp proc xml gt Listing 1 Example custom board reset settings VisualDSP 5 0 Blackfin Processor and SDRAM Technology EE 326 Page 11 of 53 ANALOG DEVICES To enable this feature in VisualDSP development tools perform the following steps l From the Settings menu choose Session 2 Inthe Session Settings dialog box select Enable customizations 3 In Custom board support isle name navigate to the file named My custom board reset settings xml that contains the SDRAM reset values Whenever the processor is reset by VisualDSP tools these reset values will be set in the registers 2 2 Initialization Using Memory Mapped Registers The classical approach to initializing the SDRAM controller is to assign the values directly to the memory mapped registers MMRs As an example we take a mobile SDRAM data sheet 64ms refresh period 8K cycle K4M56163LG R B N GILIFTS 133MHz CL3 111MHz CL2 54 FBGA Pb KAMSE183LG R B NIGILAF 1H 111MHz CL2 VCMOS Pb Free K4M56163LG R B N GILIFIL 11MHz CL 3 1 B3MHz CL2 Parameter Symbol D p Ix oj onm j 1 m 1 9 1 3 41 1 1 Row active time Lm o oom o Figure 8 Example portion of a data sheet for mobile SDRAM Address configuration 16Mx16 BAD BAT1 AD A12 AD A8 Figure 9 Address config
59. opile Lon Power SDRAM OPCION dd aE E TE AE AE EEA 8 La PASE Partial Array Self Refresh nmsmnste irinenn i enia HEREDI E r ER A S r Aaaa iaraa r i ae irian Pid 8 1 4 2 TCSR Temperature Compensated Self Refresh s ssssrsesesrsssesessssrsesesesesesessssesrsesesesesessosrsrsesesesesesesseseseseseo 8 L5 Options to Fie Thea CORAM TIMIN RERO aE enaa EE E E E aE E e EE 8 teos Blackiin Orcutt 7 DORAM Inport Egualion WII CO neiesten e E 9 Lowe Blackfin Impure SDRAM O utp t Eg g ation Read J voice nbicceutdedacccteeduacudeeduducteddunsutesduccnteiencutesindenesaudestdaducsatsuans 9 fle SA 5 51 a a a A A 10 2 1 SDRAM Initialization Via an Emulator and VisualDSP4 KML EX L68 3 att to ED e e ean 10 2 4 Initialization Using Memory Mapped Beglstet8asdca emus cd uude ee Qass od tuaM dE Cid S NUMEN a tos EA UNUM Id oU dE CEE 12 p oiL MA cunt o MN Us nong oyo NES C eR COO Rm 14 2 4 SDRAM Initialization by the Values in the OTP Memory siccccscdiscicnstiacscsssiacsascdassicscdiacicnasdasseacdaanocadessieasddaciatace 16 2 9 Initializing Memory via Initialization Code Before Loading the Application e 17 3 Using an LDF File to Place Data and Program Code in Memory cissstisedssciciensastecedsschovesesscnsssesadbsessnnedodsaavenswaceniunes 20 CE SBI EN HEM E ea ies Wa ame cube NES mm ne PTO tne TO ene No eee See me ee E E eer ee 22 4 1 Connecting SDRAM to a Blackfin Processor SOhOHNAtlOS uuesssrkitrake usi tI REUS rau UR UM M REM A
60. r a 16 Mbit 2 MB SDRAM As shown there 1s a 3 MB gap in our address space Blackfin Processor and SDRAM Technology EE 326 Page 32 of 53 ANALOG DEVICES 6 Increasing the SDRAM Performance of Your System In many applications execution time 1s one of the key factors The placement of data and instructions can have a significant impact to the processing speed of your application This section presents an overview of the possible ways of increasing SDRAM performance For a system approach refer to System Optimization Techniques for Blackfin Processors EE 324 6 1 Optimal Multi Bank Accesses It is time consuming to open a page via the activate command or close a page via the precharge command Thus reducing page changeovers results in better SDRAM performance A case that applies to many applications is coping data from one array to another via memory DMA The problem occurs when both arrays are on the same internal bank If this happens within a page it will not be a problem but if the dimension of the two arrays exceeds the page size the DMA will access at least two pages Figure 37 shows how the DMA works within a bank single bank access Source Destination Source Destination Source Destination DMA DMA DMA DMA DMA DMA Ini p B i gl B Ii Bg B Activate t R Read Accesses Write Accesses P Precharge Bank 0 Bank 0 Bank 0 Bank 0 Bank 0 Bank 0 Figure 37 Accesses to one memory bank The data 1s place
61. re reset Verify all writes to target memory System reset C Reset cycle counters on run Use opcode scan method Use XML reset values C Mask interrupts during step On Emulator E sit C Do single byte memory access stall the DSP k C Disable breakpoint in shared memory messages applies to both cores a global option Figure 6 Target Options dialog box For VisualDSP release 4 5 or lower the values are taken from an xmi file extensible markup language named ADSP BF5XX proc xml where xx stands for the architecture e g AbSP BF537 proc xml Of ADSP BF561 proc xml These files are located in the install path NAnalog Devices VisualDSP X X System ArchDef directory By changing these values you can configure the settings of the EBIU Figure 7 shows a portion of a processor xmu file For more information refer to custom board support in VisualDSP Help Blackfin Processor and SDRAM Technology EE 326 Page 10 of 53 ANALOG gli TEEN PEN PET PEN PET PEN PEN PET PEY PEN PEN PEN PEN PET PEN PEN PET PET PEN PEN PEN PEN PET PEN PEN PEN PET PEN PEN PE PEN PEN PET PET PEN PET PEN PEN PET PEN PET PETTEN PET PEPEN Y l D or E 3 La E T dz z Demis s used b mila 5 di dL LJD La LA t ie A A Liha L ee e LFL zl L A A d e SS FS SS SSS FS SS SS SS SF SS SS SS SS SS SS SS SS SS SS SS SS 8 gt 4 1 register reset definitions register name EBIU_SDRRC reset value 0x03A0 core Common
62. ress the row address and bank have different bits positions in the logical address For example with a column addressing width CAW of 11 bits the row address has its LSB at bit 12 of the logical 32 bit address 31 0 This is a very important parameter if you want to access the SDRAM consciously The number of the row address depends on the size of the SDRAM To determine the column addressing width in the data sheet find how many address pins are dedicated to column addressing For a detailed overview refer to the EBIU chapter of the Blackfin processor s Hardware Reference 1 2 2 EBSZ SDHAM External Bank Size The SDRAM external bank size can be determined by the following formula Bank size x Number of Data pins x Number of Banks 8 For example the MT48LC32M16A2 has 8 Mbytes x 16 pins x 4 banks which is 536 870 912 bits equaling 64 Mbytes To use less than 16 MB refer to Using a Blackfin Processor with Less than 16 MB of SDRAM MemorySize 1 2 3 SDRAM Timing Clock Cmd Address Data gt lt CL tras tap trop Figure 2 SDRAM Timing Blackfin Processor and SDRAM Technology EE 326 Page 6 of 53 ANALOG DEVICES The SDRAM timing of SDRAM CAS Latency CL SDRAM bank activate command delay t lt SDRAM bank precharge delay t RAS to CAS delay t and write to precharge delay ty are described in detail in the EBIU chapter of your processor s Hardware Reference 1 3 Multipr
63. s which may result from Analog Devices assistance All trademarks and logos are property of their respective holders Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer to Engineer Notes ANALOG DEVICES Table of Contents INTUS IO AG cse OMEN MM MEM UI MM MEME II MEME dM MEM S l TUG oy Sm o lt E E E E eee tance eee ee eer ene ere eee 2 Ent c no sup em a E a O a E 5 te Te a a a E E E E E A E EEE E EE E E E E E ES 5 des DRAM Parameters 10 BPlackfrin SOOGLSLO S bede ebeadimenadiazuoti r aT T 6 1 2 1 EBCAW SDRAM External Bank Column Address Width e s sssesssereresersrsesenesenerersrersrsestsrsereoersrsesesesenererersrsesenes 6 1 2 2 EBSZ SDRAM External Bank Bg ues IU EN RIED RRIRP IPIE DO EDIEPPIE PI D Eee EDEN esen S PEPESE PPEP EPESES SEDE DE PPEP ES ESEP EDS MP qx SREETE 6 Mg ae DRM SUP Gutes I tema dde DM dM MEM MM MINUM MM acc MEINE EM ME UM M EE EE 6 leo MUILTDEOOSSSOT EnvriPOHHente OBLEOLDODSSGen savrRE Uv UE S E AE DUrRR I REE DRNM EM PR ITI Red E EE USED PARE RE 7 1 3 1 BGSTAT B s gms SSH aca ce asians Ee REI D ID MEI E DP dE 7 MP POP OMNES uiti we Ty m i 7 T ODDBG Cc sheng or MBs clonic Dnring 45815 apes NM md PREMIERS PNEU NENNEN remit then EU IDE 7 l9 M
64. st back to back read to write off EBUFE amp External buffering enabled off SRFS amp Self refresh setting off PSM amp Powerup sequence mode PSM first PUPSD amp Powerup start delay PUPSD off TCSR Temperature compensated self refresh at 85 EMREN Extended mode register enabled on PSS Powerup sequence start enable PSSE on TWR 2 Write to precharge delay TWR 2 14 15 ns TRCD 3 RAS to CAS delay TRCD 3 15 20ns TRP 3 Bank precharge delay TRP 2 15 20ns TRAS 6 Bank activate command delay TRAS 4 PASR BO Partial array self refresh Only SDRAM Bank0O QS CAS latency SCTLE A SDRAM clock enable POI RO Listing 12 Initialization code example in assembly language Blackfin Processor and SDRAM Technology EE 326 Page 45 of 53 ANALOG DEVICES Schematics to Interface SDRAM to the Blackfin Processor Chapter 4 The next few pages show implementation examples These schematics are given to illustrate the right connection between SDRAM and the Blackfin processor rather than as an approach to signal integrity Interf ace the Blackf in to SDRAM Document Number MT48LC 16M16 TSOP54 U2 ADSP BF537 10 cN oocordcouosow o VNo gt ooooo aaor a a z izixixi l a c alaala 7 U1A Blackfin Processor and SDRAM Technology EE 326 Page 46 of 53 ADSP BF561 in 16 Bit Mode U13A A25 os A24 Fpj A22 pe A20 754 O A19 7B3 A18 F6
65. sus Background The LpF file specifies where code and data are placed in memory space The EBIU settings configure the SDRAM controller of the Blackfin processor and specify size timing and features of the SDRAM Since the EBIU settings cannot set to that of an 8 MB SDRAM we have to set the SDRAM size to 16 MB What does this mean to the addressing We are using an SDRAM with a column address width CAW of 10 bits which means we can address 2 10 1024 columns With each column and row address we are addressing 2 bytes for x16 SDRAM Now we have set the RAM to 16 MBs 716777216 bytes which means we have a row address width of 13 memory size data width 2 addresses 16777216 2 bytes 2 10 8192 2 13 but we are using only a 8 MB RAM which has a row address width of 12 But the controller has calculated a row address width of 13 The row address and the column address are sent to the SDRAM time multiplexed Looking at your SDRAM you see 12 address lines and 2 bank address lines But the controller has calculated 13 and is using 13 Since the 13 address line is not connected you will address the same physical address independent of the state of bit 13 of the row address This is why the memory space is mirrored Blackfin Processor and SDRAM Technology EE 326 Page 31 of 53 ANALOG DEVICES For example row address 0x1000 will access the same data as row address 0x0000 It 1s critical when you place something into aliased m
66. th the desired signal by superposition Coupling The currents conducted through different traces influence each other When a changing current flows down trace A it creates a changing magnetic field that couples into trace B The coupling generates a current in trace B that is dependent upon the coupling factor The inducted current s direction 1s opposite to the current in trace A this effect is negative if two signal traces influence each other crosstalk But the effect can also be positive when the influence is between the signal line and its return line GND The coupled signal helps to boost the return signal and the returning signal boosts the primary signal Blackfin amp Processor and SDRAM Technology EE 326 Page 24 of 53 ANALOG DEVICES 4 2 2 Avoid Reflections Calculate the characteristic impedance to add the correct termination resistor There are several ways to terminate a transmission line m Series termination m Parallel termination m Thevenin termination m Termination by diodes m AC termination The most important techniques for SDRAM devices are described next Series Termination For SDRAM use a series termination Figure 15 Place the series resistor close to the output pin of the transmitter The advantage is that there will not be any DC current draw like if you are using a parallel termination This is essential for low power designs The disadvantage is that there will be a nearly 100 refection at th
67. the following linker Ty Kernel and compiler switches will be removed Eih Splitter DUSER_CRT LessMemorythan4MB_basicert doj js Pre build DUSE_FILEIO EE Post build D cplusplus 9 2 Remove Startup Code LDF S Fis LDF Settings Which generated files do you want to remove dy System Heap Remove the generated LDF dy User Heap Remove the generated Startup Code y System Stack fg External Memory Do you want to E Advanced Options Remove the files from the project but leave them on the disk E s Startup Code Settings O Remove the files from the project and Eh Cache and Memory Pro send them to the recycle bin E Processor Clock and Po Leave the files in the project but stop regenerating them dy Run time Initialization E Compiler Instrumented 4 Not change anything Figure 32 Ensuring that the LDF file will not be changed Doing so allows you to change the LDF file manually For example if we use a 64 Mbit SDRAM 8 MB the address space in the Linker Description File has MEM SDRAMO BANKO TYPE RAM START 0x00000000 END OxOOIFFFFF WIDTH 8 MEM SDRAMO BANK1 TYPE RAM START 0x00400000 END OxOOSFFFFF WIDTH 8 MEM SDRAMO BANK2 TYPE RAM START 0x00800000 END OxOO9FFFFF WIDTH 8 MEM SDRAMO BANK3 TYPE RAM START 0x00CO0000 END OxOODFFFFF WIDTH 8 Figure 33 Ensuring that the LDF file will not be changed As shown in Figure 33 there are gaps of 2 MB in our address space 5 2 1 Excur
68. tput signals Input Delay 0 Do not add input delay 1 Add approximately 200 ps of delay to the time when inputs are latched on the external memory interface 0 All internal clocks on 1 All internal clocks off Figure 3 PLL CTL register copied from Hardware Reference Blackfin Processor and SDRAM Technology EE 326 Page 8 of 53 ANALOG DEVICES Bit 6 and bit 7 Figure 3 provide a delay to the SDRAM signals Apply the output delay when the specification of a write access will be violated It will delay the data hold for 200 ps The input delay must be applied when the specification of a read access will be violated It delays the latch of the incoming data signal by 200 ps E ose CLKOUT Period tsspar Data Setup Before CLKOUT BF data sheet iac Access time from CLK SDRAM data sheet LN Input Hold time SDRAM data sheet tuspar Data Hold after CLKOUT BF data sheet tou Output Hold time SDRAM data sheet toz Delay to the output high impedance from CLK SDRAM data sheet toyz Delay from high impedance to signal from CLK SDRAM data sheet 1 5 1 Blackfin Output SDRAM Input Equation Write For SDRAM input the following equation must be valid Con lt Cuspat a UscLK gt Clock Figure 4 Timing 1 5 2 Blackfin Inout SDRAM Output Equation Read This case applies especially when setting the SDRAM clock to 133 MHz which places the timing parameters at the limit of the specification Clock
69. uration specification in the data sheet Before setting the SDRAM registers we must first configure the PLL For our example we are using a system clock frequency of 133 MHz First we calculate the refresh rate sax t RDIV eH EE tras ep Samsung K4M56163 R B N G L F Mobile SDRAM Blackfin Processor and SDRAM Technology EE 326 Page 12 of 53 ANALOG DEVICES From the data sheet 75 we get the following information fsck 133MHz tarp 64 ms NRA 8192 teas 45ns at 133 MHz tgas 6cycles f 18ns at 133 MHz t 3 cycles RDIV 133106410 6 3 1030 0625 1030 in Hex 0x406 Further we need to calculate following values tecp l8ns at 133 MHz tgep 3 cycles At Samsung fy is called tgpi lus du 52 yeles Additionally we have to enable the extended register to set the temperature and the partial self refresh The PASR can be set to following settings m PASR ALL All four SDRAM banks refreshed in self refresh m PASR B0 BI SDRAM banks 0 and 1 are refreshed in self refresh m PASR B0 Only SDRAM bank 0 is refreshed in self refresh Listing 2 shows the initialization 1n C SDRAM Refresh Rate Setting pEBIU SDRRC 0x406 SDRAM Memory Bank Control Register PEBIU SDBCIL EBCAW 9 Page size 512 EBSZ 64 64 MB of SDRAM EBE SDRAM enable SDRAM Memory Global Control Register SERBIUESDSCPS CDDBG amp Control disable during bus grant off FBBRW amp Fast bac
70. ze ADI EBIU CMD SET SDRAM BANK COL WIDTH void amp bank caw ADI EBIU CMD SET SDRAM CL THRESHOLD void amp MyCAS a ADI EBIU CMD SET SDRAM TRASMIN void amp MyTRAS ir ADI EBIU CMD SET SDRAM TRPMIN void amp MyTRP ADI EBIU CMD SET SDRAM TRCDMIN void amp MyTRCD im ADI EBIU CMD SET SDRAM TWRMIN void amp MyTWR p ADI EBIU CMD SET SDRAM REFRESH void amp Refresh lm ADI EBIU CMD SET SDRAM FBBRW void amp MyFBBRW Pe ADI EBIU CMD SET SDRAM EMREN void amp MyEMREN Is ADI EBIU CMD SET SDRAM PASR void amp MyPASR lm ADI EBIU CMD SET SDRAM TCSR void amp MyTCSR I ADI EBIU CMD SET SDRAM EBUFE void amp MyEBUFE a ADI EBIU CMD SET SDRAM CDDBG void amp MyCDDBG m ADI EBIU CMD SET SDRAM PUPSD void amp MyPUPSD j ADI EBIU CMD SET SDRAM PSM void amp MyPSM s ADI EBIU CMD END 0 Init the service and ensure that the Refresh rate is reset if fsclk is changing IRL e ele esabsb Inet sehen Wales Ee true enables automatic adjustment Listing 4 Initialization of the EBIU Blackfin Processor and SDRAM Technology EE 326 Page 15 of 53 ANALOG DEVICES Code examples that demonstrate the use of system services for the ADSP BF537 and the ADSP BF561 processors are located in the z 1 file attached to this EE Note 2 4 SDRAM Initialization by the Values in the OTP Memory Devices with One Time Programmable OTP memory ADSP BF52x and ADSP BF54x processors

Blackfin® Processor and SDRAM Technology Application

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Blackfin&reg; Processor and SDRAM Technology Application

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Blackfin® Processor and SDRAM Technology Application