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Preliminary GPM8F3232A/3216A/3208A

1. 16 bit timer T2CON 0xC8 TH2 0xCD TL2 0xCC slal lalalalalal 8 5 5 DININ A vint o 1 gt N o gt N A A A A T2EX P11 mode1 k ded e Timer 2 interrupt request CRCH 0xCB CRCL 0xCA 8 22 2 8 8 818 COl O 8 8 8 8 81 8 SE SE E ad ES I I I r r r r r r r r N D a gt w N fe o a T w N o e Figure 5 19 The block diagram of reload function for Timer 2 Generalplus Technology Inc Proprietary amp Confidential 58 AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A 5 9 3 3 Compare Functions PWM output The 16 bit value stored in a compare capture register is compared with the contents of the timer register If the count value in the timer register matches the stored value an appropriate output signal is generated at a corresponding port pin and an interrupt is requested The contents of a compare register can be considered as time stamp at which a dedicated output reacts in a predefined way either with a positive or negative transition Variation of this time stamp somehow changes the wave of a rectangular output signal at a port pi
2. 80 5 15 3 81 5 15 4 Data Transfers T 81 5 15 5 Program Brarches iini icone 83 6 ELECTRICAL 6 8 5 84 6 1 ABSOLUTE MAXIMUM RATINGS reno rrr 84 6 2 AGC CHARACTERISTICS 2526 E 84 6 3 ig 84 6 4 ADC CHARACTERISTICS T 25 0 ex i 84 12 MODE vei M 84 22 08 ERES 85 Generalplus Technology Inc 3 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary A Generalplus GPM8F3232A 321 6A 3208A 6 5 OP CHARACTERISTICS Ta 9 25 ree ed ree ede tate to Da d AR WORRY FANE TR ERU ERE ERKENNEN T E TR 85 T PACKAGE INFORMAT O N rr 86
3. 34 5 7 4 Pad Reset 35 Generalplus Technology Inc 2 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary gt Generalplus GPM8F3232A 321 6A 3208A 5 7 5 Watchdog Timer R set WDT_RST ss ves ette ee needa 35 9 6 Other Reset eer 35 5 8 WOIPORTS si E 40 5 8 1 Introduction 5 9 MODULE E 5 9 1 Introduction De TITRE 47 5 9 2 1 Timer 0 Mode 0 13 Bit Timer GCount r osi 50 5 9 2 2 Timer 0 Mode 1 16 Bit Timer Counter 51 5 9 2 3 0 Mode 2 8 bit Timer Counter with Auto reloadable 0 52 5 9 2 4 0 Mode 3 Two 8 Bit 53 5 92 5 Timer 1 Mode 0 13 Bit Timer Counter 54 5 9 2 6 Timer 1 Mode 1 16 Bit Timer Counter 55 5 9 2 7 Timer 1 Mode 2 8 Bit Timer Counter with Auto reloadable 56 5 9 2 8 56 5 9 3 2
4. 7 3 2 GPMBES216A is tet ca AAT ne A ais ec nee AT A A R AAE 8 3 3 GPMBES208A I 9 4 SIGNAL DESCRIPTIONS 10 4 1 IPIN DESCRIPTIONS iiss DE 10 4 1 1 2 2 10 412 GPM8F 92 0A MS 11 4413 20 12 4 2 P 13 5 FUNCTIONAL DESCRIPTIONS 15 CENTRABDPROGESSING UNIT SERES REA SER 15 5 1 1 CPU Introduction pow ddltucr M 5 1 3 Arithmetic Logic Unit 15 5 1 4 Accumulator A 90900000 15 jc 15 5 1 6 Program Status Word tgp ve cap sage da pasa pe de Ea Veg ree be 15 orl Program Counter PO Jarari 15 Eee rue 16 5 21 licere
5. Bit Function Description Condition 7 6 Generalplus Technology Inc 33 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A Bit Function Description Condition 5 4 AUDIOF R W AUDIO interrupt flag cleared by 1 3 ADCF R ADC interrupt flag cleared by 1 in ADCON register 2 1 R W___ Reserved 0 MERRF R W IMemory related error interrupt flag cleared by 1 Table 5 33 BIF register 5 7 Reset Sources 5 7 1 Introduction There are eight types of reset Sources for GPM8F3232A 3216A 3208A including Power On Reset POR Low Voltage Reset LVR Pad Reset RAD_RST Watchdog Timer Reset WDT_RST Software Reset S W_RST STOP mode Reset STOP_RST Flash Error Reset FLASH ERR RST and missing system clock Reset MISS CLK RST Figure 5 6 shows the block diagram of each reset source LVR POR Macro clkrun Missing Clock Detect SYSRESET RESET_pad WDT_RST S W_RST STOP_RST FLASH_ERR_RST MISS_CLK_RST PAD_RST Figure 5 6 Reset sources 5 7 2 Power On Reset POR A POR is generated when VDD is rising from Ov When VDD rises to an acceptable level 1 5V the power on reset circuit will starts a power on sequence After that the system sta
6. WOL LOW 9011 01 vol colL Voli 0 01L SYSCLK 12 clock division SYSCLK 4 selection timer counter switch Interrupt request 8 bit upper counter TO P34 TMOD 0x89 Set 9 m 5 THO 0x8C 25 25 as a 6 Figure 5 13 The block diagram of Timer 0 for Mode 2 Generalplus Technology Inc 52 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 9 2 4 Timer 0 Mode 3 Two 8 Bit Timers Counters Timer 0 in Mode 3 establishes TLO and THO as two separated Mode 3 is provided for applications requiring an extra 8 bit counters The block diagram for Mode 3 on Timer 0 is shown in timer counter When Timer 0 is in Mode 3 Timer 1 can be turned Figure 5 14 TLO uses the Timer 0 control bits GATEO off by switching it into its own Mode 3 or can still be used by the TRO and TFO THO is locked into a timer function and uses the serial channel as a baud rate generator or in any application TR1 and TF1 flags from Timer 1 and controls Timer 1 interrupt where interrupt from Timer 1 is not required THO 0x8C 8 bit upper counter Interrupt request CKCON 0x8E TLO 0x8A TCON 0x88
7. SYSCLK 12 clock division selection SYSCLK 4 8 bit upper counter TO P34 Interrupt request TMOD 0x89 GATEO P36 Figure 5 14 The block diagram of Timer 0 for Mode 3 Generalplus Technology Inc 53 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 9 2 5 Timer 1 Mode 0 13 Bit Timer Counter In this mode the Timer 1 register is configured as a 13 bit register Timer1 to be controlled by external input GATE1 P37 to facilitate As the count rolls over from all 1s to all Os Timer 1 interrupt flag pulse width measurements The 13 bit register consists of all 8 TF1 is set The counted input is enabled to the Timer1 when TR1 TCON 6 1 and either GATE1 TMOD 7 0 or GATE1 input pin P37 1 Setting GATE1 TMOD 7 1 allows the bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are indeterminate and should be ignored Figure 5 15 shows the block diagram of Timer1 for Mode 0 CKCON 0x8E TH1 0x8D TL1 0x8B SYSCLK 12 clock division selection SYSCLK 4 Interrupt request 13 bit upper counter TCON 0x88 3 T1 P35 TMOD 0x89 VaL p GATE1 P37 Figure 5 15 The block diagram of Timer 1 for Mode 0 Generalplus Technology Inc 54 AUG 03 2012 Proprietary amp Confidential
8. Table 5 47 PO register Address 0x90 Port1 Register 3 Function P13 Default 1 Function Description Condition P1 7 0 Table 5 48 P1 register Address 0 0 Port2 Register Function Default Function Description Condition P2 7 0 Port2 Table 5 49 P2 register Generalplus Technology Inc 41 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus P3 Preliminary GPM8F3232A 3216A 3208A Address 0xBO Port3 Register Bit Function Default Function Description Condition P3 7 0 Port3 Table 5 50 P3 register Address 0xA1 Port4 Register Function Default Function Description Condition P4 7 0 PO PU Port4 Table 5 51 P4 register Address 0x9A 0 pull up configuration Register Bit 5 3 2 1 Function P05 PU PU P02 PU P01 PU Default Function 1 Description 1 1 1 Condition PO PU 7 0 pull up control bits 0 floating 1 pull up Table 5 52 PO PU register Address 0 9 0 pull down configuration Register 3 2 1 Function PD P02 PD P01 PD Default
9. Function Description Condition TH1 7 0 Timer 1 Load value high byte Table 5 69 1 register TL1 Address 0x8B Timer1 Low Byte Register Bit 5 3 2 Function 1 7 0 Default Function Description Condition TL1 7 0 Timer 1 Load value low byte Table 5 70 TL 1 register Address 0x89 Timer0 1 Control Mode Register 3 Function GATEO Default 0 Generalplus Technology Inc 48 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A Function Description Condition GATE1 Gating control 0 Timer 1 enabled while TR1 control bit is set 1 Timer 1 enabled while GATE1 pin is high and TR1 control bit is set Counter or timer select bit 0 Timer mode internally clocked 1 Counter mode Timer 1 clock source is from T1 pin M1 1 0 Mode select bits of timer 1 which is tabled as Table 5 72 GATEO Gating control 0 Timer 0 enabled while TRO control bit is set 1 Timer 0 enabled while GATEO pin is high and TRO control bit is set Counter or timer select bit 0 Timer mode internally clocked 1 Counter mode Timer 0 clock source is from TO pin Mode select bits of timer 0 which is tabled as Table 5 72 Table 5 71 TMOD register Function description THO 1 operates as 8 bit timer counter with a divid
10. Generalplus Technology Inc Proprietary amp Confidential 20 AUG 03 2012 Preliminary Version 0 1 Preliminary 240 Generalplus GPM8F3232A 321 6A 3208A Address 0x83 Data Pointer Register high byte 5 3 2 Function DPTRO 15 8 Default 0 Function Description Condition DPTRO 15 8 Data pointer register DPTRO high byte Table 5 8 The DPHO register DPLO Address 0x82 Data Pointer Register low byte Bit 5 3 2 Function RO 7 0 Default 0 Function Description Condition DPTRO 7 0 Data pointer register DPTRO low byte Table 5 9 The DPLO register Address 0x85 Data Pointer 1 Register high byte 5 3 2 Function DPTR1 15 8 Default 0 Function Description Condition DPTR1 15 8 Data pointer 1 register DPTR1 high byte Table 5 10 DPH1 register DPL1 Address 0x84 Data Pointer 1 Register low byte Bit 5 3 2 Function RO 7 0 Default 0 Function Description Condition DPTR1 7 0 Data pointer 1 register DPTR1 low byte Table 5 11 The register Address 0x86 Data Pointer Select Register Bit Function Default Generalplus Technology Inc 21 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd General
11. Function Description Condition Reserved ADO 3 0 ADC output data 3 0 Table 5 101 ADOL register Address 0 5 ADC Output High Data Register 3 Function ADO 11 4 Default Generalplus Technology Inc 75 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary i Generalplus GPM8F3232A 321 6A 3208A Function Description Condition ADO 11 4 ADC output data 11 4 Table 5 102 ADOH register ADLB Address 0xF6 ADC Low Boundary register Bit 5 3 2 Function LB 7 0 Default 0 Function Description Condition ADLB ADC low boundary compare to ADC 11 4 Table 5 103 ADLB register Address 0xF7 ADC UP Boundary register 5 3 2 Function ADUBJ7 0 Default 0 Function Description Condition ADUB ADC up boundary compare to ADC 11 4 Table 5 104 ADUB register SYSCON2 Address 0xA7 SYSTEM control2 Register Bit 5 4 3 2 1 0 Function SCHMIT_DIS SCHMIT_DIS_ SCHMIT_DIS_ SCHMIT_DIS_ ADCLKX2 INT_filter_en GPIO_SSO _P3 P2 P1 PO Default 0 0 0 0 0 0 Key Code Function Description Condition ADCLKX2 ADCLK double enable bit Reserved INT filter en INTO INT2 pad filter enable bit 0 no filter 1 2us GPIO SSO GPIO SSO function enable bit Avoid
12. HR JH No operation Generalplus Technology Inc 83 Proprietary amp Confidential 0x00 AUG 03 2012 Preliminary Version 0 1 Preliminary GPM8F3232A 3216A 3208A G Generalplus 6 ELECTRICAL CHARACTERISTICS 6 1 Absolute Maximum Ratings Characteristics Ratings DC Supply Voltage 0 3V 6 0V Input Voltage Range 0 3V to V 0 3V Operating Temperature 40 to 85 C VDD Total MAX Current 100mA VSS Total MAX Current 150mA Note Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device conditions see AC DC Electrical Characteristics 6 2 AC Characteristics TA 25 C Characteristics Min Max For normal operational Test Condition 5 Frequency 24 5 1 2 24 5 1 2 2 at 2 4V 5 5V 6 3 DC Characteristics TA 25 C Characteristics Test Condition Operating Voltage Operating Current SYSCLK 24 5MHz 5 0V no load Standby Current 5 0 VDD 5 5V Input High Level 0 7 VDD VDD 5 0V Input Low Level 0 3 VDD VDD 5 0V Output High Level 0 8 VDD lon 8mA at VDD 5 0V Output Low Level 0 2 VDD lo 20mA at VDD 5 0V Input Pull High Resistor 1 30 70 VDD 5 0V In
13. Of T 58 5 9 3 3 Compare Functions PWM 22 244 42 0100 0 59 5 9 3 4 FUNCOMS ET 60 5 9 3 5 Timer 2 Related Registers idis rece red e cire 62 5 10 VARTO m LC 66 5 10 1 UARTO Mode 0 Synchronous Shift rent nnns irn 66 5 10 2 UARTO Mode 1 8 Bit UART Variable Baud Rate Timer1 Clock 67 5 10 3 UARTO Mode 2 9 Bit UART Fixed Baud 67 5 10 4 UARTO Mode 9 Bit UART Variable Baud Rate Timer1 Clock Source 67 5 10 5 WARTO Related Registers rere ser chon eater 67 5 11 9 O 5 12 ADC 5 12 1 ADG Control E 73 De OP CIRCUS 76 5 14 PR 77 5 15 AEPHABETICAL LIST OF INSTRUCTION SET erkennt e p nna dg pn gea 80 Et 80 5 15 2 Operations
14. Generalplus 44 28 24 Pin 8 bit Microcontroller with 32 16 8KB Flash Preliminary AUG 03 2012 Version 0 1 Generalplus Technology Inc reserves the right to change this documentation without prior notice Information provided by Generalplus Technology Inc is believed to be accurate and reliable However Generalplus Technology Inc makes no warranty for any errors which may appear in this document Contact Generalplus Technology Inc to obtain the latest version of device specifications before placing your order No responsibility is assumed by Generalplus Technology Inc for any infringement of patent or other rights of third parties which may result from its use addition Generalplus products are not authorized for use as critical components in life support devices systems or aviation devices systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user without the express written approval of Generalplus Preliminary gt Generalplus GPM8F3232A 321 6A 3208A Table of Contents PAGE DEI diced 5 2 FEATURES sis 5 3 BLOCK 7 3 1 GPMBF3232A c
15. Port 3 bit 0 RXDO Port 3 bit 1 TXDO Port 3 bit 2 INTO Port 3 bit 3 INT1 Port 3 bit 4 TO Timer 0 input Port 3 bit 5 T1 Timer 1 input o IN A gt N Port 3 bit 6 GATEO Timer 0 gate AUDIO N Port 3 bit 7 GATE1 Timer 1 gate AUDIO P Ground Port 2 bit 7 Port 2 bit 0 Port 2 bit 1 Port 2 bit 2 Port 2 bit 3 Port 2 bit 4 lt A gt N N N N Port 2 bit Port 2 bit 6 XTO N A N Regulator output needs 2 2uF Port 4 bit 4 Port 4 bit 3 Port 4 bit 2 SDA 2 wire serial bus data input output line Port 4 bit 1 Port 4 bit 0 N Port 0 bit 7 AN7 ADC channel 7 input SPIO RX Port 0 bit 6 AN6 ADC channel 6 input SPIO TX OP OUT Port 0 bit 5 AN5 ADC channel 5 input SPIO CLK OP V Port 0 bit 4 AN4 ADC channel 4 input SPIO CSB OP V Port 0 bit AN3 ADC channel input Port 0 bit 2 AN2 ADC channel 2 input Port 0 bit 1 ANT ADC channel 1 input Port 0 bit 0 ANO ADC channel 0 input A A e A Power 5V input A 5 Generalplus Technology Inc 10 AUG 0
16. o o a gt wo N Ld Figure 5 22 The block diagram of Timer 2 capture mode 0 for CRCL CRCH T2IF 0xC9 m og 8 6 N Interrupt request 16 bit timer TH2 0xCD TL2 0xCC Input clock i i i i i i i i B d d d B Overflow o a gt N gt o a A N gt Y Y CAPTUREx V V CAPTURE 1 P13 mE CAPTURE2 P14 CAPTURE3 P15 modei Capture x v y y 7 y CCHx 0xC3 0xC5 0xC7 CCLx 0xC2 0xC4 0xC6 Write to CCLx 8 8 8 8 8 8 8 8 838888883 SEE o a o o Figure 5 23 The block diagram of Timer 2 capture mode 0 for CCLx and 1 2 3 Generalplus Technology Inc 61 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary Generalplus GPM8F3232A 321 6A 3208A 5 9 3 5 Timer 2 Related Registers SYSCON1 Address 0xAF SYSTEM Control1 Register Bit 7 5 4 Function T2CLK SW EN SPIO EN Default 0 0 0 Key Code FF 00 Function Description Condition T2CLK SW Timer 2 timer function input frequency switch 0 SYSCLK 12 2 5 0 or SYSCLK 24 2 5 1 1 SYSCLK 1 2 5 0 or SYSCLK 2 2 5 1 Reserved EN SPI signals forward to P3 6 4 enable P3 4 SPI CLK P3 5 SPI TX P3 6 SPI SPIO EN SPI signals forward to PO 7 4 enable PO 4 SPI
17. Table 5 65 ADAEN register Generalplus Technology Inc Proprietary amp Confidential 46 AUG 03 2012 Preliminary Version 0 1 Preliminary 1 Generalplus GPM8F3232A 321 6A 3208A Address 0xF9 IOSC Control Register 7 6 5 4 3 2 1 Function XTO AEN XTI AEN XTAL PAD EN OSC SEL 1 0 CLKDIV 2 0 Default 0 0 0 0 1 0 Function Description XTO AEN XTO analog PAD enable control bit 0 can be I O PAD 1 XTO can be analog PAD XTI AEN XTI analog PAD enable control bit 0 can be I O PAD 1 XTI can be analog PAD XTAL PAD EN If using XTAL or XTAL PAD EN should be set first for selection OSC SEL 1 0 00 Internal ROSC 01 Internal ROSC 10 XTAL 11 External CLK If using XTAL OSC SEL 1 I XTAL EN should be set after XOSC is stable CLK DIV System Clock source divider CLK DIV Clock control 000 SYSCLK source 001 SYSCLK source 2 SYSCLK source 4 SYSCLK source 8 SYSCLK source 16 SYSCLK source 32 SYSCLK source 64 SYSCLK source 1 5 Table 5 66 The IOSCCON register 5 9 Timer Module 5 9 1 Introduction GPM8F3232A 3216A 3208A is equipped with three timers They TLO Ox8A TH1 0x8D TL1 0x8B Timers 0 and Timer 1 work in are Timer 0 Timer 1 and Timer 2 respectively addition Timer the same three modes except for mode 3 and the related control 2 also features
18. 2 50 ET1 EX1 ETO EXO OxAB OPCON 0x00 S TRIM VOSN OP EN OxAD SRCON OxFF P4 SR P3 SR P2 SR P1 SR SR Generalplus Technology Inc 23 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A Addr Function d sen 7 6 5 4 3 2 1 0 Code Value ir SYSCONO FF 00 0x00 LVRENB ICCOUTENB pubs N DIS EN DIS P4 OxAF SYSCON1 00 0x02 T2CLK SW EN SPIO EN OxBO P3 OxFF Port 3 OxB3 AUDCON 0x00 AUDIO AUDIOIE AUDIO EN FREQ SEL 0 4 AUDBUF 0x80 AUDBUF 7 0 OXB6 WKUEN AF 50 0x07 6 WKUEN INT5 WKUEN INT4 WKUEN INT3 WKUEN INT1 WKUEN INTO WKUEN 0 7 CONFIG BYTE OxFF LVRVSEL IOSEL cope Lock OxB8 IP 0x00 PT2 PS0 PT1 PX1 PTO 0 2 CCL1 0x00 Timer2cc compare capture 1 low byte CCH1 0x00 Timer2cc compare capture 1 high byte OxC4 CCL2 0x00 Timer2cc compare capture 2 low byte 0 5 2 0 00 Timer2cc compare capture 2 high byte 0 6 0 00 Timer2cc compare capture 3 low byte OxC7 CCH3 0x00 Timer2cc compare capture 3 high byte 0 8 2 0 00 2 5 I3FR
19. 5 9 2 8 Timer 1 Mode 3 Timer 1 in Mode 3 is has no timer function effect is the same as setting TR1 0 Generalplus Technology Inc 56 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A 5 9 3 Timer 2 Timer 2 which is a 16 bit wide register can operate as timer The additional Compare Capture Reload feature is one of the most powerful peripheral units of the core It can be used for all kinds of digital signal generation and event capturing like pulse generation pulse width modulation pulse width measuring etc Figure 5 18 shows the block diagram of compare capture function for Timer 2 T2EX P11 11 1 oi RE Reload m Interrupt MS 16 bit comparator 16 bit comparator 16 bit upper counter bit ey 16 bit comparator Compare0 INT3 Compare1 INT4 SYSCLK 12 SYSCLK 1 SYSCLK 24 SYSCLK 2 Compare rax L m Capture CCL2 CCH2 CCL1 CCH1 CRCL CRCH Figure 5 18 The block diagram of compare capture function for Timer 2 5 9 3 1 Timer Mode In timer function the count rate is derived from the oscillator frequency A 2 1 pre scaler offers the possibility of s
20. Function Description 0 0 0 Condition PO PD 7 0 PortO pull down control bits 0 floating 1 pull down Note If PO PU and PO PD are setting to 1 simultaneously PO will be output mode Table 5 53 PO PD register Address 0x9C Port1 pull up configuration Register 3 2 1 Function P13 PU P12 PU P11 PU Default Generalplus Technology Inc Proprietary amp Confidential 42 1 1 1 AUG 03 2012 Preliminary Version 0 1 G Generalplus Function Preliminary GPM8F3232A 3216A 3208A Description Condition P1_PU 7 0 Port1 pull up control bits 0 floating 1 pull up Table 5 54 P1 PU register Address 0x9D Port1 pull down configuration Register 3 2 1 Function P13 PD P12 PD P11 PD Default Function Description 0 0 0 Condition P1 PD 7 0 Port1 pull down control bits 0 floating 1 pull down Note If P1 PU and P1 PD are setting to 1 simultaneously P1 will be output mode Table 5 55 P1 PD register Address 0x9E Port2 pull up configuration Register 3 2 1 Function P23 PU P22 PU P21 PU Default Function Description 1 1 1 Condition P2 PU 7 0 P2 PD Port2 pull up control bits 0 floating 1 pull up Table 5 56
21. eh 5 3 o N N gt Interrupt Figure 5 21 The block diagram of compare mode 1 for Timer 2 5 9 3 4 Capture Functions Each of compare capture registers from CC1 CC2 and CC3 to CRC register can be used to latch the current 16 bit value of the Timer 2 registers TL2 and TH2 provided for this function Two different modes are Capture mode 0 In mode 0 an external event latches Timer 2 contents to a dedicated capture register The external event causing a capture is for the CC registers 1 to 3 a positive transition on pins CAPTURE1 to CAPTURE3 for the CRC register a positive or negative transition on the CAPTUREO pin depending on the bit IBFR of T2CON If the I3FR flag is cleared a capture occurs in response to a negative transition otherwise a capture occurs in response to a positive transition on pin Capture mode 1 In mode 1 a capture will occur upon writing to the low order byte of the dedicated 16 bit capture register This mode is provided to allow software reading of Timer 2 contents on the fly capture occurs in response to a write instruction to the low order byte of a capture register write to register signal e g write to CRCL is used to initiate a capture The value written to the dedicated capture register is irrelevant for this
22. 0 the whole chip memory is protected and any page erase or program by two wire serial interface is not allowed The only thing user can do is to erase whole chip Figure 5 1 shows the program memory map of 32KB 16KB 8KB Flash After each reset CPU starts execution in the program memory at location 0 0000 Each interrupt has its own start address for service routine Flash memory can be programmed in system through the SCK SDA interface or by software using the MOVX instruction when PWE 1 User can refer to the example code in the programming guide for the procedure of write and erase operations Flash data cannot be programmed from 40 to a 1 and only erase operation can realize it Therefore flash data would typically be erased set to OxFF before being programmed The write and erase operations are executed by using Pseudo idle mode to be automatically timed by hardware without data polling to determine the end of the write and erase operation For software security consideration user can set the programmable Flash level by FL LEVEL register to limit the code area that avoids inadvertently erased or written by software the protected region is called READONLY PAGE Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A CONFIG_BYTE LAST_PAGE Code Area Ox7FFF 32KB 0x7C00 31KB Code Ar
23. 10 0 17 Overflow flag 11 Bank 3 data address 0x18 0x1F General purpose flag 1 Parity flag Table 5 3 The PSW register 5 2 Memory Organization 5 2 1 Introduction The GPM8F3232A 3216A 3208A has three separated address spaces for program memory and data memory The program memory is on chip re programmable Flash memory and contains up to 32 16 8K bytes spaces The data memory is divided into 1K 512 256 bytes of external RAM 256 bytes IDM with 128 bytes of SFR which can be read and written The upper IDM and SFR use the same access address in different access ways which are described in Figure 5 2 5 2 2 Program Memory Allocation The program memory allocation is divided into two parts including The GPM8F3232A 3216A 3208A implements 32 16 8KB memory size It begins at address 0 0000 and ends at address Ox7FFF OxSFFF Ox1FFF space between 0x0000 and Ox7BFF Ox3BFF Ox1BFF is used for code area and the code area and last page The address address space between 0x7C00 0x3C00 0x1C00 and Ox7FFF Ox3FFF Ox1FFF is called LAST PAGE which cannot be erased by software reserves for constants storage The last address Ox7FFF Ox3FFF Ox1FFF is used for CONFIG BYTE whose definition of each bit is described in Table 5 4 This CONFIG BYTE value can be read from CONFIG BYTE register 0xB7 User can lock the whole chip by CONFIG BYTE 0 If BYTE 0 is programmed to be
24. 6 13 14 Note1 Interrupt is also generated at falling edge of T2EX pin while 2 bit is set This interrupt doesn t set TF2 flag but EXF2 only and uses 0x2B vector Note2 External interrupt pins are activated at low level or by a falling edge Table 5 22 Summaries of all interrupt sources Address 0xB8 Interrupt Priority Register Function Description Condition Reserved Timer 2 priority level control 1 high level UARTO priority level control 1 high level Timer 1 priority level control 1 high level INT1 priority level control 1 high level Timer 0 priority level control 1 high level INTO priority level control 1 high level Table 5 23 IP register Address 0 8 Extended Interrupt Priority Register Bit 3 2 1 Function 5 4 Default 0 0 0 Description Condition Reserved Reserved Watchdog priority level control 1 high level INT6 Compare3 priority level control 1 high level INT5 Compare2 priority level control 1 high level INT4 Compare1 priority level control 1 high level priority level control 1 high level Reserved Table 5 24 EIP register Generalplus Technology Inc 30 AUG 03 2012 Proprietary amp Con
25. 8 bit Figure 5 30 Master Mode POLARITY 1 PHASE 0 SPI CSB SPI CLK 8 bit Figure 5 31 Master Mode POLARITY 1 PHASE 1 Address OxAF SYSTEM Control1 Register 7 5 4 3 2 Function T2CLK SW EN SPIO EN Default 0 0 0 0 0 Key Code Function Description Condition T2CLK SW Timer 2 timer function input frequency switch 0 SYSCLK 12 2 5 0 or SYSCLK 24 2 5 1 1 SYSCLK 1 2 5 0 or SYSCLK 2 2 5 1 Reserved SPI signals forward to P3 6 4 enable P3 4 SPI P3 5 SPI TX P3 6 SPI RX Generalplus Technology Inc 71 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Function Preliminary GPM8F3232A 3216A 3208A Description Condition SPIO_EN SPI signals forward to PO 7 4 enable SPI CSB PO B SPI PO 6 SPI TX PO 7 SPI Reserved Table 5 94 SYSCON1 register Address OxFC SPI Control Register 7 5 4 3 0 Function POLARITY SPI SEL 1 0 CSB KEEP SPI START Default 0 Function 0 0 0 Description Condition 0 POLARITY SPI CLK initial state 0 low state 1 high state PHASE SPI CLK type control 0 rising sample 1 falling sample SPI CLK SE
26. 85 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 7 PACKAGE INFORMATION 7 1 Ordering Information Product Number Package Type GPM8F3232A QLO1x Halogen Free Package GPM8F3216A HS05x Halogen Free Package GPM8F3208A HS10x Halogen Free Package Note1 Package form number x 1 9 serial number 7 2 Package Information LQFP 44 GAGE PLANE SEATING PLANE Millimeter Nom 12 00 BSC 10 00 BSC 12 00 BSC 10 00 BSC 0 80 BSC 0 37 0 60 1 00 REF 3 5 Generalplus Technology Inc 86 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus SOP28 Preliminary GPM8F3232A 3216A 3208A lt GAUGE PLANE SEATING PLANE x Millimeter Nom Generalplus Technology Inc Proprietary amp Confidential 87 AUG 03 2012 Preliminary Version 0 1 Preliminary Generalplus GPM8F3232A 321 6A 3208A SOP24 0 020X45 GAUGE PLANE SEATING PLANE Millimeter Generalplus Technology Inc 88 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary 1 Generalplus GPM8F3232A 321 6A 3208A 8 DISCLAIM
27. AN5 ADC channel 5 input SPIO_CLK OP V Port 0 bit 4 AN4 ADC channel 4 input SPIO OP V N A N Port 0 bit 3 AN3 ADC channel 3 input Port 0 bit 2 AN2 ADC channel 2 input Port 0 bit 1 1 channel 1 input EN Generalplus Technology Inc 11 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 4 1 3 GPM8F3208A Type Input O Output S Supply Pin Name Description P02 Port 0 bit 2 AN2 ADC channel 2 input VCC Power 5V input P12 Port 1 bit 2 INT3 CAPTUREO COMPARE2 PWM2 P13 Port 1 bit 3 INT4 CAPTURE1 COMPARE3 PWM3 P15 Port 1 bit INT6 CAPTURE3 RESET P30 P31 P32 VSS P21 P22 P23 P24 P25 P26 VREG P42 P41 P07 P06 P05 P04 P03 RESET signal high active SCK 2 wire serial bus clock input line Port 3 bit 0 RXDO Port 3 bit 1 TXDO Port 3 bit 2 INTO IN A N Ground Port 2 bit 1 Port 2 bit 2 Port 2 bit 3 Port 2 bit 4 Port 2 bit 5 XTI Port 2 bit 6 eX N A Regulator output needs 2 2uF Cap Port 4 bit 2 SDA 2 wire serial bus data input output line Port 4 bit 1 Port 0 bit 7 AN7 A
28. Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 9 2 6 Timer 1 Mode 1 16 Bit Timer Counter Mode 1 is the same as Mode 0 except that the timer register is Figure 5 16 running with all 16 bits block diagram of Mode 1 is shown in CKCON 0x8E TH1 0x8D TL1 0x8B SYSCLK 12 clock division selection SYSCLK 4 timer counter switch Interrupt request 16 bit upper counter T1 P35 TMOD 0x89 TCON 0x88 GATE1 P37 Figure 5 16 The block diagram of Timer 1 for Mode 1 Generalplus Technology Inc 55 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 9 2 7 Timer 1 Mode 2 8 Bit Timer Counter with Auto reloadable Function Mode 2 configures the timer register as an 8 bit counter TL1 with not only sets TF1 but also reloads TL1 with the contents of TH1 automatic reloads as shown in Figure 5 17 Overflow from TL1 which is loaded by software The reload leaves TH1 unchanged CKCON 0x8E TL1 0x8B LOM WIL WOL SYSCLK 12 clock division selection SYSCLK 4 timer counter switch Interrupt request 8 bit upper counter T1 P35 TCON 0x88 TH1 0x8D GATE1 P37 Figure 5 17 The block diagram of Timer 1 for Mode 2
29. T2R1 T2RO T2CM T2 210 OxC9 21 0 00 EXEN2 EXF2 TF2 OxCA CRCL 0x00 CRC register Low byte OxCB CRCH 0x00 CRC register High Byte OxCC TL2 0x00 Timer 2 Load value low byte OxCD TH2 0x00 Timer 2 Load value high byte OxCE CCEN 0x00 CMH3 CML3 CMH2 CML2 CMH1 CML1 CMHO CMLO OxDO PSW 0x00 FO RS1 RSO F1 P OxD8 WDCON 0x00 WDIF WTRF EWT RWT OxEO ACC 0x00 ACC register OxE8 EIE 0x00 EWDI EINT6 EINT5 EINT4 EINT3 OxEB TA 0x00 Timed Access protection register 0xaa 3 0x55 OxEC FLASHCON 0x00 M ERASE P PROG OxED FL LEVEL 0x00 FLASH LEVEL 5 0 OxEF KEYCODE 0x00 KC7 KC6 KC5 4 KC3 KC2 KC1 KCO OxFO B 0x00 B register OxF 1 ADCON 0x00 WINF READYF WIN _SEL WINIE ADIE PSIDLE START OxF2 ADCFG 0 00 AD BITSEL CH SEL 2 0 SHCLK 1 0 ADCLK 1 0 OxF3 ADAEN 0x00 7 AEN 6 AEN P05 04 AEN 2 AEN 1_ P00 AEN OxF4 ADOL ADO 3 0 OxF5 ADOH ADO 11 4 OxF6 ADLB 0x00 ADLB 7 0 OxF7 ADUB 0x00 ADUBJ7 0 OxF8 EIP 0x00 PWDI 6 5 PINTA PINT3 OxF9 IOSCCON 0x09 AEN XTI AEN OSC SEL 1 0 CLKDIV 2 0 OxFA IOSCTO 0x18 TEMP TRIM 2 0 XFCN 2 0 Generalplus Technology Inc 24 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary eid Generalplus GPM8F3232A 321 6A 3208A Function IOSCT1 OSC TRIM 2 0 SC TUNE 4 0 P
30. Blei E 16 5 2 2 Program 16 5 2 3 Data Memory AllOCATOM 18 5 2 4 Memory Related Sf Es 19 5 2 4 1 Program Write Enable Bit 5 2 4 2 Data Pointer Registers te dee ended eeu crier dre ee ru lesa p Uer sake ana Vea a Ou spur moScceduen se e 19 5 9 SPECIAL FUNCTION REGISTERS SER e 22 5 4 GLOCK SOURCE xe 25 POWER SAVING MODE ifsc ERA 27 Ds Delis pe 27 5 52 IDLE M 27 5 5 3 M MOG eis cs ccc 27 5 6 INTERRUPT SYSTEMS 29 sno ml 29 mm 34 5 7 1 5 7 2 Power On Reset POR 5 7 3 Low Voltage Reset
31. CSB PO 5 SPI PO 6 SPI TX PO 7 SPI Reserved Table 5 75 SYSCON1 register T2CON Address 0xC8 Timer2 Configuration Register Bit 3 2 Function T2RO T2CM Default 0 0 Bit Function Type Description Condition 7 T2PS R W Pre scaler selection bit 0 SYSCLK 12 or SYSCLK 1 1 SYSCLK 24 or SYSCLK 2 6 I3FR R W Interrupt edge activity selection bit of compare 0 function in combination with capture 0 function and register CRC Compare 0 0 a negative transition on compareO output can generate interrupt 1 a positive transition on compareO output can generate interrupt Capture 0 0 capture to CRC register occurs on a positive transition of CAPTUREO pin 1 capture to CRC register occurs on a positive transition of CAPTUREO pin 5 R W Reserved 4 3 T2R 1 0 R W Timer 2 reload mode selection bit T2R1 T2RO Function 0 X Reload disabled 1 0 Mode 0 auto reload upon Timer 2 overflow 1 1 Mode 1 reload upon falling edge at pin T2EX Generalplus Technology Inc 62 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary i Generalplus GPM8F3232A 321 6A 3208A Function Description T2CM Condition Compare mode select bit for registers CRC CC1 CC2 and CC3 0 compare mode 0 is selected 1 compare mode 1 is selected T21 1 0 Timer 2 input selec
32. Compare Capture Reload function All of these registers TMOD 0x89 0 88 and three timers are up count timers and 16 bit timer counters Each registers the timer mode timer registers are incremented timer s function is described in the following sections every 4 12 SYSCLK periods depends on 0 8 setting when appropriate timer is enabled the counter mode the 5 9 2 Timer 0 1 timer registers are incremented every falling transition on theirs Timer 0 and Timer 1 are fully compatible with the standard 8051 corresponding input pins TO or T1 The input pins are sampled timers Each timer consists of two 8 bit registers THO 0x8C every CLK period Generalplus Technology Inc 47 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary 240 Generalplus GPM8F3232A 321 6A 3208A Address 0x8C 0 High Byte Register Bit 5 3 2 Function 0 7 0 Default Function Description Condition THO 7 0 Timer 0 Load value high byte Table 5 67 THO register TLO Address 0x8A Low Byte Register Bit 5 3 2 Function TLO 7 0 Default Function Description Condition TLO 7 0 Timer 0 Load value low byte Table 5 68 TLO register Address 0x8D Timer1 High Byte Register Bit 5 3 2 Function 1 7 0 Default
33. Generalplus Technology Inc 31 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary A1 Generalplus GPM8F3232A 321 6A 3208A Function Description Condition Reserved Table 5 27 EIE register TCON Address 0x88 Timer0 1 Configuration Register Bit Function Default Function Description Condition TF1 Timer 1 interrupt overflow flag TR1 Timer 1 run control bit 0 disabled 1 enabled TFO Timer 0 interrupt overflow flag TRO Timer 0 run control bit 0 disabled 1 enabled IE1 INT1 interrupt flag IT1 INT1 level at 0 edge at 1 sensitivity IEO INTO interrupt flag ITO INTO level at 0 edge at 1 sensitivity Table 5 28 TCON register Address 0xC9 Timer 2 Interrupt Flag Register Bit Function Default Function Description Condition Reserved Timer 2 external reload interrupt enable 0 external reload interrupt is disabled 1 external reload interrupt is enabled Timer 2 external reload flag Cleared by the software Timer 2 overflow flag Cleared by the software Table 5 29 T2IF register WDCON Address 0xD8 Watchdog Control Register Bit 3 2 Function WDIF WTRF Default 0 0 Bit Function Type Description Condition 7 4 R W Reser
34. P2 PU register Address 0x9F Port2 pull down configuration Register Bit 5 3 2 1 Function P25 PD P23 PD P22 PD P21 PD Default Function 0 Description 0 0 0 Condition P2 PD 7 0 Port2 pull down control bits 0 floating 1 pull down Note If P2 PU and P2 PD are setting to 1 simultaneously P2 will be output mode Table 5 57 P2 PD register P3 PU Address 0xA2 Port3 pull up configuration Register Bit 5 3 2 1 Function P35 PU P33 PU P32 PU P31 PU Default Generalplus Technology Inc Proprietary amp Confidential 1 43 1 1 1 AUG 03 2012 Preliminary Version 0 1 G Generalplus Function Preliminary GPM8F3232A 3216A 3208A Description Condition P3_PU 7 0 Port3 pull up control bits 0 floating 1 pull up Table 5 58 P3_PU register Address 0xA3 Port3 pull down configuration Register 3 2 1 Function P33 PD P32 PD P31 PD Default Function Description 0 0 0 Condition PD 7 0 Port3 pull down control bits 0 floating 1 pull down Note If P3 PU and PD are setting to 1 simultaneously will be output mode Table 5 59 P3 PD register Address 0xA4 Port4 pull up configuration Register 3 2 1 Function P43_PU P4
35. Reserved Division selection of the system clock that drives Timer 1 0 Timer 1 uses a divide by 12 of the system clock frequency 1 Timer 1 uses a divide by 4 of the system clock frequency Division selection of the system clock that drives Timer 0 0 Timer 0 uses a divide by 12 of the system clock frequency 1 Timer 0 uses a divide by 4 of the system clock frequency Reserved Table 5 74 CKCON register 5 9 2 1 Timer 0 Mode 0 13 Bit Timer Counter As the count rolls over from all 1s to all Os Timer O interrupt flag TFO is In this mode Timer 0 is configured as a 13 bit register set The counted input is enabled to the Timer 0 when TRO TCON 4 1 and either GATEO TMODI 3 0 or input pin P36 1 Setting 1 allows the Timer 0 to be controlled by external input GATEO P36 to facilitate pulse width measurements The 13 bit register consists of all 8 bits of THO and the lower 5 bits of TLO The upper 3 bits of TLO are indeterminate and should be ignored Figure 5 11 shows the block diagram of Timer 0 for Mode 0 0 8 THO 0x8C TLO 0x8A a lalalzlz z Aalajajajajaia a 5 5 5 2 2 5 5 5 55558555 1 SYSCLK 12 clock division SYSCLK 4 selection timer Interrupt request c
36. Table 5 38 CKCON register Generalplus Technology Inc 37 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary Generalplus GPM8F3232A 321 6A 3208A KEYCODE Address OxEF KEYCODE Register Bit Function Default Function Description Condition KEYCODE 7 0 KEYCODE register Note Some protected registers are needed to write correct key code to KEYCODE register before write data to them Table 5 39 KEYCODE register Address 0x87 Power Configuration Register 5 3 Function CPU IDLE STOP RST EN Default 0 0 Function Description Condition SMODO UARTO double baud rate bit when clocked by Timer1 Reserved CPU IDLE IDLE mode enable bit 0 IDLE mode disabled 1 IDLE mode entered Program Write Enable PWE 0 Disable Flash write activity during MOVX instruction 1 Enable Flash write activity during MOVX instruction STOP RST EN Wakeup state selection bit 0 Next instruction state after wakeup 1 Reset state afer wakeup Reserved STOP mode enable bit 0 Disabled 1 Enabled Reserved Table 5 40 PCON register Address 0 8 Flash Error RESET Enable Control Register Bit 7 6 5 4 3 2 1 0 Function CB P ENB LP E FLASH FLOW ENB XADDR CHIP ENB MISS ERR Defaul
37. amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A ADC Related Register Address OxF1 ADC Control Register 6 5 3 1 Function READYF WIN_SEL ADIE PSIDLE Default 0 0 0 0 Function Description Condition WINF Window detect flag cleared by 1 READYF ADC transfer ready flag cleared by 1 WIN SEL ADC output window selection 0 ADC output is between ADLB and ADUB 1 ADC output isn t between ADLB and ADUB ADC window interrupt enable ADC transfer ready interrupt enable Reserved PSIDLE IDLE mode enable bit ADC start transfer with suspending CPU clock START ADC start transfer control Table 5 98 ADCON register Address 0xF2 ADC Configuration Register 7 5 3 2 Function AD_BITSEL CH SEL 2 0 SHCLK 1 0 LK 1 0 Default 0 0 Function Description Condition AD BITSEL 0 8 bit ADC 1 12 bit ADC CH SEL 2 0 ADC channel selection POO is selected P01 is selected 2 is selected is selected P04 is selected PO5 is selected 6 is selected PO7 is selected SHCLK 1 0 ADC sample and hold period 0 2T of ADCLK 1 4T of ADCLK 2 8T of ADCLK 3 16T of ADCLK N o ADC clock selection 0 conversion clock 3 0625MHz Fosc 8 1 ADC conversion clock 7 1 53MHz Fosc 16 2 ADC conversion clock 765 625
38. direct byte to A with carry flag 0x35 ADDC A Ri Add indirect RAM to A with carry flag 0x36 0x37 ADDC A data Add immediate data to A with carry flag 0x34 SUBB A Rn Subtract register from A with borrow 0x98 0x9F SUBB A direct Subtract direct byte from A with borrow 0x95 SUBB A Ri Subtract indirect RAM from A with borrow 0 96 0 97 SUBB A data Subtract immediate data from A with borrow 0x94 INCA Increment accumulator 0x04 INC Rn Increment register 0x08 0x0F INC direct Increment direct byte 0x05 INC Ri Increment indirect RAM 0x06 0x07 DECA Decrement accumulator 0x14 DEC Rn Decrement register 0x18 0x1F DEC direct Decrement direct byte 0x15 DEC Ri Decrement indirect RAM 0x16 0x17 INC DPTR Increment data pointer MUL Multiply A and B 0 4 DIV A B Divide A by B 0x84 DAA Decimal adjust accumulator 5 15 2 Logic Operations 0xD4 Proprietary amp Confidential Mnemonic Description Code Bytes Cycles ANL A Rn AND register to accumulator 0x58 0x5F 1 1 ANL A direct AND direct byte to accumulator 0x55 2 2 ANLA Ri AND indirect RAM to accumulator 0x56 0x57 1 2 ANL A data AND immediate data to accumulator 0x54 2 2 ANL direct A AND accumulator to direct byt
39. rox Ee cedente gm 86 7 2 PACKAGE INFORMATION 12 86 8 DISCLAIMER 89 9 dauklenWHylkxuehi dee R 90 Generalplus Technology Inc 4 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A 44 28 24 PIN 8 BIT MICROCONTROLLER WITH 32 16 8KB FLASH 1 GENERAL DESCRIPTION The GPM8F3232A 3216A 3208A highly integrated microcontroller which integrates a pipelined 1T 8051 CPU 1K 512 256 byte XRAM 256 byte IDM SRAM and 32 16 8K byte program Flash It includes 34 24 20 programmable multi functional 1 0 1 2 UARTO SPI master built in OP audio and one up to 8 channel of 12 bit ADC for general purpose application It operates over a wide voltage range of 2 4V 5 5V with different clock sources has two modes in power management unit Moreover there is one on chip debug circuit with two pins to facilitate full speed in system debug The detail is described in the following sections 2 FEATURES CPU High speed high performance 1T 8051 10096 software compatible with industry standard 8051 Pipeline RISC architecture enables to execute instructions 10
40. 1 Only P37 is output as AUDIO P Reserved CLKOUT EN Clock output enable bit SYSCLK is output on P35 CCOUTENB Disable output function of compare mode in Timer2 0 P1 3 1 compare3 compare2 compare1 1 P1 3 1 is GPIO 5 DIS P4 P4 Schmitt trigger function disable control bit Table 5 109 SYSCONO register Generalplus Technology Inc Proprietary amp Confidential 78 AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A AUDIO_CNT 8 hff AUDBUFT 7 0 AUDIO P AUDIO If AUDCON 7 0 8 h09 Audio 24KHz output AUDIO CNT 8 hff AUDBUFT 7 0 AUDIO P AUDIO N If AUDCON 7 0 8 h0A Audio 32KHz output Figure 5 35 The diagram of P36 AUDIO and P37 AUDIO P output for audio application Generalplus Technology Inc 79 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary GPM8F3232A 3216A 3208A G Generalplus 5 15 Alphabetical List of Instruction Set 5 15 1 Arithmetic Operations Mnemonic Description Code ADD Add register to accumulator 0x28 0x2F ADD A direct Add direct byte to accumulator 0x25 ADD A Ri Add indirect RAM to accumulator 0x26 0x27 ADD A data Add immediate data to accumulator 0x24 ADDC A Rn Add register to accumulator with carry flag 0x38 0x3F ADDC A direct Add
41. 2_PU P41_PU Default Function Description 1 1 1 Condition P4_PU 7 0 P4 PD Port4 pull up control bits 0 floating 1 pull up Table 5 60 P4 PU register Address 0xA5 Port4 pull down configuration Register Bit 5 3 2 1 Function P45 PD P43 PD P42 PD P41 PD Default Function 0 Description 0 0 0 Condition PD 7 0 Port4 pull down control bits 0 floating 1 pull down Note If P4 PU and P4 PD are setting to 1 simultaneously will be output mode Table 5 61 P4 PD register Address 0xAD Slew Rate Control Register 3 2 Function P3 SR P2 SR Default 1 1 Generalplus Technology Inc Proprietary amp Confidential 44 AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A Function Description Condition Reserved Port4 slew rate control bit 0 slew rate control disable 1 slew rate control enable 30ns Port3 slew rate control bit 0 slew rate control disable 1 slew rate control enable 30ns Port2 slew rate control bit 0 slew rate control disable 1 slew rate control enable 30ns Port1 slew rate control bit 0 slew rate control disable 1 slew rate control enable 30ns PortO slew rate control bit 0 slew rate contro
42. 3 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary 1 Generalplus GPM8F3232A 321 6A 3208A Pin Name LQFP44 Description P11 42 Port 1 bit T2EX COMPARE1 PWM1 P12 43 Port 1 bit 2 INT3 CAPTUREO COMPARE2 PWM2 P13 44 Port 1 bit 3 INT4 CAPTURE1 COMPARE3 PWM3 4 1 2 GPM8F3216A Type Input Output S Supply Pin Name Description 00 Port 0 bit 0 ANO ADC channel 0 input VCC Power 5V input P12 Port 1 bit 2 INT3 CAPTUREO COMPARE2 PWM2 P13 Port 1 bit 3 INT4 CAPTURE1 COMPARE3 PWM3 P14 Port 1 bit 4 INT5 CAPTURE2 P15 Port 1 bit 5 INT6 CAPTURE3 RESET P30 P31 P32 P33 VSS P21 P22 P23 P24 P25 P26 VREG P42 P41 P07 P06 P05 P04 P03 P02 P01 RESET signal high active SCK 2 wire serial bus clock input line Port 3 bit 0 RXDO Port 3 bit 1 TXDO Port 3 bit 2 INTO Port 3 bit 3 INT1 j gt o N Ground Port 2 bit 1 Port 2 bit 2 Port 2 bit 3 Port 2 bit 4 Port 2 bit 5 XTI Port 2 bit 6 wo A N Regulator output needs 2 2uF Port 4 bit 2 SDA 2 wire serial bus data input output line Port 4 bit 1 Port 0 bit 7 AN7 ADC channel 7 input SPIO_RX Port 0 bit 6 AN6 ADC channel 6 input SPIO TX OP OUT Port 0 bit 5
43. 6A 3208A Address 0xB7 CONFIG_BYTE Register Bit 5 0 Function LVRVSEL CODE Lock Default Function 1 1 Description Condition Reserved LVRVSEL LVR voltage level selection 0 3 9V 1 2 2V Reserved IOSEL IO initial state selection bit 0 Input pull high 1 floating CODE Lock 0 CODE is locked 1 CODE is unlocked Table 5 34 The CONFIG BYTE register Address OxAE SYSTEM 10 Register 7 5 4 3 2 1 0 Function LVRENB AUDIO DIS CLKOUT EN CCOUTENB SCHMIT DIS P4 Default 0 0 0 0 0 0 0 Key Code FF 00 Function Description Condition LVRENB LVR enable control 0 enable LVR function 1 disable LVR function Reserved AUDIO N DIS AUDIO N disable bit available only if audio function is enabled 0 P36 P37 are output simultaneously as AUDIO 1 Only P37 is output as AUDIO P Reserved CLKOUT EN Clock output enable bit SYSCLK is output on P35 CCOUTENB Disable output function of compare mode in Timer2 0 P1 3 1 compare3 compare2 compare1 1 P1 3 1 is GPIO 5 DIS P4 WDCON P4 Schmitt trigger function disable control bit Table 5 35 SYSCONO register Address 0 08 Watchdog Control Register Bit 3 2 Function WDIF WTRF Default 0 0 Gen
44. 8F3232A 321 6A 3208A 5 15 5 Program Branches Mnemonic Description Code ACALL addr11 Absolute subroutine call 0 11 0 1 LCALL addr16 Long subroutine call 0 12 Return from subroutine 0x22 RETI Return from interrupt 0x32 AJMP addr11 Absolute jump 0 01 0 1 LJMP addr16 Long jump 0x02 SJMP rel Short jump relative address 0x80 N N JMP A DPTR Jump indirect relative to the DPTR 0x73 JZ rel Jump if accumulator is zero 0x60 JNZ rel Jump if accumulator is not zero 0x70 JC rel Jump if carry flag is set 0x40 JNC Jump if carry flag is not set 0x50 JB bit rel Jump if direct bit is set 0x20 JNB bit rel Jump if direct bit is not set 0x30 JBC bit direct rel Jump if direct bit is set and clear bit 0x10 direct rel Compare direct byte to A and jump if not equal 0xB5 CJNE A data rel Compare immediate to A and jump if not equal 0xB4 CJNE Rn data rel Compare immediate to reg and jump if not equal 0xB8 0xBF CJNE Ri data rel Compare immediate to ind and jump if not equal 0 6 0 7 DJNZ Rn rel Decrement register and jump if not zero 0xD8 0xDF DJNZ direct rel Decrement direct byte and jump if not zero OxD5 IN j j IN N j gt
45. ASHERRF register Address 0x94 RESET Status Flag Register Bit 6 5 4 3 2 1 0 Function MISS CLK RST STOP RST FLASH ERR S W RST RST RST RAD RST Default 0 Function 0 0 0 0 Description 0 0 Condition Reserved 155 RST RESET from system clock missing clock STOP RST RESET from STOP mode FLASH ERR RST RESET from FLASH error SW RST RESET from SW RST WDT RST RESET from WDT LVR RST RESET from LVR PAD RST RESET from RESET PAD Table 5 43 RSTSTS register Generalplus Technology Inc Proprietary amp Confidential 39 AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 8 Ports 5 8 1 Introduction The GPM8F3232A 3216A 3208A has five ports including standard Port 0 Port 1 Port 2 Port 3 and additional Port 4 These port pins may be multiplexed with an alternate function for the 79 7 5 Driving Low peripheral features the device general when an initial Floating reset state occurs all ports are used as a general purpose input Driving Low Pull low port with open drain structure and Schmitt trigger function User can change IO initial state by CONFIG 1 through the SCK SDA interface The Schmitt trigger function can be controll
46. AUG 03 2012 Preliminary Version 0 1 Generalplus Technology Inc Proprietary amp Confidential G Generalplus Function Description Preliminary GPM8F3232A 3216A 3208A Condition Reserved INT6_WKUEN INT6 PAD wake up enable control active high 5 WKUEN INT5 PAD wake up enable control active high 4 WKUEN 4 PAD wake up enable control active high WKUEN INT3 PAD wake up enable control active high Reserved INT1_WKUEN INT1 PAD wake up enable control active high INTO_WKUEN 5 6 Interrupt System 5 6 1 Introduction The GPM8F3232A 3216A 3208A provides 14 14 12 types of interrupt sources including 11 interrupt sources of standard 8051 and additional 3 3 1 interrupt sources with two levels interrupt priority control which tabled in Table 5 22 For standard 8051 interrupt sources each interrupt can be in high or low level priority group by setting or clearing a bit in the 8 and EIP OxF8 registers INTO has the top priority in default state and user can choose the related interrupt source to be the top priority by IP register For additional interrupt sources high or low level priority group is set or cleared a bit in the BIP 0x96 Interrupt requests are sampled each system clock at the rising edge of clock control Each interrupt vector can be individually enabled or disabled by setting or clearing a correspondi
47. DC channel 7 input SPIO_RX Port 0 bit 6 AN6 ADC channel 6 input SPIO TX OP OUT Port 0 bit 5 AN5 ADC channel 5 input SPIO_CLK OP V N N N Port 0 bit 4 AN4 ADC channel 4 input SPIO_CSB OP V Port 0 bit 3 AN3 ADC channel 3 input gt Generalplus Technology Inc 12 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 20 Generalplus Preliminary GPM8F3232A 3216A 3208A 4 2 PIN Map Package Pin Sequence LQFP 44 Package Top View INT5 CAPTURE2 P14 6 P15 SCK RESET NC RXDO P30 TXDO P31 INTO P32 INT1 P33 TO P34 T1 P35 NC ZZ 22 pope mam gt amp lt lt lt 232 mmm 222 ON gt gt 2 lt Sevens 25 0989 98 0d A dO 8SO OldS PNV A dOM10 OldS SNV GPM8F3232A IL OL6 82 968 vc Sc 8c 06 LE P06 6 5 0 TX OP OUT P07 AN7 SPIO NC P40 P41 P42 SDA P43 P44 VREG P26 XTO P25 XTI A OFA gt gt 440 gt gt ce Z2 Generalplus Technology Inc 13 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary _ Gener
48. E8 TA FLASHCON FL_LEVEL KEYCODE OxEO OxD8 OxDO 0xC8 0xB8 0 0 AUDCON AUDBUF WKUEN CONFIG BYTE OxA8 OPCON SYSCONO SYSCON1 0 P3 PD P4 PU FLASHERRF SYSCON2 0x98 PD P1 PU P2 PU P2 PD 0x90 RSTSTS BIP BIF 0x88 TL1 THO CKCON RSTCON 0x80 DPHO DPS PCON 2 3 B 4 50 6 0 8 1 9 Table 5 6 SFR memory map 5 2 4 Memory Related SFR The following sub sections describe program external and internal memories related SFRs of 8051 core and their functionality For other information about standard SFRs please refer to appropriate peripheral section 5 2 4 1 Program Write Enable Bit The Program Write Enable PWE bit located in PCON register bit 4 is used during MOVX instructions When PWE bit is set to logic 1 the MOVX QDPTR An instruction writes data located in accumulator register into program memory addressed by DPTR register of PWE bit Program memory can be read by MOVC only regardless 5 2 4 2 Data Pointer Registers Dual data pointer registers are implemented to speed up data block copying DPTRO and DPTR1 are located in four SFR addresses Active DPTR register is selected by SEL bit DPS 0 If SEL 0 then DPTRO is selected otherwise DPTR1 5 2 4 3 Stack Pointer The 8051 has 8 bit stack pointer called SP 0x81 located in the internal RAM space t is incremented before data is stored during PUSH and CALL execution and decremented after data is popp
49. EM 10 Register 7 5 4 3 2 1 0 Function LVRENB AUDIO_N_DIS CLKOUT_EN CCOUTENB SCHMIT DIS P4 Default 0 0 0 0 0 0 0 Key Code FF 00 Function Description Condition LVRENB LVR enable control 0 enable LVR function 1 disable LVR function Reserved AUDIO_N_DIS AUDIO_N disable bit available only if audio function is enabled 0 P36 P37 are output simultaneously as AUDIO_N P 1 Only P37 is output as AUDIO P Reserved CLKOUT EN Clock output enable bit SYSCLK is output on P35 CCOUTENB Disable output function of compare mode in Timer2 0 P1 3 1 compare3 compare2 compare1 1 P1 3 1 is GPIO 5 DIS P4 P4 Schmitt trigger function disable control bit Table 5 16 SYSCONO register Generalplus Technology Inc Proprietary amp Confidential 26 AUG 03 2012 Preliminary Version 0 1 Preliminary GPM8F3232A 3216A 3208A G Generalplus Address 0xFA IOSC Timing 0 Register 5 4 3 2 1 TEMP TRIM 2 0 XFCN 2 0 Default 1 0 Function Function Description Condition Reserved TEMP_TRIM 2 0 Temperature coefficient trimming 011 default External XTAL Freq control bit XTAL PAD EN need to be1 XFCN XTAL HZ 000 F 32768Hz weak 001 F 32768Hz strong 010 1MHz lt F lt 4MHz 011 4MHz lt F lt 8MHz 100 8MHz l
50. ER The information appearing in this publication is believed to be accurate Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only GENERALPLUS makes no warranty express statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip s from patent infringement FURTHERMORE GENERALPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE GENERALPLUS reserves the right to halt production or alter the specifications and prices at any time without notice Accordingly the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders Products described herein are intended for use in normal commercial applications Applications involving unusual environmental or reliability requirements e g military equipment or medical life support equipment are specifically not recommended without additional processing by GENERALPLUS for such applications Please note that application circuits illustrated in this document are for reference purposes only Generalplus Technology Inc 89 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 9 REVISION HISTORY Date Revision Description Page AUG 03 2012 0 1 Original 90
51. GEMENT UNIT Port CONTROLLER Figure 3 2 Block diagram of GPM8F3216A Generalplus Technology Inc 8 Proprietary amp Confidential Preliminary GPM8F3232A 3216A 3208A 42 5 RESET SCK SPITXD SPIRXD PO 7 0 P1 5 2 P2 6 1 P3 3 0 P4 2 1 AUG 03 2012 Preliminary Version 0 1 G Generalplus 3 3 GPM8F3208A RESET SCK SYSCLK CAPTURE 3 CAPTURE 1 0 COMPARE 3 2 PO 5 4 PO 6 INT 6 INT 4 3 01 OPCODE DECODER IDM I F EXTERNAL DATA MEMORY VF FLASH CONTROLLER TIMERS 0 1 TIMER 2 INTERRUPT CONTROLLER ADC CONTROLLER N T z D e 2 m 2WIRE WRITER ICE VF SFR WATCHDOG TIMER POWER MANAGEMENT UNIT Port CONTROLLER Figure 3 3 Block diagram of GPM8F3208A Generalplus Technology Inc 9 Proprietary amp Confidential Preliminary GPM8F3232A 3216A 3208A 42 5 RESET SCK SPITXD SPIRXD PO 7 2 P1 5 P1 3 2 P2 6 1 P3 2 0 P4 2 1 AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 4 SIGNAL DESCRIPTIONS 4 1 Pin Descriptions 4 1 1 GPM8F3232A Type Input Output Supply Pin Name LQFP44 Description P14 P15 RESET NC Port 1 bit 4 INT5 CAPTURE2 Port 1 bit 5 INT6 RESET signal high active SCK 2 wire serial bus clock input line
52. GPIO change simultaneously SCHMIT DIS P3 P3 Schmitt trigger function disable control bit SCHMIT DIS P2 P2 Schmitt trigger function disable control bit SCHMIT DIS P1 P1 Schmitt trigger function disable control bit SCHMIT DIS PO Schmitt trigger function disable control bit Table 5 105 SYSCON2 register 5 13 Built in OP Circuits In GPM8F3232 3216 3208A there is one built in OP circuit The related control registers are OPCO Figure 5 34 shows the diagram of the built in OP circuit Generalplus Technology Inc 76 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A Address 0xAB OP Control Register 4 3 Function TRIM VOSP TRIM VOSN Function 0 0 Description Condition Reserved TRIM VOSP Trimming bit for OP offset TRIM VOSN Trimming bit for OP offset V Reserved Reserved 5 14 Audio Unit GPM8F3232A 3216A 3208A there is one audio control unit utilized for audio application AUDCON and AUDBUF When audio function is enabled P36 The related control registers are Enable OP function Table 5 106 OPCON register P04 OP_EN To ADC channel 6 Figure 5 34 Built in OP circuit by setting SYSCONO 4 and P37 are used as AUDIO N and AUDIO P in default setting Address 0xB3 Audio C
53. Generalplus Technology Inc 90 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1
54. H_LEVEL 5 0 7 address lt 0x1C00 is read only 8 address lt 0x2000 is read only 9 address 0x2400 is read only 10 address 0x2800 is read only 11 address lt 0 2 00 is read only 12 address 0x3000 is read only 13 address 0x3400 is read only 14 address 0x3800 is read only 15 address lt 0x3C00 is read only 16 address 0x4000 is read only 17 address 0x4400 is read only 18 address 0x4800 is read only 19 address lt 0 4 00 is read only 20 address 0x5000 is read only 21 address 0x5400 is read only 22 address 0x5800 is read only 23 address lt 0 5 00 is read only 24 address 0x6000 is read only 25 address 0x6400 is read only 26 address 0x6800 is read only 27 address lt 0 6 00 is read only 28 address 0x7000 is read only 29 address 0x7400 is read only 30 address 0x7800 is read only 31 address lt 0 7 00 is read only 232 address lt Ox7FFF is read only Only FLASH LEVEL 5 0 is useful in GPM8F3232A Only FLASH LEVEL 4 0 is useful in GPM8F3216A Only FLASH LEVEL 3 0 is useful in GPM8F3208A Table 5 5 The FL LEVEL register 5 2 3 Data Memory Allocation Data memory address allocations on the GPM8F3232A 3216A 3208A are divided into two parts first
55. If IO OE DATA PU amp PD ports are needed to change immediately without slew rate control the corresponding control bit of each port can be set to 0 The default state of SRCON register is OxFF with 30ns slew rate control Figure 5 9 and Figure 5 10 show the block diagrams of analog pad and digital pad respectively 79 79 5 Driving Low Floating Driving Low Pull low Illegal Pull high Figure 5 10 The block diagram of digital pad Driving Low 0 0 0 0 1 1 1 1 Driving High JO jo o Floating Table 5 44 The truth table of analog pad Generalplus Technology Inc 40 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary 240 Generalplus GPM8F3232A 321 6A 3208A CONFIG_BYTE Address 0xB7 CONFIG_BYTE Register Bit 5 0 Function LVRVSEL CODE Lock Default 1 1 Function Description Condition Reserved LVRVSEL LVR voltage level selection 0 3 9V 1 2 2V Reserved IO initial state selection bit IOSEL 0 Input pull high 1 floating CODE Lock 0 CODE is locked 1 CODE is unlocked Table 5 46 The CONFIG_BYTE register PO Address 0x80 0 Register Bit Function Default Function Description Condition PO 7 0 Porto
56. KHz Fosc 32 3 conversion clock 382 81KHz Fosc 64 Table 5 99 ADCFG register Generalplus Technology Inc 74 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A ADAEN Address 0xF3 ADC Analog PAD Enable Register Bit 7 6 5 4 3 2 1 0 Function P07 AEN P06 AEN P05 AEN 04 AEN P03 AEN 02 AEN P01 AEN Default 0 0 0 0 0 0 0 0 Function Description Condition P07 AEN P07 analog PAD enable control bit 0 7 can be 1 P07 can be analog PAD P06 AEN analog PAD enable control bit 0 be PAD 1 P06 can be analog PAD P05 AEN P05 analog PAD enable control bit 0 5 be PAD 1 P05 can be analog PAD P04 AEN P04 analog PAD enable control bit 0 04 can be PAD 1 P04 can be analog PAD P03 AEN P03 analog PAD enable control bit 0 can be PAD 1 P03 can be analog PAD P02 AEN P02 analog PAD enable control bit 0 2 can be I O PAD 1 P02 can be analog PAD P01 AEN P01 analog PAD enable control bit 0 1 can be PAD 1 P01 can be analog PAD 00 00 analog PAD enable control bit 0 POO be PAD 1 P00 can be analog PAD Table 5 100 ADAEN register Address 0xF4 ADC Output Low Data Register 2 Function ADO 3 0 Default
57. L 1 0 SPI Clock output selection 00 SYSCLK 2 01 SYSCLK 4 10 SYSCLK 8 11 SYSCLK 16 CSB KEEP SPI CSB keep low control high active Reserved SPI RD SPI read command SPI START SPI enable W SPI busy flag R Table 5 95 SPICON register Address OxFD SPI Output Buffer Register 5 3 2 Function SPITXD 7 0 Default Function 0 Description Condition SPITXD SPIRXD SPI output buffer Table 5 96 SPITXD register Address OxFE SPI Input Buffer Register Bit 5 3 2 Function SPIRXD 7 0 Default Function 0 Description Condition SPIRXD SPI input buffer Table 5 97 SPIRXD register Generalplus Technology Inc Proprietary amp Confidential 72 AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 12 ADC 5 12 1 ADC Control There is Analog to Digital Converter ADC Eight channels of 12 bit SAR built GPM8F3232A 3216A 3208A It provides general purpose GPM8F3232A 3216A 3208A They defined as usages such as voice record feature and any other analog general purpose line input POO PO1 07 These eight functions channels are very suitable for system voltage detection and other 8 Channels 12 bit resolution 11 bit no missing code ADC g
58. O CSB_ SPICON PHASE SPI_CLK_SEL 1 0 SPI RD LARITY KEEP SPITXD SPI TX Data 7 0 SPIRXD SPI RX Data 7 0 5 4 Clock Source GPM8F3232A 3216A 3208A has three clock sources including and can be controlled by CLKDIV 2 0 bits of IOSCCON register internal oscillator 24 5MHz external crystal and external clock User can monitor the frequency of SYSCLK on P35 by setting source These three clocks are chosen to be system clock SYSCONO 2 The block diagram of clock source and detailed Source by controlling 5 SEL 1 0 bits of IOSCCON register description of IOSCCON register are shown in Figure 5 5 and addition a clock divisor for the system clock source is contained to Table 5 15 respectively obtain different frequencies There are eight selections totally IOSCCON OXF9 N3V OLX N3V TO OAIQX TO 1 1 1138 250 0148 950 l 08 PERIPHERAL XTI CLK XOSC CLK CLKGATE SYSCLK DIV2 DIV64 STOP DIV1 5 Figure 5 5 The block diagram of clock sources If crystal mode is utilized different frequencies can be selected by tuning frequencies is possible through OSCT1 7 0 If IOSCTO 2 0 as shown in Table 5 17 and software should delay a IOSCT1 7 5 is used for trimming bit each step of frequency is period of time according to different crystals for clock stable time 10 I
59. OD0 0 Timer 1 overflow rate 1 16 SMODO 1 SYSCLK 64 SMODO 1 9 bit UART Variable Address 0x87 Power Configuration Register 5 3 Function CPU IDLE STOP RST EN Default 0 0 Bit Function Description Condition 7 SMODO R W UARTO double baud rate bit when clocked by Timer1 R W 5 CPU IDLE R W IDLE mode enable bit 0 IDLE mode disabled 1 IDLE mode entered Generalplus Technology Inc 68 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary A1 Generalplus GPM8F3232A 321 6A 3208A Function Description Condition PWE Program Write Enable PWE 0 Disable Flash write activity during MOVX instruction 1 Enable Flash write activity during MOVX instruction STOP RST EN Wakeup state selection bit 0 Next instruction state after wakeup 1 Reset state afer wakeup Reserved STOP mode enable bit 0 Disabled 1 Enabled Reserved Table 5 91 PCON register IE Address 0xA8 Interrupt Enable Register Bit 7 6 5 4 3 2 1 0 Function EA ET2 ESO ET1 EX1 ETO EXO Default 0 0 0 0 0 0 0 0 Function Description Condition EA Enable global interrupts Reserved Enable Timer 2 interrupt Enable UARTO interrupt Enable Timer 1 interrupt Enable INT1 interrupt Enable Timer 0 int
60. OxF1 please refer to related block For more detailed description Interrupt flag Function Active level edge Flag resets Vector Vector number Priority IEO Device pin INT 0 Low Falling Hardware 0x03 0 1 TFO Internal Timer 0 Hardware 0x0B 1 2 IE1 Device pin INT 1 Low Falling Hardware 0x13 2 3 TF1 Internal Timer 1 Hardware Ox1B 3 4 AUDIOF AUDIO interrupt Software cleared by 1 0x23 4 5 TIO amp RIO Internal UARTO Software cleared by 0 TF2 Internal Timer2 Software cleared by 0 0 2 5 6 EXF2 Timer2 external reload Software cleared by 0 ADCF ADC interrupt Software cleared by 1 0x33 Reserved 0 3 7 8 INT3F Device pin INT3 Low Hardware 0x43 Internal Compare 0 Software cleared by 1 Generalplus Technology Inc 29 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A Interrupt flag Function Active level edge Flag resets Vector Vector number Priority INT4F Device pin INT4 Low Hardware 0x4B 9 10 Internal Compare 1 Software cleared by 1 INT5F Device pin INT5 Falling Software cleared by 1 Internal Compare 2 Software cleared by 1 INT6F Device pin INT6 Falling Software cleared by 1 0x53 10 11 0x5B 11 12 Internal Compare 3 Software cleared by 1 WDIF Internal Watchdog Software cleared by 0 0x63 12 13 MERRF Memory access Error Software cleared by 1 0
61. SBUFO sets this data in UARTO PCON 0x87 IE OxA8 and IP 0xB8 The UARTO data buffer output register and starts a transmission data read from SBUFO consists of two separate registers transmit and receive SBUFO reads data from the UARTO receive register Generalplus Technology Inc 67 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A SBUFO Address 0x99 UARTO Buffer Register Bit 5 3 2 Function FO 7 0 Default 0 Function Description Condition SBUFOJ7 0 UARTO buffer Table 5 89 SBUFO register Address 0x98 UARTO Configuration Register 3 2 Function 08 08 0 0 Function Description Condition SMO 1 0 Mode and baud rate setting which described as below table SM02 Enables a multiprocessor communication feature RENO Enable serial reception 08 9th transmitted data bit in Modes 2 and Mode 3 08 In Mode 0 this bit is not used In Mode 1 if SMO2 is 0 08 is the stop bit In Mode 2 and Mode 3 it is the 9th data bit received UARTO transmitter interrupt flag UARTO receiver interrupt flag Table 5 90 SCONO register Function Baud Rate Variable in Mode1 and Mode 3 Shift register SYSCLK 12 Timer Baud Rate 8 bit UART Variable Timer 1 overflow rate T1 32 SMODO 0 9 bit UART SYSCLK 32 SM
62. SETB bit Set direct bit CPLC Complement carry flag CPL bit Complement direct bit ANL C bit AND direct bit to carry flag ANL C bit AND complement of direct bit to carry ORL C bit OR direct bit to carry flag ORL C bit OR complement of direct bit to carry MOV C bit Move direct bit to carry flag MOV bit C Move carry flag to direct bit 5 15 4 Data Transfers Mnemonic Description Code Bytes Cycles MOV A Rn Move register to accumulator 0 8 0 1 1 MOV Agirect Move direct byte to accumulator OxE5 2 2 MOV A QRi Move indirect RAM to accumulator OxE6 OxE7 1 2 MOV A data Move immediate data to accumulator 0 74 2 2 MOV Rn A Move accumulator to register OxF8 OxFF 1 1 MOV Rn direct Move direct byte to register 2 3 MOV Rn data Move immediate data to register 0x78 0x7F 2 2 MOV direct A Move accumulator to direct byte OxF5 2 2 MOV direct Rn Move register to direct byte 0x88 0x8F 2 2 MOV direct1 direct2 Move direct byte to direct byte 0x85 3 3 MOV direct Ri Move indirect RAM to direct byte 0x86 0x87 2 3 MOV direct data Move immediate data to direct byte 0x75 3 3 MOV Ri A Move accumulator to indirect RAM OxF6 0xF7 1 2 MOV Ri direct Move direct byte to indirect RAM OxA6 0xA7 2 3 MOV Ri data Move immediate data to indirect RAM 0 76 0 77 2 2 MOV DPTR Zdata16 Load 16 bi
63. SPI 1 1 1 12 bit ADC 8 channel 8 channel 6 channel Built in OP Yes Yes Yes IO 34 24 20 Package Type Generalplus Technology Inc Proprietary amp Confidential LQFP44 AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A 3 BLOCK DIAGRAM 3 1 GPM8F3232A RESET SCK SYSCLK 2 CAPTURE 3 0 1 PO 5 4 PO 6 INT 6 3 INT 1 0 P0 7 0 OPCODE DECODER IDM I F EXTERNAL DATA MEMORY FLASH CONTROLLER TIMERS 0 1 TIMER 2 INTERRUPT CONTROLLER ADC CONTROLLER 2WIRE WRITER ICE SFR WATCHDOG TIMER POWER MANAGEMENT UNIT Port CONTROLLER Figure 3 1 Block diagram of GPM8F3232A 42 5 gt RESET SCK SPITXD SPIRXD PO 7 0 P1 5 1 P2 7 0 P3 7 0 P4 4 0 P3 7 6 Generalplus Technology Inc 7 Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus 3 2 GPM8F3216A RESET SCK SYSCLK CAPTURE 3 0 COMPARE 3 2 5 4 PO 6 INT 6 3 INT 1 0 PO 7 0 OPCODE DECODER IDM I F EXTERNAL DATA MEMORY VF FLASH CONTROLLER TIMERS 0 1 TIMER 2 INTERRUPT CONTROLLER ADC CONTROLLER N T z e gt m 2WIRE WRITER ICE SFR WATCHDOG TIMER POWER MANA
64. STOP mode Reset STOP RST Flash Error Reset FLASH_ERR_RST and missing system clock Reset MISS CLK RST Reset is occurred when writing KEY code to KEYCODE register OxEF The key codes are and Oxc3 The timing Software does not matter but the key codes must be written in order before SW reset is take place STOP mode Reset is enabled by setting bit This is the reset when system is reset from STOP mode Flash Error Reset is the reset when five flash related errors are arisen The first error is to execute whole chip erase by software The second error is to access the wrong address The third error is when flash is programmed in a wrong way or to program READONLY PAGE The forth error is to erase LAST PAGE and the last error is to program CONFIG BYTE Each flash error related reset source can be enabled or disabled by clearing or setting a bit the RSTCON 0x94 as shown in Table 5 41 The corresponding flag when flash error reset occurs can be observed in FLASHERRF register which is shown in Table 5 42 Missing system clock Reset is the reset when system clock is missed over 4095 10 clocks if external crystal is utilized as clock source There are seven reset status flag can be monitored by RSTSTS register which is shown as Table 5 43 Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus CONFIG BYTE Preliminary GPM8F3232A 321
65. T4F INT3F MISS STOP FLASH 0x94 RSTSTS 0x00 S W RST WDT_RST LVR_RST RAD CLK RST RST ERR RST 0x96 BIP 0x00 PAUDIO PADC PMERR 0 97 0 00 AUDIOF ADCF MERRF 0x98 SCONO 0x00 5 00 5 01 SM02 RENO 08 RB08 TIO RIO 0x99 SBUFO 0x00 UART 0 buffer Ox9A PU OxFF P07 PU P06 PU 5 PU P04 PU PU 2 PU PO01 PU PU Ox9B PO PD 0x00 07 PD PD 5 PD P04 PD PD 2 PD PD PD 0x9C P1_PU OxFF P17 PU P16 PU P15 PU P14 PU P13 PU P12 PU PU P10 PU 0 90 P1 PD 0x00 P17 PD P16 PD P15 PD P14 PD P13 PD P12 PD P11 PD P10 PD Ox9E P2 PU OxFF P27 PU P26 PU P25 PU P24 PU P23 PU P22 PU P21 PU 20 PU Ox9F P2 PD 0x00 P27 PD P26 PD P25 PD P24 PD P23 PD P22 PD P21 PD P20 PD 0 0 2 OxFF Port 2 OxA1 P4 OxFF Port 4 OxA2 P3 PU OxFF P37 PU P36 PU P35 PU P34 PU P33 PU P32 PU P31 PU P30 PU OxA3 P3 PD 0x00 P37 PD P36 PD P35 PD P34 PD P33 PD P32 PD P31 PD P30 PD 0 4 P4 PU OxFF P46 PU P45 PU P44 PU P43 PU P42 PU P41 PU 0 5 P4 PD 0x00 46 PD P45 PD P44 PD PD P42 PD PD P40 PD FLASH _ FLASHERRF 0x00 CB PF CHIP E F FLOW F INT filler GPIO_ 5 SCHMIT SCHMIT SCHMIT_ 0 7 SYSCON2 00 0x00 ADCLKX2 550 DIS P3 DIS P2 DIS P1 DIS PO IE 0x00 EA
66. alplus GPM8F3232A 321 6A 3208A Package Pin Sequence SOP28 Package Top View POO ANO PO1 AN1 P02 AN2 P12 INT3 CAPTUREO COMPARE2 P13 INT4 CAPTURE1 COMPARE3 P04 ANA SPIO CSB OP V P14 INT5 P05 ANS5 SPIO CLK OP V P15 INT6 PO6 AN6 SPI0_TX OP_OUT RESET SCK PO7 AN7 SPIO_RX GPM8F3216A P30 RXD P41 P31 TXD P42 SDA P32 INTO VREG P33 INT1 P26 XTO VSS P25 XTI P21 P24 P22 P23 Package Pin Sequence SOP24 Package Top View P02 AN2 P03 AN2 4 4 5 0 CSB OP V P12 INT3 CAPTUREO COMPARE2 P05 ANS SPIO CLK OP V P13 INT4 CAPTURE1 COMPARE3 P06 ANG SPIO TX OP OUT P15 CAPTURE3 07 7 RESET SCK P41 P30 RXD GPMBF 3208A P42 SDA P31 TXD VREG P32 INTO P26 XTO vss P25 XTI P21 P24 P22 P23 Generalplus Technology Inc 14 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A 5 FUNCTIONAL DESCRIPTIONS 5 1 Central Processing Unit 5 1 1 CPU Introduction The CPU is an ultra high performance high speed embedded microcontroller Pipelined architecture enables the CPU 10 times faster than standard architecture This performance can also be exploited to great advantage in low power application where the core be clocked over ten times slower than original implementation for no performance penalty 5 1 2 CPU Features 100 software compat
67. atchdog circuitry makes the device entering reset state when MCU goes into unknown state and has no watchdog cleared information This function prevents the MCU to be stuck in an abnormal condition WDT be enabled or disabled through WDCON register bit 1 At any time prior to reaching its user selected terminal value software can set the Reset Watchdog Timer WDCON O0 bit RWT is set before the timeout is reached the timer will start over If timeout is reached without RWT being set the watchdog will reset the CPU Hardware will automatically clear RWT after software sets When the reset occurs the Watchdog Timer Reset WDCON 2 will automatically be set to indicate the cause of the reset however software must clear this bit manually WDCON register is a timed access register that prevent it from accidental writes TA is located at OxEB Correct sequence OxAA and 0x55 is required before write to WDCON register Reading from such register is not protected The Watchdog has four timeout selections based on the system clock frequency The selections are a pre selected number of clocks and can be set by CKCON 7 6 Therefore the actual timeout interval is dependent on the SYSCLK frequency Figure 5 8 shows the block diagram of Watchdog timer Watchdog interrupt RESET Figure 5 8 The block diagram of Watchdog timer 5 7 6 Other Reset Sources Other reset sources include Software Reset S W_RST
68. dential 65 AUG 03 2012 Preliminary Version 0 1 G Generalplus Address 0xCD Preliminary GPM8F3232A 3216A 3208A Timer 2 High Byte Register Bit 5 3 2 Function 2 7 0 Default Function Description Condition TH2 7 0 Timer 2 Load value high byte Table 5 87 TH2 register TL2 Address 0 Timer 2 Low Byte Register Bit 5 3 2 Function TL2 7 0 Function Description Condition TL2 7 0 5 10 UARTO UARTO has the same functionality as a standard 8051 UART The serial port is full duplex meaning it can transmit and receive concurrently It is receive double buffered meaning it commence reception of a second byte before a previously received byte has been read from the receive register Writing to SBUFO loads the transmit register and reading SBUFO reads a physically separate receive register The serial port can operate in 4 modes one synchronous and three asynchronous modes Mode 2 and Mode 3 have a special feature for multiprocessor communications This feature is enabled by setting 5 02 bit in SCONO register address byte which identifies the target slave An address byte The master processor first sends out an differs from a data byte in that the 9th bit is 1 in an address byte and 0 a data byte With SMO2 1 no slave will be interrupted by a data byt
69. e An address byte will interrupt all slaves The Timer 2 Load value low byte Table 5 88 TL2 register addressed slave will clear its SMO2 bit and prepare to receive the data bytes that will be coming The slaves that were not being addressed leave their 5 02 set and ignoring the incoming data 5 10 1 UARTO Mode 0 Synchronous Shift Register This mode is used as shift register IO control and not for real communication application baud rate is fixed at 1 12 of the system clock frequency and TXDO P31 output is a shift clock Eight bits are transmitted with LSB first Reception is initialized by setting the flags in SCONO as follows RIO 0 and RENO 1 Figure 5 24 shows the timing diagram of UARTO transmission mode 0 TXDO P31 i i Figure 5 24 The timing diagram of UARTO transmission mode 0 Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 Preliminary A1 Generalplus GPM8F3232A 321 6A 3208A 5 10 2 UARTO Mode 1 8 Bit UART Variable Baud Rate Timer1 Clock Source In mode 1 TXDO serves as serial output 10 bits are transmitted the SFR SCONO The baud rate is variable and depends from a start bit always 0 8 data bits LSB first and a stop bit always Timer 1 mode Figure 5 25 shows the timing diagram of UARTO 1 receive a start bit synchronizes the reception 8 data bits transmission mode 1 are available by readi
70. e 0x52 2 3 ANL direct data AND immediate data to direct byte 0x53 3 3 ORL A Rn OR register to accumulator 0 48 0 4 1 1 ORL OR direct byte to accumulator 0x45 2 2 ORLA QRi OR indirect RAM to accumulator 0 46 0 47 1 2 ORL A data OR immediate data to accumulator 0x44 2 2 ORL direct A OR accumulator to direct byte 0x42 2 3 ORL direct data OR immediate data to direct byte 0x43 3 3 XRL A Rn Exclusive OR register to accumulator 0x68 0x6F 1 1 XRL A direct Exclusive OR direct byte to accumulator 0x65 2 2 XRLA Ri Exclusive OR indirect RAM to accumulator 0x66 0x67 1 2 XRL A data Exclusive OR immediate data to accumulator 0x64 2 2 Generalplus Technology Inc 80 AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A Mnemonic Description Code Bytes Cycles XRL direct A Exclusive OR accumulator to direct byte 0x62 2 3 XRL direct data Exclusive OR immediate data to direct byte 0x63 3 3 CLRA Clear accumulator 0 4 1 1 CPLA Complement accumulator OxF4 1 1 RLA Rotate accumulator left 0x23 1 1 RLCA Rotate accumulator left through carry 0x33 1 1 RRA Rotate accumulator right 0x03 1 1 RRCA Rotate accumulator right through carry 0x13 1 1 SWAPA Swap nibbles within the accumulator 0 4 1 1 5 15 3 Boolean Operations Mnemonic Description CLRC Clear carry flag CLR bit Clear direct bit SETBC Set carry flag
71. e by 32 pre scaler served by lower 5 bit of TLO 1 16 bit timer counter THO 1 and are cascaded TLO 1 operates as 8 bit timer counter with 8 bit auto reload by 1 TLO is configured as 8 bit timer counter controlled by the standard Timer 0 bits THO is an 8 bit timer controlled by the Timer 1 controls bits Timer 1 holds its count Table 5 72 Four modes of Timer 0 and Timer 1 Address 0x88 Timer0 1 Configuration Register Function Default Function Description Condition TF1 Timer 1 interrupt overflow flag TR1 Timer 1 run control bit 0 disabled 1 enabled Timer 0 interrupt overflow flag Timer 0 run control bit 0 disabled 1 enabled INT1 interrupt flag INT1 level at 0 edge at 1 sensitivity INTO interrupt flag INTO level at 0 edge at 1 sensitivity Table 5 73 TCON register Generalplus Technology Inc 49 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus CKCON Address 0 8 Preliminary GPM8F3232A 3216A 3208A Clock Control Register Bit Function Default Function Description Condition WD 1 0 Watchd og timeout selection bits WD 1 0 Watchdog internal Number of clocks 00 217 131072 01 1048576 10 8388608 11 67108864
72. ea CONFIG_BYTE Ox3FFF 16KB LAST PAGE 0x3C00 15KB CONFIG_BYTE 0x1 FFF 8KB LAST_PAGE 0x1C00 7KB Code Area 0x0000 0KB 0x0000 0KB 0x0000 0KB GPM8F3232A GPM8F3216A Figure 5 1 Program memory organization GPM8F3208A CONFIG_BYTE Address 0xB7 CONFIG_BYTE Register Bit 5 0 LVRVSEL CODE Lock Default 1 1 Function Function Description Condition Reserved LVRVSEL LVR voltage level selection 0 3 9V 1 2 2V Reserved IO initial state selection bit IOSEL 0 Input pull high 1 floating 0 CODE islocked 1 CODE is unlocked Table 5 4 The CONFIG BYTE register CODE Lock FL LEVEL Address 0xED Flash Level Register Bit 5 3 2 FLASH LEVEL 5 0 Default 0 0 Function Function Description Condition Reserved FLASH LEVEL 5 0 FLASH LEVEL it determines how many 1K pages are read only FLASH LEVEL Note no page is read only address 0x400 is read only address 0x800 is read only address lt 0 0 is read only address 0x1000 is read only address 0x1400 is read only address 0x1800 is read only Generalplus Technology Inc 17 Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus Function Description Preliminary GPM8F3232A 3216A 3208A Condition FLAS
73. ed SYSCON2 3 0 and SYSCONO O All the input ports can be programmable pull high low by PU and PD registers The PU and PD registers of Port 0 are controlled by 0 9 and Ox9B the and PD registers of Port 1 are controlled by 0x9C and Ox9D the PU and PD registers of Port 2 are controlled by Illegal Pull high Driving Low 0 0 0 0 1 1 1 1 Driving High Table 5 45 The truth table of digital pad ANAEN ANAIP Ox9E and Ox9F the PU and PD registers of P3 are controlled by OE DATA PU amp PD 0 2 and and the PU and PD registers of P4 are controlled by 4 and OxA5 Read and write accesses to the I O port performed via their corresponding SFRs PO 0x80 P1 0x90 2 0 P3 0xBO and P4 0xA1 When PU and PD enabled at the same time the port can output high or low depending on the data Table 5 44 and Table 5 45 show the truth table of analog pad digital respectively In GPM8F3232A 3216A 3208A PO 7 0 and P2 6 5 be analog pad for special function PO 7 0 are used for ADC input P2 6 5 are used for external crystal input and output The detailed descriptions of analog function are in corresponding sections M Figure 5 9 The block diagram of analog pad The built in pull high low resister is addition there is register SRCON for slew rate control OXAD of PO P4
74. ed during POP RET and RETI execution it always points to the last valid stack byte The SP is accessed In the other words as any other SFRs Figure 5 3 shows an example when PUSH is executed and Figure 5 4 shows an example when POP PSW is executed Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 Preliminary GPM8F3232A 3216A 3208A 07H 08H 08H 23H 08H ACC 21H 07H ACC 21H 07H 23H 23H After execution G Generalplus Before execution Figure 5 3 Stack byte order for PUSH A instruction SP SP 65H 08H PSW 21H 07H PSW 23H 65H Before execution Figure 5 4 Stack byte order for POP PSW instruction 08H 07H After execution Address 0x87 Power Configuration Register 5 3 CPU IDLE STOP RST EN Default 0 0 Function Function Description Condition SMODO UARTO double baud rate bit when clocked by Timer1 Reserved CPU IDLE IDLE mode enable bit 0 IDLE mode disabled 1 IDLE mode entered Program Write Enable PWE 0 Disable Flash write activity during MOVX instruction 1 Enable Flash write activity during MOVX instruction STOP RST EN Wakeup state selection bit 0 Next instruction state after wakeup 1 Reset state afer wakeup Reserved STOP mode enable bit 0 Disabled 1 Enabled Reserved Table 5 7 The PCON register
75. electing a count rate of 1 12 1 1 or 1 24 1 2 of an oscillator frequency Thus the 16 bit timer register consisted of TH2 and TL2 is either Compare2 INT5 Compare3 INT6 033002 1ndino incremented in every 1 12 1 1 clock periods or in every 1 24 1 2 clock periods The pre scaler is selected by bit T2PS of T2CON and the clock switch is selected by bit T2CLK SW of SYSCON1 Generalplus Technology Inc Proprietary amp Confidential 57 AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A 5 9 3 2 Reload of Timer 2 The reload mode for Timer 2 is selected by T2RO and 2 1 bits of T2CON mode 0 when Timer2 rolls over from all 1 s to all 05 not only TF2 is set but also Timer 2 registers is loaded with the 16 bit value from CRC register Required CRC value can be preset by software The reload occurs in the same clock cycle in which TF2 is set thus overwriting the count value 0x0000 In mode 1 a 16 bit reload from the CRC register is caused by a negative transition at the corresponding T2EX input pin P11 addition this transition sets EXF2 flag if bit EXEN2 is set Setting EXF2 will generate an interrupt if Timer 2 interrupt is enabled T2IF 0xC9 2 1 E
76. enabled 0 P36 P37 are output simultaneously 1 Only P37 is output Reserved CLKOUT_EN Clock output enable bit SYSCLK is output on P35 CCOUTENB Disable output function of compare mode in Timer2 0 1 3 1 compare3 compare2 compare1 1 P1 3 1 is GPIO SCHMIT DIS P4 P4 Schmitt trigger function disable control bit Table 5 64 SYSCONO register Address 0 ADC analog PAD enable Register 7 6 5 4 3 2 1 0 Function P07 AEN P06 AEN 05 AEN 04 AEN P03 AEN P02 AEN 01 AEN AEN Default 0 Function 0 0 0 0 0 0 Description Condition 0 P07 AEN P07 analog PAD enable control bit 0 7 can be I O PAD 1 P07 can be analog PAD 06 AEN P06 analog PAD enable control bit 0 can be I O PAD 1 P06 can be analog PAD 05 AEN P05 analog PAD enable control bit 0 5 can be PAD 1 P05 can be analog PAD P04 AEN P04 analog PAD enable control bit 0 4 can be PAD 1 P04 can be analog PAD P03 AEN P03 analog PAD enable control bit 0 can be I O PAD 1 P03 can be analog PAD P02 AEN P02 analog PAD enable control bit 0 P02 can be PAD 1 P02 can be analog PAD P01 AEN P01 analog PAD enable control bit 0 P01 can be I O PAD 1 P01 can be analog PAD 00 AEN POO analog PAD enable control bit 0 can be PAD 1 can be analog PAD
77. eneral purpose usages In addition there is an AD_BITSEL Supports programming sample hold and ADC clock function control pin which can choose 8 bit ADC or 12 bit ADC to be used Figure 5 32 and Figure 5 33 show the related timing and block diagrams ADEN cb 5 2 Ulee e sr sp S LU U U U L L SHCLK 2 418 16 gt 10T 8 bit mode 14T 10 bit mode READY Figure 5 32 The timing diagram of ADC control ADAEN OxF3 eg g 5 5 81 8 81 8 p gt gt gt M pa p gt mimimimim m mi m al cea gt gt VCC VSS VREG UN VN eoo X ADCON OxF1 VW Po 2 8 sl gt 1 z i9 joj z 02 5 3 E a Lie KIA READY P05 PX Interrupt request P06 Interrupt request DK ADCFG 0xF2 2 gt gt aq ADLB 4 h0 lt ADO t 410 8 s 2 ADO lt ADLB 4 h0 2 _ auc nd ADO gt ADUB 4 h0 8 L ADC output data 11 0 12 bit mode SYSCON2 0xA7 gt la la 5 N Figure 5 33 The block diagram of ADC Generalplus Technology Inc 73 AUG 03 2012 Proprietary
78. ential Preliminary Version 0 1 G Generalplus Address 0 4 Preliminary GPM8F3232A 3216A 3208A Timer 2 CC2 Register low byte 5 3 2 Function 2 7 0 Default Function Description Condition CCH3 CC2 7 0 Timer2 compare capture 2 low byte Table 5 82 The CCL2 register Address 0xC7 Timer 2 CC3 Register high byte Bit 5 3 2 Function CC3 15 8 Default Function 0 Description Condition CC3 15 8 Timer2 compare capture 3 high byte Table 5 83 The CCH3 register Address 0xC6 Timer 2 CC3 Register low byte 5 3 2 Function 3 7 0 Default Function Description Condition CRCH CC3 7 0 Timer2 compare capture 3 low byte Table 5 84 The register Address OxCB CRC Register high byte Bit 5 3 2 Function CRC 15 8 Default Function 0 Description Condition CRC 15 8 CRC high byte Table 5 85 The CRCH register Address 0xCA CRC Register low byte 5 3 2 Function C 7 0 Default Function Description Condition CRC 7 0 CRC low byte Table 5 86 The CRCL register Generalplus Technology Inc Proprietary amp Confi
79. eralplus Technology Inc Proprietary amp Confidential 36 AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A Function Description Condition Reserved WDIF Watchdog interrupt flag WTRF Watchdog timer reset flag EWT Watchdog timer reset enable bit 0 Disable 1 Enable Reset watchdog timer 0 NA 1 Reset Table 5 36 WDCON register TA Address 0xEB Timed Access Protection Register Bit 5 4 3 2 Function Timed Access protection register 0xaa 3 0x55 Default 0 0 0 Function Description Condition TA 7 0 Timed Access protection register 0xaa 3 0x55 Table 5 37 TA register Address 0x8E Clock Control Register Function Default Function Description Condition WD 1 0 Watchdog timeout selection bits WD 1 0 Watchdog internal Number of clocks 00 2 131072 01 22 1048576 10 22 8388608 11 2 67108864 Reserved Division selection of the system clock that drives Timer 1 0 Timer 1 uses a divided by 12 of the system clock frequency 1 Timer 1 uses a divided by 4 of the system clock frequency Division selection of the system clock that drives Timer 0 0 Timer 0 uses a divided by 12 of the system clock frequency 1 Timer 0 uses a divided by 4 of the system clock frequency Reserved
80. errupt Enable INTO interrupt Table 5 92 IE register IP Address 0xB8 Interrupt Priority Register Bit Function Description Condition Reserved Timer 2 priority level control 1 high level UARTO priority level control 1 high level Timer 1 priority level control 1 high level INT1 priority level control 1 high level Timer 0 priority level control 1 high level INTO priority level control 1 high level Table 5 93 IP register Generalplus Technology Inc 69 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A 5 11 SPI Serial Peripheral Interface SPI controller is built in GPM8F3232A 3216A 3208A to facilitate communicating with other devices and components The SPI controller includes four master modes There are four control signals on SPI including SPI CSB SPI CLK SPI TX and SPI RX these four signals are shared with PO 7 4 or PXX P3 6 4 is used for SPICSN and can be a random pin as long as it is not utilized for any other function based on SPIO or SPI1 is chosen control share is set by SYSCON1 5 4 J While SPI module is enabled by corresponding control bit these four pins cannot be GPIOs other words any setting on corresponding GPIO control register will have no effect The SPI provides followin
81. f IOSCT1 4 0 is used for trimming bit each step of In order to enter stop mode XTAL PAD EN should be turned off frequency is 0 4 for fine tuning IOSCTI1 register is shown before PCON 1 is set to 1 If internal oscillator mode is utilized in Table 5 18 IOSCCON Address 0xF9 05 Control Register Bit 7 6 5 4 3 1 Function XTO AEN AEN XTAL PAD OSC SEL 1 0 CLKDIV 2 0 Default 0 0 0 0 1 0 Generalplus Technology Inc 25 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Function Preliminary GPM8F3232A 3216A 3208A Description XTO_AEN XTO analog PAD enable control bit 0 XTO can be I O PAD 1 XTO can be analog PAD AEN XTI analog PAD enable control bit 0 can be PAD 1 XTI can be analog PAD XTAL PAD EN If using XTAL XTAL PAD EN should be set first for SEL selection OSC SEL 1 0 00 Internal ROSC 01 Internal ROSC 10 XTAL 11 External CLK If using XTAL OSC_SEL 1 XTAL_EN should be set after 5 is stable CLK DIV System Clock source divider CLK DIV 000 SYSCLK SOURCE 001 SYSCLK SOURCE 2 010 SYSCLK SOURCE 4 011 SYSCLK SOURCE 8 100 SYSCLK SOURCE 16 101 SYSCLK SOURCE 32 110 SYSCLK SOURCE 64 111 SYSCLK SOURCE 1 5 Clock control Table 5 15 The IOSCCON register Address OxAE SYST
82. fidential Preliminary Version 0 1 Preliminary 240 Generalplus GPM8F3232A 321 6A 3208A Address 0x96 Additional Interrupt Priority Register Bit 4 3 Function PAUDIO PADC Default 0 0 Description Condition Reserved Reserved Reserved PAUDIO AUDIO priority level control 1 high level PADC ADC priority level control 1 high level Reserved Reserved MERR priority level control 1 high level Table 5 25 BIP register IE Address 0xA8 Interrupt Enable Register Bit Function Default Function Description Condition EA Enable global interrupts Reserved Enable Timer 2 interrupt Enable UARTO interrupt Enable Timer 1 interrupt Enable INT1 interrupt Enable Timer 0 interrupt Enable INTO interrupt Table 5 26 IE register EIE Address 0 8 Extended Interrupt Enable Register Bit 5 3 2 1 Function EWDI EINT5 EINT4 EINT3 Default 0 0 0 0 Bit Function Type Description Condition 7 R W___ Reserved 6 R W___ Reserved 5 EWDI watchdog interrupt 4 EINT6 Enable INT6 Compare3 interrupts 3 EINT5 R W _ Enable INT5 Compare2 interrupts 2 EINT4 Enable INT4 Compare1 interrupts 1 EINT3 Enable interrupts
83. function The Timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction this mode no interrupt request will be generated Figure 5 22 and Figure 5 23 show functional diagrams of the Timer 2 capture function Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 Preliminary Generalpius GPM8F3232A 3216A 3208A T2IF 0xC9 1 1 8 d S N Interrupt request gt 16 bit timer T2CON 0xC8 TH2 0xCD TL2 0xCC Input clock alalalalalalala 0 N om o a gt wo N o a gt wo N yY 7 y y Y E NN modeO CAPTUREO 12 Capture EG mode1 v v CRCH 0xCB CRCL 0xCA Write to CRCL E EE E N D a gt
84. g features Programmable phase and polarity of master clock Programmable master SPI CLK clock frequency SPI CSB In master mode the shifting clock SPI CLK is generated by SPI block There are two control bits to control the clock phase and polarity transmission starts immediately after SPI START is set SPICON 0 1 0xFC The SPI shifts the 8 bit data from MSB to LSB through the SPI TX pin during 8 SCK cycles Programmer can read SPI data from SPIRXD control register by setting SPI RD 71 The following four diagrams depict the timing scheme on SPI master mode for different operation types polarity control bit equals 1 or 0 phase control bit equals 1 or 0 The related registers are SYSCON1 register SPICON register SPITXD register and SPIRXD registers which are tabled as Table 5 94 to Table 5 97 SPI CLK LI L3 LI SR LAUS 8 bit Figure 5 28 Master Mode POLARITY 0 PHASE 0 SPI CSB SPI CLK LJ L LI Bn 8 bit Figure 5 29 Master Mode POLARITY 0 PHASE 1 Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A SPI_CSB SPI_CLK 1 i i i i i LAUS QPXIXIAIALALA
85. ible with industry 8051 24 times faster multiplication 12 times faster addition The CPU is fully compatible with industry standard 8051 microcontroller maintaining all instruction mnemonics and binary compatibility It incorporates some great architectural enhancements allowing the CPU instructions execution with high performance and high speed The arithmetic section of the processor performs extensive data manipulation and is comprised of an 8 bit arithmetic logic unit ALU an ACC OxEO register B OxFO register and PSW 0xDO register 5 1 3 Arithmetic Logic Unit ALU The ALU performs the arithmetic and logic operations during one Address OxEO instruction execution Typical arithmetic operations are addition subtraction multiplication and division Additional operations are such as increment decrement BCD decimal add adjust and compare Within logic unit operation such as AND OR Exclusive OR complement and rotation are performed The Boolean processor performs the bit operations as set clear complement jump if not set jump if set and clear and move to from carry 5 1 4 Accumulator A Register The accumulation is the 8 bit general purpose register which can be operated with data transfer temporary saving condition judgment etc 5 1 5 B Register The B register is used during multiply and divide operations other cases it may be used as normal SFR 5 1 6 Program Status Wo
86. ieved by cutting off frequency provided to SYSCLK resulting in a fully static condition processing is possible timers are stopped and no serial communication is executed Processor operation will be postponed on the instruction that sets the STOP bit STOP mode can be exited in the following ways i A non clocked interrupt such as the external interrupts INTO INT6 can be used Clocked watchdog timer internal timers and serial ports do not operate in STOP mode interrupts such as the Processor operation will resume with the fetching of Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A the interrupt vector associated with the interrupt that caused the exit from STOP mode RETI immediately following the one that invoked the STOP mode completed returns the program When the interrupt service routine is to the instruction When INTO INT6 are used for wakeup source WKUEN register must be set as shown in Table 5 21 the place of instruction execution System Clock There are two selections of after wakeup when entering Peripheral Clock Wakeup Source STOP mode and the control bit is in is set to 1 reset state will take place after wakeup otherwise next instruction will be executed modes in GPM8F3232A 3216A 3208A If STOP_RST_EN Table 5 19 show
87. ister Generalplus Technology Inc 63 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary Generalplus GPM8F3232A 321 6A 3208A T2IF Address 0xC9 Timer 2 Interrupt Flag Register Bit 2 Function EXEN2 Default 0 Description Condition Reserved Timer 2 external reload interrupt enable 0 external reload interrupt is disabled 1 external reload interrupt is enabled Timer 2 external reload flag Cleared by the software Timer 2 overflow flag Cleared by the software Table 5 78 T2IF register CCH1 Address 0xC3 Timer 2 CC1 Register high byte Bit 5 3 2 Function CC1 15 8 Default 0 Function Description Condition CC1 15 8 Timer2 compare capture 1 high byte Table 5 79 The CCH1 register Address 0xC2 Timer 2 CC1 Register low byte 5 3 2 Function 1 7 0 Default Function Description Condition CC41 7 0 Timer2 compare capture 1 low byte Table 5 80 The CCL1 register CCH2 Address 0xC5 Timer 2 CC2 Register high byte Bit 5 3 2 Function CC2 15 8 Default 0 Function Description Condition CC2 15 8 Timer2 compare capture 2 high byte Table 5 81 The CCH2 register Generalplus Technology Inc 64 AUG 03 2012 Proprietary amp Confid
88. ite to those bits don t have any Addr Function ped eee 7 6 5 4 3 2 1 0 Code Value 0x80 PO OxFF Port 0 0x81 SP 0x07 Stack Pointer 0x82 DPLO 0x00 Data pointer register DPTRO low byte 0x83 DPHO 0x00 Data pointer register DPTRO high byte 0x84 DPL1 0x00 Data pointer register DPTR1 low byte 0x85 DPH1 0x00 Data pointer register DPTR1 high byte 0x86 DPS 0x00 ID1 IDO TSL SEL Generalplus Technology Inc 22 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A Key Reset Addr Function 7 6 5 4 3 2 1 0 Code Value CPU STOP 0x87 PCON 0x00 SMODO PWE STOP IDLE RST EN 0x88 TCON 0x00 TF1 TR1 TFO TRO IE1 IT1 IEO ITO 0x89 TMOD 0x00 GATE1 1 M11 M10 GATEO CTO M01 Moo TLO 0x00 Timer 0 Load value low byte 0 8 TL1 0x00 Timer 1 Load value low byte 0 8 THO 0x00 Timer 0 Load value high byte 0x8D TH1 0x00 Timer 1 Load value high byte Ox8E CKCON 0x01 WD1 WDO 1 TOM 4F 72 CB_P_ LP_E_ FLASH XADDR_ MISS_CLK_ FLASH_ERR Ox8F RSTCON 0x10 T 7 07 FLOW ENB ENB 0x90 P1 Oxff Port 1 0x91 EIF 0x00 INT6F INT5F IN
89. l disable 1 slew rate control enable 30ns Table 5 62 SRCON register SYSCON2 Address 0xA7 SYSTEM control2 Register Bit 5 4 3 2 1 0 Function DIS SCHMIT DIS SCHMIT DIS SCHMIT DIS ADCLKX2 INT filter en GPIO SSO _P3 P2 P1 PO Default 0 0 0 0 0 0 Key Code Function Description Condition ADCLKX2 ADCLK double enable bit Reserved INT filter en INTO INT2 pad filter enable bit 0 no filter 1 2us GPIO SSO GPIO SSO function enable bit Avoid GPIO change simultaneously SCHMIT DIS P3 P3 Schmitt trigger function disable control bit SCHMIT DIS P2 P2 Schmitt trigger function disable control bit SCHMIT DIS P1 P1 Schmitt trigger function disable control bit SCHMIT DIS PO Schmitt trigger function disable control bit Table 5 63 SYSCON2 register SYSCONO Address 0xAE SYSTEM control0 Register Bit 7 5 4 3 2 1 0 Function LVRENB AUDIO DIS CLKOUT EN CCOUTENB DIS P4 Default 0 0 0 0 0 0 0 Key Code FF 00 Generalplus Technology Inc 45 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Function Preliminary GPM8F3232A 3216A 3208A Description Condition LVRENB LVR enable control 0 enable LVR function 1 disable LVR function Reserved AUDIO_N_DIS AUDIO_N disable bit available only if audio function is
90. n This may as a variation of the duty cycle of a periodic signal be used for pulse width modulation as well as for a continually controlled generation of any kind of square waveforms Two compare modes are The compare modes 0 and 1 are selected by bit T2CM in special implemented to cover a wide range of possible applications Compare Register CCx function register T2CON both compare modes the new value arrives at certain pin of P1 3 1 within the same clock cycle in which the internal compare signal is activated Compare mode 0 mode 0 upon matching the timer and compare register contents an output signal changes from low to high It goes back to a low level on timer overflow As long as compare mode 0 is enabled the appropriate output pin is controlled by the timer circuit exclusively It means that instructions writing to the P1 pin will have no effect Figure 5 20 shows a functional diagram of a port register in compare mode 0 The port register is directly controlled by the two signals timer overflow and compare Only for CRC o Interrupt EINTx 16 bit comparator Set Register Reset Register P13 P12 P11 16 bit timer2 TH2 0xCD TL2 0xCC T2IF 0xC9 T2CON 0xC8 alalajlaiaialatla la Ssss s s ms
91. ng SBUFO and stop bit sets the flag 08 in TX CLK ao de Figure 5 25 The timing diagram of UARTO transmission mode 1 5 10 3 UARTO Mode 2 9 Bit UART Fixed Baud Rate This mode is similar to Mode 1 with two differences The baud to control the parity of the UARTO interface at transmission bit rate is fixed at 1 32 or 1 64 of system clock frequency and 11 bits in SCONO is output as the 9th bit and at receive the 9 pit are transmitted or received a start bit 0 8 data bits LSB first a affects 08 in SCONO Figure 5 26 shows the timing diagram programmable 9 pit and a stop bit 1 The 9th bit can be used of UARTO transmission mode 2 ao XK or Ads X 56 X tee Figure 5 26 The timing diagram of UARTO transmission mode 2 5 10 4 UARTO Mode 3 9 Bit UART Variable Baud Rate Timer1 Clock Source The only difference between Mode 2 and Mode 3 is that the baud enabled The baud rate is variable and depends from Timer 1 rate is a variable in Mode 3 When RENO 1 data receiving is mode i i B B i B ee up da adr co Gr Figure 5 27 The timing diagram of UARTO transmission mode 3 5 10 5 UARTO Related Registers The UARTO related registers are SBUFO 0x99 SCONO 0x98 registers A data written into
92. ng bit in the IE 0xA8 EIE OxE8 The IE contains global interrupt system disable 0 enable 1 bit called EA event occurs the corresponding flag bit will be set In general once an interrupt The related registers of interrupt flag are described as below If the related interrupt control bit is set to enable interrupt an INTO PAD wake up enable control active high Table 5 21 The WKUEN register interrupt request signal will be generated and then CPU executes service routine If the related interrupt control bit is disabled programmer still can observe the corresponding flag bit but no interrupt request signal will be generated The interrupt flag bits must be cleared in the interrupt service routine to prevent program from deadlock in interrupt service routine With any instruction interrupts pending during the previous instruction is served Before entering interrupt service routine the system saves the current PC address into top of stack pointer and jumps to After finishing the interrupt service the system abstract the return PC corresponding vector to execute the interrupt service address from the top of the stack to execute the following instruction As to additional six interrupt sources each interrupt vector can be individually enabled or disabled by setting or clearing a corresponding bit the AUDCON 0xB3 ADCON OxF1 and RSTCON Ox8F corresponding flag can be found in BIF 0x97 and ADCON
93. ontrol Register user can disable the output of AUDIO N and leave P36 as GPIO Figure 5 35 shows the diagram of P36 and P37 output for different AUDCON settings Bit 3 2 1 0 Function AUDIO MODE AUDIOIE AUDIO FREQ SEL AUDIO EN Default Function 0 0 Description 0 0 Condition Reserved AUDIO MODE Audio mode selection 0 x 1 PWM mode AUDIOIE Enable audio interrupt AUDIO FREQ SEL Audio output frequency selection 0 AUDIO 24KHz output 1 AUDIO 32KHz output AUDIO EN Enable audio function Table 5 107 AUDCON register Generalplus Technology Inc Proprietary amp Confidential 77 AUG 03 2012 Preliminary Version 0 1 Preliminary GPM8F3232A 3216A 3208A G Generalplus Address 0xB4 Audio Buffer Register 5 3 2 Function BUF 7 0 Address 0xAE 0 Table 5 108 AUDBUF register SYSTEM control0 Register 7 5 4 3 2 1 0 Function LVRENB AUDIO DIS CLKOUT EN CCOUTENB SCHMIT DIS P4 Default 0 0 0 0 0 0 0 Key Code FF 00 Function Description Condition LVRENB LVR enable control 0 enable LVR function 1 disable LVR function Reserved AUDIO DIS AUDIO disable bit available only if audio function is enabled 0 P36 P37 are output simultaneously as AUDIO
94. ounter 13 bit upper counter switch TO P34 TMOD 0x89 TCON 0x88 o z z o z z 2 2 1414 2 4 8 GATEO P36 Figure 5 11 The block diagram of Timer 0 for Mode 0 Generalplus Technology Inc 50 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 9 2 2 Timer 0 Mode 1 16 Bit Timer Counter Mode 1 is the same as Mode 0 except that the timer register is Figure 5 12 running with all 16 bits block diagram of Mode 1 is shown in CKCON 0x8E THO 0x8C TLO 0x8A 99 3 division SYSCLK 4 selection Interrupt request 16 bit upper counter 34 TMOD 0x89 TCON 0x88 0 0 GATEO P36 Figure 5 12 The block diagram of Timer 0 for Mode 1 Generalplus Technology Inc 51 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 5 9 2 3 Timer 0 Mode 2 8 bit Timer Counter with Auto reloadable Function Mode 2 configures the timer register as an 8 bit counter TLO with not only sets TFO but also reloads TLO with the contents of THO automatic reloads as shown in Figure 5 13 Overflow from TLO which is loaded by software reload leaves THO unchanged CKCON 0x8E TLO 0x8A
95. part is 1K 512 256 bytes of external RAM and the second one is 256 byte IDM as shown in Figure 5 2 The lowest internal data memory IDM consists of four register banks with eight registers each A bit addressable segment with 128 bits 16 bytes begins at 0x20 The address from 0x30 to Ox7F is not defined and can be utilized freely by user The last 128 bytes of data memory can With the indirect addressing mode address from 0x80 to OxFF shared with stack be used by different addressing modes space is addressed With the direct addressing mode the SFR addressing from 0x80 to OxFF is accessed The SFR memory map is shown in Table 5 6 Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A XRAM Upper Internal RAM SFR OxFF shared with Stack Special Function space Registers indirect addressing direct addressing 0x80 Lower Internal RAM shared with Stack space direct amp indirect addressing 0x30 Bit addressable area 0x20 4 banks RO R7 each 0x00 XRAM 1KB GPM8F3232A 512B GPM8F3216A 256B GPM8F3208A IDM 256B and SFR 128B Figure 5 2 Data memory organization Note1 Black standard 8051 register gray additional register OxF8 IOSCCON IOSCT1 SPICON SPITXD SPIRXD OxFO ADCON ADCFG ADAEN ADOL ADOH ADLB ADUB Ox
96. plus GPM8F3232A 321 6A 3208A Function Description Condition Increment decrement function select See Table 5 13 ID 1 0 TSL Toggle select enable bit 0 DPTR related instructions do not affect state of SEL bit 1 DPTR related instructions to toggle the SEL bit Reserved Active data pointer select bit See Table 5 13 Table 5 12 The DPS register SEL 0 SEL 1 INC DPTRO INC DPTR1 DEC DPTRO INC DPTR1 INC DPTRO DEC DPTR1 DEC DPTRO DEC DPTR1 Table 5 13 DPTRO DPTR1 operations SP Address 0x81 Stack Pointer Register Bit 5 3 2 Function SP 7 0 Default Function Description Condition SP 7 0 Stack pointer Table 5 14 The SP register 5 3 Special Function Registers SFR GPM8F3232A 3216A 3208A has up to 84 control registers for effect on corresponding bits Some SFRs have key code design special function registers All of the SFRs are used by MCU and that KEYCODE register must be written with correct key codes in peripheral function block for controlling the desired operation sequence before writing a value to it for software security The Some of the SFRs contain control and status bits for peripheral following table shows the summary of the SFRs The detailed module such as Timer unit Interrupt control unit etc Some of information of each SFRs are explained in each peripheral section bits in SFRs are read only so wr
97. put Pull High Resistor 1 30 70 VDD 5 0V Low Voltage Reset 1 2 2 1 5 2 2 1 5 CONGIF_BYTE 5 1 Low Voltage Reset 2 6 4 ADC Characteristics Ta 25 C 6 4 1 12 bit Mode Characteristics Symbol 3 9 1 5 3 9 1 5 BYTE 5 0 Test Condition Operating Voltage VDD ADC Input Voltage Range VADCIN ADC Clock Period Tap us ADCLKmax 24 5MHz 8 Input Channel channel Resolution Bit No Missing Code bits ADC Conversion Time us ADCLK 16 ADCFG 1 0 2 b00 Integral Linearity Error Differential Linearity Error Generalplus Technology Inc Proprietary amp Confidential 84 AUG 03 2012 Preliminary Version 0 1 Preliminary nd Generalplus GPM8F3232A 321 6A 3208A 6 4 2 8 bit Mode Characteristics Test Condition Operating Voltage Input Voltage Range ADC Clock Period us ADCLKmax 24 5MHz 8 Input Channel channel Resolution Bit No Missing Code bits ADC Conversion Time us ADCLK 12 ADCFG 1 0 2 b00 Integral Linearity Error Differential Linearity Error E 6 5 OP Characteristics TA 25 C Characteristics Test Condition Operating Voltage OP Input Offset VDD 5 0V Generalplus Technology Inc
98. rd PSW The PSW contains several bits that reflect the current state of the CPU which is similar to the flag register of general CPU 5 1 7 Program Counter PC The program counter is 16 bit wide register It consists of two 8 bit registers which are PCH and PCL This register indicates the address of next instruction to be executed Reset state the content of 0x0000 is stored into program counter Accumulator A Register Bit 5 3 2 Function ACC 7 0 Default Function Description Condition Accumulator A ACC 7 0 Table 5 1 The ACC register B Address B Register Bit 5 3 Function 7 0 Default Function Description Condition B 7 0 B Table 5 2 The B register Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus Address 0xD0 Preliminary GPM8F3232A 3216A 3208A Program Status Word Register Bit 5 2 Function FO OV Default 0 Function Description 0 Condition Carry flag AC Auxiliary carry flag FO General purpose flag 0 RS 1 0 Register bank selection bits RS 1 0 Function Description 00 Bank 0 data address 0x00 0x07 01 Bank 1 data address 0x08 0xOF 10 Bank 2 data address 0
99. rts to activate and will operate in target speed The POR will reset whole chip and registers 5 7 3 Low Voltage Reset LVR The on chip Low Voltage Reset LVR circuitry forces the system entering reset state when power supplying voltage falls below the specific LVR trigger voltage This function prevents MCU from working at an invalid operating voltage range To enable or disable this function SYSCONO 7 can be set If this function is enabled the LVR circuit will monitor power level while Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A chip is operating And the LVR voltage level can be 2 2V or 3 9V by setting CONFIG_BYTE 5 through 2 wire interface If the power is lower than the specific level for a specific period the system reset will take place and go to initial state 5 7 4 Pad Reset PAD_RST The GPM8F3232A 3216A 3208A provides an external pin to force the system returning to its initial status The RESET pin is high active as shown in Figure 5 7 When the RESET pin equals to VDD system will be forced to enter reset state execute instruction from address 0x0000 and all registers go to default state VDD H External Internal lt gt 2 0 i RESET Figure 5 7 Pad reset circuit 5 7 5 Watchdog Timer Reset WDT RST On chip w
100. s SISISISISISINSIR gt gt e Interrupt Figure 5 20 The block diagram of compare mode 0 for Timer 2 Generalplus Technology Inc 59 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A Compare mode 1 compare mode 1 the software adaptively determines the transition of the output signal It is commonly used when output signals are not related to a constant signal period In compare mode 1 both transitions of a signal can be controlled If mode 1 is enabled and the software writes to an appropriate output register of P1 a new value will not appear at the output pin until Compare Register CCx 16 bit comparator Shadow Register the next compare match occurs User can select this way whether the output signal should make a new transition or should keep its old value until the Timer 2 counter matches the stored compare value Figure 5 21 shows a functional diagram of Timer 2 in compare mode 1 Only for CRC H EINTx Interrupt Bx Port Register Circuit Output Register o n o P13 P12 P11 16 bit timer2 TH2 0xCD TL2 0xCC T2IF 0xC9 T2CON 0xC8 ZEE SENSE za
101. s the three ii RESET pin cause exit from stop mode and the processor operation will resume execution at address 0x0000 After Wakeup RUN Mode Register setting Register setting IDLE Mode OFF ON 1 All wakeup sources 2 All interrupt so urces Next instruction state STOP Mode OFF 1 All wakeup sources Reset state or next instruction state base on PCON 3 Table 5 19 The three operation modes for GPM8F3232A 3216A 3208A Address 0x87 Power Configuration Register 5 3 Function CPU IDLE STOP RST EN Default Function 0 Description 0 Condition SMODO UARTO double baud rate bit when clocked by Timer1 Reserved IDLE mode enable bit 0 IDLE mode disabled 1 IDLE mode entered Program Write Enable PWE 0 Disable Flash write activity during MOVX instruction CPU IDLE 1 Enable Flash write activity during MOVX instruction STOP RST EN Wakeup state selection bit 0 Next instruction state after wakeup 1 Reset state afer wakeup Reserved STOP mode enable bit 0 Disabled 1 Enabled Reserved Table 5 20 The PCON register WKUEN Address 0xB6 Bit 6 5 4 3 2 1 0 6 WKUEN INT5 WKUEN 4 WKUEN INT3 WKUEN INT1 WKUEN WKUEN Default 0 0 0 0 1 1 1 Key Code Wake Up Enable Register Function 28
102. t 0 0 0 1 0 0 0 0 Key Code 4F 72 7A Bit Function Type Description Condition 7 CB_P_ENB BYTE program reset disable control bit 6 LP E ENB R W LAST PAGE erase reset disable control bit 5 FLASH FLOW ENB Error flash flowREADONLY PAGE program reset disable control bit 4 XADDR ENB R W Error flash address access reset disable control bit 3 RAV Generalplus Technology Inc 38 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 G Generalplus Preliminary GPM8F3232A 3216A 3208A Function Description Condition CHIP_E_ENB Whole chip erase reset disable control bit MISS_CLK_ ENB Miss clock reset disable control bit FLASH ENB FLASHERRF Global Flash related error reset disable control bit Table 5 41 RSTCON register Address 0xA6 Flash Error RESET Status Flag Register Bit 5 4 2 Function FLASH FLOW F XADDR F CHIP E F Default Function 0 0 0 Description Condition CB PF Error CONFIG BYTE program reset flag Error LAST PAGE erase reset flag FLASH FLOW F Error flash flow READONLY PAGE program reset flag XADDR F Error flash address access reset flag Reserved CHIP E F Error Macro erase reset flag Reserved RSTSTS Reserved Table 5 42 FL
103. t F lt 12MHz 101 12MHz lt F lt 16MHz 110 16MHz lt F lt 20MHz 111 25MHz gt F gt 20MHz XFCN 2 0 Table 5 17 The IOSCTO register Address 0xFB IOSC Control Timing 1 Register 6 2 OSC_TRIM 2 OSC_TUNE 4 0 Default Function Function Condition OSC TRIM 2 0 OSC_TUNE 4 0 Description Internal OSC frequency trimming bit 10 each step Internal OSC frequency trimming bit 0 4 each step Table 5 18 The IOSCT1 register 5 5 Power Saving Mode 5 5 1 Introduction to enter IDLE mode In this mode peripheral clock is not turned Although GPM8F3232A 3216A 3208A off so peripheral device can still work normally microcontrollers designed for maximum performance are high speed it also provides Power Management Unit PMU with two advanced 5 5 3 STOP Mode power conservation modes These modes are IDLE mode and STOP mode is the lowest power states that the microcontroller can STOP mode system does not need to be active STOP mode can be utilized In order to reduce the current consumption when For more information about these two modes please see the following two sections 5 5 2 IDLE Mode IDLE Mode reduces power consumption by turning off the clock provided to the microcontroller causing MCU to stop to execute following instruction By setting CPU IDLE bit PCON 5 is able enter It is ach
104. t constant into active and DPL in LARGE mode 0x90 3 3 MOVC A A DPTR Move code byte relative to DPTR to accumulator 0x93 1 5 MOVC A QA PC Move code byte relative to PC to accumulator 0x83 1 4 Generalplus Technology Inc 81 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary i Generalplus GPM8F3232A 321 6A 3208A Mnemonic Description Code Bytes Cycles MOVX A Ri Move external RAM 8 bit address to A XDM 0xE2 0xE3 1 SXDM 3 MOVX Move external 16 bit address to XDM OxEO 1 2 SXDM 2 Move A to external XDM 8 bit address ODE inside ROM RAM 4 MOVX QRi A Other cases 0 2 0 1 5 Move A to external SXDM 8 bit address All cases 3 Move A to external XDM 16 bit address CODE inside ROM RAM 3 MOVX DPTR A Other cases OxFO 1 4 Move A to external SXDM 16 bit address All cases 2 PUSH direct Push direct byte onto IDM stack 0 0 2 3 POP direct Pop direct byte from IDM stack OxDO 2 2 A Rn Exchange register with accumulator 0 8 1 2 AJirect Exchange direct byte with accumulator 0xC5 2 3 A Exchange indirect RAM with accumulator OxC6 0xC7 1 3 XCHD A Ri Exchange low order nibble indirect RAM with A OxD6 0xD7 1 3 Generalplus Technology Inc 82 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary Generalplus GPM
105. times faster than standard 8051 Up to 24 5MHz clock operation m Memories 1K 512 256 bytes XRAM 256 bytes internal Data Memory IDM SRAM 32 16 8K bytes Flash with high endurance Minimum 200 000 program erase cycles Minimum 20 years data retention Programming read only level for software security Clock Management Internal oscillator 24 5 2 2 2 4V 5 5V External clock input max 24 5MHz Crystal input with 32768Hz or 1MHz 25MHz W Power Management 1STOP mode for power saving 1IDLE mode for only peripheral operation W Interrupt Management 14 interrupt sources GPM8F3232A 3216A Up to 6 external interrupt sources GPM8F3232A 3216A 12 interrupt sources GPM8F3208A Up to 4 external interrupt sources GPM8F3208A Reset Management Power On Reset POR Low Voltage Reset LVR Reset PAD RST Watchdog Reset WDT Software Reset S W RST Stop mode Reset STOP RST Miss Clock Reset MISS CLK RST Flash Related Error Reset FLASH ERR RST Programmable Watchdog Timer time base generator An event timer System supervisor Ports 34 24 20 multifunction bi directional 1 Each incorporate with pull up resistor pull down resistor output high output low or floating input depending on programmer s settings on the corresponding registers ports with 20mA current sink ports with 8mA current drive Two 16 bit Timer Co
106. tion bit T2 120 Function 0 0 No input selected Timer 2 is stopped 0 1 Timer function input frequency SYSCLK 12 or SYSCLK 1 T2PS 0 SYSCLK 24 or SYSCLK 2 T2PS 1 No input selected Timer 2 is stopped No input selected Timer 2 is stopped Compare Capture Enable Register 3 2 1 CMH1 CML1 CMHO 0 0 0 Function Default Function Description Condition CM3 1 0 Compare capture mode for CC3 register CML3 Function 0 0 Compare capture disabled 0 1 Capture on rising edge of CAPTURE3 pin 1 0 Compare enabled 1 1 Capture on write operation into register CCL3 CM2 1 0 Compare capture mode for CC2 register CMH2 CML2 Function 0 0 Compare capture disabled 0 1 Capture on rising edge of CAPTURE2 pin 1 0 Compare enabled 1 1 Capture on write operation into register CCL2 CM1 1 0 Compare capture mode for CC1 register CMH1 CML1 Function 0 0 Compare capture disabled 0 1 Capture on rising edge of CAPTURE 1 pin 1 0 Compare enabled 1 1 Capture on write operation into register CCL1 CMO 1 0 Compare capture mode for CRC register CMH2 CML2 Function 0 0 Compare capture disabled Capture on falling rising edge of CAPTUREO pin Compare enabled Capture on write operation into register CRCL Table 5 77 CCEN reg
107. unter Timer 0 1 Timer mode with clock source selectable Auto reload 8 bit timers Externally gated event counters One Powerful Timer 2 with 16 bit Compare Capture Unit Timer mode with clock source selectable Auto reload 16 bit timers Externally gated event counters Event capturing Pulse width modulation and measurement UARTO One synchronous mode Three asynchronous modes SPI master mode Programmable phase and polarity of master clock Programmable master SPI CLK clock frequency Max SPI clock 6 125MHz Fosc 4 24 5MHz AID Converter One 8 channel 8 bit resolution mode GPM8F3232A 3216A One 8 channel 12 bit resolution mode GPM8F3232A 3216A One 6 channel 8 bit resolution mode GPM8F3208A One 6 channel 12 bit resolution mode GPM8F3208A Max conversion clock 6 125MHz Fosc 4 24 5MHz W Built in OP Circuit W Audio Module available only in GPM8F3232A 24KHz output or 32KHz output 24 5MHz Debug Unit Generalplus Technology Inc Proprietary amp Confidential AUG 03 2012 Preliminary Version 0 1 G Generalplus Product Number GPM8F3232A Preliminary GPM8F3232A 3216A 3208A GPM8F3216A GPM8F3208A Speed MHz 24 5 24 5 24 5 Operating Voltage V 2 4 5 5 2 4 5 5 2 4 5 5 Flash Kbytes 32 16 8 XRAM bytes 1K 512 256 IDM bytes 256 256 256 Timer 3 3 3 UART 1 1 1
108. ved 3 WDIF R W Watchdog interrupt flag Generalplus Technology Inc 32 AUG 03 2012 Proprietary amp Confidential Preliminary Version 0 1 Preliminary 1 Generalplus GPM8F3232A 321 6A 3208A Function Description Condition WTRF Watchdog timer reset flag EWT Watchdog timer reset enable bit 0 Disable 1 Enable RWT Reset watchdog timer 0 NA 1 Reset Table 5 30 WDCON register Address 0x98 UARTO configuration register 3 2 Function 08 08 0 0 Function Description Condition SMO 1 0 Mode and baud rate setting SM02 Enables a multiprocessor communication feature RENO Enable serial reception The 9th transmitted data bit in Modes 2 and Mode 3 RB08 In Mode 0 this bit is not used In Mode 1 if SMO2 is 0 RBO8 is the stop bit In Mode 2 and Mode 3 it is the 9 data bit received UARTO transmitter interrupt flag UARTO receiver interrupt flag Table 5 31 SCONO register EIF Address 0x91 Extended interrupt flag Bit 3 2 Function INT5F INT4F 0 0 Description Condition Reserved INT6 interrupt flag INT5 interrupt flag INT4 interrupt flag INT3 interrupt flag Reserved Table 5 32 EIF register Address 0x97 Additional interrupt flag Bit 4 3 Function AUDIOF ADCF Default 0 0

Preliminary GPM8F3232A/3216A/3208A

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