Sony PremierPro SDM-P82 18.1" LCD Monitor
Contents
1. s L 09 202 2 lt d T 55 3525 8 Doocooo J eed 1 1 Y 6814 s bd d Px 9 26 0501 28 x 10802 2 t 8 6803 0804 AS ET 3 R 2221 8 0225 off End Cl A excu a EL r na n E e 9 CNRO3 COMPONENT SIDE gt 7 98 se sse 6598 1094 lt CONDUCTOR SIDE gt SDM P82 E 3 12 2 Schematic Diagram of Board PWR ON OFF 1 4 2 5 7 3 NC 8982 1 1 1 2 1 GREEN LED 4 N C A 5 N C er 1 INPUTI 8 2 INPUTZ 7 AUTO 9 R910 8989 R912 R914 R913 WAN 2 2K 2 2 2K 2 2 EU e o e o SES 9 9 4 SIE 4 0917 5915 5909 5908 5911 5913 912 5914 8 8 6 4 3 4 3 49 08 4 53 42003 4823 4 3 296 4 8 Ka 8 vy 2 SS SS 56V Ne oe Ne zl C904 9052. rof v 22 TXI E 24 21 2 TX2 E 26 pna TXCK E 28 21 3 TX3 E 0 1 0 TX1 0 TX2 0 TX240 lt TXCK O TX3 0 12 120 100MHz BEAD 1206 X82 P82 X72 100U 16V A C257 L205 0 T 1U 0210 L204 0 5V_A SI4435DY R241 044 R246 dii Q215 Caf3 9216 WAN MMBT3904 Q216 gt 3 8 10K R242 MMBT39 4 ake afg2 orr 54 C263 D 33V_F IC501 THC63LVDM83A LVDS df80 DARED O 7 a pAREDO 231759 558 32 DARED 54 ad PDWN LVDS_EN DARED2 2512 DARED3 DAREDA 5518 58 DAREDS 58 Tat 46 DARED6 2 TD 45 DARED TD1 TB 4131 DAGRN 0 7 Tra DAGRNO Hras 145 DAGRNI 8 2 DAGRN2 171781 eg S EH DAGRNS 14 18 6 T 102 LVDSVCC FB501 DAGRN7 TD3 4132 DABLU 0 7 15 os 0565 120 100 DABLU1 281155 LVOSGND Ge BEAD 1206 DABLU2 29 11 6 LVDSGND DABLUS 22 LVDSGND pABLU4 TC2 ABLU5 26 TCS pABLU6 18 104 DABLU7 TD5 120 10
3. 4 3 2 4 White Balance Adjustment 2 3 2 5 Action after Replacing 5 ELECTRICAL PARTS LIST 5 1 the LCD Panel and Board 2 5 SDM P82 UC 5 SECTION 1 DISASSEMBLY 1 1 REAR COVER AND CABINET ASSY REMOVAL 9 Two screws PSW 4X8 9 Cabinet assy Protechtion sheet SDM P82 UC 1 1 1 2 BOARD REMOVAL 2 Invertor shield Screw 3 6 3 Connector 1 CNO4 3 Connector a 3 Connector 3 Connector CNO2 CNO6 1 Screw s ae RK 3X6 X 5 Board 3 SDM P82 UC 1 2 1 3 BOARD REMOVAL Two crews RK 3X6 V 2 Shield MA 4 Screw 3X6 Connector CN102 3 Connector CN101 SDM P82 UC 1 3 1 4 ABOARD REMOVAL 2 Three screws PWH 3 6 e 3X6 3 Interface shield 5 Connector CN304 5 Frexible cable 6 Four screws PWH 3X6 lt 5 Connector CN202 ie Connector PSS CN501 A board 4 Six connector screws SDM P82 UC 1 4 1 5 LCD UNIT REMOVAL 3 LCD unit D Flexible cable 2 Two screws 2X4 5 2 Two screws Beznet assy K 2X4 SDM P82 UC
4. 3 Adjust the SUB BRIGHTNESS R and Specifications are listed below Brightness cd m2 SUB BRIGHTNESS SUB CONTRAST 8 G B 30 30 30 141 141 141 0 283 0 003 0 298 0 003 1410 7 SDM P82 UC 4 Select COLOR TEMP 6500K in the service mode menu and set the data listed below as initial data for adjustment SUB BRIGHTNESS SUB CONTRAST R G B R G B 40 40 40 130 130 130 5 Adjust the SUB BRIGHTNESS R G and B Specifications are listed below x y 0 313 0 003 0 329 0 003 Brightness cd m2 14 0 7 Setting for shipping Turn off the power with the POWER button in the front panel Check that the red POWER LED lights on and then execute the all mode recall press the POWER button with pressing the OK button in the power off state Action after Replacing the LCD Panel and Board After replacing the LCD panel 1 White balance adjustment Refer to Section 2 4 2 CLEAR ETI TIME Refer to Section 2 3 step 3 3 Check of picture and sound After replacing the A board 1 White balance adjustment Refer to Section 2 4 2 EDID writing As the write protection is not applied in this unit it is possible to write data with an ordinary writing fixture It is required to be written for INPUT1 DVI D INPUT1 HD15 and INPUT2 HD15 respectively Take care that
5. DALC2 8SC6 8666 C638 GND OUTPUT B BLUE 1 rm 47 6 3 19 22 L e 1 Jk R637 11 INPUT2 R GND 26 R616 8 51 6917 82 NC R640 ROBOSW 199 8665 717 GND OUTPUT 25 m C639 o 47 6 3 13 INPUT2 G vcc R612 100 R636 R626 A ME 86865 VGA B ii T 715199 OUTPUT H HSYNC ZE BLUE 1 7 We NPUT B OUTPUTV VSYNC 0608 VGA_5V_2 5V_B NPUT2 H 56 St 100 R644 5VGA_2 INPUT2 V SWITCH 5 NAN A_A DSEL cg18 109 199 IC603 i 2 2 52758 ANALOG SW 1 8627 R628 IC607 yc 22K 22K Ji TC7W74FU 2 gt CK VCC 213 4 4 45 on 215 R C305 crab AT2XC02 10SC EEPROM 4 GND 5 VGA_HS_1 2 cg 1 5 1 1 Divided circuit diagram One sheet of A board are circuit diagram is divided into eight sheets each having the code A to A G For example the destination a b on the code A G sheet is connected to 1 U Ref No Circuit diagram division code on the A b sheet ANALOG NEN 553627 lt gt SDM P82 UC 3 6 AVDD_3 3_A C402 AVDD_3 3_A 3 5V Y C403 1 C404_L C405 1 C406 C407_L C408 1U AVDD_3 3_A 0 10 000101 1 0 10 1 AVDD_3 3_A 3 3V
6. SONY SAFETY CHECK OUT After correcting the original service problem perform the following safety checks before releasing the set to the customer 1 Check the area of your repair for unsoldered or poorly soldered connections Check the entire board surface for solder splashes and bridges Check the interboard wiring to ensure that no wires are pinched or contact high wattage resistors Check that all control knobs shields covers ground straps and mounting hardware have been replaced Be absolutely certain that you have replaced all the insulators Look for unauthorized replacement parts particularly transistors that were installed during a previous repair Point them out to the customer and recommend their replacement Look for parts which though functioning show obvious signs of deterioration Point them out to the customer and recommend their replacement Check the line cords for cracks and abrasion Recommend the replacement of any such line cord to the customer Check the connector shell metal trim metallized knobs screws and all other exposed metal parts for AC Leakage Check leakage as de scribed right LEAKAGE TEST The AC leakage from any exposed metal part to earth ground and from all exposed metal parts to any exposed metal part having a return to chassis must not exceed 0 5 mA 500 microamperes Leakage current can be measured by any one of three methods
7. Y C410 1 0411 1 412 1 C413 C414 L C415_L 416 1 C417_L C429 C422 100U 16V 0 1U 9010 0 10 0010 910 60 910 1U 8 81 9 811 D3 3V DVDD_3 3_1 3 3 Y 120 100MHz BEAD 1206 C419 C420 1 C423 1 424 425 1 426 4 427_1_ C42 47U 16V SM BT sell sep ec EU ew DVDD_3 3_1 DVDD_3 3_1 430 1 casi C432 C433 434 1 C435 1 c436 010 010 0 0010 010 9 1 9109 0 0010 out 4 4 4 4 4 4 425V DVDD 25 1 8465 257 120 100MHz BEAD 1206 0441 1 0442 1 C443 C444 1 C445 1 C446 c447_L C448 100U 16V 010 010 010 0 10 0 10 910 0 10 4 4 4 4 4 4 4 DVDD_2 5_1 DVDD_2 5_1 42 5V Y C450 1 C451 1 0452 1 C454 C455 C456 1 c457_L C458 0 10 0 10 0 10 0 10 0 10 0 10 1 4 4 4 4 4 AVDD_3 3_A FB410 1337 120 100MHZ BEAD 1206 C460 C461 C462 PVDD_3 3 C463_L C464_L C465 1 C466_L C467_L C468 1U 0 10 8 811 0 0010 1 1 1 1 0 0010 2 5V 1 PLLGND AVDD_2 5 FB411 12 54 Y 120 100MHZ BEAD 1206 C472 C4
8. HO mm o 0 3 D101 0183 zs R113 D108 8 NM 4 R119 103 0102 R126 Wwe t t EN 9 17 C113 i ae D 28 R118 5 m 259 6 S 4 0103 258 257 e n oo 18 e e E 5 1 1 1 8 9101 8 3 v la alo lo LO 10 o 1990 3 5 1 2 2 1 0104 101 e ES 25 19 25 9 19 17 4 v a E F x o 5 e 2 lo 8 4 t E T5 9 7 C261 59 e e e e NM 1 E R107 Ja AJ SS R256 a a 4 nd 2 49 T G pier 6182 25 M 4 4 1 o o 5 gt lt N x 81121 81122 81123 R1124 R1125 t 59 MA MA MA MA W 5 12 a a C131 l 4 4 454 d t H 4 B SS3633 lt UC gt G J SDM P82 UC 3 16 POWER SUPPLY G G BOARD GND 12 5 203 R265 vo XXXXXXXXXXXXX HS1 Dos C255 C254 ANO 3991 3403 WG 001 2 09 05 O 3 30 ASNIVOV NOILOJLOHJ 0202 6 2255 0201 113 6014 dl 93 NOILOVO FL101 F101 4 250 CN102 lt COMPONENT SIDE gt aan
9. R346 100 BKLEN 1 100 Q211 237 1 4 233 n 6 10 15 e Divided circuit diagram B SS3627 lt J gt A P7 One sheet of A board are circuit diagram is divided into eight sheets each having the code A to A For example the destination on the code A sheet is connected to the A sheet ab 1 Ref No SDM P82 UC 3 10 Circuit diagram division code ABOARD o 2 pa OB RP501 RP502 563 1111 am RP5 5 506 2 24 MAIN CPU SYSTEM IC COLOR DEC A D CONV 3D COMB FILTER k 5 38 268 0220 1505 5 f EE lt COMPONENT SIDE gt ELS jm 1 11111 S 1 Koch 0532 RP508 A 5 22 GH 1221 esl 8 S 5 S 505 540 E 16 8 E EJ 5 8 3 2953 68 LE 8 jm sj Lecu een 1029 eeu Ep 1189 21899185 5 et Coen argol 688 SCH cH 1 5951 zeen
10. 120 100MHz 1206 TX3 E LVDS_EN 0120 B SS3627 lt J gt A P6 14 15 SDM P82 UC 3 9 TO H BOARD CN901 15 5V_A 12V_1 12V_2 R236 3 3K 8 D RP301 RP304 5 8 UA 180 HDATAF 0 3 9924 T HDATAFO RP302 1 T HDATAF1 10K 716 Ors 2 x 5 15 HDATAF2 1 13 4 13 rer SI4435DY i 12 1 5 C248 242 R226 11 6 11 0025 1U 2 2K 1 7 ARQ 1900 158 ROBOSW E 5 RESET 45V A 10301 e 5 5V_A 0 34 17 R337 47 8362 126 0 24
11. 18512 ADI R338 47 FB303 YY 120 20 1 2 P6 2 AD2 NAN 47 4 Y 120 R301 3 s lt 2173 P6 3 AD3 10K Pm 54 23 P1 4 P6 4 DA10 R303 PIS P6 5 DA11 4 484 24 191 6 P6 6 DA12 R325 A A 470 HOT PLUG 564 NC RESET 0 lt 7 alg P6 7 DA13 H 10306 R323 XC61C 2 100 VBLANK P4 0 36 R326 A AA 20 DDC VGA 6910 14513504 DDC_SCL_1 HSCLI P3 0 Rxd HBLANK P4 1 7 PD 201 gt DDC_SDA_1 A V 6 HSDA1 P3 1 Txd g R324 luscL2 P7 0 323329 523 350 8 gt 100 HSDA2 P7 1 DAQ P5 0 VGA DETI 5 ES 15 P3 2 INTO DA1 PS 1 9 R330 A A A478 VGA_DET2 913 1938 BKLT_EN taga DA2 P5 2 7415 vGA Vs 21 C gia X301 1 98 13 ISCL P7 2 DA3 P5 3 41 4 R333 NS T 1 11 0592MHZ XTALI TAR 12 ap t VGA_HS_ 6915 2 14 ho 6 38 2 4 3 C 6918 lt 18 jvss 7 535 p 1 arse 518 BV DAB P7 4 A 0 1 0 9 7 3 55 0 R336 499 sP_MUTE C gh39 5V_A 8349 i VGA_HS_11 Ta 43 HSYNC P4 3 8 10M VGA_VS_it 5 4 4 vod 5V_A 2 S vob 281 910 0305 C310 sev BS l 10U 16V 2 1 6 1 rae SC GND SDA 4 9 1302 AT24C16 10sC 108 lt EEPROM Hn ANN jeh ANN 470 8308 5V 45 5 0306 0307 0308 0311 0312 0313 0514 sev 5 6v 5 6V NC NC NC NC 0301 0302 9
12. 34 34 FSDATA31 3 34 34 CKE 0915 37 37 18 NC RFU 18 NC RFU 18 NC RFU 3 17 33 3 38 17 JES 55 17 03 NC FSRAS RAS RAS RAS 3 16 gt gt 3 34 16 3 34 16 SaS FSCAS CAS CAS CAS FSWE 3 34 15 WE E 15 WE 3 34 15 WE 14 14 0414 FSDQMO LDQM EDL FSDQM2 100 LDQM 636 4 FSDOMI 94 36 Up u 8888 FSDQM3 36 9999 8888 gt S992 gs 995 22 Sess Raps es se adsl sls es ms 88 33 Sae 8 als 1 i i i i i 1 BB E ala lt lt lt lt lt lz E B S 5 Bu a D a 8 AJA lt a aja 1 al 3131313 RUM alalala R535 8526 edel RP5O8 RP507 10K 10K 2 aam 3 3V F 33V_F 444 FSDATA 0 47 SDRAM 553627 lt gt 5 14 15 SDM P82 UC 3 8 10 11 12 13 120 100MHz 120 100MHz BEAD 1206 VCC_PANEL TXI E 23 1 34 25 TX2 E TXCK E 1 27 BKLT TX1 0 TX2 0
13. 5 322 001 2 DQ2 9 2 2 FSDATA2 FSADDR2 2 42 2 FSDATAIB FSADDR2 2 A 23 A2 092 003 8 422 8 80 8 FSADDR3 424 A5 eg 8 20 6 FSDATA19 FSADDR3 2 4 24 JAZ 003 8 0 8 1 2427 8 0 8 1 2427 4 004 20 8 PSDATA4 3 FSADDR4 4 004 FSDATA20 FSADDR4 4 004 AS nas 9 41 90 FSDATAS 1 2 2 28 1 5 1151 0 FSPATAZI FSADDR5 amp 28 45 005 1503 DASH 41 0 1 4 23 36 0564 D06 13 4 L FSDATA22 FSADDR6 29 A6 Ces 096 45161622 007 SS 6 TSDATA 45161622 007 30 40 6 2 x FSADDR 1 7 4 31 K45161622 T 6 52 DQ8 22 1 0 FSDATAB FSADDR8 6 232 DaQ8s 48 510 FSDATA24 FSADDR8 6 a 32 008 FSADDR9 2019 SDRAM 009 0 21 0 FSDATAS FSADDR9 A9 SDRAM DQo 42 501 FSDATA25 FSADDRO A 32 lag SDRAM 009 B FSADDR10 19 16 45 0 FSDATAIO 77 FSADDRI0 pa 19 AP 0010 Hi ko FSDATA26 FSADDR10 0 19 0010 FSADDRI1I 419 0911 a5 50 3 FSDATA1I FSADDR11 BA 3 FSADDRi1 BA 0011 C539 0012 45 20 3 PSDATA12 3 J r1 0013 28 2 8 psbATAIS FSDATA29 FSCLK 243A 35 00141 25 1 0 14 1 3 25 FSDATA30 1 34 ox 0014 FSCKE 2 3 34 34 CK 0015 FSDATA15 3
14. 8 PE k 5 g 888 4 266 C220 6565 2060 84 0583 Lect 6584 zzex 1 Gen 156584 01284 6252 18 4 il 4 2922 L 9059 90284 EZY 8 21783 69284 SL 225311 922 resa 6152 9252 LEE 12830653 LOSY 0583 9162 siso isu 41899182 2154 ar 9 918 KI 8 8 50590754055 Ru 1152 a 2088 grey TEN 2284 6084 kl ES 8952 4962 295 dE 8 a 1192 298 Maii 622052 80531168
15. 9 Re 5 8 0524 90584 6253 2759 C531 u 9159 A trey LC 8g 8 6192 ezsa _ 222 83 1992 59 3 7975 1289059 eeso 59 2168 458 se Eye 0493 2293 198 2195 1155 Been 2 Ise 9282 lt CONDUCTOR SIDE gt SDM P82 UC 3 11 ABOARD MAIN CPU SYSTEM IC COLOR DEC A D CONV 3D COMB FILTER X82A BE 1 tans BA 71 CN202 18 R229 ER A d d C2 ye 20 end 210207 204 T 4 78203 CH
16. 906 967 05 992 1 2 91 2 9 1 2 91 2 91 291 291 291 Taa 28 2 29 ERE Rou Ro Rau laatu 0 010 8 91 8 81 DOWN UP 4 MENU ECO ON OFF INPUT SEL POWER_ON OFF 8o 1 1806 AUTO 4 4 4 4 4 0912 L ES M NC d B SS3633 lt UC gt H TO A BOARD CN303 SDM P82 UC 3 12 HBOARD KEY COMPONENT SIDE CONDUCTOR SIDE gt SDM P82 UC 3 13 3 Schematic Diagrams of Board 010 lt 220u 817 25 35 R41 2k rer ICT54 A BOARD 4 4 co CN202 CNO2 R42 ale 4 ICT T01 2PIN g YST A186490 s 1 A 8 B ni2 TO LCD BACK LIGHT 47k ICT23 ra Pu 14 20 817 155226 ICT53 2NTOORLTA 1 34 813 E NB 55 ROB 27k js nr 580 021 10k 100 ND ICT25 l
17. set these adjustments they are stored in memory as user modes and automatically recalled whenever the monitor receives the same input signals SDM P82 UC 4 TABLE OF CONTENTS Section Title Page Section Title Page 1 DISASSEMBLY 3 DIAGRAMS 1 1 Rear Cover and Cabinet Assy Removal 1 1 3 1 Block Diagrams 3 1 1 2 I Board Removal 1 2 3 2 Circuit Boards Location 3 2 1 3 G Board Removal 1 3 3 3 Schematic Diagrams and Printed Wiring Boards 3 2 1 4 A Board Removal 1 4 1 Schematic Diagram 1 5 LCD Removal ient EE 5 of A D 3 4 1 6 LCD Panel Removal 1 6 2 Schematic Diagram of H Board 3 12 1 7 H Board Removal 1 7 3 Schematic Diagram of I Board 3 14 4 Schematic Diagram of G Board 3 16 2 ADJUSTMENTS 2 Service Functions of Buttons in Front Panel 2 1 4 EXPLODED VIEWS 2 2 Usea of Service Mode 2 2 LM NE EE 4 2 2 3 Functions of Service Mode 2 3 4 2 Packing Materials
18. the data for DVI D and HD 15 terminals are different from each other 3 EDID copy to the EEPROM and ETI clear Refer to Section 2 1 step 6 Be sure to perform them after EDID writing After executing check that the correct model information is displayed Refer to Section 2 1 step 1 4 Operation check of buttons and LED s in the front panel and Check of picture and sound for respective inputs After replacing the board 1 White balance adjustment Refer to Section 2 4 2 Check of picture and sound After replacing the G board 1 Operation check of the MAIN POWER switch 2 Check of picture and sound After replacing the H board 1 Operation check of buttons and LED s in the front panel SDM P82 UC 2 5 SECTION 3 3 1 BLOCK DIAGRAMS om I BOARD INVERTER INTERFACE R CN602 G gt R INVERTER pn 8 gt G 4 BOARD INPUT2 Um H gt B Analog 0502 VGA_SDA 7 d 15 PINS VGA SCL IC603 LVDS Analog SW 1 401 CN501 R
19. they are seldom required for routine Ne les remplacer que par une pi ce portant service Some delay should be anticipated le num ro sp cifi when ordering these items When indicating parts by reference RESISTORS number please include the board name All resistors are in ohms F nonflammable SDM P82 UC 5 1 Board Ref No Part No Descrption Remarks 1 Remarks 2 Difference 1 G DIODE D130 8 719 510 51 DIODE SB60B SDM P82 UC 5 2 English Sony EMCS Corporation 200HL08 Data Ichinomiya TEC Made in Japan 2002 8 SDM P82 UC 41 9 978 738 01
20. to INPUT2 HD15 Signal timing Pattern Pattern VESA 1280 1024 60Hz All gray 30 IRE 0 21 Vp p 3 Select COLOR TEMP 9300K in the service mode menu and set the data listed below as initial data for adjustment SUB BRIGHTNESS SUB CONTRAST 6 Adjust the SUB BRIGHTNESS R G and B Specifications are listed below x y Brightness cd m2 R G B R G B 30 30 30 141 141 141 4 Adjust SUB BRIGHTNESS R G and B Specifications are listed below Brightness cd m2 0 283 0 003 0 298 0 003 14 2 0 7 5 Select COLOR TEMP 6500K in the service mode menu and set the data listed below as initial data for adjustment 0 313 0 003 0 329 0 003 1410 7 7 After adjusting 4 and 6 write down the value of SUB CONTRAST and SUB BRIGHTNESS 8 Feed the signal to INPUTI HD 15 and then select INPUT1 HD15 Select COLOR TEMP 9300K then 6500K in the service mode menu and enter the value written down in step 7 respectively Digital RGB white balance adjustment 1 Feed the signal listed below to INPUT1 DVI D Signal timing Pattern Input level VESA 1280 1024 60Hz All gray 30 IRE 2 Select COLOR TEMP 9300K in the service mode menu and set the data listed below as initial data for adjustment SUB BRIGHTNESS SUB CONTRAST R G B R G 40 40 40 130 130 130
21. 027 2PIN 2N7002LTA YST A186490 E IcT13 777 TT A A 1 m vum 2 1004 C40 1 ce 830 2 8958 104 4 i rai tf el gy ICTIO 4 NY ms re NE Nos 77 560 1 1 TO5 Cen 7 YST A186490 lt gt 1 ICT41 OE 7 TO LCD BACK LIGHT 390 2 i 188355 L cyos 2 4 gt 1005 x T 2 D12 8958 1 188355 1 M aD SI 77 ee N 155555 ES B SS3627 J SDM P82 UC 3 14 INVERTER I BOARD Hh 001 DAC 12B094 Y lt COMPONENT SIDE gt lt CONDUCTOR SIDE gt SDM P82 UC 3 15 4 Schematic Diagrams of Board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A 7 SS SS CN203 101 vo 181 FL101 FL102 me 0201 1281 5V 0 mE o o e o 7 A B ACIN al 9 zle 100V qo 25 5 ee o 1 SS Parse A BOARD 50 60Hz 5 OO d LG 5359 25 SS CN201 oT la la la 2 KE TH103 zs
22. 0MHz BEAD 1206 DHS 2814 DVS 5 PLLGND f26 4 DEN 30 res PLLGND DCLK CLKIN 53 25 SNOT 106 GND 21 17 60118 R F S GND Divided circuit diagram One sheet of A board are circuit diagram is divided into eight sheets TX3 0 2127 DBRED O 7 df28 DBGRN O 7 df29 DBBLU O 7 each having the code A to A For example the destination a b 1 U Ref No on the code sheet is connected to Circuit diagram division code TX3 0 1938 TXCK E 10 0 010 C515 1U 05164 0 811 16502 THC63LVDM83A LVDS DBREDO 51 DBREDI DBRED2 5512 DBRED3 55 DBRED4 6 TA4 DBRED5 zo 1755 DBREDG 2 1709 DBRED T01 DBGRNO 5176 DBGRN1 5 DBGRN2 1 DBGRN3 13 1182 DBGRN4 12 DBGRN5 5175 DBGRN6 101702 DBBLUO 15 5 48 DBBLU1 381186 LVDSGNO DBBLU2 20 LVDSGND DBBLU3 224161 LVDSGND DBBLU4 55 1 2 DBBLUS 24 DBBLUG 15 1 04 PLLVCC DBBLU T05 DHS 27 DVS 28 res PLLGND DEN 30 PLLGND DCLK CLKIN 53 25 GND 29 GND 29 17 R F GND R513 NC WN R512 9 4H 120 100MHz BEAD 1206
23. 1 2 commercial leakage tester such the Simpson 229 RCA WT 540A Follow the manufacturers instructions to use these instruments A battery operated AC milliammeter The Data Precision 245 digital multimeter is suitable for this job Measuring the voltage drop across a resistor by means of a VOM or battery operated AC voltmeter The limit indication is 0 75 V so analog meters must have an accurate low voltage scale The Simpson 250 and Sanwa SH 63Trd are examples of a passive VOMs that are suitable Nearly all battery operated digital multimeters that have a 2 AC range are suitable See Fig A Fig A Using an AC voltmeter to check AC leakage To Exposed Metal Parts on Set AC Voltmeter lesy 0 15 Earth Ground SDM P82 UC 2 WARNING SAFETY RELATED COMPONENT WARNING COMPONENTS IDENTIFIED BY SHADING AND MARK ON THE SCHEMATIC DIAGRAMS EXPLODED VIEWS AND IN THE PARTS LIST ARE CRITICAL FOR SAFE OPERATION REPLACE THESE COMPONENTS WITH SONY PARTS WHOSE PART NUMBERS APPEAR AS SHOWN IN THIS MANUAL OR IN SUPPLEMENTS PUBLISHED BY SONY CIRCUIT ADJUST MENTS THAT ARE CRITICAL FOR SAFE OPERATION ARE IDENTIFIED IN THIS MANUAL FOLLOW THESE PROCEDURES WHENEVER CRITICAL COMPONENTS ARE REPLACED OR PROPER OPERATION IS SUSPECTED AVERTISSEMENT ATTENTION AUX COMPOSANTS RELATIFS A LA SECURITE LES COMPOSANTS IDENTIFIES PAR UNE TRAME ET UNE MARQUE 4 SONT CRITIQUES
24. 1 5 1 6 LCD PANEL REMOVAL LCD panel SS Two screws PWH 3X6 CD Two screws Gf PWH 3X6 SDM P82 UC 1 6 1 7 H BOARD REMOVAL 3 Connector ER Switch cover 2 Flexible cable 3 H Board SDM P82 UC 1 7 SECTION 2 ADJUSTMENTS 2 1 Service Functions of Buttons in Front Panel The following functions are available for servicing the set 1 To display the model information Press the MENU button for five seconds or more in the ordinary power on state and the following information is displayed on the screen Model name Serial number Manufactured year and week This function is described in the instruction manual also To display ETI Elapsed Time Indicator Press the OK button for five seconds or more in the ordinary power on state and the cumulative power on time excluding the power off and power saving state is displayed on the screen All mode recall Press the POWER button with pressing the OK button in the power off state and the user memory is completely cleared and the system is reset to the factory setting This reset is similar to RESET in the OSD menu but differs from it in the following The NO SYNC AGING flag is cleared LANGUAGE is set to ENGLIDH INPUT is set to INPUT1 DVI D To set the NO SYNC AGING flag Press the POWER button with pressing the UP button in the power off state and the NO SYNC AGING f
25. 11 HD 15 INPUT 1 ANALOG RGB 6 5 R613 47 12 ANN VGA SDA Cbc8 14 15 1 VGA_SCL 568 R614 47 1204 35V 5V_B R609 410821 5VGA 5 10UH D604 2 2K Top C228 5V_C k 22U 16V E 5 Drs 1 5VGA 4 AAN VGA VS 11 8 R642 100 7 AZ 8 R641 199 244614 AS ANN VGA HS 11 4 44 RS SA 0218 R698 16629 IC304 DVI_PD SI4435DY C265 L 2 2K 5V SW 1 24 02 105 EEPROM MM x 5V_C FB6Q1 16538 cea Jl wem FB510 470U 16V FB513 47 6 3 BEAD L S 5V_C ROBOSW R620 0617 _ 22 606 FB603 4 VGA_R 9 01 i y 7076 3 JE RED o VCC R 2 8 R634 R619 C605 CN603 o INPUT R OUTPUT R 22 AAA RED 1 VGA_RED_2 8692 DS DALC2 8SC6 2 VGA_GRN_2 rm 3 GND R618 3 VGA_BLU_2 e 7 NC 8528 NC N INPUT 1 3 VGA DET2 13 82 HD 15 INPUT 7 sci sy a ROBOSW R622 C608 DN NG sn 0 910 ANALOG RGB 8 32 VGA G 2 1 AAN 4H GREEN 2 6 m 13 R629 47 1 2 0603 7 1 OUTPUT G 15 NANG 1 R635 47 6 3 DALC2 8SC6 8656 47 82 E R617 R659 86865 ANN NPUT1 H GND t 65 ve R652 AAA V INPUTI 2 C604 5 all 0610 IKS S
26. 1ev 919 8919 R244 E 7 7 159 R1206W Divided circuit diagram One sheet of A board are circuit diagram is divided into eight sheets each having the code A to A For example the destination on the code A G sheet is connected to a 1 Ll Ref No Circuit diagram division code n the A sheet D3 3V C261 C260 8 10 22U 16V A POWER B SS3627 lt J gt A P1 13 14 15 SDM P82 UC 3 4 CN601 5DVI 5DVI 11 12 13 1 R639 o 1 AAA 2 3 ARX2 8643 R604 o 39 ANN INPUT 1 Se Se DVI D INPUT 9 47 DIGITAL RGB E ARXTF M RXI 12 DVI_5V 1 12 R601 2 2 2647 o 17 19 1 ARXO R648 0 20 d 21 22 4 R655 0 23 ARXC 8656 RXC 5V_A 203 HOT_PLUG R649 10K App DL aw 5V_B 0607 0601 DNO04 GND VCC 3 1 01 1 02 44 44 5DVI 45VGA 388 8 0613 ST IC601 CD4052BC Sw R657 R6
27. 2 13 15 71 DBBLU 0 7 625 DBBLU0 DBBLU6 DBBLU7 DBBLU1 DBBLU2 DBBLU3 DBBLU5 DARED O 7 1 DABLU 0 7 12 9 8514 DCLK ees 120 100MHz 22 e 19 DBRED4 866 DBRED3 DBRED2 520 R502 100 z DBREDI NAN DHS DBREDO 19 R503 199 F18 R504 100 DVS DBRED6 ZE NWN 4 DEN DBRED DARO DBRED5 DARI 213 DAR2 DAR3 RP56 419 DARA 1e DBGRNO H18 DARS DBGRN1 17 DARE DBGRN2 DAR DBGRNG M19 DAGO M20 ACB DBGRN3 ts n m DAG4 E DAG5 19 DAGE RP503 DAG 10 819 DABO ae DABI 518 DAB2 n DAB3 DAB5 DAB6 DBBLU4 N20 DAB s DBRO DBR1 816 RP504 Bis DBR3 18 AS DBR4 DARED4 BE DBR5 DARED3 HE DBR6 DARED2 DBR DARED1 820 DBGO DAREDO 819 0
28. 20506 1203 nito MMBT3906 Herde 25 8315 5 6 8212 10UH 120 100MHZ 240 Jt casi 1 4 8 T 0 10 19 16 259 66 16 N 100U 16V F gt 0304 4 8 m 2 R312 MMBT3906 R315 3 1 Te 4 AMBER LED 5 6 5 R319 1 R318 GREEN LED 5V_B 6 1 1 PE ANN R317 A AA 4 7 4 7 1 4 INPUT2 AAA e ain LCD 12V c3 s_L C306 C307 C308 C309 1 C312 R321 367 NC T NC NC T NC TNC gt NC NC 5307 m raze vu Sor N E 0 5 2 2 Cdg22 4 N 4 4 CN202 5V_B R235 653 1C307 47K TO om R229 TO MAX2 2CSE NANG 681p 4423 4 FPN 10K H BOARD vec 10 524 6 CNO1 9 J AAA 5 m ro Cgh40 VOL_ADJ WW jaw CN301 i 316 WA ar e Aer Si 3 SS 23 1 2 KALIH 1y Fw vec 1 3 28 4 4 9 R347 100 BEAD 1206 3 C317 amp jez 2 RXD IC207 120 100MHz 5 0301 4 2 8 5 12 4 8 2244 358 80 236 235 8266 49 0 uma 81071 R245 R239 SI 7 R348 8 T20UT T2IN 0562 0304 W c3i5 L d 18 12 3T R2OUT R34 m BIEN 5 8 4 z 45V B 45V B 47K L R344 8252 SANAN 100 100 8222 523 R345 86
29. 36 1988 187 255 7 4 7 4 30K 1 1 1 201 4 5 6K 2M C204 2 4 0202 325 o 1 R202 T 3 9K 10 5 PP 41203 120 100MHz 1U R203 11 amp amp S S HON BEAD 1206 Sch 9 2 0 g gt ME BA9741F 41 208 me F 8269 4 7K e S SSES S l 120 100MHz R204 c212 209 8 0 1206 5 6 1 2 R215 7T 4000 16V 220U 16V 21 297 8810 S 0206 es 1 gx 944350 noo 10 8 5V REG 2224 MMBT3904 0 2 as s 82 0205 5 10K 0 4401 orr lt Ve 2 5 R225 Vs ars R216 10 6 10K s 4 G 45V_A 100 1 0204 202 t C214 ak MMBT4403 S 36 1000U 10V R219 8208 4 30K 4 7K Eis 1 14 4 R220 10K 1 5V_B IC204 33V_F 5V_B 25V 513033 5 T 10203 2 FB203 35V 3 3V REG Y iv 0265 10208 LD1085DT Y m Y XC6203E 6203 ny 3254 REG 120 166 FB204 3 3V REG 3 FB201 3 1327 Y Y BEAD 1206 Y Y Y IN OUT 1 Min Vin Vout af 3 9216 ANS M 29998 40 120 100MHz 120 100MHz ADJ 5555 1206 Vss BEAD 1206 C262 L C224 R243 C217 10K 220 18V 158 229 16 228 C221 C223 R1206W 010 S 218 C219 C266 6229 C227 0222 100U 16V i 22U 16V 0 10 1000 16V 22U
30. 58 22K 22K 11 gt 3x 49 VGA_SCL 107018 x oUT N 13 DDC_SCL_1 1 2 Ro 12 lox Kaes v our gt 4 DDC_SDA_1 1 24 02 105 1 8 Cbg EEPROM 1 1 10 TXD ai 4 4 Aa scl 5 vid VGA_SDA 424 4 B DDC_VGA 6g 10 4 4 6 8 inn 8 gt gt 1 B A Output DDC_VGA DDC_DVI Port Port active 1 0 0 0 Mini Din In A O 1 0 2 Input 2 DH 15 e Divided circuit diagram One sheet of A board are circuit diagram is divided into eight sheets each having the code A to A For example the destination ab1 on the code A sheet is connected to ab1 on the A sheet ab 1 Ref No Circuit diagram division code DVI AND DDC SWITCH IC B SS3627 lt J gt A P2 14 SDM P82 UC 3 5 CN602 1 2 3 4 INPUT 2 1 VGA_DET1 C9
31. 73 C474 C475 476 C477 C478 10 9 10 10 10 1 01U 0 0010 Divided circuit diagram One sheet of A board are circuit diagram is divided into eight sheets each having the code A to A For example the destination Ref No on the code A G sheet is connected to Circuit diagram division code 469 R401 DVDD_2 5_1 AVDD_2 5 AVDD 33 A PVDD_3 3 IPLLVDD_ 3 3 IPLLVDD_ 3 3 IPLLVDD_ 3 3 RED RED GREEN GREEN BLUE BLUE RXC RXC 565 RX1 RXi RX2 RX2 AVDD_3 3_A 5P AA X401 24MHZ VSYNC 5P HSYNC GPIO7 DOVL IGPIO6 DFSYNCn LVDS_EN AL A2SEL 4022 023 PWMo 0 31 32 HDATAFS HDATAF2 HDATAF1 HDATAFO HFS IHFSn SDA HCLK IHCLK SCL 4025 ARQ RESET c FB412 120 100MHz GND BEAD 1206 PLLGND DVDD_3 3_1 10401 GM5020 SCALER FSDATA1 1 FSDATA1 2 FSDATA1 3 FSDATA1 4 FSDATA20 FSDATA21 FSDATA27 FSDATA2B FSDATA29 FSDATA3Q FSDATA36 FSDATA37 FSDATA38 FSDATA39 FSDATA49 FSDATA41 FSDATA42 FSDATA43 FSDATA44 FSDATA45 FSDATA46 FSDATA47 FSADDR1 oi FSADDR1 1 FSADDR12 11 1
32. 861 DAREDG 820 DBG2 DARED En DBG3 DAREDS BE DBG4 HE DBG5 C17 DBG6 RP505 E28 19 DAGRNO E19 DEED E18 PETS DAGRN2 n shen 018 DBB4 DAGRN3 C20 HRA DAGRN4 19 9856 DAGRN5 DBB7 ve FSDATAO ws FSDATAI RP506 16 FSDATA2 10 DABU Q FSDATA3 FSDATA4 DABS Y7 DABLUT FSDATAS DABLUI FSDATAG DABLU2 FSDATA wg DABLU3 FSDATA8 Y9 FSDATA9 DABLUS ve FSDATA10 FSDATAI Hr FSDATAI2 FSDATA13 E FSDATA14 un FSDATA15 FSDATA16 Ae FSDATAI7 E FSDATAI8 EH FSDATAI9 M FSDATA20 zi FSDATA21 FSDATA22 aE FSDATA23 we FSDATA24 FSDATA25 FSDATA26 FSDATA O 47 e33 mE FSDATA27 HE FSDATA28 m FSDATA29 A FSDATA30 uH FSDATA31 FSDATA32 wie FSDATA33 FSDATA34 119 FSDATA35 EE FSDATA36 720 FSDATA37 vie FSDATA38 JH FSDATA39 FSDATA40 818 FSDATA41 119 FSDATA42 D FSDATA43 FSDATA44 He FSDATA45 720 FSDATA46 FSDATA47 15 FSADDRO FSADDR O 13 we FSADDR1 FSADDR2 FSADDR3 5 FSADDR4 FSADDRS Y FSADDR6 Vs FSADDR7 E FSADDRB A FSADDR9 w FSADDR10 A FSADDR11 FSADDR12 x FSADDRI3 FSCLK FSCKE A FSRAS geng 2 FSCAS FSWE FSDQMO 18 FSDOMI 9636 e FSDQM2 FSDQM3 S DAGRN O 7 CALER 553627 lt gt 4 SDM P82 UC 3 7 10 11 13 3 3V_F 3 3V_F1 C540 0 117 120 100MHz BEAD 1206 0518 519 C520 0521 6522 6523 C524 22U 16
33. DISPLAY ENGINE LVDS d HD 15 gt V gt GM5020 PANEL 4 IC503 509 CON V 4 ADC DVI SCALER VGA_ SDA_2 LVDS 15 PINS 80 2 INPUT1 IC503 CN601 RXO RX1 RX2 RXC gt Digital IC504 DVI D I P x 8Pins lt gt IC505 CON DVI D SDA SDRAM 24 PINS pvI D SCL ont INPUT SEL CN301 SDA IC302 ECS Port UF SCL DATA 8 PIN EEPROM 10301 MCU 303 L DDC SDA_1 DVI D DVI D SDA DDC SCL 1 DDC DVI D SCL H BOARD EEPROM DDC_VGA lt IKEY BOARD 1 305 15 VGA_ SDA_2 IC601 KEY DDC VGA_ SCL_2 DDC y BOARD EEPROM SW IC IC304 DH 15 VGA_SDA DDC VGA_SCL CN802 em EEPROM AUDIO IC801 CN801 Audio Audio gt 2 CON SPK SW IC AMP ON OFF CN803 22 Control AUDIO 2 d 0201 12V Adapter 12V POWER 5V Ear Phone PWR LF 3 3V Jack In 2 5V U BOARD G BOARD EARPHONE POWER SDM P82 E 3 1 3 2 CIRCUIT BOARDS LOCATION Board Board G Board SDM P82 UC 3 2 3 3 SCHEMATIC DIAGRAMS AND PRINTED WIRING BOARDS Note All capacitors are in uF unless otherwise noted pF Capacitors without voltage indication are all 50 V Indication of resistance which does not have one for rating electrical power is as follows Pitch 5 mm Rating electrical power 1 4 W CHIP 1 10 W All resistors are i
34. L9zy LLSZY 652 16222522 2 cone 9929 2588 2929 8 3 2 Sg gt 1 9 22 X 8 5 5 m 5 1960 D 6620 2922 2820 8825 9 952 4522 9924 9114 gt 2504 aiza 9510 1 vola 51 e 9013 Qi oc 2112 6103 r 77613 waal 6114 1T 78019 velo coin SLIM RN 1510 19 1 19013 010 a4 iol z soro am 10121 6112 8019 1 21014 11013 2 01MITOLM 90v1900v6c CONDUCTOR SIDE gt 3 17 SDM P82 UC 4 EXPLODED VIEWS Items with no part number and no description are not stocked because they are seldom required for routine service The construction parts of an assembled part are indicated with a collation number in the remark column Items marked are not stocked since they are seldom required for routine service Some delay should be anticipated when ordering these items The components identified marked are critical for safety Replace only with the part number specified Les composants identifi s par la marque A sont critiques pour la s curit Ne les remplacer que par une pi ce portant le num ro sp cifi SDM P82 UC 4 1 4 1 CHASSIS REF NO PART DESCRIPTION REMARK X 4040 765 1 BEZEL A
35. Mode Turn off the power with the POWER button in the front panel The red POWER LED lights on Press the POWER button in the front panel with pressing the UP and DOWN 4 buttons and the system enters the service mode When no signal is input to the selected input terminal the following functions are disabled Press the MENU button and the main menu is displayed Then go to page 2 of the main menu with the UP D or DOWN 4 button then select the MAINTAIN icon on the bottom line and then press the OK button In this menu screen the version number and released date of the internal software can be checked The structure of the MAINTAIN menu is shown below MAINTAIN CONFIGURATION COLOR TEMP 9300K SUB BRIGHTNESS R 6500K G B EXIT SUB CONTRAST R G B INITIAL EEPROM CLEAR ETI TIME EEPROM TEST RGB RESET EXIT CHIPS AGING MODE ON OFF REGISTERS VALUE CONTROL REG 000 1FF EXIT EXIT The operation procedure is basically same as that of the ordinary user controls The function of each menu is explained in next section SDM P82 UC 2 2 2 3 Functions of Service Mode COLOR TEMP This is used for the white balance adjustment at color tem
36. POUR LA SECURITE NE LES REMPLACER QUE PAR UNE PIECE PORTANT LE NUMERO SPECIFIE LES REGLAGES DE CIRCUIT DONT L IMPORTANCE EST CRITIQUE POUR LA SECURITE DU FONCTIONNEMENT SONT IDENTIFIES DANS LE PRESENT MANUEL SUIVRE CES PROCEDURES LORS DE CHAQUE REMPLACEMENT DE COMPOSANTS CRITIQUES OU LORSQU UN MAUVAIS FONCTIONNEMENT EST SUSPECTE SDM P82 UC 3 POWER SAVING FUNCTION This monitor meets the power saving guidelines set by VESA ENERGY STAR and NUTEK If the monitor is connected to a computer or video graphics board that is DPMS Display Power Management Signaling compliant the monitor will automatically reduce power consumption as shown below Power mode Power consumption power indicator normal 58 W max green operation active off 3 W max orange deep sleep power off 1W red main power off 0 W off When your computer enters the active off mode the input signal is cut and NO INPUT SIGNAL appears on the screen After 10 seconds the monitor enters the power saving mode sleep is a power saving mode defined by the Environmental Protection Agency Note If the POWER SAVE is set to OFF page 16 the monitor does not enter the power saving mode AUTOMATIC PICTURE QUALITY ADJUSTMENT FUNCTION ANALOG RGB When the monitor receives an input signal it automatically adjusts the picture s position and sharpness phase pitch and ensures that a clear picture appears
37. SERVICE MANUAL LCD panel Input signal format Resolution Input signal levels Power requirements Power consumption Operating temperature 6 SPECIFICATIONS Panel type a Si TFT Active Matrix Picture size 18 1 inch RGB operating frequency Horizontal 28 92 kHz Vertical 56 85 Hz Horizontal Max 1280 dots Vertical Max 1024 lines Analog RGB video signal 0 7 Vp p 75 positive SYNC signal TTL level 2 2 positive or negative Separate horizontal and vertical or composite sync 0 3 Vp p 750 negative Sync on green Digital RGB DVI signal TMDS Single link 100 240 V 50 60 Hz Max 1 2 A Max 58 W 5 35 SDM P82 US Model Canadian Model Dimensions width height depth Mass Plug amp Play Display upright Approx 404 x 406 x 201 mm 16 x 16 8 inches with stand Approx 404 x 332 6 x 86 2 mm 16 x 13 x 3 1 2 inches without stand Approx 7 6 kg 16 lb 12 oz with stand Approx 6 3 kg 13 Ib 14 oz without stand DDC2B Recommended horizontal and vertical timing condition Horizontal sync width duty should be more than 4 8 of total horizontal time or 0 8 us whichever is larger e Horizontal blanking width should be more than 2 5 usec Vertical blanking width should be more than 450 Design and specifications are subject to change without notice TFT LCD Color Computer Display
38. SSY 3 704 176 51 EMBLEM NO 6 SONY 1 761 645 11 H BOARD MOUNT 1 804 967 11 PANEL LCD LM181E05 1 761 646 11 BOARD MOUNT 1 761 615 11 G BOARD MOUNT 1 761 644 11 A BOARD MOUNT X 4040 766 1 STAND ASSY 9 4 090 701 01 ARM REAR 0 4 090 715 01 COVER REAR CO Oo NO gt N lt PWH 3X6 E po RK 3X6 PWH 3X6 8 bei 11 4 090 704 01 COVER CABLE 12 X 4040 764 1 CABINET ASSY 13 13 4 089 923 01 COVER MINI DIN DAK 2 6 4 20 QoooooQ SDM P82 UC 4 2 4 2 PACKING MATERIALS Be ON NO eee 51 4 090 725 01 INDIVIDUAL CARTON 52 4 090 727 11 CUSHION LOWER 53 4 378 262 21 BAG PROTECTION 54 4 090 726 01 CUSHION UPPER 55 1 765 718 11 CORD SET POWER 5 6796 56 1 796 496 11 DISC CD ROM 57 1 824 596 11 CABLE D SUB 58 1 824 598 11 CABLE DVI D 59 4 090 729 11 MANUAL INSTRUCTION 60 4 091 820 01 PAPER SHEET BOTTOM 61 4 091 819 01 PAPER SHEET BACK SDM P82 UC 4 3 SECTION 5 ELECTRICAL PARTS LIST NOTE Th All variable and adjustable resistors have characteristic curve unless otherwise critical for safety noted Replace only with the part number specified Les composants identifi s par la marque A Items marked are not stocked since sont critiques pour la s curit
39. V 1U 9 10 0 10 220 220 220P FSADDR O 13 43 3V F1 Divided circuit diagram 3 3V_F 3 3V_F2 68596 120 100MHz c541 BEAD 1206 525 c526 527 cs28 529 530 oa 22U 16V e 10 oul 220 220 220 4 4 4 3 3V_F2 3 3V_F 3 3V_F3 8597 120 100MHz 42 8540 1206 c532 c533 535 6536 C537 C538 22U 16V 220 220 220 3 3V_F3 One sheet of A board are circuit diagram is divided into eight sheets each having the code A to A G For example the destination on the code A sheet is connected to a b 1 Ref No Circuit diagram division code on the A sheet 88 8888 88 8888 1 1 2421 55 8800 2 51 8 1 24 21 55 FSADDRO a 21 0 9995 pool 241 8 rsparais FSADDR0 5 4 21 jao gt gt gt gt poo 220 FSADDRI T 22 DQ1 3 5 FSDATAIY FSADDRI
40. lag is set In this setting when the input with no input signal is selected the system goes into the AGING MODE The NO SYNC AGING flag is held until it is cleared To clear the NO SYNC AGING flag go into the service mode and then set the AGING MODE to OFF or execute the all mode recall To enter the service mode Press the POWER button with pressing the UP D and DOWN 4 buttons in the power off state and the system is set to the service mode The service mode will be explained later To exit from the service mode turn off the power To copy EDID to the EEPROM and to clear Press the POWER button with pressing the UP and OK buttons in the power off state and the data for the model information are copied to the EEPROM for the internal microcontroller from EDID of INPUT2 HD15 and the model information display is made correct When replacing the A board this operation is required after writing EDID and at the same time is reset to 0 To enter the ISP mode Turn on the MAIN POWER switch with pressing the DOWN J button in the main power off state and the system enters the ISP mode The POWER LED goes off and both input LED s 1 and 2 light on and the picture disappears and any button becomes invalid In the ISP mode the internal software can be updated with an external personal computer using a special fixture To cancel the ISP mode turn off the MAIN POWER switch SDM P82 UC 2 1 2 2 Uses of Service
41. n ohms lt Em nonflammable resistor NF fusible resistor internal component panel designation and adjustment for repair All variable and adjustable resistors have characteristic curve B unless otherwise noted e earth ground h earth chassis When replacing the part in below table be sure to perform the related adjustment All voltages are in V Readings are taken with a 10 M digital multimeter Readings are taken with a color bar signal input Voltage variations may be noted due to normal production tolerances Can not be measured Circled numbers are waveform references ome bus B bus Note The components identified by shading and mark A are critical for safety Replace only with part number specified Note Les composants identifi s par un tram et une marque sont critiques pour la s curit Ne les remplacer que par une pi ce portant le num ro sp cifi Divided circuit diagram One sheet of A board are circuit diagram is divided into eight sheets each having the code A to A h For example the destination ab1 on the code A sheet is connected to ab1 on the A sheet a b 1 L Ref No Circuit diagram division code Terminal name of semiconductors in silk screen printed circuit Device Transistor Printed symbol Terminal name Collector Base I Emitter Transistor Collec
42. of screen 2 Measurement distance 50 cm 3 Measurement angle 90 4 Color analyzer Minolta CS 1000 or equivalent 5 Signal generator Astro Design VG 828D or equivalent Be sure to calibrate the analog RGB output level with 75Q termination Service mode setting Enter the service mode referring to step 1 and 2 of Section 2 2 Aging Set the AGING MODE in the service mode to ON Disconnect the signal input terminal or select the input with no signal input and the system goes into the AGING MODE Execute aging for 30 minutes or more User control setting Feed a signal to the selected input and then execute reset in the menu screen Then move the menu display position to avoid the measurement point Or set the following for respective inputs BACKLIGHT Brightness of backlight 100 CONTRAST 70 BRIGHTNESS 50 Menu display position not center of screen Avoid the measurement point The setting of the menu display position is common to respective inputs ECO OFF The setting of ECO is common to respective inputs Do not change the above setting until the white balance adjustment is completed SDM P82 UC 2 3 Analog RGB white balance adjustment 1 Feed the signal listed below to INPUT2 HD15 and then select INPUT2 HD15 Then execute RGB RESET the service mode menu Signal timing Pattern Input level VESA 1280 1024 60Hz Gray scale 0 73 Vp p 2 Feed the signal listed below
43. on the screen The factory preset mode When the monitor receives an input signal it automatically matches the signal to one of the factory preset modes stored in the monitor s memory to provide a high quality picture at the center of the screen If the input signal matches the factory preset mode the picture is appears on the screen automatically with the appropriate default adjustment If input signals do not match one of the factory preset modes When the monitor receives an input signal the automatic picture quality adjustment function of this monitor is activated and ensures that a clear picture always appears on the screen within the following monitor frequency ranges Horizontal frequency 28 92 kHz Vertical frequency 56 85Hz Consequently the first time the monitor receives input signals that do not match one of the factory preset modes the monitor may take a longer time than normal for displaying the picture on the screen This adjustment data is automatically stored in memory so that next time the monitor will function in the same way as when the monitor receives the signals that match one of the factory preset modes If you adjust the phase pitch and pictures position manually For some input signals the automatic picture quality adjustment function of this monitor may not completely adjust the picture position phase and pitch In this case you can manually set these adjustments page 12 If you manually
44. perature 9300 K and 6500 The adjustment requires to be done for every input INPUTI DVI D INPUTI HD15 or INPUT2 HD15 by switching the input The adjustment data is stored into the register for respective inputs INITIAL EEPROM This sets the data of the EEPROM to the default data This operation is not required usually CLEAR ETI TIME This resets the ETI Elapsed Time Indicator counter to 00000 H EEPROM TEST This tests writing and reading of the EEPROM RGB RESET This adjust the offset and gain of the input AD converter for the analog inputs INPUT1 HD15 and INPUT2 HD15 As these adjustments are common to both inputs perform them for either input It is unnecessary for another input Execute the adjustments under the condition where the signal specified in White Balance Adjustment is input AGING IN MODE This sets and clears the NO SYNC AGING flag AGING Sets the NO SYNC AGING flag AGING MODE OFF Clears the NO SYNC AGING flag When the NO SYNC AGING flag is set and the input with no input signal is selected the system goes into the AGING MODE The NO SYNC AGING flag is held until it is cleared To clear the NO SYNC AGING flag go into the service mode and then set the AGINGN MODE to OFF or execute the all mode recall CONTROL REG This can check the data of the internal registers This operation is not required usually White Balance Adjustment Preparation 1 Measurement point Center
45. t OPD Pa ORV Qos E 639 80817257 HI ra 10120 qo ICT28 ICT40 6 E L4 SH 10k mar cio 6727 3 186490 2001 x 2 19 emen CT26 BI 1 ICT6 1 VN UDZSTE 175 6B m 2 ICT24 lt 2 TO LCD BACK LIGHT ae 4 17 2 1 62k Eu 1 R45 postres cos C04 Cos 5 16 wi o 1 03 15 ICT59 AU Ftu 6 Gis ootu C14 2958 ICTS 10 77 t E 925 2 177 EM V7 7LND imam ICT43 ICT42 ae 610 8 13 5 1 S De wi 2 77 18 PRV O Dt 10 11 t DRV D 7 X Q03 6 00154 V V 777 ICT44 ICT45 1 46 ICT29 4D ICT60 P n 77 m UN 1M 2PIN ICT33 03 re 4 YST A186490 ER por QD 1 cv03 e BASS 6750 0 45 TO LCD BACK LIGHT 004 850 oe 100k 224 gaz L 806 E 2N7002LTA Ou 1M mE 3 HY COPS BAS32 S CH c 5 oer M lj 177 003 ICT52 iM 2 1 BAS32 c p oe bo F 1M 0 185355 FBT Sik 004 Si 4 1 WI BAS32 R20 6 65 026 Rot 188355 ray 2N7002LTA EM 15k 2PIN C24 R29 1 YST A186490 ICT36 T M 77 I z z TO LCD BACK LIGHT F02 2 1 C36 2 e 4 6 BAS32 CNO7 63 2200
46. tor Base ircuit Cathode Anode Cathode Anode NC Cathode 8 Anode Anode Cathode Common Anode Cathode Anode Anode Common Anode Anode cathode Sais Diode Common wa Cathode Cathode Diod Anode Cathode Anode Anode Anode Cathode Transisi FET I Source Drain Gate Transisi FET Source Drain Gate Transis Drain O Source O Gate Transis or 1414141411 4 Collector 1 Emitter O Base Chip semiconductors that are not actually used are included Discrete semiconductot Ver 1 6 SDM P82 UC 3 3 1 Schematic Diagrams of A 9 D Board 12 12 0205 T 44350 5V REG 2 TK 0201 MMBT4401 s D 715 D 754 D R213 7 5 R221 7 5 4 5V_B 0207 A x 100 22 MMBT3904 R205 0 si e 7 74 0202 PD ANN lt MMBT4405 0201 it C210 10K R223 55
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